Atmel-11100K-ATARM-SAM4S-Datasheet_09-Jun-15
Description
The Atmel® | SMART SAM4S series is a member of a family of Flash
microcontrollers based on the high-performance 32-bit ARM ® Cortex®-M4 RISC
processor. It operates at a maximum speed of 120 MHz and features up to
2048 Kbytes of Flash, with optional dual-bank implementation and cache
memory, a nd up to 160 Kbytes of SRAM . The pe riph eral set includ es a f ull-sp eed
USB Device port with embedded transceiver, a high-speed MCI for
SDIO/SD/MMC, an External Bus Interface featuring a Static Me mo r y Co n tro lle r to
connect to SRAM, PSRAM, NOR Flash, LCD Module and NAND Flash, 2
USARTs, 2 UARTs, 2 TWIs, 3 SPIs, an I2S, as well as a PWM timer, two 3-
channel general-purpose 16-bit timers (with stepper motor and quadrature
decoder logic support), an RTC, a 12-bit ADC, a 12-bit DAC and an analog
comparator.
The SAM4S series is ready for capacitive touch, offering native support for the
Atmel QTouch® library for easy implementation of buttons, wheels and sliders.
The Atmel | SMART SAM 4S devices have three softw are-selectable low-power
modes: Sleep, Wait and Backup. In Sleep mode, the processor is stopped while
all other functions can be kept running. In Wait mode, all clocks and functions are
stopped but some peripherals can be configured to wake up the system based on
predefined conditions. In Backup mode, only the low-power RTC and wakeup
logic are running.
The real-time event management allows peripherals to receive, react to and send
events in Active and Sleep modes without processor intervention.
The SAM4S device is a medium-range general-purpose microcontroller with the
best ratio in terms of reduced power consumption, processing power and
peripheral set. This enab les the SAM4S to sustain a wide range of applicat ions
that includes consumer, industrial control, and PC peripherals.
SAM4S devices operate from 1.62V to 3.6V.
The SAM4S series is pin-to-pin compatible with the SAM3N, SAM3S series (48-,
64- and 100-pin versions), SAM4N and SAM7S legacy series (64-pin versions).
SAM4S Series
Atmel | SMART ARM-based Flash MCU
DATASHEET
SAM4S Series [DATASHEET]
Atmel-11100K-ATARM-SAM4S-Datasheet_09-Jun-15
2
Features
Core
ARM Cortex-M4 with 2 Kbytes of cache running at up to 120 MHz
Memory Protection Unit (MPU)
DSP Instruction Set
Thumb®-2 instruction set
Pin-to-pin compatible with SAM3N, SAM3S, SAM4N and SAM7S lega cy product s (64-pin version)
Memories
Up to 2048 Kbytes embedded Flash with optional dual-bank and cache memory, ECC, Security Bit and Lock
Bits
Up to 160 Kbytes embedded SRAM
16 Kbytes ROM with embedded boot loader routines (UART, USB) and IAP routines
8-bit Static Memory Controller (SMC): SRAM, PSRAM, NOR and NAND Flash support
System
Embedded voltage regulator for single supply operation
Power-on-Reset (POR), Brown-out Detector (BOD) and Watchdog for safe operation
Quartz or ceramic resonator oscillators: 3 to 20 MHz main power with failure detection and optional low-power
32.768 kHz for RTC or device clock
RTC with Gregorian and Persian calendar mode, waveform generation in low-power modes
RTC counter calibration circuitry compensates for 32.768 kHz crystal frequency inaccuracy
High-precision 8/12 MHz factory-trimmed internal RC oscillator with 4 MHz default frequency for device startup,
in-application trimming access for frequency adjustment
Slow clock internal RC oscillator as permanent low-power mode device clock
Two PLLs up to 240 MHz for device clock and for USB
Temperature sensor
Low-power tamper detection on two inputs, anti-tampering by immediate clear of general-purpose backup
registers (GPBR)
Up to 22 Peripheral DMA (PDC) channels
Low-power Modes
Sleep, Wait and Backup modes; consumption down to 1 µA in Backup mode
Peripherals
USB 2.0 Device: 12 Mbps, 2668 byte FIFO, up to 8 bidirectional Endpoints, on-chip transceiver
Up to two USARTs with ISO7816, IrDA®, RS-485, SPI, Manchester and Modem Mode
Two 2-wire UARTs
Up to two 2-Wire Interface modules (I2C-compatible), one SPI, one Serial Synchronous Controller (I2S), one
high-speed Multimedia Card Interface (SDIO/SD Card/MMC)
Two 3-channel 16-bit Timer Counters with capture, waveform, compare and PWM mode, Quadrature decoder
logic and 2-bit Gray up/down counter for stepper motor
4-channel 16-bit PWM with complementary output, fault input, 12-bit dead time generator counter for motor
control
32-bit Real-time Timer and RTC with calendar, alarm and 32 kHz trimming features
256-bit General Purpose Backup Registers (GPBR)
Up to 16-channel, 1Msps ADC with differential input mode and programmable gain stage and auto calibration
One 2-channel 12-bit 1Msps DAC
One Analog Comparator with flexible input selection, selectable input hysteresis
32-bit Cyclic Redundancy Check Calculation Unit (CRCCU) for data integrity check of off-/on-chip memories
Register Write Protection
3
SAM4S Series [DATASHEET]
Atmel-11100K-ATARM-SAM4S-Datasheet_09-Jun-15
I/O
Up to 79 I/O lines with external interrupt capability (edge or level sensitivity), debouncing, glitch filtering and on-
die series resistor termination
Three 32-bit Parallel Input/Output Controllers, Peripheral DMA-assisted Parallel Capture mode
Packages
100-lead packages
LQFP – 14 x 14 mm, pitch 0.5 mm
TFBGA – 9 x 9 mm, pitch 0.8 mm
VFBGA – 7 x 7 mm, pitch 0.65 mm
64-lead packages
LQFP – 10 x 10 mm, pitch 0.5 mm
QFN – 9 x 9 mm, pitch 0.5 mm
WLCSP – 4.42 x 4.72 mm, pitch 0.4 mm (SAM4SD32/SAM4SD16)
WLCSP – 4.42 x 3.42 mm, pitch 0.4 mm (SAM4S16/S8)
WLCSP – 3.32 x 3.32 mm, pitch 0.4 mm (SAM4S4/S2)
48-lead packages
LQFP – 7 x 7 mm, pitch 0.5 mm
QFN – 7 x 7 mm, pitch 0.5 mm
SAM4S Series [DATASHEET]
Atmel-11100K-ATARM-SAM4S-Datasheet_09-Jun-15
4
Safety Features Highlight
Flash
Built-in ECC (hamming), single error correction
Security bit and lock bits
5
SAM4S Series [DATASHEET]
Atmel-11100K-ATARM-SAM4S-Datasheet_09-Jun-15
1. Configuration Summary
The SAM4S series devices differ in memory size, package and features. Table 1-1 and Table 1-2 summari ze the
configurat ion s of th e de vice fam ily.
Notes: 1. One channel is reserved for internal temperature sensor.
2. Three TC channels are reserved for internal use.
3. Full modem support on USART1.
Table 1-1. Configuration Summary for SAM4SD32/SD16/SA16/S16 Devices
Feature SAM4SD32C SAM4SD32B SAM4SD16C SAM4SD16B SAM4SA16C SAM4SA16B SAM4S16C SAM4S16B
Flash 2 x 1024 Kbytes 2 x 1024 Kbytes 2 x 512 Kbytes 2 x 512 Kbytes 1024 Kbytes 1024 Kbytes 1024 Kbytes 1024 Kbytes
SRAM 160 Kbytes 160 Kbytes 160 Kbytes 160 Kbytes 160 Kbytes 160 Kbytes 128 Kbytes 128 Kbytes
HCACHE 2 Kbytes 2 Kbytes 2 Kbytes 2 Kbytes 2 Kbytes 2 Kbytes – –
Package LQFP100
TFBGA100
VFBGA100
LQFP64
QFN64
WLCSP64
LQFP100
TFBGA100
VFBGA100
LQFP64
QFN64
WLCSP64
LQFP100
TFBGA100
VFBGA100
LQFP64
QFN64
LQFP100
TFBGA100
VFBGA100
LQFP64
QFN64
WLCSP64
Number of PIOs 79 47 79 47 79 47 79 47
External
Bus
Interface
8-bit data,
4 chip selects,
24-bit address –8-bit data,
4 chip selects,
24-bit address –8-bit data,
4 chip selects,
24-bit address –8-bit data,
4 chip selects,
24-bit address –
12-bit ADC 16 ch.(1) 11 ch.(1) 16 ch.(1) 11 ch.(1) 16 ch.(1) 11 ch.(1) 16 ch.(1) 11 ch.(1)
12-bit DAC 2 ch. 2 ch. 2 ch. 2 ch. 2 ch. 2 ch. 2 ch. 2 ch.
Timer Counter
Channels 66
(2) 66
(2) 66
(2) 66
(2)
PDC Channels 22 22 22 22 22 22 22 22
USART/UART 2/2(3) 2/2(3) 2/2(3) 2/2(3) 2/2(3) 2/2(3) 2/2(3) 2/2(3)
HSMCI 1 port, 4 bits 1 port, 4 bits 1 port, 4 bits 1 port, 4 bits 1 port, 4 bits 1 port, 4 bits 1 port, 4 bits 1 port, 4 bits
Table 1-2. Configuration Summary for SAM4S8/S4/S2 Devices
Feature SAM4S8C SAM4S8B SAM4S4C SAM4S4B SAM4S4A SAM4S2C SAM4S2B SAM4S2A
Flash 512 Kbytes 512 Kbytes 256 Kbytes 256 Kbytes 256 Kbytes 128 Kbytes 128 Kbytes 128 Kbytes
SRAM 128 Kbytes 128 Kbytes 64 Kbytes 64 Kbytes 64 Kbytes 64 Kbytes 64 Kbytes 64 Kbytes
HCACHE – – – – – – – –
Package LQFP100
TFBGA100
VFBGA100
LQFP64
QFN64
WLCSP64
LQFP100
TFBGA100
VFBGA100
LQFP64
QFN64
WLCSP64
LQFP48
QFN48
LQFP100
TFBGA100
VFBGA100
LQFP64
QFN64
WLCSP64
LQFP48
QFN48
Number of PIOs 79 47 79 47 34 79 47 34
External
Bus
Interface
8-bit data,
4 chip selects,
24-bit address –8-bit data,
4 chip selects,
24-bit address ––
8-bit data,
4 chip selects,
24-bit address ––
12-bit ADC 16 ch. (1) 11 ch.(1) 16 ch.(1) 11 ch.(1) 8 ch. 16 ch.(1) 16 ch.(1) 8 ch
12-bit DAC 2 ch. 2 ch. 2 ch. 2 ch. – 2 ch. 2 ch. –
Timer Counter
Channels 66
(2) 66
(2) 6(2) 66
(2) 6(2)
PDC Channels 22 22 22 22 22 22 22 22
USART/UART 2/2(3) 2/2(3) 2/2(3) 2/2(3) 2/1 2/2(3) 2/2(3) 2/1
HSMCI 1 port, 4 bits 1 port, 4 bits 1 port, 4 bits 1 port, 4 bits – 1 port, 4 bits 1 port, 4 bits –
SAM4S Series [DATASHEET]
Atmel-11100K-ATARM-SAM4S-Datasheet_09-Jun-15
6
2. Block Diagram
Figure 2-1. SAM4SD32/SD16/SA16 100-pin Version Block Diagra m
SPI
PDC
ID
AHB/APB
Bridge
PCK[2:0]
XIN
XOUT
XIN32
XOUT32
ERASE
VDDIO
VDDCORE
ADTRG
System Controller
TCK/SWCLK
TDI
TDO
JTAGSEL
VDDIO
VDDOUT
JTAG and Serial Wire
Flash
Unique
Identifier
Voltage
Regulator
Analog Comparator
CRCCU
NPCS[3:0]
MISO
MOSI
SPCK
TST
ADC
VDDPLL
TCLK[2:0]
TIOA[2:0]
TIOB[2:0]
TCLK[5:3]
TIOA[5:3]
TIOB[5:3]
DAC
PDC
PWMH[3:0]
PWML[3:0]
PWMFI0
ADVREF
DAC[1:0]
DATRG
High-speed
MCI
TK
TD
RD
RK
RF
SSC
PDC
USB 2.0
Full-speed
TF
D[7:0]
A[23:0]
A21/NANDALE
A22/NANDCLE
NWAIT
NCS[3:0]
NRD
NWE
NANDOE
NANDWE
In-Circuit Emulator
MPU
Cortex-M4 Processor
fMAX 120 MHz
NVIC 24-bit SysTick
Counter
DSP
Transceiver
MCCK
MCCDA
MCDA[3:0]
Flash
2*1024/2*512/1024 Kbytes
DDP
DDM
DAC
Temp. Sensor
ADVREF
ADC
PDC
User
Signature
WKUP[15:0]
RTCOUT0
RTCOUT1
NRST
AD[14:0]
PIOA/PIOB/PIOC
TMS/SWDIO
PDC
Timer Counter 0
TC[0..2]
Timer Counter 1
TC[3..5]
Temp Sensor
PWM
SRAM
160 Kbytes
ROM
16 Kbytes
Event System
S
Supply
Controller
32K Cryst
Osc
256-bit
GPBR
Real-time
Timer
Real-time
Clock
Watchdog
Timer
PLLA Power
Management
Controller
3–20 MHz
Oscillator
RC Osc
4/8/12 MHz
UART0
URXD0
UTXD0
PDC
UART1
URXD1
UTXD1
PDC
PLLB
TWCK1
TWD1
TWI1
PDC
TWCK0
TWD0
TWI0
PDC
PDC
CMCC
(2 Kbyte Cache)
PDC
External Bus
Interface
NAND Flash
Logic
Static Memory
Controller
RXD0
TXD0
SCK0
RTS0
CTS0
USART0
PDC
USART1
PDC
RXD1
TXD1
SCK1
RTS1
CTS1
RI1
DCD1
DSR1
DTR1
PIO
PDC
PIODC[7:0]
PIODCCLK
PIODCEN[2:1]
2668
bytes
FIFO
Tamper Detection
Reset
Controller
Supply
Monitor
4-layer AHB Bus Matrix
f
MAX
120 MHz
S
S
S
S
M
SM
M
32K typ.
RC Osc
Power-on
Reset
Backup
7
SAM4S Series [DATASHEET]
Atmel-11100K-ATARM-SAM4S-Datasheet_09-Jun-15
Figure 2-2. SAM4SD32/SD16/SA16 64-p in Version Block Diagram
ID
AHB/APB
Bridge
PCK[2:0]
XIN
XOUT
XIN32
XOUT32
ERASE
VDDIO
VDDCORE
ADTRG
TCK/SWCLK
TDI
TDO
JTAGSEL
VDDIO
VDDOUT
JTAG and Serial Wire
Flash
Unique
Identifier
Voltage
Regulator
Analog Comparator
TST
ADC
VDDPLL
DAC
PDC
ADVREF
DAC[1:0]
DATRG
In-Circuit Emulator
MPU
Cortex-M4 Processor
f
MAX
120 MHz
NVIC 24-bit SysTick
Counter
DSP
Flash
2*1024/2*512/1024 Kbytes
DAC
Temp Sensor
ADVREF
ADC
PDC
User
Signature
WKUP[15:0]
RTCOUT0
RTCOUT1
NRST
AD[9:0]
TMS/SWDIO
PDC
Temp Sensor
SRAM
160 Kbytes
ROM
16 Kbytes
Event System
S
UART0
URXD0
UTXD0
PDC
UART1
URXD1
UTXD1
PDC
TWCK1
TWD1 TWI1 PDC
TWCK0
TWD0 TWI0 PDC
CMCC
(2 Kbyte Cache)
RXD0
TXD0
SCK0
RTS0
CTS0
USART0
PDC
USART1
PDC
RXD1
TXD1
SCK1
RTS1
CTS1
RI1
DCD1
DSR1
DTR1
PIO
PDC
PIODC[7:0]
PIODCCLK
PIODCEN[2:1]
SPI
PDC
CRCCU
NPCS[3:0]
MISO
MOSI
SPCK
High-speed
MCI
TK
TD
RD
RK
RF
SSC
PDC
USB 2.0
Full-speed
TF
Transceiver
MCCK
MCCDA
MCDA[3:0]
DDP
DDM
TCLK[2:0]
TIOA[2:0]
TIOB[2:0]
PWMH[3:0]
PWML[3:0]
PWMFI0
Timer Counter 0
TC[0..2]
PWM
PDC
PDC
2668
bytes
FIFO
Timer Counter 1
TC[3..5]
4-layer AHB Bus Matrix
fMAX 120 MHz
S
S
S
S
M
SM
M
System Controller
PIOA/PIOB/PIOC
Supply
Controller
32K Cryst
Osc
256-bit
GPBR
Real-time
Timer
Real-time
Clock
Watchdog
Timer
PLLA Power
Management
Controller
3–20 MHz
Oscillator
RC Osc
4/8/12 MHz
PLLB
Tamper Detection
Reset
Controller
Supply
Monitor
32K typ.
RC Osc
Power-on
Reset
Backup
SAM4S Series [DATASHEET]
Atmel-11100K-ATARM-SAM4S-Datasheet_09-Jun-15
8
Figure 2-3. SAM4S16/S8 100-pin Version Block Diagram
SPI
PDC
AHB/APB
Bridge
PCK[2:0]
XIN
XOUT
XIN32
XOUT32
ERASE
VDDIO
VDDCORE
ADTRG
TCK/SWCLK
TDI
TDO
JTAGSEL
VDDIO
VDDOUT
JTAG and Serial Wire
Flash
Unique
Identifier
Voltage
Regulator
Analog Comparator
CRCCU
NPCS[3:0]
MISO
MOSI
SPCK
TST
ADC
VDDPLL
TCLK[2:0]
TIOA[2:0]
TIOB[2:0]
TCLK[5:3]
TIOA[5:3]
TIOB[5:3]
DAC
PDC
PWMH[3:0]
PWML[3:0]
PWMFI0
ADVREF
DAC[1:0]
DATRG
High-speed
MCI
TK
TD
RD
RK
RF
SSC
PDC
USB 2.0
Full-speed
TF
D[7:0]
A[23:0]
A21/NANDALE
A22/NANDCLE
NWAIT
NCS[3:0]
NRD
NWE
NANDOE
NANDWE
In-Circuit Emulator
MPU
Cortex-M4 Processor
fMAX 120 MHz
NVIC 24-bit SysTick
Counter
DSP
Transceiver
MCCK
MCCDA
MCDA[3:0]
Flash
1024/512 Kbytes
DDP
DDM
DAC
Temp Sensor
ADVREF
ADC
PDC
User
Signature
RTCOUT0
RTCOUT1
WKUP[15:0]
NRST
AD[14:0]
TMS/SWDIO
PDC
Timer Counter 0
TC[0..2]
Timer Counter 1
TC[3..5]
Temp Sensor
PWM
SRAM
128 Kbytes
ROM
16 Kbytes
Event System
I/D
S
UART0
URXD0
UTXD0
PDC
UART1
URXD1
UTXD1
PDC
TWCK1
TWD1 TWI1 PDC
TWCK0
TWD0 TWI0 PDC
PDC
PDC
External Bus
Interface
NAND Flash
Logic
Static Memory
Controller
RXD0
TXD0
SCK0
RTS0
CTS0
USART0
PDC
USART1
PDC
RXD1
TXD1
SCK1
RTS1
CTS1
RI1
DCD1
DSR1
DTR1
PIO
PDC
PIODC[7:0]
PIODCCLK
PIODCEN[2:1]
2668
bytes
FIFO
4-layer AHB Bus Matrix
f
MAX
120 MHz
S
S
S
S
M
SM
M
System Controller
PIOA/PIOB/PIOC
Supply
Controller
32K Cryst
Osc
256-bit
GPBR
Real-time
Timer
Real-time
Clock
Watchdog
Timer
PLLA
Power
Management
Controller
3–20 MHz
Oscillator
RC Osc
4/8/12 MHz
PLLB
Tamper Detection
Reset
Controller
Supply
Monitor
32K typ.
RC Osc
Power-on
Reset
Backup
9
SAM4S Series [DATASHEET]
Atmel-11100K-ATARM-SAM4S-Datasheet_09-Jun-15
Figure 2-4. SAM4S16/S8 64-pin Version Block Diagram
AHB/APB
Bridge
PCK[2:0]
XIN
XOUT
XIN32
XOUT32
ERASE
VDDIO
VDDCORE
ADTRG
TCK/SWCLK
TDI
TDO
JTAGSEL
VDDIO
VDDOUT
JTAG and Serial Wire
Flash
Unique
Identifier
Voltage
Regulator
Analog Comparator
TST
ADC
VDDPLL
DAC
PDC
ADVREF
DAC[1:0]
DATRG
In-Circuit Emulator
MPU
Cortex-M4 Processor
f
MAX
120 MHz
NVIC 24-bit SysTick
Counter
DSP
Flash
1024/512 Kbytes
DAC
Temp Sensor
ADVREF
ADC
PDC
User
Signature
RTCOUT0
RTCOUT1
WKUP[15:0]
SPI
PDC
CRCCU
NPCS[3:0]
MISO
MOSI
SPCK
High-speed
MCI
TK
TD
RD
RK
RF
SSC
PDC
USB 2.0
Full-speed
TF
Transceiver
MCCK
MCCDA
MCDA[3:0]
DDP
DDM
TCLK[2:0]
TIOA[2:0]
TIOB[2:0]
PWMH[3:0]
PWML[3:0]
PWMFI0
Timer Counter 0
TC[0..2]
PWM
PDC
PDC
2668
bytes
FIFO
Timer Counter 1
TC[3..5]
System Controller
PIOA/PIOB
Supply
Controller
32K Cryst
Osc
256-bit
GPBR
Real-time
Timer
Real-time
Clock
Watchdog
Timer
PLLA Power
Management
Controller
3–20 MHz
Oscillator
RC Osc
4/8/12 MHz
PLLB
Tamper Detection
Reset
Controller
Supply
Monitor
32K typ.
RC Osc
Power-on
Reset
Backup
NRST
AD[9:0]
TMS/SWDIO
PDC
Temp Sensor
SRAM
128 Kbytes
ROM
16 Kbytes
Event System
I/D
S
UART0
URXD0
UTXD0
PDC
UART1
URXD1
UTXD1
PDC
TWCK1
TWD1 TWI1 PDC
TWCK0
TWD0 TWI0 PDC
RXD0
TXD0
SCK0
RTS0
CTS0
USART0
PDC
USART1
PDC
RXD1
TXD1
SCK1
RTS1
CTS1
RI1
DCD1
DSR1
DTR1
PIO
PDC
PIODC[7:0]
PIODCCLK
PIODCEN[2:1]
4-layer AHB Bus Matrix
fMAX 120 MHz
S
S
S
S
M
SM
M
SAM4S Series [DATASHEET]
Atmel-11100K-ATARM-SAM4S-Datasheet_09-Jun-15
10
Figure 2-5. SAM4S4/S2 100-pin Version Block Diagram
SPI
PDC
AHB/APB
Bridge
PCK[2:0]
XIN
XOUT
XIN32
XOUT32
ERASE
VDDIO
VDDCORE
ADTRG
TCK/SWCLK
TDI
TDO
JTAGSEL
VDDIO
VDDOUT
JTAG and Serial Wire
Flash
Unique
Identifier
Voltage
Regulator
Analog Comparator
CRCCU
NPCS[3:0]
MISO
MOSI
SPCK
TST
ADC
VDDPLL
TCLK[2:0]
TIOA[2:0]
TIOB[2:0]
TCLK[5:3]
TIOA[5:3]
TIOB[5:3]
DAC
PDC
PWMH[3:0]
PWML[3:0]
PWMFI0
ADVREF
DAC[1:0]
DATRG
High-speed
MCI
TK
TD
RD
RK
RF
SSC
PDC
USB 2.0
Full-speed
TF
D[7:0]
A[23:0]
A21/NANDALE
A22/NANDCLE
NWAIT
NCS[3:0]
NRD
NWE
NANDOE
NANDWE
In-Circuit Emulator
MPU
Cortex-M4 Processor
fMAX 120 MHz
NVIC 24-bit SysTick
Counter
DSP
Transceiver
MCCK
MCCDA
MCDA[3:0]
Flash
256/128 Kbytes
DDP
DDM
DAC
Temp Sensor
ADVREF
ADC
PDC
User
Signature
RTCOUT0
RTCOUT1
WKUP[15:0]
NRST
AD[14:0]
TMS/SWDIO
PDC
Timer Counter 0
TC[0..2]
Timer Counter 1
TC[3..5]
Temp Sensor
PWM
SRAM
64 Kbytes
ROM
16 Kbytes
Event System
I/D
S
UART0
URXD0
UTXD0
PDC
UART1
URXD1
UTXD1
PDC
TWCK1
TWD1
TWI1
PDC
TWCK0
TWD0
TWI0
PDC
PDC
PDC
External Bus
Interface
NAND Flash
Logic
Static Memory
Controller
RXD0
TXD0
SCK0
RTS0
CTS0
USART0
PDC
USART1
PDC
RXD1
TXD1
SCK1
RTS1
CTS1
RI1
DCD1
DSR1
DTR1
PIO
PDC
PIODC[7:0]
PIODCCLK
PIODCEN[2:1]
2668
bytes
FIFO
4-layer AHB Bus Matrix
fMAX 120 MHz
S
S
S
S
M
SM
M
System Controller
PIOA/PIOB/PIOC
Supply
Controller
32K Cryst
Osc
256-bit
GPBR
Real-time
Timer
Real-time
Clock
Watchdog
Timer
PLLA
Power
Management
Controller
3–20 MHz
Oscillator
RC Osc
4/8/12 MHz
PLLB
Tamper Detection
Reset
Controller
Supply
Monitor
32K typ.
RC Osc
Power-on
Reset
Backup
11
SAM4S Series [DATASHEET]
Atmel-11100K-ATARM-SAM4S-Datasheet_09-Jun-15
Figure 2-6. SAM4S4/S2 64-pin Version Block Diagram
SPI
PDC
AHB/APB
Bridge
PCK[2:0]
XIN
XOUT
XIN32
XOUT32
ERASE
VDDIO
VDDCORE
ADTRG
TCK/SWCLK
TDI
TDO
JTAGSEL
VDDIO
VDDOUT
JTAG and Serial Wire
Flash
Unique
Identifier
Voltage
Regulator
Analog Comparator
CRCCU
NPCS[3:0]
MISO
MOSI
SPCK
TST
ADC
VDDPLL
DAC
PDC
ADVREF
DAC[1:0]
DATRG
High-speed
MCI
TK
TD
RD
RK
RF
SSC
PDC
USB 2.0
Full-speed
TF
In-Circuit Emulator
MPU
Cortex-M4 Processor
fMAX 120 MHz
NVIC 24-bit SysTick
Counter
DSP
Transceiver
MCCK
MCCDA
MCDA[3:0]
Flash
256/128 Kbytes
DDP
DDM
DAC
Temp Sensor
ADVREF
ADC
PDC
User
Signature
RTCOUT0
RTCOUT1
WKUP[15:0]
TCLK[2:0]
TIOA[2:0]
TIOB[2:0]
PWMH[3:0]
PWML[3:0]
PWMFI0
NRST
AD[9:0]
TMS/SWDIO
PDC
Timer Counter 0
TC[0..2]
Temp Sensor
PWM
SRAM
64 Kbytes
ROM
16 Kbytes
Event System
I/D
S
UART0
URXD0
UTXD0
PDC
UART1
URXD1
UTXD1
PDC
TWCK1
TWD1 TWI1 PDC
TWCK0
TWD0 TWI0 PDC
PDC
PDC
RXD0
TXD0
SCK0
RTS0
CTS0
USART0
PDC
USART1
PDC
RXD1
TXD1
SCK1
RTS1
CTS1
RI1
DCD1
DSR1
DTR1
PIO
PDC
PIODC[7:0]
PIODCCLK
PIODCEN[2:1]
2668
bytes
FIFO
Timer Counter 1
TC[3..5]
System Controller
PIOA/PIOB
Supply
Controller
32K Cryst
Osc
256-bit
GPBR
Real-time
Timer
Real-time
Clock
Watchdog
Timer
PLLA Power
Management
Controller
3–20 MHz
Oscillator
RC Osc
4/8/12 MHz
PLLB
Tamper Detection
Reset
Controller
Supply
Monitor
32K typ.
RC Osc
Power-on
Reset
Backup
4-layer AHB Bus Matrix
fMAX 120 MHz
S
S
S
S
M
M
M
SAM4S Series [DATASHEET]
Atmel-11100K-ATARM-SAM4S-Datasheet_09-Jun-15
12
Figure 2-7. SAM4S4/S2 48-pin Version Block Diagram
SPI
PDC
AHB/APB
Bridge
PCK[2:0]
XIN
XOUT
XIN32
XOUT32
ERASE
VDDIO
VDDCORE
ADTRG
TCK/SWCLK
TDI
TDO
JTAGSEL
VDDIO
VDDOUT
JTAG and Serial Wire
Flash
Unique
Identifier
Voltage
Regulator
Analog Comparator
NPCS[3:0]
MISO
MOSI
SPCK
TST
ADC
VDDPLL
TCLK[2:0]
TIOA[2:0]
TIOB[2:0]
PWMH[3:0]
PWML[3:0]
PWMFI0
ADVREF
TK
TD
RD
RK
RF
SSC
PDC
USB 2.0
Full-speed
TF
In-Circuit Emulator
MPU
Cortex-M4 Processor
fMAX 120 MHz
NVIC 24-bit SysTick
Counter
DSP
Transceiver
Flash
256/128 Kbytes
DDP
DDM
DAC
Temp Sensor
ADVREF
ADC
PDC
User
Signature
RTCOUT0
RTCOUT1
WKUP[15:0]
NRST
AD[7:0]
TMS/SWDIO
PDC
Timer Counter 0
TC[0..2]
Temp Sensor
PWM
SRAM
64 Kbytes
ROM
16 Kbytes
Event System
I/D
S
Timer Counter 1
TC[3..5]
UART0
URXD0
UTXD0
PDC
UART1
URXD1
UTXD1
PDC
TWCK1
TWD1 TWI1 PDC
TWCK0
TWD0 TWI0 PDC
PDC
RXD0
TXD0
SCK0
RTS0
CTS0
USART0
PDC
2668
bytes
FIFO
System Controller
PIOA/PIOB
Supply
Controller
32K Cryst
Osc
256-bit
GPBR
Real-time
Timer
Real-time
Clock
Watchdog
Timer
PLLA Power
Management
Controller
3–20 MHz
Oscillator
RC Osc
4/8/12 MHz
PLLB
Tamper Detection
Reset
Controller
Supply
Monitor
32K typ.
RC Osc
Power-on
Reset
Backup
4-layer AHB Bus Matrix
fMAX 120 MHz
S
S
S
S
M
M
M
13
SAM4S Series [DATASHEET]
Atmel-11100K-ATARM-SAM4S-Datasheet_09-Jun-15
3. Signal Description
Table 3-1 gives details on signal names classified by peripheral.
Table 3-1. Signal Description List
Signal Name Function Type Active
Level Voltage
Reference Comments
Power Supplies
VDDIO Peripherals I/O Lines and USB
transceiver Power Supply Power – – 1.62V to 3.6V
VDDIN V olt age Regulator Input, ADC, DAC
and Analog Comparator Power
Supply Power – – 1.62V to 3.6V(4)
VDDOUT Voltage Regulator Output Power – – 1.2V output
VDDPLL Oscillator and PLL Power Supply Power – – 1.08V to 1.32V
VDDCORE Power the core, the embedded
memories and the peripherals Power – – 1.08V to 1.32V
GND Ground Ground – – –
Clocks, Oscillators and PLLs
XIN Main Oscillator Input Input –
VDDIO
Reset State:
- PIO Input
- Internal Pull -up disabled
- Schmitt Trigger enabled(1)
XOUT Main Oscillator Output Output –
XIN32 Slow Clock Oscillator Input Input –
XOUT32 Slow Clock Oscillator Output Output –
PCK0–PCK2 Programmable Clock Output Output –
Reset State:
- PIO Input
- Internal Pull -up enabled
- Schmitt Trigger enabled(1)
Real Time Clock - RTC
RTCOUT0 Programmable RTC waveform
output Output –
VDDIO
Reset State:
- PIO Input
- Internal Pull -up enabled
- Schmitt Trigger enabled(1)
RTCOUT1 Programmable RTC waveform
output Output –
Serial Wire/JTAG Debug Port - SWJ-DP
TCK/SWCLK Test Clock/Serial Wire Clock Input –
VDDIO
Reset State:
- SWJ-DP Mode
- Internal pull-up disabled(5)
- Schmitt Trigger enabled(1)
TDI Test Data In Input –
TDO/TRACESWO Test Data Out / Trace Asynchronous
Data Out Output –
TMS/SWDIO Test Mode Select /Serial Wire
Input/Output Input / I/O –
JTAGSEL JTAG Selectio n Input High Permanent Internal
pull-down
SAM4S Series [DATASHEET]
Atmel-11100K-ATARM-SAM4S-Datasheet_09-Jun-15
14
Flash Memory
ERASE Flash and NVM Configuration Bits
Erase Command Input High VDDIO
Reset State:
- Erase Input
- Internal pull-down
enabled
- Schmitt Trigger enabled(1)
Reset/Test
NRST Synchronous Microcontroller Reset I /O Low
VDDIO
Permanent Internal
pull-up
TST Test Select Input – Permanent Internal
pull-down
Wake-up
WKUP[15:0] Wa ke-up Inputs Input – VDDIO –
Universal Asynchronous Receiver Transceiver - UARTx
URXDx UART Receive Data Input – – –
UTXDx UART Transmit Data Output – – –
PIO Controller - PIOA - PIOB - PIOC
PA0–PA31 Parallel IO Controller A I/O –
VDDIO
Reset State:
- PIO or System IOs(2)
- Internal pull-up enabled
- Schmitt Trigger enabled(1)
PB0–PB14 Parallel IO Controller B I/O –
PC0–PC31 Parallel IO Controller C I/O –
PIO Controller - Parallel Capture Mode
PIODC0–PIODC7 Parallel Capture Mode Data Input –
VDDIO –PIODCCLK Parallel Capture Mode Clock Input –
PIODCEN1–2 Parallel Capture Mode Enable Input –
External Bus Interface
D0–D7 Data Bus I/O – – –
A0–A23 Address Bus Output – – –
NWAIT External Wait Signal Input Low – –
Static Memory Controller - SMC
NCS0–NCS3 Chip Select Lines Output Low – –
NRD Read Signal Output Low – –
NWE Write Enable Output Low – –
NAND Flash Logic
NANDOE NAND Flash Output Enable Output Low – –
NANDWE NAND Flash Write Enable Output Low – –
Table 3-1. Signal Description List (Continued)
Signal Name Function Type Active
Level Voltage
Reference Comments
15
SAM4S Series [DATASHEET]
Atmel-11100K-ATARM-SAM4S-Datasheet_09-Jun-15
High Sp eed Multimedia Card Interface - HSMCI
MCCK Multimedia Card Clock Output – – –
MCCDA Multimedia Card Slot A Command I/O – – –
MCDA0–MCDA3 Multimedia Card Slot A Data I/O – – –
Universal Synchron ous Asynchronous Rec eiver Transmitter - USARTx
SCKx USARTx Serial Clock I/O – – –
TXDx USARTx Transmit Data I/O – – –
RXDx USARTx Receive Data Input – – –
RTSx USARTx Request To Send Output – – –
CTSx USARTx Clear To Send Input – – –
DTR1 USART1 Data Terminal Ready Output – – –
DSR1 USART1 Data Set Ready Input – – –
DCD1 USART1 Data Carrier Detect Output – – –
RI1 USART1 Ring Indicator Input – – –
Synchronous Serial Controller - SSC
TD SSC Transmit Data Output – – –
RD SSC Receive Data Input – – –
TK SSC Transmit Clock I/O – – –
RK SSC Receive Clock I/O – – –
TF SSC Transmit Frame Sync I/O – – –
RF SSC Receive Frame Sync I/O – – –
Timer/Counter - TC
TCLKx TC Channel x External Clo ck Input Input – – –
TIOAx TC Channel x I/O Line A I/O – – –
TIOBx TC Channel x I/O Line B I/O – – –
Pulse Width Modulation Controller - PWMC
PWMHx PWM Waveform Output High for
channel x Output – – –
PWMLx PWM Waveform Output Low for
channel x Output – –
Only output in
complementary mode
when dead time insertion is
enabled.
PWMFI0–2 PWM Fault Input Input – – PWMFI1 and PWMFI2 on
SAM4S4/S2 only
Table 3-1. Signal Description List (Continued)
Signal Name Function Type Active
Level Voltage
Reference Comments
SAM4S Series [DATASHEET]
Atmel-11100K-ATARM-SAM4S-Datasheet_09-Jun-15
16
Note: 1. Sch mitt triggers can be disa bled through PIO registers.
2. Some PIO lines are shared with system I/Os.
3. Refer to USB section of the product Electrical Characteristics fo r information on pull-down value in USB mode.
4. See “Typical Powering Schematics” section for restrictions on voltage range of analog cells.
5. TDO pin is set in input mode when the Cortex-M4 processor is not in debug mode. Thus the internal pull-up corresponding
to this PIO line must be enabled to avoid current consump ti on due to floating input
Serial Peripheral Interface - SPI
MISO Master In Slave Out I/O – – –
MOSI Master Out Slave In I/O – – –
SPCK SPI Serial Clock I/O – – –
SPI_NPCS0 SPI Peripheral Chip Select 0 I/O Low – –
SPI_NPCS1–SPI_NPCS3 SPI Peripheral Chip Select Output Low – –
Two-Wire Interface - TWI
TWDx TWIx Two-wire Serial Data I/O – – –
TWCKx T WIx Two-wire Serial Clock I/O – – –
Analog
ADVREF ADC, DAC and Analog Comparator
Reference Analog – – –
12-bit Analog-to-Digital Converter - ADC
AD0–AD14 Analog Inputs Analog,
Digital –– –
ADTRG ADC T rigger Input – VDDIO –
12-bit Digital-to-Analog Converter - DAC
DAC0–DAC1 Analog output Analog,
Digital –– –
DACTRG DAC Trigger Input – VDDIO –
Fast Flash Programming Interface - FFPI
PGMEN0-PGMEN2 Programming Enablin g Input – VDDIO –
PGMM0–PGMM3 Programming Mode Input –
VDDIO
–
PGMD0–PGMD15 Programming Data I/O – –
PGMRDY Programming Ready Output High –
PGMNVALID Data Direction Output Low –
PGMNOE Programming Read Input Low –
PGMCK Programming Clock Input – –
PGMNCMD Programming Command Input Low –
USB Full Speed Device
DDM USB Full Speed Data - Analog,
Digital – VDDIO Reset State:
- USB Mode
- Internal Pull -down(3)
DDP USB Full Speed Data +
Table 3-1. Signal Description List (Continued)
Signal Name Function Type Active
Level Voltage
Reference Comments
17
SAM4S Series [DATASHEET]
Atmel-11100K-ATARM-SAM4S-Datasheet_09-Jun-15
4. Package and Pinout
SAM4S devices are pin-to-p in compa tible with SAM3N, SAM 3S products i n 48-, 6 4- and 1 00-pin ver sions, SAM4N
and SAM7S legacy products in 64-pin versions.
4.1 100-lead Packages and Pinouts
Refer to Table 1-1 and Tabl e 1-2 for the overview of devices available in 100-lead packages.
4.1.1 100-lead LQFP Package Outline
Figure 4-1. Orientation of the 100-lead LQFP Package
4.1.2 100-ball TFBGA Package Out line
The 100-ball TFBGA package has a 0.8 mm ball pitch and respects Green Standards. Its dimensions are 9 x 9 x
1.1 mm. Figure 4-2 shows the orientation of the 100-ball TFBGA package.
Figure 4-2. Orientation of the 100-ball TFBGA Package
125
26
50
5175
76
100
1
3
4
5
6
7
8
9
10
2
ABCDEFGHJK
TOP VIEW
BALL A1
SAM4S Series [DATASHEET]
Atmel-11100K-ATARM-SAM4S-Datasheet_09-Jun-15
18
4.1.3 100-ball VFBGA Package Outline
Figure 4-3. Orientation of the 100-ball VFBGA Package
19
SAM4S Series [DATASHEET]
Atmel-11100K-ATARM-SAM4S-Datasheet_09-Jun-15
4.1.4 100-lead LQFP Pinout
Table 4-1. SAM4SD32/SD16/SA16/S16/S8/S4/S2 100-lead LQFP Pino ut
1 ADVREF 26 GND 51 TDI/PB4 76 TDO/TRACESWO/PB5
2 GND 27 VDDIO 52 PA6/PGMNOE 77 JTAGSEL
3 PB0/AD4 28 PA16/PGMD4 53 PA5/PGMRDY 78 PC18
4 PC29/AD13 29 PC7 54 PC28 79 TMS/SWDIO/PB6
5 PB1/AD5 30 PA15/PGMD3 55 PA4/PGMNCMD 80 PC19
6 PC30/AD14 31 PA14/PGMD2 56 VDDCORE 81 PA31
7 PB2/AD6 32 PC6 57 PA27/PGMD15 82 PC20
8 PC31 33 PA13/PGMD1 58 PC8 83 TCK/SWCLK/PB7
9 PB3/AD7 34 PA24/PGMD12 59 PA28 84 PC21
10 VDDIN 35 PC5 60 NRST 85 VDDCORE
11 VDDOUT 36 VDDCORE 61 TST 86 PC22
12 PA17/PGMD5/AD0 37 PC4 62 PC9 87 ERASE/PB12
13 PC26 38 PA25/PGMD13 63 PA29 88 DDM/PB10
14 PA18/PGMD6/AD1 39 PA26/PGMD14 64 PA30 89 DDP/PB11
15 PA21/PGMD9/AD8 40 PC3 65 PC10 90 PC23
16 VDDCORE 41 PA12/PGMD0 66 PA3 91 VDDIO
17 PC27 42 PA11/PGMM3 67 PA2/PGMEN2 92 PC24
18 PA19/PGMD7/AD2 43 PC2 68 PC11 93 PB13/DAC0
19 PC15/AD11 44 PA10/PGMM2 69 VDDIO 94 PC25
20 PA22/PGMD10/AD9 45 GND 70 GND 95 GND
21 PC13/AD10 46 PA9/PGMM1 71 PC14 96 PB8/XOUT
22 PA23/PGMD11 47 PC1 72 PA1/PGMEN1 97 PB9/PGMCK/XIN
23 PC12/AD12 48 PA8/XOUT32/PGMM0 73 PC16 98 VDDIO
24 PA20/PGMD8/AD3 49 PA7/XIN32/
PGMNVALID 74 PA0/PGMEN0 99 PB14/DAC1
25 PC0 50 VDDIO 75 PC17 100 VDDPLL
SAM4S Series [DATASHEET]
Atmel-11100K-ATARM-SAM4S-Datasheet_09-Jun-15
20
4.1.5 100-ball TFBGA Pinout
Table 4-2. SAM4SD32/SD16/SA16/S16/S8/S4/S2 100-ball TFBGA Pinout
A1 PB1/AD5 C6 TCK/SWCLK/PB7 F1 PA18/PGMD6/AD1 H6 PC4
A2 PC29/AD13 C7 PC16 F2 PC26 H7 PA11/PGMM3
A3 VDDIO C8 PA1/PGMEN1 F3 VDDOUT H8 PC1
A4 PB9/PGMCK/XIN C9 PC17 F4 GND H9 PA6/PGMNOE
A5 PB8/XOUT C10 PA0/PGMEN0 F5 VDDIO H10 TDI/PB4
A6 PB13/DAC0 D1 PB3/AD7 F6 PA27/PGMD15 J1 PC15/AD11
A7 DDP/PB11 D2 PB0/AD4 F7 PC8 J2 PC0
A8 DDM/PB10 D3 PC24 F8 PA28 J3 PA16/PGMD4
A9 TMS/SWDIO/PB6 D4 PC22 F9 TST J4 PC6
A10 JTAGSEL D5 GND F10 PC9 J5 PA24/PGMD12
B1 PC30/AD14 D6 GND G1 PA21/PGMD9/AD8 J6 PA25/PGMD13
B2 ADVREF D7 VDDCORE G2 PC27 J7 PA10/PGMM2
B3 GNDANA D8 PA2/PGMEN2 G3 PA15/PGMD3 J8 GND
B4 PB14/DAC1 D9 PC11 G4 VDDCORE J9 VDDCORE
B5 PC21 D10 PC14 G5 VDDCORE J10 VDDIO
B6 PC20 E1 PA17/PGMD5/AD0 G6 PA26/PGMD14 K1 PA22/PGMD10/AD9
B7 PA31 E2 PC31 G7 PA12/PGMD0 K2 PC13/AD10
B8 PC19 E3 VDDIN G8 PC28 K3 PC12/AD12
B9 PC18 E4 GND G9 PA4/PGMNCMD K4 PA20/PGMD8/AD3
B10 TDO/TRACESWO/PB5 E5 GND G10 PA5/PGMRDY K5 PC5
C1 PB2/AD6 E6 NRST H1 PA19/PGMD7/AD2 K6 PC3
C2 VDDPLL E7 PA29 H2 PA23/PGMD11 K7 PC2
C3 PC25 E8 PA30 H3 PC7 K8 PA9/PGMM1
C4 PC23 E9 PC10 H4 PA14/PGMD2 K9 PA8/XOUT32/PGMM0
C5 ERASE/PB12 E10 PA3 H5 PA13/PGMD1 K10 PA7/XIN32/
PGMNVALID
21
SAM4S Series [DATASHEET]
Atmel-11100K-ATARM-SAM4S-Datasheet_09-Jun-15
4.1.6 100-ball VFBGA Pinout
Table 4-3. SAM4SD32/SD16/SA16/S16/S8/S4/S2 100-ball VFBGA Pinout
A1 ADVREF C6 PC9 F1 VDDOUT H6 PA12/PGMD0
A2 VDDPLL C7 TMS/SWDIO/PB6 F2 PA18/PGMD6/AD1 H7 PA9/PGMM1
A3 PB9/PGMCK/XIN C8 PA1/PGMEN1 F3 PA17/PGMD5/AD0 H8 VDDCORE
A4 PB8/XOUT C9 PA0/PGMEN0 F4 GND H9 PA6/PGMNOE
A5 JTAGSEL C10 PC16 F5 GND H10 PA5/PGMRDY
A6 DDP/PB11 D1 PB1/AD5 F6 PC26 J1 PA20/AD3/PGMD8
A7 DDM/PB10 D2 PC30/AD14 F7 PA4/PGMNCMD J2 PC12/AD12
A8 PC20 D3 PC31 F8 PA28 J3 PA16/PGMD4
A9 PC19 D4 PC22 F9 TST J4 PC6
A10 TDO/TRACESWO/PB5 D5 PC5 F10 PC8 J5 PA24/PGMD12
B1 GNDANA D6 PA29 G1 PC15/AD11 J6 PA25/PGMD13
B2 PC25 D7 PA30 G2 PA19/PGMD7/AD2 J7 PA11/PGMM3
B3 PB14/DAC1 D8 GND G3 PA21/AD8/PGMD9 J8 VDDCORE
B4 PB13/DAC0 D9 PC14 G4 PA15/PGMD3 J9 VDDCORE
B5 PC23 D10 PC11 G5 PC3 J10 TDI/PB4
B6 PC21 E1 VDDIN G6 PA10/PGMM2 K1 PA23/PGMD11
B7 TCK/SWCLK/PB7 E2 PB3/AD7 G7 PC1 K2 PC0
B8 PA31 E3 PB2/AD6 G8 PC28 K3 PC7
B9 PC18 E4 GND G9 NRST K4 PA13/PGMD1
B10 PC17 E5 GND G10 PA27/PGMD15 K5 PA26/PGMD14
C1 PB0/AD4 E6 GND H1 PC13/AD10 K6 PC2
C2 PC29/AD13 E7 VDDIO H2 PA22/AD9/PGMD10 K7 VDDIO
C3 PC24 E8 PC10 H3 PC27 K8 VDDIO
C4 ERASE/PB12 E9 PA2/PGMEN2 H4 PA14/PGMD2 K9 PA8/XOUT32/PGMM0
C5 VDDCORE E10 PA3 H5 PC4 K10 PA7/XIN32/
PGMNVALID
SAM4S Series [DATASHEET]
Atmel-11100K-ATARM-SAM4S-Datasheet_09-Jun-15
22
4.2 64-lead Packages and Pinouts
Refer to Table 1-1 and Table 1-2 for the overview of devices available in 64-lead packages.
4.2.1 64-lead LQFP Package Outline
Figure 4-4. Orientation of the 64-lead LQFP Package
4.2.2 64-lead QFN Package Outline
Figure 4-5. Orientation of the 64-lead QFN Package
4.2.3 64-ball WLCSP Package Outline
Figure 4-6. Orientation of the 64-ball WLCSP Package
33
49
48
32
17
16
1
64
1
16 17 3233
48
4964
T OP VIEW
23
SAM4S Series [DATASHEET]
Atmel-11100K-ATARM-SAM4S-Datasheet_09-Jun-15
4.2.4 64-lead LQFP and QFN Pinout
Note: The bottom pad of the QFN package must be connected to ground.
Table 4-4. 64-pin SAM4SD32/SD16/SA16/S16/S8/S4/S2 Pinout
1 ADVREF 17 GND 33 TDI/PB4 49 TDO/TRACESWO/PB5
2 GND 18 VDDIO 34 PA6/PGMNOE 50 JTAGSEL
3 PB0/AD4 19 PA16/PGMD4 35 PA5/PGMRDY 51 TMS/SWDIO/PB6
4 PB1/AD5 20 PA15/PGMD3 36 PA4/PGMNCMD 52 PA31
5 PB2/AD6 21 PA14/PGMD2 37 PA27/PGMD15 53 TCK/SWCLK/PB7
6 PB3/AD7 22 PA13/PGMD1 38 PA28 54 VDDCORE
7 VDDIN 23 PA24/PGMD12 39 NRST 55 ERASE/PB12
8 VDDOUT 24 VDDCORE 40 TST 56 DDM/PB10
9 PA17/PGMD5/AD0 25 PA25/PGMD13 41 PA29 57 DDP/PB11
10 PA18/PGMD6/AD1 26 PA26/PGMD14 42 PA30 58 VDDIO
11 PA21/PGMD9/AD8 27 PA12/PGMD0 43 PA3 59 PB13/DAC0
12 VDDCORE 28 PA11/PGMM3 44 PA2/PGMEN2 60 GND
13 PA19/PGMD7/AD2 29 PA10/PGMM2 45 VDDIO 61 XOUT/PB8
14 PA22/PGMD10/AD9 30 PA9/PGMM1 46 GND 62 XIN/PGMCK/PB9
15 PA23/PGMD11 31 PA8/XOUT32/PGMM0 47 PA1/PGMEN1 63 PB14/DAC1
16 PA20/PGMD8/AD3 32 PA7/XIN32/PGMNVALID 48 PA0/PGMEN0 64 VDDPLL
SAM4S Series [DATASHEET]
Atmel-11100K-ATARM-SAM4S-Datasheet_09-Jun-15
24
4.2.5 64-ball WLCSP Pinout
Table 4-5. SAM4SD32/S32/SD16/S16/S8 64-ball WLCSP Pinout
A1 PA31 C1 GND E1 PA29 G1 PA5
A2 PB7 C2 PA1 E2 TST G2 PA6
A3 VDDCORE C3 PA0 E3 NRST G3 PA9
A4 PB10 C4 PB12 E4 PA28 G4 PA11
A5 VDDIO C5 ADVREF E5 PA25 G5 VDDCORE
A6 GND C6 PB3 E6 PA23 G6 PA14
A7 PB9 C7 PB1 E7 PA18 G7 PA20
A8 PB14 C8 PB0 E8 VDDIN G8 PA19
B1 PB5 D1 VDDIO F1 PA27 H1 PA7
B2 JTAGSEL D2 PA3 F2 VDDCORE H2 PA8
B3 PB6 D3 PA30 F3 PA4 H3 PA10
B4 PB11 D4 PA2 F4 PB4 H4 PA12
B5 PB13 D5 PA13 F5 PA26 H5 PA24
B6 VDDPLL D6 PA21 F6 PA16 H6 PA15
B7 PB8 D7 PA17 F7 PA22 H7 VDDIO
B8 GND D8 PB2 F8 VDDOUT H8 GND
Table 4-6. SAM4S4/S2 64-ball WLCSP Pinout
A1 PB5 C1 GND E1 PA3 G1 VDDCORE
A2 PA31 C2 PA0 E2 PA30 G2 PA4
A3 VDDCORE C3 PB7 E3 PA29 G3 PA9
A4 VDDIO C4 PB12 E4 PA27 G4 PA11
A5 GND C5 PA 10 E5 PA24 G5 PA25
A6 PB8 C6 PB0 E6 PA18 G6 PA14
A7 PB9 C7 PB2 E7 PA17 G7 VDDIO
A8 ADVREF C8 PB1 E8 VDDIN G8 PA19
B1 PA1 D1 VDDIO F1 TST H1 PB4
B2 JTAGSEL D2 PA2 F2 NRST H2 PA7
B3 PB10 D3 PA28 F3 PA5 H3 PA8
B4 PB11 D4 PB6 F4 PA6 H4 PA12
B5 PB13 D5 PA26 F5 PA13 H5 VDDCORE
B6 VDDPLL D6 PA 23 F6 PA22 H6 PA15
B7 PB14 D7 PA16 F7 PA21 H7 GND
B8 GNDANA D8 PB3 F8 VDDOUT H8 PA20
25
SAM4S Series [DATASHEET]
Atmel-11100K-ATARM-SAM4S-Datasheet_09-Jun-15
4.3 48-lead Packages and Pinouts
Refer to Table 1-1 for the overview of devices available in 48-lead packages.
4.3.1 48-lead LQFP Package Outline
Figure 4-7. Orientation of the 48-lead LQFP Package
4.3.2 48-lead QFN Package Outline
Figure 4-8. Orientation of the 48-lead QFN Package
SAM4S Series [DATASHEET]
Atmel-11100K-ATARM-SAM4S-Datasheet_09-Jun-15
26
4.3.3 48-lead LQFP and QFN Pinout
Note: The bottom pad of the QFN package must be connected to ground.
Table 4-7. SAM4S4/S2 48-pin LQFP and QFN Pinout
1 ADVREF 13 VDDIO 25 TDI/PB4 37 TDO/TRACESWO/PB5
2 GND 14 PA16/PGMD4 26 PA6/PGMNOE 38 JTAGSEL
3 PB0/AD4 15 PA15/PGMD3 27 PA5/PGMRDY 39 TMS/SWDIO/PB6
4 PB1/AD5 16 PA14/PGMD2 28 PA4/PGMNCMD 40 TCK/SWCLK/PB7
5 PB2/AD6 17 PA13/PGMD1 29 NRST 41 VDDCORE
6 PB3/AD7 18 VDDCORE 30 TST 42 ERASE/PB12
7 VDDIN 19 PA12/PGMD0 31 PA3 43 DDM/PB10
8 VDDOUT 20 PA11/PGMM3 32 PA2/PGMEN2 44 DDP/PB11
9 PA17/PGMD5/AD0 21 PA10/PGMM2 33 VDDIO 45 XOUT/PB8
10 PA18/PGMD6/AD1 22 PA9/PGMM1 34 GND 46 XIN/PB9/PGMCK
11 PA19/PGMD7/AD2 23 PA8/XOUT32/PGMM0 35 PA1/PGMEN1 47 VDDIO
12 PA20/AD3 24 PA7/XIN32/PGMNVALID 36 PA0/PGMEN0 48 VDDPLL
27
SAM4S Series [DATASHEET]
Atmel-11100K-ATARM-SAM4S-Datasheet_09-Jun-15
5. Power Considerations
5.1 Power Supplies
The SAM4S has several types of power supply pins:
VDDCORE pins: Power the core, the first flash rail and the embedded memories and peripherals. Voltage
ranges from 1.08 to 1.32 V.
VDDIO pins: Power the peripheral I/O lines (input/output buffers), the second Flash rail, USB transceiver,
backup part, 32 kHz crystal oscillator and oscillator pads. Voltage ranges from 1.62 to 3.6 V.
VDDIN pin: Voltage regulator input, ADC, DAC and analog comparator power supply. Voltage ranges from
1.62 to 3.6 V.
VDDPLL pin: Powers the PLLA, PLLB, the fast RC and the 3 to 20 MHz oscillator. Voltage ranges from
1.08 to 1.32 V.
5.2 Power-up Considerations
5.2.1 VDDIO Versus VDDCORE
VDDIO must always be higher than or equal to VDDCORE.
VDDIO must reach its minimum operating voltage (1.62 V) before VDDCORE has reached VDDCORE(min). The minimum
slope for VDDCORE is define d by (VDDCORE(min) - VT+) / tRST.
If VDDCORE rises at the same time as VDDIO, the VDDIO rising slope must be higher than or equal to 8.8 V/ms.
If VDDCORE is powered by the internal regulator, all power-up considerations are met.
Figure 5-1. VDDCORE and VDDIO Constraints at Startup
Supply (V)
Time (t)
t
RST
VDDIO
VT+
VDDCORE
VDDIO(min)
VDDCORE(min)
Core supply POR output
SLCK
SAM4S Series [DATASHEET]
Atmel-11100K-ATARM-SAM4S-Datasheet_09-Jun-15
28
5.2.2 VDDIO Versus VDDIN
At power-up, VDDIO needs to reach 0.6 V before VDDIN reac he s 1.0 V .
VDDIO voltage needs to be equal to or below (VDDIN voltage + 0.5 V).
5.3 Voltage Regulator
The SAM4S embed s a volt ag e re gu la to r tha t is managed by the Supply Controller.
This internal regulator is designed to supply the internal core of SAM4S. It features two operating modes:
In Normal mode, the voltage regulator consumes less tha n 500 µA st atic cu rrent a nd dra ws 80 mA of output
current. Internal adaptive biasing adjusts the regulator quiescent curre nt depending on the required load
current. In Wait mode quiescent current is only 5 µA.
In Backup mode, the voltage regulator consumes less than 1 µA while its output (VDDOUT) is driven
internally to GND. The default output voltage is 1.20 V and the start-up time to reach Nor m al mod e is less
than 300 µs.
For adequate input and output power supply decoupling/bypassing, re fer to Table 44-4 "1.2V Voltage Regulator
Characteristics" in Section 44. “Electrical Characteristics”.
29
SAM4S Series [DATASHEET]
Atmel-11100K-ATARM-SAM4S-Datasheet_09-Jun-15
5.4 Typical Powering Schematics
The SAM4S supports a 1.62–3.6 V single supply mode. The internal regulator input is con nected to the source and
its output feeds VDDCORE. Figure 5-2 below shows the power schematics.
As VDDIN powers the voltage regulator, the ADC, DAC and the analog comparator, when the user does not want
to use the embedded voltag e regulator, it can be disabled by software via the SUPC (note that this is different from
Backup mode).
Figure 5-2. Single Supply
Note: Restrictions:
For USB, VDDIO needs to be greater than 3.0V.
For ADC, DAC and Analog Comparator, VDDIN needs to be greater than 2.4V.
Figure 5-3. Core Externally Supplied
Note: Restrictions:
For USB, VDDIO needs to be greater than 3.0V.
For ADC, DAC and Analog Comparator, VDDIN needs to be greater than 2.4V.
Main Supply
(1.62–3.6 V) ADC, DAC,
Analog Comp.
USB
Transceivers
VDDIN
Voltage
Regulator
VDDOUT
VDDCORE
VDDIO
VDDPLL
Main Supply
(1.62–3.6 V)
Can be the
same supply
VDDCORE Supply
(1.08–1.32V)
ADC, DAC, Analog
Comparator Supply
(2.4–3.6 V)
ADC, DAC,
Analog Comp.
USB
Transceivers
VDDIN
Voltage
Regulator
VDDOUT
VDDCORE
VDDIO
VDDPLL
SAM4S Series [DATASHEET]
Atmel-11100K-ATARM-SAM4S-Datasheet_09-Jun-15
30
Figure 5-4 provides an example of the power ing scheme when using a backup battery. Since the PIO state is
preserved when in Backup mode , any free PIO line can be used to switch off the external regulator by driving the
PIO line at low level (PIO is input, pull-up enabled after backup reset). External wake- up of the system can be from
a push button or any signal. See Section 5.7 “Wake-up Sources” for further details.
Figure 5-4. Backup Battery
Note: Restrictions:
For USB, VDDIO needs to be greater than 3.0V.
For ADC, DAC and Analog Comparator, VDDIN needs to be greater than 2.4V.
5.5 Active Mode
Active mode is the normal running mode with the core clock running from the fast RC oscillator, the main crystal
oscillator or the PLLA. The Power Management Controller can be used to adapt the frequency and to disable the
peripheral clocks.
5.6 Low-power Modes
The SAM4S has the following low-power modes: Backup mode, Wait mode and Sleep mode.
Note: The Wait For Event instruction (WFE) of the Cortex-M4 core can be used to enter any of the low-power modes, how-
e ver, this ma y add complexity in the design of application state machines. This is due to the fact that the WFE
instruction goes along with an ev ent flag of the Cortex core (cannot be managed by the software application). The
event flag can be set by interrupts, a debug e v ent or an event signal from another processor . Since it is possible f or an
interrupt to occur just before the execution of WFE, WFE take s into account events that happened in the past. As a
result, WFE prevents the device from entering Wait mode if an interrupt event has occurred.
Atmel has made provision to avoid using the WFE instruction. The wor k arounds to ease applicati on design are as fol-
lows:
- F or Backup mode , switch off the voltage regulator and configure the VROFF bit in the Supply Controller Control Reg-
ister (SUPC_CR).
- For Wait mode, configure the WAITMODE bit in the PMC Clock Generator Main Oscillator Register of the Power
Management Controller (PMC)
- For Sleep mode, use the Wait for Interrupt (WFI) instruction.
Complete information is available in Table 5-1 “Low-power Mode Configuration Sum mary".
ADC, DAC,
Analog Comp.
USB
Transceivers
VDDIN
Voltage
Regulator
3.3V
LDO
Backup
Battery +
-
ON/OFF
IN OUT VDDOUT
Main Supply
VDDCORE
VDDIO
VDDPLL
PIOx (Output)
WKUPx
External wakeup signal
Note: The two diodes provide a “switchover circuit” (for illustration purpose)
between the backup battery and the main supply when the system is put in
backup mode.
31
SAM4S Series [DATASHEET]
Atmel-11100K-ATARM-SAM4S-Datasheet_09-Jun-15
5.6.1 Backup Mode
The purpose of Backup mode is to achieve the lowest power consumption possible in a system which is
performing periodic wake-ups to perform tasks but not requiring fast startup time. Total current consumption is 1
µA typical (VDDIO = 1.8V at 25°C).
The Supply Controller, zero-power power-on reset, RTT, RTC, backup registers and 32 kHz oscillator (RC or
crystal oscillator selected by software in the Supply Controller) are running. The regulator and the core supply are
off.
The SAM4S can be woke up from this mode using the pins WKUP0–15, the supply monitor (SM), the RTT or RTC
wake-up event.
Backup mode is entered by writing a 1 to the VROFF bit of the Supply Controller Control Register (SUPC_CR) (A
key is needed to write the VROFF bit; refer to Section 18. “Supply Controller (SUPC)”.) and with the SLEEPDEEP
bit in the Cortex-M4 System Control Register set to 1. (See the power management description in Section 12.
“ARM Cortex-M4 Processor”).
To enter Backup mode using the VROFF bit:
1. Write a 1 to the VROFF bit of SUPC_CR.
To enter Backup mode using the WFE instruction:
1. Write a 1 to the SLEEPDEEP bit of the Cortex-M4 processor.
2. Execute the WFE instruction of the processor.
In both cases, exit from Backup mode happens if one of the following enable wake-up events occurs:
Level transition, configurable debouncing on pins WKUPEN0–15
Supply Monitor alarm
RTC alarm
RTT alarm
5.6.2 Wait Mode
The purpose of Wait mode is to achieve very low power consumption while maint aining the whole device in a
powered state for a startup time of less than 10 µs. Current consumption in Wait mode is typically 32 µA (total
current consumption) if the internal voltage regulator is used.
In this mode, the clocks of the core, peripherals and memories are stopped. However, the core, peripherals and
memories power supplies are still powered. From this mode, a fast start up is available.
This mode is entered by setting the WAITMODE bit to 1 in the PMC Clock Generator Main Oscillator Register
(CKGR_MOR) in conjunction with the Flash Low Powe r Mode field FLPM = 0 or FLPM = 1 in th e PMC Fast Startup
Mode Register (PMC_FSMR) or by the WFE instruction.
The Cortex-M4 is able to handle external or internal events in order to wake-up the core. This is done by
configuring the external lines WKUP0–15 as fast startup wake-up pins (refer to Section 5.8 “Fast Start-up”). RTC
or RTT Alarm and USB wake-up events can be used to wake up the CPU.
To enter Wait mode with WAITMODE bit:
1. Select the 4/8/12 MHz fast RC oscillator as Main Clock.
2. Set the FLPM field in the PMC_FSMR.
3. Set Flash wait state to 0.
4. Set the WAITMODE bit = 1 in C K GR _MO R.
5. Wait for Master Clock Ready MCKRDY = 1 in the PMC Status Register (PMC_SR).
SAM4S Series [DATASHEET]
Atmel-11100K-ATARM-SAM4S-Datasheet_09-Jun-15
32
To enter Wait mode with WFE:
1. Select the 4/8/12 MHz fast RC oscillator as Main Clock.
2. Set the FLPM field in the PMC_FSMR.
3. Set Flash wait state to 0.
4. Set the LPM bit in the PMC_FSMR.
5. Execute the Wait-For-Event (WFE) instruction of the processor.
In both cases, depending on the value of the field FLPM, the Flash enters three different modes:
FLPM = 0 in Standby mode (low consumption)
FLPM = 1 in Deep power-down mode (extra low consumption)
FLPM = 2 in Idle mode. Memory ready for Read access
Table 5-1 summarizes the power consumption, wake-up time and system state in Wait mode.
5.6.3 Sleep Mode
The purpose of Sleep mode is to optimize power consumption of the device versus response time. In this mode,
only the core clock is stoppe d. The peripheral clocks can be e nabled. The current consump tion in this mode is
application dependent.
This mode is entered via Wait for Interrupt (WFI) or WFE instructions with bit LPM = 0 in PMC_FSMR.
The processor can be woken up from an interrupt if the WFI instruction of the Cortex-M4 is used or from an event
if the WFE instruction is used.
5.6.4 Low-power Mode Summary Table
The modes detailed above are the main low-power modes. Each part can be set to on or off separately and wake-
up sources can be configured individually. Table 5-1 provides the configuration summary of the low-power modes.
33
SAM4S Series [DATASHEET]
Atmel-11100K-ATARM-SAM4S-Datasheet_09-Jun-15
Notes: 1. The external loads on PIOs are not taken into account in the calculation.
2. Supply Monitor current consumption is not included.
3. When considering wake-up time, the time required to start the PLL is not taken into account. Once started, the device works with the 4/8/12 MHz fast RC
oscillator. The user has to add the PLL start-up time if it is needed in the system. The wake-up time is defined as the time taken for wake up until the first
instruction is fetched.
4. Total consumption 1 µA typ to 1.8V on VDDIO at 25°C.
5. 20.4 µA on VDDCORE, 32.2 µA fo r total current consumption .
6. Depends on MCK frequency.
7. Depends on MCK frequency. In this mode, the core is supplied but some peripherals can be clocked.
Table 5-1. Lo w-power Mode Configuration Summary
Mode
SUPC, 32 kHz Osc.,
RTC, RTT, GPBR,
POR
(Backup Region) Regulator Core Memory
Peripherals Mode Entry Potential Wake Up
Sources Core at
Wake Up
PIO State
while in Low-
Power Mode PIO State
at Wake Up Consumption
(1) (2) Wake-up
Time(3)
Backup
Mode ON OFF OFF
(Not powered)
VROFF = 1
or
WFE +
SLEEPDEEP = 1
WKUP0-15 pins
SM alarm
RTC alarm
RTT alarm
Reset Previous state
saved
PIOA &
PIOB &
PIOC
Inputs with
pull ups
1 µA typ(4) < 1 ms
Wait Mode
w/Flash in
Standby
Mode
ON ON Powered
(Not clocked)
WA ITMODE = 1
+ FLPM = 0
or
WFE +
SLEEPDEEP = 0
+ LPM = 1
+ FLPM = 0
Any Event from:
Fast startup through
WKUP0-15 pins
RTC alarm
RTT alarm
USB wake-up
Clocked
back Previous state
saved Unchanged 32.2 µA(5) < 10 µs
Wait Mode
w/Flash in
Deep Power
Down Mode
ON ON Powered
(Not clocked)
WA ITMODE = 1
+ FLPM = 1
or
WFE +
SLEEPDEEP = 0
+ LPM = 1
+ FLPM = 1
Any Event from:
Fast startup through
WKUP0-15 pins
RTC alarm
RTT alarm
USB wake-up
Clocked
back Previous state
saved Unchanged 27.6 µA < 100 µs
Sleep Mode ON ON Powered(6)
(Not clocked)
WFE
or
WFI +
SLEEPDEEP = 0
+ LPM = 0
Entry mode =WFI
Interrupt Only;
Entry mode =WFE
Any Enabled Interrupt
and/or Any Event
from:
Fast start-up through
WKUP0-15 pins
RTC alarm
RTT alarm
USB wake-up
Clocked
back Previous state
saved Unchanged (7) (7)
SAM4S Series [DATASHEET]
Atmel-11100K-ATARM-SAM4S-Datasheet_09-Jun-15
34
5.7 Wake-up Sources
The wake-up events allow the device to exit the Backup mode. When a wake-up event is detected, the Supply
Controller performs a sequence which automatically reenables the core power supply and the SRAM power
supply, if they are not already enabled.
5.8 Fast Start-up
The SAM4S allows the processor to restart in a few microseconds while the processor is in Wait mode. A fast
start-up can occur upon detection of a low level on one of the 19 wake-up inputs (WKUP0 to 15 + USB + RTC +
RTT).
The fast restar t circuitry is fully asynchronous an d provides a fast start-up sign al to the Power Management
Controller. As soon as the fast start-up signal is asserted, the PMC automatically restarts the embedded
4/8/12 MHz Fast RC oscillator, switches the master clock on this 4 MHz clock and reenables the processor clock.
35
SAM4S Series [DATASHEET]
Atmel-11100K-ATARM-SAM4S-Datasheet_09-Jun-15
6. Input/Output Lines
The SAM4S ha s several kinds of inpu t/output (I/O) lines such as general purpose I/Os (GPIO) and system I/Os.
GPIOs can have alternate functionality due to multiplexing capabilitie s of the PIO controllers. The same PIO line
can be used wheth er in I/O mode or by the m ultiplexed peripheral. System I/Os include pins such as test pins,
oscillators, erase or analog inputs.
6.1 General Purpose I/O Lines
GPIO Lines are managed by PIO controllers. All I/Os have several input or output modes such as pull-up or pull-
down, input Schmitt triggers, multi-drive (open-drain), glitch filters, debouncing or input change interrupt.
Programming of these modes is performed independently for each I/O line through the PIO controller user
interface. For more details, refer to Section 31. “Parallel Input/Output Controller (PIO)”.
Some GPIOs can have alternate function as analog input. When the GPIO is set in analog mode, all digital
features of the I/O are disabled.
The input/output buffers of the PIO lines are supplied through VDDIO power supply rail.
The SAM4S embeds high-speed pads able to handle up to 70 MHz for HSMCI (MCK/2), 70 MHz for SPI clock
lines and 46 MHz on other lines. See Section 44.12 “AC Characteristics” for more details. Typical pull-up and pull-
down value is 100 kΩ for all I/Os.
Each I/O line also embeds an ODT (On-Die Termination), (see Figure 6-1). It consists of an internal series resistor
termination scheme for impedance matching between the driver output (SAM4S) and the PCB trace impedance
preventing signal reflection. The series resistor helps to reduce IOs switching current (di/dt) thereby reducing in
turn, EMI. It also decreases overshoot and undershoot (ringing) due to inductance of interconnect between
devices or between boards. In conclusion ODT helps diminish signal integrity issues.
Figure 6-1. On-Die Termination
PCB Trace
Z0 ~ 50 Ω
Receiver
SAM4 Driver with
R
ODT
Z
O
~ 10 Ω
Z0 ~ Z
O
+ R
ODT
ODT
36 Ω Typ.
SAM4S Series [DATASHEET]
Atmel-11100K-ATARM-SAM4S-Datasheet_09-Jun-15
36
6.2 System I/O Lines
System I/O lines are pins used by oscillators, test mode, reset and JTAG. Table 6-1 provides the SAM4S system
I/O lines shared with PIO lines.
These pins are software configurable as general-purpose I/O or system pins. At startup, the default function of
these pins is always used.
Notes: 1. If PB12 is used as PIO input in user applications, a low level must be ensured at startup to prevent Flash erase before the
user application sets PB12 into PIO mode,
2. Refer to “Slow Clock Generator” in Section 18. “Supply Controller (SUPC)”.
3. Refer to the 3 to 20 MHZ crystal oscillator information in Section 29. “Power Management Controller (PMC)”.
6.2.1 Serial Wire JTAG Debug Port (SWJ-DP) Pins
The SWJ-DP pins are TCK/SWCLK, TMS/SWDIO, TDO/SWO, TDI and commonly provided on a standard 20-pin
JTAG connector defined by ARM. For more details about voltage reference and reset state, refer to Table 3-1 on
page 13.
At startup, SWJ-DP pins are configured in SWJ-DP mode to allow connection with debugging probe. Please refer
to Section 13. “Debug and Test Features”.
SWJ-DP pins can be used as standard I/Os to provide users more general input/out put pins when the debug port
is not needed in the end application. Mode selection between SWJ-DP mode (System IO mode) and general IO
mode is performed through the AHB Matrix Special Function Registers (MATRIX_ SFR). Configuration of th e pad
for pull-up, triggers, debouncing and glitch filters is possible regardless of the mode.
The JTAG pin and PA7 pin are used to select the JTAG Boundary Scan when asserted JTAGSEL at a high level
and PA7 at low level. It integrates a permanen t pull-down resistor of about 15 kΩ to GND, so that it can be left
unconnected for normal operations.
By default, the JTAG Debug Port is a ctive. If the debugger host wants to switch to the Serial Wire Debug Port, it
must provide a dedicated JTAG sequence on TMS/SWDIO and T CK/SWCLK which disables the JTAG-DP and
enables the SW-DP. When the Serial Wire Debug Port is active, TDO/TRACESWO can be used for trace.
The asynchronous TRACE output (TRACESWO) is multiplexed with TDO. So the asynchronous trace can only be
used with SW-DP, not JTAG-DP. For more information about SW-DP and JTAG-DP switching, please refer to
Section 13. “Debug and Test Features”.
Table 6-1. System I/O Configuration Pin List
SYSTEM_IO
Bit Number Default Function
After Reset Other Function Constraints For
Normal Start Configuration
12 ERASE PB12 Low Level at
startup(1)
In Matrix User Interface Registers
(Refer to the System I/O Configuration Register
in Section 25. “Bus Matrix (MATRIX)”.)
10 DDM PB10 –
11 DDP PB11 –
7TCK/SWCLKPB7 –
6 TMS/SWDIO PB6 –
5 TDO/TRACESWO PB5 –
4TDIPB4–
– PA7 XIN32 – (2)
–PA8 XOUT32–
– PB9 XIN – (3)
– PB8 XOUT –
37
SAM4S Series [DATASHEET]
Atmel-11100K-ATARM-SAM4S-Datasheet_09-Jun-15
6.3 Test Pin
The TST pin is used fo r JTAG Boundary Scan Manufa cturing Test or Fa st Flash pro gramming mode of the SAM4S
series. The TST pin integrates a permanent pull-down resistor of about 15 kΩ to GND, so that it can be left
unconnected for normal operations. To enter fast p rogramming mode, see Section 21. “Fast Flash Programming
Interface (F F P I) ”. For more on the manufacturing and test mode, refer to Section 13. “Debug and Test Features”.
6.4 NRST Pin
The NRST pin is bidirectional. It is handled by the on-chip reset controller and can be driven low to provide a reset
signal to the external components or asserted low externally to reset the microcontroller. It will reset the Core and
the peripherals except the Backup region (RTC, RTT and Supply Controller). There is no constraint on the length
of the reset pulse and the reset controller can guarante e a minimum pulse length. The NRST pin integrate s a
permanent pull-up resistor to VDDIO of about 100 kΩ. By default, the NRST pin is configured as an input.
6.5 ERASE Pin
The ERASE pin is used to reinitialize the Flash content (and some of its NVM bits) to an erased state (all bits read
as logic level 1). The ERASE pin and the ROM code ensure an in-situ reprogrammability of the Flash content
without the use of a debug tool. When the security bit is activated, the ERASE pin provides the capability to repro-
gram the Flash content. It integrates a pull-down resistor of about 100 kΩ to GND, so that it can be left
unconnected for normal operations.
This pin is debounced by SCLK to improve the glitch tolerance. To avoid unexpected erase at power-up, a
minimum ERASE pin assertion time is required. This time is defined in Table 44-74 “AC Flash Characteristics”.
The ERASE pin is a system I/O pin and can be used as a standard I/O. At startup, the ERASE pin is not configured
as a PIO pin. If the ERASE pin is used as a standard I/O, startup level of this pin must be low to prevent unwanted
erasing. Refer to Section 11.2 “Peripheral Sign al Multiplexing on I/ O Lines” on page 51 . Also, if the ERASE pin is
used as a standard I/O output, asserting the pin to low does not erase the Flash.
6.6 Anti-tamper Pins/Low-power Tamper Detection
WKUP0 and WKUP1 generic wake-up pins can be used as anti-tamper pins. Anti-tamper pins detect intrusion, for
example, into a housing box. Upon detection through a tamper switch, automatic, asynchronous and immediate
clear of registers in the backup area will be performed. Anti-tamper pins can be used in all power modes (Back-
up/Wait/Sleep/Active). Anti-tampering events can be programmed so that half of the General Purpose Backup
Registers (GPBR) are erased automatically. See "Supply Controller" section for further description.
RTCOUT0 and RTCOUT1 pins can be used to generate waveforms from the RTC in order to take advantage of
the RTC inherent prescaler s while the RTC is the only po wered circuitry (low-power mode, Backup mode) or in any
active mode. Entering backup or low-power modes does not affect the waveform generation outputs. Anti-
tampering pin detection can be synchronized with this signal.
SAM4S Series [DATASHEET]
Atmel-11100K-ATARM-SAM4S-Datasheet_09-Jun-15
38
7. Product Mapping
Figure 7-1. SAM4S Product Mapping
Address memory space
Code
1 Mbyte
bit band
region
1 Mbyte
bit band
1 Mbyte
bit band
regiion
0x00000000
SRAM
0x20000000
0x20100000
0x20400000
0x22000000
0x24000000
offset
ID
peripheral
block
Code
Boot Memory
0x00000000
0x00400000
0x00800000
Reserved
0x00C00000
0x1FFFFFFF
Peripherals
HSMCI
18
0x40000000
SSC
22
0x40004000
SPI
21
0x40008000
0x4000C000
TC0
TC0
0x40010000
23
TC0
TC1
+0x40
24
TC0
TC2
+0x80
25
TC1
TC3
0x40014000
26
TC1
TC4
+0x40
27
TC1
TC5
+0x80
28
TWI0
19
0x40018000
TWI1
20
0x4001C000
PWM
31
0x40020000
USART0
USART1
14
0x40024000
15
0x40028000
0x4002C000
Reserved
Reserved
0x40030000
UDP
33
0x40034000
ADC
29
0x40038000
DACC
30
0x4003C000
ACC
34
0x40040000
CRCCU
35
0x40044000
0x40048000
System Controller
0x400E0000
0x400E2600
0x40100000
0x42000000
0x43FFFFFF
0x60000000
External RAM
SMC Chip Select 0
0x60000000
SMC Chip Select 1
Undefined
32 Mbytes
bit band alias
0x61000000
SMC Chip Select 2
0x62000000
SMC Chip Select 3
0x63000000
0x64000000
0x9FFFFFFF
System Controller
SMC
10
0x400E0000
MATRIX
0x400E0200
PMC
5
0x400E0400
UART0
UART1
8
0x400E0600
CHIPID
0x400E0740
9
0x400E0800
EEFC0
6
0x400E0A00
0x400E0C00
PIOA
11
0x400E0E00
PIOB
12
0x400E1000
PIOC
13
0x400E1200
RSTC
0x400E1400
1
SUPC
+0x10
RTT
+0x30
3
WDT
+0x50
4
RTC
+0x60
2
GPBR
+0x90
0x400E1600
0x4007FFFF
Internal Flash
Internal ROM
Reserved
Peripherals
External SRAM
0x60000000
0xA0000000
System
0xE0000000
0xFFFFFFFF
Reserved
Reserved
EEFC1
Reserved
Reserved
Reserved
Reserved
32 Mbytes
bit band alias
Reserved
Undefined
0x40000000
39
SAM4S Series [DATASHEET]
Atmel-11100K-ATARM-SAM4S-Datasheet_09-Jun-15
8. Memories
8.1 Embedded Memories
8.1.1 Internal SRAM
The following table shows the amount of high-speed SRAM embedded in the SAM4Sx devices.
The SRAM is accessible over system Cortex-M4 bus at address 0x2000 0000.
The SRAM is in the bit band region. The bit band alias region is from 0x2200 0000 to 0x23FF FFFF.
8.1.2 Internal ROM
The SAM4S embeds an internal ROM, which contains the SAM boot assistant (SAM-BA®), In-Application
Programming (IAP) routines and Fast Flash Programming Interface (FFPI).
At any time, the ROM is mapped at address 0x0080 0000.
8.1.3 Embedded Flash
8.1.3.1 Flash Overview
The memory is organized in sectors. Each sector has a size of 64 Kbytes. The first sector of 64 Kbytes is divided
into three smaller sectors.
The three smalle r sectors are org anized to co nsist of two sector s of 8 Kbytes and o ne sector of 48 Kbytes. Refer to
Figure 8-1, "Global Flash Organization".
Table 8-1. Embedded High-speed SRAM per Device
Device Flash Total Embedded High-speed SRAM
SAM4SD32 2 x 1024 Kbytes 160 Kbytes
SAM4SD16 2 x 512 Kbytes 160 Kbytes
SAM4SA16 1024 Kbytes 160 Kbytes
SAM4S16 1024 Kbytes 128 Kbytes
SAM4S8 512 Kbytes 128 Kbytes
SAM4S4 256 Kbytes 64 Kbytes
SAM4S2 128 Kbytes 64 Kbytes
SAM4S Series [DATASHEET]
Atmel-11100K-ATARM-SAM4S-Datasheet_09-Jun-15
40
Figure 8-1. Global Flas h Orga ni za tion
Each sector is organized in pages of 512 bytes.
For sector 0:
The smaller sector 0 has 16 pages of 512 bytes
The smaller sector 1 has 16 pages of 512 bytes
The larger sector ha s 96 pages of 512 bytes
From Sector 1 to n:
The rest of the arra y is compos ed of 64-Kb yte sect ors of 128 pages, each page of 512 bytes. Refer to Figure 8-2,
"Flash Sector Organization".
Small Sector 0
8 Kbytes
Small Sector 1
8 Kbytes
Larger Sector
48 Kbytes
Sector 164 Kbytes
64 Kbytes Sector n
Sector 0
Sector size Sector name
41
SAM4S Series [DATASHEET]
Atmel-11100K-ATARM-SAM4S-Datasheet_09-Jun-15
Figure 8-2. Flash Sector Organization
Flash size varies by product:
SAM4S2: the Flash size is 128 Kbytes in a single plane
SAM4S4: the Flash size is 256 Kbytes in a single plane
SAM4S8/S16: the Flash size is 512 Kbytes in a single plane
Internal Flash address is 0x0040_0000
SAM4SD16/SA16: the Flash size is 2 x 512 Kbytes
Internal Flash0 address is 0x0040_0000
Internal Flash1 address is 0x0048_0000
SAM4SD32: the Flash size is 2 x 1024 Kbytes
Internal Flash0 address is 0x0040_0000
Internal Flash1 address is 0x0050_0000
Refer to Figure 8-3, "Flas h Size" for the organization of the Flash depending on its size.
SAM4S Series [DATASHEET]
Atmel-11100K-ATARM-SAM4S-Datasheet_09-Jun-15
42
Figure 8-3. Flash Size
The following era se co mm a nd s ca n be use d de pe ndin g on the sect or size:
8 Kbyte small sector
Erase and write page (EWP)
Erase and write page and lock (EWPL)
Erase sector (ES) with FARG set to a page number in the sector to erase
Erase pages (EPA) with FARG [1:0] = 0 to erase four pages or FARG [1:0] = 1 to erase eight pages.
FARG [1:0] = 2 and FARG [1:0] = 3 must not be used.
48 Kbyte and 64 Kbyte sectors
One block of 8 pages inside any sector, with the command Erase pages (EPA) with FARG[1:0] = 1
One block of 16 pages inside any sector, with the command Erase pages (EPA) and FARG[1:0] = 2
One block of 32 pages inside any sector, with the command Erase pages (EPA) and FARG[1:0] = 3
One sector with the command Erase sector (ES) and FARG set to a page number in the sector to
erase
Entire memory plane
The entire Flash, with the command Erase all (EA)
The Write commands of the Flash cannot be used under 330 kHz.
8.1.3.2 Enhanced Embedded Flash Controller
The Enhanced Em bedded Flash Co ntroller m anage s accesses performed by the masters of th e system. It enables
reading the Flash and writing the write buffer. It also contains a User Interface, mapped on the APB.
The Enhanced Embedded Flash Controller ensures the interface of the Fl ash block.
It manages the programming, erasing, locking and unlocking sequences of the Flash using a full set of commands.
One of the commands returns the embedded Flash descriptor definition that informs the system about the Flash
organization, thus making the software generic.
8.1.3.3 Flash Speed
The user must set the number of wait states depending on the frequency used.
For more details, refer to Section 44.12 “AC Characteristics”.
2 * 8 Kbytes
1 * 48 Kbytes
15 * 64 Kbytes
2 * 8 Kbytes
1 * 48 Kbytes
7 * 64 Kbytes
2 * 8 Kbytes
1 * 48 Kbytes
3 * 64 Kbytes
Flash 1 Mbytes Flash 512 Kbytes Flash 256 Kbytes
43
SAM4S Series [DATASHEET]
Atmel-11100K-ATARM-SAM4S-Datasheet_09-Jun-15
8.1.3.4 Error Code Correction (ECC)
The Flash em beds an ECC mo dule wit h 8 parity bits for each 64 data bits. The EC C is able to correct one un ique
error. The errors a re detected while a read access is pe rformed into memory array. The ECC (Hamming Algorithm)
is a mechanism that encodes data in a manner that makes possible the identification and correction of certain
errors in data. The ECC is capable of single bit error correction.
8.1.3.5 Lock Regions
Several lock bits are used to protect write and erase operat ions on lock regions. A lock region is compos ed of
several consecutive pages, and each lock region has its associated lock bit.
If a locked region erase or progr am command occur s, the command is aborted and the EEFC triggers an interrupt.
The lock bits ar e software pro grammable through the EEFC User Interface. The command “Set Lock Bit” enables
the protection. The command “Clear Lock Bit” unlocks the lock region.
Asserting the ERASE pin clears the lock bits, thus unlocking the entire Flash.
8.1.3.6 Security Bit
The SAM4SD32/SD16/S16/SA16/S8/S4/S2 feature one security bit based on a specific General Purpose NVM bit
(GPNVM bit 0). When the security bit is enabled, any access to the Flash, SRAM, core registers and internal
peripherals through the ICE interface or through the Fast Flash Programming Interface, is forbidden. This ensures
the confidentiality of the code programmed in the Flash.
This security bit can only be enable d through the comm and “Set General Purpose NVM Bit 0” of the EEFC User
Interface. Disabling the security bit can only be achieved by asserting the ERASE pin at 1, and after a full Flash
erase is performed. When the security bit is deactivated, all accesses to the Flash, SRAM, Core registers, Internal
Peripherals are permitted.
The ERASE pin integrates a permanent pull-down. Cons equently, it can be left unconnected during normal
operation. However, it is recommended, in harsh environment, to connect it directly to GND if the erase operation
is not used in the application.
To avoid unexpected erase at power-up, a minimum ERASE pin assertion time is required. This time is defined in
Table 44-74 “AC Flash Characteristics”.
The erase operatio n is n ot perfor me d when the system is in Wait mod e with the Flash in deep- powe r-down mod e.
To make sure that the erase operation is performed after power-up, the system must not reconfigure the ERASE
pin as GPIO or enter Wait mode with Flash in Deep-power-down mode before the ERASE pin assertion time has
elapsed.
The following sequence ensures the erase operation in all cases:
1. Assert the ERASE pin (High)
2. Assert the NRST pin (Low)
3. Power cycle the device
Table 8-2. Lock Bit Number
Product Number of Lock Bits Lock Region Size
SAM4SD32 256 (128 + 128) 8 Kbytes
SAM4SD16 128 (64 + 64) 8 Kbytes
SAM4S16/SA16 128 8 Kbytes
SAM4S8 64 8 Kbytes
SAM4S4 32 8 Kbytes
SAM4S2 16 8 Kbytes
SAM4S Series [DATASHEET]
Atmel-11100K-ATARM-SAM4S-Datasheet_09-Jun-15
44
4. Maintain the ERASE pin high for at least the minimum assertion time.
8.1.3.7 Calibration Bits
NVM bits ar e used to calib rate the brow nout detect or and the voltage regulator. These bits are factory configured
and cannot be changed by the user. The ERASE pin has no effect on the calibration bits.
8.1.3.8 Unique Identifier
Each device integrates its own 128-bit unique identifier. These bits are factory-configured and cannot be changed
by the user. The ERASE pin has no effect on the unique identifier.
8.1.3.9 User Signature
Each device contains a user signature of 512 bytes. It can be used by the user to store user information such as
trimming, keys, etc., that the customer does not want to be erased by asserting the E RASE pin or by soft ware
ERASE command. Read, write and erase of this area is allowed.
8.1.3.10 Fast Flash Programming Interface
The Fast Flash Program ming Interface allows programming the device through a multiple xed fully-handshaked
parallel port. It allows gang programming with market-standard industrial progr ammers.
The FFPI suppo rts read, page prog r am, pa ge era se , fu ll er as e, lock, unlo ck an d pr ot ec t c omm an d s.
8.1.3.11 SAM-BA Boot
The SAM-BA Boot is a default Boot Program which provides an easy way to program in-situ the on-chip Flash
memory.
The SAM-BA Boot Assistant supports serial communication via the UART and USB.
The SAM-BA Boot provides an interface with SAM-BA Graphic User Interface (GUI).
The SAM-BA Boot is in ROM and is mapped in Flash at address 0x0 when GPNVM bit 1 is set to 0.
8.1.3.12 GPNVM Bits
The SAM4S16/S8/S4/S2 feature two GPNVM bits.
The SAM4SA16/SD32/SD16 feature three GPNVM bits, coming from Flash 0, that can be cleared or set,
respectively, through the "Clear GPNVM Bit" and "Set GPNVM Bit" commands of the EEFC0 User Interface.
There is no GPNVM bit on Flash 1.
The GPNVM0 is the security bit.
The GPNVM1 is used to select the boot mode (boot always at 0x00) on ROM or Flash.
The SAM4SD32/16 embeds an additional GPNVM bit, GPNVM2. GPNVM2 is used only to swap the Flash 0 and
Flash 1. If GPNVM2 is ENABLE, the Flash 1 is mapped at address 0x0040_0000 (Flash 1 and Flash 0 are
45
SAM4S Series [DATASHEET]
Atmel-11100K-ATARM-SAM4S-Datasheet_09-Jun-15
continuous). If GPNVM2 is DISABLE, the Flash 0 is mapped at address 0x0040_0000 (Flash 0 and Flash 1 are
continuous).
8.1.4 Boot Strategies
The system always boots at address 0x0. To ensure maximum boot possibilities, the memory layout can be
changed using GPNVM bits.
A general-purpose NVM (GPNVM) bit is used to boot either on the ROM (default) or from the Flash.
The GPNVM bit can be cleared or set respectively through the comm ands “Clear GPNVM Bit” and “Set GPNVM
Bit” of the EEFC User Interface.
Setting GPNVM1 selects the boot from th e Flash. Clearing it selects the boot from the ROM. Asserting ERASE
clears the GPNVM1 and thus selects the boot from the ROM by default.
Setting the GPNVM2 selects Flash 1, clearing it selects the boot from Flash 0. Asserting ERASE clears GPNVM2
and thus selects the boot from Flash 0 by default. GPNVM2 is available only on SAM4SD32/SD16/SA16.
8.2 External Memories
The SAM4S features one External Bus Interface to provide an interface to a wide range of external memories and
to any parallel peripheral.
Table 8-3. General-purpose Non-volatile Memory Bits
Device Name GPNVM0 GPNVM1 GPNVM2
SAM4SD32
Security Bit Boot Mode Selection
Flash Selection
(Flash 0 or Flash 1)
SAM4SD16
SAM4SA16
SAM4S16
Not available
SAM4S8
SAM4S4
SAM4S2
SAM4S Series [DATASHEET]
Atmel-11100K-ATARM-SAM4S-Datasheet_09-Jun-15
46
9. Real T ime Event Management
The events generated by peripherals are designed to be directly routed to peripherals managing/using these
events without processor intervention. Peripherals receiving events contain logic by which to select the one
required.
9.1 Embedded Characteristics
Timers, PWM, IO peripherals generate event triggers which are directly routed to event managers such as
ADC or DACC, for example, to start measurement/conversion without processor intervention.
UART, USART, SPI, TWI, SSC, PWM, HSMCI, ADC, DACC, PIO also generate event triggers directly
connected to Peripheral DMA Controller (PDC) for data transfer without processor intervention.
Parallel capture logic is directly embedded in PIO and generates trigger event to PDC to capture data
without processor intervention.
PWM security even ts (faults) are in comb inatio n al form and directly routed from event generators (ADC,
ACC, PMC, TIMER) to PWM module.
PMC security event (clock failure detection) can be programmed to switch the MCK on reliable main RC
internal clock withou t pr oc essor interven tio n.
47
SAM4S Series [DATASHEET]
Atmel-11100K-ATARM-SAM4S-Datasheet_09-Jun-15
9.2 Real Time Event Mapping List
Notes: 1. Refer to “Low-power Tamper Detection and Anti-Tampering” in Section 18. “Supply Controller (SUPC)” and “General
Purpose Backup Register x” in “General Purpose Backup Registers (GPBR)” .
2. Refer to “Main Clock Failure Detector” in Section 29. “Power Management Controller (PMC)”.
3. Refer to “Fault Inputs” and “Fault Protection” in “Pulse Width Modulation Controller (PWM)” .
Table 9-1. Real-time Event Mapping List
Function Application Description Event Source Event Destination
Security General-purpose Immediate GPBR clear (asynchronous) on
Tamper detection through WKUP0/1 IO pins (1)
Parallel Input/Output
Controller (PIO):
WKUP0/1
General Purpose
Backup Registers
(GPBR)
Safety
General-purpose Automatic Switch to reliabl e main RC oscillator
in case of Main Crystal Clock Failure (2) Power Management
Controller (PMC) PMC
General-
purpose, motor
control
Puts the PWM Outputs in Safe Mode (Main
Crystal Clock Failure Detection) (2)(3) PMC
Pulse Width
Modulation (PWM)
Motor control
Puts the PWM Outputs in Safe Mode
(Overcurrent sensor, ...) (3)(4) Analog Comparator
Controller (ACC)
Puts the PWM Outputs in Safe Mode
(Overspeed, Overcurrent detection ...) (3)(5) Analog-Front-End-
Controller (ADC)
Puts the PWM Outputs in Safe Mode
(Overspeed detection through TIMER
Quadrature Decoder) (3)(6) Timer Counter (TC)
General-
purpose, motor
control
Puts the PWM Outputs in Safe Mode (General
Purpose Fault Inputs) (3) PIO
Image
capture Low-cost image
sensor PC is embedded in PIO (Capture Image from
Sensor directly to System Memory) (7) PIO PDC
Measurement
trigger
General-purpose Trigger source selection in ADC (8)
PIO (ADTRG)
ADC
TC Output 0
TC Output 1
TC Output 2
Motor control ADC-PWM synchronization (9)(10)
Trigg er source selection in ADC (8)
PWM Event Line 0
PWM Event Line 1
Delay
measurement Motor control Propagation delay of external components (IOs,
power transistor bridge driver, etc.) (11)(12)
PWM Output
Compare Line 0 TC Input (A/B) 0
PWM Output
Compare Line 1 TC Input (A/B) 1
PWM Output
Compare Line 2 TC Input (A/B) 2
Conversion
trigger General-purpose Trigger source selection in DACC (13)
PIO DATRG
Digital-Analog
Converter
Controller (DACC)
TC Output 0
TC Output 1
TC Output 2
PWM Event Line 0 (10)
PWM Event Line 1 (10)
SAM4S Series [DATASHEET]
Atmel-11100K-ATARM-SAM4S-Datasheet_09-Jun-15
48
4. Refer to “Fault Mode” in “Anal og Comparator Controller (ACC)” .
5. Refer to “Fault Output” in Section 42. “Analog-to-Digital Converter (ADC)” .
6. Refer to “Fault Mode” in Section 37. “Timer Counter (TC)”.
7. Refer to “Parallel Capture Mode” in “Parallel Input/Output Controller (PIO)” .
8. Refer to “Conversion Triggers” and the ADC Mode Register (ADC_MR) in Section 42., “Analog-to-Digital Converter (ADC)”.
9. Refer to PWM Comparison Value Register (PWM_CMPV) in Section 39. “Pulse Width Modulation Controller (PWM)”.
10.Refer to “PWM Comparison Units” and “PWM Event Lines” in Section 39. “Pulse Width Modulation Controller (PWM)”.
11. Refer to Section 39.6.2.2 “Compa rator” in Section 39. “Pulse Width Modulation Controller (PW M )”.
12.Refer to Section 37. “Timer Counter (TC)”.
13.Refer to DACC Trigger Register (DACC_TRIGR) in Section 43. “Digital-to-Analog Converter Controller (DACC)”.
49
SAM4S Series [DATASHEET]
Atmel-11100K-ATARM-SAM4S-Datasheet_09-Jun-15
10. System Controller
The System Controller is a set of peripherals which allows handling of key elements of the system, such as power,
resets, clocks, time, interrupts, watchd og , et c.
10.1 System Controller and Peripheral Mapping
Refer to Figure 7-1, "SAM4S Product Mapping".
All the peripherals are in the bit band region and are mapped in the bit band alias region.
10.2 Power-on-Reset, Brownout and Supply Monitor
The SAM4S embeds three features to monitor, warn and/or reset the chip:
Power-on-Reset on VDDIO
Brownout Detector on VDDCORE
Supply Monitor on VDDIO
10.2.1 Power-on-Reset
The Power-on-Reset monitors VDDIO. It is always activated and monitors voltage at start up but also during power
down. If VDDIO goes below the threshold voltage, the entire chip is reset. For more information, refer to Section
44. “Electrical Characteristics”.
10.2.2 Brownout Detector on VDDCORE
The Brownout Detector monitors VDDCORE. It is active by default. It can be deactivated by software through the
Supply Controller Mode Register (SUPC_MR). It is especially recommended to disable it during low-power modes
such as Wait or Sleep modes.
If VDDCORE goes below the threshold voltage, the reset of the core is asserted. For m ore information, refer to
Section 18. “Supply Controller (SUPC)” and Section 44. “Electrical Characteristics”.
10.2.3 Supply Monitor on VDDIO
The Supply Monitor monitors VDDIO. It is not active by default. It can be activated by software and is fully
programmable with 16 steps for the threshold (between 1.6V to 3.4V). It is controlled by the Supply Controller
(SUPC). A sample mode is possible. It allows to divide the supply monitor power consumption by a factor of up to
2048. For more information, refer to Section 18. “Supply Controller (SUPC)” and Section 44. “Electrical
Characteristics”.
SAM4S Series [DATASHEET]
Atmel-11100K-ATARM-SAM4S-Datasheet_09-Jun-15
50
11. Peripherals
11.1 Peripheral Identifiers
Table 11-1 defines the Peripheral Identifiers of the SAM4S. A peripheral identifier is required for the control of the
peripheral interrupt with the Nested Vector ed Interrupt Co ntroller and control of the peripheral clock with the Power
Managemen t Co nt ro ller .
Table 11-1. Peripheral Identifiers
Instance ID Instance Name NVIC Interru pt PMC Clock Control Instance Description
0 SUPC X Supply Controller
1 RSTC X Reset Controller
2 RTC X Real-Time Clock
3 RTT X Real-Time Timer
4 WDT X Watchdog Timer
5 PMC X Power Management Controller
6 EEFC0 X Enhanced Embedded Flash Control ler 0
7 EEFC1 – Enhanced Embedded Flash Controller 1
8UART0 X X
Universal Asynchronous Receiver
Transmitter 0
9UART1 X X
Universal Asynchronous Receiver
Transmitter 1
10 SMC – X Static Memory Controller
11 PIOA X X Parallel I/O Controller A
12 PIOB X X Parallel I/O Controller B
13 PIOC X X Parallel I/O Controller C
14 USART0 X X Universa l Synchronous Asynchronous
Receiver Transmitter 0
15 USART1 X X Universa l Synchronous Asynchronous
Receiver Transmitter 1
16 – – – Reserved
17 – – – Reserved
18 HSMCI X X Multimedia Card Interface
19 TWI0 X X Two-Wire Interface 0
20 TWI1 X X Two-Wire Interface 1
21 SPI X X Serial Peripheral Interface
22 SSC X X Synchronous Serial Controller
23 TC0 X X Timer/Counter 0
24 TC1 X X Timer/Counter 1
25 TC2 X X Timer/Counter 2
26 TC3 X X Timer/Counter 3
27 TC4 X X Timer/Counter 4
28 TC5 X X Timer/Counter 5
51
SAM4S Series [DATASHEET]
Atmel-11100K-ATARM-SAM4S-Datasheet_09-Jun-15
11.2 Peripheral Signal Multiplexing on I/O Lines
The SAM4S features two PIO controllers on 64-pin versions (PIOA and PIOB) or three PIO controllers on the 100-
pin version (PIOA, PIOB and PIOC), that multiplex the I/O lines of the peripheral set.
The SAM4S 64-pin and 100-pin PIO controllers control up to 32 lines. Each line can be assigned to one of three
peripheral functions: A, B or C. The multiplexing tables in the following tables define how the I/O lines of the
peripherals A, B and C are multiplexed on the PIO Controllers. The column “Comments” has been inserted in this
table for the user’s own comments; it may be used to track how pins are defined in an application.
Note that some peripheral functions which are output only, might be duplicated within the tables.
29 ADC X X Analog-to-Digital Converter
30 DACC X X Digital-to-Analog Converter Controller
31 PWM X X Pulse Width Modulation
32 CRCCU X X CRC Calculation Unit
33 ACC X X Analog Comparator Controller
34 UDP X X USB Device Port
Table 11-1. Peripheral Identifiers (Continued)
Instance ID Instance Name NVIC Interru pt PMC Clock Control Instance Description
SAM4S Series [DATASHEET]
Atmel-11100K-ATARM-SAM4S-Datasheet_09-Jun-15
52
11.2.1 PIO Controller A Multiplexing
Notes: 1. Only available in SAM4S4x and SAM4S2x.
2. WKUPx can be used if PIO controller defines the I/O line as "input".
3. Refer to Section 6.2 “System I/O Lines”.
Table 11-2. Multiplexing on PIO Controller A (PIOA)
I/O Line Peripheral A Peripheral B Peripheral C Peripheral D(1) Extra Function System
Function Comments
PA0 PWMH0 TIOA0 A17 WKUP0(2)
PA1 PWMH1 TIOB0 A18 WKUP1(2)
PA2 PWMH2 SCK0 DATRG WKUP2(2)
PA3 TWD0 NPCS3
PA4 TWCK0 TCLK0 WKUP3(2)
PA5 RXD0 NPCS3 WKUP4(2)
PA6 TXD0 PCK0
PA7 RTS0 PWMH3 XIN32(3)
PA8 CTS0 ADTRG WKUP5(2) XOUT32(3)
PA9 URXD0 NPCS1 PWMFI0 WKUP6(2)
PA10 UTXD0 NPCS2 PWMFI1(1)
PA11 NPCS0 PWMH0 WKUP7(2)
PA12 MISO PWMH1
PA13 MOSI PWMH2
PA14 SPCK PWMH3 WKUP8(2)
PA15 TF TIOA1 PWML3 WKUP14/PIODCEN1(4)
PA16 TK TIOB1 PWML2 WKUP15/PIODCEN2(4)
PA17 TD PCK1 PWMH3 AD0(5)
PA18 RD PCK2 A14 PWMFI2(1) AD1(5)
PA19 RK PWML0 A15 AD2/WKUP9(2)
PA20 RF PWML1 A16 AD3/WKUP10(2)
PA21 RXD1 PCK1 AD8(5) 64-/100-pin versions
PA22 TXD1 NPCS3 NCS2 AD9(5) 64-/100-pin versions
PA23 SCK1 PWMH0 A19 PIODCCLK(6) 64-/100-pin versions
P A24 RTS1 PWMH1 A20 PIODC0 64-/100-pin versions
P A25 CTS1 PWMH2 A23 PIODC1 64-/100-pin versions
P A26 DCD1 TIOA2 MCDA2 PIODC2 64-/100-pin versions
P A27 DTR1 TIOB2 MCDA3 PIODC3 64-/100-pin versions
P A28 DSR1 TCLK1 MCCDA PIODC4 64-/100-pin versions
P A29 RI1 TCLK2 MCCK PIODC5 64-/100-pin versions
PA30 PWML2 NPCS2 MCDA0 WKUP11(2)/PIODC6 64-/100-pin versions
P A31 NPCS1 PCK2 MCDA1 PIODC7 64-/100-pin versions
53
SAM4S Series [DATASHEET]
Atmel-11100K-ATARM-SAM4S-Datasheet_09-Jun-15
4. PIODCENx/PIODCx has priority over WKUPx. Refer to Section 31.5.13 “Parallel Capture Mode”.
5. To select this extra function, refer to Section 42.5.3 “Analog Inputs”.
6. To select this extra function, refer to “Section 31.5.13 “Parallel Capture Mode”.
11.2.2 PIO Controller B Multiplexing
Notes: 1. Analog input has priority ove r RTCOUTx pin. See Section 16.5.8 “Waveform Generation ”.
2. WKUPx can be used if PIO controller defines the I/O line as "input".
3. To select this extra function, refer to Section 42.5.3 “Analog Inputs”.
4. Refer to Section 6.2 “System I/O Lines”.
5. DAC0 is selected when DACC_CHER.CH0 is set. DAC1 is selected when DACC_CHER.CH1 is set. See Section 43.7.3
“DACC Channel Enable Register”.
Table 11-3. Multiplexing on PIO Controlle r B (PIOB)
I/O
Line Peripheral A Peripheral B Peripheral C Extra Fu nction System Function Comments
PB0 PWMH0 AD4/RTCOUT0(1)
PB1 PWMH1 AD5/RTCOUT1(1)
PB2 URXD1 NPCS2 AD6/WKUP12(2)
PB3 UTXD1 PCK2 AD7(3)
PB4 TWD1 PWMH2 TDI(4)
PB5 TWCK1 PWML0 WKUP13(2) TDO/TRACESWO(4)
PB6 TMS/SWDIO(4)
PB7 TCK/SWCLK(4)
PB8 XOUT(4)
PB9 XIN(4)
PB10 DDM
PB11 DDP
PB12 PWML1 ERASE(4)
PB13 PWML2 PCK0 DAC0(5) 64-/100-pin versions
PB14 NPCS1 PWMH3 DAC1(5) 64-/100-pin versions
SAM4S Series [DATASHEET]
Atmel-11100K-ATARM-SAM4S-Datasheet_09-Jun-15
54
11.2.3 PIO Controller C Multiplexing
Note: 1. To select this extra functi on, refer to Section 42.5.3 “Analog Inputs”.
Table 11-4. Multiplexing on PIO Controlle r C (PIOC)
I/O Line Peripheral A Peripheral B Peripheral C Extra
Function System
Function Comments
PC0 D0 PWML0 100-pin version
PC1 D1 PWML1 100-pin version
PC2 D2 PWML2 100-pin version
PC3 D3 PWML3 100-pin version
PC4 D4 NPCS1 100-pin version
PC5 D5 100-pin version
PC6 D6 100-pin version
PC7 D7 100-pin version
PC8 NWE 100-pin version
PC9 NANDOE 100-pin version
PC10 NANDWE 100-pin version
PC11 NRD 100-pin version
PC12 NCS3 AD12(1) 100-pin version
PC13 NWAIT PWML0 AD10(1) 100-pin version
PC14 NCS0 100-pin version
PC15 NCS1 PWML1 AD11(1) 100-pin version
PC16 A21/NANDALE 100-pin version
PC17 A22/NANDCLE 100-pin version
PC18 A0 PWMH0 100-pin version
PC19 A1 PWMH1 100-pin version
PC20 A2 PWMH2 100-pin version
PC21 A3 PWMH3 100-pin version
PC22 A4 PWML3 100-pin version
PC23 A5 TIOA3 100-pin version
PC24 A6 TIOB3 100-pin version
PC25 A7 TCLK3 100-pin version
PC26 A8 TIOA4 100-pin version
PC27 A9 TIOB4 100-pin version
PC28 A10 TCLK4 100-pin version
PC29 A11 TIOA5 AD13(1) 100-pin version
PC30 A12 TIOB5 AD14(1) 100-pin version
PC31 A13 TCLK5 100-pin version
55
SAM4S Series [DATASHEET]
Atmel-11100K-ATARM-SAM4S-Datasheet_09-Jun-15
12. ARM Cortex-M4 Processor
12.1 Description
The Cortex-M4 processor is a high performance 32-bit processor designed for the micr ocon trolle r mar ket. It offers
significant benefits to developers, including outstanding processing performance combined with fast interrupt
handling, enhanced system debug with extensive breakpoint and trace capabilities, efficient processor core,
system and memories, ultra-low power consumption with integrated sleep modes, and platform security
robustness, with integrated memory protection unit (MPU).
The Cortex-M4 processor is built on a high-performance processor core, with a 3-stage pipeline Harvard
architecture, making it ideal for demanding embedded a pplications. The processor delivers exceptional power
efficiency through an e fficient instruction set and extensively optimized d esign, providing high-end processing
hardware including a range of single-cycle and SIMD multiplication and multiply-with-accumulate capabilities,
saturating arithmetic and dedicated hardware division.
To facilitate the design of cost-sensitive devices, the Cortex-M4 processor implements tightly-coupled system
components that reduce processor area while significantly improving interrupt handling and system debug
capabilities. The Cortex-M4 processor implements a version of th e Thumb® instruction set based on Thumb-2
technology, ensuring high code density and reduced program memory requirements. The Cortex-M4 instruction
set provides the exceptional performance expected of a modern 32-bit architecture, with the high code density of
8-bit and 16-bit microcontrollers.
The Cortex-M4 processor closely integrates a configurable NVIC, to deliver industry-leading interrupt
performance. The NVIC includes a non-maskable interrupt (NMI), and provides up to 256 interrupt priority levels.
The tight integration of the processor core and NVIC provides fast execution of interrupt service routines (ISRs),
dramatically reducing the interrupt latency. This is achieved through the hardware stac king of registers, and the
ability to suspend load-multiple and store-multiple operations. Interrupt handlers do not require wrapping in
assembler code, removing any code over head from the ISRs. A tail-chain optimization also significantly re duces
the overhead when switching from one ISR to another.
To optimize low-power designs, the NVIC integrates with the sleep modes, that include a deep sleep function that
enables the entire device to be rapidly powered down while still retaining program state.
12.1.1 System Level Interface
The Cortex-M4 processor provides multiple interfaces using AMBA® technology to provide high speed, low laten cy
memory acces ses. It supports unaligned data accesses and implements atomic bit manipulation that enables
faster peripheral controls, system spinlocks and thread-safe Boolean data handling.
The Cortex-M4 processor has a Memory Protection Unit (MPU) that provides fine grain memory control, enabling
applications to utilize multiple privilege levels, separating and protecting code, data and stack on a task-by-task
basis. Such requirements are becoming critical in many embe dd e d ap plic at ion s such as automoti ve .
12.1.2 Integrated Configurable Debug
The Cortex-M4 processor implements a complete hardware debug solution. This provides high system visibility of
the processor and memory through either a traditional JTAG port or a 2-pin Serial Wire Debug (SWD) port that is
ideal for microcontrollers and other small package devices.
For system trace the processor integrates an In strumentation Trace Macrocell (ITM) a longside data wa tchpoints
and a profiling unit. T o enable simple and cost-ef fective profiling of the system eve nts these generate, a Serial
Wire Viewer (SWV) can export a stream of software-ge nerated messages, data trace, and profiling inform ation
through a single pin.
The Flash Patch and Breakpoint Unit (FPB) provides up to eight hardware breakpoint comparators that debuggers
can use. The comparators in the FPB also pr ovide rema p functions of up to eight wo rds in the pr ogram code in the
SAM4S Series [DATASHEET]
Atmel-11100K-ATARM-SAM4S-Datasheet_09-Jun-15
56
CODE memory region. This enables applications stored o n a non-erasable, ROM-base d microcontroller to be
patched if a small programmable memory, for example flash, is available in the device. During initialization, the
application in ROM dete cts, from the programm able memory, whethe r a patch is required. If a patch is required,
the application programs the FPB to remap a number of addresses. When those addresses are accessed, the
accesses are redirected to a remap table sp ecified in the FPB configuration, which means the program in the non-
modifiable ROM can be patched.
12.2 Embedded Characteristics
Tigh t int eg ra tio n of syste m peri ph er al s reduces area and deve lo pm e nt co sts
Thumb instruction set combines high code density with 32-bit performance
Code-patch ability for ROM system updates
Power control optimization of system components
Integrated sleep modes for low power consumption
Fast code execution permits slower processor clock or increases sleep mode time
Hardware division and fast digital-signal-processing oriented multiply accumulate
Saturating arithmetic for signal processing
Deterministic, high-performance interrupt handling for time-critical applications
Memory Protection Unit (MPU) for safety-critical applications
Extensive debug and trace capabilities:
Serial Wire Debug and Serial Wire Trace reduce the number of pins required for debugging, tracing,
and code profiling.
12.3 Block Diagram
Figure 12-1. Typical Cortex-M4 Implementation
NVIC
Debug
Access
Port
Memory
Protection Unit
Serial
Wire
Viewer
Bus Matrix
Code
Interface
SRAM and
Peripheral Interface
Data
Watchpoints
Flash
Patch
Cortex-M4
Processor
Processor
Core
57
SAM4S Series [DATASHEET]
Atmel-11100K-ATARM-SAM4S-Datasheet_09-Jun-15
12.4 Cortex-M4 Models
12.4.1 Programmers Model
This section describes the Cortex-M4 programmers model. In addition to the individual core register descriptions, it
contains information about the processor modes and privilege levels for software execution and stacks.
12.4.1.1 Processor Modes and Privilege Levels for Software Execution
The processor modes are:
Thread mode
Used to execute application software. The processor enters the Thread mode when it comes out of reset.
Handler mode
Used to handle exceptions. The processor returns to the Thread mode when it has finished exception
processing.
The privilege levels for software execution are:
Unprivileged
The software:
Has limited access to the MSR and MRS instructions, and cannot use the CPS instruction
Cannot access the System Timer, NVIC, or System Control Block
Might have a restricted access to memory or periphera ls.
Unprivileged software executes at the unprivileged level.
Privileged
The software can use all the instructions and has access to all resources. Privileged software executes at
the privileged level.
In Thread mode, the Control Register controls whether the software execution is privileged or unprivileged, see
“Control Register” . In Handler mode, software execution is always privileged.
Only privileged software can write to the Control Register to change the privilege level for software execution in
Thread mode. Unprivile ged software can use the SVC inst ruction to make a supervisor call to transfer c ontrol to
privileged software.
12.4.1.2 Stacks
The processor uses a full descending stack. This means the stack pointer holds the address of the last stacked
item in memory When the processor pushes a new item onto the stack, it decrements the stack pointer and then
writes the item to the new memory lo cation. The pr ocessor implements two stacks, the main stack and the process
stack, with a pointer for each held in independent registers, see “Stack Pointer” .
In Thread mode, the Control Register controls whether the proces sor uses the main stack or the process stack,
see “Control Register” .
In Handler mode, the processor always uses the main stack.
The options for processor operations are:
Note: 1. See “Control Register” .
Table 12-1. Summary of processor mode, execution privilege level, and stack use options
Processor
Mode Used to Execute Privilege Level for
Software Execution Stack Used
Thread Applications Privileged or unprivileged(1) Main stack or process stack(1)
Handler Exception handlers Always privileged Main stack
SAM4S Series [DATASHEET]
Atmel-11100K-ATARM-SAM4S-Datasheet_09-Jun-15
58
12.4.1.3 Core Registers
Figure 12-2. Processor Core Regist ers
Notes: 1. Describes access type during program execution in thread mode and Handler mode. Debug access can differ.
2. An entry of Either means privileged and unprivileged software can access the register.
SP (R13)
LR (R14)
PC (R15)
R5
R6
R7
R0
R1
R3
R4
R2
R10
R11
R12
R8
R9
Low registers
High registers
MSP‡
PSP‡
PSR
PRIMASK
FAULTMASK
BASEPRI
CONTROL
General-purpose registers
Stack Pointer
Link Register
Program Counter
Program status register
Exception mask registers
CONTROL register
Special registers
‡Banked version of SP
Table 12-2. Core Processor Registers
Register Name Access(1) Required Privilege(2) Reset
General-purpose registers R0–R12 Read/Write Either Unknown
Stack Pointer MSP Read/Write Privileged See description
Stack Pointer PSP Read/Write Either Unknown
Link Register LR Read/Write Either 0xFFFFFFFF
Program Counter PC Read/Write Either See description
Program Status Register PSR Read/Write Privileged 0x01000000
Application Program Status Register APSR Read/Write Either 0x00000000
Interrupt Program Status Register IPSR Read-only Privileged 0 x 00000000
Execution Program Status Register EPSR Read-only Privileged 0x01000000
Priority Mask Register PRIMASK Read/Write Privileged 0x00000000
Fault Mask Register FAULTMASK Read/Write Privileg ed 0x00000000
Base Priority Mask Register BASEPRI Read/Write Privileged 0x00000000
Control Register CONTROL Read/Write Privileged 0x00000000
59
SAM4S Series [DATASHEET]
Atmel-11100K-ATARM-SAM4S-Datasheet_09-Jun-15
12.4.1.4 General-purpose Registers
R0–R12 are 32 -b it ge ne ra l- pu rp os e re gisters for data opera tio ns.
12.4.1.5 Stack Pointer
The Stack Pointer (SP) is register R13. In Thread mode, bit[1] of the Control Register indicates the stack pointer to
use:
0 = Main Stack Pointer (MSP). This is the reset value.
1 = Process Stack Pointer (PSP).
On reset, the processor loads the MSP with the value from address 0x00000000.
12.4.1.6 Link Register
The Link Register (LR) is register R14. It stores the return information for subroutines, function calls, and
exceptions. On reset, the processor loads the LR value 0xFFFFFFFF
.
12.4.1.7 Program Counter
The Progra m Coun te r ( PC) is r eg ister R15. It con tains th e cur rent pro gr am addr ess. On r eset, the pr ocesso r lo ads
the PC with the value of the reset vector, which is at address 0x00000004. Bit[0] of the value is loa ded into the
EPSR T-bit at reset and must be 1.
SAM4S Series [DATASHEET]
Atmel-11100K-ATARM-SAM4S-Datasheet_09-Jun-15
60
12.4.1.8 Program Status Register
Name: PSR
Access: Read/Write
Reset: 0x000000000
The Program Status Register (PSR) combines:
•Application Program Status Register (APSR)
•Interrupt Program Status Register (IPSR)
•Execution Program Status Register (EPSR).
These registers are mutually exclusive bitfields in the 32-bit PSR.
The PSR accesses these registers individually or as a combination of any two or all three registers, using the register
name as an argument to the MSR or MRS instructions. For example:
• Read of all th e registers using PSR with the MRS instruction
• Write to the APSR N, Z, C, V and Q bits using APSR_nzcvq with the MSR instruction.
The PSR combinations and attributes are:
Notes: 1. The processor ignores writes to the IPSR bits.
2. Reads of the EPSR bits return zero, and the processor ignores writes to these bits.
See the instruction descriptions “MRS” and “MSR” for more information about how to access the program status registers.
31 30 29 28 27 26 25 24
NZCVQ ICI/IT T
23 22 21 20 19 18 17 16
–
15 14 13 12 11 10 9 8
ICI/IT – ISR_NUMBER
76543210
ISR_NUMBER
Name Access Combination
PSR Read/Write(1)(2) APSR, EPSR, and IPSR
IEPSR Read-only EPSR and IPSR
IAPSR Read/Write(1) APSR and IPSR
EAPSR Read/Write(2) APSR and EPSR
61
SAM4S Series [DATASHEET]
Atmel-11100K-ATARM-SAM4S-Datasheet_09-Jun-15
12.4.1.9 Application Program Status Register
Name: APSR
Access: Read/Write
Reset: 0x000000000
The APSR contains the current state of the condition flags from previous instruction executions.
• N: Negative Flag
0: Operation result was positive, zero, greater than, or equal
1: Operation result was negative or less than.
• Z: Zero Flag
0: Operation result was not zero
1: Operation result was zero.
• C: Carry or Borrow Flag
Carry or borrow flag:
0: Add operation did not result in a carry bit or subtract operation resulted in a borrow bit
1: Add operation resulted in a carry bit or subtract operation did not result in a borrow bit.
• V: Overflow Flag
0: Operation did not result in an overflow
1: Operation resulted in an overflow.
• Q: DSP Overflow and Saturation Flag
Sticky saturation flag:
0: Indicates that saturation has not occurred since reset or since the bit was last cleared to zero
1: Indicates when an
SSAT
or
USAT
instruction results in saturation.
This bit is cleared to zero by software using an
MRS
instruction.
• GE[19:16] : Gre at er Tha n or Eq ua l Fl ags
See “SEL” for more information.
31 30 29 28 27 26 25 24
NZCVQ –
23 22 21 20 19 18 17 16
– GE[3:0]
15 14 13 12 11 10 9 8
–
76543210
–
SAM4S Series [DATASHEET]
Atmel-11100K-ATARM-SAM4S-Datasheet_09-Jun-15
62
12.4.1.10 Interrupt Program Status Register
Name: IPSR
Access: Read/Write
Reset: 0x000000000
The IPSR contains the exception type number of the current Interrupt Service Routine (ISR).
• ISR_NUMBER: Number of the Current Exception
0 = Thread mode
1 = Reserved
2 = NMI
3 = Hard fault
4 = Memory management fault
5 = Bus fault
6 = Usage fault
7–10 = Reserved
11 = SVCall
12 = Reserved for Debug
13 = Reserved
14 = PendSV
15 = SysTick
16 = IRQ0
49 = IRQ34
See “Exception Types” for more informatio n.
31 30 29 28 27 26 25 24
–
23 22 21 20 19 18 17 16
–
15 14 13 12 11 10 9 8
– ISR_NUMBER
76543210
ISR_NUMBER
63
SAM4S Series [DATASHEET]
Atmel-11100K-ATARM-SAM4S-Datasheet_09-Jun-15
12.4.1.11 Execution Program Status Register
Name: EPSR
Access: Read/Write
Reset: 0x000000000
The EPSR contains the Thumb state bit, and the execution state bits for either the If-Then (IT) instruction, or the Interrupt-
ible-Continuable Instruction (ICI) field for an interrupted load multiple or store multiple instruction.
Attempts to read the EPSR directly through application software using the MSR instruction always return ze ro. Attempts to
write the EPSR using the MSR instruction in the application software are ignored. Fault handlers can examine the EPSR
value in the stacked PSR to indicate the operation that is at fault. See “Exception Entry and Return” .
• ICI: Interruptible-continuable Instruction
When an interrupt occurs during the execution of an LDM, STM, PUSH, POP, VLDM, VSTM, VPUSH, or VPOP instruction,
the processor:
– Stops the load multiple or store multiple instruction operation temporarily
– Stores the next register operand in the multiple operation to EPSR bits[15:12].
After servicing the interrupt, the processor:
– Returns to the register pointed to by bits[15:12]
– Resumes the execution of the multiple load or store instruction.
When the EPSR holds the ICI execution state, bits[26:25,11:10] are zero.
• IT: If-Then Instruction
Indicates the execution state bits of the IT instruction.
The If-Then block contains up to four instructions following an IT instruction. Each instruction in the block is conditional.
The conditions for the instructions are either all the same, or some can be the inverse of others. See “IT” for more
information.
• T: Thumb State
The Cortex-M4 processor only supp or ts the execution of instructions in Thumb state. The following can clear the T b it to 0:
– Instructions BLX, BX and POP{PC}
– Restoration from the stacked xPSR value on an exception return
– Bit[0] of the vector value on an exception entry or reset.
Attempting to execute instructions when the T bit is 0 results in a fault or lockup. See “Lockup” for more information.
31 30 29 28 27 26 25 24
–ICI/ITT
23 22 21 20 19 18 17 16
–
15 14 13 12 11 10 9 8
ICI/IT –
76543210
–
SAM4S Series [DATASHEET]
Atmel-11100K-ATARM-SAM4S-Datasheet_09-Jun-15
64
12.4.1.12 Exception Mask Registers
The exception mask registers disable the handling of exceptions by the processor. Disable exceptions where they
might impact on timing critical tasks.
To access the exception mask registers use the MSR and MRS instructions, or the CPS instruction to change the
value of PRIMASK or FAULTMASK. See “MRS” , “MSR” , and “CPS” for more information.
12.4.1.13 Priority Mask Register
Name: PRIMASK
Access: Read/Write
Reset: 0x000000000
The PRIMASK register prevents the activation of all exceptions with a configurable priority.
•PRIMASK
0: No effect
1: Prevents the activation of all exceptions with a configurable priority.
31 30 29 28 27 26 25 24
–
23 22 21 20 19 18 17 16
–
15 14 13 12 11 10 9 8
–
76543210
– PRIMASK
65
SAM4S Series [DATASHEET]
Atmel-11100K-ATARM-SAM4S-Datasheet_09-Jun-15
12.4.1.14 Fault Mask Register
Name: FAULTMASK
Access: Read/Write
Reset: 0x000000000
The FAULTMASK register prevents the activation of all exceptions except for Non-Maskable Interrupt (NMI).
• FAULTMASK
0: No effect.
1: Prevents the activation of all exceptions except for NMI.
The processor clears the FAULTMASK bit to 0 on exit from any exception handler except the NMI handler.
31 30 29 28 27 26 25 24
–
23 22 21 20 19 18 17 16
–
15 14 13 12 11 10 9 8
–
76543210
– FAULTMASK
SAM4S Series [DATASHEET]
Atmel-11100K-ATARM-SAM4S-Datasheet_09-Jun-15
66
12.4.1.15 Base Priority Mask Register
Name: BASEPRI
Access: Read/Write
Reset: 0x000000000
The BASEPRI register defines the minimum priority for exception processing. When BASEPRI is set to a nonzero value, it
prevents the activation of all exceptions with same or lower priority level as the BASEPRI value.
• BASEPRI
Priority mask bits:
0x0000: No effect
Nonzero: Defines the base priority for exception processing
The processor does not process any exception with a priority value greater than or equal to BASEPRI.
This field is similar to the priority fields in the interru pt priority registers. The processor implements only bits[7:4] of this
field, bits[3:0] read as zero and ignore writes. See “Interrupt Priority Registers” for more information. Remember that
higher priority field values correspond to lower exception priorities.
31 30 29 28 27 26 25 24
–
23 22 21 20 19 18 17 16
–
15 14 13 12 11 10 9 8
–
76543210
BASEPRI
67
SAM4S Series [DATASHEET]
Atmel-11100K-ATARM-SAM4S-Datasheet_09-Jun-15
12.4.1.16 Control Register
Name: CONTROL
Access: Read/Write
Reset: 0x000000000
The Control Register contro ls the stack used and the p rivilege level for software execution when the processor is in Thread
mode.
• SPSEL: Active Stack Pointer
Defines the current stack:
0: MSP is the current stack pointer.
1: PSP is the current stack pointer.
In Handler mode, this bit reads as zero and igno res writes. The Cortex-M4 updates this bit automatically on exception
return.
• nPRIV: Thread Mode Privilege Level
Defines the Thread mode privilege level:
0: Privileged.
1: Unprivileged.
Handler mode always uses the MSP, so the processor ignores explicit writes to the active stack pointer bit of the Control
Register when in Handler mode. The exception entry and return mechanisms update the Control Register based on the
EXC_RETURN value.
In an OS environment, ARM recommen ds that threa ds running in Thr ead mode use the proce ss stack, and the kernel and
exception handlers use the main stack.
By default, the Thread mode uses the MSP. To switch the stack pointer used in Thread mode to the PSP, either:
• Use the MSR instruction to set the Active stack pointer bit to 1, see “MSR” , or
• Perform an exception return to Thread mode with the appropriate EXC_RETURN value , see Table 12-10.
Note: When changing the stack pointer, the software must use an ISB instruction immediately after the MSR instruction. This ensures
that instructions after the ISB execute using the new stack pointer. See “ISB” .
31 30 29 28 27 26 25 24
–
23 22 21 20 19 18 17 16
–
15 14 13 12 11 10 9 8
–
76543210
– – SPSEL nPRIV
SAM4S Series [DATASHEET]
Atmel-11100K-ATARM-SAM4S-Datasheet_09-Jun-15
68
12.4.1.17 Exceptions and Interrupts
The Cortex-M4 processor supports interrupts and system exceptions. The processor and the Nested Vectored
Interrupt Controller (NVIC) prioritize and handle all exceptions. An exception changes the normal flow of software
control. The processor uses the Handler mode to handle all exceptions except for reset. See “Exception Entry”
and “Exception Return” for more information.
The NVIC registers control interrupt handling. See “Nested Vectored Interrupt Controller (NVIC)” for more
information.
12.4.1.18 Data Types
The processor supports the following data types:
32-bit words
16-bit halfwords
8-bit bytes
The process or ma nage s all da ta memor y acc es se s as little-e nd ian . In str uc tio n me m or y an d Private
Peripheral Bus (PPB) accesses are always little-endian. See “Memory Regions, Types and Attributes” for
more information.
12.4.1.19 Cortex Microcontroller Software Interface Standard (CMSIS)
For a Cortex-M4 microcontroller system, the Cortex Microcontroller Software Interface Standard (CMSIS) defines:
A common way to:
Access peripheral registers
Define exception vectors
The names of :
The registe rs of the co re per iph e ra ls
The core exception vectors
A device-independent interface for RTOS kernels, including a debug channel.
The CMSIS includes address definitions and data structures for the core peripherals in the Cortex-M4 processor.
The CMSIS simplifies the software development by enabling the reuse of template code and the combination of
CMSIS-compliant software components from various middleware vendors. Software vendors can expand the
CMSIS to include their peripheral definitions and access functions for those peripherals.
This document includes the register names defined by the CMSIS, an d gives short descriptions of the CMSIS
functions that address the processor core and the core peripherals.
Note: This document uses the register short names defined by the CMSIS. In a few cases, these differ from the architectural
short names that might be used in other documents.
The following sections give more information about the CMSIS:
Section 12.5.3 ”Power Management Programming Hints”
Section 12.6.2 ”CMSIS Functions”
Section 12.8.2.1 ”NVIC Programming Hints”.
69
SAM4S Series [DATASHEET]
Atmel-11100K-ATARM-SAM4S-Datasheet_09-Jun-15
12.4.2 Memory Model
This section describes the processor memory map, the behavior of memory accesses, and the bit-banding
features. The processor has a fixed memory map that provides up to 4 GB of addressable memory.
Figure 12-3. Memory Map
The regions for SRAM and peripherals include bit-band r egions. Bit-banding provides atomic operatio ns to bit
data, see “Bit-banding” .
The processor reserves regions of the Private peripheral bus (PPB) address range for core peripheral registers.
This memory mapping is gen eric to ARM Cortex-M 4 products. To get the sp ecific memory map ping of this product,
refer to the Memories section of the datasheet.
12.4.2.1 Memory Regions, Types and Attributes
The memory map and the programming of the MPU split the memory map into regions. Each region has a defined
memory type, and some regions have additional memo ry attributes. The memory type and attributes determin e the
behavior of accesses to the region.
Vendor-specific
memory
External device
External RAM
Peripheral
SRAM
Code
0xFFFFFFFF
Private peripheral
bus
0xE0100000
0xE00FFFFF
0x9FFFFFFF
0xA0000000
0x5FFFFFFF
0x60000000
0x3FFFFFFF
0x40000000
0x1FFFFFFF
0x20000000
0x00000000
0x40000000
32 MB Bit-band alias
0x400FFFFF
0x42000000
0x43FFFFFF
1 MB Bit-band region
32 MB Bit-band alias
0x20000000
0x200FFFFF
0x22000000
0x23FFFFFF
1.0 GB
1.0 GB
0.5 GB
0.5 GB
0.5 GB
0x DFFFFFFF
0xE000 0000
1.0 MB
511 MB
1 MB Bit-band region
SAM4S Series [DATASHEET]
Atmel-11100K-ATARM-SAM4S-Datasheet_09-Jun-15
70
Memory Types
Normal
The processor can re-order transactions for efficiency, or perform speculative reads.
Device
The processor preserves transaction order relative to other transactions to Device or Strongly-ordered
memory.
Strongly-ordered
The processor preserves transaction order relative to all other transactions.
The different ordering requirements for Device and Strongly-ordered memory mean that the memory system can
buffer a write to Device memory, but must not buffer a write to Strongly-ordered memory.
Additional Memory Attributes
Shareable
For a shareable memor y region, the memory system pr ovides data synchronizatio n between bus masters in
a system with multiple bus masters, for example, a processor with a DMA controller.
Strongly-ordered memory is always shareable.
If multiple bus masters can access a non-shareable memory region, the software must ensure data
coherency between the bus masters.
Execute Never (XN)
Means the processor prevents instruction accesses. A fault exception is generated only on execution of an
instruction executed from an XN region.
12.4.2.2 Memory System Ordering of Memory Accesses
For most memory accesses caused by explicit memory access instructions, the memory system does not
guarantee that the order in which the accesses complete matches the program order of the instructions, providing
this does not affect the behavior of the instruction sequence. Normally, if correct progr am execution depends on
two memory accesses completing in program order, the software must in sert a me mory barrier instructi on betwee n
the memory access instructions, see “Software Ordering of Memory Accesses” .
However, the memory system does guarantee some ordering of accesses to Device and Strongly-ordered
memory. F or t wo m e mo ry a ccess instru ctio n s A1 a nd A2, if A1 occurs before A2 in program order, the ordering of
the memory accesses is described below.
Where:
– Means that the memory system does not guarantee the ordering of the accesses.
< Means that accesses are observed in program order, that is, A1 is always observed
before A2.
12.4.2.3 Behavior of Memory Accesses
The following table describes the behavior of accesses to each region in the memory map.
Table 12-3. Ordering of the Memory Accesses Caused by Two Instr uction s
A2
Normal
Access
Device Access Strongly-
ordered
AccessA1 Non-
shareable Shareable
Normal Access ––––
Device access, non-shareable – < – <
Device access, shareable – – < <
Strongly-ordered access – < < <
71
SAM4S Series [DATASHEET]
Atmel-11100K-ATARM-SAM4S-Datasheet_09-Jun-15
Note: 1. See “Memory Regions, Types and Attributes” for more information.
The Code, SRAM, and externa l RAM regions can hold program s. However, ARM recommends that programs
always use the Code region. This is beca use the processor has separ ate buses that enable instruction fetches and
data accesses to occur simultaneously.
The MPU can overr ide the default memory acce ss behavior described in this section. For more in formation, see
“Memory Protection Unit (MPU)” .
Additional Memory Access Constraints For Caches and Shared Memory
When a system includes ca ches or shared memory, some memory regions have additional access constraints,
and some regions are subdivided, as Table 12-5 shows.
Notes: 1. See “Memory Regions, Types and Attributes” for more information.
2. WT = Write through, no write allocate. WBWA = W rite back, write allocate. See the “Glossary” for more information.
Instruction Prefetch and Branch Prediction
The Cortex-M4 processor:
Table 12-4. Memory Access Behavior
Address Range Memory Region Memory
Type XN Description
0x00000000–0x1FFFFFFF Code Normal(1) –Executable region for program code. Data can also be
put here.
0x20000000–0x3FFFFFFF SRAM Normal(1) –Executable region for data. Code can also be put here.
This region includes bit band and bit band alias areas,
see Table 12-6.
0x40000000–0x5FFFFFFF Peripheral Device(1) XN This region includes bit band and bit band alias areas,
see Table 12-6.
0x60000000–0x9FFFFFFF External RAM Normal(1) – Executable region for data
0xA0000000–0xDFFFFF FF External device Device(1) XN External Device memory
0xE0000000–0xE00FFFFF Private Peripheral Bus Strongly-
ordered(1) XN This region includes the NVIC, system timer , and system
control block.
0xE0100000–0xFFFFFFFF Reserved Device(1) XN Reserved
Table 12-5. Memory Region Shareability and Cache Policies
Address Range Memory Region Memory Type Shareability Cache Policy
0x00000000–0x1FFFFFFF Code Normal(1) –WT
(2)
0x20000000–0x3FFFFFFF SRAM Normal(1) –WBWA
(2)
0x40000000–0x5FFFFFFF Peripheral Device(1) ––
0x60000000–0x7FFFFFFF External RAM Normal(1) –WBWA(2)
0x80000000–0x9FFFFFFF WT(2)
0xA0000000–0xBFFFFFFF External device Device(1) Shareable(1) –
0xC0000000–0xDFFFFFFF Non-shareable(1)
0xE0000000–0xE00FFFFF Private Peripheral
Bus Strongly-ordered(1) Shareable(1) –
0xE0100000–0xFFFFFFFF Vendor-specific
device Device(1) ––
SAM4S Series [DATASHEET]
Atmel-11100K-ATARM-SAM4S-Datasheet_09-Jun-15
72
Prefetches instructions ahead of execution
Speculatively prefetches from branch target addresses.
12.4.2.4 Software Ordering of Memory Accesses
The order of instructions in the program flow does not always guarantee the order of the corresponding memory
transactions. This is because:
The processor can reorder some memory accesses to improve efficiency, providing this does not affect the
behavior of the instruction sequence.
The processor has multiple bus interfaces
Memory or devices in the memory map have different wait states
Some memory accesses are buffered or speculative.
“Memory System Ordering of Memory Acce sses” describes the cases where the memory system guarantees the
order of memory accesses. Otherwise, if the order o f memory accesses is critical, the software must include
memory barrier instructions to force that ordering. The processor provides the following memory barrier
instructions:
DMB
The Data Memory Barrier (DMB) instruction ensures that outstanding memory transactions complete before
subsequent memory transactions. See “DMB” .
DSB
The Data Synchronization Barrier (DSB) instruction ensur es that outstanding memory transactions comp lete
before subsequent instructions execute. See “DSB” .
ISB
The Instruction Synchronization Barrier (ISB) ensures that the effect of all completed memory transactions is
recognizable by subsequent instructions. See “ISB” .
MPU Programming
Use a DSB followed by an ISB instruction or exception return to ensure that the new MPU configuration is used by
subsequent instructions.
12.4.2.5 Bit-banding
A bit-band re gion maps each word in a bit-band alia s region to a sing le bit in the bit-band region. T he bit-band
regions occupy the lowest 1 MB of the SRAM and peripheral memory regions.
The memory map has two 32 MB alias regions that map to two 1 MB bit-band regions:
Accesses to the 32 MB SRAM alias region map to the 1 MB SRAM bit-band region, as shown in Table 12-6.
Accesses to the 32 MB peripheral alias region map to the 1 MB peripheral bit- band region, as shown in
Table 12-7.
Table 12-6. SRAM Memory Bit-banding Regions
Address Range Memory Region Instruction and Data Accesses
0x20000000–0x200FFFFF SRAM bit-band region Direct accesses to this memory range behave as SRAM memory accesses,
but this region is also bit-addressable through bit-band alias.
0x22000000–0x23FFFFFF SRAM bit-band alias Data accesses to this region are remapped to bit-band region. A write
operation is performed as read-modify-write. In struction accesses are not
remapped.
73
SAM4S Series [DATASHEET]
Atmel-11100K-ATARM-SAM4S-Datasheet_09-Jun-15
Notes: 1. A word access to the SRAM or peripheral bit-band alias regions map to a single bit in the SRAM or peripheral bit-band
region.
2. Bit-band accesses can use byte, halfword, or word transfers. The bit-band transfe r size matches the transfer size of the
instruction making the bit-band access.
The following formula shows how the alias region maps onto the bit-band region:
bit_word_offset = (byte_offset x 32) + (bit_number x 4)
bit_word_addr = bit_band_base + bit_word_offset
where:
Bit_word_offset
is the position of the target bit in the bit-band memory region.
Bit_word_addr
is the address of the word in the alias memory region that maps to the targeted bit.
Bit_band_base
is the starting address of the alias region.
Byte_offset
is the number of the byte in the bit-band region that contains the targeted bit.
Bit_number
is the bit position, 0–7, of the targeted bit.
Figure 12-4 shows examples of bit-band mapping between the SRAM bit-band alias region and the SRAM bit-
band region:
The alias word at 0x23FFFFE0 maps to bit[0] of the bit-band byte at 0x200FFFFF: 0x23FFFFE0 =
0x22000000 + (0xFFFFF*32) + (0*4).
The alias word at 0x23FFFFFC maps to bit[7] of the bit-band byte at 0x200FFFFF: 0x23FFFFFC =
0x22000000 + (0xFFFFF*32) + (7*4).
The alias word at 0x22000000 maps to bit[0] of the bit-band byte at 0x20000000: 0x22000000 =
0x22000000 + (0*32) + (0*4).
The alias word at 0x2200001C maps to bit[7] of the bit-band byte at 0x20000000: 0x2200001C =
0x22000000+ (0*32) + (7*4).
Table 12-7. Peripheral Memory Bit-banding Regions
Address Range Memory Region Ins t ruction and Data Accesses
0x40000000–0x400FFFFF Peripheral bit-band alias Direct accesses to this memory range behave as peripheral memory
accesses, but th is region is also bit-addressable through bit-band alias.
0x42000000–0x43FFFFFF Peripheral bit-band region Data accesses to this region are remapped to bit-band region. A write
operation is performed as read-modify-write. Instruction accesses are not
permitted.
SAM4S Series [DATASHEET]
Atmel-11100K-ATARM-SAM4S-Datasheet_09-Jun-15
74
Figure 12-4. Bit-band Mapp ing
Directly Accessing an Alias Region
Writing to a word in the alias region updates a single bit in the bit-band region.
Bit[0] of the value written to a word in the alias region determines the value written to the targeted bit in the bit-
band region . Writin g a va lue wit h bit[ 0] se t to 1 writes a 1 to the bit-band bit, and writing a value with bit[0] set to 0
writes a 0 to the bit-band bit.
Bits[31:1] of the alias word have no effect on the bit-band bit. Writing
0x01
has the same effect as writing
0xFF
.
Writing
0x00
has the same effect as writing
0x0E
.
Reading a word in the alias region:
0x00000000 indicates that the targeted bit in the bit-band region is set to 0
0x00000001 indicates that the targeted bit in the bit-band region is set to 1
Directly Accessing a Bit-band Region
“Behavior of Memory Accesses” describes the behavior of direct byte, halfword, or word accesses to the bit-band
regions.
12.4.2.6 Memory Endianness
The processor views memory as a linear collection of bytes numbered in ascending order from zero. For example,
bytes 0–3 hold the first stored word, and bytes 4–7 hold the second stored word. “Little-endian Format” describes
how words of data are stored in memory.
Little-endian Format
In little-endian format, the processor stores the least significant byte of a word at the lowest-nu mbered byte, and
the most significant byte at the highest-numbered byte. For example:
0x23FFFFE4
0x22000004
0x23FFFFE00x23FFFFE80x23FFFFEC0x23FFFFF00x23FFFFF40x23FFFFF80x23FFFFFC
0x220000000x220000140x220000180x2200001C 0x220000080x22000010 0x2200000C
32 MB alias region
0
7 0
07
0x200000000x200000010x200000020x20000003
6 5 4 3 2 1 07 6 5 4 3 2 1 7 6 5 4 3 2 1 07 6 5 4 3 2 1
07 6 5 4 3 2 1 6 5 4 3 2 107 6 5 4 3 2 1 07 6 5 4 3 2 1
0x200FFFFC0x200FFFFD0x200FFFFE0x200FFFFF
1 MB SRAM bit-band region
75
SAM4S Series [DATASHEET]
Atmel-11100K-ATARM-SAM4S-Datasheet_09-Jun-15
Figure 12-5. Little-endian Format
12.4.2.7 Synchronization Primitives
The Cortex-M4 instruction set includes pairs of synchronization primitives. These provide a non-blocking
mechanism that a thread or process can use to obta in exclusive access to a memory location. The software can
use them to perform a guaranteed read-modify-write memory update sequence, or for a semaphore mechanism.
A pair of synchronization primitives comprises:
A Load-exclusive Instruction, used to read the value of a memory location, requesting exclusive access to that
location.
A Store-Exclusive instruction, used to attempt to write to the same memory location, returning a status bit to a
register. If this bit is:
0: It indicates that the thread or process gained exclusive access to the memory, and the write succeeds,
1: It indicates that the thread or process did no t gain exclusive access to the memory, and no write is
performed.
The pairs of Load-Exclusive and Store-Exclusive instructions are:
The word instructions LDREX and STREX
The halfword instructions LDREXH and STREXH
The byte instructions LDREXB and STREXB.
The software mu st use a Load-Exclu sive instruction with the corresponding Store-Exclusive instruction.
To perform an exclusive read-modify-write of a memory location, the software must:
1. Use a Load-Exclusive instruction to read the value of the location.
2. Update the value, as required.
3. Use a Store-Exclusive instruction to attempt to write the new v alue back to the memory location
4. Test the returned status bit. If this bit is:
0: The read-modify-write completed successfully.
1: No write was performed. This indicates that the value returned at step 1 might be out of date. The
software must retry the read-modify-write sequence.
The software can use the synchronization primitives to implement a semaphore as follows:
1. Use a L oad-Exclusiv e instruction to read fr om the semaphore add ress to chec k whether the semaph ore is
free.
2. If the semaphore is free, use a Store-Exclusive instru ction to write the claim value to the semaphore
address.
Memory Register
Address
A
A+1
lsbyte
msbyte
A+2
A+3
07
B0B1B3 B2
31 24 23 16 15 8 7 0
B0
B1
B2
B3
SAM4S Series [DATASHEET]
Atmel-11100K-ATARM-SAM4S-Datasheet_09-Jun-15
76
3. If the returned status bit from step 2 indicates that the Store-Exclusive instruction succeeded then the
software has claimed the se ma p ho re . How ev er, if the Store-Exclusive instruction failed, another process
might have claimed the semaphore after the software performed the first step.
The Cortex-M4 includes an exclusive access monitor, that tags the fact that the processor has executed a Load-
Exclusive instruction. If the processor is part of a multiprocessor system, the system also globally tags the memory
locations addressed by exclusive accesses by each processor.
The processor removes its exclusive access tag if:
It executes a CLREX instruction
It executes a Store-Exclusive instruction, regardless of whethe r the write succeeds.
An exception occurs. This means that the processor can resolve semaphore conflicts between different
threads.
In a multiprocessor implementation:
Executing a CLREX instruction removes only the local exclusive access tag for the processor
Executing a Store-Exclusive instruction, or an exception, removes the local exclusive access tags, and all
global exclusive access tags for the processor.
For more information about the synchronization primitive instructions, see “LDREX and STREX” and “CLREX” .
12.4.2.8 Programming Hints for the Synchronization Primitives
ISO/IEC C cannot directly generate the exclusive access instructions. CMSIS provides intrinsic functions for
generation of these instructions:
The actual exclusive access instruction generated depends on the data type of the pointer passed to the intrinsic
function. For example, the following C code generates the required LDREXB operation:
__ldrex((volatile char *) 0xFF);
12.4.3 Exception Model
This section describes the exception model.
12.4.3.1 Exception States
Each exception is in one of the following states:
Inactive
The exception is not active and not pending.
Pending
The exception is waiting to be serviced by the processor.
Table 12-8. CMSIS Functions for Exclusive Access Instructions
Instruction CMSIS Function
LDREX uint32_t __LDREXW (uint32_t *addr)
LDREXH uint16_t __LDREXH (uin t16_t *addr)
LDREXB uint8_t __LDREXB (uint8_t *addr)
STREX uint32_t __STREXW (uint32_t value, uint32_t *addr)
STREXH uint32_t __STREXH (uint16_t value, uint16_t *addr)
STREXB uint32_t __STREXB (uint8_t value, uint8_t *addr)
CLREX void __CLREX (void)
77
SAM4S Series [DATASHEET]
Atmel-11100K-ATARM-SAM4S-Datasheet_09-Jun-15
An interrupt request from a peripheral or from software can change the state of the corresponding interrupt to
pending.
Active
An exception is being serviced by the processor but has not completed.
An exception handler can interrupt the execution of another exception handler. In this case, both exceptions are in
the active state.
Active and Pending
The exception is being serviced by the processor and there is a pending exception from the same source .
12.4.3.2 Exception Types
The exception types are:
Reset
Reset is invoked on power up or a warm reset. The exception mode l treats reset as a special form of exce ption.
When reset is asserted, the operation of the processor stops, potentially at any point in an instruction. When reset
is deasserted, execution restarts from the address provided by the reset entry in the vec tor table. Execution
restarts as privileged execution in Thread mode.
Non Maskable Interrupt (NMI)
A non maskable interrupt (NMI) can be signalled by a peripheral or triggered by software. This is the highest
priority exception other than reset. It is permanently ena bled and has a fixed priority of -2.
NMIs cannot be:
Masked or prevented from activation by any other exception.
Preempted by an y exception othe r than Rese t.
Hard Fault
A hard fault is an exception that occurs because of an error during exception processing, or because an exception
cannot be managed by any othe r except ion me chanism . Hard Faults have a fixed priority of -1 , meani ng they have
higher priority than any exception with configurable prior ity.
Memory Management Fault (MemManage)
A Memory Ma nagem ent Fau lt is an ex cept ion that o ccurs becaus e of a m emo ry pr otec tion re late d fau lt. The MPU
or the fixed memory protection constraints determ ines this fault, fo r both instru ction and data m emory transactions.
This fault is used to a bort instruction accesses to Execute Never (XN) memory regions, even if the MPU is
disabled.
Bus Fault
A Bus Fault is an exception that occurs because of a memory related fault for an instruction or data memory
transaction. This might be from an error detected on a bus in the memory system.
Usage Fault
A Usage Fault is an exception that occurs because of a fault related to an instruction execution. This includes:
An undefined instruction
An illegal unaligned access
An invalid state on instruction exec ut ion
An error on exception return.
The following can cause a Usage Fault when the core is configured to report them:
An unaligned address on word and halfword memory access
A division by zero.
SAM4S Series [DATASHEET]
Atmel-11100K-ATARM-SAM4S-Datasheet_09-Jun-15
78
SVCall
A superviso r call (SVC) is an exception that is triggered by the SVC in struction. In an OS environment, applications
can use SVC instructions to access OS kernel functions and device drivers.
PendSV
PendSV is an interrupt-driven request for system-level service. In an OS environment, use PendSV for context
switching when no other exception is active.
SysTick
A SysTick exception is an exception the system timer generates when it reaches zero. Software can also gener ate
a SysTick exception. In an OS environment, the processor can use this exception as system tick.
Interrupt (IRQ)
A interrupt, or IRQ, is an exception signalled by a peripheral, or generated by a software request. All interrupts are
asynchronous to instruction execution. In the system, peripherals use interrupts to communicate with the
processor.
Notes: 1. To simplify the software layer, the CMSIS only uses IRQ numbers and therefore uses negative values for exceptions oth er
than interrupts. The IPSR returns the Exception number, see “Interrupt Program Status Register” .
2. See “Vector Table” for more information
3. See “System Handler Priority Registers”
4. See “Interrupt Priority Registers”
5. Increasing in steps of 4.
For an asynchronous excep tion, other than re set, the processor can execute another instruction between wh en the
exception is triggered and when the processor enters the exception handler.
Privileged software can disable the exceptions that Table 12-9 shows as having configurable priority, see:
“System Handler Control and State Register”
“Interrupt Clear-enable Registers” .
Table 12-9. Properties of the Different Exception Types
Exception
Number(1) Irq Number(1) Exception Type Priority Vector Address
or Offset(2) Activation
1 – Reset -3, the highest 0x00000004 Asynchronous
2 -14 NMI -2 0x00000008 Asynchronous
3 -13 Hard fault -1 0x0000000C –
4 -12 Memory
management fault Configurable(3) 0x00000010 Synchronous
5 -11 Bus fault Configurable(3) 0x00000014 Synchro nous when precise,
asynchronous when imprecise
6 -10 Usage fault Configurable(3) 0x00000018 Synchronous
7–10 – – – Reserved –
11 -5 SVCall Configurable(3) 0x0000002C Synchronous
12–13 – – – Reserved –
14 -2 PendSV Configurable(3) 0x00000038 Asynchronous
15 -1 SysTick Configurable(3) 0x0000003C Asynchronous
16 and above 0 and above Interrupt (IRQ) Configurable(4) 0x00000040 and above(5) Asynchronous
79
SAM4S Series [DATASHEET]
Atmel-11100K-ATARM-SAM4S-Datasheet_09-Jun-15
For more information about hard faults, memory ma nagement faults, bus faults, and usage faults, see “Fault
Handling” .
12.4.3.3 Exception Handlers
The processor handles exceptions using:
Interrupt Service Routines (ISRs)
Interrupts IRQ0 to IRQ34 are the exceptions handled by ISRs.
Fault Handlers
Hard fault, memory management fault, usage fault, bus fault are fault exceptions handled by the fault
handlers.
System Handlers
NMI, PendSV, SVCall SysTick, and the fault exceptions are all system exceptions that are handled by
system handlers.
12.4.3.4 Vector Table
The vector table contains the reset value of the stack pointer, and the start addresses, also called exception
vectors, for all exception handlers. Figure 12-6 shows the order of the exception vectors in the ve ctor table. The
least-significant bit of each vector must be 1, indicating that the exception handler is Thumb code.
Figure 12-6. Vector Table
On system reset, the vector tab le is fixed at ad dre ss 0x00000 000. Privilege d software can write to the SCB_ VTOR
to relocate the vector table start address to a diffe rent memory location, in the range 0x0 0000080 to 0x3FFFFF80,
see “Vector Table Offset Register” .
Initial SP value
Reset
Hard fault
NMI
Memory management fault
Usage fault
Bus fault
0x0000
0x0004
0x0008
0x000C
0x0010
0x0014
0x0018
Reserved
SVCall
PendSV
Reserved for Debug
SysTick
IRQ0
Reserved
0x002C
0x0038
0x003C
0x0040
OffsetException number
2
3
4
5
6
11
12
14
15
16
18
13
7
10
1
Vector
.
.
.
8
9
IRQ1
IRQ2
0x0044
IRQ239
17 0x0048
0x004C
255
.
.
.
.
.
.
0x03FC
IRQ number
-14
-13
-12
-11
-10
-5
-2
-1
0
2
1
239
SAM4S Series [DATASHEET]
Atmel-11100K-ATARM-SAM4S-Datasheet_09-Jun-15
80
12.4.3.5 Exception Priorities
As Table 12-9 shows, all exceptions have an associated priority, with:
A lower priority value indicating a higher priority
Configurable priorities for all except ions except Reset, Hard fault and NMI.
If the software does not configure any priorities, then all exceptions with a configurable priority have a priority of 0.
For information about configuring exception priorities see “System Handler Priority Registers” , and “Interrupt
Priority Registers” .
Note: Configurable pri ority values are in the range 0–15. This means that the Reset, Hard fault, and NMI exceptions, with
fixed negative priority values, always have higher priority than any other exception.
For example, assigning a hig her prior ity value to IRQ[0] and a lower priority value to IRQ[1] means that IRQ[1] has
higher priority than IRQ[0]. If both IRQ[1] and IRQ[0] are asserted, IRQ[1] is processed before IRQ[0].
If multiple pending exceptio ns have the same priority, the pending excep tion with the lowest exception number
takes preced ence. For examp le, if both IRQ[0] and IRQ [1] are pending and have the same priority, then IRQ[0] is
processed before IRQ[1].
When the processor is executing an ex ception handler, the exception handler is preempted if a higher priority
exception occurs. If an exception occurs with the same priority as the except ion being handled, the handler is not
preempted, irrespective of the exception number. Howeve r, the status of the new interrupt changes to pending.
12.4.3.6 Interrupt Priority Grouping
To increase priority control in systems with interrupts, the NVIC supports priority grouping. This divides each
interrupt priority register entry into two fields:
An upper field that defines the group priority
A lower field that defines a subpriority within the group.
Only the group priority determines preemption of interrupt exceptions. When the processor is executing an
interrupt ex ception ha ndler, an other int errupt with t he same gr oup priori ty as the inte rrupt be ing handled does no t
preempt the handler.
If multiple pending interrupts have the same group priority, the subpriority field determines the order in which they
are processed. If multiple pending interrupts have the same group priority and subpriority, the interrupt with the
lowest IRQ number is processed first.
For information about splitting the interrupt priority fields into group priority and subpriority, see “Application
Interrupt and Reset Control Register” .
12.4.3.7 Exception Entry and Return
Descriptions of exception handling use the following terms:
Preemption
When the processor is executing an exception handler, an exception can preempt the exception handler if its
priority is higher than the priority of the ex ception being handled. See “Interrupt Priority Grouping” for more
information about preemption by an interrupt.
When one exception preempts another, the exceptions are ca lled nested exceptions. See “Exception Entry” more
information.
Return
This occurs when the exception handler is completed, and:
There is no pending exception with sufficient priority to be serviced
The completed exception handler was not hand ling a late-arriving exception.
The processor pops the stack and restores the processor state to the state it had before the interrupt occurred.
See “Exception Return” for more information.
81
SAM4S Series [DATASHEET]
Atmel-11100K-ATARM-SAM4S-Datasheet_09-Jun-15
Tail-chaining
This mechanism speeds up exception servicing. On completion of an exception handler, if there is a pending
exception that meets the requirements for exception entry, the stack pop is skipped and control transfers to the
new exception handler.
Late-arriving
This mechanism speeds up preemption. If a higher priority exception occu rs during state s aving for a previou s
exception, the processor switches to handle the higher pr iority exception and initiates the vector fetch for that
exception. State saving is not affe cted by late arrival because the state save d is the same for both exceptions.
Therefore the state saving continues uninterrupted. The processor can accept a late arriving exception until the
first instruction of the exception handler of the original exception enters the execute stage o f the processor. On
return from the exception handler of the late-arriving exception, the normal tail-chaining rules apply.
Exception Entry
An Exception entry occurs when there is a pending exception with sufficient priority and either the processor is in
Thread mode, or the new exception is of a higher priority than the exception being handled, in which case the new
exception preempts the original exception.
When one exception preempts another, the exceptions are nested.
Sufficient priority means that the exception has more priority than any limits set by the mask registers, see
“Exception Mask Registers” . An exception with less priority than this is pending but is not handled by the
processor.
When the processor takes a n exception, un less the except ion is a tail-chained or a late-arriving exception, the
processor pushes information onto the current stack. This operation is referred as stacking and the structure of
eight data words is referred to as stack frame.
SAM4S Series [DATASHEET]
Atmel-11100K-ATARM-SAM4S-Datasheet_09-Jun-15
82
Figure 12-7. Exception Stack Frame
Immediately after stacking, the stack pointer indicates the lowest address in the stack frame. The alignment of the
stack frame is controlled via the STKALIGN bit of the Configuration Control Register (CCR).
The stack frame includes the return address. This is the address of the next instruction in the interrupted program.
This value is restored to the PC at exception return so that the interrupted program resumes.
In parallel to the stacking operation, the processor performs a vector fetch that reads the exception handler sta rt
address from the vector table. When stacking is comple te, th e processor star ts executing the exce ption handler. At
the same time, the processor writes an EXC_RETURN value to the LR. This indicates which stack pointer
corresponds to the stack frame and what operation mode the processor was in before the entry occurred.
If no higher priority exception occurs during the exception entry, the processo r starts executing the exception
handler and automatically changes the status of the corresponding pending interrupt to active.
If another higher priority exception occurs during the exception entry, the pr ocessor starts executing the exception
handler for this exception and does not change the pending status of the earlier exception. This is the late arrival
case.
Exception Return
An Exception return occurs when the processor is in Handler mode an d executes one of the following instructions
to load the EXC_RETURN value into the PC:
An LDM or POP instruction that loads the PC
An LDR instruction with the PC as the destination.
A BX instruction using any register.
Pre-IRQ top of stack
xPSR
PC
LR
R12
R3
R2
R1
R0
{aligner}
IRQ top of stack
Decreasing
memory
address
xPSR
PC
LR
R12
R3
R2
R1
R0
S7
S6
S5
S4
S3
S2
S1
S0
S9
S8
FPSCR
S15
S14
S13
S12
S11
S10
{aligner}
IRQ top of stack
...
Exception frame with
floating-point storage
Exception frame without
floating-point storage
Pre-IRQ top of stack
...
83
SAM4S Series [DATASHEET]
Atmel-11100K-ATARM-SAM4S-Datasheet_09-Jun-15
EXC_RETURN is the value loaded into the LR on exception entry. The exception mechanism relies on this value
to detect when the processor has completed an exception handler. The lowest five bits of this value provide
information on the return stack and processor mode. Table 12-10 shows the EXC_RETURN values with a
description of the exception return behavior.
All EXC_RETURN values have bits[31:5] set to one. When this value is loaded into the PC, it indicates to the
processor that the exception is complete, and the processor initiates the appropriate exception return sequence.
12.4.3.8 Fault Handling
Faults are a subset of the exceptions, see “Exception Model” . The following generate a fault:
A bus error on:
An instruction fetch or vector table load
A data access
An internally-detected error such as an undefined instruction
An attempt to execute an instruction from a memory region marked as Non-Executable (XN).
A privilege violation or an attempt to access an unmanaged region causing an MPU fault.
Fault Types
Table 12-11 shows th e types of fault, the h andler used for the f ault, the corr esponding fau lt status registe r, and th e
register bit that indicates that the fault has occurred. See “Con figurable Fault Sta tus Register” for more information
about the fault status registers.
Table 12-10. Exception Return Behav io r
EXC_RETURN[31:0] Description
0xFFFFFFF1 Return to Handler mode, exception return uses non-floating-point state
from the MSP and execution uses MSP after return.
0xFFFFFFF9 Return to Thread mode, exception return uses non-floating-point state from
MSP and execution uses MSP after return.
0xFFFFFFFD Return to Thread mode, exception return uses non-floating-point state from
the PSP and execution uses PSP after return.
Table 12-11. Faults
Fault Handler Bit Name Fault Status Register
Bus error on a vector read Hard fault VECTTBL “Hard Fault Status Register”
Fault escalated to a hard fault FORCED
MPU or default memory map mismatch:
Memory
management
fault
––
on instruction access IACCVIOL(1)
“MMFSR: Memory Management Fault Status
Subregister”
on data access DACCVIOL(2)
during exception stacking MSTKERR
during exception unstacking MUNSTKERR
during lazy floating-point state preservation MLSPERR(3)
SAM4S Series [DATASHEET]
Atmel-11100K-ATARM-SAM4S-Datasheet_09-Jun-15
84
Notes: 1. Occurs on an access to an XN region even if the processor does not include an MPU or the MPU is disabled.
2. Attempt to use an instruction set other than the Thumb instruction set, or return to a non load/store-multiple instruction with
ICI continuation.
3. Only present in a Cortex-M4F device
Fault Escalation an d Ha rd Faul ts
All faults exceptions except for hard fault have configurable exception priority, see “System Handler Priority
Registers” . The software can disable the execution of the handlers for these faults, see “System Handler Control
and State Register” .
Usually, the exception prio rity, together with the values of the exception mask registers, determ ines whether the
processor enters the fault handler, and whether a fault handler can preempt another fault handler, as described in
“Exception Model” .
In some situations, a fault with conf igurable priority is treated as a hard fault. This is called priority escalation, and
the fault is described as escalated to hard fault. Escalation to hard fault occurs when:
A fault handler causes the same kind of fault as the one it is servicing. This escalation to hard fault occurs
because a fault handler cannot preempt itself; it must have the same priority as the current priority level.
A fault handler caus es a fa ult with the sam e or lower pr ior ity as the fault it is servicing. This is because the
handler for the new fault cannot preempt the currently executing fault handler.
An exception handler causes a fault for which the priority is the same as or lower than the currently
executing exception.
A fault occurs and the handler for that fault is not enabled.
If a bus fault occurs during a stack push when entering a bus fault handler, the bus fault does not escalate to a
hard fault. This means that if a corrupted stack causes a fault, the fault handler executes even though the stack
push for the handler failed. The fault handler operates but the stack contents are corrupted.
Note: Only Rese t and NMI can preempt the fixed priority hard fault. A hard fault can pree mp t an y exce p ti o n other than
Reset, NMI, or another hard fault.
Fault Status Registers and Fault Address Registers
The fault status registers indicate the cause of a fault. For bus faults and memory managem ent faults, the fault
address register indicates the address accessed by the operation that caused the fault, as shown in Table 12-12.
Bus error:
Bus fault
––
during exception stacking STKERR
“BFSR: Bus Fault Status Subregister”
during exception unstacking UNSTKERR
during instruction prefetch IBUSERR
during lazy floating-point state preservation LSPERR(3)
Precise data bus error PRECISERR
Imprecise data bus error IMPRECISERR
Attempt to access a coprocessor
Usage fault
NOCP
“UFSR: Usage Fault Status Subregister”
Undefined instruction UNDEFINSTR
Attempt to enter an invalid instruction set state INVSTATE
Invalid EXC_RETURN value INVPC
Illegal unaligned load or store UNALIGNED
Divide By 0 DIVBYZERO
Table 12-11. Faults (Continued)
Fault Handler Bit Name Fault Status Register
85
SAM4S Series [DATASHEET]
Atmel-11100K-ATARM-SAM4S-Datasheet_09-Jun-15
Lockup
The processor enters a lockup state if a hard fault occurs when executing the NMI or hard fault handlers. When the
processor is in lockup state, it does not execute an y instructions. The processor remains in lockup state until
either:
It is reset
An NMI occurs
It is halted by a debugger.
Note: If the lockup state occurs from the NMI handler, a subsequent NMI does not cause the processor to leave the lockup
state.
Table 12-12. Fault Status and Fault Add ress Registers
Handler Status Register
Name Address Register
Name Register Description
Hard fault SCB_HFSR – “Hard Fault Status Registe r”
Memory
management fault MMFSR SCB_MMFAR “MMF S R: Memory Management Fault Status Subregister”
“MemManage Fault Addre ss Reg ister”
Bus fault BFSR SCB_BFAR “BFSR: Bus Fault Status Subregister”
“Bus Fault Address Register ”
Usage fault UFSR – “UFSR: Usage Fault Status Subregister”
SAM4S Series [DATASHEET]
Atmel-11100K-ATARM-SAM4S-Datasheet_09-Jun-15
86
12.5 Power Management
The Cortex-M4 processor sleep modes reduce the power consumption:
Sleep mode stops the processor clock
Deep sleep mode stops the system clock and switches off the PLL and flash memory.
The SLEEPDEEP bit of the SCR selects which sleep mode is used; see “System Control Register” .
This section describes the mechanisms for entering sleep mode, and the conditions for waking up from sleep
mode.
12.5.1 Entering Sleep Mode
This section describes the mechanisms software can use to put the processor into sleep mode.
The system can generate spurious wakeup events, for example a debug operation wakes up the processor.
Therefore, the software mu st be able to put the processor back into sleep mode after such an event. A program
might have an idle loop to put the processor back to sleep mode.
12.5.1.1 Wait for Interrupt
The wait for interrupt instruction , WFI, causes immediate entry to sleep mo de. When the processor executes a
WFI instruction it stops executing instructions and enters sleep mode. See “WFI” for more information.
12.5.1.2 Wait for Event
The wait for event instruction, WFE, causes entry to sleep mode conditional on the value of an one-bit event
register. When the processor executes a WFE instruction, it checks this register:
If the register is 0, the processor stops executing instructions and enters sleep mode
If the register is 1, the processor clears the reg ister to 0 and continues executing instructions without
entering sleep mode.
See “WFE” for more information.
12.5.1.3 Sleep-on-exit
If the SLEEPONEXIT bit of the SCR is set to 1 when the processor completes the execution of an e xception
handler, it retu rns to Thread mode and im mediately enters sleep mo de. Use this mechanism in app lications that
only require the processor to run when an exception occurs.
12.5.2 Wakeup from Sleep Mode
The conditions for the processor to wake up depend on the mechanism that cause it to enter sleep mode.
12.5.2.1 Wakeup from WFI or Sleep-on-exit
Normally, the processor wakes up only when it detects an exception with sufficient priority to cause exception
entry.
Some embedded systems might have to execute system restore tasks after the processor wakes up, and before it
executes an interrupt handler. To achieve this, set the PRIMASK bit to 1 and the FAULTMASK bit to 0. If an
interrupt arrives that is enabled and has a higher priority than the current exception priority, the processor wakes
up but does not execute the interrupt handler until the processor sets PRIMASK to zero. For more information
about PRIMASK and FAULTMASK, see “Exception Mask Registers” .
12.5.2.2 Wakeup from WFE
The process or wake s up if:
It detects an exception with sufficient priority to cause an exception entr y
It detects an external event signal. See “External Event Input”
In a multiprocessor system, another processor in the system executes an SEV instruction.
87
SAM4S Series [DATASHEET]
Atmel-11100K-ATARM-SAM4S-Datasheet_09-Jun-15
In addition, if the SEVONPEND bit in the SCR is set to 1, any new pending interrupt triggers an event and wakes
up the processor, even if the interrupt is disabled or has insufficient priority to cause an exception entry. For more
information about the SCR, see “System Control Register” .
12.5.2.3 External Event Input
The processor provides an external event input signal. Peripherals can drive this signal, either to wake the
processor fro m WFE, or to set the internal WFE ev ent register to 1 to in dicate that the processo r must not enter
sleep mode on a later WFE instruction. See “Wait for Event” for more information.
12.5.3 Power Management Programming Hints
ISO/IEC C cannot directly gene rate the WF I and WF E inst r uctions. The CMSIS provides the following functions for
these instructions:
void __WFE(void) // Wait for Event
void __WFI(void) // Wait for Interrupt
SAM4S Series [DATASHEET]
Atmel-11100K-ATARM-SAM4S-Datasheet_09-Jun-15
88
12.6 Cortex-M4 Instruction Set
12.6.1 Instruction Set Summary
The processor implements a version of the Thumb instruction set. Table 12-13 lists the supported instructions.
Angle brackets, <>, enclose alternative forms of the operand
Braces, {}, enclose optional operands
The Operands column is not exhaustive
Op2 is a flexible second operand that can be either a register or a constant
Most instructions can use an optional condition code suffix.
For more information on the instructions and operands, see the instruction descriptions.
Table 12-13. Cortex-M4 Instructions
Mnemonic Operands Description Flags
ADC, ADCS {Rd,} Rn, Op2 Add with Carry N,Z,C,V
ADD, ADDS {Rd,} Rn, Op2 Add N,Z,C,V
ADD, ADDW {Rd,} Rn, #imm12 Add N,Z,C,V
ADR Rd, label Load PC-relative address –
AND, ANDS {Rd,} Rn, Op2 L ogical AND N,Z,C
ASR, ASRS Rd, Rm, <Rs|#n> Arithmetic Shift Right N,Z,C
B label Branch –
BFC Rd, #lsb, #width Bit Field Clear –
BFI Rd, Rn, #lsb, #width Bit Field Insert –
BIC, BICS {Rd,} Rn, Op2 Bit Clear N,Z,C
BKPT #imm Breakpoint –
BL label Branch with Link –
BLX Rm Branch indirect with Link –
BX Rm Branch indirect –
CBNZ Rn, lab el Compare and Branch if Non Zero –
CBZ Rn, label Compare and Branch if Zero –
CLREX – Clear Exclusive –
CLZ Rd, Rm Count leading zeros –
CMN Rn, Op2 Compare Negative N,Z,C,V
CMP Rn, Op2 Compare N,Z,C,V
CPSID i Change Processor St ate, Disable Interrupts –
CPSIE i Change Processor State, Enable Interrupts –
DMB – Data Memory Barrier –
DSB – Data Synchronization Barrier –
EOR, EORS {Rd,} Rn, Op2 Exclusive OR N,Z,C
ISB – Instruction Synchronization Barrier –
IT – If-Then condition block –
LDM Rn{!}, reglist Load Multiple registers, increment after –
89
SAM4S Series [DATASHEET]
Atmel-11100K-ATARM-SAM4S-Datasheet_09-Jun-15
LDMDB, LDMEA Rn{!}, reglist L oad Multiple registers, decrement before –
LDMFD, LDMI A Rn{!}, reglist Load Multiple registers, increment after –
LDR Rt, [Rn, #offset] Load Register with word –
LDRB, LDRBT Rt, [Rn, #offset] Load Register with byte –
LDRD Rt, Rt2, [Rn, #offset] Load Register with two bytes –
LDREX R t, [Rn, #offset] Load Register Exclusive –
LDREXB Rt, [Rn] Load Register Exclusive with byte –
LDREXH Rt, [Rn] Load Register Exclusive with halfword –
LDRH, LDRHT Rt, [Rn, #offset] Load Register with halfword –
LDRSB, DRSBT Rt, [Rn, #offset] Load Register with signed byte –
LDRSH, LDRSHT Rt, [Rn, #offset] Load Register with signed halfword –
LDRT Rt, [Rn, #offset] Load Register with word –
LSL, LSLS Rd, Rm, <Rs|#n> Logical Shift Left N,Z,C
LSR, LSRS Rd, Rm, <Rs|#n> Logical Shift Right N,Z,C
MLA Rd, Rn, Rm, Ra Multiply with Accumulate, 32-bit result –
MLS Rd, Rn, Rm, Ra Multiply and Subtract, 32-bit result –
MOV, MOVS Rd, Op 2 Move N,Z,C
MOVT Rd, #imm16 Move Top –
MOVW, MOV Rd, #imm16 Move 16-bit constant N,Z,C
MRS Rd, spec_reg Move from special register to general register –
MSR spec_reg, Rm Move from general register to special register N,Z,C,V
MUL, MULS {Rd ,} Rn, Rm Multiply, 32-bit result N,Z
MVN, MVNS Rd, Op2 Move NOT N,Z,C
NOP – No Operatio n –
ORN, ORNS {Rd,} Rn, Op2 Logical OR NOT N,Z,C
ORR, ORRS {Rd,} Rn, Op2 Logica l OR N,Z,C
PKHTB, PKHBT {Rd,} Rn, Rm, Op2 Pack Halfword –
POP reglist Pop registers from stack –
PUSH reglist Push registers onto stack –
QADD {Rd,} Rn, Rm Saturating double and Add Q
QADD16 {Rd,} Rn, Rm Saturating Add 16 –
QADD8 {Rd,} Rn, Rm Saturating Add 8 –
QASX {Rd,} Rn, Rm Saturating Add and Subtract with Exchange –
QDADD {Rd,} Rn, Rm Saturating Add Q
QDSUB {Rd,} Rn, Rm Saturati ng double and Subtract Q
QSAX {Rd ,} Rn, Rm Saturating Subtract and Add with Exchange –
QSUB {Rd,} Rn, Rm Saturating Subtract Q
Table 12-1 3. Cortex-M4 Instructions (Continued)
Mnemonic Operands Description Flags
SAM4S Series [DATASHEET]
Atmel-11100K-ATARM-SAM4S-Datasheet_09-Jun-15
90
QSUB16 {Rd,} Rn, Rm Saturating Subtract 16 –
QSUB8 {Rd,} Rn, Rm Saturating Subtract 8 –
RBIT Rd, Rn Reverse Bits –
REV Rd, Rn Reverse byte order in a word –
REV16 Rd, Rn Reverse byte order in each halfword –
REVSH Rd, Rn Reverse byte order in bottom halfword and sign extend –
ROR, RORS Rd, Rm, <Rs|#n> Rotate Right N,Z,C
RRX, RRXS Rd, Rm Rotate Right with Extend N,Z,C
RSB, RSBS {Rd,} Rn, Op2 Reverse Subtract N,Z,C,V
SADD16 {Rd,} Rn, Rm Signed Add 16 GE
SADD8 {Rd,} Rn, Rm Signed Add 8 and Subtract with Exchange GE
SASX {Rd,} Rn, Rm Signed Add GE
SBC, SBCS {Rd,} Rn, Op2 Subtract with Carry N,Z,C,V
SBFX Rd, Rn, #lsb, #width Signed Bit Field Extract –
SDIV {Rd,} Rn, Rm Signed Divide –
SEL {Rd,} Rn, Rm Select bytes –
SEV – Se nd Event –
SHADD16 {Rd,} Rn, Rm Signed Halving Add 16 –
SHADD8 {Rd,} Rn, Rm Signed Halving Add 8 –
SHASX {Rd,} Rn, Rm Signed Halving Add and Subtract with Exchange –
SHSAX {Rd,} Rn, Rm Signed Halving Subtract and Add with Exchange –
SHSUB16 {Rd ,} Rn, Rm Signed Halving Subtract 16 –
SHSUB8 {Rd,} Rn, Rm Signed Halving Subtract 8 –
SMLABB, SMLABT,
SMLATB, SMLATT Rd, Rn, Rm, Ra Signed Multiply Accumulate Long (halfwords) Q
SMLAD, SMLADX Rd, Rn, Rm, Ra Signed Multiply Accumulate Dual Q
SMLAL Rd Lo, RdHi, Rn, Rm Signed Multiply with Accumulate (32 × 32 + 64 ), 64-bit result –
SMLALBB, SMLALBT,
SMLALTB, SMLALTT RdLo, RdHi, Rn, Rm Signed Multiply Accumulate Long, halfwords –
SMLALD, SMLALDX RdLo, RdHi, Rn, Rm Signed Multi ply Accumulate Long Dual –
SMLAWB, SMLAWT Rd, Rn, Rm, Ra Signed Multi ply Accumulate, word by halfword Q
SMLSD Rd, Rn, Rm, Ra Signed Multiply Subtract Dual Q
SMLSLD RdLo, RdHi, Rn, Rm Signed Multiply Subtract Long Dual
SMMLA Rd, Rn, Rm, Ra Signed Most significant word Multiply Accumulate –
SMMLS, SMMLR Rd, Rn, Rm, Ra Signed Most significant word Multiply Subtract –
SMMUL, SMMULR {Rd,} Rn, Rm Signed Most significant word Multiply –
SMUAD {Rd,} Rn, Rm Signed dual Multiply Add Q
Table 12-1 3. Cortex-M4 Instructions (Continued)
Mnemonic Operands Description Flags
91
SAM4S Series [DATASHEET]
Atmel-11100K-ATARM-SAM4S-Datasheet_09-Jun-15
SMULBB, SMULBT
SMULTB, SMULTT {Rd,} Rn, Rm Signed Multiply (halfwords) –
SMULL R dLo, RdHi, Rn, Rm Signed Multiply (32 × 32), 64-bit result –
SMULWB, SMULWT {Rd,} Rn, Rm Signed Multiply word by hal fword –
SMUSD, SMUSDX {Rd,} Rn, Rm Signed dual Multiply Subtract –
SSAT Rd, #n, Rm {,shift #s} Signed Saturate Q
SSAT16 Rd, #n, Rm Signed Saturate 16 Q
SSAX {Rd,} Rn, Rm Signed Subtract and Add with Exchange GE
SSUB16 {Rd,} Rn, Rm Signed Subtract 16 –
SSUB8 {Rd,} Rn, Rm Signed Subtra ct 8 –
STM Rn{!}, reglist Store Multiple registers, increment after –
STMDB, STMEA Rn{!}, reglist Store Multiple registers, decrement before –
STMFD, STMIA Rn{!}, reglist Store Multiple registers, increment after –
STR Rt, [Rn, #offset] Store Register word –
STRB, STRBT Rt, [Rn, #offset] Store Register byte –
STRD Rt, Rt2, [Rn, #offset] Store Register two words –
STREX Rd, Rt, [Rn, #offset] Store Register Exclusive –
STREXB Rd, Rt, [Rn] Store Register Exclusive byte –
STREXH Rd, Rt, [Rn] Store Register Exclusive halfword –
STRH, STRHT Rt, [Rn, #offset] Store Register halfword –
STRT Rt, [Rn, #offset] Store Register word –
SUB, SUBS {Rd,} Rn, Op2 Subtract N,Z,C,V
SUB, SUBW {Rd,} Rn, #imm12 Subtract N,Z,C,V
SVC #imm Supervisor Call –
SXTAB {Rd,} Rn, Rm,{,ROR #} Extend 8 bits to 32 and add –
SXTAB16 {Rd,} Rn, Rm,{,ROR #} Dual extend 8 bits to 16 and add –
SXTAH {Rd,} Rn, Rm,{,ROR #} Extend 16 bits to 32 and add –
SXTB16 {Rd,} Rm {,ROR #n} Signed Extend Byte 16 –
SXTB {Rd,} Rm {,ROR #n} Sign extend a byte –
SXTH {Rd,} Rm {,ROR #n} Si gn extend a halfword –
TBB [Rn, Rm] Table Branch Byte –
TBH [Rn, Rm, LSL #1] Table Branch Halfword –
TEQ Rn, Op2 Test Equivalence N,Z,C
TST Rn, Op2 Test N,Z,C
UADD16 {Rd,} Rn, Rm Unsigned Add 16 GE
UADD8 {Rd,} Rn, Rm Unsigned Add 8 GE
USAX {Rd,} Rn, Rm Unsigned Subtract and Add with Exchange GE
Table 12-1 3. Cortex-M4 Instructions (Continued)
Mnemonic Operands Description Flags
SAM4S Series [DATASHEET]
Atmel-11100K-ATARM-SAM4S-Datasheet_09-Jun-15
92
UHADD16 {Rd ,} Rn, Rm Unsigned Halving Add 16 –
UHADD8 {Rd,} Rn, Rm Unsigned Halving Add 8 –
UHASX {Rd,} Rn, Rm Unsigned Halving Add and Subtract with Exchange –
UHSAX {Rd,} Rn, Rm Unsigned Halving Subtract and Add with Exchange –
UHSUB16 {Rd,} Rn, Rm Unsigned Halving Subtract 16 –
UHSUB8 {Rd,} Rn, Rm Unsigned Halving Subtract 8 –
UBFX Rd, Rn, #lsb, #width Unsigned Bit Field Extract –
UDIV {Rd,} Rn, Rm Unsigned Divide –
UMAAL RdLo, RdHi, Rn, Rm Unsigned Multiply Accumulate Accumulate Long (32 × 32 + 32 + 32),
64-bit result –
UMLAL RdLo, RdHi, Rn, Rm Unsigned Multiply with Accumulate (32 × 32 + 64), 64-bit result –
UMULL RdLo, RdHi, Rn, Rm Unsigned Multiply (32 × 32), 64-bit result –
UQADD16 {Rd,} Rn, Rm Unsigned Saturating Add 16 –
UQADD8 {Rd,} Rn, Rm Unsigned Saturating Add 8 –
UQASX {Rd,} Rn, Rm Unsigned Saturating Add and Subtract with Exchange –
UQSAX {Rd,} Rn, Rm Unsigned Saturating Subtract and Add with Exchange –
UQSUB16 {Rd,} Rn, Rm Unsigned Saturating Subtract 16 –
UQSUB8 {Rd,} Rn, Rm Unsigned Saturating Subtract 8 –
USAD8 {Rd,} Rn, Rm Unsigned Sum of Absolute Differences –
USADA8 {Rd,} Rn, Rm, Ra Unsigned Sum of Absolute Differences and Accumulate –
USAT Rd, #n, Rm {,shift #s} Unsigned Saturate Q
USAT16 Rd, #n, Rm Unsigned Saturate 16 Q
UASX {Rd,} Rn, Rm Unsigned Add and Subtract with Exchange GE
USUB16 {Rd,} Rn, Rm Unsigned Subtract 16 GE
USUB8 {Rd,} Rn, Rm Unsigned Subtract 8 GE
UXTAB {Rd,} Rn, Rm,{,ROR #} Rotate, extend 8 bits to 32 and Add –
UXTAB16 {Rd,} Rn, Rm,{,ROR #} Rotate, dual extend 8 bits to 16 and Add –
UXTAH {Rd,} Rn, Rm,{,ROR #} Rotate, unsigned extend and Add Halfword –
UXTB {Rd,} Rm {,ROR #n} Zero extend a byte –
UXTB16 {Rd,} Rm {,ROR #n} Unsigned Extend Byte 16 –
UXTH {Rd,} Rm {,ROR #n} Zero extend a halfword –
VABS.F32 Sd, Sm Floating-point Absolute –
VADD.F32 {Sd,} Sn, Sm Floating-point Add –
VCMP.F32 Sd, <Sm | #0.0> Compare two floating-point registers, or one floating-point register
and zero FPSCR
VCMPE.F32 Sd, <Sm | #0.0> Compare two floating-point registers, or one floating-point register
and zero with Invalid Operation check FPSCR
VCVT.S32.F32 Sd, Sm Convert between floating-point and integer –
Table 12-1 3. Cortex-M4 Instructions (Continued)
Mnemonic Operands Description Flags
93
SAM4S Series [DATASHEET]
Atmel-11100K-ATARM-SAM4S-Datasheet_09-Jun-15
12.6.2 CMSIS Functions
ISO/IEC cannot directly access some Cortex-M4 instructions. This section describes intrinsic functions that can
generate these instructions, provided by the CMIS an d that might be provided by a C compiler. If a C compiler
VCVT.S16.F32 Sd, Sd, #fbits Convert between floating-point and fixed point –
VCVTR.S32.F32 Sd, Sm Convert between floating-point and integer with rounding –
VCVT<B|H>.F32.F16 Sd, Sm Converts half-precision value to single-precision –
VCVTT<B|T>.F32.F16 Sd, Sm Converts single-precision register to half-precision –
VDIV.F32 {Sd,} Sn, Sm Floating-point Divide –
VFMA.F32 {Sd,} Sn, Sm Floating-point Fused Multiply Accumulate –
VFNMA.F32 {Sd,} Sn, Sm Floating-point Fused Negate Multiply Accumulate –
VFMS.F32 {Sd,} Sn, Sm Floating-point Fused Multiply Subtract –
VFNMS.F32 {Sd,} Sn, Sm Floating-point Fused Negate Multiply Subtract –
VLDM.F<32|64> Rn{!}, list Load Multiple extension registers –
VLDR.F<32|64> <Dd|Sd>, [Rn] Load an extension register from memory –
VLMA.F32 {Sd,} Sn, Sm Floating-point Multiply Accumulate –
VLMS.F32 {Sd,} Sn, Sm Floating-point Multiply Subtract –
VMOV.F32 Sd, #imm Floating-point Move immediate –
VMOV Sd, Sm Floating-point Move register –
VMOV Sn, Rt Copy ARM core register to single precision –
VMOV Sm, Sm1, Rt, Rt2 Copy 2 ARM core registers to 2 singl e precision –
VMOV Dd[x], Rt Copy ARM core register to scalar –
VMOV Rt, Dn[x] Copy scalar to ARM core register –
VMRS Rt, FPSCR Move FPSCR to ARM core register or APSR N,Z,C,V
VMSR FPSCR, Rt Move to FPSCR from ARM Core register FPSCR
VMUL.F32 {Sd,} Sn, Sm Floating-point Multiply –
VNEG.F32 Sd, Sm Floating-point Negate –
VNMLA.F32 Sd, Sn, Sm Floating-point Multiply and Add –
VNMLS.F32 Sd, Sn, Sm F loating-point Multiply and Subtract –
VNMUL {Sd,} Sn, Sm Floating-point Multiply –
VPOP list Pop extension registers –
VPUSH list Push extension registers –
VSQRT.F32 Sd, Sm Calcul ates floating-point Square Root –
VSTM Rn {!}, list Floating-point register Store Multiple –
VSTR.F<32|64> Sd, [Rn] Stores an extension register to memory –
VSUB.F<32|64> {Sd,} Sn, Sm Floating-point Subtract –
WFE – Wait For Event –
WFI – Wait For Interrupt –
Table 12-1 3. Cortex-M4 Instructions (Continued)
Mnemonic Operands Description Flags
SAM4S Series [DATASHEET]
Atmel-11100K-ATARM-SAM4S-Datasheet_09-Jun-15
94
does not support an appropriate intrinsic function , the user might have to use inline assembler to access some
instructions.
The CMSIS provides the following intrinsic functions to generate instructions that ISO/IEC C code cannot directly
access:
The CMSIS also provides a number of functions for accessing the special registers using MRS and MSR
instructions:
Table 12-14. CMSIS Functions to Generate some Cortex-M4 Instructions
Instruction CMSIS Function
CPSIE I void __enable_irq(void)
CPSID I void __disable_irq(void)
CPSIE F void __enable_fault_irq(void)
CPSID F void __disable_fault_irq(void)
ISB void __ISB(void)
DSB void __DSB(void)
DMB vo id __DMB(void)
REV uint32_t __REV(u int32_t int value)
REV16 uint32_t __REV16(uint32_t int value)
REVSH uint32_t __REVSH(uint32_t int value)
RBIT uint32_t __RBIT(uint32_t int value)
SEV void __SEV(void)
WFE void __WFE(void)
WFI void __WFI(void)
Table 12-15. CMSIS Intrinsic Functions to Access the Special Regis t ers
Special Register Access CMSIS Functio n
PRIMASK Read uint32_t __ge t_PRIMASK (void)
Write void __set_PRIMASK (uint32_t value)
FAULTMASK Read uint32_t __get_FAULTMASK (void
Write void __set_FAULTMASK (uint32_t value)
BASEPRI Read uint32_t __ge t_BASEPRI (void)
Write void __set_BASEPRI (uint32_t value)
CONTROL Read uint32_t __get_CONTROL (void)
Write void __set_CONTROL (uint32_t value)
MSP Read uint32_t __get_MSP (void)
Write void __set_MSP (uint32_t TopOfMainStack)
PSP Read uint32_t __get_PSP (void)
Write void __set_PSP (uint32_t TopOfProcStack)
95
SAM4S Series [DATASHEET]
Atmel-11100K-ATARM-SAM4S-Datasheet_09-Jun-15
12.6.3 Instruction Descriptions
12.6.3.1 Operands
An instruction operand can be an ARM register, a constant, or another instruction- specific p aramete r. Instru ctions
act on the operands and often store the result in a destination register. When there is a destination register in the
instruction, it is usually specified before the operands.
Operands in some instructions are flexible, can either be a register or a constant. See “Flexible Second Operand” .
12.6.3.2 Restrictions when Using PC or SP
Many instructions have restrictions on whether the Program Counter (PC) or Stack Pointer (SP) for the operands
or destination register can be used. See instruction descriptions for more information.
Note: Bit[0] of any address written to the PC with a BX, BLX, LDM, LDR, or POP instruction must be 1 for correct execution,
because this bit indicates the required instruction set, and the Cortex-M4 processor only supports Thumb instructions.
12.6.3.3 Flexible Second Operand
Many general data processing instructions have a flexible second operand. This is shown as Operand2 in the
descriptions of the syntax of each instruction.
Operand2 can be a:
“Constant”
“Register with Optional Shift”
Constant
Specify an Operand2 constant in the form:
#constant
where constant can be:
Any constant that can be produced by shifting an 8-bit value left by any number of bits within a 32-bit word
Any constant of the form 0x00XY00XY
Any constant of the form 0xXY00XY00
Any constant of the form 0xXYXYXYXY.
Note: In th e constants shown above, X and Y are hexadecimal digits.
In addition, in a small number of instructions, constant can ta ke a wider range of values. These are described in
the individual instruction descriptions.
When an Operand2 constant is used with the instructions MOVS, MVNS, ANDS, ORRS, ORNS, EORS, BICS,
TEQ or TST, the carry flag is updated to bit[31] of the constant, if the constant is greater than 255 and can be
produced by shifting an 8-bit value. These instructions do not affect the carry flag if Operand2 is any other
constant.
Instruction Substitution
The assembler might be able to produce an equivalent instruction in cases where the user specifies a constant
that is not permitted. For example, an assembler might assemble th e instruction CMP
Rd
, #0xFFFFFFFE as the
equivalent instruction CMN Rd, #0x2.
Register with Optional Shift
Specify an Operand2 register in the form:
Rm {, shift}
where:
Rm is the register holding the data for the second operand.
shift is an optional shift to be applied to Rm. It can be one of:
SAM4S Series [DATASHEET]
Atmel-11100K-ATARM-SAM4S-Datasheet_09-Jun-15
96
ASR #narithmetic shift right n bits, 1 ≤ n ≤ 32.
LSL #nlogical shift left n bits, 1 ≤ n ≤ 31.
LSR #nlogical shift right n bits, 1 ≤ n ≤ 32.
ROR #nrotate right n bits, 1 ≤ n ≤ 31.
RRX rotate right one bit, with extend.
- if omitted, no shift occurs, equivalent to LSL #0.
If the user omits the shift, or specifies LSL #0, the instruction uses the value in Rm.
If the user specifies a shift, the shift is applied to the value in Rm, and the re sulting 32-bit value is used by the
instruction. However, the contents in the register Rm remains unch anged. Specifying a register with shift also
updates the carry flag when used with certain instructions. For information on the shift operations and how they
affect the carry flag, see “Flexible Second Operand” .
12.6.3.4 Shift Operations
Register shift operations move the bits in a register left or right by a specified numb er of bits, th e shift length.
Register shift can be performed:
Directly by the instructions ASR, LSR, LSL, ROR, and RRX, and the re sult is written to a destination register
During the calculation of Operand2 by the instructions that specify the second operand as a register with
shift. See “Flexible Second Operand” . The result is used by the instruction.
The permitted shift lengths depend on the shift type and the instruction. If the shift length is 0, no shift occurs.
Register shift operations update the carry flag except when the specified shift length is 0. The following
subsections describe the variou s shift operations and how they affect the carry flag. In these descriptions, Rm is
the register containing the value to be shifted, and n is the shift length.
ASR
Arithmetic shift right by n bits moves the left-hand 32-n bits of the register, Rm, to the right by n places, into the
right-hand 32-n bits of the result. And it copies the original bit[31] of the register into the left-hand n bits of the
result. See Figure 12-8.
The ASR #n operation can be used to divide the value in the register Rm by 2n, with the result being rounded
towards negative-infinity.
When the instruction is ASRS or wh en ASR #n is used in Operand2 with the instructions MOVS, MVNS, ANDS,
ORRS, ORNS, EORS, BICS, TEQ or TST, the carry flag is updated to the last bit shifted out, bit[n-1] , of the
register Rm.
If n is 32 or more, then all the bits in the result are set to the value of bit[31] of Rm.
If n is 32 or more and the carry flag is updated, it is updated to the value of bit[31] of Rm.
Figure 12-8. ASR #3
LSR
Logical shift right by n bits moves the left-hand 32-n bits of the register Rm, to the right by n places, into the right-
hand 32-n bits of the result. And it sets the left-hand n bits of the result to 0. See Figure 12-9.
&DUU\
)ODJ

97
SAM4S Series [DATASHEET]
Atmel-11100K-ATARM-SAM4S-Datasheet_09-Jun-15
The LSR #n operation can be used to divide the value in the register Rm by 2n, if the value is regarded as an
unsigned integer.
When the instruction is LSRS or when LSR #n is used in Operand2 with the instructions MOVS, MVNS, ANDS,
ORRS, ORNS, EORS, BICS, TEQ or TST, the carry flag is updated to the last bit shifted out, bit[n-1], of the
register Rm.
If n is 32 or more, then all the bits in the result are cleared to 0.
If n is 33 or more and the carry flag is updated, it is updated to 0.
Figure 12-9. LSR #3
LSL
Logical shift left by n bits moves the right-hand 32- n bits of the register Rm, to the left by n places, into the left-hand
32-n bits of the result; and it sets the right-hand n bits of the result to 0. See Figure 12-10.
The LSL #n operation can be used to multiply the value in the register Rm by 2n, if the value is regarde d as an
unsigned integer or a two’s complement signed integer. Overflow can occur without warning.
When the instruction is LSLS or when LSL #n, with non-zero n, is used in Operand2 with the instructions MOVS,
MVNS, ANDS, ORRS, ORNS, EORS, BICS, TEQ or TST, the carry flag is updated to the last bit shifted out, bit[32-
n], of the register Rm. These instructions do not affect the carry flag when used with LSL #0.
If n is 32 or more, then all the bits in the result are cleared to 0.
If n is 33 or more and the carry flag is updated, it is updated to 0.
Figure 12-10. LSL #3
ROR
Rotate right by n bits moves the left-hand 32-n bits of the register Rm, to the right by n places, into the right-hand
32-n bits of the result; and it moves the right-hand n bits of the register into the left-hand n bits of the result. See
Figure 12-11.
When the instruction is RORS or when ROR #n is used in Operand2 with the instructions MOVS, MVNS, ANDS,
ORRS, ORNS, EORS, BICS, TEQ or TST, the carry flag is updated to the last bit rotation, bit[n-1], of the register
Rm.
If n is 32, then the value of the re sult is same as the value in Rm, and if th e carry flag is updated, it is updated
to bit[31] of Rm.
ROR with shift length, n, more than 32 is the same as ROR with shift length n-32.
&DUU\
)ODJ


&DUU\
)ODJ
SAM4S Series [DATASHEET]
Atmel-11100K-ATARM-SAM4S-Datasheet_09-Jun-15
98
Figure 12-11. ROR #3
RRX
Rotate right with extend moves the bits of the register Rm to the r ight by one bit; an d it copies the carry fla g into
bit[31] of the result. See Figure 12-12.
When the instruction is RRXS or when RRX is used in Operand2 with the instruct ions MOVS, MVNS, ANDS,
ORRS, ORNS, EORS, BICS, TEQ or TST, the carry flag is updated to bit[0] of the register Rm.
Figure 12-12. RRX
12.6.3.5 Address Alignment
An aligned access is an operation where a word-aligned address is used for a word, dual word, or multiple word
access, or where a halfword-aligned address is used for a halfword access. Byte accesses are always aligned.
The Cortex-M4 processor supports unaligned access only for the following instructions:
LDR, LDRT
LDRH, LDRHT
LDRSH, LDRSHT
STR, STRT
STRH, STRHT
All other load and store instructions gene rate a usage fault exception if they perform an unaligned access, and
therefore their accesses must be address-aligned. For more information about usage faults, see “Fault Handling” .
Unaligned accesses are usually s lower than aligned accesses. In addition, some memory regions might not
support unaligned accesses. Therefore, ARM re commends that prog rammers ensure that accesses are aligned.
To avoid accidental gene ration of unalig ned accesses, use the UNALIGN_TRP bit in the Configuration a nd Control
Register to trap all unalig ne d accesses, see “Configuration and Control Register” .
12.6.3.6 PC-relative Expressions
A PC-relative expression or label is a sym bol that represents the add ress of an instruction or literal data. It is
represented in the instruction as the PC value plus or minus a numeric offset. The assembler calculates the
required offset from the label and the address of the current instruction. If the offset is too big, the assembler
produces an error.
For B, BL, CBNZ, and CBZ instructions, the value of the PC is the address of the current instruction plus 4
bytes.
&DUU\
)ODJ


&DUU\
)ODJ

99
SAM4S Series [DATASHEET]
Atmel-11100K-ATARM-SAM4S-Datasheet_09-Jun-15
For all other instructions that use labels, the value of the PC is the address of the current instruction plus 4
bytes, with bit[1] of the result cleared to 0 to make it word-aligned.
Your assembler might permit other syntaxes for PC-relative expressions, such as a label plus or minus a
number, or an expression of the form [PC, #number].
12.6.3.7 Conditional Execution
Most data proc essing instructions can optionally upda te the condition flags in the Application Program Status
Register (APSR) according to the result of the operation, see “Application Program Status Register” . Some
instructions update all flags, and some only update a subset. If a flag is not updated, the original value is
preserved. See the instruction descriptions for the flags they affect.
An instruction can be exe cu ted con d ition a lly, ba se d on the condition flags set in another instruction, either:
Immediately after the instruction that updated the flags
After any number of intervening instructions that have not updated the flags.
Conditional execution is available by using conditional branches or by adding condition code suffixes to
instructions. See Table 12-16 for a list of the suffixes to add to instructions to make them conditional instructions.
The condition code suffix enables the processor to test a condition based on the flags. If the condition test of a
conditional instruction fails, the instruction:
Does not execute
Does not write any value to its destination register
Does not affect any of the flags
Does not generate any exception.
Conditional instructions, except for conditional branches, must be inside an If-Then instruction block. See “IT” for
more information and restrictions when using the IT instruction. Depending on the vendor, the assembler might
automatically insert an IT instruction if there are conditional instructions outside the IT block.
The CBZ and CBNZ instructions are used to compare th e value of a register again st zero and branch on the re sult.
This section describes:
“Condition Flags”
“Condition Code Suffixes” .
Condition Flags
The APSR contains the following condition flags:
N Set to 1 when the result of the op e ra tion was negative, cleared to 0 otherwise.
Z Set to 1 when the result of the operation was zero, cleared to 0 otherwise.
C Set to 1 when the operation resulted in a carry, cleared to 0 otherwise.
V Set to 1 when the operation caused overflow, cleared to 0 otherwise.
For more information about the APSR, see “Program Status Register” .
A carry occurs:
If the result of an addition is greater than or equal to 232
If the result of a subtraction is positive or zero
As the result of an inline barrel shifter operation in a move or logical instruction.
An overflow occurs when the sign of the result, in bit[31], does not match the sign of the result, had the operation
been performed at infinite precision, for example:
If adding two negative values results in a positive value
If adding two positive values results in a negative value
If subtracting a positive value from a negative value generates a positive value
SAM4S Series [DATASHEET]
Atmel-11100K-ATARM-SAM4S-Datasheet_09-Jun-15
100
If subtracting a negative value from a positive value generates a negative value.
The Compare operations are identical to subtracting, for CMP, or adding, for CMN, except that the result is
discarded. See the instruction descriptions for more information.
Note: Most instructions update the status flags only if the S suffix is specified. See th e instruction descriptions for more
information.
Condition Code Suffixes
The instructions that can be conditional have an optional condition code, shown in syntax descriptions as {cond}.
Conditional execution req uires a preceding IT instruction. An instruction with a conditio n code is only executed if
the condition code flags in the APSR meet the specified condition. Table 12-16 shows the condition codes to use.
A conditional execution can be used with the IT instruction to reduce the number of branch instructions in code.
Table 12-16 also shows the relationship between condition code suffixes and the N, Z, C, and V flags.
Absolute Value
The example below shows the use of a conditional instru ction to find the absolute value of a number. R0 =
ABS(R1). MOVS R0, R1 ; R0 = R1, setting flags
IT MI ; IT instruction for the negative condition
RSBMI R0, R1, #0 ; If negative, R0 = -R1
Compare and Up da te Value
The example below shows the use of conditional instructions to update the value of R4 if the signed values R0 is
greater than R1 and R2 is greater than R3.
CMP R0, R1 ; Compare R0 and R1, setting flags
ITT GT ; IT instruction for the two GT conditions
CMPGT R2, R3 ; If 'greater than', compare R2 and R3, setting flags
MOVGT R4, R5 ; If still 'greater than', do R4 = R5
Table 12-16. Condition Code Suffixes
Suffix Flags Meaning
EQ Z = 1 Equal
NE Z = 0 Not equal
CS or HS C = 1 Higher or same, unsigned ≥
CC or LO C = 0 Lower, unsigned <
MI N = 1 Negative
PL N = 0 Positive or zero
VS V = 1 Overflow
VC V = 0 No overflow
HI C = 1 and Z = 0 Higher, unsigned >
LS C = 0 or Z = 1 Lower or same, unsigned ≤
GE N = V Greater than or equal, signed ≥
LT N != V Less than, signed <
GT Z = 0 and N = V Greater than, signed >
LE Z = 1 and N != V Less than or equal, signed ≤
AL Can have any value Always. This is the default when no suffix is specified.
101
SAM4S Series [DATASHEET]
Atmel-11100K-ATARM-SAM4S-Datasheet_09-Jun-15
12.6.3.8 Instruction Width Selection
There are many instructions that can generate either a 16-bit encoding or a 32-bit encoding depending on the
operands and destination register specified. For some of these instructions, the user can force a specific
instruction size by using an instruction width suffix. The .W suffix forces a 32-bit instruction encoding. The .N suffix
forces a 16-bit instruction encoding.
If the user specifie s an instruction width suffix and th e assembler cannot generate an instruction encoding of the
requested width, it generates an error.
Note: In some cases, it might be necessary to specify the .W suffix, for example if the operand is the label of an instruction or
literal data, as in the case of branch instructions. This is because the assembler might not automatically generate the
right size encoding.
To use an instruction width suffix, place it im mediately after the instruction m nemonic and condition cod e, if any.
The example below shows instructions with the instruction width suffix.
BCS.W label ; creates a 32-bit instruction even for a short
; branch
ADDS.W R0, R0, R1 ; creates a 32-bit instruction even though the same
; operation can be done by a 16-bit instruction
SAM4S Series [DATASHEET]
Atmel-11100K-ATARM-SAM4S-Datasheet_09-Jun-15
102
12.6.4 Memory Access Instructions
The table below shows the memory access instructions.
Table 12-17. Memory Access Instructions
Mnemonic Description
ADR Load PC-relative address
CLREX Clear Exclusive
LDM{mode} Load Multiple registers
LDR{type} Load Register using immediate offset
LDR{type} Load Register using register offset
LDR{type}T Load Register with unprivileged access
LDR Load Register usin g PC-relative address
LDRD Load Register Dua l
LDREX{type} Load Register Exclusive
POP Pop registers from stack
PUSH Push registers onto stack
STM{mode} Store Multiple regi st ers
STR{type} Store Register using immediate offset
STR{type} Store Register using register offset
STR{type}T Store Register with unprivileged access
STREX{type} Store Register Exclusive
103
SAM4S Series [DATASHEET]
Atmel-11100K-ATARM-SAM4S-Datasheet_09-Jun-15
12.6.4.1 ADR
Load PC-relative address.
Syntax ADR{cond} Rd, label
where:
cond is an optional condition code, see “Conditional Execution” .
Rd is the destinatio n register.
label is a PC-relative ex pr es sio n. See “PC-relative Expressions” .
Operation
ADR determines the address by adding an immediate value to the PC, and writes the result to the destination
register.
ADR produces position-independent code, because the address is PC-relative.
If ADR is used to generate a targ et address for a BX or BLX in struction, ensu re that bit[0 ] of the addre ss gene rated
is set to 1 for correct execution.
Values of label must be within the range of −4095 to +4095 from the address in the PC.
Note: The user might have to use the .W suffix to get the maximum offset range or to generate addresses that are not word-
aligned. See “Instruction Width Selection” .
Restrictions
Rd must not be SP and must not be PC.
Condition Flags
This instruction does not change the flags.
Examples
ADR R1, TextMessage ; Write address value of a location labelled as
; TextMessage to R1
SAM4S Series [DATASHEET]
Atmel-11100K-ATARM-SAM4S-Datasheet_09-Jun-15
104
12.6.4.2 LDR and STR, Immediate Offset
Load and Store with imm edi at e of fse t, pr e- in de xe d imm ediate offset, or post-indexed immediate offset.
Syntax op{type}{cond} Rt, [Rn {, #offset}] ; immediate offset
op{type}{cond} Rt, [Rn, #offset]! ; pre-indexed
op{type}{cond} Rt, [Rn], #offset ; post-indexed
opD{cond} Rt, Rt2, [Rn {, #offset}] ; immediate offset, two words
opD{cond} Rt, Rt2, [Rn, #offset]! ; pre-indexed, two words
opD{cond} Rt, Rt2, [Rn], #offset ; post-indexed, two words
where:
op is one of:
LDR Load Register.
STR Store Register.
type is one of:
B unsigned byte, zero extend to 32 bits on loads.
SB signed byte, sign extend to 32 bits (LDR only).
H unsigned halfword, zero extend to 32 bits on loads.
SH signed halfword, sign extend to 32 bits (LDR only).
- omit, for word.
cond is an optional condition code, see “Conditional Execution” .
Rt is the register to lo a d or stor e.
Rn is the register on which the memory address is based.
offset is an offset from Rn. If offset is omitted, the address is the contents of Rn.
Rt2 is the additional register to load or stor e for two-word operations.
Operation
LDR instructions load one or two registers with a value from memory.
STR instructions store one or two register values to memory.
Load and store instructions with immediate offset can use the following addressing modes:
Offset Addressing
The offset value is ad ded to or subtracted from the address o btained from the r egister Rn. The result is used as the
address for the memory access. The register Rn is unaltered. The assembly languag e syntax for this mode is:
[Rn, #offset]
105
SAM4S Series [DATASHEET]
Atmel-11100K-ATARM-SAM4S-Datasheet_09-Jun-15
Pre-indexed Addressing
The offset value is ad ded to or subtracted from the address o btained from the r egister Rn. The result is used as the
address for the me mory access and written b ack into the re gister Rn. The assembly language syn tax for this mode
is: [Rn, #offset]!
Post-indexed Addressing
The address obtained from the register Rn is used as the address for the memory access. The offset value is
added to or subtracted from the address, and written back into the register Rn. The assembly language syntax for
this mode is:
[Rn], #offset
The value to load or store can be a byte, halfword, word, or two words. Bytes and halfwords can either be signed
or unsigned. See “Address Alignment” .
The table below shows the ranges of offset for immediate, pre-indexed and post-indexed forms.
Restrictions
For load instructions:
Rt can be SP or PC for word loads only
Rt must be different from Rt2 for two-word loads
Rn must be different from Rt and Rt2 in the pre-indexed or post-indexed forms.
When Rt is PC in a word load instruction:
Bit[0] of the loaded value must be 1 for correct execution
A branch occurs to the address created by changing bit[0] of the loaded value to 0
If the instruction is conditional, it must be the last instruction in the IT block.
For store instructions:
Rt can be SP for word stores only
Rt must not be PC
Rn must not be PC
Rn must be different from Rt and Rt2 in the pre-indexed or post-indexed forms.
Condition Flags
These instructions do not change the flags.
Table 12-18. Offset Ranges
Instruction Type Immediate Offset Pre-indexed Post-indexed
Word, halfword, signed
halfword, byte, or signed byte -255 to 4095 -255 to 255 -255 to 255
Two words multiple of 4 in the
range -1020 to 1020 multiple of 4 in the
range -1020 to 1020 mul ti ple of 4 in the
range -1020 to 1020
SAM4S Series [DATASHEET]
Atmel-11100K-ATARM-SAM4S-Datasheet_09-Jun-15
106
Examples
LDR R8, [R10] ; Loads R8 from the address in R10.
LDRNE R2, [R5, #960]! ; Loads (conditionally) R2 from a word
; 960 bytes above the address in R5, and
; increments R5 by 960.
STR R2, [R9,#const-struc] ; const-struc is an expression evaluating
; to a constant in the range 0-4095.
STRH R3, [R4], #4 ; Store R3 as halfword data into address in
; R4, then increment R4 by 4
LDRD R8, R9, [R3, #0x20] ; Load R8 from a word 32 bytes above the
; address in R3, and load R9 from a word 36
; bytes above the address in R3
STRD R0, R1, [R8], #-16 ; Store R0 to address in R8, and store R1 to
; a word 4 bytes above the address in R8,
; and then decrement R8 by 16.
12.6.4.3 LDR and STR, Register Offset
Load and Store with register offset.
Syntax op{type}{cond} Rt, [Rn, Rm {, LSL #n}]
where:
op is one of:
LDR Load Register.
STR Store Register.
type is one of:
B unsigned byte, zero extend to 32 bits on loads.
SB signed byte, sign extend to 32 bits (LDR only).
H unsigned halfword, zero extend to 32 bits on loads.
SH signed halfword, sign extend to 32 bits (LDR only).
- omit, for word.
cond is an optional condition code, see “Conditional Execution” .
Rt is the register to lo a d or stor e.
Rn is the register on which the memory address is based.
Rm is a register containing a value to be used as the offset.
LSL #nis an optional shift, with n in the range 0 to 3 .
Operation
LDR instructions load a register with a value from me m or y.
STR instructions store a register value into memory.
The memory address to load from or store to is at an offset from the register Rn. The offset is specified by the
register Rm and can be shifted left by up to 3 bits using LSL.
The value to load or store can be a byte, halfword, or word. For load instructions, bytes and halfwords can either
be signed or unsigned. See “Address Alignment” .
Restrictions
In these instructions:
Rn must not be PC
107
SAM4S Series [DATASHEET]
Atmel-11100K-ATARM-SAM4S-Datasheet_09-Jun-15
Rm must not be SP and must not be PC
Rt can be SP only for word loads and word stores
Rt can be PC only for word loads.
When Rt is PC in a word load instruction:
Bit[0] of the loaded value must be 1 for correct execution, and a branch occurs to this halfword-aligned
address
If the instruction is conditional, it must be the last instruction in the IT block.
Condition Flags
These instructions do not change the flags.
Examples
STR R0, [R5, R1] ; Store value of R0 into an address equal to
; sum of R5 and R1
LDRSB R0, [R5, R1, LSL #1] ; Read byte value from an address equal to
; sum of R5 and two times R1, sign extended it
; to a word value and put it in R0
STR R0, [R1, R2, LSL #2] ; Stores R0 to an address equal to sum of R1
; and four times R2
SAM4S Series [DATASHEET]
Atmel-11100K-ATARM-SAM4S-Datasheet_09-Jun-15
108
12.6.4.4 LDR and STR, Unprivileged
Load and Store with unprivileged access.
Syntax op{type}T{cond} Rt, [Rn {, #offset}] ; immediate offset
where:
op is one of:
LDR Load Register.
STR Store Register.
type is one of:
B unsigned byte, zero extend to 32 bits on loads.
SB signed byte, sign extend to 32 bits (LDR only).
H unsigned halfword, zero extend to 32 bits on loads.
SH signed halfword, sign extend to 32 bits (LDR only).
- omit, for word.
cond is an optional condition code, see “Conditional Execution” .
Rt is the register to lo a d or stor e.
Rn is the register on which the memory address is based.
offset is an offset from Rn and can be 0 to 255.
If offset is omitted, the address is the value in Rn.
Operation
These load and store instructions perform the same function as the memory access instructions with im mediate
offset, see “LDR and STR, Immediate Offset” . The difference is that these instructions have only unprivileged
access even when used in privileged software.
When used in unprivileged so ftware, these instruction s behave in exactly the same way as normal memory access
instructions with immediate offset.
Restrictions
In these instructions:
Rn must not be PC
Rt must not be SP and must not be PC.
Condition Flags
These instructions do not change the flags.
Examples
STRBTEQ R4, [R7] ; Conditionally store least significant byte in
; R4 to an address in R7, with unprivileged access
LDRHT R2, [R2, #8] ; Load halfword value from an address equal to
; sum of R2 and 8 into R2, with unprivileged access
109
SAM4S Series [DATASHEET]
Atmel-11100K-ATARM-SAM4S-Datasheet_09-Jun-15
12.6.4.5 LDR, PC-relative
Load register from memory.
Syntax LDR{type}{cond} Rt, label
LDRD{cond} Rt, Rt2, label ; Load two words
where:
type is one of:
B unsigned byte, zero extend to 32 bits.
SB signed byte, sign extend to 32 bits.
H unsigned halfword, zero extend to 32 bits.
SH signed halfword, sign extend to 32 bits.
- omit, for word.
cond is an optional condition code, see “Conditional Execution” .
Rt is the register to lo a d or stor e.
Rt2 is the second register to load or store.
label is a PC-relative ex pr es sio n. See “PC-relative Expressions” .
Operation
LDR loads a register with a value from a PC-relative me mory address. The mem ory address is sp ecified by a label
or by an offset from the PC.
The value to load or store can be a byte, halfword, or word. For load instructions, bytes and halfwords can either
be signed or unsigned. See “Address Alignment” .
label must be within a limited range of the current instruction. The table below shows the possible offsets between
label and the PC.
The user might have to use the .W suffix to get the maximum offset range. See “Instruction Width Selection” .
Restrictions
In these instructions:
Rt can be SP or PC only for word loads
Rt2 must not be SP and must not be PC
Rt must be different from Rt2.
Table 12-19. Offset Ranges
Instruction Type Offset Range
Word, halfword, signed halfword, byte, signed byte -4095 to 4095
Two words -1020 to 1020
SAM4S Series [DATASHEET]
Atmel-11100K-ATARM-SAM4S-Datasheet_09-Jun-15
110
When Rt is PC in a word load instruction:
Bit[0] of the loaded value must be 1 for correct execution, and a branch occurs to this halfword-aligned
address
If the instruction is conditional, it must be the last instruction in the IT block.
Condition Flags
These instructions do not change the flags.
Examples
LDR R0, LookUpTable ; Load R0 with a word of data from an address
; labelled as LookUpTable
LDRSB R7, localdata ; Load a byte value from an address labelled
; as localdata, sign extend it to a word
; value, and put it in R7
12.6.4.6 LDM and STM
Load and Store Multiple registers.
Syntax op{addr_mode}{cond} Rn{!}, reglist
where:
op is one of:
LDM Load Multiple registers.
STM Store Multiple registers.
addr_mode is any one of the followi ng :
IA Increment address After each access. This is the default.
DB Decrement address Before each access.
cond is an optional condition code, see “Conditional Execution” .
Rn is the register on which the memory addresses are based.
! is an optional writeback suffix.
If ! is present, the final address, that is loa ded from or stored to, is written back into Rn.
reglist is a list of one or more registers to be loaded or stored, enclosed in braces. It
can contain register ranges. It must be comma separated if it contain s more
than one register or register range, see “Examples” .
LDM and LDMFD are synonyms for LDMIA. LDMFD refers to its use for popping data from Full Descending
stacks.
LDMEA is a synonym for LDMDB, and refers to its use for popping data from Empty Ascending stacks.
STM and STMEA are synonyms for STMIA. STMEA refers to its use for pushing data onto Empty Ascending
stacks.
STMFD is s synonym for STMDB, and refers to its use for pushing data onto Full Descending stacks
Operation
LDM instructions load the registers in reglist with word values from memory addresses based on Rn.
STM instructions store the word values in the registers in reglist to memory addresses based on Rn.
For LDM, LDM IA, LDMFD, STM, STMIA, and STME A the m emory add resses use d for the acce sses are at 4-byte
intervals rang ing fro m Rn to Rn + 4 * (n-1), where n is the number of register s in reglist. The accesses happens in
order of increasing register numbers, with the lowest numbered register using the lowest memory address and the
111
SAM4S Series [DATASHEET]
Atmel-11100K-ATARM-SAM4S-Datasheet_09-Jun-15
highest number register using the highest memory address. If the writeback suffix is specified, the value of Rn + 4
* (n-1) is written back to Rn.
For LDMDB, LDMEA, STMDB, and STMFD the memory addresses used for the accesses are at 4-byte intervals
ranging from Rn to Rn - 4 * (n-1), where n is the nu mber of registers in reglist. The accesses ha ppen in order of
decreasing register numbers, with the highest nu mbered register using the highest memory address and the
lowest number register using the lowest memory address. If the writeback suffix is specified, the value of Rn - 4 *
(n-1) is written back to Rn.
The PUSH and POP instructions can be expressed in this form. See “PUSH and POP” for details.
Restrictions
In these instructions:
Rn must not be PC
reglist must not contain SP
In any STM instruction, reglist must not contain PC
In any LDM instruction, reglist must not contain PC if it contains LR
reglist must not contain Rn if the writeback suffix is specified.
When PC is in reglist in an LDM instruction:
Bit[0] of the value loaded to the PC must be 1 for correct execution, and a branch occurs to this halfword-
aligned address
If the instruction is conditional, it must be the last instruction in the IT block.
Condition Flags
These instructions do not change the flags.
Examples
LDM R8,{R0,R2,R9} ; LDMIA is a synonym for LDM
STMDB R1!,{R3-R6,R11,R12}
Incorrect Examples
STM R5!,{R5,R4,R9} ; Value stored for R5 is unpredictable
LDM R2, {} ; There must be at least one register in the list
SAM4S Series [DATASHEET]
Atmel-11100K-ATARM-SAM4S-Datasheet_09-Jun-15
112
12.6.4.7 PUSH and POP
Push registers onto, and pop registers off a full-descending stack.
Syntax PUSH{cond} reglist
POP{cond} reglist
where:
cond is an optional condition code, see “Conditional Execution” .
reglist is a non-empty list of registers, enclosed in braces. It can contain register
ranges. It must be comma separated if it contains more than one register or
register range.
PUSH and POP are synonyms for STMDB and LDM (or LDMIA) with the memory addresses for the access based
on SP, and with the final address for the access written back to the SP. PUSH and POP are the preferred
mnemonics in these cases.
Operation
PUSH stores registers on the stack in order of decreasing the register numbers, with the highest numbered
register using the highest memory address and the lowest numbered register using the lowest memory address.
POP loads registers from the stack in order of increasing register numbers, with the lowest numbered register
using the lowest memo ry ad d re ss an d th e hig he st numbered register using the highest memory address.
See “LDM and STM” for more information.
Restrictions
In these instructions:
reglist must not contain SP
For the PUSH instruction, reglist must not contain PC
For the POP instruction, reglist must not contain PC if it contains LR.
When PC is in reglist in a POP instruction:
Bit[0] of the value loaded to the PC must be 1 for correct execution, and a branch occurs to this halfword-
aligned address
If the instruction is conditional, it must be the last instruction in the IT block.
Condition Flags
These instructions do not change the flags.
Examples PUSH {R0,R4-R7}
PUSH {R2,LR}
POP {R0,R10,PC}
113
SAM4S Series [DATASHEET]
Atmel-11100K-ATARM-SAM4S-Datasheet_09-Jun-15
12.6.4.8 LDREX and STREX
Load and Store Register Exclusive.
Syntax LDREX{cond} Rt, [Rn {, #offset}]
STREX{cond} Rd, Rt, [Rn {, #offset}]
LDREXB{cond} Rt, [Rn]
STREXB{cond} Rd, Rt, [Rn]
LDREXH{cond} Rt, [Rn]
STREXH{cond} Rd, Rt, [Rn]
where:
cond is an optional condition code, see “Conditional Execution” .
Rd is the destination register for the returned status.
Rt is the register to lo a d or stor e.
Rn is the register on which the memory address is based.
offset is an optional offset applied to the value in Rn.
If offset is omitted, the address is the value in Rn.
Operation
LDREX, LDREXB, and LDREXH load a word, byte, an d ha lfw or d re sp ec tive ly fro m a mem or y ad dr e ss.
STREX, STREXB, and STREXH attempt to store a word, byte, and halfword respectively to a memory address.
The address used in any Store-Exclusive instruction must be the same as the address in the most recently
executed Load-exclusive instruction. The value stored by the Store-Exclusive instruction must also have the same
data size as the value loaded by the preceding Loa d-exclusive instruction. This means software must always use a
Load-exclusive instruction and a matching Store-Exclusive instruction to perform a synchronization operation, see
“Synchronization Primitives” .
If an Store-Exclusive instruction performs the store, it writes 0 to its destination register. If it does not perform the
store, it writes 1 to its destination register. If the Store-Exclusive instruction writes 0 to the des tination register, it is
guaranteed that no other p rocess in the system has accessed the memory location between the Load-exclusive
and Store-Exclusive instructions.
For reasons of performance, keep the number of instructions betwe en corresponding Load-Exclusive and Store-
Exclusive instruction to a minimum.
The result of exe cu tin g a S tor e -Exc lus ive instr u ctio n to an ad dr es s th at is diffe r en t fr om th at u se d in the pr ece d ing
Load-Exclusive instruction is unpredictable.
Restrictions
In these instructions:
Do not use PC
Do not use SP for Rd and Rt
For STREX, Rd must be diffe rent from both Rt and Rn
The value of offset must be a multiple of four in the range 0–1020.
Condition Flags
These instructions do not change the flags.
Examples MOV R1, #0x1 ; Initialize the ‘lock taken’ value try
LDREX R0, [LockAddr] ; Load the lock value
CMP R0, #0 ; Is the lock free?
SAM4S Series [DATASHEET]
Atmel-11100K-ATARM-SAM4S-Datasheet_09-Jun-15
114
ITT EQ ; IT instruction for STREXEQ and CMPEQ
STREXEQ R0, R1, [LockAddr] ; Try and claim the lock
CMPEQ R0, #0 ; Did this succeed?
BNE try ; No – try again
.... ; Yes – we have the lock
12.6.4.9 CLREX
Clear Exclusive.
Syntax CLREX{cond}
where:
cond is an optional condition code, see “Conditional Execution” .
Operation
Use CLREX to make the next STREX, STREXB, or STREXH instruction write a 1 to its destination register and fail
to perform the store. It is use ful in exce ption handler code to force the failure of the store exclusive if the exception
occurs between a load exclusive instruction and the matching store exclusive instruction in a synchronization
operation.
See “Synchronization Primitives” for more information.
Condition Flags
These instructions do not change the flags.
Examples
CLREX
115
SAM4S Series [DATASHEET]
Atmel-11100K-ATARM-SAM4S-Datasheet_09-Jun-15
12.6.5 General Data Processing Instructions
The table below shows the data processing instructions.
Table 12-20. Data Proce ssing Instructions
Mnemonic Description
ADC Add with Carry
ADD Add
ADDW Add
AND Logi cal AND
ASR Arithmetic Shift Right
BIC Bit Clear
CLZ Count leading zeros
CMN Compare Negative
CMP Compare
EOR Exclusive OR
LSL Logical Shift Left
LSR Logical Shift Right
MOV Move
MOVT Move Top
MOVW Move 16-bit constant
MVN Move NOT
ORN Logical OR NOT
ORR Logical OR
RBIT Reverse Bits
REV Reverse byte order in a word
REV16 Reverse byte order in each halfword
REVSH Reverse byte order in bottom halfword and sign extend
ROR Rotate Right
RRX Rotate Right with Extend
RSB Reverse Subtract
SADD16 Signed Add 16
SADD8 Signed Add 8
SASX Signed Add and Subtract with Exchange
SSAX Signed Subtract and Add with Exchange
SBC Subtract with Carry
SHADD16 Signed Halving Add 16
SHADD8 Signed Halving Add 8
SHASX Signed Halving Add and Subtract with Exchange
SHSAX Signed Halving Subtract and Add with Exchange
SAM4S Series [DATASHEET]
Atmel-11100K-ATARM-SAM4S-Datasheet_09-Jun-15
116
SHSUB16 Signed Halving Subtract 16
SHSUB8 Signed Halving Subtract 8
SSUB16 Signed Subtract 16
SSUB8 Signed Subtract 8
SUB Subtract
SUBW Subtract
TEQ Test Equivalence
TST Test
UADD16 Unsign ed Add 16
UADD8 Unsigned Add 8
UASX Unsigned Add and Subtract with Exchange
USAX Unsigned Subtract and Add with Exchange
UHADD16 Unsigned Halving Add 16
UHADD8 Unsigned Halving Add 8
UHASX Unsign ed Halving Add and Subtract with Exchange
UHSAX Unsign ed Halving Subtract and Add with Exchange
UHSUB16 Unsigned Halving Subtract 16
UHSUB8 Unsigned Halving Subtract 8
USAD8 Unsigned Sum of Absolute Differences
USADA8 Unsigned Sum of Absolute Differences and Accumulate
USUB16 Unsign ed Subtract 16
USUB8 Unsigned Subtract 8
Table 12-20. Data Processing Instructions (Continued)
Mnemonic Description
117
SAM4S Series [DATASHEET]
Atmel-11100K-ATARM-SAM4S-Datasheet_09-Jun-15
12.6.5.1 ADD, ADC, SUB, SBC, and RSB
Add, Add with carry, Subtract, Subtract with carry, and Reverse Subtract.
Syntax op{S}{cond} {Rd,} Rn, Operand2
op{cond} {Rd,} Rn, #imm12 ; ADD and SUB only
where:
op is one of:
ADD Add.
ADC Add with Carry.
SUB Subtract.
SBC Subtract with Carry.
RSB Reverse Subtract.
S is an optional suffix. If S is specified, the condition code flags are updated on the result of the
operation, see “Conditional Execution” .
cond is an optional condition code, see “Conditional Execution” .
Rd is the destinatio n register. If Rd is omitted, the destination register is Rn.
Rn is the register ho ldi n g the first operand.
Operand2 is a flexible second operand. See “Flexible Second Operand” for details of the
options.
imm12 is any value in the range 0–4095.
Operation
The ADD instruction adds the value of Operand2 or imm12 to the value in Rn.
The ADC instruction adds the values in Rn and Operand2, together with the carry flag.
The SUB instruction subtracts the value of Operand2 or imm12 from the value in Rn.
The SBC instruction subtracts the value of Operand2 from the value in Rn. If the carry flag is clear, the result is
reduced by one.
The RSB instruction subtracts the value in Rn from the value of Operand2. This is useful because of the wide
range of options for Operand2.
Use ADC and SBC to synthesize multiword arithmetic, see Multiword arithmetic examples on.
See also “ADR” .
Note: ADDW is equivalent t o the ADD synt ax that uses t he imm12 operand. SUBW is equivalent to the SUB syntax that uses
the imm12 operand.
Restrictions
In these instructions:
Operand2 must not be SP and must not be PC
Rd can be SP only in ADD and SUB, and only with the additional restrictions:
Rn must also be SP
Any shift in Operand2 must be limited to a maximum of 3 bits using LSL
Rn can be SP only in ADD and SUB
Rd can be PC only in the ADD{cond} PC, PC, Rm instruction where:
The user must not specify the S suffix
Rm must not be PC and must not be SP
SAM4S Series [DATASHEET]
Atmel-11100K-ATARM-SAM4S-Datasheet_09-Jun-15
118
If the instruction is conditional, it must be the last instruction in the IT block
With the exception of the ADD{cond} PC, PC, Rm instruction, Rn can be PC only in ADD and SUB, and only
with the addit ion a l rest rict ion s :
The user must not specify the S suffix
The second operand must be a constant in the range 0 to 4095.
Note: When using the PC for an addition or a subtraction, bits[1:0] of the PC are rounded to 0b00
before performing the calculation, making the base address for the calculation word-aligned.
Note: To generate the address of an instruction, the constant based on the value of the PC must be
adjusted. ARM recommends to use the ADR instruction instead of ADD or SUB with Rn equal to the
PC, because the assembler automatically calculates the correct constant for the ADR instruction.
When Rd is PC in the ADD{cond} PC, PC, Rm instruction:
Bit[0] of the value written to the PC is ignored
A branch occurs to the address created by forcing bit[0] of that value to 0.
Condition Flags
If
S
is specified, these instructions update the N, Z, C and V flags according to the result.
Examples ADD R2, R1, R3 ; Sets the flags on the result
SUBS R8, R6, #240 ; Subtracts contents of R4 from 1280
RSB R4, R4, #1280 ; Only executed if C flag set and Z
ADCHI R11, R0, R3 ; flag clear.
Multiword Arithmetic Examples
The example below shows two instruction s that add a 64-bit integer contained in R2 and R3 to another 64-bit
integer contained in R0 and R1, and place the result in R4 and R5.
64-bit Addition Example
ADDS R4, R0, R2 ; add the least significant words
ADC R5, R1, R3 ; add the most significant words with carry
Multiword values do not have to use consecutive registers. The example below shows instructions that subtract a
96-bit integer contained in R9, R1, and R11 from another contained in R6, R2, and R8. The example stores the
result in R6, R9, and R2.
96-bit Subtraction Example
SUBS R6, R6, R9 ; subtract the least significant words
SBCS R9, R2, R1 ; subtract the middle words with carry
SBC R2, R8, R11 ; subtract the most significant words with carry
12.6.5.2 AND, ORR, EOR, BIC, and ORN
Logical AND, OR, Exclusive OR, Bit Clear, and OR NOT.
Syntax op{S}{cond} {Rd,} Rn, Operand2
where:
op is one of:
AND logical AND.
ORR
logical OR, or bit set.
EOR
logical Exclusive OR.
BIC
logical AND NOT, or bit clear.
ORN
logical OR NOT.
119
SAM4S Series [DATASHEET]
Atmel-11100K-ATARM-SAM4S-Datasheet_09-Jun-15
S is an optional suffix. If S is specified, the condition code flags are updated on the result of the
operation, see “Conditional Execution” .
cond is an optional condition code, see “Conditional Execution” .
Rd is the destinatio n register.
Rn is the register ho ldi n g the first operand.
Operand2 is a flexible second operand. See “Flexible Second Operand” for details of the
options.
Operation
The AND, EOR, and ORR instructions perform bitwise AND, Exclusive OR, and OR operations on the values in Rn
and Operand2.
The BIC instruction per forms an AND operation on the bits in Rn with the com plements of the correspond ing bits in
the value of Operand2.
The ORN instruction performs an OR ope ration on the bits in Rn with the comple ments of the corresp onding bits in
the value of Operand2.
Restrictions
Do not use SP and do not use PC.
Condition Flags
If
S
is specified, these instructions:
Update the N and Z flags according to the result
Can update the C flag during the calculation of Operand2, see “Flexible Second Operand”
Do not affect the V flag.
SAM4S Series [DATASHEET]
Atmel-11100K-ATARM-SAM4S-Datasheet_09-Jun-15
120
Examples AND R9, R2, #0xFF00
ORREQ R2, R0, R5
ANDS R9, R8, #0x19
EORS R7, R11, #0x18181818
BIC R0, R1, #0xab
ORN R7, R11, R14, ROR #4
ORNS R7, R11, R14, ASR #32
12.6.5.3 ASR, LSL, LSR, ROR, and RRX
Arithmetic Shift Right, Logical Shift Left, Logical Shift Right, Rotate Right, and Rotate Right with Extend.
Syntax op{S}{cond} Rd, Rm, Rs
op{S}{cond} Rd, Rm, #n
RRX{S}{cond} Rd, Rm
where:
op is one of:
ASR Arithmetic Shift Right.
LSL Logical Shift Left.
LSR Logical Shift Right.
ROR Rotate Right.
S is an optional suffix. If S is specified, the condition code flags are updated on the result of the
operation, see “Conditional Execution” .
Rd is the destinatio n register.
Rm is the register holding the value to be shifted.
Rs is th e register holding th e shift length to apply to the value in Rm. Only the least
significant byte is used and can be in the range 0 to 255.
n is the shift length. The range of shif t length depends on the instruction:
ASR shift length from 1 to 32
LSL shift length from 0 to 31
LSR shift length from 1 to 32
ROR shift length from 0 to 31
MOVS Rd, Rm is the preferred syntax for LSLS Rd, Rm, #0.
Operation
ASR, LSL, LSR, and ROR move the bits in the register Rm to the left or right by the number of places specified by
constant n or register Rs.
RRX moves the bits in register Rm to the ri ght by 1.
In all these instructions, the result is written to Rd, but the value in r eg ist er Rm remains unchanged. For details on
what result is generated by the different instructions, see “Shift Operations” .
Restrictions
Do not use SP and do not use PC.
Condition Flags
121
SAM4S Series [DATASHEET]
Atmel-11100K-ATARM-SAM4S-Datasheet_09-Jun-15
If
S
is specified:
These instructions update the N and Z flags according to the result
The C flag is updated to the last bit shifted out, except when the shift length is 0, see “Shift Operations” .
Examples ASR R7, R8, #9 ; Arithmetic shift right by 9 bits
SLS R1, R2, #3 ; Logical shift left by 3 bits with flag update
LSR R4, R5, #6 ; Logical shift right by 6 bits
ROR R4, R5, R6 ; Rotate right by the value in the bottom byte of R6
RRX R4, R5 ; Rotate right with extend.
12.6.5.4 CLZ
Count Leading Zeros.
Syntax CLZ{cond} Rd, Rm
where:
cond is an optional condition code, see “Conditional Execution” .
Rd is the destinatio n regist er.
Rm is the operand register.
Operation
The CLZ instruction counts the number of leading zeros in the value in Rm and returns the resu lt in Rd. The result
value is 32 if no bits are set and zero if bit[31] is set.
Restrictions
Do not use SP and do not use PC.
Condition Flags
This instruction does not change the flags.
Examples CLZ R4,R9
CLZNE R2,R3
SAM4S Series [DATASHEET]
Atmel-11100K-ATARM-SAM4S-Datasheet_09-Jun-15
122
12.6.5.5 CMP and CMN
Compare an d Co mp a re Neg ativ e.
Syntax CMP{cond} Rn, Operand2
CMN{cond} Rn, Operand2
where:
cond is an optional condition code, see “Conditional Execution” .
Rn is the register ho ldi ng th e first operand.
Operand2 is a flexible second operand. See “Flexible Second Operand” for details of the
options.
Operation
These instructions compare the value in a register with Operand2. They update the condition flags on the result,
but do not write the result to a register.
The CMP instruction subtracts the value of Operand2 from the value in Rn. This is the same as a SUBS
instruction, except that the result is discarded.
The CMN instruction adds the value of Operand2 to the value in Rn. This is the same as an ADDS instruction,
except that the result is discarded.
Restrictions
In these instructions:
Do not use PC
Operand2 must not be SP.
Condition Flags
These instructions update the N, Z, C and V flags according to the result.
Examples CMP R2, R9
CMN R0, #6400
CMPGT SP, R7, LSL #2
123
SAM4S Series [DATASHEET]
Atmel-11100K-ATARM-SAM4S-Datasheet_09-Jun-15
12.6.5.6 MOV and MVN
Move and Move NOT.
Syntax MOV{S}{cond} Rd, Operand2
MOV{cond} Rd, #imm16
MVN{S}{cond} Rd, Operand2
where:
S is an optional suffix. If S is specified, the condition code flags are updated on the result of the
operation, see “Conditional Execution” .
cond is an optional condition code, see “Conditional Execution” .
Rd is the destinatio n regist er.
Operand2 is a flexible second operand. See “Flexible Second Operand” for details of the
options.
imm16 is any value in the range 0–65535.
Operation
The MOV instructio n co pie s the v alue of Operand2 into Rd.
When Operand2 in a MOV instruction is a register with a shift other than LSL #0, the preferred syntax is the
corresponding shift instruction:
ASR{S}{cond} Rd, Rm, #n is the preferred syntax for MOV{S}{cond} Rd, Rm, ASR #n
LSL{S}{cond} Rd, Rm, #n is the preferred synt ax for MOV{S}{cond} Rd, Rm, LSL #n if n!= 0
LSR{S}{cond} Rd, Rm, #n is the preferred syntax for MOV{S}{cond} Rd, Rm, LSR #n
ROR{S}{cond} Rd, Rm, #n is the preferred syntax for MOV{S}{cond} Rd, Rm, ROR #n
RRX{S}{cond} Rd, Rm is the preferred syntax for MOV{S}{cond} Rd, Rm, RRX.
Also, the MOV instruction permits additional forms of Operand2 as synonyms for shift instructions:
MOV{S}{cond} Rd, Rm, ASR Rs is a synonym for ASR{S}{cond} Rd, Rm, Rs
MOV{S}{cond} Rd, Rm, LSL Rs is a synonym for LSL{S}{cond} Rd, Rm, Rs
MOV{S}{cond} Rd, Rm, LSR Rs is a synonym for LSR{S}{cond} Rd, Rm, Rs
MOV{S}{cond} Rd, Rm, ROR Rs is a synonym for ROR{S}{cond} Rd, Rm, Rs
See “ASR, LSL, LSR, ROR, and RRX” .
The MVN instruction takes the value of Operand2, performs a bitwise logical NOT operation on the value, and
places the result into Rd.
The MOVW instruction provides the same function as MOV, but is restricted to using the imm16 opera nd .
Restrictions
SP and PC only can be used in the MOV instruction, with the following restrictions:
The second operand must be a register without shift
The S suffix must not be specified.
When Rd is PC in a MOV instruction:
Bit[0] of the value written to the PC is ignored
A branch occurs to the address created by forcing bit[0] of that value to 0.
Though it is p ossible to use MOV as a branch instruction, ARM strongly recommends the use of a BX or BLX
instruction to branch for software portability to the ARM instruction set.
Condition Flags
SAM4S Series [DATASHEET]
Atmel-11100K-ATARM-SAM4S-Datasheet_09-Jun-15
124
If S is specified, these instructions:
Update the N and Z flags according to the result
Can update the C flag during the calculation of Operand2, see “Flexible Second Operand”
Do not affect the V flag.
Examples MOVS R11, #0x000B ; Write value of 0x000B to
R11, flags get updated
MOV R1, #0xFA05 ; Write value of 0xFA05 to
R1, flags are not updated
MOVS R10, R12 ; Write value in R12 to R10,
flags get updated
MOV R3, #23 ; Write value of 23 to R3
MOV R8, SP ; Write value of stack pointer to R8
MVNS R2, #0xF ; Write value of 0xFFFFFFF0 (bitwise inverse of 0xF)
; to the R2 and update flags.
12.6.5.7 MOVT
Move Top.
Syntax MOVT{cond} Rd, #imm16
where:
cond is an optional condition code, see “Conditional Execution” .
Rd is the destinatio n regist er.
imm16 is a 16-bit immedia te con stant.
Operation
MOVT writes a 16-bit immediate value, imm16, to the top halfword, Rd[31:16], of its destination register. The write
does not affect Rd[15:0].
The MOV, MOVT instr u ction pair enables to generate any 32-bit constant.
Restrictions
Rd must not be SP and must not be PC.
Condition Flags
This instruction does not change the flags.
Examples
MOVT R3, #0xF123 ; Write 0xF123 to upper halfword of R3, lower halfword
; and APSR are unchanged.
12.6.5.8 REV, REV16, REVSH, and RBIT
Reverse bytes and Reverse bits.
Syntax op{cond} Rd, Rn
where:
op is any of:
REV Reverse byte or de r in a wor d .
REV16 Reverse byte order in each halfword independently.
125
SAM4S Series [DATASHEET]
Atmel-11100K-ATARM-SAM4S-Datasheet_09-Jun-15
REVSH Reverse byte order in the bottom halfword, and sign extend to 32 bits.
RBIT Reverse the bit order in a 32-bit word.
cond is an optional condition code, see “Conditional Execution” .
Rd is the destinatio n register.
Rn is the register hold in g th e op er an d .
Operation
Use these instructions to change endianness of data:
REV converts either:
32-bit big-endian data into little-endian data
32-bit little-endian data into big-endian data.
REV16 converts either:
16-bit big-endian data into little-endian data
16-bit little-endian data into big-endian data.
REVSH converts either:
16-bit signed big-endian data into 32-bit signed little-endian data
16-bit signed little-endian data into 32-bit signed big-endian data.
Restrictions
Do not use SP and do not use PC
.
Condition Flags
These instructions do not change the flags.
Examples
REV R3, R7; Reverse byte order of value in R7 and write it to R3
REV16 R0, R0; Reverse byte order of each 16-bit halfword in R0
REVSH R0, R5; Reverse Signed Halfword
REVHS R3, R7; Reverse with Higher or Same condition
RBIT R7, R8; Reverse bit order of value in R8 and write the result to R7.
SAM4S Series [DATASHEET]
Atmel-11100K-ATARM-SAM4S-Datasheet_09-Jun-15
126
12.6.5.9 SADD16 and SADD8
Signed Add 16 and Signed Add 8
Syntax op{cond}{Rd,} Rn, Rm
where:
op is any of:
SADD16 Performs two 16-bit signed integer additions.
SADD8 Performs four 8-bit signed integer additions.
cond is an optional condition code, see “Conditional Execution” .
Rd is the destinatio n regist er.
Rn is the first register holding the operand.
Rm is the second register holding the operand.
Operation
Use these instructions to perform a halfword or byte add in parallel:
The SADD16 instruction:
1. Adds each halfword from the first operand to the corresponding halfword of the second operand.
2. Writes the result in the corresponding halfwords of the destination register.
The SADD8 instruction:
1. Adds each byte of the first operand to the corresponding byte of the second operand.
Writes the result in the corresponding bytes of the destination register.
Restrictions
Do not use SP and do not use PC
.
Condition Flags
These instructions do not change the flags.
Examples
SADD16 R1, R0 ; Adds the halfwords in R0 to the corresponding
; halfwords of R1 and writes to corresponding halfword
; of R1.
SADD8 R4, R0, R5 ; Adds bytes of R0 to the corresponding byte in R5 and
; writes to the corresponding byte in R4.
127
SAM4S Series [DATASHEET]
Atmel-11100K-ATARM-SAM4S-Datasheet_09-Jun-15
12.6.5.10 SHADD16 and SHADD8
Signed Halving Add 16 and Signed Halving Add 8
Syntax op{cond}{Rd,} Rn, Rm
where:
op is any of:
SHADD16 Signed Halving Add 16.
SHADD8 Signed Halving Add 8.
cond is an optional condition code, see “Conditional Execution” .
Rd is the destinatio n regist er.
Rn is the first operan d re gis te r.
Rm is the second operand register.
Operation
Use these instructio ns to add 16-bit and 8-bit data and the n to halve the result before writing the result to the
destination register:
The SHADD16 instruction:
1. Adds each halfword from the first operand to the corresponding halfword of the second operand.
2. Shuffles the result by one bit to the right, halving the data.
3. Writes the halfword results in the destination register.
The SHADDB8 instruction:
1. Adds each byte of the first operand to the corresponding byte of the second operand.
2. Shuffles the result by one bit to the right, halving the data.
3. Writes the byte results in the destination register.
Restrictions
Do not use SP and do not use PC
.
Condition Flags
These instructions do not change the flags.
Examples
SHADD16 R1, R0 ; Adds halfwords in R0 to corresponding halfword of R1
; and writes halved result to corresponding halfword in
; R1
SHADD8 R4, R0, R5 ; Adds bytes of R0 to corresponding byte in R5 and
; writes halved result to corresponding byte in R4.
SAM4S Series [DATASHEET]
Atmel-11100K-ATARM-SAM4S-Datasheet_09-Jun-15
128
12.6.5.11 SHASX and SHSAX
Signed Halving Add and Subtract with Exchange and Signed Halving Subtract and Add with Exchange.
Syntax op{cond} {Rd}, Rn, Rm
where:
op is any of:
SHASX Add and Subtract with Exchange and Halving.
SHSAX Subtract and Add with Exchange and Halving.
cond is an optional condition code, see “Conditional Execution” .
Rd is the destinatio n regist er.
Rn, Rm are registers holding the first and second operands.
Operation
The SHASX instruction:
1. Adds the top halfwor d of the first operand with the bottom halfword of the second operand.
2. Writes the halfword result of the addition to the top halfword of the destination register, shifted by one bit to
the right causing a divide by two, or halving.
3. Subtracts the top halfword of the second oper and from the bottom highword of the first operand.
4. Writes the halfword result of the division in the bottom halfword of the destination register, shifted by one bit
to the right causing a divide by two, or halving.
The SHSAX instruction:
1. Subtracts the bottom halfw ord of the second operand fr om the top highword of the first operand.
2. Writes the halfword result of th e addition to the bottom halfword of the destination register, shifted by one bit
to the right causing a divide by two, or halving.
3. Adds the bottom halfword of the first operand with the top halfword of the second operand.
4. Writes the halfword result of the division in th e top halfword of the destination register, shifted by one bit to
the right causing a divide by two, or halving.
Restrictions
Do not use SP and do not use PC
.
Condition Flags
These instructions do not affect the condition code flags.
129
SAM4S Series [DATASHEET]
Atmel-11100K-ATARM-SAM4S-Datasheet_09-Jun-15
Examples
SHASX R7, R4, R2 ; Adds top halfword of R4 to bottom halfword of R2
; and writes halved result to top halfword of R7
; Subtracts top halfword of R2 from bottom halfword of
; R4 and writes halved result to bottom halfword of R7
SHSAX R0, R3, R5 ; Subtracts bottom halfword of R5 from top halfword
; of R3 and writes halved result to top halfword of R0
; Adds top halfword of R5 to bottom halfword of R3 and
; writes halved result to bottom halfword of R0.
SAM4S Series [DATASHEET]
Atmel-11100K-ATARM-SAM4S-Datasheet_09-Jun-15
130
12.6.5.12 SHSUB16 and SHSUB8
Signed Halving Subtract 16 and Signed Halving Subtract 8
Syntax op{cond}{Rd,} Rn, Rm
where:
op is any of:
SHSUB16 Signed Halving Subtract 16.
SHSUB8 Signed Halving Subtract 8.
cond is an optional condition code, see “Conditional Execution” .
Rd is the destinatio n register.
Rn is the first operan d re gis te r.
Rm is the second operand register.
Operation
Use these instructio ns to add 16-bit and 8-bit data and the n to halve the result before writing the result to the
destination register:
The SHSUB16 instruction:
1. Subtracts each halfword of the second operand from the corresponding halfwords of the first operand.
2. Shuffles the result by one bit to the right, halving the data.
3. Writes the halved halfword results in the destination register.
The SHSUBB8 instruction:
1. Subtracts each byte of the second operand from the corresponding byte of the first operand,
2. Shuffles the result by one bit to the right, halving the data,
3. Writes the corresponding signed byte res ults in the dest in a tio n re gis ter.
Restrictions
Do not use SP and do not use PC
.
Condition Flags
These instructions do not change the flags.
Examples
SHSUB16 R1, R0 ; Subtracts halfwords in R0 from corresponding halfword
; of R1 and writes to corresponding halfword of R1
SHSUB8 R4, R0, R5 ; Subtracts bytes of R0 from corresponding byte in R5,
; and writes to corresponding byte in R4.
131
SAM4S Series [DATASHEET]
Atmel-11100K-ATARM-SAM4S-Datasheet_09-Jun-15
12.6.5.13 SSUB16 and SSUB8
Signed Subtract 16 and Signed Subtract 8
Syntax op{cond}{Rd,} Rn, Rm
where:
op is any of:
SSUB16 Performs two 16-bit signed integer subtractions.
SSUB8 Performs four 8-bit signed integer subtractions.
cond is an optional condition code, see “Conditional Execution” .
Rd is the destinatio n regist er.
Rn is the first operan d re gis te r.
Rm is the second operand register.
Operation
Use these instructions to change endianness of data:
The SSUB16 instruction:
1. Subtracts each halfword from the second operand from the corresponding halfword of the first operand
2. Writes the dif fe rence r esult of two sig ned ha lfwo rd s in th e cor res pon ding ha lfwo rd o f th e d estination re gister.
The SSUB8 instruction:
1. Subtracts each byte of the second operand from the corresponding byte of the first operand
2. Writes the difference result of four signed bytes in the corresponding byte of the destination register.
Restrictions
Do not use SP and do not use PC
.
Condition Flags
These instructions do not change the flags.
Examples
SSUB16 R1, R0 ; Subtracts halfwords in R0 from corresponding halfword
; of R1 and writes to corresponding halfword of R1
SSUB8 R4, R0, R5 ; Subtracts bytes of R5 from corresponding byte in
; R0, and writes to corresponding byte of R4.
SAM4S Series [DATASHEET]
Atmel-11100K-ATARM-SAM4S-Datasheet_09-Jun-15
132
12.6.5.14 SASX and SSAX
Signed Add and Subtract with Exchange and Signed Subtract and Add with Exchange.
Syntax op{cond} {Rd}, Rm, Rn
where:
op is any of:
SASX Signed Add and Subtract with Exchange.
SSAX Signed Subtract and Add with Exchange.
cond is an optional condition code, see “Conditional Execution” .
Rd is the destinatio n regist er.
Rn, Rm are registers holding the first and second operands.
Operation
The SASX instruction:
1. Adds the signe d top halfword of the first operand with the signed bottom halfword of the second operand.
2. Writes the signed re sult of the addition to the top halfw or d of th e de st in a tio n re gis ter.
3. Subtracts the signed bottom halfwor d of the second operand from the top signed highword of the first
operand.
4. Writes the signed result of the subtraction to the bottom halfword of the destination register.
The SSAX instruction:
1. Subtracts the signed bottom halfword of the second operand from the top signed highword of the first
operand.
2. Writes the signed re sult of the addition to the bottom halfword of the destination register.
3. Adds the signed top halfword of the first operand with the signed bottom halfword of the second operand.
4. Writes the signed result of the subtraction to the top halfword of the destination register.
Restrictions
Do not use SP and do not use PC
.
Condition Flags
These instructions do not affect the condition code flags.
Examples
SASX R0, R4, R5 ; Adds top halfword of R4 to bottom halfword of R5 and
; writes to top halfword of R0
; Subtracts bottom halfword of R5 from top halfword of R4
; and writes to bottom halfword of R0
SSAX R7, R3, R2 ; Subtracts top halfword of R2 from bottom halfword of R3
; and writes to bottom halfword of R7
; Adds top halfword of R3 with bottom halfword of R2 and
; writes to top halfword of R7.
12.6.5.15 TST and TEQ
Test bits and Test Equivalence.
Syntax TST{cond} Rn, Operand2
TEQ{cond} Rn, Operand2
133
SAM4S Series [DATASHEET]
Atmel-11100K-ATARM-SAM4S-Datasheet_09-Jun-15
where
cond is an optional condition code, see “Conditional Execution” .
Rn is the register ho ldi n g the first operand.
Operand2 is a flexible second operand. See “Flexible Second Operand” for details of the
options.
Operation
These instructions te st the value in a register against Operand2. They update the cond ition flags based on the
result, but do not write the result to a register.
The TST instruction performs a bitwise AND operation on the value in Rn and the value of Operand2. This is the
same as the ANDS instruction, except that it discards the result.
To test whether a bit of Rn is 0 or 1, use the TST instruction with an Operand2 constant that has that bit set to 1
and all other bits cleared to 0.
The TEQ instr uction performs a bitwise Exclusive OR operation on the value in Rn and the value of Operand2.
This is the same as the EORS instruction, except that it discards the result.
Use the TEQ instruction to test if two values are equal without affecting the V or C flags.
TEQ is also useful for testin g the sign of a value. After th e compar ison, the N flag is th e logical Exclusive OR o f the
sign bits of the two ope r an ds .
Restrictions
Do not use SP and do not use PC.
Condition Flags
These instructions:
Update the N and Z flags according to the result
Can update the C flag during the calculation of Operand2, see “Flexible Second Operand”
Do not affect the V flag.
Examples
TST R0, #0x3F8 ; Perform bitwise AND of R0 value to 0x3F8,
; APSR is updated but result is discarded
TEQEQ R10, R9 ; Conditionally test if value in R10 is equal to
; value in R9, APSR is updated but result is discarded.
12.6.5.16 UADD16 and UADD8
Unsigned Add 16 and Unsigned Add 8
Syntax op{cond}{Rd,} Rn, Rm
where:
op is any of:
UADD16 Performs two 16-bit unsigned integer additions.
UADD8 Performs four 8-bit unsigned integer additions.
cond is an optional condition code, see “Conditional Execution” .
Rd is the destinatio n register.
Rn is the first register holding the operand.
Rm is the second register holding the operand.
Operation
SAM4S Series [DATASHEET]
Atmel-11100K-ATARM-SAM4S-Datasheet_09-Jun-15
134
Use these instructions to add 16- and 8-bit unsigned data:
The UADD16 instruction:
1. Adds each halfword from the first operand to the corresponding halfword of the second operand.
2. Writes the unsigned result in the corresponding halfwords of the destination register.
The UADD16 instruction:
1. Adds each byte of the first operand to the corresponding byte of the second operand.
2. Writes the unsigned result in the corresponding byte of the destination register.
Restrictions
Do not use SP and do not use PC
.
Condition Flags
These instructions do not change the flags.
Examples
UADD16 R1, R0 ; Adds halfwords in R0 to corresponding halfword of R1,
; writes to corresponding halfword of R1
UADD8 R4, R0, R5 ; Adds bytes of R0 to corresponding byte in R5 and
; writes to corresponding byte in R4.
135
SAM4S Series [DATASHEET]
Atmel-11100K-ATARM-SAM4S-Datasheet_09-Jun-15
12.6.5.17 UASX and USAX
Add and Subtract with Exchange and Subtract and Add with Exchange.
Syntax op{cond} {Rd}, Rn, Rm
where:
op is one of:
UASX Add and Subtract with Exchange.
USAX Subtract and Add with Exchange.
cond is an optional condition code, see “Conditional Execution” .
Rd is the destinatio n regist er.
Rn, Rm are registers holding the first and second operands.
Operation
The UASX instruction:
1. Subtracts the top halfword of the second operand from the bottom halfword of the first operand.
2. Writes the unsigned result from the subtraction to the bottom halfword of the destination register.
3. Adds the top halfword of the first operand with the bottom halfword of the second operand.
4. Writes the unsigned result of the addition to the top halfword of the destination register.
The USAX instruction:
1. Adds the bottom halfw ord of the first operand with the top halfword of the second operand.
2. Writes the unsigned result of the add ition to the bottom halfword of the destin a tio n re gist er.
3. Subtracts the bottom halfword of the second operand from the top halfword of the first operand.
4. Writes the unsigned result from the subtraction to the top halfword of th e de stin a tion register.
Restrictions
Do not use SP and do not use PC
.
Condition Flags
These instructions do not affect the condition code flags.
Examples
UASX R0, R4, R5 ; Adds top halfword of R4 to bottom halfword of R5 and
; writes to top halfword of R0
; Subtracts bottom halfword of R5 from top halfword of R0
; and writes to bottom halfword of R0
USAX R7, R3, R2 ; Subtracts top halfword of R2 from bottom halfword of R3
; and writes to bottom halfword of R7
; Adds top halfword of R3 to bottom halfword of R2 and
; writes to top halfword of R7.
12.6.5.18 UHADD16 and UHADD8
Unsigned Halving Add 16 and Unsigned Halving Add 8
Syntax op{cond}{Rd,} Rn, Rm
where:
op is any of:
UHADD16 Unsigned Halving Add 16.
UHADD8 Unsigned Halving Add 8.
SAM4S Series [DATASHEET]
Atmel-11100K-ATARM-SAM4S-Datasheet_09-Jun-15
136
cond is an optional condition code, see “Conditional Execution” .
Rd is the destinatio n register.
Rn is the register ho ldi n g the first operand.
Rm is the register holding the second operand.
Operation
Use these instructions to add 16- and 8-bit data and then to halve the result before writing the result to the
destination register:
The UHADD16 instruction:
1. Adds each halfword from the first operand to the corresponding halfword of the second operand.
2. Shuffles the halfword result by one bit to the right, halving the data.
3. Writes the unsigned results to the corresponding halfword in the destination register.
The UHADD8 instruction:
1. Adds each byte of the first operand to the corresponding byte of the second operand.
2. Shuffles the byte resu lt by one bit to the right, halving the data.
3. Writes the unsigned results in the corresponding byte in the destination register.
Restrictions
Do not use SP and do not use PC
.
Condition Flags
These instructions do not change the flags.
Examples
UHADD16 R7, R3 ; Adds halfwords in R7 to corresponding halfword of R3
; and writes halved result to corresponding halfword
; in R7
UHADD8 R4, R0, R5 ; Adds bytes of R0 to corresponding byte in R5 and
; writes halved result to corresponding byte in R4.
12.6.5.19 UHASX and UHSAX
Unsigned Halving Add and Subtract with Exchange and Unsigned Halving Subtract and Add with Exchange.
Syntax op{cond} {Rd}, Rn, Rm
where:
op is one of:
UHASX Add and Subtract with Exchange and Halving.
UHSAX Subtract and Add with Exchange and Halving.
cond is an optional condition code, see “Conditional Execution” .
Rd is the destinatio n register.
Rn, Rm are registers holding the first and second operands.
Operation
The UHASX instruction:
1. Adds the top halfwor d of the first operand with the bottom halfword of the second operand.
2. Shifts the result by one bit to the right causing a divide by two, or halving.
3. Writes the halfword result of the addition to the top halfword of the destination register.
137
SAM4S Series [DATASHEET]
Atmel-11100K-ATARM-SAM4S-Datasheet_09-Jun-15
4. Subtracts the top halfword of the second oper and from the bottom highword of the first operand.
5. Shifts the result by one bit to the right causing a divide by two, or halving.
6. Writes the halfword result of the division in the bottom halfword of the destination register.
The UHSAX instruction:
1. Subtracts the bottom halfw ord of the second operand fr om the top highword of the first operand.
2. Shifts the result by one bit to the right causing a divide by two, or halving.
3. Writes the halfword result of the subtraction in the top halfword of the destination register.
4. Adds the bottom halfword of the first operand with the top halfword of the second operand.
5. Shifts the result by one bit to the right causing a divide by two, or halving.
6. Writes the halfword result of the addition to the bottom halfword of the destination register.
Restrictions
Do not use SP and do not use PC
.
Condition Flags
These instructions do not affect the condition code flags.
Examples
UHASX R7, R4, R2 ; Adds top halfword of R4 with bottom halfword of R2
; and writes halved result to top halfword of R7
; Subtracts top halfword of R2 from bottom halfword of
; R7 and writes halved result to bottom halfword of R7
UHSAX R0, R3, R5 ; Subtracts bottom halfword of R5 from top halfword of
; R3 and writes halved result to top halfword of R0
; Adds top halfword of R5 to bottom halfword of R3 and
; writes halved result to bottom halfword of R0.
SAM4S Series [DATASHEET]
Atmel-11100K-ATARM-SAM4S-Datasheet_09-Jun-15
138
12.6.5.20 UHSUB16 and UHSUB8
Unsigned Halving Subtract 16 and Unsigned Halving Subtract 8
Syntax op{cond}{Rd,} Rn, Rm
where:
op is any of:
UHSUB16 Performs two unsigned 16-bit integer additions, halves the results,
and writes the results to the de st ina tio n re gis te r.
UHSUB8 Performs four unsigned 8-bit integer additions, halves the results, and
writes the results to the destination register.
cond is an optional condition code, see “Conditional Execution” .
Rd is the destinatio n register.
Rn is the first register holding the operand.
Rm is the second register holding the operand.
Operation
Use these instructio ns to add 16-bit and 8-bit data and the n to halve the result before writing the result to the
destination register:
The UHSUB16 instruction:
1. Subtracts each halfword of the second operand from the corresponding half word of the first operand.
2. Shuffles each halfword result to the right by one bit, halving the data.
3. Writes each unsigned halfword result to the corresponding halfwords in the de stin at ion reg ist er.
The UHSUB8 instruction:
1. Subtracts each byte of second ope rand from the corresponding byte of the first opera nd.
2. Shuffles each byte result by one bit to the right, halving the data.
3. Writes the unsigned byte results to the corresponding byte of the destination register.
Restrictions
Do not use SP and do not use PC
.
Condition Flags
These instructions do not change the flags.
Examples
UHSUB16 R1, R0 ; Subtracts halfwords in R0 from corresponding halfword of
; R1 and writes halved result to corresponding halfword in R1
UHSUB8 R4, R0, R5 ; Subtracts bytes of R5 from corresponding byte in R0 and
; writes halved result to corresponding byte in R4.
12.6.5.21 SEL
Select Bytes. Selects each byte of its result from either its first operand or its second operand, according to the
values of the GE flags.
Syntax SEL{<c>}{<q>} {<Rd>,} <Rn>, <Rm>
where:
c, q are standard assembler syntax fields.
139
SAM4S Series [DATASHEET]
Atmel-11100K-ATARM-SAM4S-Datasheet_09-Jun-15
Rd is the destinatio n register.
Rn is the first register holding the operand.
Rm is the second register holding the operand.
Operation
The
SEL
instruction:
1. Reads the value of each bit of APSR.GE.
2. Depending on the value of APSR.GE, assigns the destination register the value of either the first or second
operand re gister.
Restrictions
None.
Condition Flags
These instructions do not change the flags.
Examples
SADD16 R0, R1, R2 ; Set GE bits based on result
SEL R0, R0, R3 ; Select bytes from R0 or R3, based on GE.
SAM4S Series [DATASHEET]
Atmel-11100K-ATARM-SAM4S-Datasheet_09-Jun-15
140
12.6.5.22 USAD8
Unsigned Sum of Absolute Differences
Syntax USAD8{cond}{Rd,} Rn, Rm
where:
cond is an optional condition code, see “Conditional Execution” .
Rd is the destinatio n regist er.
Rn is the first operan d re gis te r.
Rm is the second operand register.
Operation
The USAD8 instruction:
1. Subtracts each byte of the second operand register from the corresponding byte of the first operand
register.
2. Adds the absolute values of the differences together.
3. Writes the result to the destination register.
Restrictions
Do not use SP and do not use PC
.
Condition Flags
These instructions do not change the flags.
Examples
USAD8 R1, R4, R0 ; Subtracts each byte in R0 from corresponding byte of R4
; adds the differences and writes to R1
USAD8 R0, R5 ; Subtracts bytes of R5 from corresponding byte in R0,
; adds the differences and writes to R0.
141
SAM4S Series [DATASHEET]
Atmel-11100K-ATARM-SAM4S-Datasheet_09-Jun-15
12.6.5.23 USADA8
Unsigned Sum of Absolute Differences and Accumulate
Syntax USADA8{cond}{Rd,} Rn, Rm, Ra
where:
cond is an optional condition code, see “Conditional Execution” .
Rd is the destinatio n regist er.
Rn is the first operan d re gis te r.
Rm is the second operand register.
Ra is the register tha t con tains the ac cum u lat i on value.
Operation
The USADA8 instruction:
1. Subtracts each byte of the second operand register from the corresponding byte of the first operand
register.
2. Adds the unsigned absolute differences together.
3. Adds the accumulation value to the sum of the absol ute differences.
4. Writes the result to the destination register.
Restrictions
Do not use SP and do not use PC
.
Condition Flags
These instructions do not change the flags.
Examples
USADA8 R1, R0, R6 ; Subtracts bytes in R0 from corresponding halfword of R1
; adds differences, adds value of R6, writes to R1
USADA8 R4, R0, R5, R2 ; Subtracts bytes of R5 from corresponding byte in R0
; adds differences, adds value of R2 writes to R4.
SAM4S Series [DATASHEET]
Atmel-11100K-ATARM-SAM4S-Datasheet_09-Jun-15
142
12.6.5.24 USUB16 and USUB8
Unsigned Subtract 16 and Unsigned Subtract 8
Syntax op{cond}{Rd,} Rn, Rm
where
op is any of:
USUB16 Unsigned Subtract 16.
USUB8 Unsigned Subtract 8.
cond is an optional condition code, see “Conditional Execution” .
Rd is the destinatio n regist er.
Rn is the first operan d re gis te r.
Rm is the second operand register.
Operation
Use these instructions to subtract 16-bit and 8-bit data before writing the result to the destination register:
The USUB16 instruction:
1. Subtracts each halfword from the second operand register from the corresponding halfword of the first
operand re gister.
2. Writes the unsigned result in the corresponding halfwords of the destination register.
The USUB8 instruction:
1. Subtracts each byte of the second operand register from the corresponding byte of the first operand
register.
2. Writes the unsigned byte result in the corresponding byte of the destination register.
Restrictions
Do not use SP and do not use PC
.
Condition Flags
These instructions do not change the flags.
Examples
USUB16 R1, R0 ; Subtracts halfwords in R0 from corresponding halfword of R1
; and writes to corresponding halfword in R1USUB8 R4, R0, R5
; Subtracts bytes of R5 from corresponding byte in R0 and
; writes to the corresponding byte in R4.
143
SAM4S Series [DATASHEET]
Atmel-11100K-ATARM-SAM4S-Datasheet_09-Jun-15
12.6.6 Multiply and Divide Instructions
The table below shows the multiply and divide instructions.
Table 12-2 1. Multiply and Divide Instru ctions
Mnemonic Description
MLA Multiply with Accumulate, 32-bit result
MLS Multiply and Subtract, 32-bit result
MUL Multiply, 32-bit result
SDIV Signed Divide
SMLA[B,T] Signed Multiply Accumulate (halfwords)
SMLAD
,
SMLADX
Signed Multiply Accumulate Dual
SMLAL Signed Multiply with Accumulate (32 × 32 + 64), 64-bit result
SMLAL[B,T]
Si gned Multiply Accumulate Long (halfwords)
SMLALD
,
SMLALDX
Signed Multiply Accumu late Long Dual
SMLAW[B|T ] Signed Multiply Accumulate (word by halfword)
SMLSD Signed Multiply Subtract Dual
SMLSLD Signed Multiply Subtract Long Dual
SMMLA Signed Most Significant Word Multiply Accumulate
SMMLS
,
SMMLSR
Signed Most Significant Word Multiply Subtract
SMUAD, SMUADX Signed Dual Multiply Add
SMUL[B,T] Signed Multiply (word by halfword)
SMMUL
,
SMMULR
Signed Most Significant Word Multiply
SMULL Signed Multiply (32x32), 64-bit result
SMULWB, SMULWT Signed Multiply (word by halfword )
SMUSD, SMUSDX Signed Dual Multiply Subtract
UDIV Unsigned Divide
UMAAL Unsigned Multiply Accumulate Accumulate Long (32 × 32 + 32 + 32), 64-bit result
UMLAL Unsigned Multiply with Accumulate (32 × 32 + 64), 64-bit result
UMULL Unsigned Multiply (32 × 32), 64-bit result
SAM4S Series [DATASHEET]
Atmel-11100K-ATARM-SAM4S-Datasheet_09-Jun-15
144
12.6.6.1 MUL, MLA, and MLS
Multiply, Multiply with Accumulate, and Multiply with Subtract, using 32-bit operands, an d pro ducing a 32 -bit result.
Syntax MUL{S}{cond} {Rd,} Rn, Rm ; Multiply
MLA{cond} Rd, Rn, Rm, Ra ; Multiply with accumulate
MLS{cond} Rd, Rn, Rm, Ra ; Multiply with subtract
where:
cond is an optional condition code, see “Conditional Execution” .
S is an optional suffix. If S is specified, the condition code flags are updated on the result of the
operation, see “Conditional Execution” .
Rd is the destinatio n regist er. I f Rd is omitted, the destination register is Rn.
Rn, Rm are registers holding the values to be multiplied.
Ra is a register holding the value to be added or subtracted from.
Operation
The MUL instruction multiplies the values from Rn and Rm, and places the least significant 32 bits of the result in
Rd.
The MLA instruction multiplies the values from Rn and Rm, adds the value from Ra, and places the least
significant 32 bits of the result in Rd.
The MLS instruction multiplies the v alues from Rn and Rm, subtracts the product from the value from Ra, and
places the least significant 32 bits of the result in Rd.
The results of thes e inst ru ctio n s do no t de pe n d on whether the operands are signed or unsigned.
Restrictions
In these instructions, do not use SP and do not use PC.
If the S suffix is used with the MUL instruction:
Rd, Rn, and Rm must all be in the range R0 to R7
Rd must be the same as Rm
The cond suffix must not be used.
Condition Flags
If S is specified, the MUL instruction:
Updates the N and Z flags according to the result
Does not affect the C and V flags.
Examples MUL R10, R2, R5 ; Multiply, R10 = R2 x R5
MLA R10, R2, R1, R5 ; Multiply with accumulate, R10 = (R2 x R1) + R5
MULS R0, R2, R2 ; Multiply with flag update, R0 = R2 x R2
MULLT R2, R3, R2 ; Conditionally multiply, R2 = R3 x R2
MLS R4, R5, R6, R7 ; Multiply with subtract, R4 = R7 - (R5 x R6)
12.6.6.2 UMULL, UMAAL, UMLAL
Unsigned Long Multiply, with optional Accumulate, using 32-bit operands and produ cing a 64-bit result.
Syntax op{cond} RdLo, RdHi, Rn, Rm
where:
op is one of:
145
SAM4S Series [DATASHEET]
Atmel-11100K-ATARM-SAM4S-Datasheet_09-Jun-15
UMULL Unsigned Long Multiply.
UMAAL Unsigned Long Multiply with Accumulate Accumulate.
UMLAL Unsigned Long Multiply, with Accumulate.
cond is an optional condition code, see “Conditional Execution” .
RdHi, RdLo are the destination registers. For UMAAL, UMLAL and UMLAL they also hold
the accumulating value.
Rn, Rm are registers holding the first and second operands.
Operation
These instructions interpret the values from Rn and Rm as unsigned 32-bit integers.
The UMULL instruction:
Multiplies the two unsigned integers in the first and second operands.
Writes the least significant 32 bits of the result in RdLo.
Writes the most significant 32 bits of the result in RdHi.
The UMAAL instruction:
Multiplies the two unsigned 32-bit integers in the first and second operands.
Adds the unsigned 32-bit integer in RdHi to the 64-bit result of the multiplication.
Adds the unsigned 32-bit integer in RdLo to the 64-bit result of the addition.
Writes the top 32-bits of the result to RdHi.
Writes the lower 32-bits of the result to RdLo.
The UMLAL instruction:
Multiplies the two unsigned integers in the first and second operands.
Adds the 64-bit result to the 64-bit unsigned integer contained in RdHi and RdLo.
Writes the result back to RdHi and RdLo.
Restrictions
In these instructions:
Do not use SP and do not use PC.
RdHi and RdLo must be different registers.
Condition Flags
These instructions do not affect the condition code flags.
Examples
UMULL R0, R4, R5, R6 ; Multiplies R5 and R6, writes the top 32 bits to R4
; and the bottom 32 bits to R0
UMAAL R3, R6, R2, R7 ; Multiplies R2 and R7, adds R6, adds R3, writes the
; top 32 bits to R6, and the bottom 32 bits to R3
UMLAL R2, R1, R3, R5 ; Multiplies R5 and R3, adds R1:R2, writes to R1:R2.
12.6.6.3 SMLA and SMLAW
Signed Multiply Accumulate (halfwords).
Syntax op{XY}{cond} Rd, Rn, Rm
op{Y}{cond} Rd, Rn, Rm, Ra
where:
op is one of:
SMLA Signed Multiply Accumulate Long (halfwords).
SAM4S Series [DATASHEET]
Atmel-11100K-ATARM-SAM4S-Datasheet_09-Jun-15
146
X and Y specifies which half of the source registers Rn and Rm are used as the
first and second multiply operand.
If X is B, then the bottom halfword, bits [15:0], of Rn is used.
If X is T, then the top halfword, bits [31:16], of Rn is used.
If Y is B, then the bottom halfword, bits [15:0], of Rm is used.
If Y is T, then the top halfword, bits [31:16], of Rm is used
SMLAW Signed Multiply Accumulate (word by halfword).
Y specifies which half of the source register Rm is used as the second multiply
operand.
If Y is T, then the top halfword, bits [31:16] of Rm is used.
If Y is B, then the bottom halfword, bits [15:0] of Rm is used.
cond is an optional condition code, see “Conditional Execution” .
Rd is the destinatio n register. If Rd is omitted, the destination register is Rn.
Rn, Rm are registers holding the values to be multiplied.
Ra is a register holding the value to be added or subtracted from.
Operation
The SMALBB, SMLABT, SMLATB, SMLATT instructions:
Multiplies the specified signed halfword, top or bottom, values from Rn and Rm.
Adds the value in Ra to the resulting 32-bit produc t.
Writes the result of the multiplication and addition in Rd.
The non-specified halfword s of the sour ce reg i sters are ignored.
The SMLAWB and SMLAWT instructions:
Multiply the 32-bit signed values in Rn with:
The top signe d ha lfwo rd of Rm, T instruction suffix.
The bottom signed halfword of Rm, B instruction suffix.
Add the 32-bit signed value in Ra to the top 32 bits of the 48-bit product
Writes the result of the multiplication and addition in Rd.
The bottom 16 bits of the 48-bit product are ignored.
If overflow occurs during the addition of the accumulate value, the instruction sets the Q flag in the APSR. No
overflow can occur during the multiplication.
Restrictions
In these instructions, do not use SP and do not use PC.
Condition Flags
If an overflow is detected, the
Q
flag is set.
Examples
SMLABB R5, R6, R4, R1 ; Multiplies bottom halfwords of R6 and R4, adds
; R1 and writes to R5
SMLATB R5, R6, R4, R1 ; Multiplies top halfword of R6 with bottom halfword
; of R4, adds R1 and writes to R5
SMLATT R5, R6, R4, R1 ; Multiplies top halfwords of R6 and R4, adds
; R1 and writes the sum to R5
SMLABT R5, R6, R4, R1 ; Multiplies bottom halfword of R6 with top halfword
; of R4, adds R1 and writes to R5
SMLABT R4, R3, R2 ; Multiplies bottom halfword of R4 with top halfword of
; R3, adds R2 and writes to R4
147
SAM4S Series [DATASHEET]
Atmel-11100K-ATARM-SAM4S-Datasheet_09-Jun-15
SMLAWB R10, R2, R5, R3 ; Multiplies R2 with bottom halfword of R5, adds
; R3 to the result and writes top 32-bits to R10
SMLAWT R10, R2, R1, R5 ; Multiplies R2 with top halfword of R1, adds R5
; and writes top 32-bits to R10.
SAM4S Series [DATASHEET]
Atmel-11100K-ATARM-SAM4S-Datasheet_09-Jun-15
148
12.6.6.4 SMLAD
Signed Multiply Accumulate Lo ng Dua l
Syntax op{X}{cond} Rd, Rn, Rm, Ra ;
where:
op is one of:
SMLAD Signed Multiply Accumulate Dual.
SMLADX Signed Multiply Accumulate Dual Reverse.
X specifies which halfword of the source register Rn is used as the multiply
operand.
If X is omitted, the multiplications are bottom × bottom and top × top.
If X is present, the multiplications are bottom × top and top × bottom.
cond is an optional condition code, see “Conditional Execution” .
Rd is the destinatio n regist er.
Rn is the first operand register holding the values to be multiplied.
Rm the second operand register.
Ra is the acc umulate value.
Operation
The SMLAD and SMLADX instructions regard the two operands as four halfword 16-bit values. The SMLAD and
SMLADX instructions:
If X is not present, multiply t he top signed halfword value in Rn with the top signed halfword of Rm and the
bottom signed halfword values in Rn with the bottom signed halfword of Rm.
Or if X is present, multiply the top signed halfword value in Rn with the bottom signed halfword of Rm and
the bottom signed halfword values in Rn with the top signed halfword of Rm.
Add both multiplication results to the signed 32-bit value in Ra.
Writes the 32-bit signed result of the multiplication and addition to Rd.
Restrictions
Do not use SP and do not use PC
.
Condition Flags
These instructions do not change the flags.
Examples
SMLAD R10, R2, R1, R5 ; Multiplies two halfword values in R2 with
; corresponding halfwords in R1, adds R5 and
; writes to R10
SMLALDX R0, R2, R4, R6 ; Multiplies top halfword of R2 with bottom
; halfword of R4, multiplies bottom halfword of R2
; with top halfword of R4, adds R6 and writes to
; R0.
12.6.6.5 SMLAL and SMLALD
Signed Multiply Accumulate Long, Signed Multiply Accumulate Long (halfwords) and Signed Multiply Accumulate
Long Dual.
Syntax op{cond} RdLo, RdHi, Rn, Rm
149
SAM4S Series [DATASHEET]
Atmel-11100K-ATARM-SAM4S-Datasheet_09-Jun-15
op{XY}{cond} RdLo, RdHi, Rn, Rm
op{X}{cond} RdLo, RdHi, Rn, Rm
where:
op is one of:
MLAL Signed Multiply Accumulate Long.
SMLAL Signed Multiply Accumu late Long (halfwords, X and Y).
X and Y specify which halfword of the source registers Rn and Rm are used as
the first and second multiply operand:
If X is B, then the bottom halfword, bits [15:0], of Rn is used.
If X is T, then the top halfword, bits [31:16], of Rn is used.
If Y is B, then the bottom halfword, bits [15:0], of Rm is used.
If Y is T, then the top halfword, bits [31:16], of Rm is used.
SMLALD Signed Multiply Accumulate Long Dual.
SMLALDX Signed Multiply Accumulate Long Dual Reversed.
If the X is omitted, the multiplications are bottom × bottom and top × top.
If X is present, the multiplications are bottom × top and top × bottom.
cond is an optional condition code, see “Conditional Execution” .
RdHi, RdLo are the destination registers.
RdLo is the lower 32 bits and RdHi is the upper 32 bits of the 64-bit integer.
For SMLAL, SMLALBB, SMLALBT, SMLALTB, SMLALTT, SMLALD and SMLA
LDX, they also hold the ac cu mu la ting valu e .
Rn, Rm are registers holding the first and second operands.
Operation
The SMLAL instruction:
Multiplies the two’s complement signed word values from Rn and Rm.
Adds the 64-bit value in RdLo and RdHi to the resulting 64-bit product.
Writes the 64-bit result of the multiplication and addition in RdLo and RdHi.
The SMLALBB, SMLALBT, SMLALTB and SMLALTT instructions:
Multiplies the specified signed halfword, Top or Bottom, values from Rn and Rm.
Adds the resulting sign-extended 32-bit product to the 64-bit value in RdLo and RdHi.
Writes the 64-bit result of the multiplication and addition in RdLo and RdHi.
The non-specified halfword s of the sour ce reg i sters are ignored.
The SMLALD and SMLALDX instructions interpret the values from Rn and Rm as four halfword two’s complement
signed 16-bit integers. These instructions:
If X is not present, multiply t he top signed halfword value of Rn with the top signed halfword of Rm and the
bottom signed halfword values of Rn with the bottom signed halfword of Rm.
Or if X is present, multiply the top signed halfword value of Rn with the bottom signed halfword of Rm an d
the bottom signed halfword values of Rn with the top signed halfword of Rm.
Add the two multiplication results to the signed 64-bit value in RdLo and RdHi to create the resulting 64-bit
product.
Write the 64-bit product in RdLo and RdHi.
Restrictions
In these instructions:
SAM4S Series [DATASHEET]
Atmel-11100K-ATARM-SAM4S-Datasheet_09-Jun-15
150
Do not use SP and do not use PC.
RdHi and RdLo must be different registers.
Condition Flags
These instructions do not affect the condition code flags.
Examples
SMLAL R4, R5, R3, R8 ; Multiplies R3 and R8, adds R5:R4 and writes to
; R5:R4
SMLALBT R2, R1, R6, R7 ; Multiplies bottom halfword of R6 with top
; halfword of R7, sign extends to 32-bit, adds
; R1:R2 and writes to R1:R2
SMLALTB R2, R1, R6, R7 ; Multiplies top halfword of R6 with bottom
; halfword of R7,sign extends to 32-bit, adds R1:R2
; and writes to R1:R2
SMLALD R6, R8, R5, R1 ; Multiplies top halfwords in R5 and R1 and bottom
; halfwords of R5 and R1, adds R8:R6 and writes to
; R8:R6
SMLALDX R6, R8, R5, R1 ; Multiplies top halfword in R5 with bottom
; halfword of R1, and bottom halfword of R5 with
; top halfword of R1, adds R8:R6 and writes to
; R8:R6.
151
SAM4S Series [DATASHEET]
Atmel-11100K-ATARM-SAM4S-Datasheet_09-Jun-15
12.6.6.6 SMLSD and SMLSLD
Signed Multiply Subtract Dual and Signed Multiply Subtract Long Dual
Syntax op{X}{cond} Rd, Rn, Rm, Ra
where:
op is one of:
SMLSD Signed Multiply Subtract Dual.
SMLSDX Signed Multiply Subtract Dual Reversed.
SMLSLD Signed Multiply Subtract Long Dual.
SMLSLDX Signed Multiply Subtract Long Dual Reversed.
SMLAW Signed Multiply Accumulate (word by halfword).
If X is present, the multiplications are bottom × top and top × bottom.
If the X is omitted, the multiplications are bottom × bottom and top × top.
cond is an optional condition code, see “Conditional Execution” .
Rd is the destinatio n register.
Rn, Rm are registers holding the first and second operands.
Ra is the register ho ldi ng th e accumulate value .
Operation
The SMLSD instruction interprets the values from the first and second operands as four signed halfwords. This
instruction:
Optionally rotates the halfwords of the second operand.
Performs two signed 16 × 16-b it halfword multiplications.
Subtracts the result of the upper halfword multiplication from the result of the lower halfword multiplication.
Adds the signed accumulate value to the result of the subtraction.
Writes the result of the addition to the destination register.
The SMLSLD instruction interprets the values from Rn and Rm as four signed halfwo rds.
This instruction:
Optionally rotates the halfwords of the second operand.
Performs two signed 16 × 16-b it halfword multiplications.
Subtracts the result of the upper halfword multiplication from the result of the lower halfword multiplication.
Adds the 64-bit value in RdHi and RdLo to the result of the subtraction.
Writes the 64-bit result of the addition to the RdHi and RdLo.
Restrictions
In these instructions:
Do not use SP and do not use PC.
Condition Flags
This instruction sets the Q flag if the accumulate operation overflows. Overflow cannot occur during the
multiplicat ion s or subt ra ctio n .
For the Thumb instruction set, these instructions do not affect the condition code flags.
Examples
SMLSD R0, R4, R5, R6 ; Multiplies bottom halfword of R4 with bottom
; halfword of R5, multiplies top halfword of R4
SAM4S Series [DATASHEET]
Atmel-11100K-ATARM-SAM4S-Datasheet_09-Jun-15
152
; with top halfword of R5, subtracts second from
; first, adds R6, writes to R0
SMLSDX R1, R3, R2, R0 ; Multiplies bottom halfword of R3 with top
; halfword of R2, multiplies top halfword of R3
; with bottom halfword of R2, subtracts second from
; first, adds R0, writes to R1
SMLSLD R3, R6, R2, R7 ; Multiplies bottom halfword of R6 with bottom
; halfword of R2, multiplies top halfword of R6
; with top halfword of R2, subtracts second from
; first, adds R6:R3, writes to R6:R3
SMLSLDX R3, R6, R2, R7 ; Multiplies bottom halfword of R6 with top
; halfword of R2, multiplies top halfword of R6
; with bottom halfword of R2, subtracts second from
; first, adds R6:R3, writes to R6:R3.
153
SAM4S Series [DATASHEET]
Atmel-11100K-ATARM-SAM4S-Datasheet_09-Jun-15
12.6.6.7 SMMLA and SMMLS
Signed Most Significant Word Multiply Accumulate and Signed Most Significant Word Multiply Subtract
Syntax op{R}{cond} Rd, Rn, Rm, Ra
where:
op is one of:
SMMLA Signed Most Significant Word Multiply Accumulate.
SMMLS Signed Most Significant Word Multiply Subtract.
If the X is omitted, the multiplications are bottom × bottom and top × top.
R is a rounding error flag. If R is specified, the result is rounded instead of being
truncated. In this case the constant 0x80000000 is added to the product before
the high word is extracted.
cond is an optional condition code, see “Conditional Execution” .
Rd is the destinatio n register.
Rn, Rm are registers holding the first and second multiply operands.
Ra is the register ho ldi ng th e accumulate value .
Operation
The SMMLA instruction interprets the values from Rn and Rm as signed 32-bit words.
The SMMLA instruction:
Multiplies the values in Rn and Rm.
Optionally rounds the result by adding 0x80000000.
Extracts the most significant 32 bits of the result.
Adds the value of Ra to the signed extracted value.
Writes the result of the addition in Rd.
The SMMLS instruction interprets the values from Rn and Rm as signed 32-bit words.
The SMMLS instruction:
Multiplies the values in Rn and Rm.
Optionally rounds the result by adding 0x80000000.
Extracts the most significant 32 bits of the result.
Subtracts the extract ed valu e of the resu lt fro m th e va lue in Ra.
Writes the result of the subtraction in Rd.
Restrictions
In these instructions:
Do not use SP and do not use PC.
Condition Flags
These instructions do not affect the condition code flags.
Examples
SMMLA R0, R4, R5, R6 ; Multiplies R4 and R5, extracts top 32 bits, adds
; R6, truncates and writes to R0
SMMLAR R6, R2, R1, R4 ; Multiplies R2 and R1, extracts top 32 bits, adds
; R4, rounds and writes to R6
SMMLSR R3, R6, R2, R7 ; Multiplies R6 and R2, extracts top 32 bits,
; subtracts R7, rounds and writes to R3
SAM4S Series [DATASHEET]
Atmel-11100K-ATARM-SAM4S-Datasheet_09-Jun-15
154
SMMLS R4, R5, R3, R8 ; Multiplies R5 and R3, extracts top 32 bits,
; subtracts R8, truncates and writes to R4.
12.6.6.8 SMMUL
Signed Most Significant Word Multiply
Syntax op{R}{cond} Rd, Rn, Rm
where:
op is one of:
SMMUL Signed Most Significant Word Multiply.
R is a rounding error flag. If R is specified, the result is rounded instead of being
truncated. In this case the constant 0x80000000 is added to the product before
the high word is extracted.
cond is an optional condition code, see “Conditional Execution” .
Rd is the destinatio n register.
Rn, Rm are registers holding the first and second operands.
Operation
The SMMUL instruction interprets the values from Rn and Rm as two’s complement 32-bit signed integers. The
SMMUL instruction:
Multiplies the values from Rn and Rm.
Optionally rounds the result, otherwise truncates the result.
Writes the most significant signed 32 bits of the result in Rd.
Restrictions
In this instruction:
do not use SP and do not use PC.
Condition Flags
This instruction does not affect the condition code flags.
Examples
SMULL R0, R4, R5 ; Multiplies R4 and R5, truncates top 32 bits
; and writes to R0
SMULLR R6, R2 ; Multiplies R6 and R2, rounds the top 32 bits
; and writes to R6.
12.6.6.9 SMUAD and SMUSD
Signed Dual Multiply Add and Signed Dual Multiply Subtract
Syntax op{X}{cond} Rd, Rn, Rm
where:
op is one of:
SMUAD Signed Dual Multiply Add.
SMUADX Signed Dual Multiply Add Reversed.
SMUSD Signed Dual Multiply Subtract.
155
SAM4S Series [DATASHEET]
Atmel-11100K-ATARM-SAM4S-Datasheet_09-Jun-15
SMUSDX Signed Dual Multiply Subtract Reversed.
If X is present, the multiplications are bottom × top and top × bottom.
If the X is omitted, the multiplications are bottom × bottom and top × top.
cond is an optional condition code, see “Conditional Execution” .
Rd is the destinatio n register.
Rn, Rm are registers holding the first and second operands.
Operation
The SMUAD instruction interprets the values from the first and second operands as two signed halfwords in each
operand. This instruction:
Optionally rotates the halfwords of the second operand.
Performs two signed 16 × 16-bit multiplications.
Adds the two multiplication results together.
Writes the result of the addition to the destination register.
The SMUSD instruction interprets the va lues from the first and second operands as two’s complement signed
integers. This instruction:
Optionally rotates the halfwords of the second operand.
Performs two signed 16 × 16-bit multiplications.
Subtracts the result of the top halfword multiplication from the result of the bottom halfword multiplication.
Writes the result of the subtraction to the destination register.
Restrictions
In these instructions:
Do not use SP and do not use PC.
Condition Flags
Sets the Q flag if the addition overflows. The multiplications cannot overflow.
SAM4S Series [DATASHEET]
Atmel-11100K-ATARM-SAM4S-Datasheet_09-Jun-15
156
Examples
SMUAD R0, R4, R5 ; Multiplies bottom halfword of R4 with the bottom
; halfword of R5, adds multiplication of top halfword
; of R4 with top halfword of R5, writes to R0
SMUADX R3, R7, R4 ; Multiplies bottom halfword of R7 with top halfword
; of R4, adds multiplication of top halfword of R7
; with bottom halfword of R4, writes to R3
SMUSD R3, R6, R2 ; Multiplies bottom halfword of R4 with bottom halfword
; of R6, subtracts multiplication of top halfword of R6
; with top halfword of R3, writes to R3
SMUSDX R4, R5, R3 ; Multiplies bottom halfword of R5 with top halfword of
; R3, subtracts multiplication of top halfword of R5
; with bottom halfword of R3, writes to R4.
12.6.6.10 SMUL and SMULW
Signed Multiply (halfwords) and Signed Multiply (word by halfword)
Syntax op{XY}{cond} Rd,Rn, Rm
op{Y}{cond} Rd. Rn, Rm
For SMULXY only:
op is one of:
SMUL{XY} Signed Multiply (halfwords).
X and Y specify which halfword of the source registers Rn and Rm is used as
the first and second multiply operand.
If X is B, then the bottom halfword, bits [15:0] of Rn is used.
If X is T, then the top halfword, bits [31:16] of Rn is used.If Y is B, then the bot
tom halfword, bits [15:0], of Rm is used.
If Y is T, then the top halfword, bits [31:16], of Rm is used.
SMULW{Y} Signed Multiply (word by halfword).
Y specifies which halfword of the source register Rm is used as the second mul
tiply operand.
If Y is B, then the bottom halfword (bits [15:0]) of Rm is used.
If Y is T, then the top halfword (bits [31:16]) of Rm is used.
cond is an optional condition code, see “Conditional Execution” .
Rd is the destinatio n register.
Rn, Rm are registers holding the first and second operands.
Operation
The SMULBB, SMULTB, SMULBT and SMULTT instructions inter prets th e va lues fr om Rn and Rm as four signed
16-bit integers. These instructions:
Multiplies the specified signed halfword, Top or Bottom, values from Rn and Rm.
Writes the 32-bit result of the multiplica tion in Rd.
The SMULWT and SMULWB instructions interprets the values from Rn as a 32-bit signed integer and Rm as two
halfword 16-bit signed integers. These instructions:
Multiplies the first operand and the top, T suffix, or the bottom, B suffix, halfword of the second operand.
Writes the signed most significant 32 bits of the 48-bit result in the destination register.
Restrictions
157
SAM4S Series [DATASHEET]
Atmel-11100K-ATARM-SAM4S-Datasheet_09-Jun-15
In these instructions:
Do not use SP and do not use PC.
RdHi and RdLo must be different registers.
Examples
SMULBT R0, R4, R5 ; Multiplies the bottom halfword of R4 with the
; top halfword of R5, multiplies results and
; writes to R0
SMULBB R0, R4, R5 ; Multiplies the bottom halfword of R4 with the
; bottom halfword of R5, multiplies results and
; writes to R0
SMULTT R0, R4, R5 ; Multiplies the top halfword of R4 with the top
; halfword of R5, multiplies results and writes
; to R0
SMULTB R0, R4, R5 ; Multiplies the top halfword of R4 with the
; bottom halfword of R5, multiplies results and
; and writes to R0
SMULWT R4, R5, R3 ; Multiplies R5 with the top halfword of R3,
; extracts top 32 bits and writes to R4
SMULWB R4, R5, R3 ; Multiplies R5 with the bottom halfword of R3,
; extracts top 32 bits and writes to R4.
SAM4S Series [DATASHEET]
Atmel-11100K-ATARM-SAM4S-Datasheet_09-Jun-15
158
12.6.6.11 UMULL, UMLAL, SMULL, and SMLAL
Signed and Unsigned Long M ultiply, with optional Accumulate, using 32-bit operands and producing a 64-bit
result.
Syntax op{cond} RdLo, RdHi, Rn, Rm
where:
op is one of:
UMULL Unsigned Long Multiply.
UMLAL Unsigned Long Multiply, with Accumulate.
SMULL Signed Long Multiply.
SMLAL Signed Lo ng Multiply, with Accumulate.
cond is an optional condition code, see “Conditional Execution” .
RdHi, RdLo are the destination registers. For UMLAL and SMLAL they also hold the accu
mulating value.
Rn, Rm are registers holding the operands.
Operation
The UMULL instruction interprets the values from Rn and Rm as unsigned integers. It multiplies these integers and
places the least significant 32 bits of the result in RdLo, and the most significant 32 bits of the result in RdHi.
The UMLAL instruction interprets the values from Rn and Rm as unsigned integers. It multiplies these integers,
adds the 64-bit result to the 64-bit unsigned integer contained in RdHi and RdLo, and writes the result back to
RdHi and RdLo.
The SMULL instruction interprets the values from Rn and Rm as two’s complement signed integers. It multiplies
these integers and plac es the least significant 32 bits of the result in RdLo, and the most significant 32 bits of the
result in RdHi.
The SMLAL instruction interprets the values from Rn and Rm as two’s complement signed integers. It multiplies
these integers, adds the 64-bit result to the 64-bit signed integer contained in RdHi and RdLo, and writes the result
back to RdHi and RdLo.
Restrictions
In these instructions:
Do not use SP and do not use PC
RdHi and RdLo must be different registers.
Condition Flags
These instructions do not affect the condition code flags.
Examples UMULL R0, R4, R5, R6 ; Unsigned (R4,R0) = R5 x R6
SMLAL R4, R5, R3, R8 ; Signed (R5,R4) = (R5,R4) + R3 x R8
159
SAM4S Series [DATASHEET]
Atmel-11100K-ATARM-SAM4S-Datasheet_09-Jun-15
12.6.6.12 SDIV and UDIV
Signed Divide and Unsigned Divide.
Syntax SDIV{cond} {Rd,} Rn, Rm
UDIV{cond} {Rd,} Rn, Rm
where:
cond is an optional condition code, see “Conditional Execution” .
Rd is the destinatio n regist er. I f Rd is omitted, the destination register is Rn.
Rn is the register ho ldi ng th e valu e to be div ide d.
Rm is a register holding the divis or.
Operation
SDIV performs a signed integer division of the value in Rn by the value in Rm.
UDIV performs an unsigned integer division of the value in Rn by the value in Rm.
For both instructions, if the value in Rn is not divisible by the value in Rm, the result is rounded towards zero.
Restrictions
Do not use SP and do not use PC
.
Condition Flags
These instructions do not change the flags.
Examples SDIV R0, R2, R4 ; Signed divide, R0 = R2/R4
UDIV R8, R8, R1 ; Unsigned divide, R8 = R8/R1
SAM4S Series [DATASHEET]
Atmel-11100K-ATARM-SAM4S-Datasheet_09-Jun-15
160
12.6.7 Saturating Instructions
The table below shows the saturating instructions.
For signed n-bit saturation, this means that:
If the value to be saturated is less than -2n-1, the result returned is -2n-1
If the value to be saturated is greater than 2n-1-1, the result returned is 2n-1-1
Otherwise, the result returned is the same as the valu e to be saturated.
For unsigned n-bit saturation, this means that:
If the value to be saturated is less than 0, the result returned is 0
If the value to be saturated is greater than 2n-1, the result returned is 2n-1
Otherwise, the result returned is the same as the valu e to be saturated.
If the returned result is different from the value to be saturated, it is called saturation. If saturation occurs, the
instruction sets the Q flag to 1 in the APSR. Otherwise, it leaves the Q flag unchanged. To clear the Q flag to 0, the
MSR
instruction must be used; see “MSR” .
To read the state of the Q flag, the
MRS
instruction must be used; see “MRS” .
Table 12-22. Saturating Instructions
Mnemonic Description
SSAT Signed Saturate
SSAT16 Signed Saturate Halfword
USAT Unsigned Saturate
USAT16 Unsigned Saturate Halfword
QADD Saturating Add
QSUB Saturating Subtract
QSUB16 Saturating Subtract 16
QASX Saturating Add and Subtract with Exchange
QSAX Saturating Subtract and Add with Exchange
QDADD Saturating Double and Add
QDSUB Saturatin g Double and Subtract
UQADD16 Unsigned Saturati ng Add 16
UQADD8 Unsigned Saturating Add 8
UQASX Unsigned Saturating Add and Subtract with Exchange
UQSAX Unsigned Saturating Subtract and Add with Exchange
UQSUB16 Unsigned Saturating Subtract 16
UQSUB8 Unsigned Saturating Subtract 8
161
SAM4S Series [DATASHEET]
Atmel-11100K-ATARM-SAM4S-Datasheet_09-Jun-15
12.6.7.1 SSAT and USAT
Signed Saturate and Unsigned Saturate to any bit position, with optional shift before saturating.
Syntax op{cond} Rd, #n, Rm {, shift #s}
where:
op is one of:
SSAT Saturates a signed value to a signed range.
USAT Saturates a signed value to an unsigned range.
cond is an optional condition code, see “Conditional Execution” .
Rd is the destina tio n re gist er.
n specifies the bit position to saturate to:
n ranges from 1 n ranges from 0 to 31 for USAT.
to 32 for SSAT
Rm is the register containing the value to saturate.
shift #s is an optional shift applied to Rm before saturating. It must be one of the
following:
ASR #s where s is in the range 1 to 31.
LSL #s where s is in the range 0 to 31.
Operation
These instructions saturate to a signed or unsigned n-bit value.
The SSAT instruction applies the specified shift, then saturates to the signed range
-2n–1 ≤x≤2n–1-1.
The USAT instruction applies the specified shift, then saturates to the unsigned range 0 ≤x≤2n-1.
Restrictions
Do not use SP and do not use PC
.
Condition Flags
These instructions do not affect the condition code flags.
If saturation occurs, these instructions set the Q flag to 1.
Examples SSAT R7, #16, R7, LSL #4 ; Logical shift left value in R7 by 4, then
; saturate it as a signed 16-bit value and
; write it back to R7
USATNE R0, #7, R5 ; Conditionally saturate value in R5 as an
; unsigned 7 bit value and write it to R0.
SAM4S Series [DATASHEET]
Atmel-11100K-ATARM-SAM4S-Datasheet_09-Jun-15
162
12.6.7.2 SSAT16 and USAT16
Signed Saturate and Unsigned Saturate to any bit position for two halfwords.
Syntax op{cond} Rd, #n, Rm
where:
op is one of:
SSAT16 Saturates a signed halfword value to a signed range.
USAT16 Saturates a signed halfword value to an unsigned range.
cond is an optional condition code, see “Conditional Execution” .
Rd is the destina tio n re gist er.
n specifies the bit position to saturate to:
n ranges from 1 n ranges from 0 to 15 for USAT.
to 16 for SSAT
Rm is the register containing the value to saturate.
Operation
The SSAT16 instruction:
Saturates two signed 16-bit halfword values of the register with the value to saturate from selected by the bit
position in n.
Writes the results as two signed 16-bit halfwords to the destination register.
The USAT16 instruction:
Saturates two unsigned 16-bit halfword values of the register with the value to saturate from selected by the bit
position in n.
Writes the results as two unsigned halfwords in the destination register.
Restrictions
Do not use SP and do not use PC
.
Condition Flags
These instructions do not affect the condition code flags.
If saturation occurs, these instructions set the Q flag to 1.
Examples
SSAT16 R7, #9, R2 ; Saturates the top and bottom highwords of R2
; as 9-bit values, writes to corresponding halfword
; of R7
USAT16NE R0, #13, R5 ; Conditionally saturates the top and bottom
; halfwords of R5 as 13-bit values, writes to
; corresponding halfword of R0.
12.6.7.3 QADD and QSUB
Saturating Add and Saturating Subtract, signed.
Syntax op{cond} {Rd}, Rn, Rm
op{cond} {Rd}, Rn, Rm
where:
163
SAM4S Series [DATASHEET]
Atmel-11100K-ATARM-SAM4S-Datasheet_09-Jun-15
op is one of:
QADD Saturating 32-bit add.
QADD8 Saturating four 8-bit integer additions.
QADD16 Saturating two 16-bit integer additions.
QSUB Saturating 32-bit subtraction.
QSUB8 Saturating four 8-bit integer subtraction.
QSUB16 Saturating two 16-bit integer subtraction.
cond is an optional condition code, see “Conditional Execution” .
Rd is the destinatio n register.
Rn, Rm are registers holding the first and second operands.
Operation
These instructions add or subtract two, four or eight values from the first and second operands and then writes a
signed saturated value in the destination register.
The QADD and QSUB instructions apply the specified add or subtract, and then saturate the result to the signed
range -2n–1 ≤x≤2n–1-1, where x is given by the number of bits applied in the instruction, 32, 16 or 8.
If the returned result is different from the value to be saturated, it is called saturation. If saturation occurs, the
QADD and QSUB instructions set the Q flag to 1 in the APSR. Otherwise, it leaves the Q flag unchanged. The 8-bit
and 16-bit QADD and QSUB instructions always leave the Q flag unchanged.
To clear the Q flag to 0, the MSR instruction must be used; see “MSR” .
To read the state of the Q flag, the MRS instruction must be used; see “MRS” .
Restrictions
Do not use SP and do not use PC
.
Condition Flags
These instructions do not affect the condition code flags.
If saturation occurs, these instructions set the Q flag to 1.
SAM4S Series [DATASHEET]
Atmel-11100K-ATARM-SAM4S-Datasheet_09-Jun-15
164
Examples
QADD16 R7, R4, R2 ; Adds halfwords of R4 with corresponding halfword of
; R2, saturates to 16 bits and writes to
; corresponding halfword of R7
QADD8 R3, R1, R6 ; Adds bytes of R1 to the corresponding bytes of R6,
; saturates to 8 bits and writes to corresponding
; byte of R3
QSUB16 R4, R2, R3 ; Subtracts halfwords of R3 from corresponding
; halfword of R2, saturates to 16 bits, writes to
; corresponding halfword of R4
QSUB8 R4, R2, R5 ; Subtracts bytes of R5 from the corresponding byte
; in R2, saturates to 8 bits, writes to corresponding
; byte of R4.
12.6.7.4 QASX and QSAX
Saturating Add and Subtract with Exchange and Saturating Subtract and Ad d with Exchange, signed.
Syntax op{cond} {Rd}, Rm, Rn
where:
op is one of:
QASX Add and Subtract with Exchange and Saturate.
QSAX Subtract and Add with Exchange and Saturate.
cond is an optional condition code, see “Conditional Execution” .
Rd is the destinatio n register.
Rn, Rm are registers holding the first and second operands.
Operation
The QASX instruction:
1. Adds the top halfword of the source operand with the bottom halfword of the second operand.
2. Subtracts the top halfword of the second oper and from the bottom highword of the first operand.
3. Saturates the result of the subtraction and wr ites a 16-bit signed integer in the range –215 ≤ x ≤ 215 – 1,
where x equals 16, to the bottom halfword of the destination register.
4. Saturates the results of the sum and writes a 16-bit signed integer in the range
–215 ≤ x ≤ 215 – 1, where x equals 16, to the top halfword of the destination register.
The QSAX instruction:
1. Subtracts the bottom halfw ord of the second operand fr om the top highword of the first operand.
2. Adds the bottom halfword of the source operand with the top halfword of the second operand.
3. Saturates the results of the sum and writes a 16-bit signed integer in the range
–215 ≤ x ≤ 215 – 1, where
x
equals 16, to the bottom halfword of the destination register.
4. Saturates the result of the subtraction and wr ites a 16-bit signed integer in the range –215 ≤ x ≤ 215 – 1,
where
x
equals 16, to the top halfword of the destination register.
Restrictions
Do not use SP and do not use PC
.
Condition Flags
These instructions do not affect the condition code flags.
165
SAM4S Series [DATASHEET]
Atmel-11100K-ATARM-SAM4S-Datasheet_09-Jun-15
Examples
QASX R7, R4, R2 ; Adds top halfword of R4 to bottom halfword of R2,
; saturates to 16 bits, writes to top halfword of R7
; Subtracts top highword of R2 from bottom halfword of
; R4, saturates to 16 bits and writes to bottom halfword
; of R7
QSAX R0, R3, R5 ; Subtracts bottom halfword of R5 from top halfword of
; R3, saturates to 16 bits, writes to top halfword of R0
; Adds bottom halfword of R3 to top halfword of R5,
; saturates to 16 bits, writes to bottom halfword of R0.
SAM4S Series [DATASHEET]
Atmel-11100K-ATARM-SAM4S-Datasheet_09-Jun-15
166
12.6.7.5 QDADD and QDSUB
Saturating Double and Add and Saturating Double and Subtract, signed.
Syntax op{cond} {Rd}, Rm, Rn
where:
op is one of:
QDADD Saturatin g Dou b le an d Ad d.
QDSUB Saturating Double and Subtract.
cond is an optional condition code, see “Conditional Execution” .
Rd is the destinatio n regist er.
Rm, Rn are registers holding the first and second operands.
Operation
The QDADD instruction:
Doubles the second operand value.
Adds the result of the doubling to the signed saturated value in the first operand.
Writes the result to the destination register.
The QDSUB instruction:
Doubles the second operand value.
Subtracts the doubled value from the signed saturated value in the first operand.
Writes the result to the destination register.
Both the doubling and the addition or subtraction have their results saturated to the 32-bit signed integer range –
231 ≤ x ≤ 231– 1. If saturation occurs in either operation, it sets the Q flag in the APSR.
Restrictions
Do not use SP and do not use PC
.
Condition Flags
If saturation occurs, these instructions set the Q flag to 1.
Examples
QDADD R7, R4, R2 ; Doubles and saturates R4 to 32 bits, adds R2,
; saturates to 32 bits, writes to R7
QDSUB R0, R3, R5 ; Subtracts R3 doubled and saturated to 32 bits
; from R5, saturates to 32 bits, writes to R0.
167
SAM4S Series [DATASHEET]
Atmel-11100K-ATARM-SAM4S-Datasheet_09-Jun-15
12.6.7.6 UQASX and UQSAX
Saturating Add and Subtract with Exchange and Saturating Subtract and Add with Exchange, unsigned.
Syntax op{cond} {Rd}, Rm, Rn
where:
type is one of:
UQASX Add and Subtract with Exchange and Saturate.
UQSAX Subtract and Add with Exchange and Saturate.
cond is an optional condition code, see “Conditional Execution” .
Rd is the destinatio n register.
Rn, Rm are registers holding the first and second operands.
Operation
The UQASX instruction:
1. Adds the bottom halfword of the source operand with the top halfword of the second operand.
2. Subtracts the bottom halfword of the second operand from the top highword of the first operand.
3. Saturates the results of the sum and writes a 16-bit unsigned integer in the range
0 ≤ x ≤ 216 – 1, where x equals 16, to the top halfword of the destination register.
4. Saturates the result of the subtraction and writes a 16-bit unsigned integer in th e range 0 ≤ x ≤ 216 – 1, where
x equals 16, to the bottom halfword of the destination register.
The UQSAX instruction:
1. Subtracts the bottom halfw ord of the second operand fr om the top highword of the first operand.
2. Adds the bottom halfword of the first operand with the top halfword of the second operand.
3. Saturates the result of the subtraction and writes a 16-bit unsigned integer in th e range 0 ≤ x ≤ 216 – 1, where
x
equals 16, to the top halfword of the destination register.
4. Saturates the results of the ad dition and writes a 16-bit unsigned integ er in the ra nge 0 ≤ x ≤ 216 – 1, where
x
equals 16, to the bottom halfword of the destination register.
Restrictions
Do not use SP and do not use PC
.
Condition Flags
These instructions do not affect the condition code flags.
SAM4S Series [DATASHEET]
Atmel-11100K-ATARM-SAM4S-Datasheet_09-Jun-15
168
Examples
UQASX R7, R4, R2 ; Adds top halfword of R4 with bottom halfword of R2,
; saturates to 16 bits, writes to top halfword of R7
; Subtracts top halfword of R2 from bottom halfword of
; R4, saturates to 16 bits, writes to bottom halfword of R7
UQSAX R0, R3, R5 ; Subtracts bottom halfword of R5 from top halfword of R3,
; saturates to 16 bits, writes to top halfword of R0
; Adds bottom halfword of R4 to top halfword of R5
; saturates to 16 bits, writes to bottom halfword of R0.
12.6.7.7 UQADD and UQSUB
Saturating Add and Saturating Subtract Unsigned.
Syntax op{cond} {Rd}, Rn, Rm
op{cond} {Rd}, Rn, Rm
where:
op is one of:
UQADD8 Saturating four unsigned 8-bit integer additions.
UQADD16 Saturating two unsigned 16 -bit integer additions.
UDSUB8 Saturating four unsigned 8-bit integer subtractions.
UQSUB16 Saturating two unsigned 16-bit integer subtractions.
cond is an optional condition code, see “Conditional Execution” .
Rd is the destinatio n regist er.
Rn, Rm are registers holding the first and second operands.
Operation
These instructions add or subtract two or four values and then writes an unsigned saturated value in the
destination register.
The UQADD16 instruction:
Adds the respective top and bottom halfwords of the first and second operands.
Saturates the result of the additions for each halfword in the destination register to the unsigned range
0≤x≤216-1, where x is 16.
The UQADD8 instruction:
Adds each respective byte of the first and second operands.
Saturates the result of the addition for each byte in the destination register to the unsigned range 0 ≤x≤28-
1, where x is 8.
The UQSUB16 instruction:
Subtracts both halfwords of the second operand from the respective halfwords of the first operand.
Saturates the result of the dif ferences in the de stination register to the unsigned range 0 ≤x≤216-1, where x
is 16.
The UQSUB8 instructions:
Subtracts the respective bytes of the second operand from the respective bytes of the first operand.
Saturates the results of the differences for each byte in the destination register to the unsigned range
0≤x≤28-1, where x is 8.
169
SAM4S Series [DATASHEET]
Atmel-11100K-ATARM-SAM4S-Datasheet_09-Jun-15
Restrictions
Do not use SP and do not use PC
.
Condition Flags
These instructions do not affect the condition code flags.
Examples
UQADD16 R7, R4, R2 ; Adds halfwords in R4 to corresponding halfword in R2,
; saturates to 16 bits, writes to corresponding halfword of R7
UQADD8 R4, R2, R5 ; Adds bytes of R2 to corresponding byte of R5, saturates
; to 8 bits, writes to corresponding bytes of R4
UQSUB16 R6, R3, R0 ; Subtracts halfwords in R0 from corresponding halfword
; in R3, saturates to 16 bits, writes to corresponding
; halfword in R6
UQSUB8 R1, R5, R6 ; Subtracts bytes in R6 from corresponding byte of R5,
; saturates to 8 bits, writes to corresponding byte of R1.
SAM4S Series [DATASHEET]
Atmel-11100K-ATARM-SAM4S-Datasheet_09-Jun-15
170
12.6.8 Packing and Unpacking Instructions
The table below shows the instructions that operate on packing and unpacking data.
Table 12-23. Packing and Unpacking Instructions
Mnemonic Description
PKH Pack Halfword
SXTAB Extend 8 bits to 32 and add
SXTAB16 Dual extend 8 bits to 16 and add
SXTAH Extend 16 bits to 32 and add
SXTB Sign extend a byte
SXTB16 Dual extend 8 bits to 16 and add
SXTH Sign extend a halfword
UXTAB Extend 8 bits to 32 and add
UXTAB16 Dual extend 8 bits to 16 and add
UXTAH Extend 16 bits to 32 and add
UXTB Zero extend a byte
UXTB16 Dual zero extend 8 bits to 16 and add
UXTH Zero extend a halfword
171
SAM4S Series [DATASHEET]
Atmel-11100K-ATARM-SAM4S-Datasheet_09-Jun-15
12.6.8.1 PKHBT and PKHTB
Pack Halfword
Syntax op{cond} {Rd}, Rn, Rm {, LSL #imm}
op{cond} {Rd}, Rn, Rm {, ASR #imm}
where:
op is one of:
PKHBT Pack Halfword, bottom and top with shift.
PKHTB Pack Halfword, top and bottom with shift.
cond is an optional condition code, see “Conditional Execution” .
Rd is the destinatio n regist er.
Rn is the first operan d re gis te r
Rm is the second operand register holding the value to be optionally shifted.
imm is the shift length. The type of shift length depends on the instruction:
For PKHBT
LSL a left shift with a shift length from 1 to 31, 0 means no shift.
For PKHTB
ASR an arithmetic shift right with a shift length from 1 to 32,
a shift of 32-bits is encoded as 0b00000.
Operation
The PKHBT instruction:
1. Writes the value of the bottom halfword of the first operand to the bottom halfword of the destination
register.
2. If shifted, the shifted value of the second operand is wr itte n to the to p ha lfwor d of th e de stin a tio n re gist er.
The PKHTB instruction:
1. Writes the value of the top halfword of the first operand to the top halfwor d of the destination register.
2. If shifted, the shifted va lue of the second oper and is written to the bottom halfword of the destination register .
Restrictions
Rd
must not be SP and must not be PC.
Condition Flags
This instruction does not change the flags.
SAM4S Series [DATASHEET]
Atmel-11100K-ATARM-SAM4S-Datasheet_09-Jun-15
172
Examples
PKHBT R3, R4, R5 LSL #0 ; Writes bottom halfword of R4 to bottom halfword of
; R3, writes top halfword of R5, unshifted, to top
; halfword of R3
PKHTB R4, R0, R2 ASR #1 ; Writes R2 shifted right by 1 bit to bottom halfword
; of R4, and writes top halfword of R0 to top
; halfword of R4.
12.6.8.2 SXT and UXT
Sign extend and Zero extend.
Syntax op{cond} {Rd,} Rm {, ROR #n}
op{cond} {Rd}, Rm {, ROR #n}
where:
op is one of:
SXTB Sign extends an 8-bit value to a 32-bit value.
SXTH Sign extends a 16-bit value to a 32-bit value.
SXTB16 Sign extends two 8-bit values to two 16-bit values.
UXTB Zero extend s an 8-bit valu e to a 32 -b it va lue .
UXTH Zero extends a 16-bit value to a 32-bit value.
UXTB16 Zero extends two 8-bit values to two 16-bit values.
cond is an optional condition code, see “Conditional Execution” .
Rd is the destinatio n register.
Rm is the register holding the value to extend.
ROR #n is one of:
ROR #8 Value from Rm is rotated right 8 bits.
Operation
These instructions do the following:
1. Rotate the value from Rm right by 0, 8, 16 or 24 bits.
2. Extract bits from the resulting value:
SXTB extracts bits[7:0] and sign extends to 32 bits.
UXTB extracts bits[7:0] and zero extends to 32 bits.
SXTH extracts bits[15:0] and sign extends to 32 bits.
UXTH extracts bits[15:0] and zero extends to 32 bits.
SXTB16 extracts bits[7:0] and sign extends to 16 bits,
and extracts bits [23:16] and sign extends to 16 bits.
UXTB16 extracts bits[7:0] and zero extends to 16 bits,
and extracts bits [23:16] and zero extends to 16 bits.
Restrictions
Do not use SP and do not use PC.
Condition Flags
These instructions do not affect the flags.
173
SAM4S Series [DATASHEET]
Atmel-11100K-ATARM-SAM4S-Datasheet_09-Jun-15
Examples
SXTH R4, R6, ROR #16 ; Rotates R6 right by 16 bits, obtains bottom halfword of
; of result, sign extends to 32 bits and writes to R4
UXTB R3, R10 ; Extracts lowest byte of value in R10, zero extends, and
; writes to R3.
12.6.8.3 SXTA and UXTA
Signed and Unsigned Extend and Add
Syntax op{cond} {Rd,} Rn, Rm {, ROR #n}
op{cond} {Rd,} Rn, Rm {, ROR #n}
where:
op is one of:
SXTAB Sign extends an 8-bit value to a 32-bit value and add.
SXTAH Sign extends a 16-bit value to a 32-bit value and add.
SXTAB16 Sign extends two 8-bit values to two 16-bit values and add.
UXTAB Zero extends an 8-bit value to a 32-bit value and add.
UXTAH Zero extends a 16-bit value to a 32-bit value and add .
UXTAB16 Zero extends two 8-bit values to two 16-bit values and add.
cond is an optional condition code, see “Conditional Execution” .
Rd is the destinatio n register.
Rn is the first operan d re gis te r.
Rm is the register holding the value to rotate and extend.
ROR #n is one of:
ROR #8 Value from Rm is rotated right 8 bits.
ROR #16 Value from Rm is rotated right 16 bits.
ROR #24 Value from Rm is rotated right 24 bits.
If ROR #n is omitted, no rotation is performed.
Operation
These instructions do the following:
1. Rotate the value from Rm right by 0, 8, 16 or 24 bits.
2. Extract bits from the resulting value:
SXTAB extracts bits[7:0] from Rm and sign extends to 32 bits.
UXTAB extracts bits[7:0] from Rm and zero extends to 32 bits.
SXTAH extracts bits[15:0] from Rm and sign extends to 32 bits.
UXTAH extracts bits[15:0] from Rm and zero extends to 32 bits.
SXTAB16 extracts bits[7:0] from Rm and sign extends to 16 bits,
and extracts bits [23:16] from Rm and sign extends to 16 bits.
UXTAB16 extracts bits[7:0] from Rm and zero extends to 16 bits,
and extracts bits [23:16] from Rm and zero extends to 16 bits.
3. Adds the signed or zero extended value to th e wo rd or corre sponding halfwo rd o f Rn and writes the result in
Rd.
SAM4S Series [DATASHEET]
Atmel-11100K-ATARM-SAM4S-Datasheet_09-Jun-15
174
Restrictions
Do not use SP and do not use PC.
Condition Flags
These instructions do not affect the flags.
Examples
SXTAH R4, R8, R6, ROR #16 ; Rotates R6 right by 16 bits, obtains bottom
; halfword, sign extends to 32 bits, adds
; R8,and writes to R4
UXTAB R3, R4, R10 ; Extracts bottom byte of R10 and zero extends
; to 32 bits, adds R4, and writes to R3.
175
SAM4S Series [DATASHEET]
Atmel-11100K-ATARM-SAM4S-Datasheet_09-Jun-15
12.6.9 Bi tfield Instructions
The table below shows the instructions that operate on adjacent sets of bits in register s or bitfields.
Table 12-24. Packing and Unpacking Instructions
Mnemonic Description
BFC Bit Field Clear
BFI Bit Field Insert
SBFX Signed Bit Field Extract
SXTB Sign extend a byte
SXTH Sign extend a halfwo rd
UBFX Unsigned Bit Field Extract
UXTB Zero extend a byte
UXTH Zero extend a halfword
SAM4S Series [DATASHEET]
Atmel-11100K-ATARM-SAM4S-Datasheet_09-Jun-15
176
12.6.9.1 BFC and BFI
Bit Field Clear and Bit Field Insert.
Syntax BFC{cond} Rd, #lsb, #width
BFI{cond} Rd, Rn, #lsb, #width
where:
cond is an optional condition code, see “Conditional Execution” .
Rd is the destinatio n regist er.
Rn is the source register.
lsb is the position of the least significant bit of the bitfield. lsb must be in the range
0 to 31.
width is the width of the bitfield and must be in the range 1 to 32-lsb.
Operation
BFC clears a bitfield in a register. It clears width bits in Rd, starting at the low bit position lsb. Other bits in Rd are
unchanged.
BFI copies a bitfield into one register from another register. It replaces width bits in Rd starting at the low bit
position lsb, with width bits from Rn starting at bit[0]. Other bits in Rd are unchanged.
Restrictions
Do not use SP and do not use PC.
Condition Flags
These instructions do not affect the flags.
Examples BFC R4, #8, #12 ; Clear bit 8 to bit 19 (12 bits) of R4 to 0
BFI R9, R2, #8, #12 ; Replace bit 8 to bit 19 (12 bits) of R9 with
; bit 0 to bit 11 from R2.
177
SAM4S Series [DATASHEET]
Atmel-11100K-ATARM-SAM4S-Datasheet_09-Jun-15
12.6.9.2 SBFX and UBFX
Signed Bit Field Extract and Unsigned Bit Field Extract.
Syntax SBFX{cond} Rd, Rn, #lsb, #width
UBFX{cond} Rd, Rn, #lsb, #width
where:
cond is an optional condition code, see “Conditional Execution” .
Rd is the destinatio n regist er.
Rn is the source register.
lsb is the position of the least significant bit of the bitfield. lsb must be in the range
0 to 31.
width is the width of the bitfield and must be in the range 1 to 32-lsb.
Operation
SBFX extracts a bitfield from one register , sign extends it to 32 bits, and writes the r esult to the destination register.
UBFX extracts a bitfield from one register, zero extends it to 32 bits, and writes the result to the destination
register.
Restrictions
Do not use SP and do not use PC
.
Condition Flags
These instructions do not affect the flags.
Examples
SBFX R0, R1, #20, #4 ; Extract bit 20 to bit 23 (4 bits) from R1 and sign
; extend to 32 bits and then write the result to R0.
UBFX R8, R11, #9, #10 ; Extract bit 9 to bit 18 (10 bits) from R11 and zero
; extend to 32 bits and then write the result to R8.
SAM4S Series [DATASHEET]
Atmel-11100K-ATARM-SAM4S-Datasheet_09-Jun-15
178
12.6.9.3 SXT and UXT
Sign extend and Zero extend.
Syntax SXTextend{cond} {Rd,} Rm {, ROR #n}
UXTextend{cond} {Rd}, Rm {, ROR #n}
where:
extend is one of:
B Extends an 8-bit value to a 32-bit value.
H Extends a 16-bit value to a 32-bit value.
cond is an optional condition code, see “Conditional Execution” .
Rd is the destinatio n regist er.
Rm is the register holding the value to extend.
ROR #n is one of:
ROR #8 Value from Rm is rotated right 8 bits.
ROR #16 Value from Rm is rotated right 16 bits.
ROR #24 Value from Rm is rotated right 24 bits.
If ROR #n is omitted, no rotation is performed.
Operation
These instructions do the following:
1. Rotate the value from Rm right by 0, 8, 16 or 24 bits.
2. Extract bits from the resulting value:
SXTB extracts bits[7:0] and sign extends to 32 bits.
UXTB extracts bits[7:0] and zero extends to 32 bits.
SXTH extracts bits[15:0] and sign extends to 32 bits.
UXTH extracts bits[15:0] and zero extends to 32 bits.
Restrictions
Do not use SP and do not use PC.
Condition Flags
These instructions do not affect the flags.
Examples
SXTH R4, R6, ROR #16 ; Rotate R6 right by 16 bits, then obtain the lower
; halfword of the result and then sign extend to
; 32 bits and write the result to R4.
UXTB R3, R10 ; Extract lowest byte of the value in R10 and zero
; extend it, and write the result to R3.
179
SAM4S Series [DATASHEET]
Atmel-11100K-ATARM-SAM4S-Datasheet_09-Jun-15
12.6.10 Branch and Control Instructions
The table below shows the branch and control instructions.
Table 12-25. Branch and Control Instructions
Mnemonic Description
BBranch
BL Branch with Link
BLX Branch indirect with Link
BX Branch indirect
CBNZ Compare and Branch if No n Zero
CBZ Compare and Branch if Zero
IT If-Then
TBB Table Branch Byte
TBH Table Branch Halfword
SAM4S Series [DATASHEET]
Atmel-11100K-ATARM-SAM4S-Datasheet_09-Jun-15
180
12.6.10.1 B, BL, BX, and BLX
Branch instructions.
Syntax B{cond} label
BL{cond} label
BX{cond} Rm
BLX{cond} Rm
where:
B is branch (immedia te ).
BL is bran ch with link (imm e dia te ).
BX is branch indirect (register).
BLX is branch indirect with link (register).
cond is an optional condition code, see “Conditional Execution” .
label is a PC-relative ex pr es sio n. See “PC-relative Expressions” .
Rm is a register that indicates an address to branch to. Bit[0] of the value in Rm
must be 1, but the address to branch to is created by changing bit[0] to 0.
Operation
All these instructions cause a branch to label, or to the address indicated in Rm. In addition:
The BL and BLX instruc tion s writ e th e ad dr es s of the next instruction to LR (the link register, R14).
The BX and BLX instructions result in a UsageFault exception if bit[0] of Rm is 0.
Bcond label is the only conditional instruction that can be either inside or outside an IT block. All other branch
instructions must be conditional inside an IT block, and must be unconditional outside the IT block, see “IT” .
The table below shows the ranges fo r the various branch instructions.
The .W suffix might be used to get the maximum branch range. See “Instruction Width Selection” .
Restrictions
The restrictions are:
Do not use PC in the BLX instruction
For BX and BLX, bit[0] of Rm must be 1 for correct execution but a branch occurs to the target address
created by changing bit[0] to 0
When any of thes e inst ru ctio n s is inside an IT bl oc k, it must be the last instruction of the IT block.
B
cond is the only conditional instruction that is not re quired to be inside an IT block. However, it has a longer
branch range when it is inside an IT block.
Table 12-26. Branch Ranges
Instruction Branch Range
B label −16 MB to +16 MB
Bcond label
(outside IT block) −1 MB to +1 MB
Bcond label
(inside IT block) −16 MB to +16 MB
BL{cond} label −16 MB to +16 MB
BX{cond} Rm Any value in registe r
BLX{cond} Rm Any value in register
181
SAM4S Series [DATASHEET]
Atmel-11100K-ATARM-SAM4S-Datasheet_09-Jun-15
Condition Flags
These instructions do not change the flags.
Examples
B loopA ; Branch to loopA
BLE ng ; Conditionally branch to label ng
B.W target ; Branch to target within 16MB range
BEQ target ; Conditionally branch to target
BEQ.W target ; Conditionally branch to target within 1MB
BL funC ; Branch with link (Call) to function funC, return address
; stored in LR
BX LR ; Return from function call
BXNE R0 ; Conditionally branch to address stored in R0
BLX R0 ; Branch with link and exchange (Call) to a address stored in R0.
SAM4S Series [DATASHEET]
Atmel-11100K-ATARM-SAM4S-Datasheet_09-Jun-15
182
12.6.10.2 CBZ and CBNZ
Compare and Branch on Zero, Compare and Branch on Non-Zero.
Syntax CBZ Rn, label
CBNZ Rn, label
where:
Rn is the register hold in g th e op er an d .
label is the branch destin at io n .
Operation
Use the CBZ or CBNZ instructions to avoid changing the condition code flags and to reduce the number of
instructions.
CBZ Rn, label does not change condition flags but is otherwise equivalent to:
CMP Rn, #0
BEQ label
CBNZ Rn, label does not change condition flags but is otherwise equivalent to:
CMP Rn, #0
BNE label
Restrictions
The restrictions are:
Rn must be in the range of R0 to R7
The branch destination must be within 4 to 130 bytes after the instruction
These instructions must not be used inside an IT block.
Condition Flags
These instructions do not change the flags.
Examples CBZ R5, target ; Forward branch if R5 is zero
CBNZ R0, target ; Forward branch if R0 is not zero
183
SAM4S Series [DATASHEET]
Atmel-11100K-ATARM-SAM4S-Datasheet_09-Jun-15
12.6.10.3 IT
If-Then condition instruction.
Syntax IT{x{y{z}}} cond
where:
x specifies the condition switch for the second instruction in the IT block.
y specifies the condition switch for the third instruction in the IT block.
z specifies the condition switch for the fourth instruction in the IT block.
cond specifies the condition for the first instruction in the IT block.
The condition switch for the second, third and four th instruction in the IT block can be either:
T Then. Applies the condition cond to the instruction.
E Else. Applies the inverse condition of cond to the instruction.
It is possible to use AL (the always condition) for cond in an IT instruction. If this is done, all of the instructions in
the IT block must be unconditional, and each of x, y, and z must be T or omitted but not E.
Operation
The IT instruction makes up to four following instructions conditional. The conditions can be all the same, or some
of them can be the logical inverse of the others. The conditional instructions following the IT instruction form the IT
block.
The instructions in the IT block, including any branches, must specify the condition in the {cond} part of their
syntax.
The asse mbler mig ht be able to gener ate the required I T instructions for conditional instructions automatically, so
that the user does not have to write them. See the assembler documentation for details.
A BKPT instruction in an IT block is always executed, even if its condition fails.
Exceptions can be taken between an IT instruction and the corresponding IT block, or within an IT block. Such an
exception results in entry to the appropriate exception handler, with suitable return information in LR and stacked
PSR.
Instructions designed for us e for exception returns can be used as normal to return from th e exception, and
execution of the IT block resumes corre ctly. This is the only way that a PC-modifying instruction is permitted to
branch to an instruction in an IT block.
Restrictions
The following instructions are not permitted in an IT block:
IT
CBZ and CBNZ
CPSID and CPSIE.
Other restric tio ns wh en usin g an IT block ar e:
A branch or any instruction that modifies the PC must either be outside an IT block or must be the last
instruction inside the IT block. These are:
ADD PC, PC, Rm
MOV PC, Rm
B, BL, BX, BLX
Any LDM, LDR, or POP instruction that writes to the PC
TBB and TBH
Do not branch to any instruction inside an IT block, except when returning from an exception handler
SAM4S Series [DATASHEET]
Atmel-11100K-ATARM-SAM4S-Datasheet_09-Jun-15
184
All conditional instructions except Bcond must be inside an IT block. Bcond can be either outside or inside
an IT block but has a larger branch range if it is inside one
Each instruction inside the IT block must specify a condition code suffix that is either the same or logical
inverse as for the other instructions in the block.
Your assembler might place extra restrictions on the use of IT blocks, such as prohibiting the use of assembler
directives within them.
Condition Flags
This instruction does not change the flags.
Example ITTE NE ; Next 3 instructions are conditional
ANDNE R0, R0, R1 ; ANDNE does not update condition flags
ADDSNE R2, R2, #1 ; ADDSNE updates condition flags
MOVEQ R2, R3 ; Conditional move
CMP R0, #9 ; Convert R0 hex value (0 to 15) into ASCII
; ('0'-'9', 'A'-'F')
ITE GT ; Next 2 instructions are conditional
ADDGT R1, R0, #55 ; Convert 0xA -> 'A'
ADDLE R1, R0, #48 ; Convert 0x0 -> '0'
IT GT ; IT block with only one conditional instruction
ADDGT R1, R1, #1 ; Increment R1 conditionally
ITTEE EQ ; Next 4 instructions are conditional
MOVEQ R0, R1 ; Conditional move
ADDEQ R2, R2, #10 ; Conditional add
ANDNE R3, R3, #1 ; Conditional AND
BNE.W dloop ; Branch instruction can only be used in the last
; instruction of an IT block
IT NE ; Next instruction is conditional
ADD R0, R0, R1 ; Syntax error: no condition code used in IT block
12.6.10.4 TBB and TBH
Table Branch Byte and Table Branch Halfword.
Syntax TBB [Rn, Rm]
TBH [Rn, Rm, LSL #1]
where:
Rn is the register containing the address of the table of branch lengths.
If Rn is PC, then the address of the table is the address of the byte immediately
following the TBB or TBH instruction.
Rm is the index register. This contains an index into the table. For halfword tables,
LSL #1 doubles the value in Rm to form the right offset into the table.
185
SAM4S Series [DATASHEET]
Atmel-11100K-ATARM-SAM4S-Datasheet_09-Jun-15
Operation
These instructions cause a PC-relative forward branch using a table of single byte offsets for TBB, or halfword
offsets for TBH. Rn provides a pointer to the table, and Rm supplies an index into the table. For TBB the branch
offset is twice the unsigned value of the byte returned from the table. and for TBH the branch offset is twice the
unsigned value of the halfword returned from the table. The branch occurs to the address at that of fset from the
address of the byte immediately after the TBB or TBH instruction.
Restrictions
The restrictions are:
Rn must not be SP
Rm must not be SP and must not be PC
When any of thes e inst ru ctio n s is used inside an IT bl ock, it must be the last instruction of the IT block.
Condition Flags
These instructions do not change the flags.
SAM4S Series [DATASHEET]
Atmel-11100K-ATARM-SAM4S-Datasheet_09-Jun-15
186
Examples ADR.W R0, BranchTable_Byte
TBB [R0, R1] ; R1 is the index, R0 is the base address of the
; branch table
Case1
; an instruction sequence follows
Case2
; an instruction sequence follows
Case3
; an instruction sequence follows
BranchTable_Byte
DCB 0 ; Case1 offset calculation
DCB ((Case2-Case1)/2) ; Case2 offset calculation
DCB ((Case3-Case1)/2) ; Case3 offset calculation
TBH [PC, R1, LSL #1] ; R1 is the index, PC is used as base of the
; branch table
BranchTable_H
DCI ((CaseA - BranchTable_H)/2) ; CaseA offset calculation
DCI ((CaseB - BranchTable_H)/2) ; CaseB offset calculation
DCI ((CaseC - BranchTable_H)/2) ; CaseC offset calculation
CaseA
; an instruction sequence follows
CaseB
; an instruction sequence follows
CaseC
; an instruction sequence follows
187
SAM4S Series [DATASHEET]
Atmel-11100K-ATARM-SAM4S-Datasheet_09-Jun-15
12.6.11 Miscellaneous Instructions
The table below shows the remaining Cortex-M4 instructions.
Table 12-27. Miscellaneous Instruction s
Mnemonic Description
BKPT Breakpoint
CPSID Change Processor State, Disable Interrupts
CPSIE Change Processor State, Enable Interrupts
DMB Data Memory Barrier
DSB Data Synchronization Barrier
ISB Instruction Synchronization Barrier
MRS Move from special register to register
MSR Move from register to special register
NOP No Operation
SEV Send Event
SVC Supervisor Call
WFE Wait For Event
WFI Wait For Inte rrupt
SAM4S Series [DATASHEET]
Atmel-11100K-ATARM-SAM4S-Datasheet_09-Jun-15
188
12.6.11.1 BKPT
Breakpoint.
Syntax BKPT #imm
where:
imm is an expression evaluating to an integer in the range 0–255 (8-bit value).
Operation
The BKPT instruction causes the processor to enter Debug state. Debug tools can use this to investigate system
state when the instruction at a particular address is reached.
imm is ignored by the processor. If required, a debugg er can use it to store additional information about the
breakpoint.
The BKPT instruction can be placed inside an IT b lock, bu t it executes unconditionally, unaffected by the condition
specified by the IT instruction.
Condition Flags
This instruction does not change the flags.
Examples
BKPT 0xAB ; Breakpoint with immediate value set to 0xAB (debugger can
; extract the immediate value by locating it using the PC)
Note: ARM does not recommend the use of the BKPT instruction with an immediate value set to 0xAB for any purpose other
than Semi-hosting.
12.6.11.2 CPS
Change Processor State.
Syntax CPSeffect iflags
where:
effect is one of:
IE Clears the special purpose register.
ID Sets the specia l pu rpos e re gis ter .
iflags is a se qu en ce of one or mor e flags :
i Set or clear PRIMASK.
f Set or clear FAULTMASK.
Operation
CPS changes the PRIMASK and FAULTMASK special register values. See “Exception Mask Registers” for more
information about these registers.
Restrictions
The restrictions are:
Use CPS only from privileged software, it has no effect if used in unprivileged software
CPS cannot be conditional and so must not be used inside an IT block.
189
SAM4S Series [DATASHEET]
Atmel-11100K-ATARM-SAM4S-Datasheet_09-Jun-15
Condition Flags
This instruction does not change the condition flags.
Examples
CPSID i ; Disable interrupts and configurable fault handlers (set PRIMASK)
CPSID f ; Disable interrupts and all fault handlers (set FAULTMASK)
CPSIE i ; Enable interrupts and configurable fault handlers (clear PRIMASK)
CPSIE f ; Enable interrupts and fault handlers (clear FAULTMASK)
12.6.11.3 DMB
Data Memory Barrier.
Syntax DMB{cond}
where:
cond is an optional condition code, see “Conditional Execution” .
Operation
DMB acts as a data memory barrier. It ensures that all explicit memory accesses that appear, in program order,
before the DMB instruction are completed before any explicit memory accesses tha t appear, in program order,
after the DMB instruction. DMB does not affect the ordering or execution of instructions that do not access
memory.
Condition Flags
This instruction does not change the flags.
Examples DMB ; Data Memory Barrier
SAM4S Series [DATASHEET]
Atmel-11100K-ATARM-SAM4S-Datasheet_09-Jun-15
190
12.6.11.4 DSB
Data Synchronization Barrier.
Syntax DSB{cond}
where:
cond is an optional condition code, see “Conditional Execution” .
Operation
DSB acts as a special data synchro nization memory barrier. Instructions that come after the DSB, in program
order, do not execute until the DSB instru ction completes. The DSB instruction completes when all explicit memory
accesses before it complete.
Condition Flags
This instruction does not change the flags.
Examples DSB ; Data Synchronisation Barrier
12.6.11.5 ISB
Instruction Synchronization Barrier.
Syntax ISB{cond}
where:
cond is an optional condition code, see “Conditional Execution” .
Operation
ISB acts as an instruction synchr onization barrier. It flushes the pipeline o f the processor, so that all instruction s
following the ISB are fetched from cache or memory again, after the ISB instruction has been completed.
Condition Flags
This instruction does not change the flags.
Examples ISB ; Instruction Synchronisation Barrier
191
SAM4S Series [DATASHEET]
Atmel-11100K-ATARM-SAM4S-Datasheet_09-Jun-15
12.6.11.6 MRS
Move the contents of a special register to a general-purpose register.
Syntax MRS{cond} Rd, spec_reg
where:
cond is an optional condition code, see “Conditional Execution” .
Rd is the destinatio n register.
spec_reg can be any of: APSR, IPSR, EPSR, IEPSR, IAPSR, EAPSR, PSR, MSP, PSP,
PRIMASK, BASEPRI, BASEPRI_MAX, FAULTMASK, or CONTROL.
Operation
Use MRS in combination with MSR as part of a read-modify-write sequence for updating a PSR, for example to
clear the Q flag.
In process swap code, the programmers model state of the process being swapped out must be saved, including
relevant PSR contents. Similarly, the state of the process being swapped in must also be restored. These
operations use MRS in the state-sa ving instruction sequence and MSR in the state-restoring in struction sequence.
Note: BASEPRI_MAX is an alias of BASEPRI when used with the MRS instruction.
See “MSR” .
Restrictions
Rd must not be SP and must not be PC.
Condition Flags
This instruction does not change the flags.
Examples MRS R0, PRIMASK ; Read PRIMASK value and write it to R0
12.6.11.7 MSR
Move the contents of a general-purpose register into the specified special register.
Syntax MSR{cond} spec_reg, Rn
where:
cond is an optional condition code, see “Conditional Execution” .
Rn is the source register.
spec_reg can be any of: APSR, IPSR, EPSR, IEPSR, IAPSR, EAPSR, PSR, MSP, PSP,
PRIMASK, BASEPRI, BASEPRI_MAX, FAULTMASK, or CONTROL.
SAM4S Series [DATASHEET]
Atmel-11100K-ATARM-SAM4S-Datasheet_09-Jun-15
192
Operation
The register access operation in MSR depends on the privilege level. Unprivileged software can only access the
APSR. See “Application Program Status Register” . Privileged software can access all special registers.
In unprivileged software writes to unallocated or execution state bits in the PSR are ignored.
Note: When the user writes to BASEPRI_MAX, the instruction writes to BASEPRI only if either:
Rn is non-zero and the current BASEPRI value is 0
Rn is non-zero and less than the current BASEPRI value.
See “MRS” .
Restrictions
Rn must not be SP and must not be PC.
Condition Flags
This instruction up da te s th e flag s ex plicit ly ba sed on the va lue in Rn.
Examples
MSR CONTROL, R1 ; Read R1 value and write it to the CONTROL register
12.6.11.8 NOP
No Operation.
Syntax NOP{cond}
where:
cond is an optional condition code, see “Conditional Execution” .
Operation
NOP does nothing. NOP is not necessarily a time-consuming NOP. The processor might remove it from the
pipeline befo re it reac he s th e exe cu tio n sta g e.
Use NOP for padding, for example to place the following instruction on a 64-bit boundary.
Condition Flags
This instruction does not change the flags.
Examples NOP ; No operation
193
SAM4S Series [DATASHEET]
Atmel-11100K-ATARM-SAM4S-Datasheet_09-Jun-15
12.6.11.9 SEV
Send Event.
Syntax SEV{cond}
where:
cond is an optional condition code, see “Conditional Execution” .
Operation
SEV is a hint instruction that causes an event to be signaled to all processors within a multiprocessor system. It
also sets the local event register to 1, see “Power Management” .
Condition Flags
This instruction does not change the flags.
Examples SEV ; Send Event
12.6.11.10 SVC
Supervisor Call.
Syntax SVC{cond} #imm
where:
cond is an optional condition code, see “Conditional Execution” .
imm is an expression evaluating to an integer in the range 0-255 (8-bit value).
Operation
The SVC instruction causes the SVC exception.
imm is ignored by the proce ssor. If r equired, it can be retrieve d by th e except ion han dler to deter mine what service
is being requested.
Condition Flags
This instruction does not change the flags.
Examples
SVC 0x32 ; Supervisor Call (SVC handler can extract the immediate value
; by locating it via the stacked PC)
SAM4S Series [DATASHEET]
Atmel-11100K-ATARM-SAM4S-Datasheet_09-Jun-15
194
12.6.11.11 WFE
Wait For Event.
Syntax WFE{cond}
where:
cond is an optional condition code, see “Conditional Execution” .
Operation
WFE is a hint instruction.
If the event register is 0, WFE suspends execution until one of the following events occurs:
An exception, unless masked by the exception mask registers or the curr en t prior i ty lev el
An exception enters the Pending state, if SEVONPEND in the System Control Register is set
A Debug Entry request, if Debug is enabled
An event signaled by a peripheral or another processor in a multiprocessor system using the SEV
instruction.
If the event register is 1, WFE clears it to 0 and returns immediately.
For more information, see “Power Management” .
Condition Flags
This instruction does not change the flags.
Examples
WFE ; Wait for event
12.6.11.12 WFI
Wait for Interrupt.
Syntax WFI{cond}
where:
cond is an optional condition code, see “Conditional Execution” .
Operation
WFI is a hint instruction that suspends execution until one of the following events occurs:
An exception
A Debug Entry request, regardless of whether Debug is enabled .
Condition Flags
This instruction does not change the flags.
Examples
WFI ; Wait for interrupt
195
SAM4S Series [DATASHEET]
Atmel-11100K-ATARM-SAM4S-Datasheet_09-Jun-15
12.7 Cortex-M4 Core Peripherals
12.7.1 Peripherals
Nested Vectored Interrupt Controller (NVIC)
The Nested Vectored Interrupt Controller (NVIC) is an embedded interrupt controller that supports low
latency interr up t pr oc es sing . See Section 12.8 ”Nested Vectored Interrupt Contr oller (NVIC)”.
System Control Block (SCB)
The System Control Block (SCB) is the programmers model interface to the processor. It provides system
implementation information and system control, including configuration, control, and reporting of system
exceptions. See Section 12.9 ”System Control Block (SCB)”.
System Timer (SysTick)
The System Timer , SysT ick , is a 24-b it co un t- down time r. Use this as a Real Tim e Opera tin g Syste m
(RTOS) tick timer or as a simple counter. See Section 12.10 ”System Timer ( S ysTick)”.
Memory Protection Unit (MPU)
The Memory Protection Unit (MPU) improves system reliability by defining the memory attributes for different
memory regions. It provides up to eight different regions, and an optional predefined background region.
See Section 12.11 ”Memory Protection Unit (MPU)”.
12.7.2 Ad dress Map
The addre ss ma p of the Priv at e pe rip her al bu s (PPB) is given in the following table.
In register descriptions:
The required privilege gives the privilege level required to access the register, as follows:
Privileged: Only privileged software can access the register.
Unprivileged: Both unprivileged and privileged software can access the register.
Table 12-28. Core Peripheral Register Regions
Address Core Peripheral
0xE000E008–0xE000E00F System Control Block
0xE000E010–0xE000E01F System Timer
0xE000E100–0xE000E4EF Nested Vectored Interrup t Con tro ller
0xE000ED00–0xE000ED3F System control block
0xE000ED90–0xE000EDB8 Memo ry Protection Unit
0xE000EF00–0xE000EF03 Nested Vectored Interrupt Controller
SAM4S Series [DATASHEET]
Atmel-11100K-ATARM-SAM4S-Datasheet_09-Jun-15
196
12.8 Nested Vectored Interrupt Controller (NVIC)
This section describes the NVIC and the registers it uses. The NVIC supports:
Up to 35 interrupts
A programmable priority level of 0–15 for each interrupt. A higher level corresponds to a lower priority, so
level 0 is the highest interrupt priority.
Level detection of interrupt signals
Dynamic reprioritization of interrupts
Grouping of priority values into group priority and subpriority fields
Interrupt tail-chaining
An external Non-maskable interrupt (NM I)
The processor automatically stacks its state on exception entry and unstacks this state on exception exit, with no
instruction ov er he a d. This pr ov id es low latency ex ception handling.
12.8.1 Level-sensitive Interrupts
The processor supports level-sensitive interrupts. A level-sensitive interrupt is held asserted until the peripheral
deasserts the interrupt signal. Typically, this ha ppens because the ISR accesses the peripheral, causing it to clear
the interrupt request.
When the processor enters the ISR, it au tomatically removes the pendin g state fr om the inte rrupt (se e “Hardware
and Software Control of Interrupts” ). For a level-sensitive interrupt, if the signal is not deasserted before the
processor returns from the ISR, the interrupt becomes pending again, and the processor must execute its ISR
again. This means that the peripheral can hold the interrupt signal asserted until it no longer requires servicing.
12.8.1.1 Hardware and Software Control of Interrupts
The Cortex-M4 latches all interrupts. A peripheral interrupt becomes pending for one of the following reasons:
The NVIC detects that the interrupt signal is HIGH and the interrupt is not active
The NVIC detects a rising edge on the interrupt signal
A software writes to the corresponding interrupt set-pending register bit, see “Interrupt Set-pending
Registers” , or to the NVIC_STIR to make an interrupt pending, see “Software Trigger Interrupt Register” .
A pending interrupt remains pending until one of the following :
The processor enters th e ISR for the inte rrupt. This changes the sta te of the interrup t from pendin g to active.
Then:
For a level-sensitive interrupt, when the processor returns from the ISR, the NVIC samples the
interrupt signal. If the signal is asserted, the state of the interrupt changes to pending, which might
cause the processor to immediately re-enter the ISR. Otherwise, the state of the interrupt changes to
inactive.
Software writes to the corresponding interrupt clear-pending register bit.
For a level-sensitive interrupt, if the interrupt signal is still asserted, the state of the interrupt does not
change. Otherwise, the state of the interrupt changes to inactive.
12.8.2 NVIC Design Hints and Tips
Ensure that the software uses corre ctly aligned register accesses. The processor does n ot support unaligned
accesses to NVIC registers. See the individual register descriptions for the supported access sizes.
A interrupt can enter a pending state even if it is disabled. Disabling an interrupt only prevents the processor from
taking that interrupt.
197
SAM4S Series [DATASHEET]
Atmel-11100K-ATARM-SAM4S-Datasheet_09-Jun-15
Before programming SCB_VTOR to relocate the vector table, ensure th at the vector table entries of the new vector
table are set up for fault handlers, NMI an d all enabled exception like interrupts. For more information, see the
“Vector Table Offset Register” .
12.8.2.1 NVIC Programming Hints
The software uses the CPSIE I and CPSID I instructions to enable and disable the interrupts. The CMSIS prov ides
the following intrinsic functions for these instructions:
void __disable_irq(void) // Disable Interrupts
void __enable_irq(void) // Enable Interrupts
In addition, the CMSIS provides a number of functions for NVIC control, including:
The input parameter IRQn is the IRQ number. For more information about these functions, see the CMSIS
documentation.
To improve software efficiency, the CMSIS simplifies the NVIC register presentation. In the CMSIS:
The Set-enable, Clear-enable, Set-pending, Clear-pending and Active Bit registers map to arrays of 32-bit
integers, so that:
The array ISER[0] to ISER[1] corresponds to the registers ISER0–ISER1
The array ICER[0] to ICER[1] corresponds to the regis ters ICER0–ICER 1
The array ISPR[0] to ISPR[1] corresponds to the registers ISPR0–ISPR1
The array ICPR[0] to ICPR[1] corresponds to the regis ters ICPR0–ICPR 1
The array IABR[0] to IABR[1] corresponds to the registers IABR0–IABR1
The Interrupt Priority Re gisters (IPR0–IPR8) provide an 8-bit prior ity field for each interrupt and each register
holds four priority fields.
The CMSIS provides thread-safe code that gives atomic access to the Interrupt Priority Registers. Table 12-30
shows how the interrupts, or IRQ numbers, map onto the interrupt registers and corresponding CMSIS variables
that have one bit per interrupt.
Table 12-2 9. CMSIS Functions for NVIC Con tr ol
CMSIS Interrupt Control Function Description
void NVIC_SetPriorityGrouping(uint32_t priority_grouping) Set the priority grouping
void NVIC_EnableIRQ(IRQn_t IRQn) Enable IRQn
void NVIC_DisableIRQ(IRQn_t IRQn) Disable IRQn
uint32_t NVIC_GetPendingIRQ (IRQn _t IRQn) Return true (IRQ-Number) if IRQn is pending
void NVIC_SetPendingIRQ (IRQn_t IRQn) Set IRQn pending
void NVIC_ClearPendingIRQ (IRQn_t IRQn) Clear IRQn pending status
uint32_t NVIC_GetActive (IRQn_t IRQn) Return the IRQ number of the active interrupt
void NVIC_SetPriority (IRQn_t IRQn, uint32_t priority) Set priority for IRQn
uint32_t NVIC_GetPriority (IRQn_t IRQn) Read priority of IRQn
void NVIC_SystemReset (void) Reset the system
Table 12-30. Mapping of Interrupts
Interrupts
CMSIS Array Elements(1)
Set-enable Clear-enable Set-pending Clear-pending Active Bit
0–31 ISER[0] ICER[0] ISPR[0] ICPR[0] IABR[0]
32–35 ISER[1] ICER[1] ISPR[1] ICPR[1] IABR[1]
SAM4S Series [DATASHEET]
Atmel-11100K-ATARM-SAM4S-Datasheet_09-Jun-15
198
Note: 1. Each array element corresponds to a single NVIC re gister, for example the ICER[0] element corresponds to the
ICER0.
199
SAM4S Series [DATASHEET]
Atmel-11100K-ATARM-SAM4S-Datasheet_09-Jun-15
12.8.3 Nested Vectored Interrupt Controller (NVIC) User Interface
Table 12-3 1. Nested Vectored Interrupt Controller (NVIC) Regi ster Mapping
Offset Register Name Access Reset
0xE000E100 Interrupt Set-enable Register 0 NVIC_ISER0 Read/Write 0x00000000
... ... ... ... ...
0xE000E11C Interrupt Set-enable Register 7 NVIC_ISER7 Read/Write 0x00000000
0XE000E180 I nterrupt Clear-enable Register 0 NVIC_ICER0 Read/Write 0x00000000
... ... ... ... ...
0xE000E19C Interrupt Clear-enable Register 7 NVIC_ICER7 Read/Write 0x00000000
0XE000E200 I nterrupt Set-pending Register 0 NVIC_ISPR0 Read/Write 0 x00000000
... ... ... ... ...
0xE000E21C Interrupt Set-pending Register 7 NVIC_ISPR7 Read/Write 0x00000000
0XE000E280 Interrupt Clear-pending Register 0 NVIC_ICPR0 Read/Write 0x00000000
... ... ... ... ...
0xE000E29C Interrupt Clear-pending Register 7 NVIC_ICPR7 Read/Write 0x00000000
0xE000E300 Interrupt Active Bit Register 0 NVIC_IABR0 Read/Write 0x00000000
... ... ... ... ...
0xE000E31C Interrupt Active Bit Register 7 NVIC_IABR7 Read/Write 0x00000000
0xE000E400 Interrupt Priority Register 0 NVIC_IPR0 Read/Write 0x00000000
... ... ... ... ...
0xE000E420 Interrupt Priority Register 8 NVIC_IPR8 Read/Write 0x00000000
0xE000EF00 Software Trigger Interrup t Reg ister NVIC_STIR Write-only 0x00000000
SAM4S Series [DATASHEET]
Atmel-11100K-ATARM-SAM4S-Datasheet_09-Jun-15
200
12.8.3.1 Interrupt Set-enable Registers
Name: NVIC_ISERx [x=0..7]
Access: Read/Write
Reset: 0x000000000
These registers enable interrupts and show which interrupts are enabled.
• SETENA: Interrupt Set-enable
Write:
0: No effect.
1: Enables the interrupt.
Read:
0: Interrupt disabled.
1: Interrupt enabled.
Notes: 1. If a pending interrupt is enabled, the NVIC activates the interrupt based on its priority.
2. If an interrupt is not enabled, asserting its interrupt signal changes the interrupt state to pending, the NVIC never activates
the interrupt, regardless of its priority.
31 30 29 28 27 26 25 24
SETENA
23 22 21 20 19 18 17 16
SETENA
15 14 13 12 11 10 9 8
SETENA
76543210
SETENA
201
SAM4S Series [DATASHEET]
Atmel-11100K-ATARM-SAM4S-Datasheet_09-Jun-15
12.8.3.2 Interrupt Clear-enable Registers
Name: NVIC_ICERx [x=0..7]
Access: Read/Write
Reset: 0x000000000
These registers disable interrupts, and show which interrupts are enabled.
• CLRENA: Interrupt Clear-enable
Write:
0: No effect.
1: Disables the interrupt.
Read:
0: Interrupt disabled.
1: Interrupt enabled.
31 30 29 28 27 26 25 24
CLRENA
23 22 21 20 19 18 17 16
CLRENA
15 14 13 12 11 10 9 8
CLRENA
76543210
CLRENA
SAM4S Series [DATASHEET]
Atmel-11100K-ATARM-SAM4S-Datasheet_09-Jun-15
202
12.8.3.3 Interrupt Set-pending Registers
Name: NVIC_ISPRx [x=0..7]
Access: Read/Write
Reset: 0x000000000
These registers force interrupts into the pending state, and show which interrupts are pending.
• SETPEND: Interrupt Set-pending
Write:
0: No effect.
1: Changes the interrupt state to pending.
Read:
0: Interrupt is not pending.
1: Interrupt is pending.
Notes: 1. Writing a 1 to an ISPR bit corresponding to an interrup t that is pendi ng has no effect.
2. Writing a 1 to an ISPR bit corresponding to a disabled interrupt sets the state of that interrupt to pending.
31 30 29 28 27 26 25 24
SETPEND
23 22 21 20 19 18 17 16
SETPEND
15 14 13 12 11 10 9 8
SETPEND
76543210
SETPEND
203
SAM4S Series [DATASHEET]
Atmel-11100K-ATARM-SAM4S-Datasheet_09-Jun-15
12.8.3.4 Interrupt Clear-pending Registers
Name: NVIC_ICPRx [x=0..7]
Access: Read/Write
Reset: 0x000000000
These registers remove the pending state from interrupts, and show which interrupts are pending.
• CLRPEND: Interrupt Clear-pending
Write:
0: No effect.
1: Removes the pending state from an interrupt.
Read:
0: Interrupt is not pending.
1: Interrupt is pending.
Note: Writing a 1 to an ICPR bit does not affect the active state of the corresponding interrupt.
31 30 29 28 27 26 25 24
CLRPEND
23 22 21 20 19 18 17 16
CLRPEND
15 14 13 12 11 10 9 8
CLRPEND
76543210
CLRPEND
SAM4S Series [DATASHEET]
Atmel-11100K-ATARM-SAM4S-Datasheet_09-Jun-15
204
12.8.3.5 Interrupt Active Bit Registers
Name: NVIC_IABRx [x=0..7]
Access: Read/Write
Reset: 0x000000000
These registers indicate which interrupts are active.
• ACTIVE: Interrupt Active Flags
0: Interrupt is not active.
1: Interrupt is active.
Note: A bit reads as one if the status of the corresponding interrupt is active, or active and pending.
31 30 29 28 27 26 25 24
ACTIVE
23 22 21 20 19 18 17 16
ACTIVE
15 14 13 12 11 10 9 8
ACTIVE
76543210
ACTIVE
205
SAM4S Series [DATASHEET]
Atmel-11100K-ATARM-SAM4S-Datasheet_09-Jun-15
12.8.3.6 Interrupt Priority Registers
Name: NVIC_IPRx [x=0..8]
Access: Read/Write
Reset: 0x000000000
The NVIC_IPR0– NVI C_ IPR 8 registers provide a 8-bit priority field for each interrupt. These registers are byte- accessible.
Each register holds four priority fields that map up to four elements in the CMSIS interrupt priority array IP[0] to IP[34].
• PRI3: Priority (4m+3)
Priority, Byte Offset 3, refers to register bits [31:24].
• PRI2: Priority (4m+2)
Priority, Byte Offset 2, refers to register bits [23:16].
• PRI1: Priority (4m+1)
Priority, Byte Offset 1, refers to register bits [15:8].
• PRI0: Priority (4m)
Priority, Byte Offset 0, refers to register bits [7:0].
Notes: 1. Each priority field holds a priority value, 0–15. The lower the value, the greater the priority of the corresponding interrupt.
The processor implements only bits[7:4] of each field ; bits[3:0 ] read as zero and ignore writes.
2. For more information about the IP[0] to IP[34] interrupt priority array, that provides the software view of the interrupt
priorities, see Table 12-29, “CMSIS Functions for NVIC Control” .
3. The corresponding IPR number n is given by n = m DIV 4.
4. The byte offset of the required Priority field in this register is m MOD 4.
31 30 29 28 27 26 25 24
PRI3
23 22 21 20 19 18 17 16
PRI2
15 14 13 12 11 10 9 8
PRI1
76543210
PRI0
SAM4S Series [DATASHEET]
Atmel-11100K-ATARM-SAM4S-Datasheet_09-Jun-15
206
12.8.3.7 Software Trigger Interrupt Register
Name: NVIC_STIR
Access: Write-only
Reset: 0x000000000
Write to this register to generate an interrupt from the software.
• INTID: Interrupt ID
Interrupt ID of the interrupt to trigger, in the range 0–239. For example, a value of
0x03
specifies interrupt IRQ3.
31 30 29 28 27 26 25 24
––––––––
23 22 21 20 19 18 17 16
––––––––
15 14 13 12 11 10 9 8
–––––––INTID
76543210
INTID
207
SAM4S Series [DATASHEET]
Atmel-11100K-ATARM-SAM4S-Datasheet_09-Jun-15
12.9 System Control Block (SCB)
The System Control Block (SCB) provides system implementation information, and system control. This includes
configuration, control, and reporting of the system exceptions.
Ensure that the software uses aligned accesses of the correct size to access the system control block registers:
Except for the SCB_CFSR and SCB_SHPR1–SCB_SHPR3 regist ers, it must use aligned word accesses
For the SCB_CFSR and SCB_SHPR1–SCB_SHPR3 registers, it can use byte or aligned halfword or word
accesses.
The processor does not support unaligned accesses to system control block registers.
In a fault handler, to determine the true faulting address:
1. Read and sa ve the MMFAR or SCB_BFAR value.
2. Read the MMARVALID bit in the MMFSR subregister, or the BFARVALID bit in the BFSR subregister. The
SCB_MMFAR or SCB_BFAR address is valid only if this bit is 1.
The software must follow this seque nce because anothe r higher prior ity exception might change the SCB_MMFAR
or SCB_BFAR value. For example, if a higher priority handler preempts the current fault handler, the other fault
might change the SCB_MMFAR or SCB_BFAR value.
SAM4S Series [DATASHEET]
Atmel-11100K-ATARM-SAM4S-Datasheet_09-Jun-15
208
12.9.1 System Control Block (SCB) User Interface
Notes: 1. See the register description for more information.
2. This register contains the subregisters: “MMFSR: Memory Management Fault Status Subregister” (0xE000ED28 - 8 bits),
“BFSR: Bus Fault Status Subregister” (0xE000ED29 - 8 bits), “UFSR: Usage Fault Status Subregister” (0xE000ED2A - 16
bits).
Table 12-32. System Control Block (SCB) Regi ster Mapping
Offset Register Name Access Reset
0xE000E008 Auxiliary Control Register SCB_ACTLR Read/Write 0x00000000
0xE000ED00 CPUID Base Register SCB_CPUID Read-only 0x410FC240
0xE000ED04 I nterrupt Control and State Register SCB_ICSR Read/Write(1) 0x00000000
0xE000ED08 Vector Table Offset Register SCB_VTOR Read/Write 0x00000000
0xE000ED0C Application Interrupt and Reset Control Register SCB_AIRCR Read/Write 0xFA050000
0xE000ED10 System Control Register SCB_SCR Read/Write 0x00000000
0xE000ED14 Configuration and Control Registe r SCB_CCR Read/Write 0x00000200
0xE000ED18 System Handler Priority Register 1 SCB_SHPR1 Read/Write 0x00000000
0xE000ED1C System Handler Priority Register 2 SCB_SHPR2 Read/Write 0x00000000
0xE000ED20 System Handler Priority Register 3 SCB_SHPR3 Read/Write 0x00000000
0xE000ED24 System Handler Control and State Register SCB_SHCSR Read/Write 0x00000000
0xE000ED28 Configurable Fault Status Register SCB_CFSR(2) Read/Write 0x00000000
0xE000ED2C HardFault Status Register SCB_HFSR Read/Write 0x00000000
0xE000ED34 MemManage Fault Address Register SCB_MMFAR Read/Write Unknown
0xE000ED38 BusFault Address Register SCB_BFAR Read/Wr ite Unknown
0xE000ED3C Auxiliary Fault Status Register SCB_AFSR Read/Write 0x00000000
209
SAM4S Series [DATASHEET]
Atmel-11100K-ATARM-SAM4S-Datasheet_09-Jun-15
12.9.1.1 Auxiliary Control Register
Name: SCB_ACTLR
Access: Read/Write
The SCB_ACTLR provides disable bits for the following processor functions:
• IT folding
• Write buffer use for accesses to the default memory map
• Interruption of multi-cycle instructions.
By default, this register is set to provide optimum performance from the Cortex-M4 processor, and does not normally
require modification.
• DISOOFP: Disable Out Of Order Floating Point
Disables floating point instructions that complete out of order with respect to integer instructions.
• DISFPCA: Disable FPCA
Disables an automatic update of CONTROL.FPCA.
• DISFOLD: Disable Folding
When set to 1, disables the IT folding.
Note: In some situations, the processor can start executing the first instruction in an IT block while it is still executing the IT instruction.
This behavior is called IT folding, and it improves the performance. However, IT folding can cause jitter in looping. If a task must
avoid jitter, set the DISFOLD bit to 1 before executing the task, to disable the IT folding.
• DISDEFWBUF: Disable Default Write Buffer
When set to 1, it disables the write buffer use during default memory map accesses. This causes BusFault to be precise
but decreases the performance, as any store to memory must complete before the processor can execute the next
instruction.
This bit only affects write buffers implemented in the Cortex-M4 processor.
• DISMCYCINT: Disable Multiple Cycle Interruption
When set to 1, it disables the interruption of load multiple and store multiple instructions. This increases the in terrupt
latency of the processor, as any LDM or STM must complete before th e processor can stack the curren t state and enter the
interrupt hand le r.
31 30 29 28 27 26 25 24
––––––––
23 22 21 20 19 18 17 16
––––––––
15 14 13 12 11 10 9 8
––––––DISOOFPDISFPCA
76543210
–––––DISFOLDDISDEFWBUFDISMCYCINT
SAM4S Series [DATASHEET]
Atmel-11100K-ATARM-SAM4S-Datasheet_09-Jun-15
210
12.9.1.2 CPUID Base Register
Name: SCB_CPUID
Access: Read/Write
The SCB_CPUID register contains the processor part number, version, and implementation information.
• Implementer: Implementer Code
0x41: ARM.
• Variant: Variant Number
It is the r value in the rnpn pro d uct revis ion iden tif ier :
0x0: Revision 0.
• Constant: Reads as 0xF
Reads as 0xF.
• PartNo: Part Number of the Processor
0xC24 = Cortex-M4.
• Revision: Revision Number
It is the p value in the rnpn product revision identifier:
0x0: Patch 0.
31 30 29 28 27 26 25 24
Implementer
23 22 21 20 19 18 17 16
Variant Constant
15 14 13 12 11 10 9 8
PartNo
76543210
PartNo Revision
211
SAM4S Series [DATASHEET]
Atmel-11100K-ATARM-SAM4S-Datasheet_09-Jun-15
12.9.1.3 Interrupt Control and State Register
Name: SCB_ICSR
Access: Read/Write
The SCB_ICSR provides a set-pending bit for the Non-Maskable Interrupt (NMI) exception, and set-pending and clear-
pending bits for the PendSV and SysTick exceptions.
It indicates:
• The except ion number of the exception being processed, and whether there are preempted active exceptions,
• The exception number of the highest priority pending exception, and whether any interrupts are pending.
• NMIPENDSET: NMI Set-pending
Write:
PendSV set-pending bit.
Write:
0: No effect.
1: Changes NMI exception state to pending.
Read:
0: NMI exception is not pending.
1: NMI exception is pending.
As NMI is the highest-priority exception, the p rocessor nor mally ente rs the NMI except ion handler as soon as it register s a
write of 1 to this bit. Entering the handler clears this bit to 0. A read of this bit by the NMI exception handler returns 1 only if
the NMI signal is reasserted while the processor is executing that handler.
• PENDSVSET: PendSV Set-pending
Write:
0: No effect.
1: Changes PendSV exception state to pending.
Read:
0: PendSV exception is not pending.
1: PendSV exception is pending.
Writing a 1 to this bit is the only way to set the PendSV exception state to pending.
31 30 29 28 27 26 25 24
NMIPENDSET – PENDSVSET PENDSVCLR PENDSTSET PENDSTCLR –
23 22 21 20 19 18 17 16
– ISRPENDING VECTPENDING
15 14 13 12 11 10 9 8
VECTPENDING RETTOBASE – – VECTACTIVE
76543210
VECTACTIVE
SAM4S Series [DATASHEET]
Atmel-11100K-ATARM-SAM4S-Datasheet_09-Jun-15
212
• PENDSVCLR: PendSV Clear-pending
Write:
0: No effect.
1: Removes the pending state from the PendSV exception.
• PENDSTSET: SysTick Exception Set-pending
Write:
0: No effect.
1: Changes SysTick exception state to pending.
Read:
0: SysTick except ion is not pe nd in g.
1: SysTick exception is pending.
• PENDSTCLR: SysTick Exception Clear-pending
Write:
0: No effect.
1: Removes the pending state from the SysTick exception.
This bit is Write-only. On a register read, its value is Unknown.
• ISRPENDING: Interrupt Pending Flag (Excluding NMI and Faults)
0: Interrupt not pending.
1: Interrupt pending.
• VECTPENDING: Exception Number of the Highest Priority Pending Enabled Exception
0: No pending exceptions.
Nonzero: The exception number of the highest priority pending enabled exception.
The value indicated by this field includes the effect of the BASEPRI and FAULTMASK registers, but not any effect of the
PRIMASK register.
• RETTOBASE: Preempted Active Exceptions Present or Not
0: There are preempted active exceptions to execute.
1: There are no active exceptions, or the currently-executing exception is the only active exception.
• VECTACTIVE: Active Exception Number Contained
0: Thread mode.
Nonzero: The exception number of the currently active exception. The value is the same as IPSR bits [8:0]. See “Interrupt
Program Status Register” .
Subtract 16 from this value to obtain the IRQ number required to index into the Interrupt Clear-Enable, Set-Enable, Clear-
Pending, Set-Pending, or Priority Registers, see “Interrupt Program Status Register” .
Note: When the user writes to the SCB_ICSR, the effect is unpredictable if:
- Writing a 1 to the PENDSVSET bit and writing a 1 to the PENDSVCLR bit
- Writing a 1 to the PENDSTSET bit and writing a 1 to the PENDSTCLR bit.
213
SAM4S Series [DATASHEET]
Atmel-11100K-ATARM-SAM4S-Datasheet_09-Jun-15
12.9.1.4 Vector Table Offset Register
Name: SCB_VTOR
Access: Read/Write
The SCB_VTOR indicates the offset of the vector table base address from memory address 0x00000000.
• TBLOFF: Vector Table Base Off se t
It contains bits [29:7] of the offset of the table base from the bottom of the memory map.
Bit [29] determines whether the vector table is in the code or SRAM memory region:
0: Code.
1: SRAM.
It is sometimes called the TBLBASE bit.
Note: When setting TBLOFF, the offset must be aligned to the number of exception entries in the vector table. Configure the next
statement to give the information required for your implementation; the statement reminds the user of how to determi ne the
alignment requirement. The minimum alignment is 32 words, enough fo r up to 16 interrupts. For more interrupts, adjust the
alignment by rounding up to the next power of two. For example, if 21 interrupts are required, the alignment must be on a 64-word
boundary because the required table size is 37 words, and the next power of two is 64.
Table alignment requirements mean that bits[6:0] of the table offset are always zero.
31 30 29 28 27 26 25 24
TBLOFF
23 22 21 20 19 18 17 16
TBLOFF
15 14 13 12 11 10 9 8
TBLOFF
76543210
TBLOFF–––––––
SAM4S Series [DATASHEET]
Atmel-11100K-ATARM-SAM4S-Datasheet_09-Jun-15
214
12.9.1.5 Application Interrupt and Reset Control Register
Name: SCB_AIRCR
Access: Read/Write
The SCB_AIRCR provides priority grouping control for the exception model, endian status for data accesses, and reset
control of the system. To write to this register, write 0x5FA to the VECTKEY field, otherwise the processor ignores the
write.
• VECTKEYSTAT: Register Key (Read)
Reads as 0xFA05.
• VECTKEY: Register Key (Write)
Writes 0x5FA to VECTKEY, otherwise the writ e is ignored.
• ENDIANNESS: Data Endianness
0: Little-endian.
1: Big-endian.
• PRIGROUP: Interrupt Priority Grouping
This field determines the split of group priority from subpriority. It shows the position of the binary point that splits the PRI_n
fields in the Interrupt Priority Registers into separate group priority and subpriority fields. The table below shows how the
PRIGROUP value controls this split.
Note: 1. PRI_ n[7:0] field showing the binary point. x denotes a group priority field bit, and y denotes a subpriority fi eld bit.
Determining preemption of an exception uses only the group priority field.
31 30 29 28 27 26 25 24
VECTKEYSTAT/VECTKEY
23 22 21 20 19 18 17 16
VECTKEYSTAT/VECTKEY
15 14 13 12 11 10 9 8
ENDIANNESS–––– PRIGROUP
76543210
–––––
SYSRESETREQ VECTCLRACTIVE VECTRESET
PRIGROUP
Interrupt Priority Level Value, PRI_N[7:0] Number of
Binary Point(1) Group Priority Bits Subpriority Bits Group Priorities Subpriorities
0b000 bxxxxxxx.y [7:1] None 128 2
0b001 bxxxxxx.yy [7:2] [4:0] 64 4
0b010 bxxxxx.yyy [7:3] [4:0] 32 8
0b011 bxxxx.yyyy [7:4] [4:0] 16 16
0b100 bxxx.yyyyy [7:5] [4:0] 8 32
0b101 bxx.yyyyyy [7:6] [5:0] 4 64
0b110 bx.yyyyyyy [7] [6:0] 2 128
0b111 b.yyyyyyy None [7:0] 1 256
215
SAM4S Series [DATASHEET]
Atmel-11100K-ATARM-SAM4S-Datasheet_09-Jun-15
• SYSRESETREQ: System Reset Request
0: No system reset request.
1: Asserts a signal to the outer system that requests a reset.
This is intended to force a large system reset of all major components except for debug. This bit reads as 0.
• VECTCLRACTIVE: Reserved for Debug use
This bit reads as 0. When writing to the register, write a 0 to this bit, otherwise the behavior is unpredictable.
• VECTRESET: Reserved for Debug use
This bit reads as 0. When writing to the register, write a 0 to this bit, otherwise the behavior is unpredictable.
SAM4S Series [DATASHEET]
Atmel-11100K-ATARM-SAM4S-Datasheet_09-Jun-15
216
12.9.1.6 System Control Register
Name: SCB_SCR
Access: Read/Write
• SEVONPEND: Send Event on Pending Bit
0: Only enabled interrupts or events can wake up the processor ; disabled interrupts are excluded.
1: Enabled events and all interrupts, including disabled interrupts, can wake up the processor.
When an event or an interrupt enters the pending state, the event signal wakes up the processor from WFE. If the proces-
sor is not waiting for an event, the event is registered and affe cts th e ne xt WF E.
The processor also wakes up on execution of an
SEV
instruction or an external event.
• SLEEPDEEP: Sleep or Deep Sleep
Controls whether the processor uses sleep or deep sleep as its low power mode:
0: Sleep.
1: Deep sleep.
• SLEEPONEXIT: Sleep-on-exit
Indicates sleep-on-exit when returning from the Handler mode to the Thread mode:
0: Do not sleep when returning to Thread mode.
1: Enter sleep, or deep sleep, on return from an ISR.
Setting this bit to 1 enables an interrupt-driven application to avoid returning to an empty main application.
31 30 29 28 27 26 25 24
––––––––
23 22 21 20 19 18 17 16
––––––––
15 14 13 12 11 10 9 8
––––––––
76543210
– – – SEVONPEND – SLEEPDEEP SLEEPONEXIT –
217
SAM4S Series [DATASHEET]
Atmel-11100K-ATARM-SAM4S-Datasheet_09-Jun-15
12.9.1.7 Configuration and Control Register
Name: SCB_CCR
Access: Read/Write
The SCB_CCR controls the entry to the Thre ad mode and en ables the ha ndlers for NMI, hard fault and faults escala ted by
FAULTMASK to ignore BusFaults. It also enables the division by zero and unaligned access trapping, and the access to
the NVIC_STIR by unprivileged software (see “Software Trigger Interrup t Register” ).
• STKALIGN: Stack Alignment
Indicates the stack alignment on exception entry:
0: 4-byte aligned.
1: 8-byte aligned.
On exception entry, the processor uses bit [9] of the stacked PSR to indicate the stac k alignment. On return from the
exception, it uses this stacked bit to restore the correct stack alignment.
• BFHFNMIGN: Bus Faults Ignored
Enables handlers with priority -1 or -2 to ignore data bus faults caused by load and store instructions. This applies to the
hard fault and FAULTMASK escalated handlers:
0: Data bus faults caused by load and store instructions cause a lock-up.
1: Handlers running at priority -1 and -2 ignore data bus faults caused by load and store instructions.
Set this bit to 1 only when the handler and its data are in absolutely safe memory. The normal use of this bit is to probe sys-
tem devices and bridges to detect control path problems and fix them.
• DIV_0_TRP: Division by Zero Trap
Enables faulting or halting when the processor executes an SDIV or UDIV instruction with a divisor of 0:
0: Do not trap divide by 0.
1: Trap divide by 0.
When this bit is set to 0, a divide by zero returns a quotient of 0.
• UNALIGN_TRP: Unaligned Access Trap
Enables unaligned access traps:
0: Do not trap unaligned halfword and word accesses.
1: Trap unaligned halfword and word accesses.
If this bit is set to 1, an unaligned access generates a usage fault.
31 30 29 28 27 26 25 24
––––––––
23 22 21 20 19 18 17 16
––––––––
15 14 13 12 11 10 9 8
––––––STKALIGNBFHFNMIGN
76543210
– – – DIV_0_TRP UNALIGN_TRP – USERSETMPENDNONBASETHRDE
NA
SAM4S Series [DATASHEET]
Atmel-11100K-ATARM-SAM4S-Datasheet_09-Jun-15
218
Unaligned LDM, STM, LDRD, and STRD instructions always fault irrespective of whether UNALIGN_TRP is set to 1.
• USERSETMPEND: Unprivileged Software Access
Enables unprivileged software access to the NVIC_STIR, see “Software Trigger Interrupt Register” :
0: Disable.
1: Enable.
• NONBASETHRDENA: Thread Mode Enable
Indicates how the processor enters Thread mode:
0: The processor can enter the Thread mode only whe n no exception is active.
1: The processor can enter the Thread mode from any level under the control of an EXC_RETURN value, see “Exception
Return” .
219
SAM4S Series [DATASHEET]
Atmel-11100K-ATARM-SAM4S-Datasheet_09-Jun-15
12.9.1.8 System Handler Priority Registers
The SCB_SHPR1–SCB_SHPR3 registers set the priority level, 0 to 15 of the exception handlers that have configurable pri-
ority. They are byte-accessible.
The system fault handlers and the priority field and register for each handler are:
Each PRI_N field is 8 bits wide, but the processor implements only bits [7:4] of each field, and bits [3:0] read as zero and
ignore writes.
Table 12-33. System Fault Ha ndler Priority Fi elds
Handler Field Register Description
Memory management fault (MemManage) PRI_4
System Handler Priority Register 1Bus fault (BusFault) PRI_5
Usage fault (Usa geFault) PRI_6
SVCall PRI_11 System Handler Priority Register 2
PendSV PRI_14 System Handler Priority Register 3
SysTick PRI_15
SAM4S Series [DATASHEET]
Atmel-11100K-ATARM-SAM4S-Datasheet_09-Jun-15
220
12.9.1.9 System Handler Priority Register 1
Name: SCB_SHPR1
Access: Read/Write
• PRI_6: Priority
Priority of system handler 6, UsageFault.
• PRI_5: Priority
Priority of system handler 5, BusFault.
• PRI_4: Priority
Priority of system handler 4, MemManage.
31 30 29 28 27 26 25 24
––––––––
23 22 21 20 19 18 17 16
PRI_6
15 14 13 12 11 10 9 8
PRI_5
76543210
PRI_4
221
SAM4S Series [DATASHEET]
Atmel-11100K-ATARM-SAM4S-Datasheet_09-Jun-15
12.9.1.10 System Handler Priority Register 2
Name: SCB_SHPR2
Access: Read/Write
• PRI_11: Priority
Priority of system handler 11, SVCall.
31 30 29 28 27 26 25 24
PRI_11
23 22 21 20 19 18 17 16
––––––––
15 14 13 12 11 10 9 8
––––––––
76543210
––––––––
SAM4S Series [DATASHEET]
Atmel-11100K-ATARM-SAM4S-Datasheet_09-Jun-15
222
12.9.1.11 System Handler Priority Register 3
Name: SCB_SHPR3
Access: Read/Write
• PRI_15: Priority
Priority of system handler 15, SysTick exception.
• PRI_14: Priority
Priority of system handler 14, PendSV.
31 30 29 28 27 26 25 24
PRI_15
23 22 21 20 19 18 17 16
PRI_14
15 14 13 12 11 10 9 8
––––––––
76543210
––––––––
223
SAM4S Series [DATASHEET]
Atmel-11100K-ATARM-SAM4S-Datasheet_09-Jun-15
12.9.1.12 System Handler Control and State Register
Name: SCB_SHCSR
Access: Read/Write
The SHCSR enables the system handlers, and indicates the pending status of the bus fault, memory management fault,
and SVC exceptions; it also indicates the active status of the system handlers.
• USGFAULTENA: Usage Fault Enable
0: Disables the exception.
1: Enables the exception.
• BUSFAULTENA: Bus Fault Enable
0: Disables the exception.
1: Enables the exception.
• MEMFAULTENA: Memory Management Fault Enable
0: Disables the exception.
1: Enables the exception.
• SVCALLPENDED: SVC Call Pending
Read:
0: The exception is not pending.
1: The exception is pending.
Note: The user can write to these bits to change the pending status of the exceptions.
• BUSFAULTPENDED: Bus Fault Exception Pending
Read:
0: The exception is not pending.
1: The exception is pending.
Note: The user can write to these bits to change the pending status of the exceptions.
31 30 29 28 27 26 25 24
––––––––
23 22 21 20 19 18 17 16
–––––USGFAULTENABUSFAULTENAMEMFAULTENA
15 14 13 12 11 10 9 8
SVCALLPENDED BUSFAULTPEND
ED MEMFAULTPEND
ED USGFAULTPEND
ED SYSTICKACT PENDSVACT – MONITORACT
76543210
SVCALLACT – – – USGFAULTACT – BUSFAULTACT MEMFAULTACT
SAM4S Series [DATASHEET]
Atmel-11100K-ATARM-SAM4S-Datasheet_09-Jun-15
224
• MEMFAULTPENDED: Memory Management Fault Exception Pending
Read:
0: The exception is not pending.
1: The exception is pending.
Note: The user can write to these bits to change the pending status of the exceptions.
• USGFAULTPENDED: Usage Fault Exce ption Pending
Read:
0: The exception is not pending.
1: The exception is pending.
Note: The user can write to these bits to change the pending status of the exceptions.
• SYSTICKACT: SysTick Exception Active
Read:
0: The exception is not active.
1: The exception is active.
Note: The user can write to these bits to change the active status of the exceptions.
- Caution: A software that changes the value of an active bit in this register without a correct adjustment to the stacked content
can cause the processor to generate a fault exception. Ensure that the software writing to this register retains and subsequently
restores the current active status.
- Caution: After enabling the system handlers, to change the value of a bit in this register, the user must use a read-modify-write
procedure to ensure that only the required bit is changed.
• PENDSVACT: PendSV Exception Active
0: The exception is not active.
1: The exception is active.
• MONITORACT: Debug Monitor Active
0: Debug monitor is not active.
1: Debug monitor is active.
• SVCALLACT: SVC Call Active
0: SVC call is not active.
1: SVC call is active.
• USGFAULTACT: Usage Fault Exception Active
0: Usage fault exception is not active.
1: Usage fault exception is active.
• BUSFAULTACT: Bus Fault Exception Active
0: Bus fault exception is not active.
1: Bus fault exception is active.
• MEMFAULTACT: Memory Management Fault Exception Active
0: Memory management fault exception is not active.
1: Memory management fault exception is active.
225
SAM4S Series [DATASHEET]
Atmel-11100K-ATARM-SAM4S-Datasheet_09-Jun-15
If the user disables a system handler and the corresponding fault occurs, the processor treats the fault as a hard fault.
The user can write to this register to change the pending or active status of system exceptions. An OS kernel can write to
the active bits to perform a context switch that changes the current exception type.
12.9.1.13 Configurable Fault Status Register
Name: SCB_CFSR
Access: Read/Write
• IACCVIOL: Instruction Access Violation Flag
This is part of “MMFSR: Memory Management Fault Status Subregister” .
0: No instruction access violation fault.
1: The processor attempted an instruction fetch from a location that does not permit execution.
This fault occurs on any access to an XN region, even when the MPU is disabled or not present.
When this bit is 1, the PC value stacked for the exception return points to the faulting instruc tio n. T he pro ce sso r ha s not
written a fault address to the SCB_MMFAR.
• DACCVIOL: Data Access Violation Flag
This is part of “MMFSR: Memory Management Fault Status Subregister” .
0: No data access violation fault.
1: The processor attempted a load or store at a location that does not permit the operation.
When this bit is 1, the PC value stacked fo r the exception retu rn points to the faul ting instruction. The processor has loaded
the SCB_MMFAR with the address of the attempted access.
• MUNSTKERR: Memory Manager Fault on Unstacking for a Return From Exception
This is part of “MMFSR: Memory Management Fault Status Subregister” .
0: No unstacking fault.
1: Unstack for an exception return has caused one or more access violations.
This fault is chained to the handler. This means that when this bit is 1, the original return stack is still present. The proces-
sor has not adjusted the SP from the failing return, and has not performed a new save. The processor has not written a
fault address to the SCB_MMFAR.
31 30 29 28 27 26 25 24
––––––DIVBYZERO UNALIGNED
23 22 21 20 19 18 17 16
––––NOCPINVPCINVSTATEUNDEFINSTR
15 14 13 12 11 10 9 8
BFARVALID – –STKERR UNSTKERR IMPRECISERR PRECISERR IBUSERR
76543210
MMARVALID – –MSTKERR MUNSTKERR – DACCVIOL IACCVIOL
SAM4S Series [DATASHEET]
Atmel-11100K-ATARM-SAM4S-Datasheet_09-Jun-15
226
• MSTKERR: Memory Manager Fault on Stacking for Exception Entry
This is part of “MMFSR: Memory Management Fault Status Subregister” .
0: No stacking fault.
1: Stacking for an exception entry has caused one or more access violations.
When this bit is 1, the SP is still adjusted but the values in the context area on the stack might be incorrect. The processor
has not written a fault address to SCB_MMFAR.
• MMARVALID: Memory Management Fault Address Register (SCB_MMFAR) Valid Flag
This is part of “MMFSR: Memory Management Fault Status Subregister” .
0: The value in SCB_MMFAR is not a valid fault address.
1: SCB_MMFAR holds a valid fault address.
If a memory management fault occurs and is escalated to a hard fault because of priority, the hard fault handler must set
this bit to 0. This prevents prob lems on return to a stacked active memory man agement fault handler whose SCB_MMFAR
value has been overwritten.
• IBUSERR: Instruction Bus Error
This is part of “BFSR: Bus Fault Status Subregister” .
0: No instruction bus error.
1: Instruction bus error.
The process or det ec ts the inst ru ction bu s er ro r on pre fe tch in g an instruc tio n, but it sets the IBUSERR flag to 1 on ly if it
attempts to issue the faulting instruction.
When the processor sets this bit to 1, it does not write a fault address to the BFAR.
• PRECISERR: Precise Data Bus Error
This is part of “BFSR: Bus Fault Status Subregister” .
0: No precise data bus error.
1: A data bus error has occurred, and the PC value stacked for the exception return points to the instruction that caused
the fault.
When the processor sets this bit to 1, it writes the faulting address to the SCB_BFAR.
• IMPRECISERR: Imprecise Data Bus Error
This is part of “BFSR: Bus Fault Status Subregister” .
0: No imprecise data bus error.
1: A data bus error has occurred, but the return address in the stack frame is not related to the instruction that caused the
error.
When the processor sets this bit to 1, it does not write a fault address to the SCB_BFAR.
This is an asynchronous fault. Therefor e, if it is detected when the pr iority of the current process is higher than the b us fault
priority, the bus fault becomes pending and becomes active only when the processor returns from all higher priority pro-
cesses. If a precise fault occurs before the processor enters the handler for the imprecise bus fault, the handler detects
that both this bit and one of the precise fault status bits are set to 1.
227
SAM4S Series [DATASHEET]
Atmel-11100K-ATARM-SAM4S-Datasheet_09-Jun-15
• UNSTKERR: Bus Fault on Unstacking for a Return From Exc eption
This is part of “BFSR: Bus Fault Status Subregister” .
0: No unstacking fault.
1: Unstack for an exception return has caused one or more bus faults.
This fault is chained to the handler. This means that when the processor sets this bit to 1, the original return stack is still
present. The processor does not adjust the SP from the failing return, does not performed a new save, and does not write
a fault address to the BFAR.
• STKERR: Bus Fault on Stacking for Exception Entry
This is part of “BFSR: Bus Fault Status Subregister” .
0: No stacking fault.
1: Stacking for an exception entry has caused one or more bus faults.
When the processor sets this bit to 1, the SP is still adjusted but the values in the context area on the stack might be incor-
rect. The processor does not write a fault address to the SCB_BFAR.
• BFARVALID: Bus Fault Address Register (BFAR) Valid flag
This is part of “BFSR: Bus Fault Status Subregister” .
0: The value in SCB_BFAR is not a valid fault address.
1: SCB_BFAR holds a valid fault address.
The processor sets this bit to 1 after a bus fault where the address is known . Ot he r fa ults can set this bit to 0, such as a
memory management fault occurring later.
If a bus fault occurs and is escalated to a hard fault because of priority, the hard fault handler must set this bit to 0. This
prevents problems if returning to a stacked active bus fault handler whose SCB_BFAR value has been overwritten.
• UNDEFINSTR: Undefined Instruction Usage Fault
This is part of “U FSR: Usage Fault Status Subregister” .
0: No undefined instruction usage fault.
1: The processor has attempted to execute an undefined instr uction.
When this bit is set to 1, the PC value stacked for the e xception return points to the undefined instruction.
An undefined instruction is an instruction that the processor cannot decode.
• INVSTATE: Invalid State Usage Fault
This is part of “U FSR: Usage Fault Status Subregister” .
0: No invalid state usa g e fa ult.
1: The processor has attempted to execute an instruction that makes illegal use of the EPSR.
When this bit is set to 1, the PC value stacked for the exception return points to the instruction that attempted the illegal
use of the EPSR.
This bit is not set to 1 if an undefined instruction uses the EPSR.
• INVPC: Invalid PC Load Usage Fault
This is part of “U FSR: Usage Fault Status Subregister” . It is caused by an invalid PC load by EXC_RETURN:
0: No invalid PC load usage fault.
1: The processor has attempted an illegal load of EXC_RETURN to the PC, as a result of an invalid context, or an invalid
EXC_RETURN value.
SAM4S Series [DATASHEET]
Atmel-11100K-ATARM-SAM4S-Datasheet_09-Jun-15
228
When this bit is set to 1, the PC value stacked for the exception return points to the instruction that tried to perform the ille-
gal load of the PC.
• NOCP: No Coprocessor Usage Fault
This is part of “U FSR: Usage Fault Status Subregister” . The processor does not support coprocessor instructions:
0: No usage fault caus ed by att em p tin g to ac ce ss a cop ro ce ss or .
1: The processor has attempted to access a coprocessor.
• UNALIGNED: Unaligned Access Usage Fault
This is part of “U FSR: Usage Fault Status Subregister” .
0: No unaligned access fault, or unaligned access trapping not enabled.
1: The processor has made an unaligned memory access.
Enable trapping of unaligned accesses by setting the UNALIGN_TRP bit in the SCB_CCR to 1. See “Configuration and
Control Register” . Unaligned LDM, STM, LDRD, and STRD instructions always fault irrespective of the setting of
UNALIGN_TRP.
• DIVBYZERO: Divide by Zero Usage Fault
This is part of “U FSR: Usage Fault Status Subregister” .
0: No divide by zero fault, or divide by zero trapping not enabled.
1: The processor has executed an SDIV or UDIV instruction with a divisor of 0.
When the processor sets this bit to 1, th e PC value stacked for the exception return points to th e instruction that performed
the divide by zero. Enable trapping of divide by zero by setting the DIV_0_TRP bit in the SCB_CCR to 1. See “Configura-
tion and Control Register” .
229
SAM4S Series [DATASHEET]
Atmel-11100K-ATARM-SAM4S-Datasheet_09-Jun-15
12.9.1.14 Configurable Fault Status Register (Byte Access)
Name: SCB_CFSR (BYTE)
Access: Read/Write
• MMFSR: Memory Management Fault Status Subregister
The flags in the MMFSR subregister indicate the cause of memory access faults. See bitfield [7..0] description in Section
12.9.1.13.
• BFSR: Bus Fault Status Subregister
The flags in the BFSR subregister indicate the cause of a bus access faul t. See bitfield [14..8] description in Section
12.9.1.13.
• UFSR: Usage Fault Status Subregister
The flags in the UFSR subregister indicate the cause of a usage fault. See bitfield [31..15] descri ption in Section 12 .9.1.13.
Note: The UFSR bits are sticky. This means that as one or more fault occurs, the associated bits are set to 1. A bit that is set to 1 is
cleared to 0 only by wrting a 1 to that bit, or by a reset.
The SCB_CFSR indicates the cause of a memory management fault, bus fault, or usage fault. It is byte accessible. The
user can access the SCB_CFSR or its subregisters as follows:
• Access complete SCB_CFSR with a word access to 0xE000ED28
• Access MMFSR with a byte access to 0xE000ED28
• Access MMF SR an d BFS R with a ha lfwor d access to 0xE000 ED2 8
• Access BFSR with a byte access to 0xE000ED29
• Access UFSR with a ha lfwor d ac ce ss to 0x E00 0 ED2 A.
31 30 29 28 27 26 25 24
UFSR
23 22 21 20 19 18 17 16
UFSR
15 14 13 12 11 10 9 8
BFSR
76543210
MMFSR
SAM4S Series [DATASHEET]
Atmel-11100K-ATARM-SAM4S-Datasheet_09-Jun-15
230
12.9.1.15 Hard Fault Status Register
Name: SCB_HFSR
Access: Read/Write
The SCB_HFSR gives information about events that activate the hard fault handler. This register is read, write to clear.
This means that bits in the register read normally, but wrting a 1 to any bit clears that bit to 0.
• DEBUGEVT: Reserved for Debug Use
When writing to the register, write a 0 to this bit, otherwise the behavior is unpredictable.
• FORCED: Forced Hard Fault
It indicates a forced hard fault, generated by escalation of a fault with configurable priority that cannot be handles, either
because of priority or because it is disabled:
0: No forced hard fault.
1: Forced hard fault.
When this bit is set to 1, the hard fault handler must read the other fault status registers to find the cause of the fau lt.
• VECTTBL: Bus Fault on a Vector Table
It indicates a bus fault on a vector table read during an exception processing:
0: No bus fault on vector table read.
1: Bus fault on vector table read.
This error is always handled by the hard fault handler.
When this bit is set to 1, the PC value stacked for the exception return points to the instruction that was preempted by the
exception.
Note: The HFSR bits are sticky. Th is means th at, as one or more fault occurs, the associated bits are set to 1. A bit that is set to 1 is
cleared to 0 only by wrting a 1 to that bit, or by a reset.
31 30 29 28 27 26 25 24
DEBUGEVTFORCED––––––
23 22 21 20 19 18 17 16
––––––––
15 14 13 12 11 10 9 8
––––––––
76543210
––––––VECTTBL–
231
SAM4S Series [DATASHEET]
Atmel-11100K-ATARM-SAM4S-Datasheet_09-Jun-15
12.9.1.16 MemManage Fault Address Register
Name: SCB_MMFAR
Access: Read/Write
The SCB_MMFAR contains the address of the location that generated a memory management fault.
• ADDRESS: Memory Management Fault Generation Location Address
When the MMARVALID bit of the MMF SR su bregister is set to 1, this field hold s the add ress of the location that generated
the memory management fault.
Notes: 1. When an unaligned access faults, the address is the actual address that faulted. Because a single read or write instruction
can be split into multiple aligned accesses, the fault address can be any address in the range of the requested access size.
2. Flags in the MMFSR subregister indicate the cause of the fault, and whether the value in the SCB_MMFAR is valid. See
“MMFSR: Memory Management Fault Status Subregister” .
31 30 29 28 27 26 25 24
ADDRESS
23 22 21 20 19 18 17 16
ADDRESS
15 14 13 12 11 10 9 8
ADDRESS
76543210
ADDRESS
SAM4S Series [DATASHEET]
Atmel-11100K-ATARM-SAM4S-Datasheet_09-Jun-15
232
12.9.1.17 Bus Fault Address Register
Name: SCB_BFAR
Access: Read/Write
The SCB_BFAR contains the address of the location that generated a bus fault.
• ADDRESS: Bus Fault Generation Location Address
When the BFARVALID bit of the BFSR subreg ister is se t to 1, this fie ld holds th e address of the lo cation that ge nerated the
bus fault.
Notes: 1. When an unaligned access faults, the address in the SCB_BFAR is the one requested by the instruction, even if it is not the
address of the fault.
2. Flags in the BFSR indicate the cause of the fault, and whether the value in the SCB_BFAR is valid. See “BFSR: Bus Fault
Status Subregister” .
31 30 29 28 27 26 25 24
ADDRESS
23 22 21 20 19 18 17 16
ADDRESS
15 14 13 12 11 10 9 8
ADDRESS
76543210
ADDRESS
233
SAM4S Series [DATASHEET]
Atmel-11100K-ATARM-SAM4S-Datasheet_09-Jun-15
12.10 System Timer (SysTick)
The processor has a 24-bit system timer, SysTick, that counts down from the reload value to zero, reloads (wraps
to) the value in the SYST_RVR on the next clock edge, then counts down on subsequent clocks.
When the processor is halted for debugging, the counter does not decrement.
The SysTick counter runs on the processor clock. If this clock signal is stopped for low power mode, the SysTick
counter stops.
Ensure that the software uses aligned word accesses to access the SysTick registers.
The SysTick counter relo ad and current value are undefined at re set; the correct initialization sequence fo r the
SysTick counter is:
1. Program the reload v alue.
2. Clear the current value.
3. Program the Control and Status register.
SAM4S Series [DATASHEET]
Atmel-11100K-ATARM-SAM4S-Datasheet_09-Jun-15
234
12.10.1 System Timer (SysTick) User Interface
Table 12-34. System Timer (SYST) Register Mapping
Offset Register Name Access Reset
0xE000E010 SysTick Control and Status Register SYST_CSR Read/Write 0x00000000
0xE000E014 SysTick Reload Value Register SYST_RVR Read/Write Unknown
0xE000E018 SysTick Current Value Register SYST_CVR Read/Write Unknown
0xE000E01C SysTick Calibration Value Register SYST_CALIB Read-only 0x000030D4
235
SAM4S Series [DATASHEET]
Atmel-11100K-ATARM-SAM4S-Datasheet_09-Jun-15
12.10.1.1 SysTick Control and Status Register
Name: SYST_CSR
Access: Read/Write
The SysTick SYST_CSR enables the SysTick features.
• COUNTFLAG: Count Flag
Returns 1 if the timer counted to 0 since the last time this was read.
• CLKSOURCE: Clock Source
Indicates the clock source:
0: External Clock.
1: Processor Clock.
• TICKINT: SysTick Exception Request Enable
Enables a SysTick exception request:
0: Counting down to zero does not assert the SysTick exception request.
1: Counting down to zero asserts the SysTick exception request.
The software can use COUNTFLAG to determine if SysTick has ever counted to zero.
• ENABLE: Counter Enable
Enables the counter:
0: Counter disabled.
1: Counter enabled.
When ENABLE is set to 1, the counter loads the RELOAD value from the SYST_RVR and then counts down. On reaching
0, it sets the COUNTFLAG to 1 an d op tio na lly as ser ts the SysTick depending on the value of TICKINT. It then loads the
RELOAD value again, and begins counting.
31 30 29 28 27 26 25 24
––––––––
23 22 21 20 19 18 17 16
–––––––COUNTFLAG
15 14 13 12 11 10 9 8
––––––––
76543210
–––––CLKSOURCE TICKINT ENABLE
SAM4S Series [DATASHEET]
Atmel-11100K-ATARM-SAM4S-Datasheet_09-Jun-15
236
12.10.1.2 SysTick Reload Value Registers
Name: SYST_RVR
Access: Read/Write
The SYST_RVR specifies the start value to load into the SYST_CVR.
• RELOAD: SYST_CVR Load Value
Value to load into the SYST_CVR when the counter is enabled and when it reaches 0.
The RELOAD value can be any value in the range 0x00000001–0x00FFFFFF. A start value of 0 is possible, but has no
effect because the SysTick exception request and COUNTFLAG are activated when counting from 1 to 0.
The RELOAD value is calculated according to its use: For example, to generate a multi-shot timer with a period of N pro-
cessor clock cycles, use a RELOAD value of N-1. If the SysTick interrupt is required every 100 clo ck pulse s, set RELOAD
to 99.
31 30 29 28 27 26 25 24
––––––––
23 22 21 20 19 18 17 16
RELOAD
15 14 13 12 11 10 9 8
RELOAD
76543210
RELOAD
237
SAM4S Series [DATASHEET]
Atmel-11100K-ATARM-SAM4S-Datasheet_09-Jun-15
12.10.1.3 SysTick Current Value Register
Name: SYST_CVR
Access: Read/Write
The SysTick SYST_CVR contains the current value of the SysTick counter.
• CURRENT: SysTick Counter Current Value
Reads return the current value of the SysTick counter.
A write of any value clears th e field to 0, and also clears the SYST_CSR.COUNTFLAG bit to 0.
31 30 29 28 27 26 25 24
––––––––
23 22 21 20 19 18 17 16
CURRENT
15 14 13 12 11 10 9 8
CURRENT
76543210
CURRENT
SAM4S Series [DATASHEET]
Atmel-11100K-ATARM-SAM4S-Datasheet_09-Jun-15
238
12.10.1.4 SysTick Calibration Value Register
Name: SYST_CALIB
Access: Read/Write
The SysTick SYST_CSR indicates the SysTick calibration properties.
• NOREF: No Reference Clock
It indicates whether the device provides a reference clock to the processor:
0: Reference clock provided.
1: No reference clock provided.
If your device does not provide a reference clock, the SYST_CSR.CLKSOURCE bit reads-as-one and ignores writes.
• SKEW: TENMS Value Verification
It indicates whether the TENMS value is exact:
0: TENMS value is exact.
1: TENMS value is inexact, or not given.
An inexact TENMS value can affect the suitability of SysTick as a software real time clock.
• TENMS: Ten Milliseconds
The reload value for 10 ms (100 Hz) timing is subject to system clock skew errors. If the value re ad s as ze ro, the calibra-
tion value is not known.
The TENMS field default value is 0x000030D4 (12500 decimal).
In order to achieve a 1 ms timebase on SystTick, the TENMS field must be programmed to a value corresponding to the
processor clock frequency (in kHz) divided by 8.
For example, for devices running the processor clock at 48 MHz, the TENMS field value must be 0x0001770
(48000 kHz/8).
31 30 29 28 27 26 25 24
NOREF SKEW ––––––
23 22 21 20 19 18 17 16
TENMS
15 14 13 12 11 10 9 8
TENMS
76543210
TENMS
239
SAM4S Series [DATASHEET]
Atmel-11100K-ATARM-SAM4S-Datasheet_09-Jun-15
12.11 Memory Protection Unit (MPU)
The MPU divides the mem ory map into a number of reg ions, and defines the location, size , access permissions,
and memory attributes of each region. It supports:
Independent attribute settings for each region
Overlappin g re gio ns
Export of memory attributes to the system.
The memory attributes affect the behavior of memory accesses to the region. The Cortex-M4 MPU defines:
Eight separate memory regions, 0–7
A background region.
When memory regions overlap, a memory access is affected by the attributes of the region with the highest
number. For example, the attributes for region 7 take precedence over the attributes of any region that overlaps
region 7.
The background region has the same memory access attributes as the default memory map, but is accessible
from privileged softw ar e on ly.
The Cortex-M4 MPU memory map is unified. This means that instruction accesses and data accesses have the
same region settings.
If a program accesses a memory location that is proh ibited by the MPU, the processor generat es a memory
management fault. This causes a fault exception, and might cause the termination of the process in an OS
environment.
In an OS environment, the kernel can update the MPU region setting dynamically based on the process to be
executed. Typically, an embedded OS uses the MPU for memory protection.
The configuration of MPU regions is based on memory types (see “Memory Regions, Types and Attributes” ).
Table 12-35 shows the possible MPU region attributes. These in clude Share ability and cache beh avior attributes
that are not relevant to most microcontroller implementations. See “MPU Configuration for a Microcontroller” for
guidelines for programming such an implementation.
12.11.1 MPU Access Permission Attributes
This section describes the MPU access permission attributes. The access permiss ion bits (TEX, C, B, S, AP, and
XN) of the MPU_RASR control the access to the corresponding memory region. If an access is made to an area of
memory without the required permissions, then the MPU generates a permission fault.
Table 12-3 5. Memory Attributes Summary
Memory Type Shareability Other Attributes Description
Strongly-ordered – – All accesses to Strongly-ordered memory occur in program order. All
Strongly-ordered regions are assumed to be shared.
Device Shared – Memory-mapped peripherals that several processors share .
Non-shared – Memory-mapped peripherals that only a single processor uses.
Normal
Shared Non-cacheable Write-
through Cacheable
Write-back Cacheable Normal memory that is shared between several processors.
Non-shared Non-cacheable Write-
through Cacheable
Write-back Cacheable Normal memory that only a single processo r use s .
SAM4S Series [DATASHEET]
Atmel-11100K-ATARM-SAM4S-Datasheet_09-Jun-15
240
The table below shows the encodings for the TEX, C, B, and S access permission bits.
Note: 1. The MPU ignores the value of this bit.
Table 12-37 shows the cache policy for memory attribute encodings with a TEX value is in the range 4–7.
Table 12-36. TEX, C, B, and S Encoding
TEX C B S Memory Type Shareability O ther Attributes
b000
0
0 x(1) Strongly-ordered Shareable –
1 x(1) Device Shareable –
1
0 0Normal Not
shareable Outer and inner write-through. No
write allocate.
1 Shareable
1 0Normal Not
shareable Outer and inner write-back. No write
allocate.
1 Shareable
b001
0
0 0Normal Not
shareable Outer and inner noncacheable.
1 Shareable
1 x(1) Reserved encod ing –
1
0 x(1) Implementation defined
attributes. –
1 0Normal Not
shareable Outer and inner write-back. Write and
read allocate .
1 Shareable
b010 00 x(1) Device Not
shareable Nonshared Device.
1 x(1) Reserved encoding –
1x
(1) x(1) Reserved encoding –
b1BB A A 0Normal Not
shareable Cached memory BB = outer policy,
AA = inner policy.
1Shareable
Table 12-37. Cache Policy for Memory Attribute Encoding
Encoding, AA or B B Corresponding Cac he Policy
00 Non-cacheable
01 Write back, write and read allocate
10 Write through, no write al l oca t e
11 Write back, no write allocate
241
SAM4S Series [DATASHEET]
Atmel-11100K-ATARM-SAM4S-Datasheet_09-Jun-15
Table 12-38 shows the AP encodings that define the access permissions for privileged and unprivileged software.
12.11.1.1 MPU Mismatch
When an access violates the MPU permissions, the processor generates a memory management fault, see
“Exceptions and Interrupts” . The MMFSR indicate s the caus e of the fault. Se e “MMFSR: Memory Management
Fault Status Subregister” for more information.
12.11.1.2 Updating an MPU Region
To update the attributes for an MPU region, update the MPU_RNR, MPU_RBAR and MPU_RASRs. Each register
can be programed separately, or a multiple-word write can be used to program all of these registers. MPU_RBAR
and MPU_RASR aliases can be used to program up to four regions simultaneously using an STM instruction.
12.11.1.3 Updating an MPU Region Using Separate Words
Simple code to configure one region:
; R1 = region number
; R2 = size/enable
; R3 = attributes
; R4 = address
LDR R0,=MPU_RNR ; 0xE000ED98, MPU region number register
STR R1, [R0, #0x0] ; Region Number
STR R4, [R0, #0x4] ; Region Base Address
STRH R2, [R0, #0x8] ; Region Size and Enable
STRH R3, [R0, #0xA] ; Region Attribute
Disable a region before writing new region settings to the MPU, if the region being changed was previously
enabled . Fo r ex am ple:
; R1 = region number
; R2 = size/enable
; R3 = attributes
; R4 = address
LDR R0,=MPU_RNR ; 0xE000ED98, MPU region number register
STR R1, [R0, #0x0] ; Region Number
BIC R2, R2, #1 ; Disable
STRH R2, [R0, #0x8] ; Region Size and Enable
STR R4, [R0, #0x4] ; Region Base Address
STRH R3, [R0, #0xA] ; Region Attribute
ORR R2, #1 ; Enable
Table 12-38. AP Encoding
AP[2:0] Privileged
Permissions Unprivileged
Permissions Description
000 No access No access All accesses generate a permission fault
001 RW No access Access from privileged software only
010 RW RO Writes by unprivileged software generate a permission
fault
011 RW RW Full access
100 Unpredictable Unpredictable Reserved
101 RO No access Reads by privileged software only
110 RO RO Read only, by privileged or unprivileged software
111 RO RO Read only, by privileged or unprivileged software
SAM4S Series [DATASHEET]
Atmel-11100K-ATARM-SAM4S-Datasheet_09-Jun-15
242
STRH R2, [R0, #0x8] ; Region Size and Enable
The software must use memory barrier instructions:
Before the MPU setup, if there might be outstanding memory transfers, such as buffered writes, that might
be affected by the change in MPU settings
After the MPU setup, if it includes memory transfers that must use the new MPU settings.
However, memory barrier instructions are not required if the MPU setup process starts by entering an exception
handler, or is fo llowed by an exception return, because the exception entry and exception return mechanisms
cause memory barrier behavior.
The software does not need an y memory barrier instructions during an MPU setup, because it accesses the MPU
through the PPB, which is a Strongly-Ordered memory region.
For example, if the user wants all of the memory access behavior to take effect immediately after the programming
sequence, a DSB instructio n and an ISB instru ction m ust be used . A DSB is requir ed after chan ging MPU setting s,
such as at the end of a context switch. An ISB is required if the code that programs the MPU region or regions is
entered using a branch or call. If the programming sequence is entered using a return from exception, or by taking
an exception, then an ISB is not required.
12.11.1.4 Updating an MPU Region Using Multi-word Writes
The user can program directly using multi-word writes, depending on how the information is divided. Cons ider the
following reprog ra m m i ng :
; R1 = region number
; R2 = address
; R3 = size, attributes in one
LDR R0, =MPU_RNR ; 0xE000ED98, MPU region number register
STR R1, [R0, #0x0] ; Region Number
STR R2, [R0, #0x4] ; Region Base Address
STR R3, [R0, #0x8] ; Region Attribute, Size and Enable
Use an STM instruction to optimize this:
; R1 = region number
; R2 = address
; R3 = size, attributes in one
LDR R0, =MPU_RNR ; 0xE000ED98, MPU region number register
STM R0, {R1-R3} ; Region Number, address, attribute, size and enable
This can be done in two words for pre-packed information. This means that the MPU_RBAR contains the required
region number and had th e VALID bit set to 1. See “MPU Region Ba se Ad dres s Register” . Use this when the data
is statically packed, for example in a boot loader:
; R1 = address and region number in one
; R2 = size and attributes in one
LDR R0, =MPU_RBAR ; 0xE000ED9C, MPU Region Base register
STR R1, [R0, #0x0] ; Region base address and
; region number combined with VALID (bit 4) set to 1
STR R2, [R0, #0x4] ; Region Attribute, Size and Enable
Use an STM instruction to optimize this:
; R1 = address and region number in one
; R2 = size and attributes in one
LDR R0,=MPU_RBAR ; 0xE000ED9C, MPU Region Base register
243
SAM4S Series [DATASHEET]
Atmel-11100K-ATARM-SAM4S-Datasheet_09-Jun-15
STM R0, {R1-R2} ; Region base address, region number and VALID bit,
; and Region Attribute, Size and Enable
12.11.1.5 Subregions
Regions of 256 bytes or more are divided into eight equal-sized subre gions. Set the co rrespo nding b it in the SRD
field of the MPU_RASR field to disable a subregion. See “MPU Region Attribute and Size Register” . The least
significant bit of SRD controls the first subregion, and the most significant bit controls the last subregion. Disabling
a subregion means another region overlapping the disabled range matches instead. If no other enabled region
overlaps the disabled subregion, the MPU issues a fault.
Regions of 32, 64, and 128 bytes do not suppor t subregions. With regions of these sizes, the SRD field must be
set to 0x00, otherwise the MPU behavior is unpredictable.
12.11.1.6 Example of SRD Use
Two regions with the same base address overlap. Region 1 is 128 KB, and region 2 is 512 KB. To ensure the
attributes from region 1 apply to the first 128 KB region, set the SRD field for region 2 to b00000011 to disable the
first two subregions, as in Figure 12-13 below :
Figure 12-13. SRD Use
12.11.1.7 MPU Design Hints And Tips
To avoid unexpected behavior, disable the interrupts before updating the attributes of a region that the interrupt
handlers might access.
Ensure the software uses aligned accesses of the correct size to access MPU registers:
Except for the MPU_RASR, it must use aligned word accesses
For the MPU_RASR, it can use byte or aligned halfword or word accesses.
The processor does not support unaligned accesses to MPU registers.
When setting up the MPU, and if the MPU h as previously been prog rammed, disable unu sed regions to preven t
any previous region settings from affecting the new MPU setup.
MPU Configuration for a Microcontroller
Usually, a microcontroller system has only a single processor and no caches. In such a system, program the MPU
as follows:
Region 1
Disabled subregion
Disabled subregion
Region 2, with
subregions
Base address of both regions
Offset from
base address
0
64KB
128KB
192KB
256KB
320KB
384KB
448KB
512KB
Table 12-39. Memory Region Attr ibutes for a Microcontroller
Memory Region TEX C B S Memory Type and Attributes
Flash memory b000 1 0 0 Normal memory, non-shareable, write-through
Internal SRAM b000 1 0 1 Normal memory, shareable, write-through
External SRAM b000 1 1 1 Normal memory, sharea ble, write-back, wr ite-allocate
Peripherals b000 0 1 1 Device me mory, shareable
SAM4S Series [DATASHEET]
Atmel-11100K-ATARM-SAM4S-Datasheet_09-Jun-15
244
In most microcontroller implementations, the shareability and cache policy attributes do not affect the system
behavior. However, using these settings for the MPU regions can make the application code more portable. The
values given are for typical situations. In special systems, such as multiprocessor designs or designs with a
separate DMA engine, the shareability attribute might be important. In these cases, refer to the recommendations
of the memory device manufacturer.
245
SAM4S Series [DATASHEET]
Atmel-11100K-ATARM-SAM4S-Datasheet_09-Jun-15
12.11.2 Memory Protection Unit (MPU) User Interface
Table 12-4 0. Memory Protection Unit (MPU) Register Ma pp ing
Offset Register Name Access Reset
0xE000ED90 MPU Type Register MPU_TYPE Re ad-only 0x00000800
0xE000ED94 MPU Control Register MPU_CTRL Re ad/Write 0x00000000
0xE000ED98 MPU Region Number Register MPU_RNR Read/Write 0x00000000
0xE000ED9C MPU Region Base Address Register MPU_RBAR Read/Write 0x00000000
0xE000EDA0 MPU Region Attribute and Size Register MPU_RASR Read/Write 0x00000000
0xE000EDA4 MPU Region Base Address Register Alias 1 MPU_RBAR_A1 Read/Write 0x00000000
0xE000EDA8 MPU Region Attribute and Size Register Alias 1 MPU_RASR_ A1 Read/Write 0x00000000
0xE000EDAC MPU Region Base Address Register Alias 2 MPU_RBAR_A2 Read/Write 0x00000000
0xE000EDB0 MPU Region Attribute and Size Register Alias 2 MPU_RASR_ A2 Read/Write 0x00000000
0xE000EDB4 MPU Region Base Address Register Alias 3 MPU_RBAR_A3 Read/Write 0x00000000
0xE000EDB8 MPU Region Attribute and Size Register Alias 3 MPU_RASR_ A3 Read/Write 0x00000000
SAM4S Series [DATASHEET]
Atmel-11100K-ATARM-SAM4S-Datasheet_09-Jun-15
246
12.11.2.1 MPU Type Register
Name: MPU_TYPE
Access: Read/Write
The MPU_TYPE register indicates whether the MPU is present, and if so, how many regions it supports.
• IREGION: Instruction Region
Indicates the number of supported MPU instruction regions.
Always contains 0x00. The MPU memory map is unified and is described by the DREGION field.
• DREGION: Data Region
Indicates the number of supported MPU data regions:
0x08 = Eight MPU regions.
• SEPARATE: Separate Instruction
Indicates support for unified or separate instruction and date memory maps:
0: Unified.
31 30 29 28 27 26 25 24
––––––––
23 22 21 20 19 18 17 16
IREGION
15 14 13 12 11 10 9 8
DREGION
76543210
–––––––SEPARATE
247
SAM4S Series [DATASHEET]
Atmel-11100K-ATARM-SAM4S-Datasheet_09-Jun-15
12.11.2.2 MPU Control Register
Name: MPU_CTRL
Access: Read/Write
The MPU CTRL register enables the MPU, enables the default memory map background region, and enables the use of
the MPU when in the hard fault, Non-maskable Interrupt (NMI), and FAULTMASK escalated handlers.
• PRIVDEFENA: Privileged Default Memory Map Enable
Enables privileged software access to the default memory map:
0: If the MPU is enabled, disables the use of the default memory map. Any memory access to a location not covered by
any enabled region causes a fault.
1: If the MPU is enabled, enables the use of the default memory map as a background region for privileged software
accesses.
When enabled, the backgrou nd region acts as a regio n number -1. Any region that is defined and enabled has priority over
this default map.
If the MPU is disabled, the processor ignores this bit.
• HFNMIENA: Hard Fault and NMI Enable
Enables the operation of MPU during hard fault, NMI, and FAULTMASK handlers.
When the MPU is enabled:
0: MPU is disabled during hard fault, NMI, and FAULTMASK handlers, regardless of the value of the ENABLE bit.
1: The MPU is enabled during hard fault, NMI, and FAULTMASK handlers.
When the MPU is disabled, if this bit is set to 1, the behavior is unpredictable.
• ENABLE: MPU Enable
Enables the MPU:
0: MPU disabled.
1: MPU enabled.
When ENABLE and PRIVDEFENA are both set to 1:
• For privileged accesses, the d e fault memory map is as described in “Memory Model” . Any access by privileged
software that does not address an enabled memory region behaves as defined by the def ault memory map.
• Any access b y unprivileged so ftw are th at does n ot address an enab le d memory region causes a m emory management
fault.
31 30 29 28 27 26 25 24
––––––––
23 22 21 20 19 18 17 16
––––––––
15 14 13 12 11 10 9 8
––––––––
76543210
–––––PRIVDEFENAHFNMIENAENABLE
SAM4S Series [DATASHEET]
Atmel-11100K-ATARM-SAM4S-Datasheet_09-Jun-15
248
XN and Strongly-ordered rules always apply to the System Control Space rega rd le ss of th e va lu e of the ENABLE bit.
When the ENABLE bit is set to 1, at least one region of the memor y map must be enabled for the syste m to function unless
the PRIVDEFENA bit is set to 1. If the PRIVDEFENA bit is set to 1 and no regions are enabled, then only privileged soft-
ware can operate.
When the ENABLE bit is set to 0 , the system uses th e defa ult memory map. This has the same memory attributes as if the
MPU is not implemented. The default memory map applies to accesses from both privileged and unprivileged software.
When the MPU is enabled, accesses to the System Con trol Space and vector table ar e always per mitted. Other areas are
accessible based on regions and whether PRIVDEFENA is set to 1.
Unless HFNMIENA is set to 1, the MPU is not enabled when the processor is executing the handler for an exception with
priority –1 or –2. These priorities are only possible when handling a hard fault or NMI exception, or when FAULTMASK is
enabled. Setting the HFNMIENA bit to 1 enables the MPU when operating with these two priorities.
249
SAM4S Series [DATASHEET]
Atmel-11100K-ATARM-SAM4S-Datasheet_09-Jun-15
12.11.2.3 MPU Region Number Register
Name: MPU_RNR
Access: Read/Write
The MPU_RNR selects which memory region is referenced by the MPU_RBAR and MPU_RASRs.
• REGION: MPU Region Referenced by the MPU_RBAR and MPU_RASRs
Indicates the MPU region referenced by the MPU_RBAR and MPU_RASRs.
The MPU supports 8 memory regions, so the permitted values of this field are 0–7.
Normally, the required region number is written to this register before accessing the MPU_RBAR or MPU_RASR. How-
ever, the region number can be chan ged by writing to the MPU_ RBAR with th e VALID bit set to 1; see “MPU Region Base
Address Register” . This write update s the value of the REGION field.
31 30 29 28 27 26 25 24
––––––––
23 22 21 20 19 18 17 16
––––––––
15 14 13 12 11 10 9 8
––––––––
76543210
REGION
SAM4S Series [DATASHEET]
Atmel-11100K-ATARM-SAM4S-Datasheet_09-Jun-15
250
12.11.2.4 MPU Region Base Address Register
Name: MPU_RBAR
Access: Read/Write
The MPU_RBAR defines th e base address o f the MPU region sele cted by the MPU_RNR, and can upda te the value of the
MPU_RNR.
Write MPU_RBAR with the VALID bit set to 1 to change the current region number and update the MPU_RNR.
• ADDR: Region Base Address
Software must ensure that the value written to the ADDR field aligns with the size of the selected region (SIZE field in the
MPU_RASR).
If the region size is configured to 4 GB, in the MPU_RASR, there is no valid ADDR field. In this case, the region occupies
the complete memory map, and the base address is 0x00000000.
The base address is aligne d to the size of the reg ion. For exam ple, a 64 KB region must be aligned on a multiple o f 64 KB,
for example, at 0x00010000 or 0x00020000.
• VALID: MPU Region Number Valid
Write:
0: MPU_RNR not changed, and the processor updates the base address for the region specified in the MPU_RNR, and
ignores the value of the REGION field.
1: The processor updates the value of the MPU_RNR to the value of the REGION field, a nd updates the base address for
the region specified in the REGION field.
Always reads as zero.
• REGION: MPU Region
For the behavior on writes, see the description of the VALID field.
On reads, returns the current region number, as specified by the MPU_RNR.
31 30 29 28 27 26 25 24
ADDR
23 22 21 20 19 18 17 16
ADDR
15 14 13 12 11 10 9 8
ADDR
76543210
ADDR VALID REGION
251
SAM4S Series [DATASHEET]
Atmel-11100K-ATARM-SAM4S-Datasheet_09-Jun-15
12.11.2.5 MPU Region Attribute and Size Register
Name: MPU_RASR
Access: Read/Write
The MPU_RASR defines the region size and memory attributes of the MPU region specified by the MPU_RNR, and
enables that region and any subregions.
MPU_RASR is accessible using word or halfword accesses:
• The most significant halfword holds the region attributes.
• The least significant halfword holds the region size, and the region and subregion enable bits.
• XN: Instruction Access Disable
0: Instruction fetches enabled.
1: Instruction fetches disabled.
• AP: Access Permission
See Table 12-38 .
• TEX, C, B: Memory Access Attributes
See Table 12-36 .
• S: Shareable
See Table 12-36 .
• SRD: Subregion Disable
For each bit in this field:
0: Corresponding subregion is enabled.
1: Corresponding subreg ion is disabled.
See “Subregions” for more information.
Region sizes of 128 bytes an d less do not support subregion s. When writing the attribu tes for such a region, write the SRD
field as 0x00.
31 30 29 28 27 26 25 24
–––XN– AP
23 22 21 20 19 18 17 16
–– TEX SCB
15 14 13 12 11 10 9 8
SRD
76543210
– – SIZE ENABLE
SAM4S Series [DATASHEET]
Atmel-11100K-ATARM-SAM4S-Datasheet_09-Jun-15
252
• SIZE: Size of the MPU Protection Region
The minimum permitted value is 3 (b00010).
The SIZE field defines the size of the MPU memory region specified by the MPU_RNR. as follows:
(Region size in bytes) = 2(SIZE+1)
The smallest permitted region size is 32B, corresponding to a SIZ E valu e of 4. The table below gives an example of SIZE
values, with the corresponding region size and value of N in the MPU_RBAR.
Note: 1. In the MPU_RBAR; see “MPU Region Base Address Register”
• ENABLE: Region Enable
Note: For information about access permission, see “MPU Access Permission Attributes” .
SIZE Value Region Size Value of N(1) Note
b00100 (4) 32 B 5 Minimum permitted size
b01001 (9) 1 KB 10 –
b10011 (19) 1 MB 20 –
b11101 (29) 1 GB 30 –
b11111 (31) 4 GB b01100 Maximum possible size
253
SAM4S Series [DATASHEET]
Atmel-11100K-ATARM-SAM4S-Datasheet_09-Jun-15
12.11.2.6 MPU Region Base Address Register Alias 1
Name: MPU_RBAR_A1
Access: Read/Write
The MPU_RBAR defines th e base address o f the MPU region sele cted by the MPU_RNR, and can upda te the value of the
MPU_RNR.
Write MPU_RBAR with the VALID bit set to 1 to change the current region number and update the MPU_RNR.
• ADDR: Region Base Address
Software must ensure that the value written to the ADDR field aligns with the size of the selected region.
The value of N depends on the region size. The ADDR field is bits[31:N] of the MPU_RBAR. The region size, as specified
by the SIZE field in the MPU_RASR, defines the value of N:
N = Log2(Region size in bytes),
If the region size is configured to 4 GB, in the MPU_RASR, there is no valid ADDR field. In this case, the region occupies
the complete memory map, and the base address is 0x00000000.
The base address is aligne d to the size of the reg ion. For exam ple, a 64 KB region must be aligned on a multiple o f 64 KB,
for example, at 0x00010000 or 0x00020000.
• VALID: MPU Region Number Valid
Write:
0: MPU_RNR not changed, and the processor updates the base address for the region specified in the MPU_RNR, and
ignores the value of the REGION field.
1: The processor updates the value of the MPU_RNR to the value of the REGION field, a nd updates the base address for
the region specified in the REGION field.
Always reads as zero.
• REGION: MPU Region
For the behavior on writes, see the description of the VALID field.
On reads, returns the current region number, as specified by the MPU_RNR.
31 30 29 28 27 26 25 24
ADDR
23 22 21 20 19 18 17 16
ADDR
15 14 13 12 11 10 9 8
ADDR
76543210
ADDR VALID REGION
SAM4S Series [DATASHEET]
Atmel-11100K-ATARM-SAM4S-Datasheet_09-Jun-15
254
12.11.2.7 MPU Region Attribute and Size Register Alias 1
Name: MPU_RASR_A1
Access: Read/Write
The MPU_RASR defines the region size and memory attributes of the MPU region specified by the MPU_RNR, and
enables that region and any subregions.
MPU_RASR is accessible using word or halfword accesses:
• The most significant halfword holds the region attributes.
• The least significant halfword holds the region size, and the region and subregion enable bits.
• XN: Instruction Access Disable
0: Instruction fetches enabled.
1: Instruction fetches disabled.
• AP: Access Permission
See Table 12-38 .
• TEX, C, B: Memory Access Attributes
See Table 12-36 .
• S: Shareable
See Table 12-36 .
• SRD: Subregion Disable
For each bit in this field:
0: Corresponding subregion is enabled.
1: Corresponding subreg ion is disabled.
See “Subregions” for more information.
Region sizes of 128 bytes an d less do not support subregion s. When writing the attribu tes for such a region, write the SRD
field as 0x00.
31 30 29 28 27 26 25 24
–––XN– AP
23 22 21 20 19 18 17 16
–TEXSCB
15 14 13 12 11 10 9 8
SRD
76543210
– – SIZE ENABLE
255
SAM4S Series [DATASHEET]
Atmel-11100K-ATARM-SAM4S-Datasheet_09-Jun-15
• SIZE: Size of the MPU Protection Region
The minimum permitted value is 3 (b00010).
The SIZE field defines the size of the MPU memory region specified by the MPU_RNR. as follows:
(Region size in bytes) = 2(SIZE+1)
The smallest permitted region size is 32B, corresponding to a SIZ E valu e of 4. The table below gives an example of SIZE
values, with the corresponding region size and value of N in the MPU_RBAR.
Note: 1. In the MPU_RBAR; see “MPU Region Base Address Register”
• ENABLE: Region Enable
Note: For information about access permission, see “MPU Access Permission Attributes” .
SIZE Value Region Size Value of N(1) Note
b00100 (4) 32 B 5 Minimum permitted size
b01001 (9) 1 KB 10 –
b10011 (19) 1 MB 20 –
b11101 (29) 1 GB 30 –
b11111 (31) 4 GB b01100 Maximum possible size
SAM4S Series [DATASHEET]
Atmel-11100K-ATARM-SAM4S-Datasheet_09-Jun-15
256
12.11.2.8 MPU Region Base Address Register Alias 2
Name: MPU_RBAR_A2
Access: Read/Write
The MPU_RBAR defines th e base address o f the MPU region sele cted by the MPU_RNR, and can upda te the value of the
MPU_RNR.
Write MPU_RBAR with the VALID bit set to 1 to change the current region number and update the MPU_RNR.
• ADDR: Region Base Address
Software must ensure that the value written to the ADDR field aligns with the size of the selected region.
The value of N depends on the region size. The ADDR field is bits[31:N] of the MPU_RBAR. The region size, as specified
by the SIZE field in the MPU_RASR, defines the value of N:
N = Log2(Region size in bytes),
If the region size is configured to 4 GB, in the MPU_RASR, there is no valid ADDR field. In this case, the region occupies
the complete memory map, and the base address is 0x00000000.
The base address is aligne d to the size of the reg ion. For exam ple, a 64 KB region must be aligned on a multiple o f 64 KB,
for example, at 0x00010000 or 0x00020000.
• VALID: MPU Region Number Valid
Write:
0: MPU_RNR not changed, and the processor updates the base address for the region specified in the MPU_RNR, and
ignores the value of the REGION field.
1: The processor updates the value of the MPU_RNR to the value of the REGION field, a nd updates the base address for
the region specified in the REGION field.
Always reads as zero.
• REGION: MPU Region
For the behavior on writes, see the description of the VALID field.
On reads, returns the current region number, as specified by the MPU_RNR.
31 30 29 28 27 26 25 24
ADDR
23 22 21 20 19 18 17 16
ADDR
15 14 13 12 11 10 9 8
ADDR
76543210
ADDR VALID REGION
257
SAM4S Series [DATASHEET]
Atmel-11100K-ATARM-SAM4S-Datasheet_09-Jun-15
12.11.2.9 MPU Region Attribute and Size Register Alias 2
Name: MPU_RASR_A2
Access: Read/Write
The MPU_RASR defines the region size and memory attributes of the MPU region specified by the MPU_RNR, and
enables that region and any subregions.
MPU_RASR is accessible using word or halfword accesses:
• The most significant halfword holds the region attributes.
• The least significant halfword holds the region size, and the region and subregion enable bits.
• XN: Instruction Access Disable
0: Instruction fetches enabled.
1: Instruction fetches disabled.
• AP: Access Permission
See Table 12-38 .
• TEX, C, B: Memory Access Attributes
See Table 12-36 .
• S: Shareable
See Table 12-36 .
• SRD: Subregion Disable
For each bit in this field:
0: Corresponding subregion is enabled.
1: Corresponding subreg ion is disabled.
See “Subregions” for more information.
Region sizes of 128 bytes an d less do not support subregion s. When writing the attribu tes for such a region, write the SRD
field as 0x00.
31 30 29 28 27 26 25 24
–––XN– AP
23 22 21 20 19 18 17 16
–– TEX SCB
15 14 13 12 11 10 9 8
SRD
76543210
– – SIZE ENABLE
SAM4S Series [DATASHEET]
Atmel-11100K-ATARM-SAM4S-Datasheet_09-Jun-15
258
• SIZE: Size of the MPU Protection Region
The minimum permitted value is 3 (b00010).
The SIZE field defines the size of the MPU memory region specified by the MPU_RNR. as follows:
(Region size in bytes) = 2(SIZE+1)
The smallest permitted region size is 32B, corresponding to a SIZ E valu e of 4. The table below gives an example of SIZE
values, with the corresponding region size and value of N in the MPU_RBAR.
Note: 1. In the MPU_RBAR; see “MPU Region Base Address Register”
• ENABLE: Region Enable
Note: For information about access permission, see “MPU Access Permission Attributes” .
SIZE Value Region Size Value of N(1) Note
b00100 (4) 32 B 5 Minimum permitted size
b01001 (9) 1 KB 10 –
b10011 (19) 1 MB 20 –
b11101 (29) 1 GB 30 –
b11111 (31) 4 GB b01100 Maximum possible size
259
SAM4S Series [DATASHEET]
Atmel-11100K-ATARM-SAM4S-Datasheet_09-Jun-15
12.11.2.10 MPU Region Base Address Register Alias 3
Name: MPU_RBAR_A3
Access: Read/Write
The MPU_RBAR defines th e base address o f the MPU region sele cted by the MPU_RNR, and can upda te the value of the
MPU_RNR.
Write MPU_RBAR with the VALID bit set to 1 to change the current region number and update the MPU_RNR.
• ADDR: Region Base Address
Software must ensure that the value written to the ADDR field aligns with the size of the selected region.
The value of N depends on the region size. The ADDR field is bits[31:N] of the MPU_RBAR. The region size, as specified
by the SIZE field in the MPU_RASR, defines the value of N:
N = Log2(Region size in bytes),
If the region size is configured to 4 GB, in the MPU_RASR, there is no valid ADDR field. In this case, the region occupies
the complete memory map, and the base address is 0x00000000.
The base address is aligne d to the size of the reg ion. For exam ple, a 64 KB region must be aligned on a multiple o f 64 KB,
for example, at 0x00010000 or 0x00020000.
• VALID: MPU Region Number Valid
Write:
0: MPU_RNR not changed, and the processor updates the base address for the region specified in the MPU_RNR, and
ignores the value of the REGION field.
1: The processor updates the value of the MPU_RNR to the value of the REGION field, a nd updates the base address for
the region specified in the REGION field.
Always reads as zero.
• REGION: MPU Region
For the behavior on writes, see the description of the VALID field.
On reads, returns the current region number, as specified by the MPU_RNR.
31 30 29 28 27 26 25 24
ADDR
23 22 21 20 19 18 17 16
ADDR
15 14 13 12 11 10 9 8
ADDR
76543210
ADDR VALID REGION
SAM4S Series [DATASHEET]
Atmel-11100K-ATARM-SAM4S-Datasheet_09-Jun-15
260
12.11.2.11 MPU Region Attribute and Size Register Alias 3
Name: MPU_RASR_A3
Access: Read/Write
The MPU_RASR defines the region size and memory attributes of the MPU region specified by the MPU_RNR, and
enables that region and any subregions.
MPU_RASR is accessible using word or halfword accesses:
• The most significant halfword holds the region attributes.
• The least significant halfword holds the region size, and the region and subregion enable bits.
• XN: Instruction Access Disable
0: Instruction fetches enabled.
1: Instruction fetches disabled.
• AP: Access Permission
See Table 12-38 .
• TEX, C, B: Memory Access Attributes
See Table 12-36 .
• S: Shareable
See Table 12-36 .
• SRD: Subregion Disable
For each bit in this field:
0: Corresponding subregion is enabled.
1: Corresponding subreg ion is disabled.
See “Subregions” for more information.
Region sizes of 128 bytes an d less do not support subregion s. When writing the attribu tes for such a region, write the SRD
field as 0x00.
31 30 29 28 27 26 25 24
–––XN– AP
23 22 21 20 19 18 17 16
–– TEX SCB
15 14 13 12 11 10 9 8
SRD
76543210
– – SIZE ENABLE
261
SAM4S Series [DATASHEET]
Atmel-11100K-ATARM-SAM4S-Datasheet_09-Jun-15
• SIZE: Size of the MPU Protection Region
The minimum permitted value is 3 (b00010).
The SIZE field defines the size of the MPU memory region specified by the MPU_RNR. as follows:
(Region size in bytes) = 2(SIZE+1)
The smallest permitted region size is 32B, corresponding to a SIZ E valu e of 4. The table below gives an example of SIZE
values, with the corresponding region size and value of N in the MPU_RBAR.
Note: 1. In the MPU_RBAR; see “MPU Region Base Address Register”
• ENABLE: Region Enable
Note: For information about access permission, see “MPU Access Permission Attributes” .
SIZE Value Region Size Value of N(1) Note
b00100 (4) 32 B 5 Minimum permitted size
b01001 (9) 1 KB 10 –
b10011 (19) 1 MB 20 –
b11101 (29) 1 GB 30 –
b11111 (31) 4 GB b01100 Maximum possible size
SAM4S Series [DATASHEET]
Atmel-11100K-ATARM-SAM4S-Datasheet_09-Jun-15
262
12.12 Glossary
This glossary describes some of the terms used in technical documents from ARM.
Abort A mechanism that indicates to a processor that the value associated with a memory access is invalid.
An abort can be caused by the external or internal memory system as a result of attempting to a ccess
invalid instruction or data memory.
Aligned A data item stored at an address that is divisible by the number of bytes that defines the data size is
said to be aligned. Aligned words and ha lfwords have addresses that are divisible by four and two
respectively. The terms word-aligned and halfword-aligned therefore stipulate addresses that are
divisible by four and two respectively.
Banked register A register that has multiple physical copies, where the state of the processor determines which copy is
used. The Stack Pointer, SP (R13) is a banked register.
Base register In instructio n descriptions, a register specified by a load or store instruction that is used to hold the
base value for the instruction’s address calculation. Depending on the instru ction and its addressing
mode, an offset can be added to or subtracted from the base register value to form the address that is
sent to memory.
See also “Index register” .
Big-endian (BE) Byte ordering scheme in which bytes of decreasing significance in a data word are stored at
increasing addresses in memory.
See also “Byte-invariant” , “Endianness” , “Little-endian (LE)” .
Big-endian memory Memory in which:
a byte or halfword at a word-aligned address is the most significant byte or ha lfword within the word at
that address,
a byte at a halfword-aligned address is the most significant byte within the halfword at that address.
See also “Little-endian memory” .
Breakpoint A breakpoint is a mechanism provided by debuggers to identify an instruction at which program
execution is to be halted. Breakpoints are inserted by the programmer to enable inspection of register
contents, memory locations, variable values at fixed points in the program execution to test that the
program is operating correctly. Breakpoints are removed after the program is successfully tested.
263
SAM4S Series [DATASHEET]
Atmel-11100K-ATARM-SAM4S-Datasheet_09-Jun-15
Byte-invariant In a byte-invariant system, the address of each byte of memory remains unchanged whe n switching
between little-endian and big-endian operation. When a data item larger than a byte is loaded from or
stored to memory, the bytes making up that data item are arranged into the correct order depending
on the endianness of the memory access.
An ARM byte-invariant implementation also supports unaligned halfword and word memory accesses.
It expects multi-word accesses to be word-aligned.
Cache A block of on-chip or off-chip fast access memory locations, situated between the processor and main
memory, used for storing and retrieving copies of often used instructions, data, or instructions and
data. This is done to greatly increase the average speed of memory accesses and so improve
processor performance.
Condition field A four-bit field in an instruction that specifies a condition under which the instruction can execute.
Conditional execution If the condition code flags indicate that the corresponding condition is true when the instruction starts
executing, it executes normally. Otherwise, the instruction does nothing.
Context The environment that each process operates in for a multitasking operating system. In ARM
processors, this is limited to mean the physical address range that it can access in memory and the
associated memory access permissions.
Coprocessor A processor that supplements the main processor. Cortex-M4 does not su pport any coprocessors.
Debugger A debugging system that includes a program, use d to dete ct, locate, and correct software faults,
together with custom hardware that supports software debugging.
Direct Memory Access
(DMA) An operation that accesses main memory directly, withou t the processor performing any accesses to
the data concerned.
Doubleword A 64-bit data item. The contents are taken as being an unsig ned integer unless otherwise stated.
Doubleword-aligned A data item having a memory address that is divisible by eight.
Endianness Byte ordering. The scheme that determines the order that successive bytes of a data word are stored
in memory. An aspect of the system’s memory mapping.
See also “Little-endian (LE)” and “Big-endian (BE)” .
SAM4S Series [DATASHEET]
Atmel-11100K-ATARM-SAM4S-Datasheet_09-Jun-15
264
Exception
An event that interrupts program execution. When an exception occurs, the processor suspends the
normal program flow and starts execution at the address indicated by the corresponding exception
vector. The indicated address contains the first instruction of the handler for the exception.
An exception can be an interrupt request, a fault, or a software-generated system exception. Faults
include attempting an invalid memory access, attempting to execute an instructio n in an invalid
processor state, and attempting to execute an undefined instruction.
Exception service routine See “Interrupt handler” .
Exception vector See “Interrupt vector” .
Flat address mapping A system of organizing memory in which each physical address in the memory space is the same as
the corresponding virtual address.
Halfword A 16-bit data item.
Illegal instruction An instruction that is architecturally Undefined.
Implementation-defined The behavior is not architecturally defined, but is defined and documented by individual
implementations.
Implementation-specific The behavior is not architecturally defined, and does not have to be documented by individual
implementations. Used when there are a number of implementation options available and the option
chosen does not affect software compatibility.
Index register In some load and store instruction descriptions, the value of this register is used as an offset to be
added to or subtracted from the base register value to form the address that is sent to memory. Some
addressing modes optiona lly enable the index register value to be shifted prior to the additio n or
subtraction.
See also “Base register” .
Instruction cycle count The number of cycles that an instruction occupies the Execute stage of the pipeline.
Interrupt handler A program that control of the processor is passed to when an interrupt occurs.
Interrupt vector One of a number of fixed addresses in low memory, or in high memory if high vectors are configured,
that contains the first instruction of the corresponding interrupt handler.
265
SAM4S Series [DATASHEET]
Atmel-11100K-ATARM-SAM4S-Datasheet_09-Jun-15
Little-endian (LE) Byte ordering scheme in which bytes of increasing significance in a data word are stored at increasing
addresses in memory.
See also “Big-endian (BE)” , “Byte-invariant” , “Endianness” .
Little-endian memory Memory in which:
a byte or halfword at a word-aligned address is the least significant byte or halfword within the word at
that address,
a byte at a halfword-aligned address is the least significant byte within the halfword at that address.
See also “Big-endian memory” .
Load/store architecture A processor architecture where da ta-processing operations only operate on register contents, not
directly on memory contents.
Memory Protection Unit
(MPU) Hardware that controls access permissions to blocks of memory. An MPU does not perform any
address translation.
Prefetching In pipelined processors, the process of fetching instructions from memory to fill up the pipeline before
the preceding instructions have finished executing. Prefetching an instruction does not mean that the
instruction has to be executed.
Preserved Preserved by writing the same value back that has been previously read from the same field on the
same processor.
Read Reads are defined as memory operations that have the semantics of a load. Reads include the Thumb
instructions LDM, LDR, LDRSH, LDRH, LDRSB, LDRB, and POP.
Region A partition of memory space.
Reserved A field in a control register or instruction format is reserved if the field is to be defined by the
implementation, or produces Unpredictable results if the contents of the field are not zero. These fields
are reserved for use in future extensions of the architecture or are implementation-specific. All
reserved bits not used by the implementation must be written as 0 and read as 0.
Thread-safe In a multi-tasking environment, thread-safe functions use safeguard mechanisms when accessing
shared resources, to ensure correct operation without the risk of shared access conflicts.
Thumb instruction One or two halfwords that specify an operation for a processor to perform. Thumb instructions must be
halfword-aligned.
SAM4S Series [DATASHEET]
Atmel-11100K-ATARM-SAM4S-Datasheet_09-Jun-15
266
Unaligned A data item stored at an address that is not divisible by the number of bytes that defines the data size
is said to be unaligned. For example, a word stor ed at an address that is not divisible by four.
Undefined Indicates an instruction that generates an Undefined instruction exception.
Unpredictable One cannot rely on the behavior. Unpredictable behavior must not represent security holes.
Unpredictable behavior must not halt or hang the processor, or any parts of the system.
Warm reset Also known as a core reset. Initializes the majority of the processor excluding the debug controller and
debug logic. This type of reset is useful if debugging features of a processor.
WA See “Write-allocate (WA)” .
WB See “Write-back (WB)” .
Word A 32-bit data item.
Write Writes are defined as operations that have the semantics of a store. Writes include the Thumb
instructions STM, STR, STRH, STRB, and PUSH.
Write-allocate (WA) In a write-allocate cache, a cache miss on storing data causes a cache line to be allocated into the
cache.
Write-back (WB) In a write-back cache, data is only written to main memory when it is forced out of the cache on line
replacement following a cache miss. Otherwise, writes by the processor only update the cache. This is
also known as copyback.
Write buffer A block of high-speed memory, arranged as a FIFO buffer , between the data cache and main memory,
whose purpose is to optimize stores to main memory.
Write-through (WT) In a write-through cache, data is written to main memory at the same time as the cache is updated.
267
SAM4S Series [DATASHEET]
Atmel-11100K-ATARM-SAM4S-Datasheet_09-Jun-15
13. Debug and Test Features
13.1 Description
The SAM4 series microcontrollers feature a number of complementary debug and test capabilities. The Serial
Wire/JTAG Debug Port (SWJ-DP) combining a Ser ial Wire Debug Port (SW-DP) and JTAG Debug (JTAG-DP) port
is used for standard debuggin g functions, such as downloading code and single-step ping through programs. It also
embeds a serial wire trace.
13.2 Embedded Characteristics
Debug access to all memor y and registers in the system, including Cortex-M4 register bank whe n the core is
running, halted, or held in reset
Serial Wire Debug Port (SW-DP) and Serial Wire JTAG Debug Port (SWJ-DP) debug access
Flash Patch and Breakpoint (FPB) unit for implementing breakp oin ts and code patches
Data Watchpoint and Trace (DWT) unit for implementing watchpoints, data tracing, and system profiling
Instrumentation Tr ace Macrocell (ITM) for support of printf style debugging
IEEE1149.1 JTAG Boundary scan on all digital pins
Figure 13-1 . Debug and Test Block Di agram
TST
TMS
TCK/SWCLK
TDI
JTAGSEL
TDO/TRACESWO
Boundary
TAP SWJ-DP
Reset
and
Test
POR
SAM4S Series [DATASHEET]
Atmel-11100K-ATARM-SAM4S-Datasheet_09-Jun-15
268
13.3 Application Examples
13.3.1 Debug Environment
Figure 13-2 shows a complete debug environment example. The SWJ-DP interface is used for standard
debugging functions, such as downloading code and single-stepping through the program and viewing core and
peripheral registers.
Figure 13-2. Application Debug Environment Example
13.3.2 Test Environment
Figure 13-3 shows a test environment example (JTAG Boun dary scan). Test vectors are sent and interpreted by
the tester. In this example, the “board in test” is designed using a number of JTAG-compliant devices. These
devices can be connected to form a single scan chain.
SAM4
Host Debugger
PC
SAM4-based Application Board
SWJ-DP
Connector
SWJ-DP
Emulator/Probe
269
SAM4S Series [DATASHEET]
Atmel-11100K-ATARM-SAM4S-Datasheet_09-Jun-15
Figure 13-3. Application Te st Environment Example
13.4 Debug and Test Pin Description
Chip 2
Chip n
Chip 1
SAM4
SAM4-based Application Board In Test
JTAG
Connector
Tester
Test Adaptor
JTAG
Probe
Table 13-1. Debug and Test Signal List
Signal Name Function Type Active Level
Reset/Test
NRST Microcontroller Reset Input/Output Low
TST Test Select Input
SWD/JTAG
TCK/SWCLK Test Clock/Serial Wire Clock Input
TDI Test Data In Input
TDO/TRACESWO Test Data Out/Trace Asynchronous Data Out Output
TMS/SWDIO Test Mode Select/Serial Wire Input/Output Input
JTAGSEL JTAG Selection Input High
SAM4S Series [DATASHEET]
Atmel-11100K-ATARM-SAM4S-Datasheet_09-Jun-15
270
13.5 Functional Description
13.5.1 Test Pin
One dedic ated pin, T ST, is used to define the de vice operating mode. When this pin is at low level during power-
up, the device is in normal operating mode. When at high level, the device is in test mode or FFPI mode. The TST
pin integrates a permanent pull-down resistor of about 15 kW,so that it can be left unconnected for normal
operation. Note that when setting the TST pin to low or high level at power up, it must remain in the same state
during the duration of the whole operation.
13.5.2 Debug Architecture
Figure 13-4 shows the Deb ug Architecture used in the SAM4. The Cortex-M 4 embeds five functional units for
debug:
SWJ-DP (Serial Wire/JTAG Debug Port)
FPB (Flash Patch Breakpoint)
DWT (Data Watchpoint and Trace)
ITM (Instrumentation Trace Macrocell)
TPIU (Trace Port Interface Unit)
The debug architecture information that follows is mainly dedicated to developers of SWJ-DP Emulators/Probes
and debugging tool vendors for Cortex-M4 based microcontrollers. For further details on SWJ-DP see the Cortex-
M4 technical refe re nce manual.
Figure 13-4. Debug Architecture
13.5.3 Serial Wire/JTAG Debug Port (SWJ-DP)
The Cortex-M4 embeds a SWJ-DP Debug port which is the standard CoreSight debug port. It combines Serial
Wire Debug Port (SW-DP), from 2 to 3 pins and JTAG debug Port (JTAG-DP), 5 pins.
By default, the JTAG Debug Port is a ctive. If the host debugger wa nts to switch to the Serial Wire Debug Port, it
must provide a ded icated JTAG sequence on TMS/SWDIO and TCK/SWCLK which disables JTAG-DP and
enables SW-DP.
4 watchpoints
PC sampler
data address sampler
data sampler
interrupt trace
CPU statistics
DWT
6 breakpoints
FPB
software trace
32 channels
time stamping
ITM
SWD/JTAG
SWJ-DP
SWO trace
TPIU
271
SAM4S Series [DATASHEET]
Atmel-11100K-ATARM-SAM4S-Datasheet_09-Jun-15
When the Serial Wire Debug Port is active, TDO/TRACESWO can be used for trace. The asynchronous TRACE
output (TRACESWO) is multiple xed with TDO. So the asynchronous trace can only be used with SW-DP, not
JTAG-DP.
SW-DP or JTAG-DP mode is selected when JTAGSEL is low. It is not possible to switch directly between SWJ-DP
and JTAG boundary scan operations. A chip reset must be performed after JTAGSEL is changed.
13.5.3.1 SW-DP and JTAG-DP Selection Mechanism
Debug port selection mechanism is done by sending specific SWDIOTMS sequence. The JTAG-DP is selected by
default after reset.
Switch from JTAG-DP to SW-DP. The sequence is:
Send more than 50 SWCLKTCK cycles with SWDIOTMS = 1
Send the 16-bit sequence on SWDIOTMS = 0111100111100111 (0x79E7 MSB first)
Send more than 50 SWCLKTCK cycles with SWDIOTMS = 1
Switch from SWD to JTAG. The sequence is:
Send more than 50 SWCLKTCK cycles with SWDIOTMS = 1
Send the 16-bit sequence on SWDIOTMS = 0011110011100111 (0x3CE7 MSB first)
Send more than 50 SWCLKTCK cycles with SWDIOTMS = 1
13.5.4 FPB (Flash Patch Breakpoint)
The FPB:
Implements hardware brea kpoints
Patches code and data from code space to system space.
The FPB unit cont ain s:
Two literal comparators for matching against literal loads from Code space, and remapping to a
corresponding area in System space.
Six instruction comparators for matching against instruction fetches from Code space and remapping to a
corresponding area in System space.
Alternatively, comparators can also be configured to gener ate a Br eakpoint instr uction to the processo r co re
on a match.
13.5.5 DWT (Data Watchpoint and Trace)
The DWT contains four comparators which can be configured to generate the following:
PC sampling packets at set intervals
PC or Data watchpoint packets
Watchpoint even t to ha lt cor e
Table 13-2. SWJ-DP Pin List
Pin Name JTAG Port Serial Wire Debug Port
TMS/SWDIO TMS SWDIO
TCK/SWCLK TCK SWCLK
TDI TDI –
TDO/TRACESWO TDO TRACESWO (optional: trace)
SAM4S Series [DATASHEET]
Atmel-11100K-ATARM-SAM4S-Datasheet_09-Jun-15
272
The DWT contains counters for the items that follow:
Clock cycle (CYCCNT)
Folded instructions
Load Store Unit (LSU) operations
Sleep Cycles
CPI (all instruction cycles except for the first cycle)
Interrupt overhead
13.5.6 ITM (Instrumentation Trace Macrocell)
The ITM is an application driven trace source that supports printf style debugging to trace Operating System (OS)
and application events, and emits diagnostic system information. The ITM emits trace information as packets
which can be generated by three different sources with several priority levels:
Sof tware trace : Soft ware can write dir ectly to ITM stimulus registers. This can be done thanks to the “printf”
function. For more information, refer to Section 13.5.6.1 “How to Configure the ITM”.
Hardware trace: The ITM emits packets generated by the DWT.
Time stamping: Timestamps are emitted relative to packets. The ITM contains a 21-bit counter to generate
the timestamp.
13.5.6.1 How to Configure the ITM
The following example describes how to output trace data in asynchronous trace mode.
Configure the TPIU for asynchronous trace mode (refer to Section 13.5.6.3 “5.4.3. How to Configure the
TPIU”)
Enable the write accesses into the ITM registers by writing “0xC5ACCE55” into the Lock Access Register
(Address: 0xE0000FB0)
Write 0x00010015 into the Trace Control Register:
Enable ITM
Enable Synchronization packets
Enable SWO behavior
Fix the ATB ID to 1
Write 0x1 into the Trace Enable Register:
Enable the Stimulus port 0
Write 0x1 into the Trace Privilege Register:
Stimulus port 0 only accessed in privileged mode (Clearing a bit in this register will result in the
corresponding stimulus port being accessible in user mode.)
Write into the Stimulus port 0 register: TPIU (Trace Port Interface Unit)
The TPIU acts as a bridge between the on-chip trace data and the Instruction Trace Macrocell (ITM).
The TPIU formats and transmits trace data off- chip at fre quencies asynchronous to the core.
13.5.6.2 Asynchronous Mode
The TPIU is configured in asynchronous mode, trace data are output using the single TRACESWO pin. The
TRACESWO signal is multiplexed with the TDO signal of the JTAG Debug Po rt. As a con sequence, asynchr onous
trace mode is only available when the Serial Wire De bug mode is selected since TDO signal is used in JTAG
debug mode.
Two encoding formats are available for the single pin output:
Manchester encoded stream. This is the reset value.
NRZ_based UART byte structure
273
SAM4S Series [DATASHEET]
Atmel-11100K-ATARM-SAM4S-Datasheet_09-Jun-15
13.5.6.3 5.4.3. How to Configure the TPIU
This example only concerns the asynchronous trace mode.
Set the TRCENA bit to 1 into the Debug Exception and Monitor Register (0xE000EDFC) to enable the use of
trace and debug blocks.
Write 0x2 into the Selected Pin Protocol Register
Select the Serial Wire Output – NRZ
Write 0x100 into the Formatter and Flush Control Register
Set the suitable clock prescaler value into the Async Clock Prescaler Register to scale the baud rate of the
asynchronous output (this can be done automatically by the debugging tool).
13.5.7 IEEE® 1149.1 JTAG Boundary Scan
IEEE 1149.1 JTAG Boundary Scan allows pin-level access independent of the device packaging technology.
IEEE 1149.1 JTAG Boundary Scan is enabled when TST is tied to low, while JTAGSEL is high during power-up,
and must be kept in this state during the whole boundary scan operation. The SAMPLE, EXTEST and BYPASS
functions are implemented. In SWD/JTAG debug mode, the ARM processor responds with a non-JTAG chip ID
that identifies the processor. This is not IEEE 1149.1 JTAG-compliant.
It is not possible to switch directly between JTAG Boundary Scan and SWJ Debug Port operations. A chip reset
must be performed after JTAGSEL is changed.
A Boundary-scan Descriptor Language (BSDL) file is provided on Atmel’s web site to set up the test.
13.5.7.1 JTAG Boundary-scan Register
The Boundary-scan Register (BSR) contains a number of bits which correspond to active pins and associated
control signals.
Each SAM4 input/output pin correspond s to a 3-bit register in the BSR. The OUTPUT bit contains data that can be
forced on the pad. The INPUT bit facilitates the observability of data applied to the pad. The CONTROL bit selects
the direction of the pad.
For more inform a tion , ple a se re fe r to BDSL files available for the SAM4 Series.
SAM4S Series [DATASHEET]
Atmel-11100K-ATARM-SAM4S-Datasheet_09-Jun-15
274
13.5.8 ID Code Register
Access: Read-only
• VERSION[31:28]: Product Version Number
Set to 0x0.
• PART NUMBER[27:12]: Product Part Number
• MANUFACTURER IDENTITY[11:1]
Set to 0x01F.
• Bit[0] Required by IEEE Std. 1149.1.
Set to 0x1.
31 30 29 28 27 26 25 24
VERSION PART NUMBER
23 22 21 20 19 18 17 16
PART NUMBER
15 14 13 12 11 10 9 8
PART NUMBER MANUFACTURER IDENTITY
76543210
MANUFACTURER IDENTITY 1
Chip Name Chip ID
SAM4S 0x05B32
Chip Name JTAG ID Code
SAM4S 0x05B3203F
275
SAM4S Series [DATASHEET]
Atmel-11100K-ATARM-SAM4S-Datasheet_09-Jun-15
14. Reset Controller (RSTC)
14.1 Description
The Reset Controller (RSTC), based on power-on reset cells, handles all the resets of the system without any
external components. It reports which reset occurred last.
The Reset Controller also drives independently or simultaneously the external reset and the peripheral and
processor resets.
14.2 Embedded Characteristics
Management of All System Resets, Including
External Devices through the NRST Pin
Processor Reset
Processor Peripheral Set Reset
Based on Embedded Power-on Cell
Reset Source Status
Status of the Last Rese t
Either Software Reset, User Reset, Watchdog Reset
External Reset Signal Shaping
14.3 Block Diagram
Figure 14-1. Reset Controller Block Diagram
NRST
proc_nreset
wd_fault
periph_nreset
SLCK
Reset
State
Manager
Reset Controller
rstc_irq
NRST
Manager exter_nreset
nrst_out
core_backup_reset
WDRPROC
user_reset
vddcore_nreset
SAM4S Series [DATASHEET]
Atmel-11100K-ATARM-SAM4S-Datasheet_09-Jun-15
276
14.4 Functional Description
14.4.1 Reset Controller Overview
The Reset Controller is made up of an NRST manager and a reset state manager. It runs at slow clock and
generates the following reset signals:
proc_nreset: processor reset line (also resets the Watchdog Timer)
periph_nreset: affects the whole set of embedded peripherals
nrst_out: drives the NRST pin
These reset signals are asserted by the Reset Controller, either on events generated by peripherals, events on
NRST pin, or on software a ction. The res et state ma nager controls the generation of reset signals and provides a
signal to the NRST manager when an assertion of the NRST pin is required.
The NRST manager shapes the NRST assertion during a programmable time, thus controlling external device
resets.
The Reset Controller Mode Register (RSTC_MR), used to configure the Rese t Controller, is powered with VDDIO,
so that its configuration is saved as long as VDDIO is on.
14.4.2 NRST Manager
The NRST manager samples the NRST input pin and drives this pin low when required by the reset state
manager. Figure 14-2 shows the block diagram of the NRST manager.
Figure 14-2. NRST Manager
14.4.2.1 NRST Signal or Interrupt
The NRST ma nager samples the N RST pin at slow clock speed . When the line is detec ted low, a User Reset is
reported to the reset state manager.
However, the NRST manager can be programmed to not trigger a reset when an assertion of NRST occurs.
Writing a 0 to the URSTEN bit in the RSTC_MR disables the User Reset trigger.
The level of the pin NRST can be read at any time in the bit NRSTL (NR ST level) in the Rese t Controller Status
Register (RSTC_SR). As soon as the NRST pin is asserted, bit UR STS in the RSTC_SR is set. This bit is cleared
only when the RSTC_SR is read.
The Reset Contr oller can also be pr ogra mmed to gener ate an interr upt instea d of gener ating a rese t. To do so, set
the URSTIEN bit in the RSTC_MR.
External Reset Timer
URSTS
URSTEN
ERSTL
exter_nreset
URSTIEN
RSTC_MR
RSTC_MR
RSTC_MR
RSTC_SR
NRSTL
nrst_out
NRST
rstc_irq
Other
interrupt
sources
user_reset
277
SAM4S Series [DATASHEET]
Atmel-11100K-ATARM-SAM4S-Datasheet_09-Jun-15
14.4.2.2 NRST External Reset Control
The reset state manager asserts the signal exter_nreset to assert the NRST pin. When this occurs, the “nrst_out”
signal is driven lo w by the NRST manager for a time prog ramme d by field ERSTL in t he RSTC_ MR. T his as ser tion
duration, named External Reset Length, lasts 2(ERSTL+1) slow clock cycles. This gives the approximate duration of
an assertion between 60 µs and 2 seconds. Note that ERSTL at 0 de fines a two-cycl e duration for the NRST
pulse.
This feature allows the Reset Controller to shape the NRST pin level, and thus to guarantee that the NRST line is
driven low for a time compliant with potential external devices connected on the system reset.
RSTC_MR is backed up, making it possible to use th e ERSTL field to shape the system power-u p reset for devices
requiring a longer startup time than that of the slow clock oscillator.
14.4.3 Reset States
The reset state manager ha ndles the different re se t sour ces and ge nerates the intern al rese t signals. It repor ts the
reset status in field RSTTYP of the Status Register (RSTC_SR). The update of RSTC_SR.RSTTYP is performed
when the proc ess or res et is relea s e d.
14.4.3.1 General Reset
A general reset occurs when a VDDIO power-on-reset is detected, a brownout or a voltage regulation loss is
detected by the Supply Controller. The vddcore_nreset signal is asserted by the Supply Controller when a general
reset occurs.
All the reset signals are released and field RSTC_SR.RSTTYP reports a general reset. As the RSTC_MR is reset,
the NRST line rises two cycles after the vddcore_nreset, as ERSTL defaults at value 0x0.
Figure 14-3 shows how the general reset affects the reset signals.
Figure 14-3. General Reset Stat e
14.4.3.2 Backup Reset
A backup reset occurs when the chip exits from Backup mode. While exiting Backup mode, the vddcore_nreset
signal is asserted by the Supply Controller.
SLCK
periph_nreset
proc_nreset
NRST
(nrst_out)
External Reset Length
= 2 cycles
MCK
Processor Startup
= 2 cycles
vddio_nreset
Any
Freq.
RSTTYP XXX 0x0 = General Reset XXX
SAM4S Series [DATASHEET]
Atmel-11100K-ATARM-SAM4S-Datasheet_09-Jun-15
278
Field RSTC_SR.RSTTYP is updated to report a backup reset.
14.4.3.3 Watchdog Reset
The watchdog reset is entered when a watchdog fault occurs. This reset lasts three slow clock cycles.
When in watchdog reset, assertion of the reset signals depends on the WDRPROC bit in the WDT_MR:
If WDRPROC = 0, the processor reset and the periphera l reset are asserted. The NRST line is also
asserted, depending on how field RSTC_MR.ERSTL is programmed. However, the resulting low level on
NRST does not result in a user reset state.
If WDRPROC = 1, only the processor reset is asserted.
The Watchdog Timer is reset by the proc_nreset signal. As the watchdog fault always causes a processor reset if
WDRSTEN in the WDT_MR is set, the Watchdog Timer is always reset after a watchdog reset, and the Watchdog
is enabled by default and with a period set to a maximum.
When bit WDT_MR.WDRSTEN is reset, the watchdog fault has no impact on the Reset Controller.
Figure 14-4. Watchdog Reset
14.4.3.4 Software Reset
The Reset Controller offers commands to assert the different reset signals. These commands are performed by
writing the Control Register (RSTC_CR) with the following bits at 1:
RSTC_CR.PROCRST: Writing a 1 to PROCRST resets the processor and the watchdog timer.
RSTC_CR.PERRST: Writing a 1 to PERRST resets all the embedded peripherals including the memory
system, and, in particular, the Remap Command. The Peripheral Reset is generally used for debu g
purposes.
Except for debug purposes, PERRST must always be used in conjunction with PROCRST (PERRST and
PROCRST set both at 1 simultaneously).
RSTC_CR.EXTRST: Writing a 1 to EXTRST asserts low the NRST pin duri ng a time defined by the field
RSTC_MR.ERSTL.
Only if
WDRPROC = 0
SLCK
periph_nreset
proc_nreset
wd_fault
NRST
(nrst_out)
EXTERNAL RESET LENGTH
8 cycles (ERSTL=2)
MCK
Processor Startup
= 2 cycles
Any
Freq.
RSTTYP Any XXX 0x2 = Watchdog Reset
279
SAM4S Series [DATASHEET]
Atmel-11100K-ATARM-SAM4S-Datasheet_09-Jun-15
The software reset is entered if at least one of these bits is set by the software. All these commands can be
performed independently or simultaneously. The software reset lasts three slow clock cycles.
The internal reset signals are asserted as soon as the register write is performed. This is detected on the Master
Clock (MCK). They are released when the software reset has ended, i.e., synchronously to SLCK.
If EXTRST is set, the nrst_out signal is asserted depending on the configuration of field RSTC_MR.ERSTL.
However, the resulting falling edge on NRST does not lead to a user reset.
If and only if the PROCRST bit is set, the Reset Controller reports the software status in field RSTC_SR.RSTTYP.
Other software resets are not reported in RSTTYP.
As soon as a softw are operatio n is detected , the bit SRCMP (Software Reset Command in Progress) is set in the
RSTC_SR. SRCMP is cleared at the end of the software reset. No other software reset can be performed while the
SRCMP bit is set, and writing any value in the RSTC_CR has no effect.
Figure 14-5. Software Reset
14.4.3.5 User Reset
The user reset is entered when a low level is detected on the NRST pin and bit URSTEN in the RSTC_MR is at 1.
The NRST input signal is resynchronized with SLCK to insure proper behavior of the system.
The user reset is entered as soon as a low level is detected on NRST. The processor reset and the peripheral
reset are asserted.
The user reset ends when NRST rises, after a two-cycle resynchronization time and a three-cycle processor
startup. The processor clock is re-enabled as soon as NRST is confirmed high.
When the processor reset signal is released, field RSTC_SR.RSTTYP is loaded with the value 0x4, indicating a
user reset.
SLCK
periph_nreset
if PERRST=1
proc_nreset
if PROCRST=1
Write RSTC_CR
NRST
(nrst_out)
if EXTRST=1
EXTERNAL RESET LENGTH
8 cycles (ERSTL=2)
MCK
Processor Startup
= 2 cycles
Any
Freq.
RSTTYP Any XXX 0x3 = Software Reset
Resynch.
1 cycle
SRCMP in RSTC_SR
SAM4S Series [DATASHEET]
Atmel-11100K-ATARM-SAM4S-Datasheet_09-Jun-15
280
The NRST manager guarantees that the NRST line is asserted for External Reset Length slow clock cycles, as
programmed in field RSTC_MR.ERSTL. However, if NRST does not rise after External Reset Length because it is
driven low externally, the interna l res et line s re ma in asse rt ed until NRST actually rises.
Figure 14-6. User Reset State
14.4.4 Reset State Priorities
The reset state manager manages the pr iorities among the di fferent reset sources. The resets are listed in order of
priority as follows:
1. General reset
2. Backup reset
3. Watchdog reset
4. Software reset
5. User reset
Particular cases are listed below:
When in user reset:
A watchdog event is impossible because the W atchdog T imer is being reset by the proc_nrese t signal.
A software reset is impossible, since the processor reset is being activated.
When in software reset:
A watchdog event ha s pr ior ity over the current state.
The NRST has no effect.
When in watchdog reset:
The processor reset is active and so a software reset cannot be programmed.
A user reset cann ot be ente re d.
SLCK
periph_nreset
proc_nreset
NRST
NRST
(nrst_out)
>= EXTERNAL RESET LENGTH
MCK
Processor Startup
= 2 cycles
Any
Freq.
Resynch.
2 cycles
RSTTYP Any XXX
Resynch.
2 cycles
0x4 = User Reset
281
SAM4S Series [DATASHEET]
Atmel-11100K-ATARM-SAM4S-Datasheet_09-Jun-15
14.5 Reset Controller (RSTC) User Interface
Note: 1. This value assumes that a general reset has been performed, subject to change if other types of reset are generated.
Table 14-1 . Register Mapping
Offset Register Name Access Reset
0x00 Control Register RSTC_CR Write-only –
0x04 Status Register RSTC_SR Read-only 0x0000_ 0000(1)
0x08 Mode Register RSTC_MR Read/Write 0x0000 0001
SAM4S Series [DATASHEET]
Atmel-11100K-ATARM-SAM4S-Datasheet_09-Jun-15
282
14.5.1 Reset Controller Control Register
Name: RSTC_CR
Address: 0x400E1400
Access: Write-only
• PROCRST: Processor Reset
0: No effect
1: If KEY is correct, resets the processor
• PERRST: Peripheral Reset
0: No effect
1: If KEY is correct, resets the peripherals
• EXTRST: External Reset
0: No effect
1: If KEY is correct, asserts the NRST pin
• KEY: System Reset Key
31 30 29 28 27 26 25 24
KEY
23 22 21 20 19 18 17 16
––––––––
15 14 13 12 11 10 9 8
––––––––
76543210
––––EXTRSTPERRST–PROCRST
Value Name Description
0xA5 PASSWD Writing any other value in this field aborts the write operation.
283
SAM4S Series [DATASHEET]
Atmel-11100K-ATARM-SAM4S-Datasheet_09-Jun-15
14.5.2 Reset Controller Status Register
Name: RSTC_SR
Address: 0x400E1404
Access: Read-only
• URSTS: User Reset Status
A high-to-low transition of the NRST pin sets the URSTS bit. This transition is also detected on the MCK ri sing edge. If the
user reset is disabled (URSTEN = 0 in RSTC_MR) and if the interruption is e nabled b y the URSTIEN bit in the RSTC_MR,
the URSTS bit triggers an interrupt. Reading the RSTC_SR resets the URSTS bit and clears the interrupt.
0: No high-to-low edge on NRST happened since the last read of RSTC_SR.
1: At least one high-to-low transition of NRST has been detected since the last read of RSTC_SR.
• RSTTYP: Reset Type
This field reports the cause of the last processor reset. Reading this RSTC_SR does not reset this field.
• NRSTL: NRST Pin Level
This bit registers the NRST pin level sampled on each Master Clock (MCK) rising edge.
• SRCMP: Software Reset Command in Progress
When set, this bit indicates that a software reset command is in progress and that no further software re set should be per-
formed until the end of the current one. This bit is automatically cleared at the end of the current software reset.
0: No software command is being performed by the Reset Controller. The Re set Controller is ready for a software
command.
1: A software reset command is being performed by the Reset Controller. The Reset Controller is busy.
31 30 29 28 27 26 25 24
––––––––
23 22 21 20 19 18 17 16
––––––SRCMPNRSTL
15 14 13 12 11 10 9 8
––––– RSTTYP
76543210
–––––––URSTS
Value Name Description
0 GENERAL_RST First power-up reset
1 BACKUP_RST Return from Backup Mode
2 WDT_RST Watchdog fault occurred
3 SOFT_RST Processor reset required by the software
4 USER_RST NRST pin detected low
5– Reserved
6– Reserved
7– Reserved
SAM4S Series [DATASHEET]
Atmel-11100K-ATARM-SAM4S-Datasheet_09-Jun-15
284
14.5.3 Reset Controller Mode Register
Name: RSTC_MR
Address: 0x400E1408
Access: Read/Write
This register can on ly be writte n if the W PEN bit is clea re d in the Syst em Con trolle r Writ e Pro te ctio n M od e Register
(SYSC_WPMR).
• URSTEN: User Reset Enable
0: The detection of a low level on the NRST pin does not generate a user reset.
1: The detection of a low level on the NRST pin triggers a user reset.
• URSTIEN: User Reset Interrupt Enable
0: USRTS bit in RSTC_SR at 1 has no effect on rstc_irq.
1: USRTS bit in RSTC_SR at 1 asserts rstc_irq if URSTEN = 0.
• ERSTL: Exte rna l Re se t Le n g th
This field defines the external reset length. The external reset is asserted during a time of 2(ERSTL+1) slow clock cycles. This
allows assertion duration to be programmed between 60 µs and 2 seconds. Note that synchronization cycles must also be
considered when calculating the actual reset length as previously described.
• KEY: Write Access Password
31 30 29 28 27 26 25 24
KEY
23 22 21 20 19 18 17 16
––––––––
15 14 13 12 11 10 9 8
–––– ERSTL
76543210
–––URSTIEN–––URSTEN
Value Name Description
0xA5 PASSWD Writing any other value in this field aborts the write operation.
Always reads as 0.
285
SAM4S Series [DATASHEET]
Atmel-11100K-ATARM-SAM4S-Datasheet_09-Jun-15
15. Real-time Timer (RTT)
15.1 Description
The Real-time Timer (RTT) is built around a 32-bit counter used to count roll-ove r events of the progra mma ble 16-
bit prescaler driven from th e 32-kHz slow clock source. It g enerate s a periodi c interr upt and/or trigger s an alarm on
a programmed value.
The RTT can also be configured to be driven by the 1Hz RTC signal, thus taking ad vantage of a calibrated 1Hz
clock.
The slow clock source can be fully disabled to reduce power consumption when only an elapsed seconds count is
required.
15.2 Embedded Characteristics
32-bit Free-running Counter on prescaled slow clock or RTC calibrated 1Hz clock
16-bit Configurable Prescaler
Interrupt on Alarm or Counter Increment
15.3 Block Diagram
Figure 15-1. Real-time Timer
SLCK
RTPRES
RTTINC
ALMS
16-bit
Prescaler
32-bit
Counter
ALMV =
CRTV
RTT_MR
RTT_VR
RTT_AR
RTT_SR
RTTINCIEN
RTT_MR
0
10
ALMIEN
rtt_int
RTT_MR
set
set
RTT_SR
read
RTT_SR
reset
reset
RTT_MR
reload
rtt_alarm
RTTRST
RTT_MR
RTTRST
RTT_MR
RTTDIS
10
RTT_MR
RTC1HZ
RTC 1Hz
SAM4S Series [DATASHEET]
Atmel-11100K-ATARM-SAM4S-Datasheet_09-Jun-15
286
15.4 Functional Description
The programmable 16-b it prescaler value can be configured thro ugh the RTPRES field in the “Real-time Time r
Mode Register” (RTT_MR).
Configuring the RTPRES field value to 0x8000 (default value) corresponds to feeding the real-time counter with a
1Hz signal (if the slow clock is 32.768 kHz). The 32-bit counter can count up to 232 seconds, corresponding to
more than 136 years, then roll over to 0. Bit RTTINC in the “Real-time Timer Status Register” (RTT_SR) is set
each time there is a prescaler roll-over (see Figure 15-2)
The real-time 32-bit counter can also be supplied by t he 1Hz RTC clock. This mode is interesting when the RTC
1Hz is calibrated (CORRECTION field ≠ 0 in RTC_MR) in order to guaranty the synchronism between RTC and
RTT counters.
Setting the RTC1HZ bit in the RTT_MR drives the 32-bit RTT counter from the 1Hz RTC clock. In this mode, the
RTPRES field has no effect on the 32-bit counter.
The prescaler roll-over generates an increment of the real-time timer counter if RTC1HZ = 0. Otherwise, if
RTC1HZ = 1, the real-time timer counter is incremented every second. The RTTINC bit is set independently from
the 32-bit counter increment.
The real-time timer can also be used as a free-running timer with a lower time-base. The best accuracy is achieved
by writing RTPRES to 3 in RTT_MR.
Programming RTPRES to 1 or 2 is forbidden.
If the RTT is configured to trigger an interrupt, the inte rrupt occu rs two slow clock cycles after reading the RTT_SR.
To prevent several executions of the interrupt handler, the interrupt must be disabled in the interrupt handler and
re-enabled when the RTT_SR is cleared.
The CRTV field can be read at any time in the “Real-time Timer Value Register” (RTT_VR). As this value can be
updated asynchronously with the Master Clock, the CRTV field must be read twice at the same value to read a
correct value.
The current value of the counter is compared with the value written in the “Real-time Timer Alarm Register”
(RTT_AR). If the counter value matches the alarm, the ALMS bit in the RTT_SR is set. The RTT_AR is set to its
maximum value (0xFFFF_FFFF) after a reset.
The ALMS flag is always a source of the RTT alarm signal that may be used to exit the system from low power
modes (see Figure 15-1).
The alarm interrupt must be disabled (ALMIEN must be cleared in RTT_MR) when writing a new ALMV value in
the RTT_AR.
The RTTINC bit can be used to start a periodic interrupt, the period being one second when the RTPRES field
value = 0x8000 and the slow clock = 32.768 kHz.
The RTTINCIEN bit must be cleared prior to writing a new RTPRES value in the RTT_MR.
Reading the RTT_SR automatically clears the RTTINC and ALMS bits.
Writing the RTTRST bit in the RTT_MR immediately reloads and restarts the clock divider with the new
programmed value. This also resets the 32-bit counter.
When not used, the Real-time Timer can be disabled in order to suppress dynamic power consumption in this
module. This can be achieved by setting the RTTDIS bit in the RTT_MR.
287
SAM4S Series [DATASHEET]
Atmel-11100K-ATARM-SAM4S-Datasheet_09-Jun-15
Figure 15-2. RTT Counting
Prescaler
ALMVALMV-10 ALMV+1
0
RTPRES - 1
CRTV
read RTT_SR
ALMS (RTT_SR)
APB Interface
SLCK
RTTINC (RTT_SR)
ALMV+2 ALMV+3
...
APB cycle
APB cycle
SAM4S Series [DATASHEET]
Atmel-11100K-ATARM-SAM4S-Datasheet_09-Jun-15
288
15.5 Real-time Ti mer (RTT) User Interface
Table 15-1 . Register Mapping
Offset Register Name Access Reset
0x00 Mode Register RTT_MR Read/Write 0x0000_8000
0x04 Alarm Register RTT_AR Read/Write 0xFFFF_FFFF
0x08 Value Regi ster RTT_VR Read-only 0x0000_0000
0x0C Status Register R TT_SR Read-only 0x0000_0000
289
SAM4S Series [DATASHEET]
Atmel-11100K-ATARM-SAM4S-Datasheet_09-Jun-15
15.5.1 Real-time Timer Mode Register
Name: RTT_MR
Address: 0x400E1430
Access: Read/Write
• RTPRES: Real-time Timer Prescaler Value
Defines the number of SLCK periods required to increment the Real-time timer. RTPRES is defined as follows:
RTPRES = 0: The prescaler period is equal to 216 * SLCK periods.
RTPRES = 1 or 2: forbidden.
RTPRES ≠ 0,1 or 2: The prescaler period is equal to RTPRES * SLCK periods.
Note: The RTTINCIEN bit must be cleared prior to writing a new RTPRES value.
• ALMIEN: Alarm Interrupt Enable
0: The bit ALMS in RTT_SR has no effect on interrupt.
1: The bit ALMS in RTT_SR asserts interrupt.
• RTTINCIEN: Real-time Timer Increment Interrupt Enable
0: The bit RTTINC in RTT_SR has no effect on interrupt.
1: The bit RTTINC in RTT_SR asserts interrupt.
• RTTRST: Real-time Timer Restart
0: No effect.
1: Reloads and re starts the clock divider with the new programmed value. This also resets the 32-bit counter.
• RTTDIS : Real-time Timer Disable
0: The real-time timer is enabled.
1: The real-time timer is disabled (no dynamic power cons um p tion) .
Note: RTTDIS is write only.
• RTC1HZ: Real-Time Clock 1Hz Clock Selection
0: The RTT 32-bit counter is driven by the 16-bit prescaler roll-over events.
1: The RTT 32-bit counter is driven by the 1Hz RTC clock.
Note: RTC1HZ is write only.
31 30 29 28 27 26 25 24
–––––––RTC1HZ
23 22 21 20 19 18 17 16
– – – RTTDIS – RTTRST RTTINCIEN ALMIEN
15 14 13 12 11 10 9 8
RTPRES
76543210
RTPRES
SAM4S Series [DATASHEET]
Atmel-11100K-ATARM-SAM4S-Datasheet_09-Jun-15
290
15.5.2 Real-time Timer Alarm Register
Name: RTT_AR
Address: 0x400E1434
Access: Read/Write
• ALMV: Alarm Value
When the CRTV valu e in RTT_ VR eq u als th e ALM V field , th e ALMS flag is set in RTT_SR. As soon as the ALMS flag
rises, the CRTV value equals ALMV+1 (refer to Figure 15-2).
Note: The alarm interrupt must be disabled (ALMIEN must be cleared in RTT_MR) when writing a new ALMV value.
31 30 29 28 27 26 25 24
ALMV
23 22 21 20 19 18 17 16
ALMV
15 14 13 12 11 10 9 8
ALMV
76543210
ALMV
291
SAM4S Series [DATASHEET]
Atmel-11100K-ATARM-SAM4S-Datasheet_09-Jun-15
15.5.3 Real-time Timer Value Register
Name: RTT_VR
Address: 0x400E1438
Access: Read-only
• CRTV: Current Real-time Value
Returns the curre n t valu e of the Real- tim e Time r.
Note: As CRTV can be updated asynchronously, it must be read twice at the same value.
31 30 29 28 27 26 25 24
CRTV
23 22 21 20 19 18 17 16
CRTV
15 14 13 12 11 10 9 8
CRTV
76543210
CRTV
SAM4S Series [DATASHEET]
Atmel-11100K-ATARM-SAM4S-Datasheet_09-Jun-15
292
15.5.4 Real-time Timer Status Register
Name: RTT_SR
Address: 0x400E143C
Access: Read-only
• ALMS: Real-time Ala rm Status (cleared on read)
0: The Real-time Alarm has not occurred since the last read of RTT_SR.
1: The Real-time Alarm occurred since the last read of RTT_SR.
• RTTINC: Prescaler Roll-over Status (cleared on read)
0: No prescaler roll-over occurred since the last read of the RTT_SR.
1: Prescaler roll-over occurred since the last read of the RTT_SR.
31 30 29 28 27 26 25 24
––––––––
23 22 21 20 19 18 17 16
––––––––
15 14 13 12 11 10 9 8
––––––––
76543210
––––––RTTINCALMS
293
SAM4S Series [DATASHEET]
Atmel-11100K-ATARM-SAM4S-Datasheet_09-Jun-15
16. Real-time Clock (RTC)
16.1 Description
The Real-time Clock (RTC) periphe ral is designed for very low power consumption. For optimal fun ctionality, the
RTC requires an accurate external 32.768 kHz clock, which can be provided by a crystal oscillator.
It combines a complete time-of-day clock with alarm and a Gregorian or Persian calendar, complemented by a
programmable periodic interrupt. The alarm and calendar registers are accessed by a 32-bit data bus.
The time and calendar values are cod ed in binary-coded de cimal (BCD) format. The time format can be 2 4-hour
mode or 12-hour mode with an AM/PM indicator.
Updating time a nd calendar fields and configuring the alar m fields are performed by a parallel captur e on the 32-bit
data bus. An entry control is performed to avoid loading registers with incompatible BCD format data or with an
incompatible da te acco rd in g to th e cur ren t mo nt h/ yea r /ce nt ur y.
A clock divider calibration circuitry can be used to compensate for crystal oscillator frequency inaccuracy.
An RTC output can be pro grammed to generate several waveforms , including a prescaled clock derived from
32.768 kHz.
16.2 Embedded Characteristics
Ultra Low Power Consumption
Full Asynchronous Design
Gregorian Calendar up to 2099 or Persian Calendar
Programmable Periodic Interrupt
Safety/security features:
Valid Time and Date Programmation Check
On-The-Fly Time and Date Validity Check
Crystal Oscillator Clock Calibration
Waveform Generation
Register Write Protection
SAM4S Series [DATASHEET]
Atmel-11100K-ATARM-SAM4S-Datasheet_09-Jun-15
294
16.3 Block Diagram
Figure 16-1. RTC Block Diagram
16.4 Product Dependencies
16.4.1 Power Management
The Real-time Clock is continuously clocked at 3 2.768 kHz. The Power Management Contro ller has no effect on
RTC behavior.
16.4.2 Interrupt
RTC interrup t line is con ne cted on o ne of the in tern al sour ce s of the interrupt controller. RTC interrupt requires the
interrupt controller to be programmed first.
16.5 Functional Description
The RTC provid es a full binary-c oded decimal (BC D) clock that inclu des century (1 9/20), year (with le ap years),
month, date, day, hours, minutes and seconds reported in RTC Time Register (RTC_TIMR) and RTC Calendar
Register (RTC_CALR).
The valid year range is up to 2099 in Gregorian mode (or 1300 to 1499 in Persian mode).
The RTC can operate in 24-hour mode or in 12-hour mode with an AM/PM indicator.
Corrections for leap years a re includ ed (a ll ye ar s divisi ble b y 4 being leap years except 1900). This is correct up to
the year 2099.
The RTC can generate configurable waveforms on RTCOUT0/1 outputs.
16.5.1 Reference Clock
The reference clock is the Slow Clock (SLCK) . It c an be dr ive n int er nally or by an ex te rn al 32 .7 68 kHz crysta l.
During low power modes of the processor, the oscillator runs and power consumption is critical. The crystal
selection has to take into account the current consumption for power saving and the frequency drift due to
temperat ur e ef fec t on the cir cuit for tim e ac cu ra cy.
User Interface
32768 Divider Time
Slow Clock: SLCK
System Bus
Date
RTC Interrupt
Entry
Control
Interrupt
Control
Clock Calibration
RTCOUT0
RTCOUT1
Wave
Generator
Alarm
Table 16-1. Peripheral IDs
Instance ID
RTC 2
295
SAM4S Series [DATASHEET]
Atmel-11100K-ATARM-SAM4S-Datasheet_09-Jun-15
16.5.2 Timing
The RTC is updated in real time at one-second intervals in no rmal mode for the counters of seconds, at one-
minute intervals for the counter of minutes and so on.
Due to the asynchronous op eration of the RTC with respect to the rest of the chip, to be certain that the value read
in the RTC registers (century, year, month, date, day, hours, minutes, seconds) are valid and stable, it is
necessary to read these reg isters twice. If the data is the same both times, then it is valid. Therefore , a minimum of
two and a maximum of three accesses are required.
16.5.3 Alarm
The RTC has five prog ra m ma b le fie lds: mo nth, date, hours, minutes and seconds.
Each of these fields can be enabled or disabled to match the alarm condition:
If all the fields are enabled, an alarm flag is generated (the cor responding flag is asserted and an interrupt
generated if enabled) at a given month, date, hour/minute/second.
If only the “seconds” field is enabled, then an alarm is generated every minute.
Depending on the combination of fields enabled, a large num ber of possibilities are available to the user ranging
from minutes to 365/366 days.
Hour, minute and second matching alarm (SECEN, MINEN, HOUREN) can be enabled independently of SEC,
MIN, HOUR fields.
Note: To change one of the SEC, MIN, HOUR, DATE, MONTH fields, it is recommended to disable the field before changing
the value and then re-enable it after the change has been made. This requires up to three accesses to the
RTC_TIMALR or RTC _CALALR. The first access clears the enable corresponding to the field to change (SECEN,
MINEN, HOUREN, DATEEN, MTHEN). If the fi eld is already cleared, this access is not required. The second access
performs the change of the value (SEC, MIN, HOUR, DATE, MONTH). The third access is required to re-enable the
field by writing 1 in SECEN, MINEN, HOUREn, DATEEN, MTHEN fields.
16.5.4 Error Checking when Programming
Verification on user interface data is performed when accessing the century, year, month, date, day, hours,
minutes, seconds and alarms. A check is performed on illegal BCD entries such as illegal date of the month with
regard to the year and century configured.
If one of the time fields is not correct, the data is not loaded into the register/counter and a flag is set in the validity
register. The user can not reset this flag. It is reset as soon as an acceptable value is programmed. This avoids
any further side effects in the hardware. The same procedure is followed for the alarm.
The following checks are perfor me d :
1. Century (check if it is in range 19–20 or 13–14 in Persian mode)
2. Year (BCD entry check)
3. Date (check range 01–31)
4. Month (check if it is in BCD range 01–12, check validity regarding “date”)
5. Day (check range 1–7)
6. Hour (BCD checks: in 24-hour mode, check range 00–23 and check that AM/PM flag is not set if RTC is set
in 24-hour mode; in 12-hour mode check range 01–12)
7. Minute (check BCD and range 00–59)
8. Second (check BCD and range 00–59)
Note: If the 12-hour mode is selected by means of the RTC Mode Register (RTC_MR), a 12-hour value can be programmed
and the returned value on RTC_TIMR will be the corresponding 24-hour value. Th e entry con trol checks the value of
the AM/PM indicator (bit 22 of RTC_TIMR) to determine the range to be checked.
SAM4S Series [DATASHEET]
Atmel-11100K-ATARM-SAM4S-Datasheet_09-Jun-15
296
16.5.5 RTC Internal Free Running Counter Error Checking
To improve the reliability and security of the RTC, a permanent ch eck is per formed on the internal free running
counters to report non-BCD or invalid date/time values.
An error is reported by TDERR bit in the status register (RTC_SR) if an incorrect value has been detected. The
flag can be cleared by setting the TDERRCLR bit in the Status Clear Command Register (RTC_SCCR).
Anyway the TDERR error flag will be set again if the source of the error has not been cleared before clearing the
TDERR flag. The clearing of the source of such error can be done either by reprogramm ing a correct value on
RTC_CALR and/or RTC_TIMR.
The RTC internal free running counters may aut omatically clear the source of TD ERR due to their roll-over (i.e.,
every 10 seconds for SECONDS[3:0] field in RTC_TIMR). In this case the T DERR is held high until a clear
command is asserted by TDERRCLR bit in RTC_SCCR.
16.5.6 Updating Time/Calendar
To update any of the time/calendar fie lds, the user must first stop the RTC by setting the cor responding field in the
Control Register (RTC_CR). Bit UPDTIM must be set to update time fields (hour, minute, second) and bit UPDCAL
must be set to update calendar fields (century, year, month, date, day).
The ACKUPD bit is autom atically set within a second af ter setting the UPDTIM and/or UPDCAL bit (meaning one
second is the maximum duration of the polling or wait for interrupt period). Once ACKUPD is set, it is mandatory to
clear this flag by writing the corresponding bit in the RTC_SCCR, after which the user can write to the Time
Register, the Calendar Register, or both.
Once the update is finished, the user must clear UPDTIM and/or UPDCAL in the RTC_CR.
When entering programm ing mode of the calendar fields, the time fields remain enabled. When entering the
programming mode of the time fields, both time and calendar fields are stopped. This is due to the location of the
calendar logic circuity (downstream for low-power considerations). It is highly recomm ended to prepare all the
fields to be updated before entering programmin g mode. In successive up date operations, the user mu st wait at
least one second after resetting the UPDTIM/UPDCAL bit in the RTC_CR before setting these bits a gain. This is
done by waiting for the SEC flag in the RTC_SR before setting UPDTIM/UPDCAL bit. After clearing
UPDTIM/UPDCAL, the SEC flag must also be cleared.
297
SAM4S Series [DATASHEET]
Atmel-11100K-ATARM-SAM4S-Datasheet_09-Jun-15
Figure 16-2. Update Sequence
Prepare Time or Calendar Fields
Set UPDTIM and/or UPDCAL
bit(s) in RTC_CR
Read RTC_SR
ACKUPD
= 1 ?
Clear ACKUPD bit in RTC_SCCR
Update Time and/or Calendar values in
RTC_TIMR/RTC_CALR
Clear UPDTIM and/or UPDCAL bit in
RTC_CR
No
Yes
Begin
End
Polling or
IRQ (if enabled)
SAM4S Series [DATASHEET]
Atmel-11100K-ATARM-SAM4S-Datasheet_09-Jun-15
298
16.5.7 RTC Accurate Clock Calibration
The crystal oscillator that drives the RTC may not be as accurate as expected mainly due to temperature variation.
The RTC is equipped with circuitry able to correct slow clock crystal drift.
To compensate fo r possible temperature varia tions over time, this accurate clock ca libration circuitry can be
programmed on-the-fly and also programmed during application manufac turing, in order to correct the crysta l
frequency ac curacy at r oom tempera ture (20– 25°C). The typical clock drift range at roo m temperatur e is ±20 ppm.
In the device operating temperature range, the 32.768 kHz crystal oscillator clock inaccuracy can be up to -200
ppm.
The RTC clock calibration circuitry allows positive or negative correction in a range of 1.5 ppm to 1950 ppm.
The calibration circuitry is fully digital. Thus, the configured correction is independent of temperature, voltage ,
process, etc., and no additional measurement is required to check that the correction is effective.
If the correction value conf igured in the calibration circuitry results from an accurate crystal frequency measure,
the remaining ac cu ra cy is bounded by the va lue s liste d be low:
Below 1 ppm, for an initial crystal drift between 1.5 ppm up to 20 ppm, and from 30 ppm to 90 ppm
Below 2 ppm, for an initial crystal drift between 20 ppm up to 30 ppm, and from 90 ppm to 130 ppm
Below 5 ppm, for an initial crystal drift between 130 ppm up to 200 ppm
The calibration circuitry does not modify the 32.768 kHz crystal oscillator clock frequency but it acts by slightly
modifying the 1 Hz clock period from time to time. When the period is modified, depending on the sign of the
correction, the 1 Hz clock period increases or reduces by around 4 ms. Depending on the CORRECTION,
NEGPPM and HIGHPPM values configured in RTC_MR, the period interval between two correction events differ s.
Figure 16-3. Calibration circuitry
32.768 kHz
Oscillator
Other Logic
RTC
Time/Calendar
1Hz
CORRECTION, HIGHPPM
Integrator
Comparator
Divider by 32768
Add
32.768 kHz
NEGPPM
Suppress
299
SAM4S Series [DATASHEET]
Atmel-11100K-ATARM-SAM4S-Datasheet_09-Jun-15
Figure 16-4. Calibration circuitry waveforms
The inaccuracy of a crystal oscillator at typical room temperature (±20 ppm at 20–25 °C) can be compensated if a
reference clock/signal is used to measure such inaccuracy. This kind of calibration operation can be set up during
Time
Monotonic 1Hz
Counter value
32.768 kHz -50ppm
32.768 kHz +50ppm
Crystal frequency
remains unadjusted
Internal 1Hz clock
is adjusted
Phase adjustment
(~4ms)
User configurable period
(integer multiple of 1s or 20s)
Time
-50ppm
-25ppm
-50ppm correction period
-25ppm correction period
Nominal 32.768 kHz
Crystal clock
Internally divided clock (256Hz)
Internally divided clock (128Hz)
Clock pulse periodically suppressed
when correction period elapses
128 Hz clock edge delayed by 3,906 ms
when correction period elapses
Internally divided clock (256Hz)
Internally divided clock (128Hz)
Internally divided clock (64Hz)
128 Hz clock edge delayed by 3,906 ms
when correction period elapses
Clock edge periodically added
when correction period elapses
1.000 second
1.003906 second
1.000 second
0.996094 second
NEGATIVE CORRECTION
POSITIVE CORRECTION
SAM4S Series [DATASHEET]
Atmel-11100K-ATARM-SAM4S-Datasheet_09-Jun-15
300
the final product manufacturing by means of measurement equipment embedding such a reference clock. The
correction of value must be programmed into the (RTC_MR), and this value is kept as long as the circuitry is
powered (backup area). Removing the backup power supply ca ncels this calibration. This room temperature
calibration can be further processed by means of the networking capability of the target application.
To ease the comparison of the inherent crystal accuracy with the reference clock/signal during manufacturing, an
internal prescaled 32.768 kHz clock derivative signal can be assigned to drive RTC output. To accommodate the
measure, several clock frequencies can be selected among 1 Hz, 32 Hz, 64 Hz, 512 Hz.
The clock calibration correction drives the internal RTC counters but can also be observed in the RTC output when
one of the following three frequencies 1 Hz, 32 Hz or 64 Hz is configured. The correction is not visible in the RTC
output if 512 Hz frequency is configured.
In any event, this adjustment does not take into account the temperature variat ion.
The frequency drift (u p to -200 ppm) due to temperature variation can be compensated using a reference tim e if
the application c an access such a refe rence. If a reference time cannot be used, a temperature sensor can be
placed close to the crystal oscillator in order to get the operating temperature of the crystal oscillator. Once
obtained, the temper ature may be converte d using a loo kup table (describ ing the accuracy/temper ature curve of
the crystal oscillator used) and RTC_MR configured accordingly. The calibration can be performed on-the-fly. This
adjustment method is not base d on a measurement of t he crystal fre quency/drift and the refore can be improved by
means of the networking capability of the target application.
If no crystal frequency a djustment has been done durin g manufacturing, it is still possible to do it. In the case
where a reference tim e of the day can be obtained through LAN/WAN network, it is possible to calculate the drift of
the application crystal oscillator by comparing the values read on RTC Time Register (RTC_TIMR) and
programming the HIGHPPM and CORRECTION fields on RTC_MR according to the difference measured
between the reference time and those of RTC_TIMR.
16.5.8 Waveform Generation
Waveforms can be genera ted by the RTC in order to take adva ntage of the RTC inherent p rescalers while the RTC
is the only powered circuitry (low power mode of operation, backup mode) or in any active modes. Going into
backup or low power operating modes does not affect the waveform generation outputs.
The RTC outputs (RTCOUT0 and RTCOUT1) have a source driver selected among seven possibilities.
The first selection choice sticks the associated output at 0 (This is the reset value and it can be used at any time to
disable the waveform generation).
Selection choices 1 to 4 respectively select 1 Hz, 32 Hz, 64 Hz and 512 Hz.
32 Hz or 64 Hz can drive, for example, a TN LCD backplane signal while 1 Hz can be used to drive a blinking
character like “:” for basic time display (hour, minute) on TN LCDs.
Selection choice 5 provides a toggling signal when the RTC alarm is reached.
Selection choice 6 provides a cop y of the a lar m flag, so th e associated ou tput is set high ( logical 1) wh en an alar m
occurs and immediately cleared when software clears the alarm interrupt source.
Selection choice 7 provides a 1 Hz periodic high pulse of 15 µs duration th at ca n be used to drive external de vices
for power consumption reduction or any other purpose.
PIO lines associated to RTC outputs are automatically selecting these waveforms as soon as RTC_MR
corresponding fields OUT0 and OUT1 differ from 0.
301
SAM4S Series [DATASHEET]
Atmel-11100K-ATARM-SAM4S-Datasheet_09-Jun-15
Figure 16-5. Waveform Generation
RTCOUT1
‘0’
1 Hz
32 Hz
64 Hz
512 Hz
toggle_alarm
flag_alarm
pulse
0
1
2
3
4
5
6
7
RTC_MR(OUT1)
RTCOUT0
‘0’
1 Hz
32 Hz
64 Hz
512 Hz
toggle_alarm
flag_alarm
pulse
0
1
2
3
4
5
6
7
RTC_MR(OUT0)
flag_alarm
alarm match
event 1
RTC_SCCR(ALRCLR)
alarm match
event 2
RTC_SCCR(ALRCLR)
toggle_alarm
pulse
Tperiod Tperiod
Thigh
SAM4S Series [DATASHEET]
Atmel-11100K-ATARM-SAM4S-Datasheet_09-Jun-15
302
16.6 Real-time Clock (RTC) User Interface
Note: If an offset is not listed in the table it must be considered as reserved.
Table 16-2. Register Mapping
Offset Register Name Access Reset
0x00 Control Reg ister RTC_CR Read/Write 0x0
0x04 Mode Regi ster RTC_MR Read/Write 0x0
0x08 Time Register RTC_TIMR Read/Write 0x0
0x0C Calendar Register RTC_CALR Read/Write 0x01A11020
0x10 Time Alarm Register RTC_TIMALR Read/Write 0x0
0x14 Calendar Alarm Register RTC_CALALR Read/Write 0x01010000
0x18 S tatus Register RTC_SR Read-only 0x0
0x1C Status Clear Command Register RTC_SCCR Write-only –
0x20 Interrupt Enable Register RTC_IER Write-only –
0x24 Interrupt Disable Register RTC_IDR Write-only –
0x28 Interrupt Mask Register RTC_IMR Read -only 0x0
0x2C Valid Entry Register RTC_VER Read-only 0x0
0x30–0xC8 Reserved – – –
0xD0 Reserved – – –
0xD4–0xF8 Reserved – – –
0xFC Reserved – – –
303
SAM4S Series [DATASHEET]
Atmel-11100K-ATARM-SAM4S-Datasheet_09-Jun-15
16.6.1 RTC Control Register
Name: RTC_CR
Address: 0x400E1460
Access: Read/Write
This register can on ly be writte n if the W PEN bit is clea re d in the Syst em Con trolle r Writ e Pro te ctio n M od e Register
(SYSC_WPMR).
• UPDTIM: Update Request Time Register
0: No effect.
1: Stops the RTC time counting.
Time counting co nsis ts of seco nd , min u te an d hou r coun te rs. Tim e cou n te rs can be pro gr amm e d on ce this bit is set and
acknowledged by the bit ACKUPD of the RTC_SR.
• UPDCAL: Update Request Calendar Register
0: No effect.
1: Stops the RTC calendar counting.
Calendar counting consists of day, date, month, year and century counters. Calendar counters can be programmed once
this bit is set and acknowledged by the bit ACKUPD of the RTC_SR.
• TIMEVSEL: Time Event Selection
The event that generates the flag TIMEV in RTC_SR depends on the value of TIMEVSEL.
31 30 29 28 27 26 25 24
––––––––
23 22 21 20 19 18 17 16
–––––– CALEVSEL
15 14 13 12 11 10 9 8
–––––– TIMEVSEL
76543210
––––––UPDCALUPDTIM
Value Name Description
0 MINUTE Minute change
1 HOUR Hour change
2 MIDNIGHT E very day at midnight
3 NOON Every day at noon
SAM4S Series [DATASHEET]
Atmel-11100K-ATARM-SAM4S-Datasheet_09-Jun-15
304
• CALEVSEL: Calendar Event Selection
The event that generates the flag CALEV in RTC_SR depends on the value of CALEVSEL
Value Name Description
0 WEEK Week change (every Monday at time 00:00:00)
1 MONTH Month change (every 01 of each month at time 00:00:00)
2 YEAR Year change (every January 1 at time 00:00:00)
305
SAM4S Series [DATASHEET]
Atmel-11100K-ATARM-SAM4S-Datasheet_09-Jun-15
16.6.2 RTC Mode Register
Name: RTC_MR
Address: 0x400E1464
Access: Read/Write
This register can on ly be writte n if the W PEN bit is clea re d in the Syst em Con trolle r Writ e Pro te ctio n M od e Register
(SYSC_WPMR).
• HRMOD: 12-/24-hour Mode
0: 24-hour mode is selected.
1: 12-hour mode is selected.
• PERSIAN: PERSIAN Calendar
0: Gregorian calendar.
1: Persian calendar.
• NEGPPM: NEGative PPM Correction
0: Positive correction (the divider will be slightly higher than 32768).
1: Negative correction (the divider will be slightly lower than 32768).
Refer to CORRECTION and HIGHPPM field descriptions.
Note: NEGPPM must be cleared to correct a crystal slower than 32.768 kHz.
• CORRECTION: Slow Clock Correction
0: No correction
1–127: The slow clock will be corrected according to the formula given in HIGHPPM description.
• HIGHPPM: HIGH PPM Correction
0: Lower range ppm correction with accurate correction.
1: Higher range ppm correction with accurate correction.
If the absolute value of the cor rection to be applied is lower than 30 ppm, it is recommended to clear HIGHPPM. HIGHPPM
set to 1 is recommended for 30 ppm correction and above.
Formula:
If HIGHPPM = 0, then the clock frequency correction range is from 1.5 ppm up to 98 ppm. The RTC accuracy is less
than 1 ppm for a range correction from 1.5 ppm up to 30 ppm.
The correction field must be programmed according to the required correction in ppm; the formula is as follows:
31 30 29 28 27 26 25 24
– – TPERIOD – THIGH
23 22 21 20 19 18 17 16
–OUT1–OUT0
15 14 13 12 11 10 9 8
HIGHPPM CORRECTION
76543210
– – – NEGPPM – – PERSIAN HRMOD
SAM4S Series [DATASHEET]
Atmel-11100K-ATARM-SAM4S-Datasheet_09-Jun-15
306
The value obtained must be rounded to the nearest integer prior to being programmed into CORRECTION field.
If HIGHPPM = 1, then the clock frequency correction ra nge is from 30.5 ppm up to 1 950 ppm. The RTC accuracy is
less than 1 ppm for a range correction from 30.5 ppm up to 90 ppm.
The correction field must be programmed according to the required correction in ppm; the formula is as follows:
The value obtained must be rounded to the nearest integer prior to be programmed into CORRECTION field.
If NEGPPM is set to 1, the ppm correction is negative (used to correct crystals that are faster than the nominal 32.768
kHz).
• OUT0: RTCOUT0 OutputSource Selection
• OUT1: RTCOUT1 Output Source Selection
• THIGH: High Duration of the Output Pulse
Value Name Description
0 NO_WAVE No waveform, stuck at ‘0’
1 F REQ1HZ 1 Hz square wave
2 FREQ32HZ 32 Hz square wave
3 FREQ64HZ 64 Hz square wave
4 FREQ512HZ 512 Hz square wave
5 A LARM_TOGGLE Output toggle s when alarm flag rises
6 ALARM_FLAG Output is a copy of the alarm flag
7 PROG_PULSE Duty cycle programmable pulse
Value Name Description
0 NO_WAVE No waveform, stuck at ‘0’
1 F REQ1HZ 1 Hz square wave
2 FREQ32HZ 32 Hz square wave
3 FREQ64HZ 64 Hz square wave
4 FREQ512HZ 512 Hz square wave
5 A LARM_TOGGLE Output toggles when alarm flag rises
6 ALARM_FLAG Output is a copy of the alarm flag
7 PROG_PULSE Duty cycle programmable pulse
Value Name Description
0 H_31MS 31.2 ms
1 H_16MS 15.6 ms
2 H_4MS 3.91 ms
CORRECTION 3906
20 ppm×
-----------------------1–=
CORRECTION 3906
ppm
------------1–=
307
SAM4S Series [DATASHEET]
Atmel-11100K-ATARM-SAM4S-Datasheet_09-Jun-15
• TPERIOD: Period of the Output Pulse
3 H_976US 976 µs
4 H_488US 488 µs
5 H_122US 122 µs
6 H_30US 30.5 µs
7 H_15US 15.2 µs
Value Name Description
0 P_1S 1 second
1 P_500MS 500 ms
2 P_250MS 250 ms
3 P_125MS 125 ms
Value Name Description
SAM4S Series [DATASHEET]
Atmel-11100K-ATARM-SAM4S-Datasheet_09-Jun-15
308
16.6.3 RTC Time Register
Name: RTC_TIMR
Address: 0x400E1468
Access: Read/Write
• SEC: Current Second
The range that can be set is 0–59 (BCD).
The lowest four bits encode the units. The higher bits encode the tens.
• MIN: Current Minute
The range that can be set is 0–59 (BCD).
The lowest four bits encode the units. The higher bits encode the tens.
• HOUR: Current Hour
The range that can be set is 1–12 (BCD) in 12-hour mode or 0–23 (BCD) in 24-hour mode.
• AMPM: Ante Meridiem Post Meridiem Indicator
This bit is the AM/PM indicator in 12-hour mode.
0: AM.
1: PM.
All non-significant bits read zero.
31 30 29 28 27 26 25 24
––––––––
23 22 21 20 19 18 17 16
–AMPM HOUR
15 14 13 12 11 10 9 8
–MIN
76543210
– SEC
309
SAM4S Series [DATASHEET]
Atmel-11100K-ATARM-SAM4S-Datasheet_09-Jun-15
16.6.4 RTC Calendar Register
Name: RTC_CALR
Address: 0x400E146C
Access: Read/Write
• CENT: Current Century
The range that can be set is 19–20 (gregorian) or 13–14 (persian) (BCD).
The lowest four bits encode the units. The higher bits encode the tens.
• YEAR: Current Year
The range that can be set is 00–99 (BCD).
The lowest four bits encode the units. The higher bits encode the tens.
• MONTH: Cu rre n t Mon th
The range that can be set is 01–12 (BCD).
The lowest four bits encode the units. The higher bits encode the tens.
• DAY: Current Day in Current Week
The range that can be set is 1–7 (BCD).
The coding of the number (which number represents which day) is user-defined as it has no effect on the date counter.
• DATE: Current Day in Current Month
The range that can be set is 01–31 (BCD).
The lowest four bits encode the units. The higher bits encode the tens.
All non-significant bits read zero.
31 30 29 28 27 26 25 24
–– DATE
23 22 21 20 19 18 17 16
DAY MONTH
15 14 13 12 11 10 9 8
YEAR
76543210
–CENT
SAM4S Series [DATASHEET]
Atmel-11100K-ATARM-SAM4S-Datasheet_09-Jun-15
310
16.6.5 RTC Time Alarm Register
Name: RTC_TIMALR
Address: 0x400E1470
Access: Read/Write
This register can on ly be writte n if the W PEN bit is clea re d in the Syst em Con trolle r Writ e Pro te ctio n M od e Register
(SYSC_WPMR).
Note: To change one of the SEC, MIN, HOUR fields, it is recommended to disable the field before changing th e value and then re-
enable it after the change has been made. This requires up to three accesses to the RTC_TIMALR. The first access clears the
enable corresponding to the field to change (SECEN, MINEN, HOUREN). If the field is already cleared, this access is not
required. The second access performs the change of the value (SEC, MIN, HOUR). The third access is required to re-enable the
field by writing 1 in SECEN, MINEN, HOUREN fields.
• SEC: Second Alarm
This field is the alarm field corresponding to the BCD-coded second counter.
• SECEN: Second Alarm Enable
0: The second-matching alarm is disabled.
1: The second-matching alarm is enabled.
• MIN: Minute Alarm
This field is the alarm field corresponding to the BCD-coded minute counter.
• MINEN: Minute Alarm Ena ble
0: The minute-matching alarm is disabled.
1: The minute-matching alarm is enabled.
• HOUR: Hour Alarm
This field is the alarm field corresponding to the BCD-coded hour counter.
• AMPM: AM/PM Indicator
This field is the alarm field corresponding to the BCD-coded hour counter.
• HOUREN: Hour Alarm Enable
0: The hour-matching alarm is disabled.
1: The hour-matching alarm is enabled.
31 30 29 28 27 26 25 24
––––––––
23 22 21 20 19 18 17 16
HOUREN AMPM HOUR
15 14 13 12 11 10 9 8
MINEN MIN
76543210
SECEN SEC
311
SAM4S Series [DATASHEET]
Atmel-11100K-ATARM-SAM4S-Datasheet_09-Jun-15
16.6.6 RTC Calendar Alarm Register
Name: RTC_CALALR
Address: 0x400E1474
Access: Read/Write
This register can on ly be writte n if the W PEN bit is clea re d in the Syst em Con trolle r Writ e Pro te ctio n M od e Register
(SYSC_WPMR).
Note: To change one of the DATE, MONTH fields, it is recommended to disable the field before changing the value and then re-enab le
it after the change has been made. This requires up to three accesses to the RTC_CALALR. The first access clears the enable
corresponding to the field to change (DATEEN, MTHEN). If the field is already cleared, this access is not req uired. The second
access performs the change of the value (DATE, MONTH). The third access is required to re-enable the field by writing 1 in
DATEEN, MTHEN fields.
• MONTH: Month Alarm
This field is the alarm field corresponding to the BCD-coded month counter.
• MTHEN: Month Alarm Enable
0: The month-matching alarm is disabled.
1: The month-matching alarm is enabled.
•DATE: Date Alarm
This field is the alarm field corresponding to the BCD-coded date counter.
• DATEEN: Date Alarm Enable
0: The date-matching alarm is disabled.
1: The date-matching alarm is enabled.
31 30 29 28 27 26 25 24
DATEEN – DATE
23 22 21 20 19 18 17 16
MTHEN – – MONTH
15 14 13 12 11 10 9 8
––––––––
76543210
––––––––
SAM4S Series [DATASHEET]
Atmel-11100K-ATARM-SAM4S-Datasheet_09-Jun-15
312
16.6.7 RTC Status Register
Name: RTC_SR
Address: 0x400E1478
Access: Read-only
• ACKUPD: Acknowledge for Update
• ALARM: Alarm Flag
• SEC: Second Event
• TIMEV: Time Event
Note: The time event is selected in the TIMEVSEL field in the Control Register (RTC_CR) and can be any one of the following events:
minute change, hour change, noon, midnight (day change).
• CALEV: Calendar Event
Note: T he calendar event is selected in the CALEVSEL field in the Control Register (RTC_CR) and can be any one of the following
events: week change, month change and year change.
31 30 29 28 27 26 25 24
––––––––
23 22 21 20 19 18 17 16
––––––––
15 14 13 12 11 10 9 8
––––––––
76543210
– – TDERR CALEV TIMEV SEC ALARM ACKUPD
Value Name Description
0 FREERUN Time and calendar registers cannot be updated.
1 UPDATE Time and calendar registers can be updated.
Value Name Description
0 NO_ALARMEVENT No alarm matching condition occ urred.
1 ALARMEVENT An alarm matching condition has occurred.
Value Name Description
0 NO_SECEVENT No second event has occurred since the last clear.
1 SECEVENT At least one second event has occurred since the last clear.
Value Name Description
0 NO_TIMEVENT No time event has occurred since the last clear.
1 TIMEVENT At least one time event has occurred since the last clear.
Value Name Description
0 NO_CALEVENT No calendar event has occurred since the last clear.
1 CALEVENT At least one calendar event has occurred since the last clear.
313
SAM4S Series [DATASHEET]
Atmel-11100K-ATARM-SAM4S-Datasheet_09-Jun-15
• TDERR: Time and/or Date Free Running Error
Value Name Description
0 CORRECT The internal free running counters are carrying valid values since the last read of the Status
Register (RTC_SR).
1 ERR_TIMEDATE The internal free running counters have been corru pted (invalid date or time, non-BCD
values) since the last read and/or they are still invalid.
SAM4S Series [DATASHEET]
Atmel-11100K-ATARM-SAM4S-Datasheet_09-Jun-15
314
16.6.8 RTC Status Clear Command Register
Name: RTC_SCCR
Address: 0x400E147C
Access: Write-only
• ACKCLR: Acknowledge Clear
0: No effect.
1: Clears corresponding status flag in the Status Register (RTC_SR).
• ALRCLR: Alarm Clear
0: No effect.
1: Clears corresponding status flag in the Status Register (RTC_SR).
• SECCLR: Second Clear
0: No effect.
1: Clears corresponding status flag in the Status Register (RTC_SR).
• TIMCLR: Time Clear
0: No effect.
1: Clears corresponding status flag in the Status Register (RTC_SR).
• CALCLR: Calendar Clear
0: No effect.
1: Clears corresponding status flag in the Status Register (RTC_SR).
• TDERRCLR: Time and/or Date Free Running Error Clear
0: No effect.
1: Clears corresponding status flag in the Status Register (RTC_SR).
31 30 29 28 27 26 25 24
––––––––
23 22 21 20 19 18 17 16
––––––––
15 14 13 12 11 10 9 8
––––––––
76543210
– – TDERRCLR CALCLR TIMCLR SECCLR ALRCLR ACKCLR
315
SAM4S Series [DATASHEET]
Atmel-11100K-ATARM-SAM4S-Datasheet_09-Jun-15
16.6.9 RTC Interrupt Enable Register
Name: RTC_IER
Address: 0x400E1480
Access: Write-only
• ACKEN: Acknowledge Update Interrupt Enable
0: No effect.
1: The acknowledge for update interrupt is enabled.
• ALREN: Alarm Interrupt Enable
0: No effect.
1: The alarm interrupt is enabled.
• SECEN: Second Event Interrupt Enable
0: No effect.
1: The second periodic interrupt is enabled.
• TIMEN: Time Event Interrupt Enable
0: No effect.
1: The selected time event interrupt is enabled.
• CALEN: Calendar Event Interrupt Enable
0: No effect.
1: The selected calendar event interrupt is enabled.
• TDERREN: Time and/or Date Error Interrupt Enable
0: No effect.
1: The time and date error interrupt is enabled.
31 30 29 28 27 26 25 24
––––––––
23 22 21 20 19 18 17 16
––––––––
15 14 13 12 11 10 9 8
––––––––
76543210
– – TDERREN CALEN TIMEN SECEN ALREN ACKEN
SAM4S Series [DATASHEET]
Atmel-11100K-ATARM-SAM4S-Datasheet_09-Jun-15
316
16.6.10 RTC Interrupt Disable Register
Name: RTC_IDR
Address: 0x400E1484
Access: Write-only
• ACKDIS: Acknowledge Update Interrupt Disable
0: No effect.
1: The acknowledge for update interrupt is disabled.
• ALRDIS: Alarm Interrupt Disable
0: No effect.
1: The alarm interrupt is disabled.
• SECDIS: Second Event Interrupt Disable
0: No effect.
1: The second periodic interrupt is disabled.
• TIMDIS: Time Event Interrupt Disable
0: No effect.
1: The selected time event interrupt is disabled.
• CALDIS: Calendar Event Interrupt Disable
0: No effect.
1: The selected calendar event interrupt is disabled.
• TDERRDIS: Time and/or Date Error Interrupt Disable
0: No effect.
1: The time and date error interrupt is disabled.
31 30 29 28 27 26 25 24
––––––––
23 22 21 20 19 18 17 16
––––––––
15 14 13 12 11 10 9 8
––––––––
76543210
– – TDERRDIS CALDIS TIMDIS SECDIS ALRDIS ACKDIS
317
SAM4S Series [DATASHEET]
Atmel-11100K-ATARM-SAM4S-Datasheet_09-Jun-15
16.6.11 RTC Interrupt Mask Register
Name: RTC_IMR
Address: 0x400E1488
Access: Read-only
• ACK: Acknowledge Update Interrupt Mask
0: The acknowledge for update interrupt is disabled.
1: The acknowledge for update interrupt is enabled.
• ALR: Alarm Interrupt Mask
0: The alarm interrupt is disabled.
1: The alarm interrupt is enabled.
• SEC: Second Event Interrupt Mask
0: The second periodic interrupt is disabled.
1: The second periodic interrupt is enabled.
• TIM: Time Event Interrupt Mask
0: The selected time event interrupt is disabled.
1: The selected time event interrupt is enabled.
• CAL: Calendar Event Interrupt Mask
0: The selected calendar event interrupt is disabled.
1: The selected calendar event interrupt is enabled.
• TDERR: Time and/or Date Error Mask
0: The time and/or date error event is disabled.
1: The time and/or date error event is enabled.
31 30 29 28 27 26 25 24
––––––––
23 22 21 20 19 18 17 16
––––––––
15 14 13 12 11 10 9 8
––––––––
76543210
– – TDERR CAL TIM SEC ALR ACK
SAM4S Series [DATASHEET]
Atmel-11100K-ATARM-SAM4S-Datasheet_09-Jun-15
318
16.6.12 RTC Valid Entry Register
Name: RTC_VER
Address: 0x400E148C
Access: Read-only
• NVTIM: Non-valid Time
0: No invalid data has been detected in RTC_TIMR (Time Register).
1: RTC_TIMR has contained invalid data since it was last programmed.
• NVCAL: Non-valid Calendar
0: No invalid data has been detected in RTC_CALR (Calendar Register) .
1: RTC_CALR has contained invalid data since it was last programmed.
• NVTIMALR: Non-valid Time Alarm
0: No invalid data has been detected in RTC_TIMALR (Time Alarm Register).
1: RTC_TIMALR has contained invalid data since it was last programmed.
• NVCALALR: Non-valid Calendar Alarm
0: No invalid data has been detected in RTC_CALALR (Calendar Alarm Register).
1: RTC_CALALR has contained invalid data since it was last programmed.
31 30 29 28 27 26 25 24
––––––––
23 22 21 20 19 18 17 16
––––––––
15 14 13 12 11 10 9 8
––––––––
76543210
––––NVCALALRNVTIMALRNVCALNVTIM
319
SAM4S Series [DATASHEET]
Atmel-11100K-ATARM-SAM4S-Datasheet_09-Jun-15
17. Watchdog Timer (WDT)
17.1 Description
The Watchdog Timer (WDT) is used to prevent system lock-up if the software becomes trapp ed in a deadlock. It
features a 12-bit down counter that allows a watchdog period of up to 16 second s (slow clock around 32 kHz). It
can generate a general reset or a processor reset only. In addition, it can be stopped while the processor is in
debug mode or idle mode.
17.2 Embedded Characteristics
12-bit Key-protected Programmable Counter
Watchdog Clock is Independent from Processor Clock
Provides Reset or Interrupt Signals to the System
Counter May Be Stopped while the Processor is in Debug State or in Id le Mode
SAM4S Series [DATASHEET]
Atmel-11100K-ATARM-SAM4S-Datasheet_09-Jun-15
320
17.3 Block Diagram
Figure 17-1. Watchdog Timer Block Diagram
= 0
10
set
reset
read WDT_SR
or
reset
wdt_fault
(to Reset Controller)
set
reset
WDFIEN
wdt_int
WDT_MR
SLCK
1/128
12-bit Down
Counter
Current
Value
WDD
WDT_MR
<= WDD
WDV
WDRSTT
WDT_MR
WDT_CR
reload
WDUNF
WDERR
reload
write WDT_MR
WDT_MR
WDRSTEN
321
SAM4S Series [DATASHEET]
Atmel-11100K-ATARM-SAM4S-Datasheet_09-Jun-15
17.4 Functional Description
The Watchdog Timer is used to prevent system lock-up if the software becomes trapped in a deadlock. It is
supplied with VDDCORE. It restarts with initial values on processor reset.
The watchdog is built around a 12-bit down counter, which is loaded with the value defined in the field WDV of the
Mode Register (WDT_MR). The Watchdog Tim er uses the slow clock divided by 128 to establish the maximum
watchdog period to be 16 seconds (with a typical slow clock of 32.768 kHz).
After a processor reset, the value of WDV is 0xFFF, corresponding to the maximum value of the counter with the
external reset generation enable d (field WDRSTEN at 1 after a ba ckup re se t) . This means that a d efault watchdo g
is running at reset, i.e., at power-up. The user can either disable the WDT by setting bit WDT_MR.WDDIS or
reprogram the WDT to meet the maximum watchdog period the application requires.
If the watchdog is restarted by writing into the Control Register (WDT_CR), WDT_MR must not be programmed
during a period of time of three slow clock periods following the WDT_CR write access. In any case, programming
a new value in WDT_MR automatically initiates a restart instruction.
WDT_MR can be written only once. Only a processor reset resets it. Writing WDT_MR reloads the timer with the
newly programmed mode parameters.
In normal operation, the user reloads the watchdog at regular intervals before the timer underflow occurs, by
setting bit WDT_CR.WDRSTT. The watchdog counter is then immediately reloaded from WDT_MR and restarted,
and the slow clock 128 divider is reset and restarted. WDT_CR is write-protected. As a result, writing WDT_CR
without the correct hard-coded key has no effect. If an underflow does occur, the “wdt_fault” signal to the Reset
Controller is asserted if bit WDT_MR.WDRSTEN is set. Moreover, the bit WDUNF is set in the Status Register
(WDT_SR).
To prevent a software deadlock that continuously triggers the watchdog, the reload of the watchdog must occur
while the watchdog counter is within a window between 0 and WDD, WDD is defined in WDT_MR.
Any attempt to restart the watchdog while the watchdog counter is between WDV and WDD results in a watchdog
error, even if the watchdog is disabled. The bit WDT_SR.WDERR is updated and the “wdt_fault” signal to the
Reset Controller is asserted.
Note that this feature can be disabled by progr amming a WDD value greater than or equal to the WDV value. In
such a configuration, restarting the Watchdog Timer is permitted in the whole range [0; WDV] and does not
generate an error. This is the default configuration on reset (the WDD and WDV va lues are equal).
The status bits WDUNF (Watch dog Unde rflow) and WDERR ( Watch dog Erro r) trigger an inter rupt, provide d the bit
WDT_MR.WDFIEN is set. The signal “wdt_fault” to the Reset Controller causes a watchdog reset if the
WDRSTEN bit is set as already explained in the Reset Controller documentation. In this case, the processor and
the Watchdog Timer are reset, and the WDERR and WDUNF flags are reset.
If a reset is generated or if WDT_SR is read, the status bits are reset, the interrupt is cleared, and the “wdt_fault”
signal to the reset controller is deasserted.
Writing WDT_MR reload s an d re sta r ts the dow n co un ter.
While the processor is in debug state or in idle mode, the counter may be stopped depending on the value
programmed for the bits WDIDLEHLT and WDDBGHLT in WDT_MR.
SAM4S Series [DATASHEET]
Atmel-11100K-ATARM-SAM4S-Datasheet_09-Jun-15
322
Figure 17-2 . Watchdog Behavior
0
WDV
WDD
WDT_CR.WDRSTT=1
Watchdog
Fault
Normal behavior
Watchdog Error Watchdog Underflow
FFF
if WDRSTEN is 1
if WDRSTEN is 0
Forbidden
Window
Permitted
Window
323
SAM4S Series [DATASHEET]
Atmel-11100K-ATARM-SAM4S-Datasheet_09-Jun-15
17.5 Watchdog Timer (WDT) User Interface
Table 17-1 . Register Mapping
Offset Register Name Access Reset
0x00 Con trol Register WDT_CR Write-only –
0x04 Mode Register WDT_MR Read/Write Once 0x3FFF_2FFF
0x08 Status Reg ister WDT_SR Read-only 0x0000_0000
SAM4S Series [DATASHEET]
Atmel-11100K-ATARM-SAM4S-Datasheet_09-Jun-15
324
17.5.1 Watchdog Timer Control Register
Name: WDT_CR
Address: 0x400E1450
Access: Write-only
• WDRSTT: Watchdog Restart
0: No effect.
1: Restarts the watchdog if KEY is written to 0xA5.
• KEY: Password
31 30 29 28 27 26 25 24
KEY
23 22 21 20 19 18 17 16
––––––––
15 14 13 12 11 10 9 8
––––––––
76543210
–––––––WDRSTT
Value Name Description
0xA5 PASSWD Writing any other value in this field ab orts the write operation.
325
SAM4S Series [DATASHEET]
Atmel-11100K-ATARM-SAM4S-Datasheet_09-Jun-15
17.5.2 Watchdog Timer Mode Register
Name: WDT_MR
Address: 0x400E1454
Access: Read/Write Once
Note: The first write access prevents any further modification of the value of this register. Read accesses remain possible.
Note: The WDD and WDV values must not be modified within three slow clock periods following a restart of the watchdog performed by
a write access in WDT_CR. Any modification will cause the watchdog to trigger an end of period earlier than expected.
• WDV: Watchdog Counter Value
Defines the value loaded in the 12-bit watchdog counter.
• WDFIEN: Watchdog Fault Interrupt Enable
0: A watchdog fault (underflow or error) has no effect on interrupt.
1: A watchdog fault (underflow or error) asserts interrupt.
• WDRSTEN: Watchdog Reset Enable
0: A watchdog fault (underflow or error) has no effect on the resets.
1: A watchdog fault (underflow or error) triggers a watchdog reset.
• WDRPROC: Watchdog Reset Processor
0: If WDRSTEN is 1, a watchdog fault (underflow or error) activates all resets.
1: If WDRSTEN is 1, a watchdog fault (underflow or error) activates the processor reset.
• WDDIS: Watchdog Disable
0: Enables the Watchdog Timer.
1: Disables the Watchdog Timer.
• WDD: Watchdog Delta Value
Defines the permitted range for reloading the Watchdog Timer.
If the Watchdog Timer value is less than or equal to WDD, setting bit WDT_CR.WDRSTT restarts the timer.
If the Watchdog Timer value is greater than WDD, setting bit WDT_CR.WDRSTT causes a watchdog error.
31 30 29 28 27 26 25 24
– – WDIDLEHLT WDDBGHLT WDD
23 22 21 20 19 18 17 16
WDD
15 14 13 12 11 10 9 8
WDDIS WDRPROC WDRSTEN WDFIEN WDV
76543210
WDV
SAM4S Series [DATASHEET]
Atmel-11100K-ATARM-SAM4S-Datasheet_09-Jun-15
326
• WDDBGHLT: Watchdog Debug Halt
0: The watchdog runs when the processor is in debug state.
1: The watchdog stops when the processor is in debug state.
• WDIDLEHLT: Watchdog Idle Halt
0: The watchdog runs when the system is in idle mode.
1: The watchdog stops when the system is in idle state.
327
SAM4S Series [DATASHEET]
Atmel-11100K-ATARM-SAM4S-Datasheet_09-Jun-15
17.5.3 Watchdog Timer Status Register
Name: WDT_SR
Address: 0x400E1458
Access Read-only
• WDUNF: Watchdog Underflow (cleared on read)
0: No watchdog underflow occurred sin c e th e las t read of WD T_ SR.
1: At least one watchdog underflow occurred since the last read of WDT_SR.
• WDERR: Watchdog Error (cleared on read)
0: No watchdog error occurred since the last rea d of WDT_SR.
1: At least one watchdog error occurred since the last read of WDT_SR.
31 30 29 28 27 26 25 24
––––––––
23 22 21 20 19 18 17 16
––––––––
15 14 13 12 11 10 9 8
––––––––
76543210
––––––WDERRWDUNF
SAM4S Series [DATASHEET]
Atmel-11100K-ATARM-SAM4S-Datasheet_09-Jun-15
328
18. Supply Controller (SUPC)
18.1 Description
The Supply Controller (SUPC) controls the supply voltages of the system and manages the Backup mode. In this
mode, current consumption is reduce d to a few microam ps for backup power retention. Exit from this mode is
possible on multiple wake-up sources. The SUPC also generates the slow clock by selecting either the low-power
RC oscillator or the low-power crystal oscillator.
18.2 Embedded Characteristics
Manages the Core Power Supply VDDCORE and Backup Mode by Controlling the Embedded Voltage
Regulator
A Supply Monitor Detection on VDDIO or a Brownout Detection on VDDCORE Triggers a Core Reset
Generates the Slow Clock SLCK by Selecting Either the 22-42 kHz Low-Power RC Oscillator or the 32 kHz
Low-Power Crystal Oscillator
Low-power Tamper Detection on Two Inputs
Anti-tampering by Immediate Clear of the General-purpose Backup Registers
Supports Multiple Wake-up Sources for Exit from Backup Mode
16 Wake-up Input s with Programmable Debouncing
Real-Time Cloc k Alarm
Real-Time Timer Alarm
Supply Monitor Detection on VDDIO, with Programmable Scan Period and Voltage Threshold
329
SAM4S Series [DATASHEET]
Atmel-11100K-ATARM-SAM4S-Datasheet_09-Jun-15
18.3 Block Diagram
Figure 18-1. Supply Controller Block Diagram
NRST
VDDOUT
VDDIN
on/off
Reset
Controller
vddcore_nreset
supc_irq
Power-On Reset
VDDCORE
Brown-Out
Detector
VDDCORE
por_core_out
bod_out
sm_out
por_io_out
Real-Time
Clock
WKUP0-WKUP15
Voltage Regulator
Controller
Real-Time
Timer
rtc_alarm
VROFF
Supply
Monitor
Controller
BODDIS
SMSMPL SMTH
OSCBYPASS
SMRSTEN
BODRSTEN
XTALSEL
Slow
Clock
Controller
SMIEN
Supply Controller
SMEN
Wake-Up
Controller
RTCEN
rtt_alarm
RTTEN
RTCOUT0
RTCOUT1
sm_out
LPDBCEN0
LPDBCEN1
LPDBCCLR
WKUPEN0..15
WKUPT0..15
WKUPDBC
LPDBC
General-Purpose
Backup Registers
clear
wake_up
SLCK
XIN32
XOUT32
Programmable
Supply Monitor
VDDIO
Zero-Power
Power-On Reset
VDDIO
XTAL OSC 32kHz
RC OSC 32kHz
Core Voltage
Regulator
Interrupt
Controller
ONREG
proc_nreset
periph_nreset
ice_nreset
Backup Area
SLCK
SAM4S Series [DATASHEET]
Atmel-11100K-ATARM-SAM4S-Datasheet_09-Jun-15
330
18.4 Functional Description
18.4.1 Overview
The device is divided into two power supply areas:
VDDIO power supply: includes the Supply Controller, part of the Reset Controller, the slow clock switch, the
general-purpose backu p regi sters, th e supply monitor and the clock which include s the Rea l-time Timer and
the Real-time Clock.
Core power supply: includes part of the Reset Controller, the Brownout Detector, the processor, the SRAM
memory, the Flash memory and the peripherals.
The Supply Controller (SUPC) controls the supply voltage of the core power supply. The SUPC intervenes when
the VDDIO power supply rises (when the system is starting) or when Backup mode is entered.
The SUPC also integrates the slow clock generator, which is based on a 32 kHz crystal oscillator, and an
embedded 32 kHz RC oscillator. The slow clock defaults to the RC oscillator, but the software can enable the
crystal oscillator and select it as the slow clock source.
The SUPC and the VDDIO power supply have a reset circuitry based on a zero-power power-on reset cell. The
zero-power power-on reset allows the SUPC to start correctly as soon as the VDDIO voltage becomes valid.
At start-up of the system, once the backup voltage VDDIO is valid and the embedded 32 kHz RC oscillator is
stabilized, the SUPC starts up the core by sequentially enabling the internal voltage regulator. The SUPC waits
until the core voltage VDDCORE is valid, then releases the reset signal of the core vddcore_nreset signal.
Once the system has started, the user can program a supply monitor and/or a brownout detector. If the supply
monitor detects a voltage level on VDDIO that is too low, the SUPC asserts the reset signal of the core
vddcore_nreset signal until VDDIO is valid. Likewise, if the brownout detector detects a core voltage level
VDDCORE that is too low, the SUPC asserts the reset signal vddcore_nreset until VDDCORE is valid.
When Backup mode is entered, the SUPC sequentially asserts the reset signal of the core power supply
vddcore_nreset and disables the voltage regulator, in order to supply only the VDDIO power supply. Current
consumption is reduced to a few microamps for the backup part retention. Exit from this mode is possible on
multiple wake-up sources including an event on WKUP pins, or a clock alarm. To exit this mode, the SUPC
operates in the same way as system start-up.
331
SAM4S Series [DATASHEET]
Atmel-11100K-ATARM-SAM4S-Datasheet_09-Jun-15
18.4.2 Slow Clock Generator
The SUPC embeds a slow clock generator that is supplie d with the VDDIO power supp ly. As soon as the VDDIO is
supplied, both the crystal oscillator and the embedded RC oscillator are powered up, but only the embedded RC
oscillator is enabled. When the RC oscillator is selected as the slow clock source, the slow clock stabilizes more
quickly than when the crystal oscillator is selected.
The user can select the crystal oscillator to be the source of the slow clock, as it provide s a more accurate
frequency than the RC oscillator. The crystal oscillator is selected by setting the XTALSEL bit in the SUPC Control
register (SUPC_CR). The following sequence must be used to switch from the RC oscillator to the crystal
oscillator:
1. The PIO lines multiplexed with XIN32 and XOUT32 are configured to be driven b y the oscillator.
2. The crystal oscillator is enabled.
3. A number of slow RC oscillator clock periods is counted to cover the start-up time of the crystal oscillator
(refer to the Electrical Characteristics for information on 32 kHz crystal oscillator start-up time).
4. The slow clock is switched to the output of the crystal oscillator.
5. The RC oscillator is disabled to save power.
The switching time may vary de pending on the slow RC oscillator clock frequ ency range. The switch of the slow
clock source is glitch-free. The OSCSEL bit of the SUPC Status register (SUPC_SR) indicates when the switch
sequence is finished.
Reverting to the RC oscillator as a slow clock source is only possible by shutting down the VDDIO power supply.
If the user does not need the crystal oscillator, the XIN32 and XOUT32 pins should be left unconnected.
The user can also set the crystal oscillator in Bypass mode instead of connecting a crystal. In this case, the user
has to provide the external clock signal on XIN32. The input characteristics of the XIN32 pin are given in the
section ‘Electrical Characteristics. To enter Bypass mode, the OS CBYPASS bit in the Mode register (SUPC_MR)
must be set before setting XTALSEL.
18.4.3 Core Voltage Regulator Control/Backup Low-power Mode
The SUPC can be used to control the embedded voltage regulator.
The voltage regulator automatically adapts its quiescent current depending on the required load current. More
information can be found in the Electrical Characteristics.
The user can switch off the voltage regulator, and thus put the device in Backup mode, by writing a 1 to the
VROFF bit in SUPC_CR.
This asserts the vddcore_nreset signal after the write resynchronization time, which lasts two slow clock cycles
(worst case). Once the vddcore_n reset signal is assert ed, the processor and the perip herals are stop ped one slow
clock cycle before the core power supply shuts off.
When the internal voltage regulator is not used and VDDCORE is supplied by an external supply, the voltage
regulator can be disabled by writing a 1 to the ONREG bit in SUPC_MR.
18.4.4 Supply Monitor
The SUPC embeds a supply monitor located in the VDDIO power supply and which monitors VDDIO power
supply.
The supply monitor can be used to prevent the processor from falling into an unpredictable state if the main power
supply drops below a certain level.
The threshold of the supply monitor is programmable in the SMTH field of the Supply Monitor Mode register
(SUPC_SMMR). Refer to the VDDIO Supply Monitor characteristics in the section Electrical Characteristics.
SAM4S Series [DATASHEET]
Atmel-11100K-ATARM-SAM4S-Datasheet_09-Jun-15
332
The supply monitor can also be enabled during one slow clock period on every one of either 32, 256 or 2048 slow
clock periods, depending on the user selection. This is configured in the SMSMPL field in SUPC_SMMR.
Enabling the supply monitor for such reduced times divides the typical supply monitor power consumption by
factors of 2, 16 and 128, respectively, if continuous monitoring of the VDDIO power supply is not required.
A supply monitor detection generates either a reset of the core power supply or a wake-up of the core power
supply. Generating a core re se t whe n a sup ply moni to r de tection occur s is enable d by setting the SMRSTEN bit in
SUPC_SMMR.
Waking up the core po wer su pply whe n a supply mo nitor dete ction occurs can be enable d by setting the SMEN bit
in the Wake-up Mode register (SUPC_WUMR).
The SUPC provides two status bits in the SUPC_SR for the supply monitor that determine whether the last wake-
up was due to the supply monitor:
The SMOS bit provides real-time information, updated at each measurement cycle or updated at each slow
clock cycle, if the measurement is continuous.
The SMS bit provides saved information and shows a supply monitor detection has occurre d since the last
read of SUPC_SR.
The SMS flag gener at es an inte rr up t if the SMIEN bit is set in SUPC_SMMR.
Figure 18-2. Supply Monitor Status Bit and Associated Interrupt
18.4.5 Backup Power Supply Reset
18.4.5.1 Raising the Backup Power Supply
When the backup voltage VDDIO rises, the RC oscillator is powered up and the zero-power power-on reset cell
maintains its output low as long as VDDIO has not reached its target voltage. During this period, the SUPC is
reset. When the VDDIO voltage becomes valid and the zero-power power-on reset signal is released, a counter is
started for five slow clock cycles. This is the time required for the 32 kHz RC oscillator to stabilize.
After this time, the voltage regulator is enabled. The core power supply rises and the brownout detector provides
the bodcore_in signal as soo n as the core vo ltage VDDCORE is valid. This results in releasing the vdd core_nr eset
signal to the Reset Controller after the bodcore_in signal has been confirmed as being valid for at least one slow
clock cycle.
Supply Monitor ON
3.3 V
0 V
Threshold
SMS and SUPC interrupt
Read SUPC_SR
Periodic Sampling
Continuous Sampling (SMSMPL = 1)
333
SAM4S Series [DATASHEET]
Atmel-11100K-ATARM-SAM4S-Datasheet_09-Jun-15
Figure 18-3. Raising the VDDIO Power Supply
18.4.6 Core Reset
The Supply Controller manages the vddcore_nreset signal to the Reset Controller, as described in Section 18.4.5
”Backup Power Supply Reset”. The vddcore_nr eset signal is normally asserted before shutting down the core
power supply and released as soon as the core power supply is correctly regulated.
There are two additional sources which can be programmed to activate vddcore_nreset:
a supply monitor detection
a brownout detection
18.4.6.1 Supply Monitor Reset
The supply monitor is capable of generating a reset of the system. This is enabled by setting the SMRSTEN bit in
SUPC_SMMR.
If SMRSTEN is set and if a supply monitor detection occurs, the vddcor e_nrese t signal is immediately activated for
a minimum of one slow clock cycle.
18.4.6.2 Brownout Detector Reset
The brownout detector provides the bodcore_in signal to the SUPC. This signal indicates that the voltage
regulation is operating as programmed. If this signal is lost for longer than 1 slow clock period while the voltage
regulator is enabled, the SUPC asserts vddcore_nreset if BODRSTEN is written to 1 in SUPC_MR.
Zero-Power Power-On
Reset Cell output
22 - 42 kHz RC
Oscillator output
Fast RC
Oscillator output
Backup Power Supply
vr_on
bodcore_in
vddcore_nreset
NRST
(no ext. drive assumed)
proc_nreset
Note: After “proc_nreset” rising, the core starts fetching instructions from Flash at 4 MHz.
periph_nreset
7 x Slow Clock Cycles 3 x Slow Clock
Cycles
2 x Slow Clock
Cycles
6.5 x Slow Clock
Cycles
TON Voltage
Regulator
Zero-Power POR
Core Power Supply
RSTC.ERSTL
(5 for startup slow RC + 2 for synchro.)
default = 2
SAM4S Series [DATASHEET]
Atmel-11100K-ATARM-SAM4S-Datasheet_09-Jun-15
334
If BODRSTEN is set and the voltage regulati on is lost (ou tp ut voltage of the re gulat or too low), the vdd core_nr eset
signal is asserted for a minimum of one slow clock cycle and then released if bodcore_in has been reactivated.
The BODRSTS bit in SUPC_SR indicates the source of the last reset.
Until bodcore_in is deactivated, the vddcore_nreset signal remains active.
18.4.7 Wake-up Sources
The wake-up events allow the device to exit Backup mode. When a wake-up event is detected, the SUPC
performs a sequence that automatically reenables the core power supply.
Figure 18-4. Wake-up Sources
18.4.7.1 Wake-up Inputs
The wake-up inputs, WKUPx, can be programmed to perform a wake-up of the core power supply. Each input can
be enabled by writing a 1 to the corresponding bit, WKUPENx, in the Wake-up Inputs register (SUPC_WUIR). The
wake-up level can be selected with the corresponding polarity bit, WKUPTx, also located in SUPC_WUIR.
The resulting signals are wired-ORed to trigger a debounce counter, which is programmed with the WKUPDBC
field in SUPC_WUMR. The WKUPDBC field se lects a d ebo un cing p er iod of 3 , 32, 5 12 , 4,096 o r 32,76 8 slow clock
cycles. The du ration of th ese per iods corr espond s, resp ectively, to about 100 µs, about 1 ms, about 16 ms, about
128 ms and about 1 second (for a typical slow clock fr equency of 32 kHz). Progr amming WKUPDBC to 0x0 selects
an immediate wake-up, i.e., an enabled WKUP pin must be active according to its polarity during a minimum of
one slow clock period to wake up the core power supply.
WKUP15
WKUPEN15
WKUPT15
WKUPEN1
WKUPEN0
Debouncer
SLCK
WKUPDBC
WKUPS
RTCEN
rtc_alarm
SMEN
sm_out
Core
Supply
Restart
WKUPIS0
WKUPIS1
WKUPIS15
WKUPT0
WKUPT1
WKUP0
WKUP1
RTTEN
rtt_alarm
Debouncer
RTCOUT0
LPDBC
Debouncer
LPDBC
RTCOUT0
LPDBCS0
LPDBCS1
LPDBCEN1
WKUPT1
LPDBCEN0
WKUPT0
Falling/Rising
Edge Detect
Low-power
Tamper Detection
Logic
GPBR Clear
LPDBCCLR
LPDBCS1
LPDBCS0
Falling/Rising
Edge Detect
Falling/Rising
Edge Detect
Falling/Rising
Edge Detect
Falling/Rising
Edge Detect
335
SAM4S Series [DATASHEET]
Atmel-11100K-ATARM-SAM4S-Datasheet_09-Jun-15
If an enabled WKUP pin is asser ted for a duration longer tha n the debou ncing per iod, a wake- up of the core powe r
supply is started and the signals, WKUP0 to WKUPx as shown in Figure 18-4 "Wake-up Sources", are latched in
SUPC_SR. This allows the user to identify the source of the wake-up. However, if a new wake-up condition
occurs, the primary information is lost. No new wake-up can be detected since the primary wake-up condition has
disappeared.
Before instructing the system to enter Backup mode, if the field WKUPDBC > 0, it must be checked that none of
the WKUPx pins that are enabled for a wake-up (exit from Backup mode) holds an active polarity. This is checked
by reading the pin status in the PIO Controller. If WKUPENx=1 and the pin WKUPx holds an active polarity, the
system must not be instructed to enter Backup mode.
Figure 18-5. Entering and Exiting Backup Mode with a WKUP Pin
18.4.7.2 Low-power Tamper Detection and Anti-Tampering
Low-power debouncer inputs (WKUP0, WKUP1) can be used for tamper detection. If the tamp er sens or is bias ed
through a resistor and consta ntly driven by the power supply, this leads to power consumption as long as the
tamper detection switch is in its active state. To prevent power consumption when the switch is in active state, the
tamper sensor circuitry must be intermittently powered, and thus a specific waveform must be applied to the
sensor circuitry.
The waveform is generated using RTCOUTx in all modes including Backup mode. Refer to the RTC section for
waveform ge ne ra tio n .
Separate debouncers are embedded, one for WKUP0 input, one for WKUP1 input.
The WKUP0 and/or WKUP1 inputs perform a system wake-up upon tamper detection. This is enabled by setting
the LPDBCEN0/1 bit in the SUPC_WUMR.
WKUP0 and/or WKUP1 inputs can also be used when VDDCORE is powered to detect a tamper.
When the bit LPDBCENx is written to 1, WKUPx pins must no t be config ured to act a s a de bouncing sour ce fo r the
WKUPDBC counter (WKUPENx must be cleared in SUPC_WUIR).
Low-power tamper detection or debounce requires RTC output (RTCOUTx) to be configured to generate a duty
cycle programmable pulse (i.e., OUT0 = 0x7 in RTC_MR) in order to create the sampling points of both
debouncers. The sampling point is the falling edge of the RTCOUTx waveform.
Figure 18-6 shows an example of an application where two tamper switches are used. RT COUTx powers the
external pull-up used by the tamper sensor circuitry.
WKUPx
WKUPTx=0
Active BACKUP Active BACKUP Active BACKUP
System
Edge detect +
debounce time Edge detect +
debounce time
active runtime active runtime
VROFF=1
VROFF=1
check
WKUPx
status
check
WKUPx
status
WKUPDBC > 0
SAM4S Series [DATASHEET]
Atmel-11100K-ATARM-SAM4S-Datasheet_09-Jun-15
336
Figure 18-6. Low-power Debouncer (Push-to-Make Switch, Pull-up Resistors)
Figure 18-7. Low-power Debouncer (Push-to-Break Switch, Pull-down Resistors)
The debouncing period duration is configurable. The period is set for all de bouncers (i.e., the duration cannot be
adjusted for each debouncer). The number of successive identical samples to wake up the system can be
configured from 2 up to 8 in the LPDBC field of SUPC_WUMR. The period of time betwe en two samples can be
configured by programming the TPERIOD field in the RTC_MR. Power parameters can be adjusted by modifying
the period of time in the THIGH field in RTC_MR.
The wake-up polarity of the inputs can be independently configured by writing WKUPT0 and/ or WKUPT1 fields in
SUPC_WUMR.
In order to determine which wake-up/tamper pin triggers the system wake-up, a status flag is associated for each
low-power debouncer. These flags are read in SUPC_SR.
A debounce event (tamper detection) can pe rform an immediate clear (0 delay) on the first half the genera l-
purpose backup registers (GPBR). The LPDBCCLR bit must be set in SUPC_WUMR.
Note that it is not ma ndatory to use the RTCOUTx pi n when using the WKUP0/WKUP1 pins as tampering inputs in
any mode. Using the RTCOUTx pin provid es a “sampling mode” to further reduce the power consumption of the
MCU
WKUP0
WKUP1
RTCOUTx
Pull-up
Resistor
Pull-up
Resistor
GND
GND
GND
MCU
WKUP0
WKUP1
RTCOUTx
Pull-down
Resistors
GND GND
GND
337
SAM4S Series [DATASHEET]
Atmel-11100K-ATARM-SAM4S-Datasheet_09-Jun-15
tamper detection circuitry. If RTCOUTx is n ot used, the RTC must be configured to create an internal sampling
point for the debouncer logic. The period of time between two samples can be configured by programming the
TPERIOD field in RTC_MR.
Figure 18-8 illustrates the use of WKUPx without the RTCOUTx pin.
Figure 18-8. Using WKUP Pins Without RTCOUTx Pins
18.4.7.3 Clock Alarms
The RTC and the RTT alarms can generate a wake-up of the core power supply. This can be enabled by setting,
respectively, the bits RTCEN and RTTEN in SUPC_WUMR.
The Supply Controller does not provide any status as the information is available in the user interface of either the
Real-Time Timer or the Real-Time Clock.
18.4.7.4 Supply Monitor Detection
The supply monitor can generate a wake-up of the core power supply. See Section 18.4.4 ”Supply Monitor”.
MCU
WKUP0
WKUP1
VDDIO
Pull-up
Resistor
Pull-up
Resistor
GND
GND
GND
SAM4S Series [DATASHEET]
Atmel-11100K-ATARM-SAM4S-Datasheet_09-Jun-15
338
18.4.8 Register Write Protection
To prevent any single software error from corrupting SYSC behavior, certain registers in the address space can be
write-protected by setting the WPEN bit in the ”System Controller Write Protection Mode Register”
(SYSC_WPMR).
The following registers can be write-protected:
RSTC Mode Register
RTT Mode Register
RTT Alarm Register
RTC Control Register
RTC Mode Register
RTC Time Alarm Register
RTC Calendar Alarm Register
General Purpose Backup Registers
Supply Controller Control Register
Supply Controller Supply Monitor Mode Register
Supply Controller Mode Register
Supply Controller Wake-up Mode Register
Supply Controller Wake-up Inputs Register
18.4.9 Register Bits in Backup Domain (VDDIO)
The following configuration registers, or certain bits of the registe rs, are physically located in the p roduct backup
domain:
RSTC Mode Register (all bits)
RTT Mode Register (all bits)
RTT Alarm Register (all bits)
RTC Control Register (all bits)
RTC Mode Register (all bits)
RTC Time Alarm Register (all bits)
RTC Calendar Alarm Register (all bits)
General Purpose Backup Registers (all bits)
Supply Controller Control Register (see register description for details)
Supply Controller Supply Monitor Mode Register (all bits)
Supply Controller Mode Register (see register description for details)
Supply Controller Wake-up Mode Register (all bits)
Supply Controller Wake-up Inputs Register (all bits)
Supply Controller Status Register (all bits)
339
SAM4S Series [DATASHEET]
Atmel-11100K-ATARM-SAM4S-Datasheet_09-Jun-15
18.5 Supply Controller (SUPC) User Interface
The user interface of the Supply Controller is part of the System Controller user interface.
18.5.1 System Controller (SYSC) User Interface
18.5.2 Supply Controller (SUPC) User Interface
Table 18-1. System Controller Registers
Offset System Controlle r Periph eral Name
0x00-0x0c Reset Controller RSTC
0x10-0x2C Supply Controller SUPC
0x30-0x3C Real Time Timer RTT
0x50-0x5C Watchdog Timer WDT
0x60-0x8C Real Time Clock RTC
0x90-0xDC General Purpose Backup Registe r GPBR
0xE0 Reserved –
0xE4 Write Protection Mode Register SYSC_WPMR
0xE8-0xF8 Reserved –
Table 18-2 . Register Mapping
Offset Register Name Access Reset
0x00 Supply Controller Control Register SUPC_CR Write-only –
0x04 Supply Controller Supply Monitor Mode Register SUPC_SMMR Read/Write 0x0000_ 0000
0x08 Supply Controller Mode Register SUPC_MR Read/Write 0x0000_5A00
0x0C Supply Controller Wake-up Mode Register SUPC_WUMR Read/Write 0x0000_0000
0x10 Supply Controller Wake-up Inputs Register SUPC_WUIR Read/Write 0x0000_0000
0x14 Supply Controller S tatus Register SUPC_SR Read-only 0x0000_0000
0x18 Reserved – – –
SAM4S Series [DATASHEET]
Atmel-11100K-ATARM-SAM4S-Datasheet_09-Jun-15
340
18.5.3 Supply Controller Control Register
Name: SUPC_CR
Address: 0x400E1410
Access: Write-only
This register can on ly be writte n if the W PEN bit is clea re d in the Syst em Con trolle r Writ e Pro te ctio n M od e Register
(SYSC_MR).
• VROFF: Voltage Regulator Off
0 (NO_EFFECT): No effect.
1 (STOP_VREG): If KEY is correct, VROFF asserts the vddcore_nreset and stops the voltage regulator.
Note: This bit is located in the VDDIO domain.
• XTALSEL: Crystal Oscillator Select
0 (NO_EFFECT): No effect.
1 (CRYSTAL_SEL): If KEY is correct, XTALSEL switches the slow clock on the crystal oscillator output.
Note: This bit is located in the VDDIO domain.
• KEY: Password
31 30 29 28 27 26 25 24
KEY
23 22 21 20 19 18 17 16
––––––––
15 14 13 12 11 10 9 8
––––––––
76543210
––––XTALSELVROFF––
Value Name Description
0xA5 PASSW D Writing any other value in this field aborts the write operation.
341
SAM4S Series [DATASHEET]
Atmel-11100K-ATARM-SAM4S-Datasheet_09-Jun-15
18.5.4 Supply Controller Supply Monitor Mode Register
Name: SUPC_SMMR
Address: 0x400E1414
Access: Read/Write
This register is located in the VDDIO domain.
This register can on ly be writte n if the W PEN bit is clea re d in the Syst em Con trolle r Writ e Pro te ctio n M od e Register
(SYSC_MR).
• SMTH: Supply Monitor Threshold
Selects the threshold voltage of the supply monitor. Refer to the Electrical Characteristics for voltage values.
• SMSMPL: Supply Monitor Sampling Period
• SMRSTEN: Supply Monitor Reset Enable
0 (NOT_ENABLE): The core reset signal vddcore_nreset is not affected when a supply monitor detection occurs.
1 (ENABLE): The core reset signal, vddcore_nreset is asserted when a supply monitor detection occurs.
• SMIEN: Supply Monitor Interrupt Enable
0 (NOT_ENABLE): The SUPC interrupt signal is not affected when a supply monitor detection occurs.
1 (ENABLE): The SUPC interrupt signal is asserted when a supply monitor detection occurs.
31 30 29 28 27 26 25 24
––––––––
23 22 21 20 19 18 17 16
––––––––
15 14 13 12 11 10 9 8
– – SMIEN SMRSTEN – SMSMPL
76543210
–––– SMTH
Value Name Description
0x0 SMD Supply Monitor disabl ed
0x1 CSM Continuous Supply Monitor
0x2 32SLCK Supply Monitor enabled one SLCK period every 32 SLCK periods
0x3 256SLCK Supply Monitor enabled one SLCK period every 256 SLCK periods
0x4 2048SLCK Supply Monitor enabled one SLCK period every 2,048 SLCK periods
SAM4S Series [DATASHEET]
Atmel-11100K-ATARM-SAM4S-Datasheet_09-Jun-15
342
18.5.5 Supply Controller Mode Register
Name: SUPC_MR
Address: 0x400E1418
Access: Read/Write
This register can on ly be writte n if the W PEN bit is clea re d in the Syst em Con trolle r Writ e Pro te ctio n M od e Register
(SYSC_MR).
• BODRSTEN: Brownout Detector Reset Enable
0 (NOT_ENABLE): The core reset signal vddcore_nreset is not affected when a brownout detection occurs.
1 (ENABLE): The core reset signal, vddcore_nreset is asserted when a brownout detection occurs.
Note: This bit is located in the VDDIO domain.
• BODDIS: Brownout Detector Disable
0 (ENABLE): The core brownout detector is enabled.
1 (DISABLE): The core brownout detector is disabled.
Note: This bit is located in the VDDIO domain.
• ONREG: Voltage Regulator Enable
0 (ONREG_UNUSED): Internal voltage regulator is not used (external power supply is used).
1 (ONREG_USED): Internal voltage regulator is used.
Note: This bit is located in the VDDIO domain.
• OSCBYPASS: Oscillator Bypass
0 (NO_EFFECT): No effect. Clock selection depends on the value of XTALSEL (SUPC_CR).
1 (BYPASS): The 32 kHz crystal oscillator is bypassed if XTALSEL (SUPC_CR) is set. OSCBYPASS must be set prior to
setting XTALSEL.
Note: This bit is located in the VDDIO domain.
• KEY: Password Key
31 30 29 28 27 26 25 24
KEY
23 22 21 20 19 18 17 16
–––OSCBYPASS––––
15 14 13 12 11 10 9 8
–ONREGBODDISBODRSTEN––––
76543210
––––––––
Value Name Description
0xA5 PASSW D Writing any other value in this field aborts the write operation.
343
SAM4S Series [DATASHEET]
Atmel-11100K-ATARM-SAM4S-Datasheet_09-Jun-15
18.5.6 Supply Controller Wake-up Mode Register
Name: SUPC_WUMR
Address: 0x400E141C
Access: Read/Write
This register is located in the VDDIO domain.
This register can on ly be writte n if the W PEN bit is clea re d in the Syst em Con trolle r Writ e Pro te ctio n M od e Register
(SYSC_MR).
• SMEN: Supply Monitor Wake-up Enable
0 (NOT_ENABLE): The supply monitor detection has no wake-up effect.
1 (ENABLE): The supply monitor detection forces the wake-up of the core power supply.
• RTTEN: Real-time Timer Wake-up Enable
0 (NOT_ENABLE): The RTT alarm signal has no wake-up effect.
1 (ENABLE): The RTT alarm signal forces the wake-up of the core power supply.
• RTCEN: Real-time Clock Wake-up Enable
0 (NOT_ENABLE): The RTC alarm signal has no wake-up effect.
1 (ENABLE): The RTC alarm signal forces the wake-up of the core power supply.
• LPDBCEN0: Low-power Debouncer Enable WKUP0
0 (NOT_ENABLE): The WKUP0 input pin is not connected to the low-power debouncer.
1 (ENABLE): The WKUP0 input pin is connected to the low-power debouncer and forces a system wake-up.
• LPDBCEN1: Low-power Debouncer Enable WKUP1
0 (NOT_ENABLE): The WKUP1 input pin is not connected to the low-power debouncer.
1 (ENABLE): The WKUP1 input pin is connected to the low-power debouncer and forces a system wake-up.
• LPDBCCLR: Low-power Debouncer Clear
0 (NOT_ENABLE): A low-power debounce event does not create an immediate clear on the first half of GPBR registers.
1 (ENABLE): A low-power debounce event on WKUP0 or WKUP1 generates an immediate clear on the first half of GPBR
registers.
31 30 29 28 27 26 25 24
––––––––
23 22 21 20 19 18 17 16
––––– LPDBC
15 14 13 12 11 10 9 8
– WKUPDBC ––––
76543210
LPDBCCLR LPDBCEN1 LPDBCEN0 – RTCEN RTTEN SMEN –
SAM4S Series [DATASHEET]
Atmel-11100K-ATARM-SAM4S-Datasheet_09-Jun-15
344
• WKUPDBC: Wake-up Inputs Debouncer Period
• LPDBC: Low-power Debouncer Period
Value Name Description
0 IMMEDIATE Immediate, no debouncing, detected active at least on one Slow Clock edge.
1 3_SCLK WKUPx shall be in its active state for at least 3 SLCK periods
2 32_SCLK WKUPx shall be in its active state for at least 32 SLCK periods
3 512_SCLK WKUPx shall be in its active state for at least 512 SLCK periods
4 4096_SCLK WKUPx shall be in its active state for at least 4,096 SLCK periods
5 32768_SCLK WKUPx shall be in its active state for at least 32,768 SLCK periods
Value Name Description
0 DISABLE Disable the low-power debouncers.
1 2_RTCOUT0 WKUP0/1 in active state for at least 2 RTCOU Tx clock period s
2 3_RTCOUT0 WKUP0/1 in active state for at least 3 RTCOU Tx clock period s
3 4_RTCOUT0 WKUP0/1 in active state for at least 4 RTCOU Tx clock period s
4 5_RTCOUT0 WKUP0/1 in active state for at least 5 RTCOU Tx clock period s
5 6_RTCOUT0 WKUP0/1 in active state for at least 6 RTCOU Tx clock period s
6 7_RTCOUT0 WKUP0/1 in active state for at least 7 RTCOU Tx clock period s
7 8_RTCOUT0 WKUP0/1 in active state for at least 8 RTCOU Tx clock period s
345
SAM4S Series [DATASHEET]
Atmel-11100K-ATARM-SAM4S-Datasheet_09-Jun-15
18.5.7 Supply Controller Wake-up Inputs Register
Name: SUPC_WUIR
Address: 0x400E1420
Access: Read/Write
This register is located in the VDDIO domain.
This register can on ly be writte n if the W PEN bit is clea re d in the Syst em Con trolle r Writ e Pro te ctio n M od e Register
(SYSC_MR).
• WKUPEN0 - WKUPENx: Wake-up Input Enable 0 to x
0 (DISABLE): The corresponding wake-up input has no wake-up effect.
1 (ENABLE): The corresponding wake-up input is enabled for a wake-up of the core power supply.
• WKUPT0 - WKUPTx: Wake-up Input Type 0 to x
0 (LOW): A falling edge followed by a low level for a period defined by WKUPDBC on the corresponding wake-up input
forces the wake-up of the core power supply.
1 (HIGH): A rising edge followed by a high level for a period defined by WKUPDBC on the corresponding wake-up input
forces the wake-up of the core power supply.
31 30 29 28 27 26 25 24
WKUPT15 WKUPT14 WKUPT13 WKUPT12 WKUPT11 WKUPT10 WKUPT9 WKUPT8
23 22 21 20 19 18 17 16
WKUPT7 WKUPT6 WKUPT5 WKUPT4 WKUPT3 WKUPT2 WKUPT1 WKUPT0
15 14 13 12 11 10 9 8
WKUPEN15 WKUPEN14 WKUPEN13 WKUPEN12 WKUPEN11 WKUPEN10 WKUPEN9 WKUPEN8
76543210
WKUPEN7 WKUPEN6 WKUPEN5 WKUPEN4 WKUPEN3 WKUPEN2 WKUPEN1 WKUPEN0
SAM4S Series [DATASHEET]
Atmel-11100K-ATARM-SAM4S-Datasheet_09-Jun-15
346
18.5.8 Supply Controller Status Register
Name: SUPC_SR
Address: 0x400E1424
Access: Read-only
Note: Because of the asynchronism between the Slow Clock (SLCK) and the System Clock (MCK), the status register flag reset is taken
into account only 2 slow clock cycles after the read of the SUPC_SR.
This register is located in the VDDIO domain.
• WKUPS: WKUP Wake-up Status (cleared on read)
0 (NO): No wake-up due to the assertion of the WKUP pins has occurred since the last read of SUPC_SR.
1 (PRESENT): At least one wake-up due to the assertion of the WKUP pins has occurred since the last read of SUPC_SR.
• SMWS: Supply Monitor Detection Wake-up Status (cleared on read)
0 (NO): No wake-up due to a supply monitor detection has occurred since the last read of SUPC_SR.
1 (PRESENT): At least one wake-up due to a supply monitor detection has occurred since the last read of SUPC_SR.
• BODRSTS: Brownout Detector Reset Status (cleared on read)
0 (NO): No core brownout rising edge event has been dete cted since the last read of the SUPC_SR.
1 (PRESENT): At least one brownout output rising edge event has been detected since the last read of the SUPC_SR.
When the voltage remains below the defined threshold, there is no rising edge event at the output of the brownout detec-
tion cell. The rising edge event occurs only when there is a voltage transition below the threshold.
• SMRSTS: Supply Monitor Reset Status (cleared on read)
0 (NO): No supply monitor detection has generated a core reset since the last rea d of the SUPC _SR .
1 (PRESENT): At least one supply monitor detection has generated a core reset since the last read of the SUPC_SR.
• SMS: Supply Monitor Status (cleared on read)
0 (NO): No supply mon it or det ec tio n since the last read of SUPC _SR .
1 (PRESENT): At least one supply monitor detection since the last read of SUPC_SR.
• SMOS: Supply Monitor Output Status
0 (HIGH): The supply monitor detected VDDIO higher than its threshold at its last measurement.
1 (LOW): The supply monitor detected VDDIO lower than its threshold at its last measurement.
31 30 29 28 27 26 25 24
WKUPIS15 WKUPIS14 WKUPIS13 WKUPIS12 WKUPIS11 WKUPIS10 WKUPIS9 WKUPIS8
23 22 21 20 19 18 17 16
WKUPIS7 WKUPIS6 WKUPIS5 WKUPIS4 WKUPIS3 WKUPIS2 WKUPIS1 WKUPIS0
15 14 13 12 11 10 9 8
–LPDBCS1LPDBCS0–––––
76543210
OSCSEL SMOS SMS SMRSTS BODRSTS SMWS WKUPS –
347
SAM4S Series [DATASHEET]
Atmel-11100K-ATARM-SAM4S-Datasheet_09-Jun-15
• OSCSEL: 32-kHz Oscillator Selection Status
0 (RC): The slow clock, SLCK, is generated by the embedded 32 kHz RC oscillator.
1 (CRYST): The slow clock, SLCK, is generated by the 32 kHz crystal oscillator.
• LPDBCS0: Low-power Debouncer Wake-up Status on WKUP0 (cleared on read)
0 (NO): No wake-up due to the assertion of the WKUP0 pin has occurred since the last read of SUPC_SR.
1 (PRESENT): At least one wake-up due to the assertion of the WKUP0 pin h as occurred since th e last read of SUPC_SR.
• LPDBCS1: Low-power Debouncer Wake-up Status on WKUP1 (cleared on read)
0 (NO): No wake-up due to the assertion of the WKUP1 pin has occurred since the last read of SUPC_SR.
1 (PRESENT): At least one wake-up due to the assertion of the WKUP1 pin has occurred since the last read of SUPC_SR.
• WKUPISx: WKUPx Input Status (cleared on read)
0 (DIS): The corresponding wake-up input is disabled, or was inactive at the time the debouncer triggered a wake-up
event.
1 (EN): The corresponding wake-up input was active at the time the debouncer triggered a wake-up event since the last
read of SUPC_SR.
SAM4S Series [DATASHEET]
Atmel-11100K-ATARM-SAM4S-Datasheet_09-Jun-15
348
18.5.9 System Controller Write Protection Mode Register
Name: SYSC_WPMR
Access: Read/Write
• WPEN: Write Protec ti on Ena b le
0: Disables the write protection if WPKEY corresponds to 0x525443 (“RTC” in ASCII).
1: Enables the write protection if WPKEY corresponds to 0x525443 (“RTC” in ASCII).
See Section 18.4.8 ”Register Write Protection” for the list of registers that can be write-protected.
• WPKEY: Write Protection Key.
31 30 29 28 27 26 25 24
WPKEY
23 22 21 20 19 18 17 16
WPKEY
15 14 13 12 11 10 9 8
WPKEY
76543210
–––––––WPEN
Value Name Description
0x525443 PASSWD Writing any other value in this field aborts the write operation of the WPEN bit.
Always reads as 0.
349
SAM4S Series [DATASHEET]
Atmel-11100K-ATARM-SAM4S-Datasheet_09-Jun-15
19. General Purpose Backup Registers (GPBR)
19.1 Description
The System Contr olle r em b ed s 25 6 bits of Ge ne ra l Purpo se Ba cku p re gisters organi zed as Eight 32 -b it re gist er s.
It is possible to generate an immed iate clear of the content o f General Pur pose Ba ckup register s 0 to 3 (first h alf) if
a Low-power Deboun ce event is detected on one of the wakeup pins, WKUP0 or WKUP1. The content of the other
General Purpose Backup registers (second half) remains unchanged.
The Supply Controller module must be programmed accordingly. In the register SUPC_WUMR in the Supply
Controller module, LPDBCCLR, LPDBCEN0 and/or LPDBCEN1 bit must be configured to 1 and LPDBC must be
other than 0.
If a Tamper event has been detected , it is not possible to write to the General Purpose Backup registers while the
LPDBCS0 or LPDBCS1 flags are not cleared in the Supply Controller Status Register (SUPC_SR).
19.2 Embedded Characteristics
256 bits of General Purpose Backup Registers
SAM4S Series [DATASHEET]
Atmel-11100K-ATARM-SAM4S-Datasheet_09-Jun-15
350
19.3 General Purpose Backup Registers (GPBR) User Interface
Table 19-1 . Register Mapping
Offset Register Name Access Reset
0x0 General Purpose Backup Register 0 SYS_GPBR0 Read/Write 0x00000000
... ... ... ... ...
0x1C General Purpose Backup Register 7 SYS_GPBR7 Read/Write 0x00000000
351
SAM4S Series [DATASHEET]
Atmel-11100K-ATARM-SAM4S-Datasheet_09-Jun-15
19.3.1 General Purpose Backup Regi ster x
Name: SYS_GPBRx
Address: 0x400E1490
Access: Read/Write
These registers are reset at first power-up and on each loss of VVDIO.
• GPBR_VALUE: Value of GPBR x
If a Tamper event has been detected, it is not possible to write GPBR_VALUE as long as the LPDBCS0 or LPDBCS1 flag
has not been cleared in the Supply Controller Status Register (SUPC_SR).
31 30 29 28 27 26 25 24
GPBR_VALUE
23 22 21 20 19 18 17 16
GPBR_VALUE
15 14 13 12 11 10 9 8
GPBR_VALUE
76543210
GPBR_VALUE
SAM4S Series [DATASHEET]
Atmel-11100K-ATARM-SAM4S-Datasheet_09-Jun-15
352
20. Enhanced Embedded Flash Controller (EEFC)
20.1 Description
The Enhanced Embedded Flas h Controller (EEFC) pr ovides the interface o f the Flash block with the 32-bit internal
bus.
Its 128-bit or 64-bit wide memory interface increases performance. It also manages the programming, erasing,
locking and unlockin g sequences of the Flash u sing a full set of commands. One of the commands returns the
embedded Flash descriptor definition that informs the system about the Flash organization, thus making the
software generic.
20.2 Embedded Characteristics
Increases Performance in Thumb-2 Mode with 128-bit or 64-bit-wide Memory Interface up to 120 MHz
Code Loop Optimization
256 Lock Bits, Each Protecting a Lock Region
GPNVMx General-purpose GPNVM Bits
One-by-one Lock Bit Programming
Commands Protected by a Keyword
Erase the Entire Fl as h
Erase by Plane
Erase by Sector
Erase by Page
Provides Unique Identifier
Provides 512-byte User Signature Area
Supports Erasing before Programming
Locking and Un loc king Op er at ion s
Supports Read of the Calibration Bits
20.3 Product Dependencies
20.3.1 Power Management
The Enhanced Embedded Flash Controller (EEFC) is continuously clocked. The Power Management Controller
has no effect on its behavior.
20.3.2 Interrupt Sources
The EEFC interrupt lin e is connected to the interrupt contro ller. Using the EEFC interrupt requires the interrupt
controller to be programmed first. The EEFC interrupt is generated only if the value of bit EEFC_FMR.FRDY is 1.
Table 20-1. Peripheral IDs
Instance ID
EFC0 6
EFC1 7
353
SAM4S Series [DATASHEET]
Atmel-11100K-ATARM-SAM4S-Datasheet_09-Jun-15
20.4 Functional Description
20.4.1 Embedded Flash Organization
The embedded Flash interfaces directly with the internal bus. The embedded Flash is composed of:
One memory plane organized in several pages of the same size for the code
A separate 2 x 512-byte memory area which includes the unique chip identifier
A separate 512-byte memory area for the user signature
Two 128-bit or 64-bit read buffers used for code read optimization
One 128-bit or 64-bit read buffer used for data read optimization
One write buf fer that manage s page programming. The write buf fer size is equal to the pag e size. This buffer
is write-only and accessible all along the 1 Mbyte address space, so that each word can be written to its final
address.
Several lock bits used to protect write/erase operation on several pages (lock region). A lock bit is
associated with a lock region composed of several pages in the memory plane.
Several bits that may be set and cleared through the EEFC interface, called general-purpose non-volatile
memory bits (GPNVM bits)
The embedded Flash size, the page size, the organization of lock regions and the definition of GPNVM bits are
specific to the device. The EEFC returns a descriptor of the Flash controller after a ‘Get Flash Descriptor’
command has been issued by the application (see Section 20.4.3.1 ”Get Flash Descriptor Command”).
SAM4S Series [DATASHEET]
Atmel-11100K-ATARM-SAM4S-Datasheet_09-Jun-15
354
Figure 20-1. Flash Memory Areas
@FBA+0x000
User Signature Area
Unique Identifier Area
Unique Identifier
Code Area
@FBA+0x1FF
@FBA+0x000
@FBA+0x3FF
@FBA+0x000
Write “Start Unique Identifier”
(Flash Command STUI)
Write “Start User Signature”
(Flash Command STUS)
@FBA+0x010
@FBA+0x010
Write “Stop Unique Identifier”
(Flash Command SPUI)
Write “Stop User signature”
(Flash Command SPUS)
FBA = Flash Base Address
355
SAM4S Series [DATASHEET]
Atmel-11100K-ATARM-SAM4S-Datasheet_09-Jun-15
Figure 20-2. Organization of Embedd ed Flash for Code
Start Address
Page 0
Lock Region 0
Lock Region 1
Memory Plane
Page (m-1)
Lock Region (n-1)
Page (n*m-1)
Start Address + Flash size -1
Lock Bit 0
Lock Bit 1
Lock Bit (n-1)
SAM4S Series [DATASHEET]
Atmel-11100K-ATARM-SAM4S-Datasheet_09-Jun-15
356
20.4.2 Read Operations
An optimized controller manages emb edded Flash reads, thus increasing performance when the p rocessor is
running in Thumb-2 mode by means of the 128- or 64-bit-wide memory interface.
The Flash memory is accessible through 8-, 16- and 32-bit reads.
As the Flash block size is smaller than the address space reserved for the internal memory area, the embedded
Flash wraps around the address space and appears to be repeated within it.
The read operations can be performed with or without wait states. Wait states must be programmed in the field
FWS in the Flash Mode register (EEFC_FMR). Defining FWS as 0 enables the single-cycle access of the
embedded Flash. For mre details, refer to the section “Electrical Characteristics” of this datasheet.
20.4.2.1 128- or 64-bit Access Mode
By default, the read acce sses of the Flash are performed through a 128-bit wide memory interfa ce. It improves
system performance especially when two or three wait states are needed.
For system s requ iring only 1 w ait sta t e, or to focus on current consumption rather than performance, the user can
select a 64-bit wide memory access via the bit EEFC_FMR.FAM.
For more details, refer to the section “Electrical Characteristics” of this datasheet.
20.4.2.2 Code Read Optimization
Code read optimization is enabled if the bit EEFC_FMR.SCOD is cleared.
A system of 2 x 128-bit or 2 x 64-bit buffers is added in order to optimize sequential code fetch.
Note: Imme diate consecutive code read accesses are not mandatory to benefit from this optimization.
The sequential code read optimization is enabled by default. If the bit EEFC_FMR.SCOD is set to 1, these buffers
are disabled and the sequential code read is no longer optimized.
Figure 20-3. Code Read Optimization for FWS = 0
Note: When FWS is equal to 0, all the accesses are performed in a single-cycle access.
Another system of 2 x 128-bit or 2 x 64-bit buffers is added in order to optimize loop code fetch. Refer to
Section 20.4.2.3 ”Code Loop Optimization” for more details.
Flash Access
Buffer 0 (128 bits)
Master Clock
ARM Request
(32-bit)
XXX
Data to ARM
Bytes 0–15 Bytes 16–31 Bytes 32–47
Bytes 0–15
Buffer 1 (128 bits)
Bytes 32–47
Bytes 0–3 Bytes 4–7 Bytes 8–11 Bytes 12–15 Bytes 16–19 Bytes 20–23 Bytes 24–27
XXX
XXX Bytes 16–31
@ 0 @+4 @ +8 @+12 @+16 @+20 @+24 @+28 @+32
Bytes 28–31
anticipation of @16-31
357
SAM4S Series [DATASHEET]
Atmel-11100K-ATARM-SAM4S-Datasheet_09-Jun-15
Figure 20-4. Code Read Optimization for FWS = 3
Note: When FWS is between 1 and 3, in case of sequential reads, the first access takes (FWS + 1) cycles. The following accesses take
only one cycle.
20.4.2.3 Code Loop Optimization
Code loop optimization is enabled when the bit EEFC_FMR.CLOE is set to 1.
When a backw ard jum p is insert ed in the code, t he pipelin e of the s equen tial optimiz ation is broken and bec omes
inefficient. In this case, the loop code read optimization takes over from the sequential code read optimization to
prevent the insertion of wait states. The loop co de read op timization is enabled by default. In EEFC_FMR, if the bit
CLOE is reset to 0 or the bit SCOD is set to 1, these buffers are disabled and the loop code read is not optimized.
When code loop optimization is e nabled, if inner loop body instructions L 0 to Ln are positioned from the 128-b it
Flash memory cell Mb0 to the memory cell M p1, after recognition of a first backward branch, the first two Flash
memory cells Mb0 and Mb1 targeted by this branch are cached for fast access from the processor at the next loop
iteration.
Then by combining the sequential prefetch (described in Section 20.4.2.2 ”Code Read Optimization”) through the
loop body with the fast read access to the loop entry cache, the entire loop can be iterated with no wait state.
Figure 20-5 illustrates code loop optimization.
Figure 20-5. Code Loop Optimization
Flash Access
Buffer 0 (128 bits)
Master Clock
ARM Request
(32-bit)
Data to ARM
Buffer 1 (128 bits)
0–3
XXX
XXX
Bytes 16–31
@ 0 @+4 @+8
Bytes 0–15 Bytes 16–31 Bytes 32–47 Bytes 48–6
Bytes 0–15
4–7 8–11 12–15
@+12 @+16 @+20
24–27 28–31 32–35 36–3916–19 20–23 40–43 44–47
@+24 @+28 @+32 @+36 @+40 @+44 @+48 @+52
Bytes 32–47
48–51
anticipation of @16-31 anticipation of @32-47
wait 3 cycles before
128-bit data is stable @0/4/8/12 are ready @16/20/24/28 are ready
L
n
L
n-1
L
n-2
L
n-3
L
n-4
L
n-5
L
5
L
4
L
3
L
2
L
1
L
0
B
1
B
2
B
3
B
4
B
5
B
6
B
7
B
0
P
1
P
2
P
3
P
4
P
5
P
6
P
7
P
0
M
b0
M
b0
M
b1
M
p0
M
p1
Backward address j ump
2x128-bit loop entry
cache 2x128-bit prefetch
buffer
L
0
Loop Entry instruction
L
n
Loop End instruction
Flash Memory
128-bit words
M
b0
Branch Cache 0
M
b1
Branch Cache 1
M
p0
Prefetch Buffer 0
M
p1
Prefetch Buffer 1
SAM4S Series [DATASHEET]
Atmel-11100K-ATARM-SAM4S-Datasheet_09-Jun-15
358
20.4.2.4 Data Read Optimization
The organization of the Flash in 128 bits or 64 bits is associated with two 128-bit or 64-bit prefetch buffers and one
128-bit or 64-bit data read buffer, thus providing maximum system performance. This buffer is added in order to
store the requested data plus all th e data containe d in the 128 -bit or 64-bit aligned data. This speeds up seque ntial
data reads if, for example, F WS is equal to 1 (s ee Figure 20-6 ). The data read optimization is e nabled by default. If
the bit EEFC_FMR.SCOD is set to 1, this buffer is disabled and the data read is no longer optimized.
Note: No consecutive data read accesses are mandatory to benefit from this optimization.
Figure 20-6. Data Read Optimization for FWS = 1
20.4.3 Flash Commands
The EEFC offers a set of commands to manage programming the Flash memory, locking and unlocking lock
regions, consecutive programming, locking and full Flash erasing, etc.
The commands are listed in the following table.
Flash Access
Buffer (128 bits)
Master Clock
ARM Request
(32-bit)
XXX
Data to ARM
Bytes 0–15 Bytes 16–31
Bytes 0–15
Bytes 0–3 4–7 8–11 12–15 16–19 20–23
XXX
Bytes 16–31
@Byte 0 @ 4 @ 8 @ 12 @ 16 @ 20 @ 24 @ 28 @ 32 @ 36
XXX Bytes 32–47
24–27 28–31 32–35
Table 20-2. Set of Commands
Command Value Mnemonic
Get Flash descriptor 0x00 GETD
Write page 0x0 1 WP
Write page and lock 0x02 WPL
Erase page and write page 0x03 EWP
Erase page and write page then lock 0x04 EWPL
Erase all 0x05 EA
Erase pag e s 0x07 EPA
Set lock bit 0x08 SLB
Clear lock bit 0x09 CLB
Get lock bit 0x0A GLB
Set GPNVM bit 0x0B SGPB
Clear GPNVM bit 0x0C CGPB
359
SAM4S Series [DATASHEET]
Atmel-11100K-ATARM-SAM4S-Datasheet_09-Jun-15
In order to execute one of these commands, select the required command using the FCMD field in the Flash
Command register (EEFC_FCR). As soon as EEFC_FCR is written, the FRDY flag and the FVALUE field in the
Flash Result register ( EEFC_FRR) are automatically cleared . Once the current command has comple ted, the
FRDY flag is automatically set. If an interrupt has been enabled by setting the bit EEFC_FMR.FRDY, the
corresponding interrupt line o f the interrupt controller is activated. (Note that this is true for all commands excep t
for the STUI command. The FRDY flag is not set when the STUI command has completed.)
All the commands are protected by the same keyword, which must be written in the eight highest bits of
EEFC_FCR.
Writing EEFC_FCR with data that does not contain the correct key and/or with an invalid command has no effect
on the whole memory plane, but the FCMDE flag is set in the Flash Status register (EEFC_FSR). This flag is
automatically cleared by a read access to EEFC_FSR.
When the current command writes or erases a page in a locked region, the command has no effect on the whole
memory plane, but the FLOC KE flag is set in EEFC_FSR. This flag is automatically cleared by a read access to
EEFC_FSR.
Get GPNVM bit 0x0D GGPB
Start read unique identifier 0x0E STUI
Stop read uniqu e identifier 0x0F SPUI
Get CALIB bit 0x10 GCALB
Erase sector 0x11 ES
Write user signature 0x12 WUS
Erase user signature 0x13 EUS
Start read user signature 0x14 STUS
Stop read user signature 0x15 SPUS
Table 20-2. Set of Commands (Continued)
Command Value Mnemonic
SAM4S Series [DATASHEET]
Atmel-11100K-ATARM-SAM4S-Datasheet_09-Jun-15
360
Figure 20-7. Command Stat e Chart
20.4.3.1 Get Flash Descriptor Command
This command provides the system with information on the Flash organization. The system can take full
advantage of this information. For instance, a device could be replaced by one with more Flash capacity, and so
the software is able to adapt itself to the new configuration.
To get the embedded Fla sh descrip tor, the app lication wr ites the GETD command in EEFC_FCR. The first word of
the descriptor can be read by the software application in EEFC_FRR as soon as the FRDY flag in EEFC_FSR
rises. The next reads of EEFC_FRR provide the following word of the descriptor. If extra read operations to
EEFC_FRR are done after the last word of the descriptor has been returned, the EEFC_FRR value is 0 until the
next valid command.
Check if FRDY flag Set No
Yes
Read Status: EEFC_FSR
Write FCMD and PAGENB in Flash Command Register
Check if FLOCKE flag Set
Check if FRDY flag Set No
Read Status: EEFC_FSR
Yes
Yes Locking region violation
No
Check if FCMDE flag Set Yes
No
Bad keyword violation
Command Successful
361
SAM4S Series [DATASHEET]
Atmel-11100K-ATARM-SAM4S-Datasheet_09-Jun-15
20.4.3.2 Write Commands
Several commands are used to program the Flash.
Only 0 values can be programmed using Flash technology; 1 is the erased value. In order to program words in a
page, the page must firs t be erase d. Commands are available to er ase the fu ll memory plane or a given number of
pages. With the EWP and EWPL commands, a page erase is done automatically before a page programming.
After programming, the page (the entire lock region) can be locked to prevent miscellaneous write or erase
sequences. The lock bit can be automatically set after page programming using WPL or EWPL commands.
Data to be programmed in the Flash must be written in an internal latch buffer before writing the programming
command in EEFC_FCR. Data can be written at their final destination address, as the latch buffer is mapped into
the Flash memory address space and wraps around within this Flash address space.
Byte and half-word AHB accesses to the latch buffer are not allowed. Only 32-bit word accesses are supported.
32-bit words must be written continuously, in either as cending or descending order. Writing the latch buffer in a
random order is not permitted. This prevents mapping a C-co de structure to the latch buffer an d accessing the
data of the structure in any order. It is instead recommended to fill in a C-code structure in SRAM and copy it in the
latch buffer in a continuous order.
Write operations in the latch buffer are performed with the number of wait states programmed for reading the
Flash.
The latch buffer is automatically re-initialized, i.e., written with logical 1, after execution of each progra mming
command. However, after power-up, the latch buffer is not initialized. If only part of the page is to be written with
user data, the remaining part must be erased (written with 1).
The programming sequence is the following:
1. Write the dat a to be programmed in the latch buffer.
2. Write the programming command in EEFC_FCR. This automatically clears the bit EEFC_FSR.FRDY.
3. When Flash programming is completed, the bit EEFC_FSR.FRDY rises. If an interrupt has been enable d by
setting the bit EEFC_FMR.FRDY, the interrupt line of the EEFC is activated.
Three errors can be detecte d in EEF C_F SR after a program min g sequ e nc e:
Command Error: A bad keyword has been written in EEFC_FCR.
Lock Error: The page to be programmed belongs to a locked region. A command must be run previously to
unlock the corresponding region.
Flash Error: When programming is completed, the Wr iteVerify test of the Flash memory has failed.
Only one page can be programmed at a time. It is possible to program all the bits of a page (full page
programming) or only some of the bits of the page (partial pag e pr og ra m m i ng ).
Table 20-3 . Flash Descriptor Definition
Symbol Word Index Description
FL_ID 0 Flash interface descrip ti o n
FL_SIZE 1 Flash size in bytes
FL_PAGE_SIZE 2 Page size in bytes
FL_NB_PLANE 3 Number of planes
FL_PLANE[0] 4 Number of bytes in the plane
FL_NB_LOCK 4 + FL_NB_PLANE Number of lock bits. A bit is associated with a lock region. A lock bit is
used to prevent write or erase operations in the lock region.
FL_LOCK[0] 4 + FL_NB_PLANE + 1 Number of bytes in the first lock region
SAM4S Series [DATASHEET]
Atmel-11100K-ATARM-SAM4S-Datasheet_09-Jun-15
362
Depending on the number of bits to be programmed within the page, the EEFC adapts the write operations
required to program the Flash.
When a ‘Write Page’ (WP) command is issued, the EEFC starts the pro grammin g sequen ce and all the bits written
at 0 in the latch buffer are cleared in the Flash memory array.
During programming, i.e., until EEFC_FSR .FDRY rises, access to the Flash is not allowed.
Full Page Programming
To program a full page, all the bits of the page must be erased before writing the latch buffer and issuing the WP
command. The latch buffer must be written in ascending order, starting fro m the first address of the page. See
Figure 20-8 "Full Page Programming".
Partial Page Programming
To program only part of a page using the WP command, the following constraints must be respected:
See Figure 20-9 "Partial Page Programming".
Programming Bytes
Individual bytes can be programmed using the Partial page programming mode.
Refer to Figure 20-10 "Programming Bytes in the Flash".
Data to be programmed must be contained in integer multiples of 64-bit address-aligned
words.
64-bit words can be programmed only if all the corresponding bits in the Flash array are
erased (at logical value 1).
In this case, an area of 64 bits must be reserved for each byte.
363
SAM4S Series [DATASHEET]
Atmel-11100K-ATARM-SAM4S-Datasheet_09-Jun-15
Figure 20-8. Full Page Programming
FF FF FF FF
FF FF FF FF
FF FF FF FF
FF FF FF FF
0xX00
0xX04
0xX08
0xX0C
0xX10
0xX14
0xX18
0xX1C
0xX00
0xX04
0xX08
0xX0C
0xX10
0xX14
0xX18
0xX1C
0xX00
0xX04
0xX08
0xX0C
0xX10
0xX14
0xX18
0xX1C
Before programming: Unerased page in Flash array
CA FE CA FE
CA FE CA FE
CA FE CA FE
CA FE CA FE
CA FE CA FE
CA FE CA FE
CA FE CA FE
CA FE CA FE
Step 1: Flash array after page erase
FF FF FF FF
FF FF FF FF
FF FF FF FF
FF FF FF FF
address space
for
Page N
address space
for
latch buffer
Step 2: Writing a page in the latch buffer
DE CA DE CA
DE CA DE CA
DE CA DE CA
DE CA DE CA
DE CA DE CA
DE CA DE CA
DE CA DE CA
DE CA DE CA
DE CA DE CA
CA FE CA FE
0xX00
0xX04
0xX08
0xX0C
0xX10
0xX14
0xX18
0xX1C
address space
for
Page N
Step 3: Page in Flash array after issuing
WP command and FRDY=1
DE CA DE CA
DE CA DE CA
DE CA DE CA
DE CA DE CA
DE CA DE CA
DE CA DE CA
DE CA DE CA
DE CA DE CA
DE CA DE CA
FF FF FF FF
32 bits wide 32 bits wide
SAM4S Series [DATASHEET]
Atmel-11100K-ATARM-SAM4S-Datasheet_09-Jun-15
364
Figure 20-9. Partial Page Programming
32 bits wide 32 bits wide
FF FF FF FF
FF FF FF FF
FF FF FF FF
FF FF FF FF
0xX00
0xX04
0xX08
0xX0C
0xX10
0xX14
0xX18
0xX1C
Step 2: Flash array after programming
64-bit at address 0xX08 (write latch buffer + WP)
CA FE CA FE
CA FE CA FE
FF FF FF FF
FF FF FF FF
address space
for
Page N
FF FF FF FF
FF FF FF FF
FF FF FF FF
FF FF FF FF
FF FF FF FF
FF FF FF FF
FF FF FF FF
FF FF FF FF
Step 1: Flash array after page erase
C
A FE
C
A F
E
C
A FE
C
A F
E
32 bits wide
FF FF FF FF
FF FF FF FF
FF FF FF FF
FF FF FF FF
0xX00
0xX04
0xX08
0xX0C
0xX10
0xX14
0xX18
0xX1C
Step 3: Flash array after programming
a second 64-bit data at address 0xX00
(write latch buffer + WP)
CA FE CA FE
CA FE CA FE
FF FF FF FF FF FF FF FF
FF FF FF FF
CA FE CA FE
CA FE CA FE
32 bits wide
0xX00
0xX04
0xX08
0xX0C
0xX10
0xX14
0xX18
0xX1C
Step 4: Flash array after programming
a 128-bit data word at address 0xX10
(write latch buffer + WP)
CA FE CA FE
CA FE CA FE
FF FF FF FF
CA FE CA FE
CA FE CA FE
CA FE CA FE
CA FE CA FE
CA FE CA FE
CA FE CA FE
365
SAM4S Series [DATASHEET]
Atmel-11100K-ATARM-SAM4S-Datasheet_09-Jun-15
Figure 20-10. P rogramming Bytes in the Flash
20.4.3.3 Erase Commands
Erase commands are allowed only o n u nlocked re gion s. Depend ing on th e Flash memor y, several comm and s can
be used to erase the Flash:
Erase All Memory (EA): All memory is erased. The processor must not fetch code from the Flash memory.
Erase Pages (EPA): 8 or 16 pages are erased in the Flash sector selected. The first page to be erased is
specified in the FARG[15:2] field of the EEFC_FCR. The first page number must be a multiple of 8, 16 or 32
depending on the number of pages to erase at the same time.
Erase Sector (ES): A full memory sector is erased. Sector size depends on the Flash memory.
EEFC_FCR.FARG must be set with a page number that is in the sector to be erased.
If the processor is fetching code from the Flash memory while the EPA or ES command is being executed, the
processor accesses are stalled until the EPA command is completed. To avoid stalling the processor, the code can
be run out of intern al S RAM .
32 bits wide
FF FF FF FF
FF FF FF FF
FF FF FF FF
FF FF FF FF
0xX00
0xX04
0xX08
0xX0C
0xX10
0xX14
0xX18
0xX1C
FF FF FF FF
FF FF FF FF
address space
for
Page N
Step 1: Flash array after programming first byte (0xAA)
64-bit used at address 0xX00 (write latch buffer + WP)
FF FF FF FF
xx xx xx xx
xx xx xx AA
32 bits wide
FF FF FF FF
FF FF FF FF
FF FF FF FF
FF FF FF FF
0xX00
0xX04
0xX08
0xX0C
0xX10
0xX14
0xX18
0xX1C
FF FF FF FF
xx xx xx xx
xx xx xx AA
Step 2: Flash array after programming second byte (0x55)
64-bit used at address 0xX08 (write latch buffer + WP)
xx xx xx xx
xx xx xx 55
Note: The byte location shown here is for example only, it can be any byte location within a 64-bit word.
4 x 32 bits =
1 Flash word
4 x 32 bits =
1 Flash word
SAM4S Series [DATASHEET]
Atmel-11100K-ATARM-SAM4S-Datasheet_09-Jun-15
366
The erase seq u enc e is the follo win g :
1. Erase starts as soon as one of the erase commands and the FARG field are written in EEFC_F CR .
For the EPA command, the two lowest bits of the FARG field define the num ber of p ages to be er ased
(FARG[1:0]):
2. When erasing is completed, the bit EEFC_FSR.FRDY rises. If an interrupt has been enabled by setting the
bit EEFC_FMR.FRDY, the interrupt line of the interrupt controller is activated.
Three errors can be detecte d in EEF C_F SR after an erasing se qu en ce :
Command Error: A bad keyword has been written in EEFC_FCR.
Lock Error: At least one page to be erased belongs to a locked region. The erase command has been
refused, no page has been erased. A command must be run previously to unlock the corresponding region.
Flash Error: At the end of the erase period, the EraseVerify test of the Flash memory has failed.
20.4.3.4 Lock Bit Protection
Lock bits are associated with several pages in the embed ded Flash memo ry plane. This defines lock re gions in the
embedded Fla sh me mo ry pl an e. Th ey pr ev en t writing/erasin g protected page s.
The lock sequence is the following:
1. Execute the ‘Set Lock Bit’ command by writing EEFC_FCR.FCMD with the SLB command and
EEFC_FCR.FARG with a page number to be protected.
2. When the locking completes, the bit EEFC_FSR.FRDY rises. If an interrupt has been enable d by setting the
bit EEFC_FMR.FRDY, the interrupt line of the interrupt controller is activated.
3. The result of the SLB command can be checked running a ‘Get Lock Bit’ (GLB) command.
Note: The value of the FA RG argument passed together with SLB command must not exceed the higher lock bit index
available in the product.
Two errors can be detected in EEFC_FSR after a programming sequence:
Command Error: A bad keyword has been written in EEFC_FCR.
Flash Error: At the end of the programming, the EraseVerify or WriteVerify test of the Flash memory has
failed.
It is possible to clear lock bits previously set. After the lock bits are cleared, the locked region can be erased or
programmed. The unlock sequence is the following:
1. Execute the ‘Clear Lock Bit’ command by writing EEFC_FCR.FCMD with the CLB command and
EEFC_FCR.FARG with a page number to be unprotected.
2. When the unlock completes, the bit EEFC_FSR.FRDY rises. If an interrupt has been enabled by setting the
bit EEFC_FMR.FRDY, the interrupt line of the interrupt controller is activated.
Note: The value of the FA RG argument passed together with CLB command must not exceed the higher lock bit index
available in the product.
Two errors can be detected in EEFC_FSR after a programming sequence:
Command Error: A bad keyword has been written in EEFC_FCR.
Table 20-4. EEFC_FCR.FARG Field for EPA Command
FARG[1:0] Number of pages to be erased with EPA command
0 4 pages (only valid for small 8 KB sectors)
1 8 pages
2 16 pages
3 32 pages (not valid for small 8 KB sectors)
367
SAM4S Series [DATASHEET]
Atmel-11100K-ATARM-SAM4S-Datasheet_09-Jun-15
Flash Error: At the end of the programming, the EraseVerify or WriteVerify test of the Flash memory has
failed.
The status of lock bits can be returned by the EEFC. The ‘Get Lock Bit’ sequence is the following:
1. Execute the ‘Get Lock Bit’ command by writing EEFC_FCR.FCMD with the GLB command. Fie ld
EEFC_FCR.FAR G is meaningless.
2. Lock bits can be read by the sof tware application in EEFC_FRR. The first word read corresponds to the 32
first lock bits, next reads providing the next 32 lock bits as long as it is meaningful. Extra reads to
EEFC_FRR return 0.
For example, if the third bit of the first word read in EEFC_FRR is set, the third lock region is locked.
Two errors can be detected in EEFC_FSR after a programming sequence:
Command Error: A bad keyword has been written in EEFC_FCR.
Flash Error: At the end of the programming, the EraseVerify or WriteVerify test of the Flash memory has
failed.
Note: Access to the Flash in read is permitted when a ‘Set Lock Bit’, ‘Clear Lock Bit’ or ‘Get Lock Bit’ command is executed.
20.4.3.5 GPNVM Bit
GPNVM bits do not interfere with the embedded Flash memory plane. For more details, refer to the section
“Memories” of this datasheet.
The ‘Set GPNVM Bit’ sequence is the following:
1. Execute the ‘Set GPNVM Bit’ command by writing EEFC_FCR.FCMD with the SGPB command and
EEFC_FCR.FARG with the number of GPNVM bits to be set.
2. When the GPNVM bit is set, the bit EEFC_FSR.FRDY rises. If an interrupt was enabled by setting the bit
EEFC_FMR.FRDY, the interrupt line of the interrupt controller is activated.
3. The result of the SGPB command can be checked by running a ‘Get GPNVM Bit’ (GGPB) comman d.
Note: The value of the FA RG argument passed together with SGPB command must not exceed the higher GPNVM index
available in the product. Flash data content is not altered if F ARG exceeds the limit. Command Error is detected only if
FARG is greater than 8.
Two errors can be detected in EEFC_FSR after a programming sequence:
Command Error: A bad keyword has been written in EEFC_FCR.
Flash Error: At the end of the programming, the EraseVerify or WriteVerify test of the Flash memory has
failed.
It is possible to clear GPNVM bits previously set. The ‘Clear GPNVM Bit’ sequence is the following:
1. Execute the ‘Clear GPNVM Bit’ command by writing EEFC_FCR.FCMD with the CGPB command and
EEFC_FCR.FARG with the number of GPNVM bits to be cleared.
2. When the clear completes, the bi t EEFC_FSR.FRDY rises. If an interrupt has been en abled by setting the bit
EEFC_FMR.FRDY, the interrupt line of the interrupt controller is activated.
Note: The value of the FA RG argument passed together with CGPB command must not exceed the higher GPNVM index
available in the product. Flash data content is not altered if F ARG exceeds the limit. Command Error is detected only if
FARG is greater than 8.
Two errors can be detected in EEFC_FSR after a programming sequence:
Command Error: A bad keyword has been written in EEFC_FCR.
Flash Error: At the end of the programming, the EraseVerify or WriteVerify test of the Flash memory has
failed.
The status of GPNVM bits can be returned by the EEFC. The sequence is the following:
SAM4S Series [DATASHEET]
Atmel-11100K-ATARM-SAM4S-Datasheet_09-Jun-15
368
1. Execute the ‘Get GPNVM Bit’ command by writing EEFC_FCR.FCMD with the GGPB command. Field
EEFC_FCR.FAR G is meaningless.
2. GPNVM bits can be read by the software application in EEFC_FRR. The first word read corresponds to the
32 first GPNVM bit s, following read s provide the next 3 2 GPNVM bit s as long as it is m eaningful. Extra rea ds
to EEFC_FRR return 0.
For example, if the third bit of the first word read in EEFC_FRR is set, the third GPNVM bit is active.
One error can be detected in EEFC_FSR after a programming sequence:
Command Error: A bad keyword has been written in EEFC_FCR.
Note: Access to the Flas h in read is p ermitte d when a ‘ Set GP NVM Bit’, ‘Clear GPNVM Bit’ or ‘Get GPNVM Bit’ command is
executed.
20.4.3.6 Calibration Bit
Calibration bits do not interfere with the embedded Flash memory plane.
The calibration bits cannot be modified.
The status of calibration bits are returned by the EEFC. The sequence is the following:
1. Execute the ‘Get CALIB Bit’ command by writing EEFC_FCR.FCMD with the GCALB command. Field
EEFC_FCR.FAR G is meaningless.
2. Calibration bits can be read by the software application in EEFC_FRR. The first word read corresponds to
the first 32 calibration bit s. The following reads provide the next 32 calibra tion bits as long as it is meaningful.
Extra reads to EEFC_FRR return 0.
The 4/8/12 MHz fast RC osc illator is calibrated in production. This calibration can be read through the GCALB
command. The following table shows the bit implementation for each frequency.
The RC calibration for the 4 MHz is set to ‘1000000’.
20.4.3.7 Security Bit Protection
When the security bit is enabled, access to the Flash through the SWD interface or through the Fast Flash
Programming interface is forbidden. This ensures the confidentiality of the code programmed in the Flash.
The security bit is GPNVM0 .
Disabling the security bit can only be achieved by asserting the ERASE pin at ‘1’, and after a full Flash erase is
performed. When the security bit is deactivated, all accesses to the Flash are permitted.
20.4.3.8 Unique Identifier Area
Each device is programmed with a 128 bits unique identifier area . See Figure 20-1 "Flash Memory Areas".
The sequence to read the unique identifier area is the following:
1. Execute the ‘Start Read Unique Identif ier’ command b y writing EEFC_FCR.FCMD with the STUI com-
mand. Field EEFC_FCR.FARG is meaningless.
2. Wait until the bit EEFC_FSR.FRDY falls to read the unique identifier area. The unique identifier field is
located in the first 128 bits of the Flash memory mapping. The ‘Start Read Unique Identifier’ command
reuses some addresses of the memory plane for code, but the unique identifier area is physically different
from the memory plane for code.
Table 20-5. Calibration Bit Indexes
RC Calibration Frequency EEFC_FRR Bits
8 MHz output [28–22]
12 MHz output [38–32]
369
SAM4S Series [DATASHEET]
Atmel-11100K-ATARM-SAM4S-Datasheet_09-Jun-15
3. To stop reading the unique identifier area, execute the ‘Stop Read Unique Identifier’ command by writing
EEFC_FCR.FCMD with the SPUI command. Field EEFC_FCR.FARG is meaningless.
4. When the SPUI command has been executed, the bit EEFC_FSR.FRDY rises. If an interrupt was enabled
by setting the bit EEFC_FMR.FRDY, the interrupt line of the interrupt controller is activated.
Note that durin g the se quence, the software cannot be fetched from the Flash.
20.4.3.9 User Signature Area
Each product contains a user signature area of 512-bytes. It can be used for storage. Read , write a nd eras e of this
area is allowed.
See Figure 20-1 "Flash Memory Areas".
The sequence to read the user signature area is the following:
1. Execute the ‘Start Read User Signature’ command by writing EEFC_FCR.FCMD with the STUS com-
mand. Field EEFC_FCR.FARG is meaningless.
2. Wait until the bit EEFC_FSR.FRDY falls to read the user signature area. The user signature area is located
in the first 512 bytes of the Flash memory mapping. The ‘S tart Read User Sign ature’ command reuses som e
addresses of the memory plane but the user signature area is physically different from the memory plane
3. To stop reading the user signature area, execute the ‘Stop Read User Signature’ command by writing
EEFC_FCR.FCMD with the SPUS command. Field EEFC_FCR.FARG is meaningless.
4. When the SPUI command has been executed, the bit EEFC_FSR.FRDY rises. If an interrupt was enabled
by setting the bit EEFC_FMR.FRDY, the interrupt line of the interrupt controller is activated.
Note that during the sequence, the software cannot be fetched from the Flash or from the second plane in case of
dual plane.
One error can be detected in EEFC_FSR after this sequence:
Command Error: A bad keyword has been written in EEFC_FCR.
The sequence to write the user signature area is the following:
1. Write the fu ll page, at any page address, within the internal memory area address space.
2. Execute the ‘Wri te User Signature’ command by writing EEFC_FCR.FCMD with the WUS command. Field
EEFC_FCR.FA RG is meaningless.
3. W he n prog ra m m ing is comp le te d, th e bit EEFC_ FS R.F RDY rises. If an interrupt has been enabled by
setting the bit EEFC_FMR.FRDY, the corresponding interrupt line of the interrupt controller is activated.
Two errors can be detected in EEFC_FSR after this sequence:
Command Error: A bad keyword has been written in EEFC_FCR.
Flash Error: At the end of the programming, the WriteVerify test of the Flash memory has failed.
The sequence to erase the user signature area is the following:
1. Execute the ‘Erase User Signature’ command by writing EEFC_FCR.FCMD with the EUS command.
Field EEFC_FCR.FARG is meaningless.
2. W he n prog ra m m ing is comp le te d, th e bit EEFC_ FS R.F RDY rises. If an interrupt has been enabled by
setting the bit EEFC_FMR.FRDY, the corresponding interrupt line of the interrupt controller is activated.
Two errors can be detected in EEFC_FSR after this sequence:
Command Error: A bad keyword has been written in EEFC_FCR.
Flash Error: At the end of the programming, the EraseVerify test of the Flash memory has failed.
SAM4S Series [DATASHEET]
Atmel-11100K-ATARM-SAM4S-Datasheet_09-Jun-15
370
20.5 Enhanced Embedded Flash Controller (EEFC) User Interface
The User Interface of the Embedded Flash Controller (EEFC) is integ rated within the System Controller with base address
0x400E0A00.
Table 20-6 . Register Mapping
Offset Register Name Access Reset State
0x00 EEFC Flash Mode Register EEFC_FMR Read/Write 0x0400_0000
0x04 EEFC Flash Command Register EEF C_FCR Write-only –
0x08 EEFC Flash Status Reg ister EEFC_FSR Read-only 0x0000_0001
0x0C EEFC Flash Result Register EEFC_FRR Read-only 0x0
0x10–0x14 Reserved – – –
0x18–0xE4 Reserved – – –
371
SAM4S Series [DATASHEET]
Atmel-11100K-ATARM-SAM4S-Datasheet_09-Jun-15
20.5.1 EEFC Flash Mode Register
Name: EEFC_FMR
Address: 0x400E0A00 (0), 0x400E0C00 (1)
Access: Read/Write
• FRDY: Flash Ready Interrupt Enable
0: Flash ready does not generate an interrupt.
1: Flash ready (to ac ce pt a ne w com m a nd ) ge ne rate s an inte rr up t.
• FWS: Flash Wait State
This field defines the number of wait states for read and write operations:
FWS = Number of cycles for Read/Write operations - 1
• SCOD: Sequential Code Optimization Disable
0: The sequential code optimization is enabled.
1: The sequential code optimization is disabled.
No Flash read should be done during change of this field.
• FAM: Flash Access Mode
0: 128-bit access in Read mode only, to enhance access speed.
1: 64-bit access in Read mode only, to enhance power consumption.
No Flash read should be done during change of this field.
• CLOE: Code Loop Optimization Enable
0: The opcode loop optimization is disabled.
1: The opcode loop optimization is enabled.
No Flash read should be done during change of this field.
31 30 29 28 27 26 25 24
–––––CLOE–FAM
23 22 21 20 19 18 17 16
–––––––SCOD
15 14 13 12 11 10 9 8
–––– FWS
76543210
–––––––FRDY
SAM4S Series [DATASHEET]
Atmel-11100K-ATARM-SAM4S-Datasheet_09-Jun-15
372
20.5.2 EEFC Flash Command Register
Name: EEFC_FCR
Address: 0x400E0A04 (0), 0x400E0C04 (1)
Access: Write-only
• FCMD: Flash Command
31 30 29 28 27 26 25 24
FKEY
23 22 21 20 19 18 17 16
FARG
15 14 13 12 11 10 9 8
FARG
76543210
FCMD
Value Name Description
0x00 GETD Get Flash descriptor
0x01 WP Write page
0x02 WPL Write page and lock
0x03 EWP Erase page and write page
0x04 EWPL Erase page and write page then lock
0x05 EA Erase all
0x07 EPA E rase pages
0x08 SLB Set lock bit
0x09 CLB Clear lock bit
0x0A GLB Get lock bit
0x0B SGPB Set GPNVM bit
0x0C CGPB Clear GPNVM bit
0x0D GGPB Get GPNVM bit
0x0E STUI Start read unique identifier
0x0F SPUI Stop read unique identifier
0x10 GCALB Get CALIB bit
0x11 ES Erase sector
0x12 WUS Write user signature
0x13 EUS Erase user signature
0x14 STUS Start read user signature
0x15 SPUS Stop read user signature
373
SAM4S Series [DATASHEET]
Atmel-11100K-ATARM-SAM4S-Datasheet_09-Jun-15
• FARG: Flash Command Argument
• FKEY: Flash Writing Protection Key
GETD, GLB,
GGPB, STUI,
SPUI, GCALB,
WUS, EUS, STUS,
SPUS, EA
Commands
requiring no
argument, including
Erase all command
FARG is meaningless, must be written with 0
ES Erase sector
command FARG must be written with any page number within the sector to be erased
EPA Erase pages
command
FARG[1:0] defines the number of pages to be erased
The start page must be written in FARG[15:2].
FARG[1:0] = 0: Four pages to be erased. FARG[15:2] = Page_Number / 4
FARG[1:0] = 1: Eight pages to be erased. FARG[15:3] = Page_Number / 8, FARG[2]=0
FARG[1:0] = 2: Sixteen pages to be erased. FARG[15:4] = Page_Number / 16,
FARG[3:2]=0
FARG[1:0] = 3: Thirty-two pa ges to be erased. FARG[15:5] = Page_Number / 32,
FARG[4:2]=0
Refer to Table 20-4 “EEFC_FCR.FARG Field for EPA Command”.
WP, WPL, EWP,
EWPL Programming
commands FARG must be written wi th the page number to be prog rammed
SLB, CLB Lock bit commands FARG defines the page number to be locked or unlocke d
SGPB, CGPB GPNVM commands FARG defin es the GPNVM number to be programme d
Value Name Description
0x5A PASSWD The 0x5A value enables the command defined by the bits of the register . If the field is written with a
different value, the write is not performed and no action is started.
SAM4S Series [DATASHEET]
Atmel-11100K-ATARM-SAM4S-Datasheet_09-Jun-15
374
20.5.3 EEFC Flash Status Register
Name: EEFC_FSR
Address: 0x400E0A08 (0), 0x400E0C08 (1)
Access: Read-only
• FRDY: Flash Ready Status (cleared when Flash is busy)
0: The EEFC is busy.
1: The EEFC is ready to start a new command.
When set, this flag triggers an interrupt if the FRDY flag is set in EEFC_FMR.
This flag is automatically cleared when the EEFC is busy.
• FCMDE: Flash Command Error Status (cleared on read or by writing EEFC_FCR)
0: No invalid commands and no bad keywords were written in EEFC_FMR.
1: An invalid command and/or a bad keyword was/were written in EEFC_FMR.
• FLOCKE: Flash Lock Error Status (cleared on read)
0: No programming/erase of at least one locked region has happened since the last read of EEFC_FSR.
1: Programming/erase of at least one locked region has happened since the last read of EEFC_FSR.
This flag is automatically cleared when EEFC_FSR is read or EEFC_FCR is written.
• FLERR: Flash Error Status (cleared when a programming operation starts)
0: No Flash memory error occurred at the end of programming (EraseVerify or WriteVerify test has passed).
1: A Flash memory error occurred at the end of program ming (EraseVerify or WriteVerify test has failed).
31 30 29 28 27 26 25 24
––––––––
23 22 21 20 19 18 17 16
––––––––
15 14 13 12 11 10 9 8
––––––––
76543210
––––FLERRFLOCKEFCMDEFRDY
375
SAM4S Series [DATASHEET]
Atmel-11100K-ATARM-SAM4S-Datasheet_09-Jun-15
20.5.4 EEFC Flash Result Register
Name: EEFC_FRR
Address: 0x400E0A0C (0), 0x400E0C0C (1)
Access: Read-only
• FVALUE: Flash Result Value
The result of a Flash command is returned in this register. If the size of the result is greater than 32 bits, the next resulting
value is accessible at the next register read.
31 30 29 28 27 26 25 24
FVALUE
23 22 21 20 19 18 17 16
FVALUE
15 14 13 12 11 10 9 8
FVALUE
76543210
FVALUE
SAM4S Series [DATASHEET]
Atmel-11100K-ATARM-SAM4S-Datasheet_09-Jun-15
376
21. Fast Flash Programming Interface (FFPI)
21.1 Description
The Fast Flash Programming Interface (FFPI) provides parallel high-volume programming using a standard gang
programmer. The parallel interface is fully handshaked and the device is conside red to be a standard EEPROM .
Additionally, the parallel protocol offers an optimized access to all the embedded Flash functionalities.
Although the Fast Flash Programming mode is a dedicated mode for high volu me programming, this mode is not
designed for in-situ programming.
21.2 Embedded Characteristics
Programming Mode for High-volume Flash Programming Using Gang Programmer
Offers Read and Write Access to the Flash Memory Plane
Enables Control of Lock Bits and General-purpose NVM Bits
Enables Security Bit Activation
Disabled Once Security Bit is Set
Parallel Fast Flash Programming Interface
Provides an 16-bit Parallel Interface to Program the Embedded Flash
Full Handshake Protocol
377
SAM4S Series [DATASHEET]
Atmel-11100K-ATARM-SAM4S-Datasheet_09-Jun-15
21.3 Parallel Fast Flash Programming
21.3.1 Device Configuration
In Fast Flash Programming mode, the device is in a specific test mode. Only a certain set of pins is sign ificant. The
rest of the PIOs are used as inputs with a pull-up. The crystal oscillator is in bypass mode. Other pins must be left
unconnected.
Figure 21-1. 16-bit Parallel Programming Interfa ce
NCMD PGMNCMD
RDY PGMRDY
NOE PGMNOE
NVALID PGMNVALID
MODE[3:0] PGMM[3:0]
DATA[15:0] PGMD[15:0]
XIN
TST
VDDIO
PGMEN0
PGMEN1
0 - 50MHz
VDDIO
VDDCORE
VDDIO
VDDPLL
GND
VDDIO
Table 21-1 . Signal Description List
Signal Name Function Type Active
Level Comments
Power
VDDIO I/O Lines Power Supply Power – –
VDDCORE Core Power Supply Pow er – –
VDDPLL PLL Power Supply Power – –
GND Ground Ground – –
Clocks
XIN
Main Clock Input.
This input can be tied to GND. In this
case, the device is clocked by the internal
RC oscillator.
Input – 32 KHz to 50 MHz
Test
TST Test Mode Select Input High M ust be connected to VDDIO
PGMEN0 Test Mode Select Input High Must be connected to VDDIO
PGMEN1 Test Mode Select Input High Must be connected to VDDIO
PGMEN2 Test Mode Select Input Low Must be connected to GND
PIO
PGMNCMD Valid command available Input Low Pulle d-up input at reset
SAM4S Series [DATASHEET]
Atmel-11100K-ATARM-SAM4S-Datasheet_09-Jun-15
378
21.3.2 Signal Names
Depending on the MO DE settings, DATA is latched in different internal registers.
When MODE is equal to CMDE, then a new command (strobed on DATA[15:0] signals) is stored in the command
register.
PGMRDY 0: Device is busy
1: Device is ready for a new command Output High Pulled-up input at reset
PGMNOE Output Enable (active high) Input Low Pulled-up input at reset
PGMNVALID 0: DATA[15:0] is in input mode
1: DATA[15:0] is in output mode Output Low Pulled-up input at reset
PGMM[3:0] Specifies DATA type (see Table 21-2) Input – Pulled-up input at reset
PGMD[15:0] Bi -directional data bus Input/Output – Pulled-up input at reset
Table 21-1 . Signal Description List (Continued)
Signal Name Function Type Active
Level Comments
Table 21-2. Mode Coding
MODE[3:0] Symbol Data
0000 CMDE Command Register
0001 ADDR0 Address Register LSBs
0010 ADDR1 –
0011 ADDR2 –
0100 ADDR3 Address Register MSBs
0101 DATA Data Register
Default IDLE No register
Table 21-3. Command Bit Coding
DATA[15:0] Symbol Command Executed
0x0011 READ Read Flash
0x0012 WP Write Page Flash
0x0022 WPL Write Page and Lock Flash
0x0032 EWP Erase Page and Write Page
0x0042 EWPL Erase Page and Write Page then Lock
0x0013 EA Erase All
0x0014 SLB Set Lock Bit
0x0024 CLB Clear Lock Bit
0x0015 GLB Get Lock Bit
0x0034 SGPB Set General Purpose NVM bit
0x0044 CGPB Clear General Purpose NVM bit
0x0025 GGPB Get General Purpose NVM bit
0x0054 SSE Set Security Bit
379
SAM4S Series [DATASHEET]
Atmel-11100K-ATARM-SAM4S-Datasheet_09-Jun-15
21.3.3 Entering Programming Mode
The following algorithm puts the device in Parallel Programming mode:
1. Apply the supplies as described in Table 21-1.
2. Apply XIN clock within tPOR_RESET if an external clock is available.
3. Wait for tPOR_RESET
4. Start a read or write ha ndshaking.
Note: After reset, the device is clocked by the internal RC oscillator. Before clearing RDY signal, if an external clock ( > 32
kHz) is connected to XIN, then the device switches on the external clock. Else, XIN input is not considered. A hi gher
frequency on XIN speeds up the programmer handshake.
21.3.4 Programmer Handshaking
An handshake is de fined for read and writ e operations. When th e device is ready to start a new oper ation (RDY
signal set), the programmer starts the handshake by clearing the NCMD signal. The handshaking is achieved once
NCMD signal is high and RDY is high.
21.3.4.1 Write Handshaking
For details on the write handshaking sequence, refer to Figure 21-2 and Table 21-4.
Figure 21-2. Parallel Programming Timing, Write Sequence
0x0035 GSE Get Security Bit
0x001F WRAM Write Memory
0x001E GVE Get Version
Table 21-3. Command Bit Coding (Continued)
DATA[15:0] Symbol Command Executed
NCMD
RDY
NOE
NVALID
DATA[15:0]
MODE[3:0]
1
2
3
4
5
Table 21-4. Write Handshake
Step Programmer Action Device Action Data I/O
1 Sets MODE and DATA signals Waits for NCMD low Input
2 Clears NCMD signal Latches MODE and DATA Input
3 Waits for RDY low Clears RDY signal Input
SAM4S Series [DATASHEET]
Atmel-11100K-ATARM-SAM4S-Datasheet_09-Jun-15
380
21.3.4.2 Read Handshaking
For details on the read handshaking sequence, refer to Figure 21-3 and Table 21-5.
Figure 21-3. Parallel Programming Timin g, Read Sequence
4 Releases MODE and DATA signals Executes command and polls NCMD high Input
5 Sets NCMD signal Executes command and polls NCMD high Input
6 Waits for RDY high Sets RDY Input
Table 21-4. Write Handshake (Continued)
Step Programmer Action Device Action Data I/O
NCMD
RDY
NOE
NVALID
DATA[15:0]
MODE[3:0]
1
2
3
4
5
6
7
9
8
ADDR
Adress IN Z Data OUT
10
11
XIN
12
13
Table 21-5. Read Handshake
Step Programmer Action Device Action DATA I/O
1 Sets MODE and DATA signals Waits for NCMD low Input
2 Clears NCMD signal Latch MODE and DATA Input
3 Waits for RDY low Clears RDY signal Input
4 Sets DATA signal in tristate Waits for NOE Low Input
5 Clears NOE sign al – Tristate
6 Waits for NVALID low Sets DATA bus in output mode and outputs
the flash contents. Output
7 – Clears NVALID signal Output
8 Reads value on DATA Bus Waits fo r NOE high Output
9 Sets NOE signal Output
10 Waits fo r NVALID high Sets DATA bus in inp ut mode X
11 Sets DATA in output mode Sets NVALID signal Input
12 Sets NCMD signal Wait s for NCMD high Input
13 Waits for RDY high Sets RDY signal Input
381
SAM4S Series [DATASHEET]
Atmel-11100K-ATARM-SAM4S-Datasheet_09-Jun-15
21.3.5 Device Operations
Several commands on the Flash memory are available. These commands are summarized in Table 21-3. Each
command is driven by the programmer through the parallel interface running several read/write handshaking
sequences.
When a new command is executed, the previous one is automatically achieved. Thus, chaining a read command
after a write automatically flushes the load buffer in the Flash.
21.3.5.1 Flash Read Command
This command is used to read the contents of the Flash memory. The read command can start at any valid
address in the memory plane and is optimized for consecutive reads. Read handshaking can be chained; an
internal address buffer is automatically increased.
21.3.5.2 Flash Write Command
This command is used to write the Flash contents.
The Flash memory plane is organized into several pages. Data to be written are stored in a load buffer that
corresponds to a Flash memory page. The load buffer is automatically flushed to the Flash:
before access to any page other than the current one
when a new command is validated (MODE = CMDE)
The Write Page command (WP) is optimized for consecutive writes. Write handshaking can be chained; an
internal address buffer is automatically increased.
Table 21-6. Read Command
Step Handshake Sequence MODE[3:0] DATA[15:0]
1 Write handshaking CMDE READ
2 Write handshaking ADDR0 Memory Address LSB
3 Write handshaking ADDR1 Memory Address
4 Read handshaking DATA *Memory Address++
5 Read handshaking DATA *Memory Address++
... ... ... ...
n Write handshaking ADDR0 Memory Address LSB
n+1 Write handshaking ADDR1 Memory Address
n+2 Read handshaking DATA *Memory Address++
n+3 Read handshaking DATA *Memory Address++
... ... ... ...
Table 21-7. Write Command
Step Handshake Sequence MODE[3:0] DATA[15:0]
1 Write handshaking CMDE WP or WPL or EWP or EWPL
2 Write handshaking ADDR0 Memory Address LSB
3 Write handshaking ADDR1 Memory Address
4 Write handshaking DATA *Me mor y Address++
5 Write handshaking DATA *Me mor y Address++
... ... ... ...
n Write handshaking ADDR0 Memory Address LSB
SAM4S Series [DATASHEET]
Atmel-11100K-ATARM-SAM4S-Datasheet_09-Jun-15
382
The Flash command Write Page and Lock (WPL) is equivalent to the Flash Write Command. However, the lock
bit is automatically set at the end of the Flash write op eration. As a lock region is composed of several pages, the
programmer writes to the first pages of the lock region using Flash write commands and writes to the last page of
the lock region using a Flash write and lock command.
The Flash command Erase Page and Write (EWP) is equivalent to the Flash Write Command. However, before
programming the load buffer, the page is eras ed.
The Flash command Erase Page and Write the Lock (EWPL) combin es EWP and WPL commands.
21.3.5.3 Flash Full Erase Command
This command is used to erase the Flash memory planes.
All lock regions must be unlocked before the Full Erase command by using the CLB command. Otherwise, the
erase command is aborted and no page is erased.
21.3.5.4 Flash Lock Commands
Lock bits can be set using WPL or EWPL commands. They can also be set by using the Set Lock command
(SLB). With this command, several lock bits can be activated. A Bit Mask is provided as argument to the
command. When bit 0 of the bit mask is set, then the first lock bit is activated.
In the same way, the Clear Lock command (CLB) is used to clear lock bits.
Lock bits can be read using Get Lock Bit command (GLB). The nth lock b it is active when the bit n of the bit mask
is set.
n+1 Write handshaking ADD R1 Memory Address
n+2 Write handshaking DATA *Memory Address++
n+3 Write handshaking DATA *Memory Address++
... ... ... ...
Table 21-7. Write Command (Continued)
Step Handshake Sequence MODE[3:0] DATA[15:0]
Table 21-8. Full Erase Command
Step Handshake Sequence MODE[3:0] DATA[15:0]
1 Write handshaking CMDE EA
2 Write handshaking DATA 0
Table 21-9. Set and Clear Lock Bit Command
Step Handshake Sequence MODE[3:0] DATA[15:0]
1 Write handshaking CMDE SLB or CLB
2 Write handshaking DATA Bit Mask
Table 21-10. Get Lock Bit Command
Step Handshake Sequence MODE[3:0] DATA[15:0]
1 Write handshaking CMDE GLB
2 Read handshaking DATA Lock Bit Mask Status
0 = Lock bit is cleared
1 = Lock bit is set
383
SAM4S Series [DATASHEET]
Atmel-11100K-ATARM-SAM4S-Datasheet_09-Jun-15
21.3.5.5 Flash General-purpose NVM Commands
General-purpose NVM bits (GP NVM bits) can be set using the Set GPNVM command (SGPB). This command
also activates GP NVM bits. A bit mask is provided as argument to the command. When bit 0 of the bit mask is set,
then the first GP NVM bit is activated.
In the same way, the Clear GPNVM command (CGPB) is used to clear general-purpose NVM bits. The general-
purpose NVM bit is deactivated when the corresponding bit in the pattern value is set to 1.
General-purpose NVM bits can be read using the Get GPNVM Bit command (GGPB). The nth GP NVM bit is
active when bit n of the bit mask is set.
21.3.5.6 Flash Security Bit Command
A security bit can be set using the Set Security Bit command (SSE). Once the security bit is active, the Fast Flash
programming is disabled. No other command can be run. An event on the Erase pin can eras e the security bit
once the contents of the Flash have been erased.
Once the security bit is set, it is not possible to access FFPI. The only way to erase the security bit is to erase the
Flash.
In order to erase the Flash, the user must perform the following:
1. Power-off the chip.
2. Power-on the chip with TST = 0.
3. Assert Erase during a period of more than 220 ms.
4. Power-off the chip.
Then it is possible to return to FFPI mode and check that Flash is erased.
21.3.5.7 Memory Write Command
This command is used to perform a write access to any memory location.
Table 21-11. Set/Clear GP NVM Command
Step Handshake Sequence MODE[3:0] DATA[15:0]
1 Write handshaking CMDE SGPB or CGPB
2 Write handshaking DATA GP NVM bit pattern value
Table 21-12. Get GP NVM Bit Command
Step Handshake Sequence MODE[3:0] DATA[15:0]
1 Write handshaking CMDE GGPB
2 Read handshaking DATA GP NVM Bit Mask Status
0 = GP NVM bit is cleared
1 = GP NVM bit is set
Table 21-13. Set Security Bit Command
Step Handshake Sequence MODE[3:0] DATA[15:0]
1 Write handshaking CMDE SSE
2 Write handshaking DATA 0
SAM4S Series [DATASHEET]
Atmel-11100K-ATARM-SAM4S-Datasheet_09-Jun-15
384
The Memory Write command (WRAM) is optimized for consecutive writes. Write handshaking can be chained; an
internal address buffer is automatically increased.
21.3.5.8 Get Version Command
The Get Version (GVE) command retrieves the ver sio n of the F FPI inte rfa ce .
Table 21-14. Write Comma nd
Step Handshake Sequence MODE[3:0] DATA[15:0]
1 Write handshaking CMDE WRAM
2 Write handshaking ADDR0 Memory Address LSB
3 Write handshaking ADDR1 Memory Address
4 Write handshaking DATA *Me mor y Address++
5 Write handshaking DATA *Me mor y Address++
... ... ... ...
n Write handshaking ADDR0 Memory Address LSB
n+1 Write handshaking ADD R1 Memory Address
n+2 Write handshaking DATA *Memory Address++
n+3 Write handshaking DATA *Memory Address++
... ... ... ...
Table 21-15. Get Version Comm and
Step Handshake Sequence MODE[3:0] DATA[15:0]
1 Write handshaking CMDE GVE
2 Read handshaking DATA Version
385
SAM4S Series [DATASHEET]
Atmel-11100K-ATARM-SAM4S-Datasheet_09-Jun-15
22. Cortex-M Cache Controller (CMCC)
22.1 Description
The Cortex-M Cache Controller (CMCC) is a 4-Way set associative unified cache controller. It integrates a
controller, a tag directory, data memory, metadata memory and a configuration interface.
22.2 Embedded Characteristics
Physically addressed and physically tagged
L1 data cache set to 2 Kbytes
L1 cache line size set to 16 Bytes
L1 cache integrates 32-bit bus master interface
Unified direct mapped cache architecture
Unified 4-Way set associative cache architecture
Write through cache operations, read allocate
Round Robin victim selection policy
Event Monitoring, with one programmable 32-bit counter
Configuration registers accessible through Cortex-M Private Peripheral Bus (PPB)
Cache interface includes cache maintenance operations registers
SAM4S Series [DATASHEET]
Atmel-11100K-ATARM-SAM4S-Datasheet_09-Jun-15
386
22.3 Block Diagram
Figure 22-1. Block Diagram
22.4 Functional Description
22.4.1 Cache Operation
On reset, the cache controller data entries are all invalidated and the cache is disabled. The cache is transparent
to processor operations. The cache controller is activated with its configuration registers. The configuration
interface is memory-mapped in the private peripheral bus.
Use the following sequence to enable the cache cont roller:
1. Verify that the cache con troller is disabled by re ading the v a lue of the CSTS ( Cache Contr oller Stat us) bit
of the Status r egister (CMCC_SR).
2. Enable the cache controller by writing a one to the CEN (Cache Enable) bit of the Control register
(CMCC_CTRL).
22.4.2 Cache Maintenance
If the contents seen by the cache have chan ged, the user must invalidate the cache entries. This can be done line-
by-line or for all cache entries.
Cache
Controller
META INFO RAM
DATA RAM
TAG RAM
RAM
Interface
Cortex-M Interface
Memory Interface
Registers
Interface
Cortex-M
PPB
Cortex-M Memory Interface Bus
System Memory Bus
387
SAM4S Series [DATASHEET]
Atmel-11100K-ATARM-SAM4S-Datasheet_09-Jun-15
22.4.2.1 Cache Invalidate-by-Line Operation
When an invalidate-by-line command is issued, the cache controller resets the valid bit info rmation of the decoded
cache line. As the line is no longer valid, the replacement counte r points to that line.
Use the following sequence to invalidate one line of cache:
1. Dis able the cache controller by clearing the CEN bit of CMCC_CTRL.
2. Check the CSTS bit of CMCC_SR to verify that the cache is successfully disa b l ed.
3. Perform an invalidate-by-line by configuring the bits INDEX and WAY in the Maintenance Register 1
(CMCC_MAINT1).
4. Enable the cache controller by writing a one the CEN bit of the CMCC_CTRL.
22.4.2.2 Cache Invalidate All Operation
To invalidate all cache entries, write a one to the INVALL bit of the Maintenance Register 0 (CMCC_MAINT0).
22.4.3 Cache Performance Monitoring
The Cortex-M ca che co ntro ller include s a prog ram mab le 32- bit monito r coun ter. The monit or can be configu red to
count the number of clock cycles, the number of data hits or the number of instruction hits.
Use the following sequence to activate the counter:
1. Conf igure the monitor counter by writing to the MODE field of the Monitor Configuration register
(CMCC_MCFG).
2. Enable the counter by writing a one to the MENABLE bit of the Monitor Enable register (CMCC_MEN).
3. If required, clear the counter by writing a one to the SWRST bit of the Monitor Control register
(CMCC_MCTRL).
4. Check the value of the monitor counter by reading the EVENT_CNT field of the CMCC_MSR.
SAM4S Series [DATASHEET]
Atmel-11100K-ATARM-SAM4S-Datasheet_09-Jun-15
388
22.5 Cortex-M Cache Controller (CMCC) User Interface
Table 22-1 . Register Mapping
Offset Register Name Access Reset
0x00 Cache Controller Ty pe Register CMCC_TYPE Read-only –
0x04 Cache Controller Configuration Register CMCC_CFG Read/Write 0x00000000
0x08 Cache Controller Control Register CMCC_CTRL Write-only –
0x0C Cache Control ler Status Regi ster CMCC_SR Read-only 0x00000001
0x10–0x1C Reserved – – –
0x20 Cache Controller Maintenance Register 0 CMCC_MAINT0 Write-only –
0x24 Cache Controller Maintenance Register 1 CMCC_MAINT1 Write-only –
0x28 Cache Controller Monitor Configuration Register CMCC_MCFG Read/Write 0x00000000
0x2C Cache Control ler Monitor Enable Register CMCC_MEN Read/Write 0x00000000
0x30 Cache Controller Monitor Control Register CMCC_MCTRL Write-only –
0x34 Cache Controller Monitor Status Register CMCC_MSR Read-only 0x00000000
0x38–0xFC Reserved – – –
389
SAM4S Series [DATASHEET]
Atmel-11100K-ATARM-SAM4S-Datasheet_09-Jun-15
22.5.1 Cache Controller Type Register
Name: CMCC_TYPE
Address: 0x4007C000
Access: Read-only
• AP: Access Port Access Allowed
0: Access Port Access is disabled.
1: Access Port Access is enabled.
• GCLK: Dynamic Clock Gating Supported
0: Cache controller does not support clock gating.
1: Cache controller uses dynamic clock gating.
• RANDP: Random Selection Policy Supported
0: Random victim selection is not supported.
1: Random victim selection is supported.
• LRUP: Least Recently Used Policy Supported
0: Least Recently Used Policy is not supported.
1: Least Recently Used Policy is supported.
• RRP: Random Selection Policy Supported
0: Random Selection Policy is not supported.
1: Random Selection Policy is supported.
• WAYNUM: Number of Ways
31 30 29 28 27 26 25 24
––––––––
23 22 21 20 19 18 17 16
––––––––
15 14 13 12 11 10 9 8
–CLSIZECSIZE
76543210
LCKDOWN WAYNUM RRP LRUP RANDP GCLK AP
Value Name Description
0 DMAPPED Direct Mapped Cache
1 ARCH2WAY 2-way set associ ative
2 ARCH4WAY 4-way set associ ative
3 ARCH8WAY 8-way set associ ative
SAM4S Series [DATASHEET]
Atmel-11100K-ATARM-SAM4S-Datasheet_09-Jun-15
390
• LCKDOWN: Lockdown Supported
0: Lockdown is not supported.
1: Lockdown is supported.
• CSIZE: Data Cache Size
• CLSIZE: Cache LIne Size
Value Name Description
0 CSIZE_1KB Data cache size is 1 Kbyte
1 CSIZE_2KB Data cache size is 2 Kbytes
2 CSIZE_4KB Data cache size is 4 Kbytes
3 CSIZE_8KB Data cache size is 8 Kbytes
Value Name Description
0 CLSIZ E_1KB Cache line size is 4 bytes
1 CLSIZ E_2KB Cache line size is 8 bytes
2 CLSIZE_4KB Cache line size is 16 bytes
3 CLSIZE_8KB Cache line size is 32 bytes
391
SAM4S Series [DATASHEET]
Atmel-11100K-ATARM-SAM4S-Datasheet_09-Jun-15
22.5.2 Cache Controller Configuration Register
Name: CMCC_CFG
Address: 0x4007C004
Access: Read/Write
• GCLKDIS: Disable Clock Gating
0: Clock gating is activated.
1: Clock gating is disabled.
31 30 29 28 27 26 25 24
––––––––
23 22 21 20 19 18 17 16
––––––––
15 14 13 12 11 10 9 8
––––––––
76543210
–––––––GCLKDIS
SAM4S Series [DATASHEET]
Atmel-11100K-ATARM-SAM4S-Datasheet_09-Jun-15
392
22.5.3 Cache Controller Control Register
Name: CMCC_CTRL
Address: 0x4007C008
Access: Write-only
• CEN: Cache Controller Enable
0: The cache controller is disabled.
1: The cache controller is enabled.
31 30 29 28 27 26 25 24
––––––––
23 22 21 20 19 18 17 16
––––––––
15 14 13 12 11 10 9 8
––––––––
76543210
–––––––CEN
393
SAM4S Series [DATASHEET]
Atmel-11100K-ATARM-SAM4S-Datasheet_09-Jun-15
22.5.4 Cache Controller Status Register
Name: CMCC_SR
Address: 0x4007C00C
Access: Read-only
• CSTS: Cache Controller Status
0: The cache controller is disabled.
1: The cache controller is enabled.
31 30 29 28 27 26 25 24
––––––––
23 22 21 20 19 18 17 16
––––––––
15 14 13 12 11 10 9 8
––––––––
76543210
–––––––CSTS
SAM4S Series [DATASHEET]
Atmel-11100K-ATARM-SAM4S-Datasheet_09-Jun-15
394
22.5.5 Cache Controller Maintenance Register 0
Name: CMCC_MAINT0
Address: 0x4007C020
Access: Write-only
• INVALL: Cache Controller Invalidate All
0: No effect.
1: All cache entries are invalidated.
31 30 29 28 27 26 25 24
––––––––
23 22 21 20 19 18 17 16
––––––––
15 14 13 12 11 10 9 8
––––––––
76543210
–––––––INVALL
395
SAM4S Series [DATASHEET]
Atmel-11100K-ATARM-SAM4S-Datasheet_09-Jun-15
22.5.6 Cache Controller Maintenance Register 1
Name: CMCC_MAINT1
Address: 0x4007C024
Access: Write-only
• INDEX: Invalidate Index
This field indicates the cache line that is being invalidated.
The size of the INDEX field depends on the cache size:
For example:
– for 2 Kbytes: 5 bits
– for 4 Kbytes: 6 bits
– for 8 Kbytes: 7 bits
• WAY: Invalidate Way
31 30 29 28 27 26 25 24
WAY ––––––
23 22 21 20 19 18 17 16
––––––––
15 14 13 12 11 10 9 8
–––––––INDEX
76543210
INDEX ––––
Value Name Description
0 WAY0 Way 0 is selection for index invalidation
1 WAY1 Way 1 is selection for index invalidation
2 WAY2 Way 2 is selection for index invalidation
3 WAY3 Way 3 is selection for index invalidation
SAM4S Series [DATASHEET]
Atmel-11100K-ATARM-SAM4S-Datasheet_09-Jun-15
396
22.5.7 Cache Controller Monitor Configuration Register
Name: CMCC_MCFG
Address: 0x4007C028
Access: Read/Write
• MODE: Cache Controller Monitor Counter Mode
31 30 29 28 27 26 25 24
––––––––
23 22 21 20 19 18 17 16
––––––––
15 14 13 12 11 10 9 8
––––––––
76543210
–––––– MODE
Value Name Description
0 CYCLE_COUNT Cycle counter
1 IHIT_COUNT Instruction hit counter
2 DHIT_COUNT Data hit counter
397
SAM4S Series [DATASHEET]
Atmel-11100K-ATARM-SAM4S-Datasheet_09-Jun-15
22.5.8 Cache Controller Monitor Enable Register
Name: CMCC_MEN
Address: 0x4007C02C
Access: Read/Write
• MENABLE: Cache Controller Monitor Enable
0: The monitor counter is disabled.
1: The monitor counter is enabled.
31 30 29 28 27 26 25 24
––––––––
23 22 21 20 19 18 17 16
––––––––
15 14 13 12 11 10 9 8
––––––––
76543210
–––––––MENABLE
SAM4S Series [DATASHEET]
Atmel-11100K-ATARM-SAM4S-Datasheet_09-Jun-15
398
22.5.9 Cache Controller Monitor Control Register
Name: CMCC_MCTRL
Address: 0x4007C030
Access: Write-only
• SWRST: Monitor
0: No effect.
1: Resets the event counter register.
31 30 29 28 27 26 25 24
––––––––
23 22 21 20 19 18 17 16
––––––––
15 14 13 12 11 10 9 8
––––––––
76543210
–––––––SWRST
399
SAM4S Series [DATASHEET]
Atmel-11100K-ATARM-SAM4S-Datasheet_09-Jun-15
22.5.10 Cache Controller Monitor Status Register
Name: CMCC_MSR
Address: 0x4007C034
Access: Read-only
• EVENT_CNT: Monitor Event Counter
31 30 29 28 27 26 25 24
EVENT_CNT
23 22 21 20 19 18 17 16
EVENT_CNT
15 14 13 12 11 10 9 8
EVENT_CNT
76543210
EVENT_CNT
SAM4S Series [DATASHEET]
Atmel-11100K-ATARM-SAM4S-Datasheet_09-Jun-15
400
23. Cyclic Redundancy Check Calculation Unit (CRCCU)
23.1 Description
The Cyclic Redundancy Check Calculation Unit (CRCCU) has its own DMA which functions as a Master with the
Bus Matrix. Three different polynomials are av ailable: CCITT802.3, CASTAGNOLI and CCITT16.
The CRCCU is designed to perform data integrity checks of off-/on-chip memories as a background task without
CPU intervention.
23.2 Embedded Characteristics
Data Integrity Check of Off-/On-Chip Memories
Background Task Without CPU Intervention
Performs Cyclic Redundancy Check (CRC) Operation on Programmable Memory Area
Programmable Bus Burden
Note: The CRCCU is designed to verify data integrity of off-/on-chip memories, thus the CRC must be generated and verified
by the CRCCU. The CRCCU performs the CRC from LSB to MSB. If the CRC has been performed with the same
polynomial by another device, a bit-reverse must be done on each byte be fore using the CRCCU.
401
SAM4S Series [DATASHEET]
Atmel-11100K-ATARM-SAM4S-Datasheet_09-Jun-15
23.3 CRCCU Block Diagram
Figure 23-1. Block Diagram
AHB-Layer
Context FSM
AHB Interface
Host
Interface
APB Bus
AHB SRAM
TR_ADDR
HRDATA
HTRANS
HSIZE
TR_CRC
Flash
External
Bus Interface
SAM4S Series [DATASHEET]
Atmel-11100K-ATARM-SAM4S-Datasheet_09-Jun-15
402
23.4 Product Dependencies
23.4.1 Power Management
The CRCCU is clocked thro ugh the Power Man agement Cont roller (PMC), the pr ogrammer must first configu re the
CRCCU in the PMC to enable the CRCCU clock.
23.4.2 Interrupt Source
The CRCCU has an interrupt line connected to the Inte rrupt Controller. Handling the CRCCU interrupt requires
programming the Interrupt Controller before configuring the CRCCU.
403
SAM4S Series [DATASHEET]
Atmel-11100K-ATARM-SAM4S-Datasheet_09-Jun-15
23.5 CRCCU Functional Description
23.5.1 CRC Calculation Unit
The CRCCU integrates a d edicated Cycli c Re dundancy Check (C RC) engine. Whe n configured a nd activate d, this
CRC engine performs a checksum computation on a memory area. CRC computation is performed from the LSB
to MSB. Three differe nt polynomials are available: CC ITT802.3, CASTAGNOLI and CCITT16 (see field description
“PTYPE: Primitive Polynomial” in Section 23.7.10 “CRCCU Mode Register” for details).
23.5.2 CRC Calculation Unit Operation
The CRCCU has a DMA controller that supports programmable CRC memory checks. When enabled, the DMA
channel reads a programmable amount of data and computes CRC on the fly.
The CRCCU is controlled by two registers, TR_ADDR and TR_CTRL, which need to be mapped in the internal
SRAM. The addresses of these two registers are pointed to by the CRCCU_DSCR.
TR_ADDR defines the start address of memory area targeted for CRC calculation.
TR_CTRL defines the buffer transfer size, the tra nsfer width (byte , halfword, word) an d the transfer-com pleted
interrupt enab le .
To start the CRCCU, set the CRC enable bit (ENABLE) and configure the mode of operation in the CRCCU Mode
Register (CRCCU_MR), then configure the Transfer Control Registers and finally, set the DMA enable bit
(DMAEN) in the CRCCU DMA Enable Register (CRCCU_DMA_EN).
When the CRCCU is enabled, the CRCCU reads the predefined amount of data (defined in TR_CTRL) located
from TR_ADDR start address and computes the checksum.
The CRCCU_SR contains the temporary CRC value.
The BTSIZE field located in the TR_CTRL register (lo cated in memory), is automatically decr emented if its value is
different from zero. Once the value of the BTSIZE field is equal to zero, the CRCCU is disabled by hardware. In
this case, the relevant CRCCU DMA Status Register bit DMASR is automatically cleared.
If the COMPARE field of the CR CCU_MR is set to true, the TR_C RC (Transfer Reference Register) is compared
with the last CRC computed. If a mismatch occurs, an error flag is set and an interrupt is raised (if unmasked).
The CRCCU accesses the memory by single access (TRWIDTH size) in order not to limit the bandwidth usage of
the system, but the DIVIDER field of the CRCCU Mode Register can be used to lower it by dividing the frequency
of the single accesses.
The CRCCU scrolls the defined memory area using ascending addresses.
In order to compute the CRC for a memory size la rger than 256 Kbytes or for non-contiguous memory area, it is
possible to re-enable the CRCCU on the new memory area and the CRC will be updated accordingly. Use the
RESET field of the CRCCU_CR to reset the CRCCU Status Register to its default value (0xFFFFFFFF).
Table 23-1. CRCCU Descriptor Memory Mapping
SRAM Memory
CRCCU_DSCR+0x0 ----> TR_ADDR
CRCCU_DSCR+0x4 ----> TR_CTRL
CRCCU_DSCR+0x8 ----> Reserved
CRCCU_DSCR+0xC ----> Reserved
CRCCU_DSCR+0x10 ----> TR_CRC
SAM4S Series [DATASHEET]
Atmel-11100K-ATARM-SAM4S-Datasheet_09-Jun-15
404
23.6 Transfer Control Registers Memory Mapping
Note: These registers are memory mapped.
Table 23-2. Transfer Control Register Memory Mapping
Offset Register Name Access Reset
CRCCU_DSCR + 0x0 CRCCU Transfer Address Register TR_ADDR Read/Write 0x00000000
CRCCU_DSCR + 0x4 CRCCU Transfer Control Register TR_CTRL Read/Write 0x00000000
CRCCU_DSCR + 0xC–0x10 Reserved – – –
CRCCU_DSCR+0x10 CRCCU Transfer Reference Register TR_CRC Read/Write 0x00000000
405
SAM4S Series [DATASHEET]
Atmel-11100K-ATARM-SAM4S-Datasheet_09-Jun-15
23.6.1 Transfer Address Register
Name: TR_ADDR
Access: Read/Write
• ADDR: Transfer Address
31 30 29 28 27 26 25 24
ADDR
23 22 21 20 19 18 17 16
ADDR
15 14 13 12 11 10 9 8
ADDR
76543210
ADDR
SAM4S Series [DATASHEET]
Atmel-11100K-ATARM-SAM4S-Datasheet_09-Jun-15
406
23.6.2 Transfer Control Register
Name: TR_CTRL
Access: Read/Write
• BTSIZE: Buffer Transfer Size
• TRWIDTH: Transfer Width Register
• IEN: Context Done Interrupt Enable (Active Low)
0: Bit DMAISR of CRCCU_DMA_ISR is set at the end of the current descriptor transfer.
1: Bit DMAISR of CRCCU_DMA_ISR remains cleared.
31 30 29 28 27 26 25 24
––––IEN– TRWIDTH
23 22 21 20 19 18 17 16
––––––––
15 14 13 12 11 10 9 8
BTSIZE
76543210
BTSIZE
Value Name Description
0 BYTE The data size is 8-bit
1 HALFWORD Th e data size is 16-bit
2 WORD The data size is 32-bit
407
SAM4S Series [DATASHEET]
Atmel-11100K-ATARM-SAM4S-Datasheet_09-Jun-15
23.6.3 Transfer Reference Register
Name: TR_CRC
Access: Read/Write
• REFCRC: Reference CRC
When Compare mode is enabled, the checksum is compared with this field.
31 30 29 28 27 26 25 24
REFCRC
23 22 21 20 19 18 17 16
REFCRC
15 14 13 12 11 10 9 8
REFCRC
76543210
REFCRC
SAM4S Series [DATASHEET]
Atmel-11100K-ATARM-SAM4S-Datasheet_09-Jun-15
408
23.7 Cyclic Redundancy Check Calculation Unit (CRCCU) User Interface
Table 23-3 . Register Mapping
Offset Register Name Access Reset
0x000 CRCCU Descriptor Base Register CRCCU_DSCR Read/Write 0x00000000
0x004 Reserved – – –
0x008 CRCCU DMA Ena ble Register CRCCU_DMA_EN Write-only –
0x00C CRCCU DMA Disable Register CRCCU_DMA_DIS Write-only –
0x010 CRCCU DMA Sta tu s Re gister CRCCU_DMA_SR Read-only 0x00000000
0x014 CRCCU DMA Interrupt En able Register CRCCU_DMA_IER Write-only –
0x018 CRCCU DMA Interrupt Disable Register CRCCU_DMA_IDR Write-only –
0x001C CRC CU DMA Interrupt Mask Register CRCCU_DMA_IMR Read-only 0x00000000
0x020 CRCCU DMA Interrupt Status Register CRCCU_DMA_ISR Read-only 0x00000000
0x024–0x030 Reserved – – –
0x034 CRCCU Control Register CRCCU_CR Write-only –
0x038 CRCCU Mode Register CRCCU_MR Read/Write 0x00000000
0x03C CRCCU Status Register CRCCU_SR Read-only 0xFFFFFFFF
0x040 CRCCU Interrup t Ena ble Register CRCCU_IER Write-only –
0x044 CRCCU Interrup t Disa ble Register CRCCU_IDR Write-only –
0x048 CRCCU Interrupt Mask Register CRCCU_IMR Read-only 0x00000000
0x004C CRC CU Interrupt Status Register CRCCU_ISR Read-only 0x00000000
0x050–0x0FC Reserved – – –
409
SAM4S Series [DATASHEET]
Atmel-11100K-ATARM-SAM4S-Datasheet_09-Jun-15
23.7.1 CRCCU Descriptor Base Address Register
Name: CRCCU_DSCR
Address: 0x40044000
Access: Read/Write
• DSCR: Descriptor Base Address
DSCR needs to be aligned with 512-byte boundaries .
31 30 29 28 27 26 25 24
DSCR
23 22 21 20 19 18 17 16
DSCR
15 14 13 12 11 10 9 8
DSCR –
76543210
––––––––
SAM4S Series [DATASHEET]
Atmel-11100K-ATARM-SAM4S-Datasheet_09-Jun-15
410
23.7.2 CRCCU DMA Enable Register
Name: CRCCU_DMA_EN
Address: 0x40044008
Access: Write-only
• DMAEN: DMA Enable
0: No effect
1: Enable CRCCU DMA channel
31 30 29 28 27 26 25 24
––––––––
23 22 21 20 19 18 17 16
––––––––
15 14 13 12 11 10 9 8
––––––––
76543210
–––––––DMAEN
411
SAM4S Series [DATASHEET]
Atmel-11100K-ATARM-SAM4S-Datasheet_09-Jun-15
23.7.3 CRCCU DMA Disable Register
Name: CRCCU_DMA_DIS
Address: 0x4004400C
Access: Write-only
• DMADIS: DMA Disable
0: No effect
1: Disable CRCCU DMA channel
31 30 29 28 27 26 25 24
––––––––
23 22 21 20 19 18 17 16
––––––––
15 14 13 12 11 10 9 8
––––––––
76543210
–––––––DMADIS
SAM4S Series [DATASHEET]
Atmel-11100K-ATARM-SAM4S-Datasheet_09-Jun-15
412
23.7.4 CRCCU DMA Status Register
Name: CRCCU_DMA_SR
Address: 0x40044010
Access: Read-only
• DMASR: DMA Status
0: DMA channel disabled
1: DMA channel enabled
31 30 29 28 27 26 25 24
––––––––
23 22 21 20 19 18 17 16
––––––––
15 14 13 12 11 10 9 8
––––––––
76543210
–––––––DMASR
413
SAM4S Series [DATASHEET]
Atmel-11100K-ATARM-SAM4S-Datasheet_09-Jun-15
23.7.5 CRCCU DMA Interrupt Enable Register
Name: CRCCU_DMA_IER
Address: 0x40044014
Access: Write-only
• DMAIER: Interrupt Enable
0: No effect
1: Enable interrupt
31 30 29 28 27 26 25 24
––––––––
23 22 21 20 19 18 17 16
––––––––
15 14 13 12 11 10 9 8
––––––––
76543210
–––––––DMAIER
SAM4S Series [DATASHEET]
Atmel-11100K-ATARM-SAM4S-Datasheet_09-Jun-15
414
23.7.6 CRCCU DMA Interrupt Disable Register
Name: CRCCU_DMA_IDR
Address: 0x40044018
Access: Write-only
• DMAIDR: Interrupt Disable
0: No effect
1: Disable interrupt
31 30 29 28 27 26 25 24
––––––––
23 22 21 20 19 18 17 16
––––––––
15 14 13 12 11 10 9 8
––––––––
76543210
–––––––DMAIDR
415
SAM4S Series [DATASHEET]
Atmel-11100K-ATARM-SAM4S-Datasheet_09-Jun-15
23.7.7 CRCCU DMA Interrupt Mask Register
Name: CRCCU_DMA_IMR
Address: 0x4004401C
Access: Read-only
• DMAIMR: Interrupt Mask
0: Buffer Transfer Completed interrupt disabled
1: Buffer Transfer Completed interrupt enabled
31 30 29 28 27 26 25 24
––––––––
23 22 21 20 19 18 17 16
––––––––
15 14 13 12 11 10 9 8
––––––––
76543210
–––––––DMAIMR
SAM4S Series [DATASHEET]
Atmel-11100K-ATARM-SAM4S-Datasheet_09-Jun-15
416
23.7.8 CRCCU DMA Interrupt Status Register
Name: CRCCU_DMA_ISR
Address: 0x40044020
Access: Read-only
• DMAISR: Interrupt Status
0: DMA buffer transfer has not yet started or transfer still in progress
1: DMA buffer transfer has terminated. This flag is reset after read.
31 30 29 28 27 26 25 24
––––––––
23 22 21 20 19 18 17 16
––––––––
15 14 13 12 11 10 9 8
––––––––
76543210
–––––––DMAISR
417
SAM4S Series [DATASHEET]
Atmel-11100K-ATARM-SAM4S-Datasheet_09-Jun-15
23.7.9 CRCCU Control Register
Name: CRCCU_CR
Address: 0x40044034
Access: Write-only
• RESET: CRC Computation Reset
0: No effect
1: Sets the CRCCU_SR to 0xFFFFFFFF
31 30 29 28 27 26 25 24
––––––––
23 22 21 20 19 18 17 16
––––––––
15 14 13 12 11 10 9 8
––––––––
76543210
–––––––RESET
SAM4S Series [DATASHEET]
Atmel-11100K-ATARM-SAM4S-Datasheet_09-Jun-15
418
23.7.10 CRCCU Mode Register
Name: CRCCU_MR
Address: 0x40044038
Access: Read/Write
• ENABLE: CRC Enable
Always write a 1 to this bit.
• COMPARE: CRC Compare
If set to one, this bit indicates that the CRCCU DMA will compare the CRC computed on the data stream with the value
stored in the TR_CRC reference register. If a mismatch occurs, the ERRISR bit in the CRCCU_ISR is set.
• PTYPE: Primitive Polynomial
• DIVIDER: Request Divider
CRCCU DMA performs successive transfers. It is possible to reduce the bandwidth drained by the CRCCU DMA by pro-
gramming the DIVIDER field. The transfer request frequency is divided by 2^(DIVIDER+1).
31 30 29 28 27 26 25 24
––––––––
23 22 21 20 19 18 17 16
––––––––
15 14 13 12 11 10 9 8
––––––––
76543210
DIVIDER PTYPE COMPARE ENABLE
Value Name Description
0 CCITT8023 Polynom 0x04C11DB7
1 CASTAGNOLI Polynom 0x1EDC6F41
2 CCITT16 Polynom 0x102 1
419
SAM4S Series [DATASHEET]
Atmel-11100K-ATARM-SAM4S-Datasheet_09-Jun-15
23.7.11 CRCCU Status Register
Name: CRCCU_SR
Address: 0x4004403C
Access: Read-only
• CRC: Cyclic Redundancy Check Value
This register can not be read if the COMPARE bit in the CRCCU_MR is set to true.
31 30 29 28 27 26 25 24
CRC
23 22 21 20 19 18 17 16
CRC
15 14 13 12 11 10 9 8
CRC
76543210
CRC
SAM4S Series [DATASHEET]
Atmel-11100K-ATARM-SAM4S-Datasheet_09-Jun-15
420
23.7.12 CRCCU Interrupt Enable Register
Name: CRCCU_IER
Address: 0x40044040
Access: Write-only
• ERRIER: CRC Error Interrupt Enable
0: No effect
1: Enable interrupt
31 30 29 28 27 26 25 24
––––––––
23 22 21 20 19 18 17 16
––––––––
15 14 13 12 11 10 9 8
––––––––
76543210
–––––––ERRIER
421
SAM4S Series [DATASHEET]
Atmel-11100K-ATARM-SAM4S-Datasheet_09-Jun-15
23.7.13 CRCCU Interrupt Disable Register
Name: CRCCU_IDR
Address: 0x40044044
Access: Write-only
• ERRIDR: CRC Error Interrupt Disable
0: No effect
1: Disable interrupt
31 30 29 28 27 26 25 24
––––––––
23 22 21 20 19 18 17 16
––––––––
15 14 13 12 11 10 9 8
––––––––
76543210
–––––––ERRIDR
SAM4S Series [DATASHEET]
Atmel-11100K-ATARM-SAM4S-Datasheet_09-Jun-15
422
23.7.14 CRCCU Interrupt Mask Register
Name: CRCCU_IMR
Address: 0x40044048
Access: Read-only
• ERRIMR: CRC Error Interrupt Mask
0: Interrupt disabled
1: Interrupt enabled
31 30 29 28 27 26 25 24
––––––––
23 22 21 20 19 18 17 16
––––––––
15 14 13 12 11 10 9 8
––––––––
76543210
–––––––ERRIMR
423
SAM4S Series [DATASHEET]
Atmel-11100K-ATARM-SAM4S-Datasheet_09-Jun-15
23.7.15 CRCCU Interrupt Status Register
Name: CRCCU_ISR
Address: 0x4004404C
Access: Read-only
• ERRISR: CRC Error Interrupt Status
0: Interrupt disabled
1: Interrupt enabled
31 30 29 28 27 26 25 24
––––––––
23 22 21 20 19 18 17 16
––––––––
15 14 13 12 11 10 9 8
––––––––
76543210
–––––––ERRISR
SAM4S Series [DATASHEET]
Atmel-11100K-ATARM-SAM4S-Datasheet_09-Jun-15
424
24. Boot Program
24.1 Description
The SAM-BA Boot Program integrate s an array of programs permitting download and/or upload into the different
memories of the pr od u ct.
24.2 Hardware and Software Constraints
SAM-BA Boot uses the first 2048 bytes of the SRAM for variables and stacks. The remaining available size
can be used for user's code.
USB Requirements:
External Crystal or External Clock(1) with frequency of:
11.289 MHz
12.000 MHz
16.000 MHz
18.432 MHz
UART0 requiremen ts: None
Note: 1. Must be 2500 ppm and 1.2V Square Wa ve Signal.
24.3 Flow Diagram
The Boot Program implements the algorithm in Figure 24-1.
Figure 24-1. Boot Program Algorithm Flow Diagram
The SAM-BA Boot program seeks to detect a source clock either from the embedded main oscillator with external
crystal (main oscillator enabled) or from a supported frequency signal applied to the XIN pin (main oscillator in
Bypass mode).
If a clock is found from the two possible sources above, the boot pro gram checks to verify that the frequency is one
of the supported external frequencies. If the frequency is one of the supported external frequencies, USB
activation is allowed, else (no clock or frequency other than one of the suppor ted external fre quencies), the in ternal
12 MHz RC oscillator is used as main clock and USB clock is not allowed due to frequency drift of the 12 MHz RC
oscillator.
Table 24-1. Pins Driven during Boot Program Execution
Peripheral Pin PIO Line
UART0 URXD0 PA9
UART0 UTXD0 PA10
Device
Setup Character # received
from UART0?
Run SAM-BA Monitor
USB Enumeration
Successful ?
Yes
Run SAM-BA Monitor
Yes
No
No
425
SAM4S Series [DATASHEET]
Atmel-11100K-ATARM-SAM4S-Datasheet_09-Jun-15
24.4 Device Initialization
Initialization follows the steps described below:
1. Stack setup
2. Set up the Embedded Flash Controller
3. External Clock detection (crystal or external clock on XIN)
4. If external crystal or clock with supported frequency, allow USB activation
5. Else, does not allow USB activation and use internal 12 MHz RC oscillator
6. Main oscillator frequency detection if no external clock detected
7. Switch Master Clock on Main Oscillator
8. C variable initialization
9. PLLA setup: PLLA is initialized to generate a 48 MHz clock
10. Disable the Watchdog
11. Initialization of UART0 (115200 bauds, 8, N, 1)
12. Initialization of the USB Device Port (in case USB activation allowed)
13. Wait for one of the following events
1. Check if USB device enumeration has occurred
2. Check if characters have been received in UART0
14. Jump to SAM-BA Monitor (see Section 24.5 ”SAM-BA Monitor”)
SAM4S Series [DATASHEET]
Atmel-11100K-ATARM-SAM4S-Datasheet_09-Jun-15
426
24.5 SAM-BA Monitor
Once the communication interface is identified, to run in an infinite loop waiting for different commands as shown
in Table 24-2.
Mode commands:
Normal mode configures SAM-BA Monitor to send/receive data in binary format,
Terminal mode configures SAM-BA Monitor to send/receive data in ascii format.
Write commands: Write a byte (O), a halfword (H) or a word (W) to the target.
Address: Address in hexadecimal.
Value: Byte, halfword or word to write in hexadecimal.
Output: ‘>’.
Read commands: Read a byte (o), a halfword (h) or a word (w) from the target.
Address: Address in hexadecimal
Output: Th e byte, halfword or word read in hexadecimal following by ‘>’
Send a file (S) : Sen d a file to a spec ifie d addr e s s
Address: Address in hexadecimal
Output: ‘>’.
Note: There is a time-out on this command which is reached when the prompt ‘>’ appears before the end of the command
execution.
Receive a file (R): Receive data into a file from a specified address
Address: Address in hexadecimal
NbOfBytes: Number of bytes in hexadecimal to receive
Output: ‘>’
Go (G): Jump to a specified address and execute the code
Address: Address to jump in hexadecimal
Output: ‘>’
Get Version (V): Return the SAM-BA boot version
Output: ‘>’
Table 24-2. Commands Available through the SAM-BA Boot
Command Action Argument(s) Example
NSet Normal Mo de No argumen t N#
TSet Terminal Mo de No argument T#
OWrite a Byte Address, Value# O200001,CA#
oRead a Byte Address,# o200001,#
HWrite a Half Word Add r ess, Value# H200002,CAFE#
hRead a Half Word Address,# h200002,#
WWrite a Word Address, Value# W200000,CAFEDECA#
wRead a Wo rd Address,# w200000,#
SSend a File Addr ess,# S200000,#
RReceive a File Address, NbOfBytes# R200000,1234#
GGo Address# G200200#
VDisplay Version No argu ment V#
427
SAM4S Series [DATASHEET]
Atmel-11100K-ATARM-SAM4S-Datasheet_09-Jun-15
24.5.1 UART0 Serial Port
Communication is performed through the UART0 initialized to 115200 Baud, 8, n, 1.
The Send and Receive File commands use the Xmodem protocol to communicate. Any terminal performing this
protocol can be used to send th e application file to the target. The size of the binary file to se nd depends on the
SRAM size embedded in the product. In all cases, the size of the binary file must be lower than the SRAM size
because the Xmodem protocol requires some SRAM memory to work. See Section 24.2 ”Hardware and Software
Constraints”.
24.5.2 Xmodem Protocol
The Xmodem protocol supported is the 128-byte length block. This protocol uses a two-character CRC-16 to
guarantee detection of a maximum bit error.
Xmodem protocol with CRC is accurate provided both sender and receiver repo rt successful transmission. Each
block of the transfer looks like:
<SOH><blk #><255-blk #><--128 data by te s-- ><c he ck sum > in wh ich:
<SOH> = 01 hex
<blk #> = binary number, starts at 01, increments by 1, and wraps 0FFH to 00H (not to 01)
<255-blk #> = 1’s complement of the blk#.
<checksum> = 2 bytes CRC16
Figure 24-2 s ho w s a tra ns m issio n us ing this pr ot oc ol.
Figure 24-2. Xmodem Transfer Example
24.5.3 USB Device Port
The device uses the USB communication device class (CDC) drivers to take advantage of the installed PC RS-23 2
software to talk over the USB. The CDC class is implemented in all releases of Windows®, beginning with
Windows 98 SE. The CDC document, available at www.us b.org, describes a way to implement devices such as
ISDN modems and virtual COM ports.
The Vendor ID (VID) is Atmel’s vendor ID 0x03EB. The product ID (PID) is 0x6124. These references are used by
the host operating system to mount the correct driver. On Windows systems, the INF files contain the
correspondence between vendor ID and product ID.
Host Device
SOH 01 FE Data[128] CRC CRC
C
ACK
SOH 02 FD Data[128] CRC CRC
ACK
SOH 03 FC Data[100] CRC CRC
ACK
EOT
ACK
SAM4S Series [DATASHEET]
Atmel-11100K-ATARM-SAM4S-Datasheet_09-Jun-15
428
For more details about VID/PID for End Product/Systems, please refer to the Vendor ID form available from the
USB Implementers Forum on www.usb.org.
Atmel provides an INF example to see the device as a new serial port and also provides another cu stom driver
used by the SAM-BA application: atm6124.sys. Refer to the application note “USB Basic Application”, Atm el
literature nu m be r 6123 , fo r mo re det ails .
24.5.3.1 Enumeration Process
The USB protocol is a master/slave protocol. This is the host that starts the enumeration sending requests to the
device through the control endpoint. The device handles standard requests as defined in the USB Specification.
The device also handles some class requests defined in the CDC class.
Unhandled requests are STALLed.
24.5.3.2 Communication Endpoints
There are two communication endpoints and endpoint 0 is used for the enumeration process. Endpoint 1 is a 64-
byte Bulk OUT endp oint and endpoin t 2 is a 64-byte Bu lk IN endpoint. SAM -BA Boot command s are sent by the
host through endpoint 1. If r equir ed, the messag e is split by the ho st in to se vera l data pa ylo ads by th e host dr ive r.
If the command requires a response, the host can send IN transactions to pick up the response.
Table 24-3. Handled Standard Requests
Request Definition
GET_DESCRIPTOR Returns the current device configuration value.
SET_ADDRESS Sets the device address for all future device access.
SET_CONFIGURATION Sets the device configuration.
GET_CONFIGURATION Returns the current device configuration value.
GET_STATUS Returns status for the specified recipient.
SET_FEATURE Set or Enable a specific feature.
CLEAR_FEATURE Clear or Disable a specific feature.
Table 24-4. Handled Class Requests
Request Definition
SET_LINE_CODING Configures DTE rate, stop bits, parity and number of character bits.
GET_LINE_CODING Requests current DTE rate, stop bits, parity and number of character bits.
SET_CONTROL_LINE_STATE RS-232 signal used to tell the DCE device the DTE device is now present.
429
SAM4S Series [DATASHEET]
Atmel-11100K-ATARM-SAM4S-Datasheet_09-Jun-15
24.5.4 In Application Programming (IAP) Feature
The IAP feature is a function located in ROM that can be called by any software application.
When called, this function sends the desired FLASH command to the EEFC and waits for the Flash to be ready
(looping while the FRDY bit is not set in the EEFC_FSR).
Since this fu nction is executed fro m ROM, this allows Flash programming (such as sector write) to be done by
code running in Flash.
The IAP function entry point is retrieved by reading the NMI vector in ROM (0x00800008).
This function takes two arguments in parameter: the EFC number and the command to be sent to the EEFC.
This function returns the value of the EEFC_FSR.
IAP software code example:
(unsigned int) (*IAP_Function)(unsigned long);
void main (void){
unsigned long FlashSectorNum = 200; //
unsigned long flash_cmd = 0;
unsigned long flash_status = 0;
unsigned long EFCIndex = 0; // 0:EEFC0, 1: EEFC1
/* Initialize the function pointer (retrieve function addre ss from NMI vector)
*/
IAP_Function = ((unsigned long) (*)(unsigned long))
0x00800008;
/* Send your data to the sector here */
/* build the command to send to EEFC */
flash_cmd = (0x5A << 24) | (FlashSectorNum << 8) |
AT91C_MC_FCMD_EWP;
/* Call the IAP function with appropriate command */
flash_status = IAP_Function (EFCIndex, flash_cmd);
}
SAM4S Series [DATASHEET]
Atmel-11100K-ATARM-SAM4S-Datasheet_09-Jun-15
430
25. Bus Matrix (MATRIX)
25.1 Description
The Bus Matrix implements a multi-layer AHB that enables parallel access paths between multiple AHB masters
and slaves in a system, thus increasing overall bandwidth. The Bus Matrix interconnects AHB masters to AHB
slaves. The normal latency to connect a master to a slave is one cycle. The exception is the default master of the
accessed slave which is connected directly (zero cycle latency).
The Bus Matrix user interface also provides a System I/O Configuration user interface with registers that support
application-sp ecific features .
25.2 Master/Slave Management
25.2.1 Matrix Masters
The Bus Matrix manages the masters listed in Table 25-1. Each master can perform an access to an ava ilable
slave concurrently with other masters.
Each master has its own specifically-defined decoder. To simplify addressing, all the masters have the same
decoding.
25.2.2 Matrix Slaves
The Bus Matrix manages the slaves listed in Table 25-2. Each slave has its own arbiter providing a different
arbitration per slave.
Table 25-1. List of Bus Matrix Masters
Master 0 Cortex-M4 Instruction/Data
Master 1 Cortex-M4 System
Master 2 Periphe ral DMA Controller (PDC)
Master 3 CRC Calcul ation Unit
Table 25-2. List of Bus Matrix Slaves
Slave 0 Internal SRAM
Slave 1 Internal ROM
Slave 2 Internal Flash
Slave 3 External Bus Interface
Slave 4 Peripheral Bridge
431
SAM4S Series [DATASHEET]
Atmel-11100K-ATARM-SAM4S-Datasheet_09-Jun-15
25.2.3 Master to Slave Access
Table 25-3 gives valid paths for master to slave access on Matrix 0. The paths shown as “-” are forbidden or not
wired, e.g. access from the Cortex-M4 S Bus to the internal ROM.
25.3 Memory Mapping
The Bus Matrix provides one decoder for every AHB master interface. The decoder offers each AHB master
several memory mappings. In fact, depending on the product, each memory area may be assigned to several
slaves. Thus it is possible to boot at the same address while using different AHB slaves.
25.4 Special Bus Granting Techniques
The Bus Matrix provides some speculative bus granting techniques in order to anticipate access req uests from
some masters. This technique reduces latency at the first access of a burst or single transfer. Bus granting sets a
default mast er for ev er y slave.
At the end of the current access, if no other request is pending, the slave remains connected to its associated
default master. A slave can be associated with one of the three im p lem e ntations of de fa u lt masters:
No default master
Last access master
Fixed default master
25.4.1 No Default Master
At the end of the current acce ss, if no other request is pending, the slav e is disconnected from all masters. No
default master suits low-power mode.
25.4.2 Last Access Master
At the end of th e current access, if no oth er request is pending, the slave remains connected to the last master that
performed an access request.
25.4.3 Fixed Default Master
At the end of the current access, if no other request is pending , the slave connects to its fixed default master.
Unlike the last access master, the fixed master does not change un less the user modifies it by software (field
FIXED_DEFMSTR of the related MATRIX_SCFG).
To change from one kind of default master to another, the Bus Matrix user interface provides the Slave
Configuration registers (MATRIX_SCFGx), one for each slave, used to set a default master for each slave.
MATRIX_SCFGx contains the fields DEFMSTR_TYPE and FIXED_DEFMSTR. The 2-bit DEFMSTR_TYPE field
selects the default master type (no default, last access master, fixed default master) whereas the 4-bit
FIXED_DEFMSTR field selects a fixed default master, provided that DEFMSTR_TYPE is set to fixed default
master. Refer to Table 25-4, “Register Mapping”.
Table 25-3. Master to Slave Access
Slaves Masters 0 1 2 3
Cortex-M4 I/D Bus Cortex-M4 S Bus PDC CRCCU
0 Intern al SRAM – X X X
1 Internal ROM X – X X
2 Internal Flash X – - X
3 External Bus Interface – X X X
4 Peripheral Bridge – X X –
SAM4S Series [DATASHEET]
Atmel-11100K-ATARM-SAM4S-Datasheet_09-Jun-15
432
25.5 Arbitration
The Bus Matrix provides an arbitration technique that reduces latency when conflicting cases occur; for example,
when two or more masters try to access the sa me slave at the same time. One arbiter per AHB slave is provided to
arbitrate each slave differently.
The Bus Matrix provides the user with two arbitration typ es for ea ch slave :
1. Round-robin arbitration (default)
2. Fixed priority arbitration
The field ARBT of MATRIX_SCFG is used to select the type of arbitration.
Each algorithm may be complemented by selecting a default master configuration for each slave.
In case of re-arbitration, specific conditions apply. See Section 25.5.1 “Arbitration Rules“.
25.5.1 Arbitration Rules
Each arbiter has the ability to arbitrate between requests of two or more masters. To avoid burst breaking and to
provide the maximum throughput for slave interfaces, arbitration should take place during the following cycles:
1. Idle cycles: When a slave is not connected to any master or is connected to a master which is not currently
accessing it.
2. Single cycles: When a slave is performing a single access.
3. End of burst cycles: When the current cycle is the last cycle of a burst transfer. For a defined burst length,
predicted end of burst matches the size of the tran sfer but is man aged di fferently for undefined burst length.
See Section 25.5.1.1 “Undefined Length Burst Arbitration” on page 432“.
4. Slot cycle limit: When the slot cycle counter has reached the limit indicating that the curr ent master access is
too long and must be broken. See Section 25.5.1.2 “Slot Cycle Limit Arbitration” on page 432.
25.5.1.1 Undefined Length Burst Arbitration
In order to prevent slave handling during undefined length bursts (INCR), the Bus Matrix provides specific logic to
re-arbitrate before the end of the INCR transfer.
A predicted end of burst is used for defined length burst transfer , which is selected between the following:
1. Infinite: No predicted end of burst is generated and therefore INCR burst transfer will never be broken.
2. Four-beat bursts: Predicted end of burst is generated at the end of each four be at boundary inside INCR
transfer.
3. Eight-beat bursts: Predicted end of burst is generated at the end of each eight beat boundary inside INCR
transfer.
4. Sixteen-beat bursts: Predicted end of burst is generated at the end of each sixteen beat boundary insid e
INCR transfer.
This selection can be done through the field ULBT of the Master Configuration Registers (MATRIX_MCFG).
25.5.1.2 Slot Cycle Limit Arbitration
The Bus Matrix contains specific logic to break accesses that are too lon g, such as very lo ng b ursts on a ver y slow
slave (e.g. an exte rnal low-speed memory). At the beginning of the burst access, a counter is loaded with the value
previously written in the SLOT_CYCLE field of the related MATRIX_SCFG and decreased at each clock cycle.
When the counter reaches zero, the arbiter has the ability to re-arbitrate at the end of the current byte, half-word or
word transfer.
25.5.2 Round-Robin Arbitration
Bus Matrix arbiters use the round-robin a lgorithm to dispatch the requests from different masters to the same
slave. If two or m ore maste rs make a r equest a t the same time, the master with the lowe st number is serviced firs t.
The others are then serviced in a round-robin manner.
433
SAM4S Series [DATASHEET]
Atmel-11100K-ATARM-SAM4S-Datasheet_09-Jun-15
Three round-robin algorithms are implemented:
Round-Robin arbitration without default master
Round-Robin arbitration with last access master
Round-Robin arbitration with fixed default master
25.5.2.1 Round-Robin arbitration without default master
Round-robin arbitration without default master is the main algorithm used by Bus Matrix arbiters. It allows the Bus
Matrix to dispatch requests from different masters to the same slave in a pure round-robin manner. At the end of
the current access, if no other request is pending, the slave is disconnected from all m asters. This configura tion
incurs one latency cycle for the first access of a burst. Arbitration without default master can be used for masters
that perform significant bursts.
25.5.2.2 Round-Robin arbitration with last access master
Round-robin arbitration with last access master is a biased round-robin algorithm used by Bus Matrix arbiters. It
allows the Bus Matrix to remove the one latency cycle for the last master that accessed the slave. At the end of the
current transfer, if no other master request is pending, the slave remains connected to the last master that
performs the access. Other non-privileged masters incur one latency cycle if they want to access the same slave.
This technique can be used for masters that mainly perform single accesses.
25.5.2.3 Round-Robin arbitration with fixed default master
Round-robin arb itratio n with fixed de fa ult m aster is an alg orith m use d by th e Bus Matr ix ar biters to remo ve the on e
latency cycle for the fixed default master per slave. At the end of the c urrent acc ess, the slave remains connect ed
to its fixed default master. Every request attempted by the fixed default master does not incur latency, whereas
other non-privile ged masters still incur one late ncy cycle. This technique can be used fo r masters that mainly
perform single accesses.
25.5.3 Fixed Priority Arbitration
The fixed priority arbitration algorit hm is used by the Bus Matrix arbiters to dispatch the reque sts from different
masters to the same slave by using the fixed priority defined by the user. If requests from two or more masters are
active at the same time, the master with the highest priority is serviced first. If requests from tw o or more masters
with the same priority are active at the same time, the master with the highest number is serviced first.
For each slave, the priority of each master may be defined through the Priority registers for slaves
(MATRIX_PRAS and MATRIX_PRBS).
25.6 System I/O Configuration
The System I/O Configuration register (CCFG_SYSIO) configures I/O lines in system I/O mode (such as JTAG,
ERASE, USB, etc.) or as general-purpose I/O lines. Enabling or disabling the corresponding I/O lines in peripheral
mode or in PIO mode (PIO_PER or PIO_PDR registers) in the PIO controller has no effect. However, the direction
(input or output), pull-up, pull-down and other mode control is still managed by the PIO controller.
SAM4S Series [DATASHEET]
Atmel-11100K-ATARM-SAM4S-Datasheet_09-Jun-15
434
25.7 Register Write Protection
To prevent any single software error from corrupting MATRIX behavior, certain registers in the address space can
be write-protected by setting the WPEN bit in the “Write Protection Mode Register” (MATRIX_WPMR).
If a write access to a write-protected register is detected, the WPVS flag in the “Write Protection Status Register”
(MATRIX_WPSR) is set and the field WPVSRC indicates the register in which the write access has been
attempted.
The WPVS bit is automatically cleared after reading MATRIX_WPSR.
The following registers can be write-protected:
“Bus Matrix Master Configuration Registers”
“Bus Matrix Slave Co nf igu ratio n Re gisters”
“Bus Matrix Priority Registers For Slaves”
“System I/O Configuration Register”
435
SAM4S Series [DATASHEET]
Atmel-11100K-ATARM-SAM4S-Datasheet_09-Jun-15
25.8 Bus Matrix (MATRIX) (MAT RIX) User Interface
Table 25-4 . Register Mapping
Offset Register Name Access Reset
0x0000 Master Configuration Register 0 MATRIX_MCFG0 Read/Write 0x00000000
0x0004 Master Configuration Register 1 MATRIX_MCFG1 Read/Write 0x00000000
0x0008 Master Configuration Register 2 MATRIX_MCFG2 Read/Write 0x00000000
0x000C Master Configuration Register 3 MATRIX_MCF G3 Read/Write 0x00000000
0x0010 - 0x003C Reserved – – –
0x0040 Slave Configuration Register 0 MATRIX_SC FG0 Read/Write 0x0 0010010
0x0044 Slave Configuration Register 1 MATRIX_SC FG1 Read/Write 0x0 0050010
0x0048 Slave Configuration Register 2 MATRIX_SC FG2 Read/Write 0x0 0000010
0x004C Slave Configuration Register 3 MATRIX_SCFG3 Read/Write 0x00000010
0x0050 Slave Configuration Register 4 MATRIX_SC FG4 Read/Write 0x0 0000010
0x0054 - 0x007C Reserved – – –
0x0080 Priority Register A for Slave 0 MATRIX_PRAS0 Read/Write 0x00000000
0x0084 Reserved – – –
0x0088 Priority Register A for Slave 1 MATRIX_PRAS1 Read/Write 0x00000000
0x008C Reserved – – –
0x0090 Priority Register A for Slave 2 MATRIX_PRAS2 Read/Write 0x00000000
0x0094 Reserved – – –
0x0098 Priority Register A for Slave 3 MATRIX_PRAS3 Read/Write 0x00000000
0x009C Reserved – – –
0x00A0 Priority Register A for Slave 4 MATRIX_PRAS4 Re ad/Write 0x00000000
0x00A4 - 0x0110 Reserved – – –
0x0114 System I/O Configuration register CCFG_SYSIO Read/Write 0x00000000
0x0118 Reserved – – –
0x011C SMC Chip Select NAND Flash Assignment
Register CCFG_SMCNFCS Read/Write 0x00000000
0x0120 - 0x010C Reserved – – –
0x1E4 Write Protection Mode Register MATRIX_WPMR Read/Write 0x0
0x1E8 Write Protection Status Register MATRIX_ WPSR Read-only 0x0
0x0110 - 0x01FC Reserved – – –
SAM4S Series [DATASHEET]
Atmel-11100K-ATARM-SAM4S-Datasheet_09-Jun-15
436
25.8.1 Bus Matrix Master Configuration Registers
Name: MATRIX_MCFG0..MATRIX_MCFG3
Address: 0x400E0200
Access: Read/Write
• ULBT: Undefined Length Burst Type
31 30 29 28 27 26 25 24
––––––––
23 22 21 20 19 18 17 16
––––––––
15 14 13 12 11 10 9 8
––––––––
76543210
––––– ULBT
Value Name Description
0INFINITE No predicted end of burst is generated and therefore INCR bursts coming from
this master cannot be broken.
1 SINGLE The undefined length burst is treated as a succession of single access allowing
rearbitration at each beat of the INCR burst.
2 FOUR_BEAT The undefined length burst is split into a 4-be at bursts allowing rearbitration at
each 4-beat burst end.
3 EIGHT_BEAT The undefined length burst is split into 8-beat bursts allowing rearbitration at each
8-beat burst end.
4 SIXTEEN_BEAT The undefined length burst is split into 16-beat bursts allowing rearbitration at
each 16-beat burst end.
437
SAM4S Series [DATASHEET]
Atmel-11100K-ATARM-SAM4S-Datasheet_09-Jun-15
25.8.2 Bus Matrix Slave Configuration Registers
Name: MATRIX_SCFG0..MATRIX_SCFG4
Address: 0x400E0240
Access: Read/Write
• SLOT_CYCLE: Maximum Number of Allowed Cycles for a Burst
When the SLOT_CYCLE limit is reach for a burst, it may be broken by another master trying to access this slave.
This limit has been placed to avoid locking very slow slaves when very long bursts are used.
This limit should not be very small. An unreasonably small value will break every burst and the Bus Matrix will spend its
time to arbitrate without performing any data transfer. 16 cycles is a reasonable value for SLOT_CYCLE.
• DEFMSTR_TYPE: Default Master Type
• FIXED_DEF MST R : Fix e d Defa ul t Ma s te r
This is the number of the default master for this slave. Only used if DEFMSTR_TYPE is 2. Specifying the number of a mas-
ter which is not connected to the selected slave is equivalent to setting DEFMSTR_TYPE to 0.
• ARBT: Arbitration Type
31 30 29 28 27 26 25 24
–––––– ARBT
23 22 21 20 19 18 17 16
– – – FIXED_DEFMSTR DEFMSTR_TYPE
15 14 13 12 11 10 9 8
––––––––
76543210
SLOT_CYCLE
Value Name Description
0 NO_DEFAULT
At the end of current slave access, if no other master request is pending, the slave is
disconnected from all masters.
This results in having a one cycle latency for the first access of a burst transfer or for a
single access.
1LAST
At the end of current slave access, if no other master request is pending, the slave
stays connected to the last master having accessed it.
This results in not having the one cycle latency when the last m aster tries to access the
slave again.
2 FIXED
At the end of the current slave access, if no other master request is pending, the slave
connects to the fixed master the number that has been written in the
FIXED_DEFMSTR field.
This results in not having the one cycle latency when the fixed master tries to access
the slave again.
Value Name Description
0 ROUND_ROBIN Round-robin arbitration
1 FIXED_PRIORITY Fixed priority arbitration
SAM4S Series [DATASHEET]
Atmel-11100K-ATARM-SAM4S-Datasheet_09-Jun-15
438
25.8.3 Bus Matrix Priority Registers For Slaves
Name: MATRIX_PRAS0..MATRIX_PRAS4
Address: 0x400E0280 [0], 0x400E0288 [1], 0x400E0290 [2], 0x400E0298 [3], 0x400E02A0 [4]
Access: Read/Write
• MxPR: Master x Priority
Fixed priority of master x for accessing the selected slave. The higher the number, the higher the priority.
31 30 29 28 27 26 25 24
––––––––
23 22 21 20 19 18 17 16
–––––– M4PR
15 14 13 12 11 10 9 8
–– M3PR –– M2PR
76543210
–– M1PR –– M0PR
439
SAM4S Series [DATASHEET]
Atmel-11100K-ATARM-SAM4S-Datasheet_09-Jun-15
25.8.4 System I/O Configuration Register
Name: CCFG_SYSIO
Address:0x400E0314
Access Read/Write
Reset: 0x0000_0000
• SYSIO4: PB4 or TDI Assignment
0: TDI function selected.
1: PB4 function selected.
• SYSIO5: PB5 or TDO/TRACESWO Assignment
0: TDO/TRACESWO function selected.
1: PB5 function selected.
• SYSIO6: PB6 or TMS/SWDIO Assignment
0: TMS/SWDIO function selected.
1: PB6 function selected.
• SYSIO7: PB7 or TCK/SWCLK Assignment
0: TCK/SWCLK function selected.
1: PB7 function selected.
• SYSIO10: PB10 or DDM Assignment
0: DDM function selected.
1: PB10 function selected.
• SYSIO11: PB11 or DDP Assignment
0: DDP function selected.
1: PB11 function selected.
• SYSIO12: PB12 or ERASE Assignment
0: ERASE function selected.
1: PB12 function selected.
31 30 29 28 27 26 25 24
––––––––
23 22 21 20 19 18 17 16
––––––––
15 14 13 12 11 10 9 8
– – – SYSIO12 SYSIO11 SYSIO10 – –
76543210
SYSIO7 SYSIO6 SYSIO5 SYSIO4 – – – –
SAM4S Series [DATASHEET]
Atmel-11100K-ATARM-SAM4S-Datasheet_09-Jun-15
440
25.8.5 SMC NAND Flash Chip Select Configuration Register
Name: CCFG_SMCNFCS
Address:0x400E031C
Type: Read/Write
Reset: 0x0000_0000
• SMC_NFCS0: SMC NAND Flash Chip Select 0 Assignment
0: NCS0 is not assigned to a NAND Flash (NANDOE and NANWE not used for NCS0)
1: NCS0 is assigned to a NAND Flash (NANDOE and NANWE used for NCS0)
• SMC_NFCS1: SMC NAND Flash Chip Select 1 Assignment
0: NCS1 is not assigned to a NAND Flash (NANDOE and NANWE not used for NCS1)
1: NCS1 is assigned to a NAND Flash (NANDOE and NANWE used for NCS1)
• SMC_NFCS2: SMC NAND Flash Chip Select 2 Assignment
0: NCS2 is not assigned to a NAND Flash (NANDOE and NANWE not used for NCS2)
1: NCS2 is assigned to a NAND Flash (NANDOE and NANWE used for NCS2)
• SMC_NFCS3: SMC NAND Flash Chip Select 3 Assignment
0: NCS3 is not assigned to a NAND Flash (NANDOE and NANWE not used for NCS3)
1: NCS3 is assigned to a NAND Flash (NANDOE and NANWE used for NCS3)
31 30 29 28 27 26 25 24
––––––––
23 22 21 20 19 18 17 16
––––––––
15 14 13 12 11 10 9 8
––––––––
76543210
––––SMC_NFCS3SMC_NFCS2SMC_NFCS1SMC_NFCS0
441
SAM4S Series [DATASHEET]
Atmel-11100K-ATARM-SAM4S-Datasheet_09-Jun-15
25.8.6 Write Protection Mode Register
Name: MATRIX_WPMR
Address: 0x400E03E4
Access: Read/Write
Reset: See Table 25-4
• WPEN: Write Protec ti on Ena b le
0: Disables the write protection if WPKEY corresponds to 0x4D4154 (“MAT” in ASCII).
1: Enables the write protection if WPKEY corresponds to 0x4D4154 (“MAT” in ASCII).
See Section 25.7 “Register Write Protection“ for the list of registers that can be write-protected.
• WPKEY: Write Protect Key
31 30 29 28 27 26 25 24
WPKEY
23 22 21 20 19 18 17 16
WPKEY
15 14 13 12 11 10 9 8
WPKEY
76543210
–––––––WPEN
Value Name Description
0x4D4154 PASSWD Writing any othe r val ue in this field aborts the write operation of the WPEN bit. Always reads
as 0.
SAM4S Series [DATASHEET]
Atmel-11100K-ATARM-SAM4S-Datasheet_09-Jun-15
442
25.8.7 Write Protection Status Register
Name: MATRIX_WPSR
Address: 0x400E03E8
Access: Read-only
Reset: See Table 25-4
• WPVS: Write Protection Violation Status
0: No write protec tion v iola tio n ha s occ u rred since the last read of the MATRIX_WPSR.
1: A write protection violation has occurred since th e last read of the MATRIX_WPSR. If this violation is an unauthorized
attempt to write a protected register, the associated violation is reported into field WPVSRC.
• WPVSRC: Write Protection Violation Source
When WPVS = 1, WPVSRC indicates the register address offset at which a write access has been attempted.
31 30 29 28 27 26 25 24
––––––––
23 22 21 20 19 18 17 16
WPVSRC
15 14 13 12 11 10 9 8
WPVSRC
76543210
–––––––WPVS
443
SAM4S Series [DATASHEET]
Atmel-11100K-ATARM-SAM4S-Datasheet_09-Jun-15
26. Static Memory Controller (SMC)
26.1 Description
The External Bus Interface (EBI) is designed to ensure the successful data transfer between several external
devices and the ARM-based microcontroller. The Static Memory Controller (SMC) is part of the EBI.
This SMC can handle several types of external memory and peripheral devices, such as SRAM, PSRAM, PROM,
EPROM, EEPROM, LCD Module, NOR Flash and NAND Flash.
The SMC generates the signals that control the access to the external memory devices or peripheral devices. It
has 4 Chip Selects, a 24-bit address bus, and an 8-bit data bus. Separate read an d write control signals allow for
direct memory and peripheral interfacing. Read and write signal waveforms are fully adjustable.
The SMC can manage wait requests from external devices to extend the current access. The SMC is provided with
an automatic Slow clock mod e. In Slow clock mode, it switches from user-programmed waveforms to slow-rate
specific waveforms on read and write signals. The SMC supports asynchronous burst read in Page mode access
for page sizes up to 32 bytes.
The External Data Bus can be scrambled/unscrambled by means of user keys.
26.2 Embedded Characteristics
Four Chip Selects Available
16-Mbyte Address Space per Chip Select
8-bit Data Bus
Zero Wait State Scrambling/Unscrambling Function with User Key
Word, Halfword, Byte Transfers
Programmable Setup, Pulse And Hold Time for Read Signals per Chip Select
Programmable Setup, Pulse And Hold Time for Write Signals per Chip Select
Programmable Data Float Time per Chip Select
External Wait Request
Automatic Switch to Slow Clock Mode
Asynchronous Read in Page Mode Supported: Page Size Ranges from 4 to 32 Bytes
Register Write Protection
SAM4S Series [DATASHEET]
Atmel-11100K-ATARM-SAM4S-Datasheet_09-Jun-15
444
26.3 I/O Lines Description
26.4 Product Dependencies
26.4.1 I/O Lines
The pins used for interfacing the SMC are multiplexed with the PIO lines. The programmer must first program the
PIO controller to assign the SMC pins to their peripheral function. If I/O Lines of the SMC are no t used by the
application, they can be used for other purposes by the PIO Controller.
Table 26-1. I/O Line Description
Name Description Type Active Level
NCS[3:0] Static Memory Controller Chip Select Lines Output Low
NRD Read Signal Output Low
NWE Write Enable Signal Output Low
A[23:0] Address Bus Output –
D[7:0] Data Bus I/O –
NWAIT External Wait Signal Input Low
NANDCS NAND Flash Chip Select Line Output Low
NANDOE NAND Flash Output Enable Ou tput Low
NANDWE NAND Flash Write Enable Output Low
NANDALE NAND Flash Address Latch Enable Output –
NANDCLE NAND Fla s h Command Latch Enable Output –
Table 26-2. I/O Lines
Instance Signal I/O Line Periphera l
SMC A0 PC18 A
SMC A1 PC19 A
SMC A2 PC20 A
SMC A3 PC21 A
SMC A4 PC22 A
SMC A5 PC23 A
SMC A6 PC24 A
SMC A7 PC25 A
SMC A8 PC26 A
SMC A9 PC27 A
SMC A10 PC28 A
SMC A11 PC29 A
SMC A12 PC30 A
SMC A13 PC31 A
SMC A14 PA18 C
SMC A15 PA19 C
445
SAM4S Series [DATASHEET]
Atmel-11100K-ATARM-SAM4S-Datasheet_09-Jun-15
26.4.2 Power Management
The SMC is clocked through the Power Management Controller (PMC), thus the programmer must first configure
the PMC to enable the SMC clock.
26.5 Multiplexed Signals
SMC A16 PA20 C
SMC A17 PA0 C
SMC A18 PA1 C
SMC A19 PA23 C
SMC A20 PA24 C
SMC A21/NANDALE PC16 A
SMC A22/NANDCLE PC17 A
SMC A23 PA25 C
SMC D0 PC0 A
SMC D1 PC1 A
SMC D2 PC2 A
SMC D3 PC3 A
SMC D4 PC4 A
SMC D5 PC5 A
SMC D6 PC6 A
SMC D7 PC7 A
SMC NANDOE PC9 A
SMC NANDWE PC10 A
SMC NCS0 PC14 A
SMC NCS1 PC15 A
SMC NCS2 PA22 C
SMC NCS3 PC12 A
SMC NRD PC11 A
SMC NWAIT PC13 A
SMC NWE PC8 A
Table 26-2. I/O Lines
Table 26-3. Static Memory Controller (SMC) Multiplexed Signals
Multiplexed Signals Related Function
A22 NANDCLE NAND Flash Command Latch Enable
A21 NANDALE NAND Flash Address Latch Enab l e
SAM4S Series [DATASHEET]
Atmel-11100K-ATARM-SAM4S-Datasheet_09-Jun-15
446
26.6 External Memory Mapping
The SMC provides up to 24 address lines, A[23:0]. This allows each chip select line to address up to 16 Mbytes of
memory.
If the physical memory device connected on one chip select is smaller than 16 Mbytes, it wraps around and
appears to be repeated within this space. The SMC correctly handles any valid access to the memory device
within the page (see Figure 26-1).
Figure 26-1. Memory Connections for Four External Device s
26.7 Connection to External Devices
26.7.1 Data Bus Width
The data bus width is 8 bits.
Figure 26-2 shows how to connect a 512-Kbyte x 8-bit memory on NCS2.
Figure 26-2. Memory Connection for an 8-bit Data Bus
NRD
NWE
A[23:0]
D[7:0]
8
Memory Enable
Memory Enable
Memory Enable
Memory Enable
Output Enable
Write Enable
A[23:0]
D[7:0]
NCS3
NCS0
NCS1
NCS2
NCS[0] - NCS[3]
SMC
24
SMC
A1
NWE
NRD
NCS[2]
A1
Write Enable
Output Enable
Memory Enable
D[7:0] D[7:0]
A[18:2]
A[18:2]
A0 A0
447
SAM4S Series [DATASHEET]
Atmel-11100K-ATARM-SAM4S-Datasheet_09-Jun-15
26.7.2 NAND Flash Support
The SMC integrates circuitry that interfaces to NAND Flash devices.
The NAND Flash logic is driven by the SMC. It depends on the programming of the SMC_NFCSx field in the
CCFG_SMCNFCS register on the Bus Matrix User Interface. For details on this register, refer to the section “Bus
Matrix (MATRIX)” of this datasheet. Access to an external NAND Flash device via the address space reserved to
the chip select programmed.
The user can connect up to four NAND Flash devices with separate chip selects.
The NAND Flash logic drives the read and write command signals of the SMC on the NANDOE and NANDWE
signals when the NCSx programmed is active. NANDOE and NANDWE are disabled as soon as the transfer
address fails to lie in the NCSx programmed address space.
Figure 26-3. NAND Flash Signal Multiplexing on SMC Pins
Note: When the NAND Flash logic is activated, (SMC_NFCSx=1), the NWE pin cannot be used in PIO mode but only in
Peripheral mode (NWE function). If the NWE function is not used for other external memories (SRAM, LCD), it must
be configured in one of the following modes:
– PIO Input with pull-up enabled (default state after reset)
– PIO Output set at level 1
The address latch ena ble and co mmand latch enable sig nals on the NAND Fla sh device are dr iven by address b its
A22 and A21of the address bus. Any bit of the address bus can also be used for this purpose. The command,
address or data words on the data bus of the NAND Flash device use their own addresses within the NCSx
address space (configured by the register CCFG_SMCNF CS on the Bus Matrix User Interface). The chip enable
(CE) signal of the device and the read y/busy ( R/B) signals are connecte d to PIO lines. The CE signal then remains
asserted even when NCS3 is not selected, preventing the device from returning to Standby mode. The NANDCS
output signal should be used in accordance with the external NAND Flash device type.
Two types of CE behavior exist depending on the NAND Flash device:
Standard NAND Flash devices require that the CE pin remains asserted Low continuously during the read
busy period to pre ven t th e de vice from returning to Standby mode. Since the SMC asserts the NCSx signal
High, it is necessary to connect the CE pin of the NAND Flash device to a GPIO line, in order to hold it low
during the busy period preceding data read out.
This restriction has been removed for “CE don’t care” NAND Flash devices. The NCSx signal can be directly
connected to the CE pin of the NAND Flash device.
Figure 26-4 illustrates both topologies: Standard and “CE don’t care” NAND Flash.
SMC
NRD
NWE
NANDOE
NANDWE
NAND Flash Logic
NCSx (activated if SMC_NFCSx=1) *
NANDWE
NANDOE
* in CCFG_SMCNFCS Matrix register
SAM4S Series [DATASHEET]
Atmel-11100K-ATARM-SAM4S-Datasheet_09-Jun-15
448
Figure 26-4. Standard and “CE don’t care” NAND Flash Application Examples
26.8 Application Example
26.8.1 Implementation Examples
Hardware configurations are given for illustration only. The user should refer to the manufacturer web site to check
for memory device availability.
For hard wa re imp l em e nt at ion e xa m ple s, r efe r to th e ev aluation kit schematics for this microcontroller, which show
examples of a connection to an LCD module and NAND Flash.
D[7:0]
ALE
NANDWE NOE
NWE
A[22:21]
CLE
AD[7:0]
PIO R/B
SMC
CE
NAND Flash
PIO
NCSx Not Connected
NANDOE
D[7:0]
ALE
NANDWE NOE
NWE
A[22:21]
CLE
AD[7:0]
PIO R/B
SMC
CE
“CE don’t care”
NAND Flash
NCSx
NANDOE
449
SAM4S Series [DATASHEET]
Atmel-11100K-ATARM-SAM4S-Datasheet_09-Jun-15
26.8.1.1 8-bit NAND Flash
Hardware Configuration
Software Configuration
Perform the following configuration:
1. Assign the SMC_NFCSx (for example SMC_NFCS3) field in the CCFG_SMCNFCS register on the Bus
Matrix User Interface.
2. Reserve A21 / A22 for ALE / CLE functions. Address and Command Latches are controlled by setting the
address bits A21 and A22, respectively, during accesses.
3. NANDOE and NANDWE signals are multiplexed with PIO lines. Thus, the dedicated PIOs must be
programmed in Peripheral mode in the PIO controller.
4. Configure a PIO line as an input to manage the Ready/Busy signal.
5. Configure SMC CS3 Setup, Pulse, Cycle and Mode according to NAND Flash timings, the data bus width
and the system bus frequency.
In this example, the NAND Flash is not addressed a s a “CE don’t care”. To addre ss it as a “CE don’t car e”, connect
NCS3 (if SMC_NFCS3 is set) to the NAND Flash CE.
D6
D0
D3
D4
D2
D1
D5
D7
NANDOE
NANDWE
(ANY PIO)
(ANY PIO)
ALE
CLE
D[0..7]
3V3
3V3
2 Gb
TSOP48 PACKAGE
U1 K9F2G08U0MU1 K9F2G08U0M
WE
18
N.C
6
VCC 37
CE
9
RE
8
N.C
20
WP
19
N.C
5
N.C
1
N.C
2
N.C
3
N.C
4
N.C
21
N.C
22
N.C
23
N.C
24
R/B
7
N.C
26
N.C 27
N.C 28
I/O0 29
N.C 34
N.C 35
VSS 36
PRE 38
N.C 39
VCC 12
VSS 13
ALE
17
N.C
11 N.C
10
N.C
14
N.C
15
CLE
16
N.C
25
N.C 33
I/O1 30
I/O3 32
I/O2 31
N.C 47
N.C 46
N.C 45
I/O7 44
I/O6 43
I/O5 42
I/O4 41
N.C 40
N.C 48
R2 10KR2 10K
C2
100NF
C2
100NF
R1 10K
R1 10K
C1
100NF
C1
100NF
SAM4S Series [DATASHEET]
Atmel-11100K-ATARM-SAM4S-Datasheet_09-Jun-15
450
26.8.1.2 NOR Flash
Hardware Configuration
Software Configuration
Configure the SMC CS0 Setup, Pulse, Cycle and Mode depending on Flash timing s an d system bus freque nc y .
26.9 Standard Read and Write Protocols
In the following sections, NCS represents one of the NCS[0..3] chip select lines.
26.9.1 Read Waveforms
The read cycle is shown on Figure 26-5.
The read cycle starts with the address setting on the memory address bus.
A21
A1
A0
A2
A3
A4
A5
A6
A7
A8
A15
A9
A12
A13
A11
A10
A14
A16
D6
D0
D3
D4
D2
D1
D5
D7
A17
A20
A18
A19
D[0..7]
A[0..21]
NRST
NWE
NCS0
NRD
3V3
3V3
C2
100NF
C2
100NF
C1
100NF
C1
100NF
U1U1
A0
A1
A2
A3
A4
A5
A6
A7
A8
A9
A10
A11
A12
A13
A14
A15
A16
A17
A18
A21
A20
A19
WE
RESET
WP
OE
CE
VPP
DQ0
DQ1
DQ2
DQ3
DQ4
DQ5
DQ6
DQ7
VCCQ
VSS
VSS
VCC
451
SAM4S Series [DATASHEET]
Atmel-11100K-ATARM-SAM4S-Datasheet_09-Jun-15
Figure 26-5. Standard Read Cycle
26.9.1.1 NRD Waveform
The NRD signal is characterized by a setup timing, a pulse width and a hold timing.
NRD_SETUP—the NRD setup time is defined as the setup of address before the NRD falling edge;
NRD_PULSE—the NRD pulse length is the time between NRD falling edge and NRD rising edge;
NRD_HOLD—the NRD hold time is defined as the hold time of address after the NRD rising edge.
26.9.1.2 NCS Waveform
The NCS signal can be divided into a setup time, pulse length and hold time:
NCS_RD_SETUP—the NCS setup time is defined as the setup time of address before the NCS falling edge.
NCS_RD_PULSE— the NCS pulse length is the time between NCS falling edge and NCS rising edge;
NCS_RD_HOLD—the NCS hold time is defined as the hold time of address after the NCS rising edge.
26.9.1.3 Read Cycle
The NRD_CYCLE time is defined as the total duration of the read cycle, i.e., from the time wher e address is se t on
the address bus to the point where address may change. The total read cycle time is equal to:
NRD_CYCLE = NRD_SETUP + NRD_PULSE + NRD_HOLD = NCS_RD_SETUP + NCS_RD_PULSE + NCS_RD_HOLD
All NRD and NCS timings are d efined separate ly for each ch ip select as an integer num ber of Master Clo ck cycles.
To ensure that th e NRD a nd NC S timing s are consis tent, u ser must define the total read cycle instead of the hold
timing. NRD_CYCLE implicitly defines the NRD hold time and NCS hold time as:
NRD_HOLD = NRD_CYCLE - NRD SETUP - NRD PULSE
NCS_RD_HOLD = NRD_CYCLE - NCS_RD_SETUP - NCS_RD_PULSE
26.9.1.4 Null Delay Setup and Hold
If null setup and hold parameters are programmed for NRD and/or NCS, NRD and NCS remain active continuously
in case of consecutive read cycles in the same memory (see Figure 26 -6).
A[23:0]
NCS
NRD_SETUP NRD_PULSE NRD_HOLD
MCK
NRD
D[7:0]
NCS_RD_SETUP NCS_RD_PULSENCS_RD_HOLD
NRD_CYCLE
SAM4S Series [DATASHEET]
Atmel-11100K-ATARM-SAM4S-Datasheet_09-Jun-15
452
Figure 26-6. No Setup, No Hold on NRD and NCS Read Signals
26.9.1.5 Null Pulse
Programming null pulse is not permitted. Pulse must be at least set to 1. A null value leads to unpredictable
behavior.
26.9.2 Read Mode
As NCS and NRD waveforms are de fined ind epe ndently of o ne other, the SMC ne eds to know whe n th e rea d d ata
is available on the data bus. The SMC d oes not compare NCS and NRD timings to know which signal rises first.
The READ_MODE parameter in the SMC_MODE register of the corresponding chip select indicates which signal
of NRD and NCS controls the read operation.
26.9.2.1 Read is Controlled by NRD (READ_MODE = 1):
Figure 26-7 shows the waveforms of a read operation of a typical asynchronous RAM. The read data is available
tPACC after the falling edge of NRD, and turns to ‘Z’ after the rising edge of NRD. In this case, the READ_MODE
must be set to 1 (read is controlled by NRD), to indicate that data is availab le with the rising edge of NRD. The
SMC samples the read data internally on the rising edge of Master Clock that generates the rising edge of NRD,
whatever the programmed waveform of NCS may be.
MCK
NRD_PULSE
NCS_RD_PULSE
NRD_CYCLE
NRD_PULSE NRD_PULSE
NCS_RD_PULSENCS_RD_PULSE
NRD_CYCLE NRD_CYCLE
A[23:0]
NCS
NRD
D[7:0]
453
SAM4S Series [DATASHEET]
Atmel-11100K-ATARM-SAM4S-Datasheet_09-Jun-15
Figure 26-7. READ_MODE = 1: Data is sampled by SMC before the rising edge of NRD
Data Sampling
tPACC
MCK
A[23:0]
NCS
NRD
D[7:0]
SAM4S Series [DATASHEET]
Atmel-11100K-ATARM-SAM4S-Datasheet_09-Jun-15
454
26.9.2.2 Read is Controlled by NCS (READ_MODE = 0)
Figure 26-8 shows the typ ical read cycle of an LCD module . The read data is valid tPACC after the falling edge of the
NCS signal and rem ains valid until the rising edge of NC S. Data must be sampled when NCS is ra ised. In that
case, the READ_MODE must be set to 0 (read is controlled by NCS): the S MC internally samples the data on the
rising edge of Master Clock that gener ates the rising edge of NCS, whatever the programmed waveform of NRD
may be.
Figure 26-8. READ_MODE = 0: Data is sampled by SMC before the rising edge of NCS
Data Sampling
tPACC
MCK
D[7:0]
A[23:0]
NCS
NRD
455
SAM4S Series [DATASHEET]
Atmel-11100K-ATARM-SAM4S-Datasheet_09-Jun-15
26.9.3 Write Waveforms
The write protocol is similar to the read pro tocol. It is depicted in Figure 26-9. The write cycle starts with the
address setting on the memory address bus.
26.9.3.1 NWE Waveforms
The NWE signal is characterized by a setup timing, a pulse width and a hold timing.
NWE_SETUP—the NWE setup time is defined as the setup of address and data before the NWE falling
edge;
NWE_PULSE—the NWE pulse length is the time between NWE falling edge and NWE rising edge;
NWE_HOLD—the NWE hold time is defined as the hold time of address and dat a afte r the NWE rising edge.
26.9.3.2 NCS Waveforms
The NCS signal wa veforms in write operation are not the same that those ap plied in read operations, b ut are
separately defined:
NCS_WR_SETUP—the NCS setup time is defined as the setup time of address before the NCS falling
edge.
NCS_WR_PULSE—the NCS pulse length is the time between NCS falling edge and NCS rising edge;
NCS_WR_HOLD—the NCS hold time is defined as the hold time of address after the NCS rising edge.
Figure 26-9. Write Cycle
26.9.3.3 Write Cycle
The write_cycle time is defined as the total duration of the write cycle, that is, from the time where address is set
on the address bus to the point where address may change. The total write cycle time is equal to:
NWE_CYCLE=NWE_SETUP + NWE_PULSE + NWE_HOLD=NCS_WR_SETUP + NCS_WR_PULSE + NCS_WR_HOLD
All NWE and NCS (write) timing s are d efined sepa rately fo r each chip select as an integer num ber of Master Clock
cycles. To ensure that the NWE and NCS timings are consistent, the user must d ef ine the total write cyc le ins tead
of the hold timing. This implicitly defines the NWE hold time and NCS (write) hold times as:
A
[23:0]
NCS
NWE_SETUP NWE_PULSE NWE_HOLD
MCK
NWE
NCS_WR_SETUP NCS_WR_PULSENCS_WR_HOLD
NWE_CYCLE
SAM4S Series [DATASHEET]
Atmel-11100K-ATARM-SAM4S-Datasheet_09-Jun-15
456
NWE_HOLD = NWE_CYCLE - NWE_SETUP - NWE_PULSE
NCS_WR_HOLD = NWE_CYCLE - NCS_WR_SETUP - NCS_WR_PULSE
26.9.3.4 Null Delay Setup and Hold
If null setup parameter s are programmed for NWE and/or NCS, NWE and/or NCS remain active continuously in
case of cons ecutive w rite cy cles in the sa me mem ory (se e Figure 26-10). However, for devices that perform write
operations on the rising edge of NWE or NCS, such as SRAM, either a setup or a hold must be programmed.
Figure 26-10. Null Setup and Hold Values of NCS and NWE in Write Cycle
26.9.3.5 Null Pulse
Programming null pulse is not permitted. Pulse must be at least set to 1. A null value leads to unpredictable
behavior.
26.9.4 Write Mode
The bit WRITE_MODE in the SMC_MODE register of the corresponding chip select indicates which signal controls
the write operation.
26.9.4.1 Write is Controlled by NWE (WRITE_MODE = 1):
Figure 26-11 shows the wa veform s of a write operat ion with WRITE_MODE set . The data is put on the bus during
the pulse and hold steps of the NWE signal. The internal data buffers are switched to Ou tput mode after the
NWE_SETUP time, and until the end of the write cycle, regardless of the programmed waveform on NCS.
NCS
MCK
NWE
D[7:0]
NWE_PULSE
NCS_WR_PULSE
NWE_CYCLE
NWE_PULSE
NCS_WR_PULSE
NWE_CYCLE
NWE_PULSE
NCS_WR_PULSE
NWE_CYCLE
A
[23:0]
457
SAM4S Series [DATASHEET]
Atmel-11100K-ATARM-SAM4S-Datasheet_09-Jun-15
Figure 26-11. WRITE_MODE = 1. The write operation is controlled by NWE
26.9.4.2 Write is Controlled by NCS (WRITE_MODE = 0)
Figure 26-12 shows the waveforms of a write operat ion with WRITE_MODE cleared. The data is put on the bus
during the pulse and hold steps of the NCS signal. The internal data buffers are switched to Output mode af te r th e
NCS_WR_SETUP time , an d un til th e en d of the writ e cyc le, reg ardle ss of the pro gram m ed wav efo r m on NW E.
Figure 26-12. WRITE_MODE = 0. The write operation is controlled by NCS
26.9.5 Register Write Protection
To prevent any single software error that may corrupt SMC behavior, the registers listed below can be write-
protected by setting the WPEN bit in the SMC Write Protection Mode register (SMC_WPMR).
If a write access in a write-protected register is detected, the WPVS flag in the SMC Write Protection Status
register (SMC_WPSR) is set and the field WPVSRC indicates in which register the write access has been
attempted.
The WPVS flag is automatically cleared after reading the SSMC_WPSR.
The following registers can be write-protected:
“SMC Setup Register”
“SMC Pulse Register”
MCK
D[7:0]
NCS
A
[23:0]
NWE
MCK
D[7:0]
NCS
NWE
A
[23:0]
SAM4S Series [DATASHEET]
Atmel-11100K-ATARM-SAM4S-Datasheet_09-Jun-15
458
“SMC Cycle Register”
“SMC MODE Register”
26.9.6 Coding Timing Parameters
All timing parameters ar e d efine d for one ch ip select and are grouped together in one SM C_REGIST ER a ccor ding
to their type.
The SMC_SETUP register groups the definition of all setup parameters:
NRD_SETUP, NCS_RD_SETUP, NWE_SETUP, NCS_WR_SETUP
The SMC_PULSE register groups the definition of all pulse parameters:
NRD_PULSE, NCS_RD_PULSE, NWE_PULSE, NCS_WR_PULSE
The SMC_CYCLE register groups the definition of all cycle parameters:
NRD_CYCLE, NWE_CYCLE
Table 26-4 shows how the timing parameters are coded and their permitted range.
26.9.7 Reset Values of Timing Parameters
Table 26-5 gives the default value of timing parameters at reset.
26.9.8 Usage Restriction
The SMC does not check the validity of the user-programmed parameters. If the sum of SETUP and PULSE
parameters is larger than the corresponding CYCLE parameter, this leads to unpredictable behavior of the SMC.
For read operations:
Null but positive setup and hold of address and NRD and/or NCS can not be guaranteed at the memory interface
because of the propagation delay of theses signals through external logic and pads. If positive setup and hold
values must be verified, then it is strictly recommended to program non-null values so as to cover possible skews
between address, NCS and NRD signals.
Table 26-4. Coding and Range of Timing Parameters
Coded Value Number of Bits Effective Value
Permitted Range
Coded Value Effective Value
setup [5:0] 6 1 28 x setup[5] + setup[4:0] 0 ≤ ≤ 31 0 ≤ ≤ 128+31
pulse [6:0] 7 256 x pulse[6] + pulse[5:0] 0 ≤ ≤ 63 0 ≤ ≤ 256+63
cycle [8:0] 9 256 x cycle[8:7] + cycle[6:0] 0 ≤ ≤ 127 0 ≤ ≤ 256+127
0 ≤ ≤ 512+127
0 ≤ ≤ 768+127
Table 26-5. Reset Values of Timing Parameters
Register Reset Value Definitio n
SMC_SETUP 0x0101 0101 All setup timings are set to 1.
SMC_PULSE 0x01010101 All pulse timings are set to 1.
SMC_CYCLE 0x00030003 The read and write operation s last 3 Master Clock
cycles and provide one hold cycle.
WRITE_MODE 1 Write is controll ed with NWE.
READ_MODE 1 Read is controlled with NRD.
459
SAM4S Series [DATASHEET]
Atmel-11100K-ATARM-SAM4S-Datasheet_09-Jun-15
For write operations:
If a null hold value is programmed on NWE, the SMC can guarantee a positive hold of address and NCS signal
after the rising edge of NWE. This is true for WRITE_MODE = 1 only. See Section 26.11.2 ”Early Read Wait
State”.
For read and write operations: a null value for pulse parameters is forbidden and may lead to unpredictable
behavior.
In read and write cycles, the setup and hold time parameters are defined in reference to the address bus. For
external devices that require setup and hold time between NCS and NRD signals (read), or between NCS and
NWE signals (write), these setup and hold times must be converted into setup and hold times in reference to the
address bus.
26.10 Scrambling/Unscrambling Function
The external data bus can be scrambled in order to prevent intellectual property data located in off-chip memories
from being easily recovered by analyzing data at the package pin level of either microcontroller or memory device.
The scrambling and unscrambling are performed on-the-fly without additional wait states.
The scrambling/unscrambling function can be enabled or disabled by configuring the CSxSE bits in the SMC
OCMS Mode Register (SMC_OCMS).
When multiple chip selects are handled, it is possible to configure the scrambling function per chip select using the
CSxSE bits in the SMC_OCMS register.
The scrambling method depends on two user-configurable key registers, SMC_KEY1 and SMC_KEY2. These key
registers are only accessible in Write mode.
The scrambling user key or the seed for key generation must be securely stored in a reliable non-volatile memory
in order to recover data from the off-chip memory. Any data scrambled with a given key cannot be recovered if the
key is lost.
26.11 Automatic Wait States
Under certain cir c umstances, the SMC automatically inserts idle cycles between accesses to avoid bus co ntentio n
or operation conflict.
26.11.1 Chip Select Wait States
The SMC always inserts an idle cycle between two transfers on separate chip selects. This idle cycle ensures that
there is no bus contention between the de-activation of one device and the activation of the ne xt one .
During chip select wait state, all control lines are turned inactive: NWR, NCS[0..3], NRD lines are all set to 1.
Figure 26-13 illustrates a chip select wait state between access on Chip Select 0 and Chip Select 2.
SAM4S Series [DATASHEET]
Atmel-11100K-ATARM-SAM4S-Datasheet_09-Jun-15
460
Figure 26-13. Chip Select Wait State between a Read Access on NCS0 and a Write Access on NCS2
26.11.2 Early Read Wait State
In some cases, the SMC inserts a wait st ate cycle between a writ e access and a read acce ss to allow time for the
write cycle to end before the subsequent read cycle begins. This wait state is not generated in addition to a chip
select wait state. The early read cycle thus only occurs between a write and read access to the same memory
device (same chip select).
An early read wait state is automatically inserted if at least one of the following conditions is valid:
if the write controlling signal has no hold time and the read controlling signal has no setup time (Figure 26-
14).
in NCS Write controlled mode (WRITE_MODE = 0), if there is no hold timing on the NCS signal and the
NCS_RD_SETUP parameter is set to 0, regardless of the Read mode (Figure 26-15). The write operation
must end with a NCS rising edge. Without an Early Read Wait S tate, the write operation could not complete
properly.
in NWE controlled mode (WRITE_MODE = 1) an d if ther e is no ho ld timing (NWE_HOLD = 0), th e feedba ck
of the write control signal is used to control address, data, and chip select lines. If the external write control
signal is not inactivated as expected due to load capacitances, an Early Read Wait State is inserted and
address, data and control signals are maintained one more cycle. See F i gu r e 26 -1 6 .
A[23:0]
NCS0
NRD_CYCLE
Chip Select
Wait State
NWE_CYCLE
MCK
NCS2
NRD
NWE
D[7:0]
Read to Write
Wait State
461
SAM4S Series [DATASHEET]
Atmel-11100K-ATARM-SAM4S-Datasheet_09-Jun-15
Figure 26-14. Early Read Wait State: Write with No Hold Followed by Read with No Setup
Figure 26-15. Early Read Wait State: NCS Controlled Write with No Hold Followed by a Read with No NCS Setup
write cycle Early Read
wait state
MCK
NRD
NWE
read cycle
no setup
no hold
D[7:0]
A[23:0]
write cycle
(WRITE_MODE = 0) Early Read
wait state
MCK
NRD
NCS
read cycle
no setup
no hold
D[7:0]
A[23:0]
(READ_MODE = 0 or READ_MODE = 1)
SAM4S Series [DATASHEET]
Atmel-11100K-ATARM-SAM4S-Datasheet_09-Jun-15
462
Figure 26-16. Early Read Wait State: NWE-controlled Write with No Hold Followed by a Read with one Set-up Cycle
26.11.3 Reload User Config u r at io n Wait State
The user may change any of the configuration parameters by writing the SMC user interface.
When detecting that a new user configuration has been written in the user inte rface, the SM C inserts a wait state
before starting the next access. This “Reload User Configuration Wait State” is us ed by the SMC to load the new
set of parameters to apply to next accesses.
The Reload Configuration Wait State is not applied in addition to the Chip Select Wait State. If accesses before
and after re-programming the user interface are made to different devices (Chip Selects), then one single Chip
Select Wait State is applied.
On the ot her hand , if access es before and afte r writing th e user inte rface ar e made to the same device, a Reload
Configuration Wait State is inserted, even if the change does not concern the current Chip Select.
26.11.3.1 User Procedure
To insert a Reload Configura tion Wait State, the SMC detects a write access to any SMC _MODE register of the
user interface. If the user only modifies timing registers (SMC_SETUP, SMC_PULSE, SMC_CYCLE registers) in
the user interface, he must validate the modification by writing the SMC_MODE, even if no change was made on
the mode parameters.
The user must not change the configur ation parameters of an SMC Chip Select (Setup, Pulse, Cycle, Mode) if
accesses are performed on this CS during the modification. Any change of the Chip Select para meters, while
fetching the code from a memory conn ected on this CS, may lead to unpredicta ble behavior. The instructions used
to modify the parameters of an SMC Chip Select can be executed from the internal RAM or from a memory
connected to another CS.
A
[25:2]
write cycle
(WRITE_MODE = 1) Early Read
wait state
MCK
NRD
internal write controlling signal
external write controlling signal
(NWE)
D[7:0]
read cycle
no hold read setup = 1
(READ_MODE = 0 or READ_MODE = 1)
463
SAM4S Series [DATASHEET]
Atmel-11100K-ATARM-SAM4S-Datasheet_09-Jun-15
26.11.3.2 Slow Clock Mode Transition
A Reload Configuration Wait State is also inserted when the Slo w Clock m ode is entered or exited , after the end of
the current transfer (see Section 26.14 ”Slow Clock Mode”).
26.11.4 Read to Write Wait State
Due to an internal mechanism, a wait cycle is always inserted between consecutive read and write SMC accesses.
This wait cycle is referred to as a read to write wait state in this document.
This wait cycle is applied in addition to chip select and reload user configuration wait states when they are to be
inserted. See Figure 26-13 on page 460.
SAM4S Series [DATASHEET]
Atmel-11100K-ATARM-SAM4S-Datasheet_09-Jun-15
464
26.12 Data Float Wait States
Some memory devices are slow to release the external bus. For such devices, it is necessary to add wait states
(data float wait states) after a read access:
before starting a read access to a different external memory
before starting a write access to the same device or to a differen t external one.
The Data Float Output Time (tDF) for each ex ternal memor y device is programmed in the TDF_ CYCLES field o f the
SMC_MODE register for the corresponding chip select. The value of TDF_CYCLES ind icates the num ber of data
float wait cycles (between 0 and 15) before the external device releases the bus, and represents the time allowed
for the data output to go to high impedance after the memory is disabled.
Data float wait states do not delay internal memory accesses. Hence, a single access to an external memory with
long tDF will not slow down the execution of a program from internal memory.
The data float wait states management depends on the READ_MODE and the TDF_MODE fields of the
SMC_MODE register for the corresponding chip select.
26.12.1 READ_MODE
Setting the READ_MODE to 1 indicates to the SMC that the NRD signal is responsible for turning off the tri-state
buffers of the external memory device. The Data Float Period then begins after the rising edge of the NRD signal
and lasts TDF_CYCLES MCK cycles.
When the read ope ration is controlled by the NCS sign al (READ_MODE = 0), the TD F field gives the number of
MCK cycles during which the data bus remains busy after the rising edge of NCS.
Figure 26-17 illustrates the Data Float Period in NRD-controlled mode (READ_MODE =1), assuming a data float
period of 2 cycles (TDF_CYCLES = 2). Figure 26-18 shows the read operation when controlled by NCS
(READ_MODE = 0) and the TDF_CYCLES parameter equals 3.
Figure 26-17. TDF Period in NRD Contr olle d Read Access (TDF = 2)
NCS
NRD controlled read operation
tpacc
MCK
NRD
D[7:0]
TDF = 2 clock cycles
A[23:0]
465
SAM4S Series [DATASHEET]
Atmel-11100K-ATARM-SAM4S-Datasheet_09-Jun-15
Figure 26-18. TDF Period in NCS Controlled Read Operation (TDF = 3)
26.12.2 TDF Optimization Enabled (TDF_MODE = 1)
When the TDF_MODE of the SMC_MODE register is set to 1 (TDF optimization is enabled), the SMC takes
advantage of the setup period of the next access to optimize the number of wait states cycle to insert.
Figure 26-19 shows a read access controlled by NRD, followed by a write access controlled by NWE, on Chip
Select 0. Chip Select 0 has been programmed with :
NRD_HOLD = 4; READ_MODE = 1 (NRD controlled)
NWE_SETUP = 3; WRITE_MODE = 1 (NWE controlled)
TDF_CYCLES = 6; TDF_MODE = 1 (optimization enabled).
NCS
TDF = 3 clock cycles
tpacc
MCK
D[7:0]
NCS controlled read operation
A[23:0]
NRD
SAM4S Series [DATASHEET]
Atmel-11100K-ATARM-SAM4S-Datasheet_09-Jun-15
466
Figure 26-19. TDF Optimization: No TDF wait states are inserted if the TDF period is over when the next acce ss begins
26.12.3 TDF Optimization Disabled (TDF_MODE = 0)
When optimization is disabled, tdf wait states ar e inserted at the end of the read transfer, so that the d ata float
period is ended when the second access begins. If the hold period of the read1 controlling signal overlaps the data
float period, no additional tdf wait states will be inserted.
Figure 26-20, Figure 26-21 and Figure 26-22 illustrate the cases:
read access followed by a read access on another chip select,
read access followed by a write access on another chip select,
read access followed by a write access on the same chip select,
with no TDF optimization.
NCS0
MCK
NRD
NWE
D[7:0]
Read to Write
Wait State
TDF_CYCLES = 6
read access on NCS0 (NRD controlled)
NRD_HOLD= 4
NWE_SETUP= 3
write access on NCS0 (NWE controlled)
467
SAM4S Series [DATASHEET]
Atmel-11100K-ATARM-SAM4S-Datasheet_09-Jun-15
Figure 26-20. TDF Optimization Disabled (TDF Mode = 0): TDF wait states between 2 read accesses on different chip selects
Figure 26-21. TDF Mode = 0: TDF wait states between a read and a write access on different chip selects
TDF_CYCLES = 6
TDF_CYCLES = 6 TDF_MODE = 0
A[
23:0]
read1 cycle
Chip Select
Wait State
MCK
read1 controlling signal
(NRD)
read2 controlling signal
(NRD)
D[7:0]
read1 hold = 1
read 2 cycle
read2 setup = 1
5 TDF WAIT STATES
(optimization disabled)
TDF_CYCLES = 4
TDF_CYCLES = 4 TDF_MODE = 0
(optimization disabled)
A
[23:0]
read1 cycle
Chip Select
Wait State
Read to Write
Wait State
MCK
read1 controlling signal
(NRD)
write2 controlling signal
(NWE)
D[7:0]
read1 hold = 1
write2 cycle
write2 setup = 1
2 TDF WAIT STATES
SAM4S Series [DATASHEET]
Atmel-11100K-ATARM-SAM4S-Datasheet_09-Jun-15
468
Figure 26-22. TDF Mode = 0: TDF wait states between read and write accesses on the same chip select
26.13 External Wait
Any access can be extended by an external device using the NWAIT input signal of the SMC. The EXNW_MODE
field of the SMC_MODE register on the correspon din g chip select must be set either to “10” ( Froze n mo de) or “ 11 ”
(Ready mode). When the EXNW_MODE is set to “00” (disabled), the NWAIT signal is simply ignored on the
corresponding chip select. The NWAIT signal delays the read or write operation in regards to the read or write
controlling signal, depending on the Read and Write modes of the corresponding chip select.
26.13.1 Restriction
When one of the EXNW_MODE is enabled, it is mandatory to program at least one hold cycle for the
read/write controlling signal. For that reason, the NWAIT signal cannot be used in Page mode (Section
26.15 ”Asynchronous Page Mode”), or in Slow clock mode (Sec ti o n 26 .1 4 ”Slo w Clo ck Mo de ”).
The NWAIT signal is as sume d to be a respon se of th e exte rnal d evice to the read /w rite requ est of the SMC. Then
NWAIT is examined by the SMC only in the pulse state of the read or write controlling signal. The assertion of the
NWAIT signal outside the expected period has no impact on SMC behavior.
TDF_CYCLES = 5
TDF_CYCLES = 5 TDF_MODE = 0
(optimization disabled)
A
[23:0]
read1 cycle
Read to Write
Wait State
MCK
read1 controlling signal
(NRD)
write2 controlling signal
(NWE)
D[7:0]
read1 hold = 1
write2 cycle
write2 setup = 1
4 TDF WAIT STATES
469
SAM4S Series [DATASHEET]
Atmel-11100K-ATARM-SAM4S-Datasheet_09-Jun-15
26.13.2 Frozen Mode
When the external device asserts the NWAIT signal (active low), and after internal synchronization of this signal,
the SMC state is frozen, i.e., SMC internal counters are frozen, and all control signals r emain unchanged. When
the resynchronized NWAIT signal is deasserted, the SMC completes the access, resuming the access from the
point where it was stopped. See Figure 26-23. This mode must be selected when the external device uses the
NWAIT signal to delay the access and to freeze the SMC.
The assertion of the NWAIT signal outside the expected period is ignored as illustrated in Figure 26-24.
Figure 26-23. Write Access with NWAIT Assertion in Frozen Mode (EXNW_MODE = 10)
EXNW_MODE = 10 (Frozen)
WRITE_MODE = 1 (NWE_controlled)
NWE_PULSE = 5
NCS_WR_PULSE = 7
A
[23:0]
MCK
NWE
NCS
432 1 1101
4563222210
Write cycle
D[7:0]
NWAIT
FROZEN STATE
internally synchronized
NWAIT signal
SAM4S Series [DATASHEET]
Atmel-11100K-ATARM-SAM4S-Datasheet_09-Jun-15
470
Figure 26-24. Read Access with NWAIT Assertion in Frozen Mode (EXNW_MODE = 10)
EXNW_MODE = 10 (Frozen)
READ_MODE = 0 (NCS_controlled)
NRD_PULSE = 2, NRD_HOLD = 6
NCS_RD_PULSE =5, NCS_RD_HOLD =3
A
[23:0]
MCK
NCS
NRD 10
43
43
2
555
22 0 210
210
1
Read cycle
Assertion is ignored
NWAIT
internally synchronized
NWAIT signal
FROZEN STATE
471
SAM4S Series [DATASHEET]
Atmel-11100K-ATARM-SAM4S-Datasheet_09-Jun-15
26.13.3 Ready Mode
In Ready mode (EXNW_MODE = 11), the SMC beha ves differently. Normally, the SMC begins the access by
down counting the setup and pulse counters of the read/write controlling signal. In the last cycle of the pulse
phase, the resynchronized NWAIT signal is examined.
If asserted, the SMC suspends the access as shown in Figure 26-25 and Figure 26-26. After deassertion, the
access is completed: the hold step of the access is performed.
This mode must be selected when the external device uses deassertion of the NWAIT signal to indicate its ability
to complete the read or write operation.
If the NWAIT signal is deasserted before the end of the pulse, or asserted after the end of the pulse of the
controlling read/write signal, it has no impact on the access length as shown in Figure 26-26.
Figure 26-25. NWAIT Assertion in Write Acce ss: Read y Mode (EXNW_MODE = 11)
EXNW_MODE = 11 (Ready mode)
WRITE_MODE = 1 (NWE_controlled)
NWE_PULSE = 5
NCS_WR_PULSE = 7
A
[23:0]
MCK
NWE
NCS
4321 000
456 321110
Write cycle
D[7:0]
NWAIT
internally synchronized
NWAIT signal
Wait STATE
SAM4S Series [DATASHEET]
Atmel-11100K-ATARM-SAM4S-Datasheet_09-Jun-15
472
Figure 26-26. NWAIT Assertion in Read Access: Ready Mode (EXNW_MODE = 11)
EXNW_MODE = 11(Ready mode)
READ_MODE = 0 (NCS_controlled)
NRD_PULSE = 7
NCS_RD_PULSE =7
A[23:0]
MCK
NCS
NRD
456 3200
0
1
456 3211
Read cycle
Assertion is ignored
NWAIT
internally synchronized
NWAIT signal
Wait STATE
Assertion is ignored
473
SAM4S Series [DATASHEET]
Atmel-11100K-ATARM-SAM4S-Datasheet_09-Jun-15
26.13.4 NWAIT Latency and Read/Write Timings
There may be a latency between the assertion of the read/write controlling signal and the assertion of the NWAIT
signal by the device. The programmed pulse length of the read/write controlling signal must be at least equal to
this latency plus the 2 cycles of resynchron ization + one cycle. Otherwise, the SMC ma y enter the ho ld state of th e
access without detecting the NWAIT signal assertion. This is true in Frozen mode as well as in Ready mode. This
is illustrated on Figure 26-27.
When EXNW_MODE is enabled (ready or frozen), the user must program a pulse length of the read and write
controlling signal of at least:
minimal pulse length = NWAIT latency + 2 resynchronization cycles + one cycle
Figure 26-27. NWAIT Latency
EXNW_MODE = 10 or 11
READ_MODE = 1 (NRD_controlled)
NRD_PULSE = 5
A
[23:0]
MCK
NRD
43 210 00
Read cycle
minimal pulse length
NWAIT latency
NWAIT
intenally synchronized
NWAIT signal
WAIT STATE
2 cycle resynchronization
SAM4S Series [DATASHEET]
Atmel-11100K-ATARM-SAM4S-Datasheet_09-Jun-15
474
26.14 Slow Clock Mode
The SMC is able to automatically apply a set of “Slow clock mode” read/write waveforms when an internal signal
driven by the Power Management Controller is asserted because MCK has been turned to a very slow clock rate
(typically 32kHz clock rate). In this mode, the user-programmed waveforms are ignored and the Slow clock mode
waveforms are applied. This mode is provided so as to avoid reprogramming the User Interface with appropriate
waveforms at very slow clock rate. When activated, the Slow mode is active on all chip selects.
26.14.1 Slow Clock Mode Waveforms
Figure 26-28 illustrates the read and write operations in Slow clock mode. They are valid on all chip selects. Table
26-6 indicates the value of read and write parameters in Slow clock mode.
Figure 26-28. Read /Write Cycles in Slow Clock Mode
A[
23:0]
NCS
1
MCK
NWE 1
1
NWE_CYCLE = 3
A
[23:0]
MCK
NRD
NRD_CYCLE = 2
11
NCS
SLOW CLOCK MODE WRITE SLOW CLOCK MODE READ
Table 26-6. Read and Write Timing Parameters in Slow Clock Mode
Read Parameters Duration (cycles) Write Parameters Duration (cycles)
NRD_SETUP 1 NWE_SETUP 1
NRD_PULSE 1 NWE_PULSE 1
NCS_RD_SETUP 0 NCS_WR_SETUP 0
NCS_RD_PULSE 2 NCS_WR_PULSE 3
NRD_CYCLE 2 NWE_CYCLE 3
475
SAM4S Series [DATASHEET]
Atmel-11100K-ATARM-SAM4S-Datasheet_09-Jun-15
26.14.2 Switching from (to) Slow Clock Mode to (from) Normal Mode
When switching from Slow clock mode to Nor mal mode , the current Slow clock mode transfer is completed at high
clock rate, with the set of Slow clock mode parameters.See Figure 26-29. The external device may not be fast
enough to support such timings.
Figure 26-30 illus trates the recommended procedure to properly switch from one mode to the other.
Figure 26-29. Clock Rate Transition Occurs while the SMC is Performing a Write Operation
Figure 26-30. Recommended Procedure to Switch from Slow Clock Mode to Normal Mode or from Normal Mode to Slow Clock
Mode
A
[23:0]
NCS
1
MCK
NWE
1
1
NWE_CYCLE = 3
SLOW CLOCK MODE WRITE
Slow Clock Mode
internal signal from PMC
111 2 32
NWE_CYCLE = 7
NORMAL MODE WRITE
Slow clock mode
transition is detected:
Reload Configuration Wait State
This write cycle finishes with the slow clock mode set
of parameters after the clock rate transition
SLOW CLOCK MODE WRITE
A
[23:0]
NCS
1
MCK
NWE
1
1
SLOW CLOCK MODE WRITE
Slow Clock Mode
internal signal from PMC
232
NORMAL MODE WRITEIDLE STATE
Reload Conguration
Wait State
SAM4S Series [DATASHEET]
Atmel-11100K-ATARM-SAM4S-Datasheet_09-Jun-15
476
26.15 Asynchronous Page Mode
The SMC supports asynchronous burst reads in Page mode, providing that the Page mode is enabled in the
SMC_MODE r egister (PME N field). T he pa ge size must be configured in the SMC_MODE register (PS field) to 4,
8, 16 or 32 bytes.
The page defines a set of consecutive bytes into memory. A 4-byte page (resp. 8-, 16-, 32-byte page) is always
aligned to 4-byte boundaries (resp. 8-, 16-, 32-byte boundaries) of memory. The MSB of data address defines the
address of the page in memo ry, the LSB of a ddr ess defi ne the addr ess of the data in the page as detailed in Table
26-7.
With Page mode memory devices, the first access to one page (tpa) takes longer than the subsequent accesses to
the page (tsa) as shown in Figure 26-31. When in Page mod e, the SMC enables the user to define different read
timings for the first access within one page, and next accesses within the page.
Note: 1. “A” deno tes the address bus of the memory device.
26.15.1 Protocol and Timings in Page Mode
Figure 26-31 shows the NRD and NCS timings in Page mode access.
Figure 26-31. Page Mode Rea d Pro t ocol (Address MSB and LSB are defined in Table 26-7)
The NRD and NCS signals are held low during all read transfers, whatever the programmed values of the setup
and hold timings in the User Interface ma y be. Moreover , the NRD and NCS timings are iden tical. The pulse length
of the first access to the page is defined with the NCS_RD_PULSE field of the SMC_PULSE register. The pulse
length of subsequent accesses within the page are defined using the NRD_PULSE parameter.
Table 26-7. Page Address and Data Address within a Page
Page Size Page Address(1) Data Address in the Page
4 bytes A[23:2] A[1:0]
8 bytes A[23:3] A[2:0]
16 bytes A[23: 4] A[3:0]
32 bytes A[23: 5] A[4:0]
A[MSB]
NCS
MCK
NRD
D[7:0]
NCS_RD_PULSE NRD_PULSE
NRD_PULSE
tsatpatsa
A[LSB]
477
SAM4S Series [DATASHEET]
Atmel-11100K-ATARM-SAM4S-Datasheet_09-Jun-15
In Page mode, the programming of the read timings is described in Table 26-8:
The SMC does not check the co herency of timings. It will always apply the NCS_RD_PULSE timings as page
access timing (tpa) and the NRD_PULSE for accesses to the page (tsa), e ven if the progra mmed value for t pa is
shorter than the programmed value for tsa.
26.15.2 Page Mode Restriction
The Page mode is not compatible with the use of the NWAIT signal. Using the Page mode and the NWAIT signal
may lead to unpredictable behavior.
26.15.3 Sequential and Non-sequential Access es
If the chip select and the MSB of addresses as defined in Table 26-7 are identical, then the current access lies in
the same page as the previous one, and no page break occurs.
Using this information, all data within the same page, sequential or not sequential, are accessed with a minimum
access time (tsa). Figure 26-32 illustrates access to an 8-bit memory device in Page mode, with 8-byte pages.
Access to D1 causes a page access with a long access time (tpa). Accesses to D3 and D7, though they are not
sequential accesses, only require a short access time (tsa).
If the MSB of addresses are different, the SMC performs the access of a new page. In the same way, if the chip
select is different from the previous access, a page break occurs. If two sequential accesses are ma de to the Page
mode memory, but separated by an other internal or ex ternal peripheral access, a page break occurs on the
second access because the chip select of the device was deasserted between both accesses.
Table 26-8. Programming of Read Timings in Page Mode
Parameter Value Definition
READ_MODE ‘x’ No impact
NCS_RD_SETUP ‘x’ No impact
NCS_RD_PULSE tpa Access time of first access to the page
NRD_SETUP ‘x’ No impact
NRD_PULSE tsa Access time of subsequent accesses in the page
NRD_CYCLE ‘x’ No impact
SAM4S Series [DATASHEET]
Atmel-11100K-ATARM-SAM4S-Datasheet_09-Jun-15
478
Figure 26-32. Access to Non-Sequ en tial Data within the Same Page
A
[23:3]
A[2], A1, A0
NCS
MCK
NRD
Page address
A1 A3 A7
D[7:0]
NCS_RD_PULSE NRD_PULSE
NRD_PULSE
D1 D3 D7
479
SAM4S Series [DATASHEET]
Atmel-11100K-ATARM-SAM4S-Datasheet_09-Jun-15
26.16 Static Memory Controller (SMC) User Interface
The SMC is program med using the registers listed in Table 26- 9. For each chip select, a set of four registers is used to pro-
gram the parameters of the external device connected on it. In Table 26-9, “CS_number” denotes the chip select number.
16 bytes (0x10) are required per chip select.
The user must complete writing the configuration by writing any one of the SMC_MODE registers.
Notes: 1. All unlisted offset values are considered as ‘reserved’.
Table 26-9 . Register Mapping
Offset Register Name Access Reset
0x10 x CS_number + 0x00 SMC Setup Register SMC_SETUP Read/Write 0x01010101
0x10 x CS_number + 0x04 SMC Pulse Register SMC_PULSE Read/write 0x01010101
0x10 x CS_number + 0x08 SMC Cycle Register SMC_CYCLE Read/Write 0x00030003
0x10 x CS_number + 0x0C SMC MODE Register SMC_MODE Read/Write 0x10000003
0x80 SMC OCMS MODE Register SMC_OCMS Read/Write 0x00000000
0x84 SMC OCMS KEY1 Register SMC_KEY1 Write Once 0x00000000
0x88 SMC OCMS KEY2 Register SMC_KEY2 Write Once 0x00000000
0xE4 SMC Write Protection Mode Register SMC_WPMR Read/Write 0x00000000
0xE8 SMC Write Protection Status Register SMC_W P SR Rea d-only 0x00000000
0xEC-0xFC Reserved – – –
SAM4S Series [DATASHEET]
Atmel-11100K-ATARM-SAM4S-Datasheet_09-Jun-15
480
26.16.1 SMC Setup Register
Name: SMC_SETUP[0..3]
Address: 0x400E0000 [0], 0x400E0010 [1], 0x400E0020 [2], 0x400E0030 [3]
Access: Read/Write
This register can only be written if the WPEN bit is cleared in the “SMC Write Protection Mode Register” .
• NWE_SETUP: NWE Setup Length
The NWE signal setup length is defined as:
NWE setup length = (128* NWE_SETUP[5] + NWE_SETUP[4:0]) clock cycles
• NCS_WR_SETUP: NCS Setup Length in WRITE Access
In write access, the NCS signal setup length is defined as:
NCS setup length = (128* NCS_WR_SETUP[5] + NCS_WR_SETUP[4:0]) clock cycles
• NRD_SETUP: NRD Setup Length
The NRD signal setup length is defined in clock cycles as:
NRD setup length = (128* NRD_SETUP[5] + NRD_SETUP[4:0 ]) clock cycles
• NCS_RD_SETUP: NCS Setup Length in READ Access
In read access, the NCS signal setup length is defined as:
NCS setup length = (128* NCS_RD_SETUP[5] + NCS_RD_SETUP[4:0]) clock cycles
31 30 29 28 27 26 25 24
– – NCS_RD_SETUP
23 22 21 20 19 18 17 16
– – NRD_SETUP
15 14 13 12 11 10 9 8
– – NCS_WR_SETUP
76543210
– – NWE_SETUP
481
SAM4S Series [DATASHEET]
Atmel-11100K-ATARM-SAM4S-Datasheet_09-Jun-15
26.16.2 SMC Pulse Register
Name: SMC_PULSE[0..3]
Address: 0x400E0004 [0], 0x400E0014 [1], 0x400E0024 [2], 0x400E0034 [3]
Access: Read/Write
This register can only be written if the WPEN bit is cleared in the “SMC Write Protection Mode Register” .
• NWE_PULSE: NWE Pulse Length
The NWE signal pulse length is defined as:
NWE pulse length = (256* NWE_PULSE[6] + NWE_PULSE[5:0]) clock cycles
The NWE pulse length must be at least 1 clock cycle.
• NCS_WR_PULSE: NCS Pulse Length in WRITE Access
In write access, the NCS signal pulse length is defined as:
NCS pulse length = (256* NCS_WR_PULSE[6] + NCS_WR_PULSE[5:0]) clock cycles
The NCS pulse length must be at least 1 clock cycle.
• NRD_PULSE: NRD Pulse Length
In standard read access, the NRD signal pulse length is defined in clock cycles as:
NRD pulse length = (256* NRD_PULSE[6] + NRD_PULSE[5:0]) clock cycles
The NRD pulse length must be at least 1 clock cycle.
In Page mode read access, the NRD_PULSE parameter defines the duration of the subsequent accesses in the page.
• NCS_RD_PULSE: NCS Pulse Length in READ Access
In standard read access, the NCS signal pulse length is defined as:
NCS pulse length = (256* NCS_RD_PULSE[6] + NCS_RD_PULSE[5:0]) clock cycles
The NCS pulse length must be at least 1 clock cycle.
In Page mode read access, the NCS_RD_PULSE parameter defines the duration of the first access to one page.
31 30 29 28 27 26 25 24
– NCS_RD_PULSE
23 22 21 20 19 18 17 16
– NRD_PULSE
15 14 13 12 11 10 9 8
– NCS_WR_PULSE
76543210
–NWE_PULSE
SAM4S Series [DATASHEET]
Atmel-11100K-ATARM-SAM4S-Datasheet_09-Jun-15
482
26.16.3 SMC Cycle Register
Name: SMC_CYCLE[0..3]
Address: 0x400E0008 [0], 0x400E0018 [1], 0x400E0028 [2], 0x400E0038 [3]
Access: Read/Write
This register can only be written if the WPEN bit is cleared in the “SMC Write Protection Mode Register” .
• NWE_CYCLE: Tota l Write Cycle Length
The total write cycle length is the total duration in clock cycles of the write cycle. It is equal to the sum of the setup, pul se
and hold steps of the NWE and NCS signals. It is defined as:
Write cycle length = (NWE_CYCLE[8:7]*256 + NWE_CYCLE[6:0]) clock cycles
• NRD_CYCLE: Total Read Cycle Length
The total read cycle length is the total duration in clock cycles of the read cycle. It is equal to the sum of the setup, pulse
and hold steps of the NRD and NCS signals. It is defined as:
Read cycle length = (NRD_CYCLE[8:7]*256 + NRD_CYCLE[6:0]) clock cycles
31 30 29 28 27 26 25 24
–––––––NRD_CYCLE
23 22 21 20 19 18 17 16
NRD_CYCLE
15 14 13 12 11 10 9 8
–––––––NWE_CYCLE
76543210
NWE_CYCLE
483
SAM4S Series [DATASHEET]
Atmel-11100K-ATARM-SAM4S-Datasheet_09-Jun-15
26.16.4 SMC MODE Register
Name: SMC_MODE[0..3]
Address: 0x400E000C [0], 0x400E001C [1], 0x400E002C [2], 0x400E003C [3]
Access: Read/Write
This register can only be written if the WPEN bit is cleared in the “SMC Write Protection Mode Register” .
• READ_MODE: Read Mode
0: The read operation is controlled by the NCS signal.
– If TDF cycles are programmed, the external bus is marked busy after the rising edge of NCS.
– If TDF optimization is enabled (TDF_MODE =1), TDF wait states are inserted after the setup of NCS.
1: The read operation is controlled by the NRD signal.
– If TDF cycles are programmed, the external bus is marked busy after the rising edge of NRD.
– If TDF optimization is enabled (TDF_MODE =1), TDF wait states are inserted after the setup of NRD.
• WRITE_MODE: Write Mode
0: The write operation is controlled by the NCS sign a l.
– If TDF optimization is enabled (TDF_MODE =1), TDF wait states will be inserted after the setup of NCS.
1: The write opera tio n is con trolle d by th e NWE sign a l.
– If TDF optimization is enabled (TDF_MODE =1), TDF wait states will be inserted after the setup of NWE.
• EXNW_MODE: NWAIT Mode
The NWAIT signal is used to extend the current read or write signal. It is only take n into a ccount during th e pulse ph ase of
the read and write controlling signal. When the use of NWAIT is enabled, at least one cycle hold duration must be pro-
grammed for the read and write controlling signal.
• Disabled Mode: The NWAIT input signal is ignored on the corresponding Chip Select.
• Frozen Mode: If asserted, the NWAIT signal freezes the current read or write cycle. After deassertion, the read/write
cycle is resumed from the point where it was stopped.
31 30 29 28 27 26 25 24
–– PS –– –PMEN
23 22 21 20 19 18 17 16
– – – TDF_MODE TDF_CYCLES
15 14 13 12 11 10 9 8
–––––– – –
765432 1 0
– – EXNW_MODE – – WRITE_MODE READ_MODE
Value Name Description
0 DISABLED Disabled
1– Reserved
2 FROZEN Frozen Mode
3 READY Ready Mode
SAM4S Series [DATASHEET]
Atmel-11100K-ATARM-SAM4S-Datasheet_09-Jun-15
484
• Ready Mode: The NWAIT signal indicates the av ailability of the external de vice at the end of the pulse of the controlling
read or write signal, to complet e the acce ss. If high, the a ccess normally completes. I f low, the access is extended until
NWAIT returns high.
• TDF_CYCLES: Data Float Time
This field gives the integer number of clock cycles required by the external device to release the data after the rising edge
of the read controlling signal. The SMC always provide one full cycle of bus turnaround after the TDF_CYCLES period. The
external bus cannot be used by another chip select during TDF_CYCLES + 1 cycles. From 0 up to 15 TDF_CYCLES can
be set.
• TDF_MODE: TDF Optimization
0: TDF optimization is disabled.
– The number of TDF wait states is inserted before the next access begins.
1: TDF optimization is enabled.
– The number of TDF wait states is optimiz ed using the setup period of the next read/write access.
• PMEN: Page Mode Enabled
0: Standard read is applied.
1: Asynchronous burst read in Page mode is applied on the corresponding chip select.
• PS: Page Size
If Page mode is enabled, this field indicates the size of the page in bytes.
Value Name Description
0 4_BYTE 4-byte page
1 8_BYTE 8-byte page
2 16_BYTE 16-byte page
3 32_BYTE 32-byte page
485
SAM4S Series [DATASHEET]
Atmel-11100K-ATARM-SAM4S-Datasheet_09-Jun-15
26.16.5 SMC OCMS Mode Register
Name: SMC_OCMS
Address: 0x400E0080
Access: Read/Write
• CSxSE: Chip Select (x = 0 to 3) Scrambling Enable
0: Disable scrambling for CSx.
1: Enable scrambling for CSx.
• SMSE: Static Memory Controller Scrambling Enable
0: Disable scrambling for SMC access.
1: Enable scrambling for SMC access.
31 30 29 28 27 26 25 24
––––––––
23 22 21 20 19 18 17 16
––––CS3SECS2SECS1SECS0SE
15 14 13 12 11 10 9 8
––––––––
76543210
–––––––SMSE
SAM4S Series [DATASHEET]
Atmel-11100K-ATARM-SAM4S-Datasheet_09-Jun-15
486
26.16.6 SMC OCMS Key1 Register
Name: SMC_KEY1
Address: 0x400E0084
Access: Write Once
• KEY1: Off Chip Memory Scrambling (OCMS) Key Part 1
When off-chip memory scrambling is enabled, setting the SMC_OCMS and SMC_TIMINGS registers in accordance, the
data scrambling depends on KEY1 and KEY2 values.
31 30 29 28 27 26 25 24
KEY1
23 22 21 20 19 18 17 16
KEY1
15 14 13 12 11 10 9 8
KEY1
76543210
KEY1
487
SAM4S Series [DATASHEET]
Atmel-11100K-ATARM-SAM4S-Datasheet_09-Jun-15
26.16.7 SMC OCMS Key2 Register
Name: SMC_KEY2
Address: 0x400E0088
Access: Write Once
• KEY2: Off Chip Memory Scrambling (OCMS) Key Part 2
When off-chip memory scrambling is enabled, setting the SMC_OCMS and SMC_TIMINGS registers in accordance, the
data scrambling depends on KEY2 and KEY1 values.
31 30 29 28 27 26 25 24
KEY2
23 22 21 20 19 18 17 16
KEY2
15 14 13 12 11 10 9 8
KEY2
76543210
KEY2
SAM4S Series [DATASHEET]
Atmel-11100K-ATARM-SAM4S-Datasheet_09-Jun-15
488
26.16.8 SMC Write Protection Mo d e Re gi st er
Name: SMC_WPMR
Address: 0x400E00E4
Access: Read/Write
• WPEN: Write Protec t En ab le
0: Disables the write protection if WPKEY corresponds to 0x534D43 (“SMC” in ASCII).
1: Enables the write protection if WPKEY corresponds to 0x534D43 (“SMC” in ASCII).
See Section 26.9.5 ”Register Write Protection” for the list of registers that can be write-protected.
• WPKEY: Write Protection Key
31 30 29 28 27 26 25 24
WPKEY
23 22 21 20 19 18 17 16
WPKEY
15 14 13 12 11 10 9 8
WPKEY
76543210
———————WPEN
Value Name Description
0x534D43 PASSWD Writing any othe r val ue in this field aborts the write operation of the WPEN bit. Always reads
as 0.
489
SAM4S Series [DATASHEET]
Atmel-11100K-ATARM-SAM4S-Datasheet_09-Jun-15
26.16.9 SMC Write Protection Status Register
Name: SMC_WPSR
Address: 0x400E00E8
Type: Read-only
• WPVS: Write Protection Violation Status
0: No write protec tion v iola tio n ha s occ ur re d since the last read of the SMC_WPSR register.
1: A write protection violation has occurred since the last read of the SMC_WPSR register. If this violation is an unauthor-
ized attempt to write a protected register, the associated violation is reported into field WPVSRC.
• WPVSRC: Write Protection Violation Source
When WPVS = 1, WPVSRC indicates the register address offset at which a write access has been attempted.
31 30 29 28 27 26 25 24
————————
23 22 21 20 19 18 17 16
WPVSRC
15 14 13 12 11 10 9 8
WPVSRC
76543210
———————WPVS
SAM4S Series [DATASHEET]
Atmel-11100K-ATARM-SAM4S-Datasheet_09-Jun-15
490
27. Peripheral DMA Controller (PDC)
27.1 Description
The Peripheral DMA Controller (PDC) transfers data between on-chip serial peripherals and the target memories.
The link between the PDC and a serial peripheral is operated by the AHB to APB bridge.
The user interface of each PDC channel is integrated into the user interface of the peripheral it serves. The u ser
interface of mono-direction al channels (receive- only or tr ansmit-only) contains two 32-bit memory pointers and two
16-bit counters , one set (pointer, counter) fo r the current transfer and one s et (pointer, counter) for the nex t
transfer. The bidirectional channel user interface contains four 32-bit memory pointers and four 16-bit counters.
Each set (pointer, counter) is used by the current transmit, next transmit, current receive and next receive.
Using the PDC decreases processor overhead by reducing its intervention during the transfer. This lowers
significantly the number of clock cycles required for a data transfer, improving microcontroller performance.
To launch a transfer, the peripheral triggers its associated PDC channels by using transmit and receive signals.
When the programmed data is transferred, an end of transfer interrupt is generated by the peripheral itself.
27.2 Embedded Characteristics
Performs Transfers to/from APB Communication Serial Peripherals
Supports Half-duplex and Full-duplex Peripherals
491
SAM4S Series [DATASHEET]
Atmel-11100K-ATARM-SAM4S-Datasheet_09-Jun-15
27.3 Peripheral DMA Controller Connections
The Peripheral DMA Controller handles the data transfer between peripherals and memory and receives triggers
from the peripherals listed in the following table.
The Peripheral DMA Controller handles transfer requests from the channel according to the following priorities
(Channel 0 is high priority):
Table 27-1. Peripheral DMA Controller
Instance Name Channel T/R Channel Number
PWM Transmit 21
TWI1 Transmit 20
TWI0 Transmit 19
UART1 Transmit 18
UART0 Transmit 17
USART1 Transmit 16
USART0 Transmit 15
DACC Transmit 14
SPI Transmit 13
SSC Transmit 12
HSMCI Transmit 11
PIOA Receive 10
TWI1 Receive 9
TWI0 Receive 8
UART1 Receive 7
UART0 Receive 6
USART1 Receive 5
USART0 Receive 4
ADC Receive 3
SPI Receive 2
SSC Receive 1
HSMCI Receive 0
SAM4S Series [DATASHEET]
Atmel-11100K-ATARM-SAM4S-Datasheet_09-Jun-15
492
27.4 Block Diagram
Figure 27-1. Block Diagram
PDC
FULL DUPLEX
PERIPHERAL
THR
RHR
PDC Channel A
PDC Channel B
Control
Status & Control
Control
PDC Channel C
HALF DUPLEX
PERIPHERAL
THR
Status & Control
RECEIVE or TRANSMIT
PERIPHERAL
RHR or THR
Control
Control
RHR
PDC Channel D
Status & Control
493
SAM4S Series [DATASHEET]
Atmel-11100K-ATARM-SAM4S-Datasheet_09-Jun-15
27.5 Functional Description
27.5.1 Configuration
The PDC channel user interface enables the user to configure and control data transfers for each channel. The
user interface of each PDC channel is integrated into the associated peripheral user interface.
The user interface of a serial pe ripheral, whether it is full- or half-duplex, contains four 32-bit pointers (RPR,
RNPR, TPR, TNPR) and four 16-bit counter registers (RCR, RNCR, TCR, TNCR). However, the transmit and
receive parts of each type are programmed differently: the transmit and receive parts of a full-duplex peripheral
can be programmed at the same time, whereas only one part (transmit or receive) of a half-duplex peripheral can
be programmed at a time.
32-bit pointers define the access location in memory for the current and next transfer, whether it is for read
(transmit) or write (receive). 16-bit counters define the size of the current and next transfers. It is possible, at any
moment, to read the number of transfers remaining for each channel.
The PDC has dedicated status registers which indicate if the transfer is enabled or disabled for each channel. The
status for each channel is located in the associated peripheral status register . Transfers can be enabled and/or
disabled by setting TXTEN/TXTDIS and RXTEN/RXTDIS in the peripheral’s Transfer Control register.
At the end of a transfer, the PDC channel sends status flags to its associated peripheral. These flags are visible in
the peripheral Status register (ENDRX, ENDTX, RXBUFF, and TXBUFE). Refer to Section 27.5.3 and to the
associated peripheral user interface.
The peripheral where a PDC transfer is configured must have its peripheral clock enabled. The peripheral clock
must be also enabled to access the PDC register set associated to this peripheral.
27.5.2 Memory Pointers
Each full-duplex peripheral is connected to the PDC by a receive channel and a transmit channel. Both channels
have 32-bit memory pointers that po int to a receive area and to a transmit area, resp ectively, in the target memor y.
Each half-duplex peripheral is con nected to the PDC by a bidirectional channel. This channel has two 32-bit
memory pointers, one for current transfer and the other for next transfer. These pointers point to transmit or
receive data depending on the operating mode of the peripheral.
Depending on the type of transfer (byte, half-wo rd or word), the memo ry pointer is in cremented respective ly by 1,
2 or 4 bytes.
If a memory pointer address changes in the middle of a transfer, the PDC channel continues operating using the
new address.
27.5.3 Transfer Counters
Each channel has two 16-bit counters, one for the current transfer and the one for the next transfer. These
counters define the size of data to be transferred by the channel. The current transfer counter is decremented first
as the data addressed by the current memory po inter starts to be transferred. When the current transfer counter
reaches zero, the channel checks its next transfer counter. If the value of the next counter is zero, the channel
stops transferring data and sets the appropriate flag. If the next counter value is greater than zero, the values of
the next pointer/next c ounter are copied into the current poin ter/current counter and the channe l resumes the
transfer, wher eas next pointer/n ext counter get zero /zero as values.At the end of this transf er, the PDC channel
sets the appropriate flags in the Peripheral Status register.
The following list gives an overview of how status register flags behave depending on the counters’ values:
ENDRX flag is set when the PDC Receive Counter Register (PERIPH_RCR) reaches zero.
RXBUFF flag is set when both PERIPH_RCR and the PDC Receiv e Next Counter Register
(PERIPH_RNCR) reach zero.
SAM4S Series [DATASHEET]
Atmel-11100K-ATARM-SAM4S-Datasheet_09-Jun-15
494
ENDTX flag is set when the PDC Transmit Counter Register (PERIPH_TCR) reaches zero.
TXBUFE flag is set when both PERIPH_TCR and the PDC Transmit Next Counter Register
(PERIPH_TNCR) reach zero.
These status flags are described in the Transfer Status Register (PERIPH_PTSR).
27.5.4 Data Transfers
The serial peripheral triggers its associated PDC channels’ transfers using transmit enable (TXEN) and receive
enable (RXEN) flags in the transfer control register integrated in the peripheral’s user interface.
When the peripheral receives external data, it sends a Receive Ready signal to its PDC receive channel which
then requests access to the Matrix. When access is granted, the PDC receive channel starts reading the
peripheral Receive Holding register (RHR). The read data are stored in an internal buffer and then written to
memory.
When the peripheral is about to send data, it sends a Transmit Ready to its PDC transmit channel which then
requests access to the Matrix. When access is granted, the PDC tra nsmit channel reads data from mem ory and
transfers the data to the Transmit Holding register (THR) of its associated periphera l. The same peripheral sends
data depending on its mechanism.
27.5.5 PDC Flags and Peripheral Status Register
Each peripheral connected to the PDC sends out receive ready and transmit ready flags and the PDC returns flags
to the peripheral. All these flags are only visible in the peripheral’s Status register.
Depending on whether the peripheral is half- or full-duplex, the flags belong to either one single channel or two
different channels.
27.5.5.1 Receive Transfer End
The receive transfer end flag is set when PERIPH_RCR reaches zero and the last data has been transferred to
memory.
This flag is reset by writing a non-zero value to PERIPH_RCR or PERIPH_RNCR.
27.5.5.2 Transmit Transfer End
The transmit transfer end flag is set when PERIPH_TCR reaches zero and the last data has been written to the
peripheral THR.
This flag is reset by writing a non-zero value to PERIPH_TCR or PERIPH_TNCR.
27.5.5.3 Receive Buffer Full
The receive buffer full flag is set when PERIPH_RCR reaches zero, with PERIPH_RNCR also s et to zero and the
last data transferred to memory.
This flag is reset by writing a non-zero value to PERIPH_TCR or PERIPH_TNCR.
27.5.5.4 Transmit Buffer Empty
The transmit buffer em pty flag is se t when PERIPH_T CR reache s zero, with PERI PH_TNCR a lso set to zero and
the last data written to peripheral THR.
This flag is reset by writing a non-zero value to PERIPH_TCR or PERIPH_TNCR.
495
SAM4S Series [DATASHEET]
Atmel-11100K-ATARM-SAM4S-Datasheet_09-Jun-15
27.6 Peripheral DMA Controller (PDC) User Interface
Note: 1. PERIPH: Ten registers are mapped in the peripheral memory space at the same offset. These can be defined by the user
depending on the function and the desired perip heral.
Table 27-2 . Register Mapping
Offset Register Name Access Reset
0x00 Rece ive Pointer Register PERIPH(1)_RPR Read/Write 0
0x04 Rece ive Counter Register PERIPH_RCR Read/Write 0
0x08 Transmit Pointer Register PERIPH_TPR Read/Write 0
0x0C Transmit Counter Register PERIPH_TCR Read/Write 0
0x10 Rece ive Next Pointer Register PERIPH_RNPR Read/Write 0
0x14 Rece ive Next Counter Register PERIPH_RNCR Read/Write 0
0x18 Transmit Next Pointer Register PERIPH_TNPR Read/Write 0
0x1C Transmit Next Counter Register PERIPH_TNCR Read/Write 0
0x20 Transfer Control Register PERIPH_PTCR Write-only –
0x24 Transfer Status Register PERIPH_PTSR Read-only 0
SAM4S Series [DATASHEET]
Atmel-11100K-ATARM-SAM4S-Datasheet_09-Jun-15
496
27.6.1 Receive Pointer Register
Name: PERIPH_RPR
Access: Read/Write
• RXPTR: Receive Pointer Register
RXPTR must be set to receive buffer address.
When a half-duplex peripheral is connected to the PDC, RXPTR = TXPTR.
31 30 29 28 27 26 25 24
RXPTR
23 22 21 20 19 18 17 16
RXPTR
15 14 13 12 11 10 9 8
RXPTR
76543210
RXPTR
497
SAM4S Series [DATASHEET]
Atmel-11100K-ATARM-SAM4S-Datasheet_09-Jun-15
27.6.2 Receive Counter Register
Name: PERIPH_RCR
Access: Read/Write
• RXCTR: Receive Counter Register
RXCTR must be set to receive buffer size.
When a half-duplex peripheral is connected to the PDC, RXCTR = TXCTR.
0: Stops periph er al data transfer to the receiver.
1–65535: Starts peripheral data transfer if the corresponding channel is active.
31 30 29 28 27 26 25 24
––––––––
23 22 21 20 19 18 17 16
––––––––
15 14 13 12 11 10 9 8
RXCTR
76543210
RXCTR
SAM4S Series [DATASHEET]
Atmel-11100K-ATARM-SAM4S-Datasheet_09-Jun-15
498
27.6.3 Transmit Pointer Register
Name: PERIPH_TPR
Access: Read/Write
• TXPTR: Transmit Counter Registe r
TXPTR must be set to transmit buffer address.
When a half-duplex peripheral is connected to the PDC, RXPTR = TXPTR.
31 30 29 28 27 26 25 24
TXPTR
23 22 21 20 19 18 17 16
TXPTR
15 14 13 12 11 10 9 8
TXPTR
76543210
TXPTR
499
SAM4S Series [DATASHEET]
Atmel-11100K-ATARM-SAM4S-Datasheet_09-Jun-15
27.6.4 Transmit Counter Register
Name: PERIPH_TCR
Access: Read/Write
• TXCTR: Transmit Counter Register
TXCTR must be set to transmit buffer size.
When a half-duplex peripheral is connected to the PDC, RXCTR = TXCTR.
0: Stops periph er al data transfer to the transmitter.
1–65535: Starts peripheral data transfer if the corresponding channel is active.
31 30 29 28 27 26 25 24
––––––––
23 22 21 20 19 18 17 16
––––––––
15 14 13 12 11 10 9 8
TXCTR
76543210
TXCTR
SAM4S Series [DATASHEET]
Atmel-11100K-ATARM-SAM4S-Datasheet_09-Jun-15
500
27.6.5 Receive Next Pointer Register
Name: PERIPH_RNPR
Access: Read/Write
• RXNPTR: Receive Next Poin t er
RXNPTR contains the next receive buffer addre ss.
When a half-duplex peripheral is connected to the PDC, RXNPTR = TXNPTR.
31 30 29 28 27 26 25 24
RXNPTR
23 22 21 20 19 18 17 16
RXNPTR
15 14 13 12 11 10 9 8
RXNPTR
76543210
RXNPTR
501
SAM4S Series [DATASHEET]
Atmel-11100K-ATARM-SAM4S-Datasheet_09-Jun-15
27.6.6 Receive Next Counter Register
Name: PERIPH_RNCR
Access: Read/Write
• RXNCTR: Receive Next Counter
RXNCTR contains the next receive buffer size.
When a half-duplex peripheral is connected to the PDC, RXNCTR = TXNCTR.
31 30 29 28 27 26 25 24
––––––––
23 22 21 20 19 18 17 16
––––––––
15 14 13 12 11 10 9 8
RXNCTR
76543210
RXNCTR
SAM4S Series [DATASHEET]
Atmel-11100K-ATARM-SAM4S-Datasheet_09-Jun-15
502
27.6.7 Transmit Next Pointer Register
Name: PERIPH_TNPR
Access: Read/Write
• TXNPTR: Transmit Next Pointer
TXNPTR contains the next transmit buffer address.
When a half-duplex peripheral is connected to the PDC, RXNPTR = TXNPTR.
31 30 29 28 27 26 25 24
TXNPTR
23 22 21 20 19 18 17 16
TXNPTR
15 14 13 12 11 10 9 8
TXNPTR
76543210
TXNPTR
503
SAM4S Series [DATASHEET]
Atmel-11100K-ATARM-SAM4S-Datasheet_09-Jun-15
27.6.8 Transmit Next Counter Register
Name: PERIPH_TNCR
Access: Read/Write
• TXNCTR: Transmit Counter Next
TXNCTR contains the next transmit buffer size.
When a half-duplex peripheral is connected to the PDC, RXNCTR = TXNCTR.
31 30 29 28 27 26 25 24
––––––––
23 22 21 20 19 18 17 16
––––––––
15 14 13 12 11 10 9 8
TXNCTR
76543210
TXNCTR
SAM4S Series [DATASHEET]
Atmel-11100K-ATARM-SAM4S-Datasheet_09-Jun-15
504
27.6.9 Transfer Control Register
Name: PERIPH_PTCR
Access: Write-only
• RXTEN: Receiver Transfer Enable
0: No effect.
1: Enables PDC receiver channel requests if RXTDIS is not set.
When a half-duplex per ipheral is conn ected to the PDC, ena bling the r eceiver cha nnel r equests automa tically di sables th e
transmitter channel requests. It is forbidden to set both TXTEN and RXTEN for a half-duplex peripheral.
• RXTDIS: Receiver Transfer Disable
0: No effect.
1: Disables the PDC receiver channel requests.
When a half-duplex p eriphe ral is connecte d to the PDC, d isablin g th e receiver chan nel requests also disables the tra nsmit-
ter channel requests.
• TXTEN: Transmitter Transfer Enable
0: No effect.
1: Enables the PDC transmitter channel requests.
When a half-duplex peripheral is connected to the PDC, it enables the transmitter channel requests only if RXTEN is not
set. It is forbidden to set both TXTEN and RXTEN for a half-duplex peripheral.
• TXTDIS: Transmitter Transfer Disable
0: No effect.
1: Disables the PDC transmitter channel requests.
When a half-duplex peripheral is connected to the PDC, disabling the transmitter channel requests disables the receiver
channel requests.
31 30 29 28 27 26 25 24
––––––––
23 22 21 20 19 18 17 16
––––––––
15 14 13 12 11 10 9 8
––––––TXTDISTXTEN
76543210
––––––RXTDISRXTEN
505
SAM4S Series [DATASHEET]
Atmel-11100K-ATARM-SAM4S-Datasheet_09-Jun-15
27.6.10 Transfer Status Register
Name: PERIPH_PTSR
Access: Read-only
• RXTEN: Receiver Transfer Enable
0: PDC receiver channel requests are disabled.
1: PDC receiver channel requests are enabled.
• TXTEN: Transmitter Transfer Enable
0: PDC transmitter channel requests are disabled.
1: PDC transmitter channel requests are enabled.
31 30 29 28 27 26 25 24
––––––––
23 22 21 20 19 18 17 16
––––––––
15 14 13 12 11 10 9 8
–––––––TXTEN
76543210
–––––––RXTEN
SAM4S Series [DATASHEET]
Atmel-11100K-ATARM-SAM4S-Datasheet_09-Jun-15
506
28. Clock Generator
28.1 Description
The Clock Generator user interface is embedded within the Power Management Controller and is described in
Section 29.17 ”Power Management Controller (PMC) User Interface”. However, the Clock Generator registers are
named CKGR_.
28.2 Embedded Characteristics
The Clock Generator is made up of:
A low-power 32768 Hz slow clock oscillator with Bypass mode
A low-power RC oscillator
A 3 to 20 MHz crystal or ceramic resonator-based oscillator, which can be bypassed.
A factory-programmed fast RC oscillator. Three output frequencies can be selected: 4/8/12 MHz. By default
4 MHz is selected.
Two 80 to 240 MHz programmable PLL (inp ut fr om 3 to 32 MHz), capable of providing the clock MCK to the
processor and to the peripherals.
It provides the following clocks:
SLCK, the slow clock, which is the only permanent clock within the system.
MAINCK is the output of the main clock oscillator selection: either the crystal or ceramic resonator-based
oscillator or 4/8/12 MHz fast RC oscillator.
PLLACK is the output of the divider and 80 to 240 MHz pr ogrammable PLL (PLLA).
PLLBCK is the output of the divider and 80 to 240 MHz pr ogrammable PLL (PLLB).
507
SAM4S Series [DATASHEET]
Atmel-11100K-ATARM-SAM4S-Datasheet_09-Jun-15
28.3 Block Diagram
Figure 28-1. Clock Generator Block Diagram
PLLA and
Divider /2
PLLB and
Divider /2
PLLADIV2
PLLBDIV2
Management
Controller
MAINCK
ControlStatus
MOSCSEL
XIN
XOUT
XIN32
XOUT32
SLCK
(Supply Controller)
PLLBCK
0
1
0
1
3–20 MHz
Crystal
or
Ceramic
Resonator
Oscillator
Embedded
4/8/12 MHz
Fast
RC Oscillator
32768 Hz
Crystal
Oscillator
Embedded
32 kHz
RC Oscillator
Clock Generator
XTALSEL
Slow Clock
Main Clock
PLLB Clock
PLLA Clock
PLLACK
Power
PMC_MCKR
PMC_MCKR
CKGR_MOR
SAM4S Series [DATASHEET]
Atmel-11100K-ATARM-SAM4S-Datasheet_09-Jun-15
508
28.4 Slow Clock
The Supply Controller embeds a slow clock generator that is supplied with the VDDIO power supply. As soon as
VDDIO is supplied, both the crystal oscillator and the embedded RC oscillator are pow ered up, but only the
embedded RC oscillator is enabled. This allows the slow clock to be valid in a short time (about 100 µs).
The slow clock is generated either by the slow clock crystal os cillator or by the slow clock RC oscillator.
The selection between the RC or the crystal oscillator is made by writing the XTALSEL bit in the Supply Controller
Control Register (SUPC_CR).
28.4.1 Slow Clock RC Oscillator
By default, the slow clock RC oscillator is enabled and selected. The user has to take into account the possible
drifts of the RC oscillator. More details are given in the section “DC Characteristics” of the product datasheet.
It can be disabled via the XTALSEL bit in SUPC_CR.
28.4.2 Slow Clock Crystal Oscillator
The Clock Generator integrates a 32768 Hz low-power oscillator. To use this oscillator, the XIN32 and XOUT32
pins must be connected to a 32768 Hz crystal. Two external capacitors must be wired as shown in Figure 28-2.
More details are given in the section “DC Characteristics” of the prod u ct da ta sh ee t.
Note that the user is not obliged to use the slow clock crystal and can use the RC oscillator instead.
Figure 28-2. Typical Slow Clock Crystal Oscillator Connection
The user can select the crystal oscillator to be the source of the slow clock, as it provide s a more accurate
frequency. The command is made by writing a 1 to the SUPC_CR.XTALSEL bit. This results in a sequence which
first configures the PIO lines multiplexed with XIN32 and XOUT32 to be driven by the oscillator, then enables the
crystal oscillator and then disables the RC oscillator to save power. The switch of the slow cloc k source is glitch
free. The OSCSEL bit of the Supply Controller Status Register (S UPC_SR) or the OSCSEL bit of the PMC Status
Register (PMC_SR) tracks the oscillator frequency down stream. It must be read in order to be informed when the
switch sequence, initiated when a new value is written in the SUPC_CR.XTALSEL bit, is done.
Coming back on the RC oscillator is only possible by shutting down the VDDIO power supply. If the user does not
need the crystal oscillator, the XIN32 and XOUT32 pins can be left unconnected since by default the XIN32 and
XOUT32 system I/O pins are in PIO input mode with pull-up after reset.
The user can also set the crystal oscillator in Bypass mode instead of connecting a crystal. In this case, the user
has to provide the external clock signal on XIN32. The input characteristics of the XIN32 pin are given in the
product electrical characteristics section. In order to set the Bypass mode, the OSCBYPASS bit of the Supply
Controller Mode Register (SUPC_MR) needs to be set at 1 prior to writing a 1 in bit XTALSEL.
XIN32 XOUT32 GND
32768 Hz
Crystal
509
SAM4S Series [DATASHEET]
Atmel-11100K-ATARM-SAM4S-Datasheet_09-Jun-15
28.5 Main Clock
Figure 28-3 shows the main clock block diagram.
Figure 28-3. Main Clock Block Diagram
The main clock has two sources:
4/8/12 MHz fast RC oscillator which starts very quickly and is used at startup.
3 to 20 MHz crystal or ceramic resonator-based oscillator which can be bypassed (Refer to Section 28.5.5
”Bypassing the Main Crystal Oscillator”).
28.5.1 Fast RC Oscillator
After reset, the 4/8/12 MHz fast RC oscillator is enabled with the 4 MHz frequency selected and it is selected as
the source of MAINCK. MAINCK is the default clock selected to start the system.
The fast RC oscillator frequencies are calibrated in production except the lowest frequency which is not calibrated.
Refer to the “DC Characteristics” section of the product datasheet.
XIN
XOUT
MOSCXTEN
MOSCXTST
MOSCXTS
Main Clock
Frequency
Counter
MAINF
SLCK
Slow Clock
3–20 MHz
Crystal
or
Ceramic Resonator
Oscillator
3–20 MHz
Oscillator
Counter
MOSCRCEN
Fast RC
Oscillator
MOSCRCS
MOSCRCF
MOSCRCEN
MOSCXTEN
MOSCSEL
MOSCSEL MOSCSELS
1
0
MAINCK
Main Clock
MAINCK
Main Clock
Ref.
RCMEAS
CKGR_MCFR
CKGR_MOR CKGR_MOR
CKGR_MOR
PMC_SR
PMC_SR
CKGR_MOR
CKGR_MOR
CKGR_MOR
CKGR_MOR
CKGR_MOR
CKGR_MCFR
PMC_SR
CKGR_MCFR
MAINFRDY
SAM4S Series [DATASHEET]
Atmel-11100K-ATARM-SAM4S-Datasheet_09-Jun-15
510
The software can disable or enable the 4/8/12 MHz fast RC oscillator with the MOSCRCEN bit in the Clock
Generator Main Oscillator Register (CKGR_MOR).
The user can also select the output frequency of the fast RC oscillator, eith er 4/8/12 MHz are available. It c an be
done through MOSCRCF bits in CKGR_MOR. When changing this frequency selection, the MOSCRCS bit in the
Power Management Co ntroller Status Register (PM C_SR) is automatically cleared an d MAINCK is stopp ed until
the oscillator is stabilized. Once the oscillator is stabilized, MAINCK restarts and MOSCRCS is set.
When disabling the main clock by clearing the MOSCRCEN bit in CKGR _MOR, the MOSCRCS bit in PMC_SR is
automatically cleared, indicating the main clock is off.
Setting the MOSCRCS bit in the Power Management Controller Interrupt Enable Register (PMC_IER) can trigger
an interrupt to the processor.
When main clock (MAINCK) is not used to drive the processor and frequency monitor (SLCKis used instead), it is
recommended to disable the main oscillators.
The CAL4, CAL8 and CAL12 values in the PMC Oscillator Calibration Register (PMC_OCR) are the default values
set by Atmel during production. These values are stored in a specific Flash memory area different from the main
memory plane. These values cannot be modified by the user and cannot be erased by a Flash erase command or
by the ERASE pin. Values written by the user's application in PMC_OCR are reset after each power up or
peripheral reset.
28.5.2 Fast RC Oscillator Clock Frequency Adjustment
It is possible for the user to adjust the main RC oscillator frequency through PMC_OCR. By default, SEL4/8/12 are
low, so the RC oscillator will be driven with Flash calibration bits which are programmed during chip production.
The user can adjust the trimming of the 4/8/12 MHz fast RC oscillator through th is register in order to obtain more
accurate frequency (to compensate derating factors such as temperature and voltage).
In order to calibrate the oscillator lower frequency, SEL4 must be set to 1 and a good frequen cy value must be
configured in CAL4. Likewise, SEL8/12 must be set to 1 and a trim value must be configured in CAL8/12 in order
to adjust the other frequencies of the oscillator.
It is possible to adjust the oscillator frequency while operating from this clock. For example, when running on
lowest frequency it is possible to change the CAL4 value if SEL4 is set in PMC_OCR.
It is possible to restart, at anytim e, a measurem ent of the main frequency by means of the RCMEAS bit in Main
Clock Frequency Register (CKGR_MCFR). Thus, when MAINFRDY flag reads 1, another read access on
CKGR_MCFR provides an image of the frequ ency of the main clock on MAINF field. The software can calculate
the error with an expected frequency and correct the CAL4 (or CAL8/CAL12 ) field accord ingly. This may b e used
to compensate frequency drift due to derating factors such as temperature and/or voltage.
28.5.3 3 to 20 MHz Crystal or Ceramic Resonator-based Oscillator
After reset, the 3 to 20 MHz crystal or ceramic resonator-based oscillator is disabled and it is not selected as the
source of MAINCK.
The user can select the 3 to 20 MHz crystal or ceramic resonator-based oscillator to be the source of MAINCK, as
it provides a more accurate frequency. The software enables or disables the main oscillator in order to reduce
power consumption by clearing the MOSCXTEN bit in CKGR_MOR.
When disabling the main oscillator by clearing the MOSCXTEN bit in CKGR_MOR, the MOSCXTS bit in PMC_SR
is automatically cleared, indicating the main clock is off.
When enabling the main oscillator, the user must initiate the main oscillator counter with a value corresponding to
the start-up time of the oscillator. This start-up time depends on the crystal frequency connected to the oscillator.
When the MOSCXTEN bit and the MOSCXTST are written in CKGR_MOR to enable the main oscillator, the XIN
and XOUT pins are automatically switched into Oscillator mode and MOSCXTS bit in PMC_SR is cleared and the
511
SAM4S Series [DATASHEET]
Atmel-11100K-ATARM-SAM4S-Datasheet_09-Jun-15
counter starts cou nting down on the slow clock divided by 8 from the MOSCXTST value. Since the MO SCXTST
value is coded with 8 bits, the maximum start-up time is about 62 ms.
When the counter reaches 0, the MOSCXTS bit is set, indicating that the main clock is valid. Setting the
MOSCXTS bit in the Interrupt Mask Register (PMC_IMR) can trigger an interrupt to the processor.
28.5.4 Main Clock Oscillator Selection
The user ca n select the sou rce of the main c lock from either the 4/8/12 MHz fast RC oscillator, the 3 to 20 MHz
crystal oscillator or the ceramic resonator-based oscillator.
The advantage of the 4/8/12 MH z fast RC os cillator is its fast start-up time. By default, this oscillator is selected to
start the system and when entering Wait mode.
The advantage of the 3 to 20 MHz crystal oscillator or ceramic resonator-based oscillator is the high level of
accuracy provided.
The selection of the oscillator is made by writing the MOSCSEL bit in CKGR_MOR. The switch of the main clock
source is glitch-free, so there is no need to run out of SLCK, PLLACK in order to change the selection. The
MOSCSELS bit of PMC_SR indicates when the switch sequence is done.
Setting the MOSCSELS bit in PMC_IMR can trig ge r an interr up t to the pr oc essor.
Enabling the fast RC oscillator (MOSCRCEN = 1) and changing the fast RC frequency (MOSCCRF) at the same
time is not allowed.
The fast RC must be enabled first and its frequency changed in a second step.
28.5.5 Bypassing the Main Crystal Oscillator
Prior to bypassing the 3 to 20 MHz crystal oscillator, the external clock frequency provided on the XIN pin must be
stable and within the values specified in the XIN Clock characteristics in the sectio n “Ele ctr ical Characteristics”.
The sequence is as follows:
1. Make sure an external clock is connected on XIN.
2. Enable the bypass by writing a 1 to CKGR_MOR.MOSCXTBY.
3. Disable the 3 to 20 MHz oscillator by writing a 0 to bit CKGR_MOR.MOSCXTEN.
28.5.6 Switching Main Clock between the Main RC Oscillator and Fast Crystal Oscillator
Both sources must be enabled during the switchover operation. Only after completion can the unused oscillator be
disabled. If switching to fast crystal oscillator, the clock presence must first be checked according to what is
describe d in Section 28.5.7 ”Software Sequence to Detect the Presence of Fast Crystal” because the source may
not be reliable (crystal failure or bypass on a non-existent clock).
28.5.7 Software Sequence to Detect the Presence of Fast Crystal
The frequency meter carried on CKGR_MCFR is operating on the selected main cloc k and not on the fast crystal
clock nor on the fast RC oscillator clock.
Therefore, to check for the presence of the fast crystal clock, it is necessary to have the main clock (MAINCK)
driven by the fast crystal clock (MOSCSEL = 1).
The following software sequence order must be followed:
1. MCK must select the slow clock (CSS = 0 in the Master Clock Register (PMC_MCKR)).
2. Wait for the MCKRDY flag in PMC_SR to be 1.
3. The fast crystal must be enabled by programming 1 in the MOSCXTEN field in the CKGR_MOR with the
MOSCXTST field being programmed to the appropriate value (see the “Electrical Characteristics” se ction).
SAM4S Series [DATASHEET]
Atmel-11100K-ATARM-SAM4S-Datasheet_09-Jun-15
512
4. Wait for the MOSCXTS flag to be 1 in PMC_SR to get the end of a st art-up period of the fast crystal
oscillator.
5. Then, MOSCSEL must be programmed to 1 in CKGR_MOR to select fast main crystal oscillator for the main
clock.
6. MOSCSEL must be read until its value equals 1.
7. Then the MOSCSELS status flag must be checked in PMC_SR.
At this point, two cases may occur (either MOSCSELS = 0 or MOSCSELS = 1).
If MOSCSELS = 1: There is a valid crystal connected and its frequency can be determined by initiating a
frequency measure by programming RCMEAS in CKGR_MCFR.
If MOSCSELS = 0:
There is no fast crystal clock (either no crystal connected or a crystal clock out of specification). A
frequency measure can reinforce this status by initiating a frequency measure by programming
RCMEAS in CKGR_MCFR.
If MOSCSELS = 0, the selection of the main clock must be programmed back to the main RC oscillator
by writing MOSCSEL to 0 prior to disabling the fast crystal oscillator.
If MOSCSELS = 0, the crystal oscillator can be disabled (MOSCXTEN = 0 in CKGR_MOR).
28.5.8 Main Clock Frequency Counter
The device features a main clock frequency counter that provides the frequency of the main clock.
The main clock frequency counter is reset and starts incrementing at the main clock speed after the next rising
edge of the slow clock in the following cases:
When the 4/8/12 MHz fast RC oscillator clock is selected as the source of main clock and when this
oscillator becomes stable (i.e., when the MOSCRCS bit is set)
When the 3 to 20 MHz crystal or ceramic resonator-based oscillator is selected as the source of main clock
and when this oscillator becomes stable (i.e., when the MOSCXTS bit is set)
When the main clock oscillator selection is modified
When the RCMEAS bit of CKGR_MFCR is written to 1.
Then, at the 16th falling edge of slow clock, the MAINFRDY bit in CKGR_MCFR) is set and the counter stops
counting. Its value can be read in the MAINF field of CKGR_MCFR and gives the num ber of main clock cycles
during 16 periods of slow clock, so that the frequency of the 4/8/12 MHz fast RC oscillator or 3 to 20 MHz crystal or
ceramic resonator-based oscillator can be determined.
513
SAM4S Series [DATASHEET]
Atmel-11100K-ATARM-SAM4S-Datasheet_09-Jun-15
28.6 Divider and PLL Block
The device features two divider blocks and two PLL blocks that permit a wide range of frequencies to be selected
on either the master clock, the processor clock or the programmable clock outputs. A 48 MHz clock signal is
provided to the embe d de d USB device port re ga r dless of the freq ue n cy of the ma in clock.
Figure 28-4 shows the block diagram of the divider and PLL blocks.
Figure 28-4. Dividers and PLL Block Diagram
28.6.1 Divider and Phase Lock Loop Programming
The divider can be set between 1 and 255 in steps of 1. When a divider field (DIV) is cleared, the output of the
corresponding di vider and the PLL outp ut is a contin uous signa l at lev el 0. On re set, e ach DIV field is clea red, thus
the corresponding PLL input clock is stuck at 0.
The PLLs (PLLA, PLLB) allow multiplication of the divider’s outputs. The PLL clock signal has a fr equency that
depends on the respective source signal frequency and on the parameters DIV (DIVA, DIVB) and MUL (MULA,
MULB) . The factor applied to the source signal frequency is (MUL + 1)/DIV. When MUL is written to 0 or DIV = 0,
the PLL is disabled and its power consumption is saved. Note that there is a delay of two SLCK clock cycles
between the disa ble comman d and the re al disab le of the PLL. Re-enabling the PLL can be per formed b y writing a
value higher than 0 in the MUL field and DIV higher than 0.
Whenever the PLL is re-enabled or one of its parameter s is ch ang ed , th e LOCK (LOCKA, LOCKB) bit in PMC_SR
is automatically cleared. The values written in the PLLCOUNT field (PLLACOUNT, PLLBCOUNT) in CKGR_PLLR
(CKGR_PLLAR, CKGR_PLLBR) are load ed in the PL L cou nter . The PLL counter th en d ecre men ts a t the sp ee d of
Divider B
DIVB
PLL B
MULB
DIVA
PLL A
Counter
PLLBCOUNT
LOCKB
PLL A
Counter
PLLACOUNT
LOCKA
MULA
SLCK
PLLACK
PLLBCK
Divider A
PLL B
MAINCK
PLLADIV2
PLLBDIV2
CKGR_PLLBR
CKGR_PLLBR
CKGR_PLLBR
CKGR_PLLAR CKGR_PLLAR
CKGR_PLLAR
PMC_MCKR
PMC_MCKR
PMC_SR
PMC_SR
SAM4S Series [DATASHEET]
Atmel-11100K-ATARM-SAM4S-Datasheet_09-Jun-15
514
the slow clock until it reaches 0. At this time, the LOCK bit is set in PMC_SR and can trigger an interrupt to the
processor. The user has to load the number of slow clock cycles required to cover the PLL transient time into the
PLLCOUNT field.
The PLL clock can be divided by 2 by writing the PLLDIV2 (PLLADIV2, PLLBDIV2) bit in PMC_MCKR.
It is prohibited to change the 4/8/12 MHz fast RC oscillator or the main o scillator selection in CKGR_MOR while
the master clock source is the PLL and the PLL reference clock is the fast RC oscillator.
The user must:
1. Switch on the main RC oscillator by writing a 1 to the CSS field of PMC_MCKR.
2. Change the frequency (MOSCRCF) or oscillator selection (MOSCSEL) in CKGR_MOR.
3. Wait for MOSCRCS (if frequency changes) or MOSCSELS (if oscillator selection changes) in PMC_SR.
4. Disable and then enable the PLL.
5. Wait for the LOCK flag in PMC_SR.
6. Switch back to the PLL by writing the appropriate value to the CSS field of PMC_MCKR.
515
SAM4S Series [DATASHEET]
Atmel-11100K-ATARM-SAM4S-Datasheet_09-Jun-15
29. Power Management Controller (PMC)
29.1 Description
The Power Management Controller (PMC) optimizes power consumption by controlling all system and user
peripheral clocks. The PMC en ables/disables the clock inputs to many of the pe ripherals and the Cortex-M4
processor.
The Supply Controller selects between the 32 kHz RC oscillator or the slow crystal oscillator. The unused oscillator
is disabled automatically so that power consumption is optimized.
By default, at startup, the chip runs out of the master clock using the fast RC oscillator running at 4 MHz.
The user can trim the 8 and 12 MHz RC oscillator frequencies by software.
29.2 Embedded Characteristics
The PMC provides the following clocks:
MCK, the Master Clock, programmable from a few hundred Hz to the maximum operating frequency of the
device. It is available to the modules running permanently, such as the Enhanced Embedded Flash
Controller.
Processor Clock (HCLK) , automatically switched off when entering the processor in Sleep Mode
Free-running processor Clock (FCLK)
The Cortex-M4 SysTick external clock
UDP Clock (UDPCK), required by USB Device Port operations
Peripheral Clocks, provided to the embedded peripherals (USART, SPI, TWI, TC, etc.) and independently
controllable.
Programmable Clock Outputs (PCKx), selected from the clock generator outputs to drive the device PCK
pins
The PMC also provides the following operations on clocks:
A main crystal oscillator clock failure detector
A frequency counter on main clock and an on-the-fly adjustable main RC oscillator frequency
SAM4S Series [DATASHEET]
Atmel-11100K-ATARM-SAM4S-Datasheet_09-Jun-15
516
29.3 Block Diagram
Figure 29-1. General Clock Block Diagram
29.4 Master Clock Controller
The Master Clock Controller provides selection and division of the master clock (MCK). MCK is the source clockof
the peripheral clocks. The master clock is selected from one of the clocks provided by the Clock Gene rator.
Selecting the slow clock provides a slow clock signal to the whole device. Selecting the main clock saves power
consumption of the PLLs. The Master Clock Controller is made up of a clock selector and a prescaler.
The master clock selection is made by writing the CSS field (Clock Source Selection) in PMC_MCKR.
The prescaler supports the division by a power of 2 of the selected clock between 1 and 64, and the division by 3.
The PRES field in PMC_MCKR programs the prescaler.
Each time PMC_MCKR is written to define a new master clock, the MCKRDY bit is cleared in PMC_SR. It reads 0
until the master clock is established. Then, the MCKRDY bit is set and can trigger an interrupt to the processor.
This feature is useful wh en switching from a high-speed clock to a lower one to inform the software when the
change is actually done.
USB Clock
UDPCK
Management
Controller
Main Clock
MAINCK
PLLA Clock
PLLACK
ControlStatus
3–20 MHz
Crystal
or
Ceramic
Resonator
Oscillator
MOSCSEL
PLLA and
Divider /2
XIN
XOUT
XIN32
XOUT32
SLCK
(Supply Controller)
Embedded
32 kHz RC
Oscillator
32768 Hz
Crystal
Oscillator
PLLB Clock
PLLBCK
0
1
0
1
MCK
periph_clk[..]
int
SLCK
MAINCK
PLLACK
Prescaler
/1, /2, /3, /4, /8,
/16, /32, /64
HCLK
Processor
Clock
Controller
Sleep Mode
Master Clock Controller
(PMC_MCKR)
ON/OFF
Prescaler
/1, /2, /4, /8,
/16, /32, /64 pck[..]
PLLBCK
ON/OFF
FCLK
SysTick
Divider
/8
SLCK
MAINCK
PLLACK
PLLBCK
Processor clock
Free Running Clock
Master Clock
PLLB and
Divider /2 Divider
/1, /2, /3,... /16
USB Clock Controller (PMC_USB)
PLLBCK
Embedded
4/8/12 MHz
Fast
RC Oscillator
Programmable Clock Controller
(PMC_PCKx)
PRES
USBDIV
PLLADIV2
PLLBDIV2
PRES
USBS
PLLACK
CSS
ON/OFF
CSS
MCK
Clock Generator
XTALSEL
Power
Slow Clock
Peripherals
Clock Controller
(PMC_PCERx)
PMC_MCKR
PMC_MCKR
CKGR_MOR
(PMC_SCER/SCDR)
517
SAM4S Series [DATASHEET]
Atmel-11100K-ATARM-SAM4S-Datasheet_09-Jun-15
Figure 29-2. Master Clock Controller
29.5 Processor Clock Controller
The PMC features a Processor Clock Controller (HCLK) that implements the processor Sleep mode. These
processor clock can be disabled by executing the WFI (WaitForInterrupt) or the WFE (WaitForEvent) processor
instruction while the LPM bit is at 0 in the PMC Fast Startup Mode Register (PMC_FSMR).
The Processor Clock Controller HCLK is enabled after a reset and is automatically re-enabled by any enabled
interrupt. The processor Sleep mode is entered by disabling the processor clock, which is automatically re-enabled
by any enabled fast or normal interrupt, or by the reset of the product.
When processor Sleep mode is entered, the current instruction is finished before the clock is stopped, but this
does not prevent data transfers from other masters of the system bus.
29.6 SysTick Clock
The SysTick calibration value is fixed to 12500 which allows the generation of a time base of 1 ms with SysTick
clock to the maximum frequency on MCK divided by 8.
29.7 USB Clock Controller
The user can select the PLLA or the PLLB output as the USB source clock by writing the USBS bit in PMC_USB.
If using the USB, the user must program the PLL to generate an appropriate frequency depending on the USBDIV
bit in the USB Clock Register (PMC_USB).
When the PLL ou tput is stable, i.e., the LOCK bit is set, the USB device FS clock can be enabled by setting the
UDP bit in the System Clock Enable Register (PMC_SCER). To save power on this peripheral when it is not used,
the user can set the UD P bit in the System Clock Disable Register (PMC_SCDR). The UDP bit in the System
Clock Status Register (PMC_SCSR) gives the activity of th is clock. The USB device port re quir es bo th th e 48 M Hz
signal and the peripheral clock. The USB peripheral clock may be controlled by means of the Master Clock
Controller.
Figure 29-3. USB Clock Controller
SLCK
Master Clock
Prescaler To the MCK Divider
PRESCSS
MAINCK
PLLACK
PLLBCK To the Processor
Clock Controller (PCK)
PMC_MCKR PMC_MCKR
USB
Source
Clock
UDP Clock (UDPCK)
UDP
USBDIV
Divider
/1,/2,/3,.../16
PMC_USB PMC_SCER,
PMC_SDER
SAM4S Series [DATASHEET]
Atmel-11100K-ATARM-SAM4S-Datasheet_09-Jun-15
518
29.8 Peripheral Clock Controller
The PMC controls the clocks of each embedded peripheral by means of the Peripheral Clock Controller. The user
can individually enable and disable the clock on the peripherals.
The user can also enable and disable these clocks by writing Peripheral Clock Enable 0 (PMC_PCER0),
Peripheral Clock Disable 0 (PMC_PCDR0), Peripheral Clock Enable 1 (PMC_PCER1) and P eripheral Clock
Disable 1 (PMC_PCDR1) registers. The status of the peripheral clock activity can be read in the Peripheral Clock
Status Register (PMC_PCSR0) and Peripheral Clock Status Register (PMC_PCSR1).
When a peripheral clock is disabled, the clock is immediately stopped. The peripheral clocks are automatically
disabled after a reset.
To stop a peripheral, it is recommended that the system software wait until the peripheral has executed its last
programmed operat ion before disabling the clock. This is to avoid data corru ption or erroneous behavior of the
system.
The bit number within the Peripheral Clock Control registers (PMC_PCER0–1, PMC_PCDR0–1, and
PMC_PCSR0–1) is the Peripheral Identifier defined at the product level. The bit number corresponds to the
interrupt source number as signed to the peripheral.
29.9 Free-Running Processor Clock
The free-running processor clock (FCLK)used for sampling interrupts and clocking debug b locks ensures that
interrupts can be sampled, and sleep events can be traced, while the processor is sleeping. It is connected to
master clock (MCK).
29.10 Programmable Clock Output Controller
The PMC controls three signals to be output on external pins, PCKx. Each signal can be independently
programmed via the Programmable Clock Registers (PMC_PCKx).
PCKx can be independently selected between th e slow clock (SLCK), the main clock (MAINCK), the PLLA clock
(PLLACK), the PLLB clock (PLLBCK),and the master clock (MCK) by writing the CSS field in PMC_PCKx. Each
output signal can also be divided by a power of 2 between 1 and 64 by writing the PRES (Prescaler) field in
PMC_PCKx.
Each output signal can be enabled and disabled by writing a 1 to the corresponding PCKx bit of PMC_SCER and
PMC_SCDR, respectively. Status of the active programmable output clocks are given in the PCKx bits of
PMC_SCSR.
The PCKRDYx status flag in PMC_SR indicates that the programmable clock is actually what has been
programmed in the programmable clock registers.
As the Program mable Clock Controller d oes not mana ge with glitch prevention when switching clocks, it is strongly
recommended to disa ble the programmable clock before any configu ration change and to re-enable it after the
change is actually performed.
29.11 Fast Startup
At exit from Wait mode, the device allows the processor to restart in less than 10 microseconds only if the C-code
function that manages the Wait mode entry and exit is linked to and executed from on-chip SRAM.
The fast startup time cannot be achieved if the first instruction after an exit is located in the embedded Flash.
If fast startup is not required, or if the fir st instruction after a Wait mode exit is located in embe dded Flash, see
Section 29.12 ”Startup from Embedded Flash”.
519
SAM4S Series [DATASHEET]
Atmel-11100K-ATARM-SAM4S-Datasheet_09-Jun-15
Prior to instructing the device to enter Wait mode:
1. Select the fast RC oscillator as the master clock source (the CSS field in PMC_MCKR must be written to
1).
2. Disable the PLL if enabled.
3. Clear the internal wake-up sources.
The system enters Wait mode either by setting the WAITMODE bit in CKGR_MOR, or by executing the
WaitForEvent (WFE) instruction of th e processor while the LPM bit is at 1 in PMC_FSMR. Immed iately after settin g
the WAITMODE bit or using the WFE instruction, wait for the MCKRDY bit to be set in PMC_SR.
A fast startup is enabled upon the detection of a programmed level on one of the 16 wake-up inputs (WKUP) or
upon an active alarm from the RTC, RTT and USB Controller. The polarity of the 16 wake-up inputs is
programmable by writing the PMC Fast Startup Polarity Register (PMC_FSPR).
The fast startup circuitry, as shown in Figure 29-4, is fully asynchronous and provides a fast startup signal to the
PMC. As soon as the fast startup signal is asserted, the embedded 4/8/12 MHz fast RC oscillator restarts
automatically.
When entering Wait mode, the embedded Flash can be placed in one of the Low-power m odes (Deep-power-
down or Standby modes) depending on the configuration of the FLPM field in the PMC_FSMR. The FLPM field
can be programmed at anytime and its value will be applied to the next Wait mode period.
The power consumption reduction is optimal when configuring 1 (Deep-power-down mode) in field FLPM. If 0 is
programmed (Standby mode), the power consumption is slightly higher than in Deep- power-down mode.
When programming 2 in field FLPM, the Wait mode Flash power consumption is equivalent to that of the Active
mode when there is no read access on the Flash.
Figure 29-4. Fast Startup Circuitry
fast_restart
WKUP15
FSTT15
FSTP15
WKUP1
FSTT1
FSTP1
WKUP0
FSTT0
FSTP0
RTTAL
RTCAL
USBAL
RTT Alarm
RTC Alarm
USB Alarm
SAM4S Series [DATASHEET]
Atmel-11100K-ATARM-SAM4S-Datasheet_09-Jun-15
520
Each wake-up input pin an d alarm ca n be enable d to gener ate a fa st startup event by setting the corresponding bit
in PMC_FSMR.
The user inte rface does not pr ovide any statu s for fast startup, bu t the user can ea sily recover this infor mation by
reading the PIO Controller and the status registers of the RTC, RTT and USB Controller.
29.12 Startup from Embedded Flash
The inherent start-up time of the embedded Flash cannot provide a fast startup of the system.
If system fast start-up time is not required, the first instruction after a Wait mode exit can be located in the
embedded Flash. Under these conditions, prior to entering Wait mode, the Flash controller must be programmed
to perform access in 0 wait-state (see Flash controller section).
The procedure and conditions to enter Wait mode and the circuitry to exit W ait mode are strictly the same as fast
startup (s ee Section 29.11 ”Fast Startup”).
29.13 Main Clock Failure Detector
The clock failure de tector monitors the main crystal oscillator or ceram ic resonator-based oscillato r to identify an
eventual failure of this oscillator.
The clock failure detector can be enabled or disabled by bit CFDEN in CKGR_MOR. After a VD DCO RE reset, t he
detector is disabled. However, if the oscillator is disabled (MOSCXTEN = 0), the detector is disabled too.
The clock failure detection must be enabled only when sys tem cloc k MCK selects the fast RC oscillator. PMC_SR
must be read two slow clock cycles after enabling the clock failure detector. Then, MCK can select another clock
source by programming the CSS field in PMC_MCKR.
A failure is detected by means of a counter incrementing on the main oscillator clock edge and detection logic is
triggered by the slow RC Oscillator clock. The slow RC is automatically enabled when CFDEN=1.
The counter is cleared when the slow RC oscillator clock signal is low and e nabled when the signal is high. Thus,
the failure detection time is one slow RC oscillator period. If, during the high level period of the slow RC oscillator
clock signal, less than eight fast crystal oscillator clock periods have been counted, then a failure is reported.
If a failure of the main oscillator is detected, bit CFDEV in PMC_SR indicates a failure event and generates an
interrupt if the corresponding interrupt source is enabled. The interrupt remains active until a read occurs in
PMC_SR. The user can know the status of the clock failure detection at any time by reading the CF DS bit in
PMC_SR.
Figure 29-5. Clock Failure Detectio n (Example)
If the main oscillator is selected as the source clock of MAINCK (MOSCSEL in CKGR_MOR = 1), and if the master
clock source is PLLACK or PLLBCK (CSS = 2 or 3), a clock failure detection automatically forces MAINCK to be
the source clock for the master clock (MCK). Then, regardless of the PMC configuration, a clock failure detection
Main Crytal Clock
SLCK
Note: ratio of clock periods is for illustration purposes only
CDFEV
CDFS
Read PMC_SR
521
SAM4S Series [DATASHEET]
Atmel-11100K-ATARM-SAM4S-Datasheet_09-Jun-15
automatically forces the fast RC oscillator to be the s ource clock for MAINCK. If the fast RC oscillator is disabled
when a clock failure detection occurs, it is automatically re-enabled by the clock failure detection mechanism.
It takes two slow RC oscillator clock cycles to detect and switch from the main oscillator, to the fast RC oscillator if
the source master clock (MCK) is main clock (MAINCK), or three slow clock RC oscillator cycles if the source of
MCK is PLLACKor PLLBCK.
A clock failure detection activates a fault output that is connected to the Pulse Width Modulator (PWM) Controller.
With this connection, the PWM controller is able to force its outputs and to protect the driven device, if a clock
failure is detected.
The user can know the status of the clock failure detector at any time by reading the FOS bit in PMC_SR.
This fault output remains active until the defe ct is detected and until it is cleared by the bit FOCLR in the PM C Fault
Output Clear Register (PMC_FOCR).
SAM4S Series [DATASHEET]
Atmel-11100K-ATARM-SAM4S-Datasheet_09-Jun-15
522
29.14 Programming Sequence
1. If the fast crystal oscillator is not required, the PLL and divider can be directly configured (Step 6.) else
the fast crystal oscillator must be started (Step 2.).
2. Enable the fast crystal oscillator:
The fast crystal oscillator is enabled by setting the MOSCXTEN field in CKGR_MOR. The user can define a
start-up time. This can be achieved by writing a value in the MOSCXTST field in CKGR_MOR. Once this
register has been correctly configured, the user must wait for MOSCXTS field in PMC_SR to be set. This
can be done either by polling MOSCXTS in PMC_SR, or by waiting for the interrupt line to be raised if the
associated interrupt source (MOSCXTS) has been enabled in PMC_IER.
3. Switch the MAINCK to the main crystal oscillator by setting MOSCSEL in CKGR_MOR.
4. Wait for the MOSCSELS to be set in PMC_SR to ensure the switchover is complete.
5. Check the main clock frequency:
This main clock frequency can be measured via CKGR_MCFR.
Read CKGR_MCFR until the MAINFRDY field is set, after which the user can read the MAINF field in
CKGR_MCFR by performing an additional read. This provides the number of main clock cycles that have
been counted during a period of 16 slow clock cycles.
If MAINF = 0, switch the MAINCK to the Fast RC Oscillator by clearing MOSCSEL in CKGR_MOR. If MAINF
≠ 0, proceed to Step 6.
6. Set PLLx and Divider (if not required, proceed to Step 7.):
In the names PLLx, DIVx, MULx, LOCKx, PLLxCOUNT, and CKGR_PLL xR, ‘x’ represents A or B.
All parameters needed to configure PLLx and the divider are located in CKGR_PLLxR.
The DIVx field is used to control the divider itself. This parameter can be programmed between 0 and 127.
Divider output is divider input divided by DIVx parameter. By default, DIVx field is cleared which means that
the divider and PLLx are turned off.
The MULx field is the PLLx multiplier factor. This parameter can be programmed between 0 and 62. If MULx
is cleared, PLLx will be turn ed off, otherwise the PLLx output freq uency is PLLx input frequency multiplied by
(MULx + 1).
The PLLxCOUNT fi eld specifies the numb er of slow clock cycles before the LOCKx bit is set in the PMC_SR
after CKGR_PLLxR has been written.
Once CKGR_PLLxR has been written, the user must wait for the LOCKx bit to be set in the PMC_SR. This
can be done either by polling LOCKx in PMC_SR or by waiting for the interrupt line to be raised if the
associated interrupt source (LOCKx) has been enabled in PMC_IER. All fields in CKGR_PLLxR can be
programmed in a single write operation. If at some stage one of the following parameters, MULx or DIVx is
modified, the LOCKx bit goes low to indicate that PLLx is not yet ready. When PLLx is locked, LOCKx is set
again. The user must wait for the LOCKx bit to be set before using the PLLx output clock.
7. Sele ct the ma ste r clo ck and pr ocessor clock
The master clock and the processor clock are configurable via PMC_MCKR.
The CSS field is used to select the clock source of the master clock and processor clock dividers. By default,
the selected clock source is the main clock.
The PRES field is used to define the processor clock and master clock prescaler. The user can choose
between different values (1, 2, 3, 4, 8, 16, 32, 64). Prescaler output is the selected clock source frequency
divided by the PRES value.
Once the PMC_M CKR has bee n writ te n, the us er mus t wait for the MCKRDY bit to be set in the PMC_SR.
This can be done ei ther by pol ling MCKRDY in PMC_SR o r by waiting for the interrupt line to be raised if the
523
SAM4S Series [DATASHEET]
Atmel-11100K-ATARM-SAM4S-Datasheet_09-Jun-15
associated interrupt source (MCKRDY) has been enabled in PMC_IER. PMC_MCKR must not be
programmed in a single write operation. The programming sequence for PMC_MCKR is as follows:
If a new value for CSS field corresponds to PLL clock,
Program the PRES field in PMC_MCKR.
Wait for the MCKRDY bit to be set in PMC_SR.
Program the CSS field in PMC_MCKR.
Wait for the MCKRDY bit to be set in PMC_SR.
If a new value for CSS field corresponds to main clock or slow clock,
Program the CSS field in PMC_MCKR.
Wait for the MCKRDY bit to be set in the PMC_SR.
Program the PRES field in PMC_MCKR.
Wait for the MCKRDY bit to be set in PMC_SR.
If at some stage, parameters CSS or PRES are modified, the MCKRDY bit goes low to indicate that the
master clock and the processo r clock ar e no t yet read y. The user must wa it for MCKRDY bi t to be set aga in
before using the master and processor clocks.
Note: IF PLLx clock was selected as the master clock and the user decides to modify it by writing in CKGR_PLLxR, the
MCKRDY flag will go low while PLLx is unlocked. Once PLLx is locked aga in, LOCKx goes high an d MCKRDY is set.
While PLLx is unlocked, the master clock selection is automatically changed to slow clock for PLLA and main clock for
PLLB. For further information, see Section 29.15.2 ”Clock Switching Waveforms”.
Code Example:
write_register(PMC_MCKR,0x00000001)
wait (MCKRDY=1)
write_register(PMC_MCKR,0x00000011)
wait (MCKRDY=1)
The master clock is main clock divided by 2.
8. Select the programmable clocks
Programmable clocks are controlled via registers, PMC_SCER, PMC_SCDR and PMC_SCSR.
Programmable clocks can be enabled and/or dis abled via PMC_SCER and PMC_SCDR. Three
programmable clocks can b e used. PMC_SCSR indica tes wh ich prog rammable clock is en abled. By de fault
all programmable clocks are disabled.
PMC_PCKx registers are used to configure programmable clocks.
The CSS field is used to select the programmable clock divider source. Several clock options are available:
main clock, slow clock, master clock, PLLACK, PLLBCK. The slow clock is the default clock source.
The PRES field is used to control the programmable clock prescaler. It is possible to choose between
different values (1, 2, 4, 8, 16, 32, 64). Programmable clock output is prescaler input divided by PRES
parameter. By default, the PRES value is cleared which means that PCKx is equal to slow clock.
Once PMC_PCKx register has been configured, the corresponding prog rammable clock must be enabled
and the user is constr ained to wait for the PCKRDYx bi t to be set in the PMC_ SR. This can be done either by
polling PCKRDYx in PMC_SR or by waiting for the interrupt line to be raised if the associated interrupt
source (PCKRDYx) has been enab led in PMC_IER. All para meters in PMC_PCKx ca n be progr ammed in a
single write oper a tion .
If the CSS and PRES parameters are to be modified, the correspondin g programmable clock must be
disabled first. The parameters can then be modified. Once this has been done, the user must re-enable the
programmable clock and wait for the PCKRDYx bit to be set.
9. Enable the peripheral clocks
SAM4S Series [DATASHEET]
Atmel-11100K-ATARM-SAM4S-Datasheet_09-Jun-15
524
Once all of the previous steps have been completed, the peripheral clocks can be enabled and/or disabled
via registers PMC_PCER0, PMC_PCER, PMC_PCDR0 and PMC_PCDR.
525
SAM4S Series [DATASHEET]
Atmel-11100K-ATARM-SAM4S-Datasheet_09-Jun-15
29.15 Clock Switching Deta ils
29.15.1 Master Clock Switching Timings
Table 29-1 and Table 29-2 give the worst case timings required for the master clock to switch from one selected
clock to another one. This is in the event that the prescaler is de-activated. When the prescaler is activated, an
additional time of 64 clock cycles of the newly selected clock has to be added.
Notes: 1. PLL designates either the PLLA or the PLLB Clock.
2. PLLCOUNT desi gnates either PLLACOU NT or PLLBCOUNT.
Table 29-1. Clock Switching Timings (Worst Case)
From Main Clock SLCK PLL Clock
To
Main Clock – 4 x SLCK +
2.5 x Main Clock
3 x PLL Clock +
4 x SLCK +
1 x Main Clock
SLCK 0.5 x Main Clock +
4.5 x SLCK –3 x PLL Clock +
5 x SLCK
PLL Clock
0.5 x Main Clock +
4 x SLCK +
PLLCOUNT x SLCK +
2.5 x PLLx Clock
2.5 x PLL Clock +
5 x SLCK +
PLLCOUNT x SLCK
2.5 x PLL Clock +
4 x SLCK +
PLLCOUNT x SLCK
Table 29-2. Clock Switching Timings between Two PLLs (Worst Case)
From PLLA Clock PLLB Clock
To
PLLA Clock 2.5 x PLLA Clock +
4 x SLCK +
PLLACOUNT x SLCK
3 x PLLA Clock +
4 x SLCK +
1.5 x PLLA Clock
PLLB Clock 3 x PLLB Clock +
4 x SLCK +
1.5 x PLLB Clock
2.5 x PLLB Clock +
4 x SLCK +
PLLBCOUNT x SLCK
SAM4S Series [DATASHEET]
Atmel-11100K-ATARM-SAM4S-Datasheet_09-Jun-15
526
29.15.2 Clock Switching Waveforms
Figure 29-6. Switch Master Clock from Slow Clock to PLLx Clock
Figure 29-7. Switch Master Clock from Main Clock to Slow Clock
Slow Clock
LOCK
MCKRDY
Master Clock
Write PMC_MCKR
PLLx Clock
Slow Clock
Main Clock
MCKRDY
Master Clock
Write PMC_MCKR
527
SAM4S Series [DATASHEET]
Atmel-11100K-ATARM-SAM4S-Datasheet_09-Jun-15
Figure 29-8. Change PLLx Programming
Figure 29-9. Programmable Clock Output Programming
Slow Clock
Slow Clock
PLLx Clock
LOCKx
MCKRDY
Master Clock
Write CKGR_PLLxR
PLLx Clock
PCKRDY
PCKx Output
Write PMC_PCKx
Write PMC_SCER
Write PMC_SCDR PCKx is disabled
PCKx is enabled
PLL Clock is selected
SAM4S Series [DATASHEET]
Atmel-11100K-ATARM-SAM4S-Datasheet_09-Jun-15
528
29.16 Register Write Protection
To prevent any single software error from corrupting PMC behavior, certain registers in the address space can be
write-protected by setting the WPEN bit in the PMC Write Protection Mode Register (PMC_WPMR).
If a write access to a write-protected register is d etected, the WPVS flag in the PMC Write Protection Status
Register (PMC_WPSR) is set and the field WPVSRC indicates the register in which the write acce ss has been
attempted.
The WPVS bit is automatically cleared after reading the PMC_WPSR.
The following registers can be write-protected:
PMC System Clock Enable Register
PMC System Clock Disable Register
PMC Peripheral Clock Enable Register 0
PMC Peripheral Clock Disable Register 0
PMC Clock Generator Main Oscillator Register
PMC Clock Generator PLLA Register
PMC Clock Generator PLLB Register
PMC Master Clock Register
PMC USB Clock Register
PMC Programmable Clock Register
PMC Fast Startup Mode Register
PMC Fast Startup Polarity Register
PMC Peripheral Clock Enable Register 1
PMC Peripheral Clock Disable Register 1
PMC Oscillator Calibration Register
529
SAM4S Series [DATASHEET]
Atmel-11100K-ATARM-SAM4S-Datasheet_09-Jun-15
29.17 Power Management Controller (PMC) User Interface
Table 29-3 . Register Mapping
Offset Register Name Access Reset
0x0000 System Clock Enable Register PMC_SCER Write-only –
0x0004 System Clock Disable Register PMC_SCDR Write-only –
0x0008 System Clock S tatus Register PMC_SCSR Read-only 0x0000_0001
0x000C Reserved – – –
0x0010 Peripheral Clock Enable Register 0 PMC_PCER0 Write-only –
0x0014 Peripheral Clock Disable Regi ster 0 PMC_PCDR0 Write-only –
0x0018 Peripheral Clock Status Register 0 PMC_PCSR0 Read-only 0x0000_0000
0x001C Reserved – – –
0x0020 Main Oscillator Register CKGR_MOR Read/Write 0x0000_0008
0x0024 Main Clock Frequency Register CKGR_MCFR Rea d/Write 0x0000_0000
0x0028 PLLA Register CKGR_PLLAR Read/Write 0x0000_3F00
0x002C PLLB Register CKGR_PLLBR Read/Write 0x0000_3F00
0x0030 Master Clock Register PMC_MCKR Read/Write 0x0000_0001
0x0034 Reserved – – –
0x0038 USB Clock Register PMC_USB Read/Write 0x0000_0000
0x003C Reserved – – –
0x0040 Programmable Clock 0 Register PMC_ PCK0 Read/Write 0x0000_0000
0x0044 Programmable Clock 1 Register PMC_ PCK1 Read/Write 0x0000_0000
0x0048 Programmable Clock 2 Register PMC_ PCK2 Read/Write 0x0000_0000
0x004C– 0x005C Reserved – – –
0x0060 Interrupt Enable Register PMC_IER Write-only –
0x0064 Interrupt Disable Register PMC_IDR Write-only –
0x0068 Status Register PMC_SR Read-only 0x0003_0008
0x006C Interrupt Mask Register PMC_IMR Read-only 0x0000_0 000
0x0070 Fast Startup Mode Register PMC_FSMR Read/Write 0x0000_0000
0x0074 Fast Startup Polarity Register PMC_FSPR Read/Write 0x0000_0000
0x0078 Fault Output Clear Register PMC_FOCR Write-only –
0x007C–0x00E0 Reserved – – –
0x00E4 Write Protection Mode Register PMC_WPMR Read/Write 0x0000_0000
0x00E8 Write Protection Status Register PMC_WPSR Read-only 0x0000_0000
0x00EC–0x00FC Reserved – – –
0x0100 Peripheral Clock Enable Register 1 PMC_PCER1 Write-only –
0x0104 Peripheral Clock Disable Regi ster 1 PMC_PCDR1 Write-only –
0x0108 Peripheral Clock Status Register 1 PMC_PCSR1 Read-only 0x0000_0000
0x010C Reserved – – –
SAM4S Series [DATASHEET]
Atmel-11100K-ATARM-SAM4S-Datasheet_09-Jun-15
530
Note: If an offset is not listed in the table it must be considered as “reserved”.
0x0110 Oscillator Calibration Register PMC_OCR Read/Write 0x0040_4040
0x114–0x120 Reserved – – –
0134–0x144 Reserved – – –
Table 29-3. Register Mapping (Continued)
Offset Register Name Access Reset
531
SAM4S Series [DATASHEET]
Atmel-11100K-ATARM-SAM4S-Datasheet_09-Jun-15
29.17.1 PMC System Clock Enable Register
Name: PMC_SCER
Address: 0x400E0400
Access: Write-only
This register can only be written if the WPEN bit is cleared in the PMC Write Protection Mode Register.
• UDP: USB Device Port Clock Enable
0: No effect.
1: Enables the 48 MHz clock (UDPCK) of the USB Device Port.
• PCKx: Programmable Clock x Output Enable
0: No effect.
1: Enables the corresponding Programmable Clock output.
31 30 29 28 27 26 25 24
––––––––
23 22 21 20 19 18 17 16
––––––––
15 14 13 12 11 10 9 8
–––––PCK2PCK1PCK0
76543210
UDP–––––––
SAM4S Series [DATASHEET]
Atmel-11100K-ATARM-SAM4S-Datasheet_09-Jun-15
532
29.17.2 PMC System Clock Disable Register
Name: PMC_SCDR
Address: 0x400E0404
Access: Write-only
This register can only be written if the WPEN bit is cleared in the PMC Write Protection Mode Register.
• UDP: USB Device Port Clock Disable
0: No effect.
1: Disables the 48 MHz clock (UDPCK) of the USB Device Port.
• PCKx: Programmable Clock x Output Disable
0: No effect.
1: Disables the corresponding Programmable Clock output.
31 30 29 28 27 26 25 24
––––––––
23 22 21 20 19 18 17 16
––––––––
15 14 13 12 11 10 9 8
–––––PCK2PCK1PCK0
76543210
UDP–––––––
533
SAM4S Series [DATASHEET]
Atmel-11100K-ATARM-SAM4S-Datasheet_09-Jun-15
29.17.3 PMC System Clock Status Register
Name: PMC_SCSR
Address: 0x400E0408
Access: Read-only
• UDP: USB Device Port Clock Status
0: The 48 MHz clock (UDPCK) of the USB Device Port is disabled.
1: The 48 MHz clock (UDPCK) of the USB Device Port is enabled.
• PCKx: Programmable Clock x Output Status
0: The corresponding Programmable Clock output is disabled.
1: The corresponding Programmable Clock output is enabled.
31 30 29 28 27 26 25 24
––––––––
23 22 21 20 19 18 17 16
––––––––
15 14 13 12 11 10 9 8
–––––PCK2PCK1PCK0
76543210
UDP–––––––
SAM4S Series [DATASHEET]
Atmel-11100K-ATARM-SAM4S-Datasheet_09-Jun-15
534
29.17.4 PMC Peripheral Clock Enable Register 0
Name: PMC_PCER0
Address: 0x400E0410
Access: Write-only
This register can only be written if the WPEN bit is cleared in the PMC Write Protection Mode Register.
• PIDx: Peripheral Clock x Enable
0: No effect.
1: Enables the corresponding peripheral clock.
Note: PIDx refers to identifiers defined in the section “Peripheral Identifiers”. Other peripherals can be enabled in PMC_PCER1 (Section
29.17.23 ”PMC Peripheral Clock Enabl e Register 1”).
Note: Programming the control bits of the Peripheral ID that are not implemented has no effect on the behavior of the PMC.
31 30 29 28 27 26 25 24
PID31 PID30 PID29 PID28 PID27 PID26 PID25 PID24
23 22 21 20 19 18 17 16
PID23 PID22 PID21 PID20 PID19 PID18 PID17 PID16
15 14 13 12 11 10 9 8
PID15 PID14 PID13 PID12 PID11 PID10 PID9 PID8
76543210
––––––––
535
SAM4S Series [DATASHEET]
Atmel-11100K-ATARM-SAM4S-Datasheet_09-Jun-15
29.17.5 PMC Peripheral Clock Disable Register 0
Name: PMC_PCDR0
Address: 0x400E0414
Access: Write-only
This register can only be written if the WPEN bit is cleared in the PMC Write Protection Mode Register.
• PIDx: Peripheral Clock x Disable
0: No effect.
1: Disables the corresponding peripheral clock.
Note: PIDx refers to identifiers defined in the section “Peripheral Identifiers”. Other peripherals can be disabled in PMC_PCDR1
(Section 29.17.24 ”PMC Peripheral Clock Disable Register 1”).
31 30 29 28 27 26 25 24
PID31 PID30 PID29 PID28 PID27 PID26 PID25 PID24
23 22 21 20 19 18 17 16
PID23 PID22 PID21 PID20 PID19 PID18 PID17 PID16
15 14 13 12 11 10 9 8
PID15 PID14 PID13 PID12 PID11 PID10 PID9 PID8
76543210
––––––––
SAM4S Series [DATASHEET]
Atmel-11100K-ATARM-SAM4S-Datasheet_09-Jun-15
536
29.17.6 P M C Peri ph e ral Clo c k Status Register 0
Name: PMC_PCSR0
Address: 0x400E0418
Access: Read-only
• PIDx: Peripheral Clock x Status
0: The corresponding peripheral clock is disabled.
1: The corresponding peripheral clock is enabled.
Note: PIDx refers to identifiers defin e d in th e se cti o n “Peripheral Identifiers”. Other pe ri p he r a l s status can be read in PMC_PCSR1
(Section 29.17.25 ”PMC Peripheral Clock Status Register 1”).
31 30 29 28 27 26 25 24
PID31 PID30 PID29 PID28 PID27 PID26 PID25 PID24
23 22 21 20 19 18 17 16
PID23 PID22 PID21 PID20 PID19 PID18 PID17 PID16
15 14 13 12 11 10 9 8
PID15 PID14 PID13 PID12 PID11 PID10 PID9 PID8
76543210
––––––––
537
SAM4S Series [DATASHEET]
Atmel-11100K-ATARM-SAM4S-Datasheet_09-Jun-15
29.17.7 P M C Clo c k Gen era to r Main Os c ill at or Reg i st er
Name: CKGR_MOR
Address: 0x400E0420
Access: Read/Write
This register can only be written if the WPEN bit is cleared in the PMC Write Protection Mode Register.
• MOSCXTEN: Main Crystal Oscillator Enable
A crystal must be connected between XIN and XOUT.
0: The main crystal oscillator is disabled.
1: The main crystal oscillator is enabled. MOSCXTBY must be cleared.
When MOSCXTEN is set, the MOSCXTS flag is set once the main crystal oscillator start-up time is achieved.
• MOSCXTBY: Main Crystal Oscillator Bypass
0: No effect.
1: The main crystal oscillator is bypassed. MOSCXTEN must be cleared. An external clock must be connected on XIN.
When MOSCXTBY is set, the MOSCXTS flag in PMC_SR is automatically set.
Clearing MOSCXTEN and MOSCXTBY bits resets the MOSCXTS flag.
Note: When the main crystal oscillator bypass is disabled (MOSCXTBY = 0), the MOSCXTS flag m ust be read at 0 in PMC_SR before
enabling the main crystal oscillator (MOSCXTEN = 1).
• WAITMODE: Wait Mode Command (Write-only)
0: No effect.
1: Puts the device in Wait mode.
• MOSCRCEN: Ma in On -C hip RC Oscillator Enable
0: The main on-chip RC oscillator is disabled.
1: The main on-chip RC oscillator is enabled.
When MOSCRCEN is set, the MOSCRCS flag is set once the main on-chip RC oscillator start-up time is achieved.
31 30 29 28 27 26 25 24
––––––CFDENMOSCSEL
23 22 21 20 19 18 17 16
KEY
15 14 13 12 11 10 9 8
MOSCXTST
76543210
– MOSCRCF MOSCRCEN WAITMODE MOSCXTBY MOSCXTEN
SAM4S Series [DATASHEET]
Atmel-11100K-ATARM-SAM4S-Datasheet_09-Jun-15
538
• MOSCRCF: Main On-Chip RC Oscillator Frequency Selection
At startup, the main on-chip RC oscillator frequency is 4 MHz.
Note: MOSCRCF must be changed only if MOSCRCS is set in the PMC_SR. Therefore MOSCRCF and MOSCRCEN ca nnot be
changed at the same time.
• MOSCXTST: Main Crystal Oscillator Start-up Time
Specifies the number of slow clock cycles multiplied by 8 for the main crystal oscillator start-up time.
• KEY: Write Access Password
• MOSCSEL: Main Oscillator Selection
0: The main on-chip RC oscillator is selected.
1: The main crystal oscillator is selected.
• CFDEN: Clock Failure Detector Enable
0: The clock failure detector is disabled.
1: The clock failure detector is enabled.
Note: 1. The slow RC oscillator must be enabled when the CFDEN is en abled.
2. The clock failure detection must be enabled only when system clock MCK selects the fast RC oscillator.
3. Then the status register must be read 2 slow clock cycles after enabling.
Value Name Description
0x0 4_MHz The fast RC oscillator frequency is at 4 MHz (default)
0x1 8_MHz The fast RC oscillator frequency is at 8 MHz
0x2 12_MHz The fast RC oscillator frequency is at 12 MHz
Value Name Description
0x37 PASSWD Writing any other value in this field aborts the write operation.
Always reads as 0.
539
SAM4S Series [DATASHEET]
Atmel-11100K-ATARM-SAM4S-Datasheet_09-Jun-15
29.17.8 PMC Clock Generator Main Clock Frequency Register
Name: CKGR_MCFR
Address: 0x400E0424
Access: Read/Write
This register can only be written if the WPEN bit is cleared in the PMC Write Protection Mode Register.
• MAINF: Main Clock Frequency
Gives the number of main clock cycles within 16 slow clock periods in order to determine the main clock freq uen cy: fMCK =
(MAINF × fSLCK) / 16
where frequency is in MHz.
• MAINFRDY: Main Clock Frequency Measure Ready
0: MAINF value is not valid or the main oscillator is disabled or a measure has just been started by means of RCMEAS.
1: The main oscillator has been enabled previously and MAINF value is available.
Note: To ensure that a correct value is read on the MAINF field, the MAINFRDY flag must be read at 1 then another read access must
be performed on the register to get a stable value on the MAINF field.
• RCMEAS: RC Oscillator Frequency Measure (write-only)
0: No effect.
1: Restarts measuring of the main RC frequency. MAINF will carry the new frequency as soon as a low to high transition
occurs on the MAINFRDY flag.
The measure is performed on the main frequency (i.e. not limited to RC oscillator only), but if the main cloc k frequency
source is the fast crystal oscillator, the restart of measuring is not needed because of the well known stability of crystal
oscillators.
31 30 29 28 27 26 25 24
––––––––
23 22 21 20 19 18 17 16
–––RCMEAS–––MAINFRDY
15 14 13 12 11 10 9 8
MAINF
76543210
MAINF
SAM4S Series [DATASHEET]
Atmel-11100K-ATARM-SAM4S-Datasheet_09-Jun-15
540
29.17.9 PMC Clock Generator PLLA Register
Name: CKGR_PLLAR
Address: 0x400E0428
Access: Read/Write
Possible limitations on PLLA input frequencies and multiplier factors should be checked before using the PMC.
Warning: Bit 29 must always be set to 1 when programming the CKGR_PLLAR.
This register can only be written if the WPEN bit is cleared in the PMC Write Protection Mode Register.
•DIVA: PLLA Front_End Divider
0: Divider output is stuck at 0 and PLLA is disabled.
1: Divider is bypassed (divide by 1) PLLA is enabled
2–255: Clock is divided by DIVA
• PLLACOUNT: PLLA Counter
Specifies the number of Slow Clock cycles before the LOCKA bit is set in PMC_SR after CKGR_PLLAR is written.
• MULA: PLLA Multiplier
0: The PLLA is deactivated (PLLA also disabled if DIVA = 0).
7 up to 62 = The PLLA Clock frequency is the PLLA input frequency multiplied by MULA + 1.
Unlisted values are forbidden.
• ONE: Must Be Set to 1
Bit 29 must always be set to 1 when programming the CKGR_PLLAR.
31 30 29 28 27 26 25 24
––ONE–– MULA
23 22 21 20 19 18 17 16
MULA
15 14 13 12 11 10 9 8
– – PLLACOUNT
76543210
DIVA
541
SAM4S Series [DATASHEET]
Atmel-11100K-ATARM-SAM4S-Datasheet_09-Jun-15
29.17.10PMC Clock Generator PLLB Register
Name: CKGR_PLLBR
Address: 0x400E042C
Access: Read/Write
Possible limitations on PLLB input frequencies and multiplier factors should be checked before using the PMC.
This register can only be written if the WPEN bit is cleared in the PMC Write Protection Mode Register.
• DIVB: PLLB Front-End Divider
0: Divider output is stuck at 0 and PLLB is disabled.
1: Divider is bypassed (divide by 1)
2–255: Clock is divided by DIVB
• PLLBCOUNT: PLLB Counter
Specifies the number of Slow Clock cycles before the LOCKB bit is set in PMC_SR after CKGR_PLLBR is written.
• MULB: PLLB Multiplier
0: The PLLB is deactivated (PLLB also disabled if DIVB = 0).
7 up to 62: The PLLB Clock frequency is the PLLB input frequency multiplied by MULB + 1.
Unlisted values are forbidden.
31 30 29 28 27 26 25 24
––––– MULB
23 22 21 20 19 18 17 16
MULB
15 14 13 12 11 10 9 8
– – PLLBCOUNT
76543210
DIVB
SAM4S Series [DATASHEET]
Atmel-11100K-ATARM-SAM4S-Datasheet_09-Jun-15
542
29.17.11PMC Master Clock Register
Name: PMC_MCKR
Address: 0x400E0430
Access: Read/Write
This register can only be written if the WPEN bit is cleared in the PMC Write Protection Mode Register.
• CSS: Master Clock Source Selection
• PRES: Processor Clock Prescaler
• PLLADIV2: PLLA Divisor by 2
31 30 29 28 27 26 25 24
––––––––
23 22 21 20 19 18 17 16
––––––––
15 14 13 12 11 10 9 8
––PLLBDIV2PLLADIV2––––
76543210
–PRES––CSS
Value Name Description
0 SLOW_CLK Slow Clock is selected
1 MAIN_CLK Main Clock is selected
2 PLLA_CLK PLLA Clock is selected
3 PLLB_CLK PLLBClock is selected
Value Name Description
0 CLK_1 Selected clock
1 CLK_2 Selected clock divided by 2
2 CLK_4 Selected clock divided by 4
3 CLK_8 Selected clock divided by 8
4 CLK_16 Selected clock divided by 16
5 CLK_32 Selected clock divided by 32
6 CLK_64 Selected clock divided by 64
7 CLK_3 Selected clock divided by 3
PLLADIV2 PLLA Clock Division
0 PLLA clock frequency is divided by 1.
1 PLLA clock frequency is divided by 2.
543
SAM4S Series [DATASHEET]
Atmel-11100K-ATARM-SAM4S-Datasheet_09-Jun-15
• PLLBDIV2: PLLB Divisor by 2
PLLBDIV2 PLLB Clock Division
0 PLLB clock frequency is divided by 1.
1 PLLB clock frequency is divided by 2.
SAM4S Series [DATASHEET]
Atmel-11100K-ATARM-SAM4S-Datasheet_09-Jun-15
544
29.17.12PMC USB Clock Register
Name: PMC_USB
Address: 0x400E0438
Access: Read/Write
This register can only be written if the WPEN bit is cleared in the PMC Write Protection Mode Register.
• USBS: USB Input Clock Selection
0: USB Clock Input is PLLA.
1: USB Clock Input is PLLB
• USBDIV: Divider for USB Clock
USB Clock is Input clock divided by USBDIV + 1.
31 30 29 28 27 26 25 24
––––––––
23 22 21 20 19 18 17 16
––––––––
15 14 13 12 11 10 9 8
–––– USBDIV
76543210
–––––––USBS
545
SAM4S Series [DATASHEET]
Atmel-11100K-ATARM-SAM4S-Datasheet_09-Jun-15
29.17.13PMC Programmabl e Clo c k Register
Name: PMC_PCKx
Address: 0x400E0440
Access: Read/Write
This register can only be written if the WPEN bit is cleared in the PMC Write Protection Mode Register.
• CSS: Master Clock Source Selection
• PRES: Programmable Clock Prescaler
31 30 29 28 27 26 25 24
––––––––
23 22 21 20 19 18 17 16
––––––––
15 14 13 12 11 10 9 8
––––––––
76543210
– PRES – CSS
Value Name Description
0 SLOW_CLK Slow Clock is selected
1 MAIN_CLK Main Clock is selected
2 PLLA_CLK PLLA Clock is selected
3 PLLB_CLK PLLB Clock is selected
4 MCK Master Clock is selected
Value Name Description
0 CLK_1 Selected clock
1 CLK_ 2 Sel ecte d clock divided by 2
2 CLK_ 4 Sel ecte d clock divided by 4
3 CLK_ 8 Sel ecte d clock divided by 8
4 CLK_16 Selected clock divid ed by 16
5 CLK_32 Selected clock divid ed by 32
6 CLK_64 Selected clock divid ed by 64
SAM4S Series [DATASHEET]
Atmel-11100K-ATARM-SAM4S-Datasheet_09-Jun-15
546
29.17.14PMC Interrupt Enable Register
Name: PMC_IER
Address: 0x400E0460
Access: Write-only
The following configuration values are valid for all listed bit names of this register:
0: No effect.
1: Enables the corresponding interrupt.
• MOSCXTS: Main Crystal Oscillator Status Interrupt Enable
• LOCKA: PLLA Lock Interrupt Enable
• LOCKB: PLLB Lock Interrupt Enable
• MCKRDY: Master Clock Ready Interrupt Enable
• PCKRDYx: Programmable Clock Ready x Interrupt Enable
• MOSCSELS: Main Oscillator Selection Status Interrupt Enable
• MOSCRCS: Main On-Chip RC Status Interrupt Enable
• CFDEV: Clock Failure Detector Event Interrupt Enable
31 30 29 28 27 26 25 24
––––––––
23 22 21 20 19 18 17 16
–––––CFDEVMOSCRCSMOSCSELS
15 14 13 12 11 10 9 8
–––––PCKRDY2PCKRDY1PCKRDY0
76543210
––––MCKRDYLOCKBLOCKAMOSCXTS
547
SAM4S Series [DATASHEET]
Atmel-11100K-ATARM-SAM4S-Datasheet_09-Jun-15
29.17.15PMC Interrupt Disable Register
Name: PMC_IDR
Address: 0x400E0464
Access: Write-only
The following configuration values are valid for all listed bit names of this register:
0: No effect.
1: Disables the corresponding interrupt.
• MOSCXTS: Main Crystal Oscillator Status Interrupt Disable
• LOCKA: PLLA Lock Interrupt Disable
• LOCKB: PLLB Lock Interrupt Disable
• MCKRDY: Master Clock Re ady Interrupt Disable
• PCKRDYx: Programmable Clock Ready x Interrupt Disable
• MOSCSELS: Main Oscillator Selection Status Interrupt Disable
• MOSCRCS: Main On-Chip RC Status Interrupt Disable
• CFDEV: Clock Failure Detector Event Interrupt Disable
31 30 29 28 27 26 25 24
––––––––
23 22 21 20 19 18 17 16
–––––CFDEVMOSCRCSMOSCSELS
15 14 13 12 11 10 9 8
–––––PCKRDY2PCKRDY1PCKRDY0
76543210
––––MCKRDYLOCKBLOCKAMOSCXTS
SAM4S Series [DATASHEET]
Atmel-11100K-ATARM-SAM4S-Datasheet_09-Jun-15
548
29.17.16PMC Status Register
Name: PMC_SR
Address: 0x400E0468
Access: Read-only
• MOSCXTS: Main Crystal Oscillator Status
0: Main crystal oscillator is not stabilized.
1: Main crystal oscillator is stabilized.
• LOCKA: PLLA Lock Status
0: PLLA is not locked
1: PLLA is locked.
• LOCKB: PLLB Lock Status
0: PLLB is not locked
1: PLLB is locked.
• MCKRDY: Master Clock Status
0: Master Clock is not ready.
1: Master Clock is ready.
• OSCSELS: Slow Clock Oscillator Selection
0: Internal slow clock RC oscillator is selected.
1: External slow clock 32 kHz oscillator is selected.
• PCKRDYx: Programmable Clock Ready Status
0: Programmable Clock x is not ready.
1: Programmable Clock x is ready.
31 30 29 28 27 26 25 24
––––––––
23 22 21 20 19 18 17 16
– – – FOS CFDS CFDEV MOSCRCS MOSCSELS
15 14 13 12 11 10 9 8
–––––PCKRDY2PCKRDY1PCKRDY0
76543210
OSCSELS – – – MCKRDY LOCKB LOCKA MOSCXTS
549
SAM4S Series [DATASHEET]
Atmel-11100K-ATARM-SAM4S-Datasheet_09-Jun-15
• MOSCSELS: Main Oscillator Selection Status
0: Selection is in progress.
1: Selection is done.
• MOSCRCS: Main On-Chip RC Oscillator Status
0: Main on-chip RC oscillator is not stabilized.
1: Main on-chip RC oscillator is stabilized.
• CFDEV: Clock Failure Detector Event
0: No clock failure detection of the fast cry stal oscillator clock has occurred since the last read of PMC_SR.
1: At least one clock failure detection of the fast crystal oscillator clock has occurred since the last read of PMC_SR.
• CFDS: Clock Failure Detector Status
0: A clock failure of the fast crystal oscillator clock is not detected.
1: A clock failure of the fast crystal oscillator clock is detected.
• FOS: Clock Failure Detector Fault Output Status
0: The fault output of the clock failure detector is inactive.
1: The fault output of the clock failure detector is active.
SAM4S Series [DATASHEET]
Atmel-11100K-ATARM-SAM4S-Datasheet_09-Jun-15
550
29.17.17PMC Interrupt Mask Register
Name: PMC_IMR
Address: 0x400E046C
Access: Read-only
The following configuration values are valid for all listed bit names of this register:
0: No effect.
1: Enables the corresponding interrupt.
• MOSCXTS: Main Crystal Oscillator Status Interrupt Mask
• LOCKA: PLLA Lock Interrupt Mask
• LOCKB: PLLB Lock Interrupt Mask
• MCKRDY: Master Clock Ready Interrupt Mask
• PCKRDYx: Programmable Clock Ready x Interrupt Mask
• MOSCSELS: Main Oscillator Selection Status Interrupt Mask
• MOSCRCS: Main On-Chip RC Status Interrupt Mask
• CFDEV: Clock Failure Detector Event Interrupt Mask
31 30 29 28 27 26 25 24
––––––––
23 22 21 20 19 18 17 16
–––––CFDEVMOSCRCSMOSCSELS
15 14 13 12 11 10 9 8
–––––PCKRDY2PCKRDY1PCKRDY0
76543210
––––MCKRDYLOCKBLOCKAMOSCXTS
551
SAM4S Series [DATASHEET]
Atmel-11100K-ATARM-SAM4S-Datasheet_09-Jun-15
29.17.18PMC Fast Startup Mode Register
Name: PMC_FSMR
Address: 0x400E0470
Access: Read/Write
This register can only be written if the WPEN bit is cleared in the PMC Write Protection Mode Register.
• FSTT0–FSTT15: Fast Startup Input Enable 0 to 15
0: The corresponding wake-up input has no effect on the PMC.
1: The corresponding wake-up input enables a fast re start signal to the PMC.
• RTTAL: RTT Alarm Enable
0: The RTT alarm has no effect on the PMC.
1: The RTT alarm enables a fast restart signal to the PMC.
• RTCAL: RTC Alarm Enable
0: The RTC alarm has no effect on the PMC.
1: The RTC alarm enables a fast restart signal to the PMC.
• USBAL: USB Alarm Enable
0: The USB alarm has no effect on the PMC.
1: The USB alarm enables a fast restart signal to the PMC.
• LPM: Low-power Mode
0: The WaitForInterrupt (WFI) or the WaitForEvent (WFE) instruction of the processor makes the processor enter Sleep
mode.
1: The WaitForEvent (WFE) instruction of the processor makes the system to enter Wait mode.
• FLPM: Flash Low-power Mode
31 30 29 28 27 26 25 24
––––––––
23 22 21 20 19 18 17 16
– FLPM LPM – USBAL RTCAL RTTAL
15 14 13 12 11 10 9 8
FSTT15 FSTT14 FSTT13 FSTT12 FSTT11 FSTT10 FSTT9 FSTT8
76543210
FSTT7 FSTT6 FSTT5 FSTT4 FSTT3 FSTT2 FSTT1 FSTT0
Value Name Description
0 FLASH_STAND BY Flash is in Standby Mode when system enters Wait Mode
1 FLASH_DEEP_POWERDOWN Flash is in Deep-power-down mode when system enters Wait Mode
2 FLASH_IDLE Idle mode
SAM4S Series [DATASHEET]
Atmel-11100K-ATARM-SAM4S-Datasheet_09-Jun-15
552
29.17.19PMC Fast Startup Polarity Register
Name: PMC_FSPR
Address: 0x400E0474
Access: Read/Write
This register can only be written if the WPEN bit is cleared in the PMC Write Protection Mode Register.
• FSTPx: Fast Startup Input Pola rityx
Defines the active polarity of the corresponding wake-up input. If the corresponding wake-up input is enabled and at the
FSTP level, it enables a fast restart signal.
31 30 29 28 27 26 25 24
––––––––
23 22 21 20 19 18 17 16
––––––––
15 14 13 12 11 10 9 8
FSTP15 FSTP14 FSTP13 FSTP12 FSTP11 FSTP10 FSTP9 FSTP8
76543210
FSTP7 FSTP6 FSTP5 FSTP4 FSTP3 FSTP2 FSTP1 FSTP0
553
SAM4S Series [DATASHEET]
Atmel-11100K-ATARM-SAM4S-Datasheet_09-Jun-15
29.17.20PMC Fault Output Clear Register
Name: PMC_FOCR
Address: 0x400E0478
Access: Write-only
• FOCLR: Fault Output Clear
Clears the clock failure detector fault output.
31 30 29 28 27 26 25 24
––––––––
23 22 21 20 19 18 17 16
––––––––
15 14 13 12 11 10 9 8
––––––––
76543210
–––––––FOCLR
SAM4S Series [DATASHEET]
Atmel-11100K-ATARM-SAM4S-Datasheet_09-Jun-15
554
29.17.21PMC Write Protection Mode Register
Name: PMC_WPMR
Address: 0x400E04E4
Access: Read/Write
• WPEN: Write Protec ti on Ena b le
0: Disables the write protection if WPKEY corresponds to 0x504D43 (“PMC” in ASCII).
1: Enables the write protection if WPKEY corresponds to 0x504D43 (“PMC” in ASCII).
See Section 29.16 ”Register Writ e Protection” for the list of registers that can be write-protected.
• WPKEY: Write Protection Key
31 30 29 28 27 26 25 24
WPKEY
23 22 21 20 19 18 17 16
WPKEY
15 14 13 12 11 10 9 8
WPKEY
76543210
–––––––WPEN
Value Name Description
0x504D43 PASSWD Writing any other value in this field a bor ts th e wr ite oper ation of the WPEN bi t.
Always reads as 0.
555
SAM4S Series [DATASHEET]
Atmel-11100K-ATARM-SAM4S-Datasheet_09-Jun-15
29.17.22PMC Write Protection Status Register
Name: PMC_WPSR
Address: 0x400E04E8
Access: Read-only
• WPVS: Write Protection Violation Status
0: No write protec tion v iola tio n ha s occ u rred since the last read of the PMC_WPSR.
1: A write protection violation has occurred since th e last read of the PMC_WPSR. If this violation is an unauthorized
attempt to write a protected register, the associated violation is reported into field WPVSRC.
• WPVSRC: Write Protection Violation Source
When WPVS = 1, WPVSRC indicates the register address offset at which a write access has been attempted.
31 30 29 28 27 26 25 24
––––––––
23 22 21 20 19 18 17 16
WPVSRC
15 14 13 12 11 10 9 8
WPVSRC
76543210
–––––––WPVS
SAM4S Series [DATASHEET]
Atmel-11100K-ATARM-SAM4S-Datasheet_09-Jun-15
556
29.17.23PMC Peripheral Clock Enable Register 1
Name: PMC_PCER1
Address: 0x400E0500
Access: Write-only
This register can only be written if the WPEN bit is cleared in the PMC Write Protection Mode Register.
• PIDx: Peripheral Clock x Enable
0: No effect.
1: Enables the corresponding peripheral clock.
Notes: 1. The values for PIDx are defined in the section “Peripheral Identifiers” in the product datasheet.
2. Programming the control bits of the Peripheral ID that are not implemented has no effect on the behavior of the PMC.
31 30 29 28 27 26 25 24
––––––––
23 22 21 20 19 18 17 16
––––––––
15 14 13 12 11 10 9 8
––––––––
76543210
–––––PID34PID33PID32
557
SAM4S Series [DATASHEET]
Atmel-11100K-ATARM-SAM4S-Datasheet_09-Jun-15
29.17.24PMC Peripheral Clock Disable Register 1
Name: PMC_PCDR1
Address: 0x400E0504
Access: Write-only
This register can only be written if the WPEN bit is cleared in the PMC Write Protection Mode Register.
• PIDx: Peripheral Clock x Disable
0: No effect.
1: Disables the corresponding peripheral clock.
Note: The values for PIDx are defined in the section “Peripheral Identifiers” in the product datasheet.
31 30 29 28 27 26 25 24
––––––––
23 22 21 20 19 18 17 16
––––––––
15 14 13 12 11 10 9 8
––––––––
76543210
–––––PID34PID33PID32
SAM4S Series [DATASHEET]
Atmel-11100K-ATARM-SAM4S-Datasheet_09-Jun-15
558
29.17.25PMC Peripheral Clock Status Register 1
Name: PMC_PCSR1
Address: 0x400E0508
Access: Read-only
• PIDx: Peripheral Clock x Status
0: The corresponding peripheral clock is disabled.
1: The corresponding peripheral clock is enabled.
Note: The values for PIDx are defined in the section “Peripheral Identifiers” in the product datasheet.
31 30 29 28 27 26 25 24
––––––––
23 22 21 20 19 18 17 16
––––––––
15 14 13 12 11 10 9 8
––––––––
76543210
–––––PID34PID33PID32
559
SAM4S Series [DATASHEET]
Atmel-11100K-ATARM-SAM4S-Datasheet_09-Jun-15
29.17.26PMC Oscillator Calibration Register
Name: PMC_OCR
Address: 0x400E0510
Access: Read/Write
This register can only be written if the WPEN bit is cleared in the PMC Write Protection Mode Register.
• CAL4: RC Oscillator Calibration bits for 4 MHz
Calibration bits applied to the RC Oscillator when SEL4 is set.
• SEL4: Selection of RC Oscillator Calibration bits for 4 MHz
0: Default value stored in Flash memory.
1: Value written by user in CAL4 field of this register.
• CAL8: RC Oscillator Calibration bits for 8 MHz
Calibration bits applied to the RC Oscillator when SEL8 is set.
• SEL8: Selection of RC Oscillator Calibration bits for 8 MHz
0: Factory-determined value stored in Flash me mory.
1: Value written by user in CAL8 field of this register.
• CAL12: RC Os cillator Calibration bits for 12 MHz
Calibration bits applied to the RC Oscillator when SEL12 is set.
• SEL12: Selection of RC Oscillator Calibration bits for 12 MHz
0: Factory-determined value stored in Flash me mory.
1: Value written by user in CAL12 field of this register.
31 30 29 28 27 26 25 24
––––––––
23 22 21 20 19 18 17 16
SEL12 CAL12
15 14 13 12 11 10 9 8
SEL8 CAL8
76543210
SEL4 CAL4
SAM4S Series [DATASHEET]
Atmel-11100K-ATARM-SAM4S-Datasheet_09-Jun-15
560
30. Chip Identifier (CHIPID)
30.1 Description
Chip Identifier (CHIPID) registers permit recognition of the device and its revision. These registers provide the
sizes and types of the on-chip memories, as well as the set of embedded peripherals.
Two CHIPID registers are embedded: Chip ID Register (CHIPID_CIDR) and Chip ID Extension Register
(CHIPID_EXID). Both registers contain a hard-wired value that is read-only.
The CHIPID_CIDR contains the following fields:
VERSION: Identifies the revision of the silicon
EPROC: Indicates the embedded ARM processor
NVPTYP and NVPSIZ: Identify the type of embedded non-volatile me mor y an d th e si ze
SRAMSIZ: Indicates the size of the embedded SRAM
ARCH: Identifies the set of embedded peripherals
EXT: Shows the use of the extension identifier register
The CHIPID_EXID reg iste r is dev ice -d ep en d ent an d re ad s 0 if CHIPID_CIDR.EXT = 0.
561
SAM4S Series [DATASHEET]
Atmel-11100K-ATARM-SAM4S-Datasheet_09-Jun-15
30.2 Embedded Characteristics
Chip ID Registers
Identification of the Device Revision, Sizes of the Embedded Memories, Set of Peripherals,
Embedded Processor
Table 30-1. SAM4S Chip ID Registers
Chip Name CHIPID_CIDR CHIPID_EXID
SAM4SD32C (Rev A) 0x29A7_0EE0 0x0
SAM4SD32C (Rev B) 0x29A7_0EE1 0x0
SAM4SD32B (Rev A) 0x2997_0EE0 0x0
SAM4SD32B (Rev B) 0x2997_0EE1 0x0
SAM4SD16C (Rev A) 0x29A7_0CE0 0x0
SAM4SD16C (Rev B) 0x29A7_0CE1 0x0
SAM4SD16B (Rev A) 0x2997_0CE0 0x0
SAM4SD16B (Rev B) 0x2997_0CE1 0x0
SAM4SA16C (Rev A) 0x28A7_0CE0 0x0
SAM4SA16C (Rev B) 0x28A7_0CE1 0x0
SAM4SA16B (Rev A) 0x2897_0CE0 0x0
SAM4SA16B (Rev B) 0x2897_0C E1 0x0
SAM4S16B (Rev A) 0x289C_0CE0 0x0
SAM4S16B (Rev B) 0x289C_0CE1 0x0
SAM4S16C (Rev A) 0x28AC_0CE0 0x0
SAM4S16C (Rev B) 0x28AC_0CE1 0x0
SAM4S8B (Rev A) 0x289C_0AE0 0x0
SAM4S8B (Rev B) 0x289C_0AE1 0x0
SAM4S8C (Rev A) 0x28AC_0AE0 0x0
SAM4S8C (Rev B) 0x28AC_0AE1 0x0
SAM4S4C (Rev A) 0x28AB_09E0 0x0
SAM4S4C (Rev B) 0x28AB_09E1 0x0
SAM4S4B (Rev A) 0x289B_09E0 0x0
SAM4S4B (Rev B) 0x289B_09E1 0x0
SAM4S4A (Rev A) 0x288B_09E0 0x0
SAM4S4A (Rev B) 0x288B_09E1 0x0
SAM4S2C (Rev A) 0x28AB_07E0 0x0
SAM4S2C (Rev B) 0x28AB_07E1 0x0
SAM4S2B (Rev A) 0x289B_07E0 0x0
SAM4S2B (Rev B) 0x289B_07E1 0x0
SAM4S2A (Rev A) 0x288B_07E0 0x0
SAM4S2A (Rev B) 0x288B_07E1 0x0
SAM4S Series [DATASHEET]
Atmel-11100K-ATARM-SAM4S-Datasheet_09-Jun-15
562
30.3 Chip Identifier (CHIPID) User Interface
Table 30-2 . Register Mapping
Offset Register Name Access Reset
0x0 Chip ID Register CHIPID_CIDR Read -only –
0x4 Chip ID Extension Register CHIPID_EXID Read-only –
563
SAM4S Series [DATASHEET]
Atmel-11100K-ATARM-SAM4S-Datasheet_09-Jun-15
30.3.1 Chip ID Register
Name: CHIPID_CIDR
Address: 0x400E0740
Access: Read-only
• VERSION: Version of the De vi ce
Current version of the device.
• EPROC: Embedded Processor
• NVPSIZ: Nonvolatile Program Memory Size
31 30 29 28 27 26 25 24
EXT NVPTYP ARCH
23 22 21 20 19 18 17 16
ARCH SRAMSIZ
15 14 13 12 11 10 9 8
NVPSIZ2 NVPSIZ
76543210
EPROC VERSION
Value Name Description
0 SAM x7 Cortex-M7
1 ARM946ES ARM946ES
2 ARM7TDMI ARM7TDMI
3 CM3 Cortex-M3
4 ARM920T ARM920T
5 ARM926EJS ARM926EJS
6 CA5 Cortex-A5
7 CM4 Cortex-M4
Value Name Description
0NONE None
18K 8 Kbytes
2 16K 16 Kbytes
3 32K 32 Kbytes
4– Reserved
5 64K 64 Kbytes
6– Reserved
7 128K 128 Kbytes
8 160K 160 Kbytes
9 256K 256 Kbytes
10 512K 512 Kbytes
SAM4S Series [DATASHEET]
Atmel-11100K-ATARM-SAM4S-Datasheet_09-Jun-15
564
• NVPSIZ2: Second Nonvolatile Program Memory Size
• SRAMSIZ: Internal SRAM Size
11 – Reserved
12 1024K 1024 Kbytes
13 – Reserved
14 2048K 2048 Kbytes
15 – Reserved
Value Name Description
0NONE None
18K 8 Kbytes
2 16K 16 Kbytes
3 32K 32 Kbytes
4– Reserved
5 64K 64 Kbytes
6– Reserved
7 128K 128 Kbytes
8– Reserved
9 256K 256 Kbytes
10 512K 512 Kbytes
11 – Reserved
12 1024K 1024 Kbytes
13 – Reserved
14 2048K 2048 Kbytes
15 – Reserved
Value Name Description
0 48K 48 Kbytes
1 192K 192 Kbytes
2 384K 384 Kbytes
36K 6 Kbytes
4 24K 24 Kbytes
54K 4 Kbytes
6 80K 80 Kbytes
7 160K 160 Kbytes
88K 8 Kbytes
9 16K 16 Kbytes
10 32K 32 Kbytes
11 64K 64 Kbytes
Value Name Description
565
SAM4S Series [DATASHEET]
Atmel-11100K-ATARM-SAM4S-Datasheet_09-Jun-15
• ARCH: Architecture Identifier
• NVPTYP: Nonvolatile Program Memory Type
• EXT: Extension Flag
0: Chip ID has a single register definition without extension.
1: An extended Chip ID exists.
12 128K 128 Kbytes
13 256K 256 Kbytes
14 96K 96 Kbytes
15 512K 512 Kbytes
Value Name Description
0x88 SAM4SxA SAM4SxA (48-pin version)
0x89 SAM4SxB SAM4SxB (64-pin version)
0x8A SAM4SxC SAM4SxC (100-pin version)
Value Name Description
0ROM ROM
1 ROMLESS ROMless or on-chip Flash
2 FLASH Embedded Flash Memory
3 ROM_FLASH ROM and Embedded Flash Memory
NVPSIZ is ROM size
NVPSIZ2 is Flash size
4 SRAM SRAM emulating ROM
Value Name Description
SAM4S Series [DATASHEET]
Atmel-11100K-ATARM-SAM4S-Datasheet_09-Jun-15
566
30.3.2 Chip ID Extension Register
Name: CHIPID_EXID
Address: 0x400E0744
Access: Read-only
• EXID: Chip ID Extension
This field is cleared if CHIPID_CIDR.EXT = 0.
31 30 29 28 27 26 25 24
EXID
23 22 21 20 19 18 17 16
EXID
15 14 13 12 11 10 9 8
EXID
76543210
EXID
567
SAM4S Series [DATASHEET]
Atmel-11100K-ATARM-SAM4S-Datasheet_09-Jun-15
31. Parallel Input/Output Controller (PIO)
31.1 Description
The Parallel Input/Output Controller (PIO) manages up to 32 fully programmable input/output lines. Each I/O line
may be dedicated as a general-purpose I/O or be assigned to a function of an embedded peripheral. This ensures
effective optimization of the pins of the product.
Each I/O line is associated with a bit number in all of the 32-bit registers of the 32-bit wide user inter face.
Each I/O line of the PIO Controller features:
An input change interrupt enabling level change detection on any I/O line.
Additional Interrupt modes enabling rising edge, falling edge, low-level or high-level detection on any I/O
line.
A glitch filter providing rejection of glitches lower than one-half of peripheral clock cycle.
A debouncing filter providing rejection of unwanted pulses from key or push button operations.
Multi-drive capability similar to an open drain I/O line.
Control of the pull-up and pull-down of the I/O line.
Input visibility and output control.
The PIO Controller also features a synchronous output providing up to 32 bits of data output in a single write
operation.
An 8-bit parallel capture mode is also available which can be used to interface a CMOS digital image sensor, an
ADC, a DSP synchronous port in synchronous mode, etc.
SAM4S Series [DATASHEET]
Atmel-11100K-ATARM-SAM4S-Datasheet_09-Jun-15
568
31.2 Embedded Characteristics
Up to 32 Programmable I/O Lines
Fully Programmable through Set/Clear Registers
Multiplexing of Four Peripheral Functions per I/O Line
For each I/O Line (Whether Assigned to a Peripheral or Used as General Purpose I/O)
Input Change Interrupt
Programmable Glitch Filter
Programmable Debouncing Filter
Multi-drive Option Enables Driving in Open Drain
Programmable Pull-Up on Each I/O Line
Pin Data Status Register, Supplies Visibility of the Level on the Pin at Any Time
Additional Interrupt Modes on a Programmable Event: Rising Edge, Falling Edge, Low-Level or High-
Level
Lock of the Configuration by the Connected Peripheral
Synchronous Output, Provides Set and Clear of Several I/O Lines in a Single Write
Register Write Protection
Programmable Schmitt Trigger Inputs
Parallel Capture Mode
Can Be Used to Interface a CMOS Digital Image Sensor, an ADC, etc.
One Clock, 8-bit Parallel Data and Two Data Enable on I/O Lines
Data Can be Sampled Every Other Time (For Chrominance Sampling Only)
Supports Connection of One Peripheral DMA Controller (PDC) Channel Which
Offers Buffer Reception Without Processor Intervention
569
SAM4S Series [DATASHEET]
Atmel-11100K-ATARM-SAM4S-Datasheet_09-Jun-15
31.3 Block Diagram
Figure 31-1. Block Diagram
Embedded
Peripheral
Embedded
Peripheral
PIO Interrupt
PIO Controller
Parallel Capture
Mode
PMC
Up to x
peripheral IOs
Up to x
peripheral IOs
Peripheral Clock
APB
Data, Enable
PIN x-1
PIN 1
PIN 0
Data, Enable
PDC
Data
Status
PIODCCLK
PIODC[7:0]
PIODCEN1
PIODCEN2
Interrupt Controller
Events
x is an integer representing the maximum number
of IOs managed by one PIO controller.
Table 31-1. Signal Description
Signal Name Signal Description Signal Type
PIODCCLK Parallel Capture Mode Clock Input
PIODC[7:0] Parallel Capture Mode Data Input
PIODCEN1 Parallel Capture Mode Data Enable 1 Input
PIODCEN2 Parallel Capture Mode Data Enable 2 Input
SAM4S Series [DATASHEET]
Atmel-11100K-ATARM-SAM4S-Datasheet_09-Jun-15
570
31.4 Product Dependencies
31.4.1 Pin Multiplexing
Each pin is configurable, depending on the product, as either a general-purpose I/O line only, or as an I/O line
multiplexed with one or two peripheral I/Os. As the multiplexing is hardware defined and thus product-dependent,
the hardware designer and programmer must carefully determine the configuration of the PIO Controller s r equired
by their application. When an I/O line is general-purpose only, i.e., not multiplexed with any peripheral I/O,
programming of the PIO Controller regarding the assignment to a peripheral has no effect and only the PIO
Controller can control how the pin is driven by the product.
31.4.2 Power Management
The Power Management Controller controls the peripheral clock in order to save power. Writing any of the
registers of the user interface does not require the peripheral clock to be enabled. This means that the
configuration of the I/O lines does not require the peripheral clock to be en abled.
However, when the clock is disabled, not all of the features of the PIO Controller are available, including glitch
filtering. Note that th e inpu t chan ge inter rupt, th e inte rrupt modes on a progr ammabl e event an d the r ead of th e pin
level require the cloc k to be valid at ed .
After a hardware reset, the peripheral clock is disabled by default.
The user must configure the Power Management Controller before any access to the input line information.
31.4.3 Interrupt Sources
For interrupt handling, the PIO Controllers are considered as user peripherals. This means that the PIO Controller
interrupt lines are connected among the interrupt sources. Refer to the PIO Controller peripheral identifier in the
Peripheral Identifiers table to identify the interrupt sources dedicated to the PIO Controllers. Using the PIO
Controller requires the Interrupt Controller to be programmed first.
The PIO Controller interrupt can be generated only if the peripheral clock is enabled.
Table 31-2. Peripheral IDs
Instance ID
PIOA 11
PIOB 12
PIOC 13
571
SAM4S Series [DATASHEET]
Atmel-11100K-ATARM-SAM4S-Datasheet_09-Jun-15
31.5 Functional Description
The PIO Controller features up to 32 fully-programmable I/O lines. Most of the control logic associated to each I/O
is represented in Figure 31-2. In this description each signal shown represents one of up to 32 possible indexes.
Figure 31-2. I/O Line Control Logic
31.5.1 Pull-up and Pull-down Resistor Control
Each I/O line is designed with an embedded pull-up resistor and an embedded pull-down resistor. The pull-up
resistor can be enabled or disabled by writing to the Pull-up Enable Register (PIO_PUER) or Pull-up Disable
Register (PIO_PUDR), respectively. Writing to these registers results in setting or clearing the corresponding bit in
the Pull-up Status Register (PIO_PUSR). Reading a on e in PIO_PUSR means the pull-up is disabled and reading
a zero means the pull-up is enabled. T he pull-down resistor can be enabled or disabled by writing the Pull-down
Enable Register (PIO_PPDER) or the Pull-down Disable Register (PIO_PPDDR), respectively. Writing in these
1
0
1
0
1
0
1
0
DQ DQ
DFF
1
0
1
0
11
00
01
10
Programmable
Glitch
or
Debouncing
Filter
PIO_PDSR[0] PIO_ISR[0]
PIO_IDR[0]
PIO_IMR[0]
PIO_IER[0]
PIO Interrupt
(Up to 32 possible inputs)
PIO_ISR[31]
PIO_IDR[31]
PIO_IMR[31]
PIO_IER[31]
Pad
PIO_PUDR[0]
PIO_PUSR[0]
PIO_PUER[0]
PIO_MDDR[0]
PIO_MDSR[0]
PIO_MDER[0]
PIO_CODR[0]
PIO_ODSR[0]
PIO_SODR[0]
PIO_PDR[0]
PIO_PSR[0]
PIO_PER[0]
PIO_ABCDSR1[0]
PIO_ODR[0]
PIO_OSR[0]
PIO_OER[0]
Peripheral Clock
Resynchronization
Stage
Peripheral A Input
Peripheral D Output Enable
Peripheral A Output Enable
EVENT
DETECTOR
DFF
PIO_IFDR[0]
PIO_IFSR[0]
PIO_IFER[0]
Peripheral Clock
Clock
Divider
PIO_IFSCSR[0]
PIO_IFSCER[0]
PIO_IFSCDR[0]
PIO_SCDR
Slow Clock
Peripheral B Output Enable
Peripheral C Output Enable
11
00
01
10
Peripheral D Output
Peripheral A Output
Peripheral B Output
Peripheral C Output
PIO_ABCDSR2[0]
Peripheral B Input
Peripheral C Input
Peripheral D Input
PIO_PPDDR[0]
PIO_PPDSR[0]
PIO_PPDER[0]
VDD
GND
Integrated
Pull-Down
Resistor
Integrated
Pull-Up
Resistor
div_slck
SAM4S Series [DATASHEET]
Atmel-11100K-ATARM-SAM4S-Datasheet_09-Jun-15
572
registers results in setting or clearing the corresponding bit in the Pull-down Status Register (PIO_PPDSR).
Reading a one in PIO_PPDSR means the pull-up is disabled and reading a zero means the pull-down is enabled.
Enabling the pull-down resistor while th e pull-up resistor is still enabled is not possible. In this case, the write of
PIO_PPDER for the relevant I/O line is discarded. Likewise, enabling the pull-up resistor while the pull-down
resistor is still enabled is not possible. In this case, the write of PIO_PUER for the relev ant I/O line is discarded.
Control of the pull-up resistor is possible regardless of the configuration of the I/O line.
After reset, depending on the I/O, pull-up or pull-down can be set.
31.5.2 I/O Line or Peripheral Function Selection
When a pin is multiplexed with one or two peripheral functions, the selection is controlled with the Enable Register
(PIO_PER) and the Disable Registe r (PIO_PDR) . The Status Register (PIO_PSR) is the result of the set and clear
registers and indicates whether the pin is controlled by the corresponding peripheral or by the PIO Controller. A
value of zero indicates that the pin is controlled by the corresponding on-chip peripheral selected in the ABCD
Select registers (PIO_ABCDSR1 and PIO_ABCDSR2). A value of one indicates the pin is controlled by the PIO
Controller.
If a pin is used as a general-purpose I/O line (not multiplexed with an on-chip peripheral), PIO_PER and PIO_PDR
have no effect and PIO_PSR returns a one for the corresponding bit.
After reset, th e I/O lines are controlled by the PI O Controller, i.e., PIO_PSR reset s at one. However, in some
events, it is important th at PIO lines are controlle d by the periphera l (as in the case of memory chip sele ct lines that
must be driven inactive after reset, or for address lines that must be driven low for booting out of an external
memory). Thus, the reset value of PIO_PSR is defined at the pr oduct level and depends on the multiplexing of the
device.
31.5.3 Peripheral A or B or C or D Selection
The PIO Controller provides multiplexing of up to four peripheral functions on a single pin. The selection is
performed by writing PIO_ABCDSR1 and PIO_ABCDSR2.
For each pin:
The corresponding bit at level zero in PIO_ABCDSR1 and the corresponding bit at level zero in
PIO_ABCDSR2 means peripheral A is selected.
The corresponding bit at level one in PIO_ABCDSR1 and the corresponding bit at level zero in
PIO_ABCDSR2 means peripheral B is selected.
The correspo nd ing bit at level zero in PIO_AB CDSR 1 an d th e cor re sp o ndi ng bit at level on e in
PIO_ABCDSR2 means peripheral C is selected.
The correspo nd ing bit at level on e in PIO _ABCDSR1 and the corresponding bit at level one in
PIO_ABCDSR2 means peripheral D is selected.
Note that multiplexing of peripheral lines A, B, C and D only affects the output line. The peripheral input lines are
always connec te d to th e pin input (se e Figure 31-2).
Writing in PIO_ABCDSR1 and PIO_ABCDSR2 manages the multiplex ing regardless of the config uration of the
pin. However, assignment of a pin to a peripheral function requires a write in PIO_ABCDSR1 and PIO_ABCDSR2
in addition to a write in PIO_PDR.
After reset, PIO_ABCDSR1 and PIO_ABCDSR2 are zero, thus indicating that all the PIO lines are configured on
peripheral A. However, peripheral A generally does not drive the pin as the PIO Controller resets in I/O line mode.
If the software selects a peripheral A, B, C or D which does not exist for a pin, no alternate functions are enabled
for this pin and the selection is taken into account. The PIO Controller does not carry out checks to prevent
selection of a peripheral which does not exist.
573
SAM4S Series [DATASHEET]
Atmel-11100K-ATARM-SAM4S-Datasheet_09-Jun-15
31.5.4 Output Control
When the I/O line is assigned to a peripher al function, i.e., the corre sponding bit in PIO_PSR is a t zero, the drive of
the I/O line is controlled by the peripheral. Peripheral A or B or C or D depending on the value in PIO_ABCDSR1
and PIO_ABCDSR2 determines whether the pin is driven or not.
When the I/O line is controlled by th e PIO Controller, the p in can be configured to be drive n. This is done by writing
the Output Enable Register (PIO_OER) and Output Disable Register (PIO_ODR). The results of these write
operations are detected in the Output Status Register (PIO_OSR). When a bit in this register is at zero, the
corresponding I/O line is used as an input only. When the bit is at one, the corresponding I/O line is driven by the
PIO Controller.
The level driven on an I/O line can be determined by writing in the Set Output Data Register (PIO_SODR ) and the
Clear Output Data Register (PIO_CODR). These write operations, respectively, set and clear the Output Data
Status Register (PIO_ODSR), which represents the data driven on the I/O lines. Writing in PIO_OER and
PIO_ODR manages PIO_OSR whether the pin is configured to be controlled by the PIO Controller or assigned to
a peripheral function. This enables configuration of the I/O line prior to setting it to be managed by the PIO
Controller.
Similarly, writing in PIO_SODR and PIO_CODR affects PIO_ODSR. This is important as it defines the first level
driven on the I/O line.
31.5.5 Synchronous Data Output
Clearing one or more PIO line(s) and setting another one or more PIO line(s) synchronously cannot be done by
using PIO_SODR and PIO_CODR. It requires two successive write operations into two different registers. To
overcome this, the PIO Controller offers a direct control of PIO outputs by single write access to PIO_ODSR. Only
bits unmasked by the Outp ut Write Stat us Register (PIO_OWSR) are written. The mask bits in PIO_OWSR are set
by writing to the Output Write Enable Register (PIO_OWER) and cleared by writing to the Output Write Disable
Register (PIO_OWDR).
After reset, the synchronous data output is disabled on all the I/O lines as PIO_OWSR resets at 0x0.
31.5.6 Multi-Drive Control (Open Drain)
Each I/O can be independently programmed in open drain by using the multi-drive feature. This feature permits
several drivers to be connected on the I/O line which is driven low only by each device. An external pull-up resistor
(or enabling of the internal one) is generally required to guarantee a high level on the line.
The multi-drive featur e is controlled by the Multi-driver Enable Register (PIO_MDER) and the Multi-driver Disable
Register (PIO_MDDR). The multi-drive can be selected whether the I/O line is controlled by the PIO Controller or
assigned to a peripheral function. The Multi-driver Status Register (PIO_MDSR) indicates the pins that are
configured to support external drivers.
After reset, the multi-drive feature is disabled on all pins, i.e., PIO_MDSR resets at value 0x0.
31.5.7 Output Line Timings
Figure 31-3 shows how the outputs ar e driven either by writing PIO_SODR or PIO_CODR, or by directly writing
PIO_ODSR. This last case is valid only if the corresponding bit in PIO_OWSR is set. Fi gure 3 1-3 also shows when
the feedback in the Pin Data Status Register (PIO_PDSR) is available.
SAM4S Series [DATASHEET]
Atmel-11100K-ATARM-SAM4S-Datasheet_09-Jun-15
574
Figure 31-3. Output Line Timings
31.5.8 Inputs
The level on each I/O line can be read thro ugh PIO_PDSR. This register indicates the level of the I/O lines
regardless of the ir configuration, whether uniquely a s an input, or driven by the PIO Controller, o r driven by a
peripheral.
Reading the I/O line levels requires the clock of the PIO Controller to be enabled, otherwise PIO_PDSR reads the
levels present on the I/O line at the time the cloc k was disab le d.
31.5.9 Input Glitch and Debouncing Filters
Optional input glitch and debouncing filters are independently pr ogrammable on each I/O line.
The glitch filter can filter a glitch with a duration of less than 1/2 pe rip her al clock a nd the de bouncing filter can filter
a pulse of less than 1/2 period of a programmable divided slow clock.
The selection between glitch filtering or debounce filtering is done by writing in the PIO Input Filter Slow Clock
Disable Register (PIO_IFSCDR) and the PIO Input Filter Slow Clock Enable Register (PIO_IFSCER). Writing
PIO_IFSCDR and PIO_IFSCER, respectively, sets and clears bits in the Input Filter Slow Clock Status Register
(PIO_IFSCSR).
The current sele ctio n statu s ca n be che cke d by rea ding th e PIO_IFSCSR.
If PIO_IFSCSR[i] = 0: The glitch filter can filter a glitch with a duration of less than 1/2 master clock period.
If PIO_IFSCSR[i] = 1: The debouncing filter can filter a pulse with a duration of less than 1/2 programmable
divided slow clock period.
For the debouncing filter, the period of the d ivided slow clock is define d by writ ing in the DIV field of the Slow Clock
Divider Debouncing Register (PIO_SCDR):
tdiv_slck = ((DIV + 1) × 2) × tslck
When the glitch or debo uncing filter is enabled, a glitch or p ulse with a duration of less than 1/2 se lected clock
cycle (selected clock represents peripheral clock or divided slow clock depending on PIO_IFSCDR and
PIO_IFSCER programming) is automatically rejected, while a pulse with a duration of one selected clock
(peripheral clock or divided slow clock) cycle or more is accepted. For pulse durations between 1/2 s electe d cl ock
cycle and one selected clock cycle, the pulse may or may not be taken into account, depending on the precise
timing of its occurrence. Thus for a pulse to be visible, it must exceed one selected clock cycle, whereas for a glitch
to be reliably filtered out, its duration must not exceed 1/2 selected clock cycle.
The filters also introduce some latencies, illustrated in Figure 31-4 and Figure 31-5.
2 cycles
APB Access
2 cycles
APB Access
Peripheral clock
Write PIO_SODR
Write PIO_ODSR at 1
PIO_ODSR
PIO_PDSR
Write PIO_CODR
Write PIO_ODSR at 0
575
SAM4S Series [DATASHEET]
Atmel-11100K-ATARM-SAM4S-Datasheet_09-Jun-15
The glitch filters are controlled by the Input Filter Enable Register (PIO _IFER), the Input Filter Disable Register
(PIO_IFDR) and the Inpu t Filter Status Register (PIO_IFSR). Writing PIO_IFER and PIO_IFDR respectively sets
and clears bits in PIO_IFSR. This last register enables the glitch filter on the I/O lines.
When the glitch and/or debouncing filter is enabled, it does not modify the behavior of the inputs on the
peripherals. It acts only on the value re ad in PIO_PDSR and on th e input change inte rrupt detection. The glitch and
debouncing filters require that the peripheral clock is enabled.
Figure 31-4. Input Glitch Filter Timing
Figure 31-5. Input Debouncing Filter Timing
31.5.10 Input Edge/Level Interrupt
The PIO Controller can be programmed to generate an interrupt when it detects an edge or a level on an I/O line.
The Input Edge/Level interrupt is contro lled by writing the Interrupt Enable Register (PIO_IER) and the Interrupt
Disable Register (PIO_IDR), which enable and disable the input change interrupt respectively by setting and
clearing the corr esponding bit in the In terrupt Mask Regi ster (PIO_IMR). As input ch ange detection is possible only
by comparing two successive samplings of the input of the I/O line, the peripheral clock must be enabled. The
Input Change interrupt is available regardless of the configuration of the I/O line, i.e., configured as an input only,
controlled by the PIO Controller or assigned to a peripheral function.
By default, the interrupt can be generated at any time an edge is detected on the input.
Some addition al interrupt modes c an be enabled/disable d by writing in the Ad ditional Interrupt Mod es Enable
Register (PIO_AIMER) and Additional Interrupt Modes Disable Register (PIO_AIMDR). The current state of this
selection can be read through the Additional Interrupt Modes Mask Register (PIO_AIMMR).
These additional modes are:
Peripheral clcok
Pin Level
PIO_PDSR
if PIO_IFSR = 0
PIO_PDSR
if PIO_IFSR = 1
1 cycle 1 cycle 1 cycle
up to 1.5 cycles
2 cycles
up to 2.5 cycles up to 2 cycles
1 cycle
1 cycle
PIO_IFCSR = 0
Divided Slow Clock
(div_slck)
Pin Level
PIO_PDSR
if PIO_IFSR = 0
PIO_PDSR
if PIO_IFSR = 1
1 cycle tdiv_slck
up to 1.5 cycles tdiv_slck
1 cycle tdiv_slck
up to 2 cycles tperipheral clock up to 2 cycles tperipheral clock
up to 2 cycles tperipheral clock
up to 2 cycles tperipheral clock
up to 1.5 cycles tdiv_slck
PIO_IFCSR = 1
SAM4S Series [DATASHEET]
Atmel-11100K-ATARM-SAM4S-Datasheet_09-Jun-15
576
Rising edge detection
Falling edge detection
Low-level detection
High-level detection
In order to select an additional interrupt mode:
The type of event detection (edge or level) must be selected by writing in the Edge Select Register
(PIO_ESR) and Level Select Register (PIO_LSR) which select, respectively, the edge and level detection.
The current status of this sele ct ion is acce ssib le th ro ug h th e Edg e /L eve l Status Re gist er (PIO _EL SR) .
The polarity of the event detection (rising/falling edge or high/low-level) must be selected by writing in the
Falling Edge/Low-Level Select Register (PIO_FELLSR) and Rising Edge/High-Level Select Register
(PIO_REHLSR) which allow to select falling or rising edge (if edge is selected in PIO_ELSR) edge or high-
or low-level detection (if level is selected in PIO_ELSR). The current status of this selection is accessible
through the Fall/Rise - Low/High Status Register (PIO_FRLHSR).
When an input edge or level is detected on an I/O line, the corresponding bit in the Interrupt Status Register
(PIO_ISR) is set. If the corresponding bit in PIO_IMR is set, the PIO Controller interrupt line is asserted.The
interrupt signals of the 32 channels are ORed-wired together to generate a single interrupt signal to the interrupt
controller.
When the software reads PIO_ISR, all the interrupts are automatically cleared. This signifies that all the interrupts
that are pending when PIO_ISR is read m ust be han dled. Wh en an In terrup t is enab led on a “level” , th e inte rrupt is
generated as long as the interrupt source is not cleared, even if some read accesses in PIO_ISR are performed.
577
SAM4S Series [DATASHEET]
Atmel-11100K-ATARM-SAM4S-Datasheet_09-Jun-15
Figure 31-6. Event Detector on Input Lines (Figure Represents Line 0)
Example of interrupt generation on following lines:
Rising edge on PIO line 0
Falling edge on PIO line 1
Rising edge on PIO line 2
Low-level on PIO line 3
High-level on PIO line 4
High-level on PIO line 5
Falling edge on PIO line 6
Rising edge on PIO line 7
Any edge on the othe r line s
Table 31-3 provides the required conf iguration for this example.
Event Detector
0
1
0
1
1
0
0
1
Edge
Detector
Falling Edge
Detector
Rising Edge
Detector
PIO_FELLSR[0]
PIO_FRLHSR[0]
PIO_REHLSR[0]
Low Level
Detector
High Level
Detector
PIO_ESR[0]
PIO_ELSR[0]
PIO_LSR[0]
PIO_AIMDR[0]
PIO_AIMMR[0]
PIO_AIMER[0]
Event detection on line 0
Resynchronized input on line 0
Table 31-3. Configuration for Example Interrupt Generation
Configuration Description
Interrupt Mode All the interrupt sources ar e enabled by writing 32’hFF FF_FFFF in PIO_IER.
Then the additional interrupt mode is enabled for lines 0 to 7 by writing 32’h0000_00FF in
PIO_AIMER.
Edge or Level Detection
Lines 3, 4 and 5 are configured in level detection by writing 32’h0000_0038 in PIO_LSR.
The other lines are configured in edge detection by default, if they have not been previously
configured. Otherwise, lines 0, 1, 2, 6 and 7 must be configured in edge detection by writing
32’h0000_00C7 in PIO_ESR.
Falling/Rising Edge or Low/High-Level
Detection
Lines 0, 2, 4, 5 and 7 are configured in rising edge or high-level detection by writi ng
32’h0000_00B5 in PIO_REHLSR.
The other lines are configured in falling edge or low-level detection by default if they have
not been previously configured. Otherwise, lines 1, 3 and 6 must be configured in falling
edge/low-level detecti on by writ ing 32’h0000_004A in PIO_ FELLSR.
SAM4S Series [DATASHEET]
Atmel-11100K-ATARM-SAM4S-Datasheet_09-Jun-15
578
Figure 31-7. Input Change Interrupt Timings When No Additional Interrupt Modes
31.5.11 I/O Lines Lock
When an I/O line is controlled by a periphe ral (particularly the Pulse Width Modulation Controller PWM), it can
become locked by the action of th is peripheral via a n input of the PIO Controller. When an I/O line is locked, the
write of the corresponding bit in PIO_PER, PIO_PDR, PIO_MDER, PIO_MDDR, PIO_PUDR, PIO_PUER,
PIO_ABCDSR1 an d PIO_ABCDSR2 is di scarded in order to lo ck its configuration. The user can know at anytime
which I/O line is locked by reading the PIO Lock Status Register (PIO_LOCKSR). Once an I/O line is locked, the
only way to unlock it is to apply a hardware reset to the PIO Controller.
31.5.12 Programmable Schmitt Trigger
It is possible to configure each in put for the Schmitt trigge r. By default the Schmitt tri gger is active. Disabling the
Schmitt trigger is requested when using the QTouch® Library.
31.5.13 Parallel Capture Mode
31.5.13.1 Overview
The PIO Controller integrates an interface able to read data from a CMOS digital image se nsor, a high-speed
parallel ADC, a DSP synchronous port in synchronous mode, etc. For better understanding and to ease reading,
the following description uses an example with a CMOS digital image sensor.
31.5.13.2 Functional Description
The CMOS digital image sensor provides a sensor clock, an 8-bit data synchronous with the sensor clock and two
data enables which are also synchronous with the sensor clock.
Peripheral clock
Pin Level
Read PIO_ISR APB Access
PIO_ISR
APB Access
Figure 31-8. PIO Controller Connection with CMOS Digital Image Sensor
PIO Controller
Parallel Capture
Mode CMOS Digital
Image Sensor
PDC
Data
Status
PIODCCLK
PIODC[7:0]
PIODCEN1
PIODCEN2
PCLK
DATA[7:0]
VSYNC
HSYNC
Events
579
SAM4S Series [DATASHEET]
Atmel-11100K-ATARM-SAM4S-Datasheet_09-Jun-15
As soon as the parallel capture mode is enabled by writing a one to the PCEN bit in PIO_PCMR, the I/O lines
connected to the sensor clock (PIODCCLK), the sensor data (PIODC[7:0]) and the sensor data enable signals
(PIODCEN1 and PIODCEN2) are configured automatically as inputs. To know which I/O lines are associated with
the sensor clock, the sensor data and the sensor data enable signals, refer to the I/O multiplexing table(s) in the
section “Package and Pinout”.
Once enabled, the p arallel capture mod e sample s the data at rising edge of the sensor clock and resynchronizes it
with the peripheral clock domain.
The size of the data which can be read in PIO_PCRHR can be programmed using the DSIZE field in PIO_PCMR.
If this data size is larger than 8 bits, then the parallel capture mode samples several sensor data to form a
concatenated data of size defined by DSIZE. Then this data is stored in PIO_PCRHR and the flag DRDY is set to
one in PIO_PCISR.
The parallel capture mode can take into account the sensor data enable signals or not. If the bit ALWYS is set to
zero in PIO_PCMR, the parallel capture mode samples the sensor data at the rising edge of the sensor clock only
if both data enable signals are active (at o ne). If the bit ALWYS is set to one, the parallel capture mode sa mples
the sensor data at the rising edge of the sensor clock whichever the data enable signals are.
The parallel ca pture mode can s ample the sensor data only one time out of two. This is particularly useful when
the user wa nts only to sample the lu minance Y of a CMOS digital image sensor which outputs a YUV4 22 data
stream. If the HALFS bit is set to zero in PIO_PCMR, the parallel capture mode samples the sensor data in the
conditions described above. If the HALFS bit is set to one in PIO_PCMR, the parallel capture mode samples the
sensor data in the conditions described above, but only one time out of two. Depending on the FRSTS bit in
PIO_PCMR, the sensor can either sample the even or odd sensor data. If sensor data are numbered in the order
that they are re ceived with an index from zero to n, if FRSTS equals zero then only data with an even index are
sampled. If FRSTS e qua ls one, th en only d ata with a n od d index are samp led. If data is re ady in PIO_PCRHR an d
it is not read before a new data is stored in PIO_PCRHR, then an overrun error occurs. The previous data is lost
and the OVRE flag in PIO_PCISR is set to one. This flag is automatically reset when PIO_PCISR is read (reset
after read).
Figure 31-9. Parallel Capture Mode Waveforms (DSIZE = 2, ALWYS = 0, HALFS = 0)
The parallel ca pture mode can be asso ciated with a reception channel of the Peripheral DMA
Controller (PDC). This perfor ms reception transfer from paralle l capture mode to a memory
buffer without any intervention from the CPU. Transfer status signals from PDC are available
in PIO_PCISR through the flags ENDRX and RXBUFF.
The flags DRDY, OVRE, ENDRX and RXBUFF can be a source of the PIO interrupt.
0x23 0x34 0x450x12 0x56 0x67 0x78 0x89
0x5645_3423
0x01
PIODCLK
PIODC[7:0]
PIODCEN1
PIODCEN2
DRDY (PIO_PCISR)
RDATA (PIO_PCRHR)
Read of PIO_PCISR
MCK
SAM4S Series [DATASHEET]
Atmel-11100K-ATARM-SAM4S-Datasheet_09-Jun-15
580
Figure 31-10. Parallel Capture Mode Wav eforms (DSIZE = 2, ALWYS = 1, HALFS = 0)
Figure 31-11. Parallel Capture Mode Waveforms (DSIZE = 2, ALWYS = 0, HALFS = 1, FRST S = 0)
0x23 0x34 0x450x12 0x56 0x67 0x78 0x89
0x3423_1201
0x01
0x7867_5645
PIODCLK
PIODC[7:0]
PIODCEN1
PIODCEN2
DRDY (PIO_PCISR)
RDATA (PIO_PCRHR)
Read of PIO_PCISR
MCK
0x23 0x34 0x450x12 0x56 0x67 0x78 0x89
0x6745_2301
PIODCLK
PIODC[7:0]
PIODCEN1
PIODCEN2
DRDY (PIO_PCISR)
RDATA (PIO_PCRHR)
0x01
Read of PIO_PCISR
MCK
581
SAM4S Series [DATASHEET]
Atmel-11100K-ATARM-SAM4S-Datasheet_09-Jun-15
Figure 31-12. Parallel Capture Mod e Waveforms (DSIZE = 2, ALWYS = 0, HALFS = 1, FRSTS = 1)
31.5.13.3 Restrictions
Configuration fields DSIZE, ALWYS, HALFS and FRSTS in PIO_PCMR can be changed ONLY if the parallel
capture mode is disabled at this time (PCEN = 0 in PIO_PCMR).
The frequency of peripheral clock must be strictly superior to two times the frequency of the clock of the
device which generates the parallel data.
31.5.13.4 Programming Sequence
0x23 0x34 0x450x12 0x56 0x67 0x78 0x89
0x7856_3412
0x01
PIODCLK
PIODC[7:0]
PIODCEN1
PIODCEN2
DRDY (PIO_PCISR)
RDATA (PIO_PCRHR)
Read of PIO_PCISR
MCK
Without PDC
1. Write PIO_PCIDR and PIO_PCIER in order to configure the parallel capture mode
interrupt mask.
2. Write PIO_PCMR to set the fields DSIZE, ALWYS, HALFS and FRSTS in order to
configure the parallel capture mode WITHOUT enabling the parallel capture mode.
3. Write PIO_PCMR to set the PCEN bit to one in order to enable the parallel capture
mode WITHOUT changing the previous configuration.
4. Wait for a data ready by polling the DRDY flag in PIO_PCISR or by waiting for the
corresponding interrupt.
5. Check OVRE flag in PIO_PCISR.
6. Read the data in PIO_PCRHR.
7. If new data are expected, go to step 4.
8. Write PIO_PCMR to set the PCEN bit to zero in order to disable the parallel capture
mode WITHOUT changing the previous configuration.
With PDC
SAM4S Series [DATASHEET]
Atmel-11100K-ATARM-SAM4S-Datasheet_09-Jun-15
582
1. Write PIO_PCIDR and PIO_PCIER in order to configure the parallel capture mode
interrupt mask.
2. Configure PDC transfer in PDC registers.
3. Write PIO_PCMR to set the fields DSIZE, ALWYS, HALFS and FRSTS in order to
configure the parallel capture mode WITHOUT enabling the parallel capture mode.
4. Write PIO_PCMR to set PCEN bit to one in order to enable the parallel capture mode
WITHOUT changing the previous configuration.
5. W ait for end of transfer by waiting for the interrupt corresponding to the flag ENDRX in
PIO_PCISR.
6. Check OVRE flag in PIO_PCISR.
7. If a new buffer transfer is expected, go to step 5.
8. Write PIO_PCMR to set the PCEN bit to zero in order to disable the parallel capture
mode WITHOUT changing the previous configuration.
583
SAM4S Series [DATASHEET]
Atmel-11100K-ATARM-SAM4S-Datasheet_09-Jun-15
31.5.14 I/O Lines Programming Example
The programming example shown in Table 31-4 is used to obtain the following configuration:
4-bit output port on I/O lines 0 to 3 (should be written in a single write operation), open- drain, with pull-up
resistor
Four output signals on I/O lines 4 to 7 (to drive LEDs for example), driven high and low, no pull-up resistor,
no pull-down resistor
Four input signals on I/O lines 8 to 11 (to read push-button states for example), with pull-up resistors, glitch
filters and input change interrupts
Four input signals on I/O line 12 to 15 to read an external device status (polled, thus no input chan ge
interrupt), no pull-up resistor, no glitch filter
I/O lines 16 to 19 assigned to peripheral A functions with pull-up resistor
I/O lines 20 to 23 assigned to peripheral B functions with pull-down resistor
I/O lines 24 to 27 assigned to peripheral C with input change interrupt, no pull-up resistor and no pull-down
resistor
I/O lines 28 to 31 assigned to peripheral D, no pull-up resistor and no pull-down resistor
Table 31-4. Programming Example
Register Value to be Written
PIO_PER 0x0000_FFFF
PIO_PDR 0xFFFF_0000
PIO_OER 0x0000_00FF
PIO_ODR 0xFFFF_FF00
PIO_IFER 0x0000_0F00
PIO_IFDR 0xFFFF_F0FF
PIO_SODR 0x0000_0000
PIO_CODR 0x0FFF_FFFF
PIO_IER 0x0F00_0F00
PIO_IDR 0xF0FF_F0FF
PIO_MDER 0x0000_000F
PIO_MDDR 0xFFFF_FFF0
PIO_PUDR 0xFFF0_00F0
PIO_PUER 0x000F_FF0F
PIO_PPDDR 0xFF0F_FFFF
PIO_PPDER 0x00F0_0000
PIO_ABCDSR1 0xF0F0_0000
PIO_ABCDSR2 0xFF00_0000
PIO_OWER 0x0000_000F
PIO_OWDR 0x0FFF_ FFF0
SAM4S Series [DATASHEET]
Atmel-11100K-ATARM-SAM4S-Datasheet_09-Jun-15
584
31.5.15 Register Write Protection
To prevent any single software error from corrupting PIO behavior, certain registers in the address space can be
write-protected by setting the WPEN bit in the PIO Write Protection Mode Register (PIO_WPMR).
If a write access to a write-protected register is detected, the WPVS flag in the PIO Write Protection Status
Register (PIO_WPSR) is set and the field WPVSRC indicates the register in which the write access has been
attempted.
The WPVS bit is automatically cleared after reading the PIO_WPSR.
The following registers can be write-protected:
PIO Enable Register
PIO Disable Register
PIO Output Enable Register
PIO Output Disab le Re gist er
PIO Input Filter Enable Register
PIO Input Filter Disable Register
PIO Multi-driver Enable Register
PIO Multi-driver Disable Register
PIO Pull-Up Disable Register
PIO Pull-Up Enable Register
PIO Peripheral ABCD Select Register 1
PIO Peripheral ABCD Select Register 2
PIO Output Write Enable Register
PIO Output Write Disable Register
PIO Pad Pull-Down Disable Register
PIO Pad Pull-Down Enable Register
PIO Parallel Capture Mode Register
585
SAM4S Series [DATASHEET]
Atmel-11100K-ATARM-SAM4S-Datasheet_09-Jun-15
31.6 Parallel Input/Output Controller (PIO) User Interface
Each I/O line controlled by the PIO Controller is associated with a bit in each of the PIO Controller User Interface
registers. Each register is 32-bit wide. If a parallel I/O line is not defined, writing to the corresponding bits has no
effect. Undefined bits read zero. If the I/O line is not multiplexed with any peripheral, the I/O line is controlled by the
PIO Controller and PIO_PSR returns one systematically.
Table 31-5 . Register Mapping
Offset Register Name Access Reset
0x0000 PIO Enable Register PIO_PER Write-only –
0x0004 PIO Disable Register PIO_PDR Write-only –
0x0008 PIO Status Register PIO_PSR Read-only (1)
0x000C Reserved – – –
0x0010 Output Enable Register PIO_OER Write-only –
0x0014 Output Disable Register PIO_ODR Write-only –
0x0018 Output Status Register PIO_OSR Read-o nly 0x00000000
0x001C Reserved – – –
0x0020 Glitch Input Filter Enable Register PIO_IFER Write-only –
0x0024 Glitch Input Filter Disable Register PIO_IFDR Write-only –
0x0028 Glitch Input Filter Status Register PIO_IFSR Read-only 0x00000000
0x002C Reserved – – –
0x0030 Set Output Data Register PIO_SODR Write-only –
0x0034 Clear Output Data Register PIO_CODR Write-only
0x0038 Output Data Status Register PIO_ODSR Read-only
or(2)
Read/Write –
0x003C Pin Data Status Register PIO_PDSR Read-only (3)
0x0040 Interrupt Enable Register PIO_IER Write-only –
0x0044 Interrupt Disable Register PIO_IDR Write-only –
0x0048 Interrupt Mask Register PIO_IMR Read-o nly 0x00000000
0x004C Interrupt Status Register(4) PIO_ISR Read-only 0x00000000
0x0050 Multi-driver Enable Register PIO_MDER Write-only –
0x0054 Multi-driver Disable Register PIO_MDDR Write-only –
0x0058 Multi-driver Status Register PIO_MDSR Read-only 0x0000000 0
0x005C Reserved – – –
0x0060 Pull-up Disable Register PIO_PUDR Write-only –
0x0064 Pull-up Enable Register PIO_PUER Write-only –
0x0068 Pad Pull-up Status Register PIO_PUSR Read-only (1)
0x006C Reserved – – –
SAM4S Series [DATASHEET]
Atmel-11100K-ATARM-SAM4S-Datasheet_09-Jun-15
586
0x0070 Peripheral Select Register 1 PIO_ABCDSR1 Read/Write 0x00000000
0x0074 Peripheral Select Register 2 PIO_ABCDSR2 Read/Write 0x00000000
0x0078–0x007C Reserved – – –
0x0080 Input Filter Slow Clock Disable Register PIO_IFSCDR Write-onl y –
0x0084 Input Filter Slow Clock Enable Register PIO_IFSCER Write-only –
0x0088 Input Filter Slow Clock Status Register PIO_IFSCSR Read-only 0x00000000
0x008C Slow Clock Divider Debouncing Register PIO_SCDR Read/Write 0x000 00000
0x0090 Pad Pull-do wn Disable Register PIO_PPDDR Write-only –
0x0094 Pad Pull-do wn Enable Register PIO_PPDER Write-only –
0x0098 Pad Pull-do wn Status Register PIO_PPDSR Read-only (1)
0x009C Reserved – – –
0x00A0 Output Write Enable PIO_OWER Write-only –
0x00A4 Output Write Disable PIO_OWDR Write-only –
0x00A8 Output Write Status Register PIO_OWSR Read-only 0x00000000
0x00AC Reserved – – –
0x00B0 Additional Interrupt Modes Enable Register PIO_AIMER Write-only –
0x00B4 Additional Interrupt Modes Disable Register PIO_AIMDR Write-only –
0x00B8 Additional Interrupt Modes Mask Register PIO_AIMMR Read-only 0x00000000
0x00BC Reserved – – –
0x00C0 Edge Select Register PIO_ESR Write-only –
0x00C4 Level Select Register PIO_LSR Write-only –
0x00C8 Edge/Level S tatus Register PIO_ELSR Read-only 0x00000000
0x00CC Reserved – – –
0x00D0 Falling Edge/Low-Level Select Registe r PIO_FELLSR Write-only –
0x00D4 Rising Edge/High-Level Select Register PIO_REHLSR Write-only –
0x00D8 Fall/Rise - Low/High Status Register PIO_FRLHSR Read-only 0x00000000
0x00DC Reserved – – –
0x00E0 Lock Status PIO_LOCKSR Read-only 0x00000000
0x00E4 Write Protection Mode Register PIO_WPMR Read/Write 0x00000000
0x00E8 Write Protection Status Register PIO_WPSR Read-only 0x00000000
0x00EC–0x00FC Reserved – – –
0x0100 Schmitt Trigger Register PIO_SCHMITT Read/Write 0x00000000
0x0104–0x010C Reserved – – –
0x0110 Reserved – – –
0x0114–0x011C Reserved – – –
0x0120–0x014C Reserved – – –
0x0150 Parallel Capture Mode Register PIO_PCMR Read/Write 0x00000000
Table 31-5. Register Mapping (Continued)
Offset Register Name Access Reset
587
SAM4S Series [DATASHEET]
Atmel-11100K-ATARM-SAM4S-Datasheet_09-Jun-15
Notes: 1. Reset value depends on the product implementation.
2. PIO_ODSR is Read-only or Read/Write depending on PIO_OWSR I/O lines.
3. Reset value of PIO_PDSR depends on the level of the I/O lines. Reading the I/O line levels requires the clock of the PIO
Controller to be enabled, otherwise PIO_PDSR reads the levels present on the I/O line at the time the clock was disabled.
4. PIO_ISR is reset at 0x0. However, the first read of the register may read a different value as input changes may have
occurred.
5. If an offset is not listed in the table it must be considered as reserved.
0x0154 Parallel Capture Interrupt Enable Register PIO_PCIER Write-only –
0x0158 Parallel Capture Interrupt Disable Register PIO_PCIDR Write-only –
0x015C Parallel Capture Interrupt Mask Register PIO_PCIMR Read-only 0x00000000
0x0160 Parallel Capture Interrupt Status Register PIO_PCISR Read-only 0x00000000
0x0164 Parallel Capture Rece ption Holding Register PIO_PCRHR Read-only 0x00000000
0x0168–0x018C Reserved for PDC Registers – – –
Table 31-5. Register Mapping (Continued)
Offset Register Name Access Reset
SAM4S Series [DATASHEET]
Atmel-11100K-ATARM-SAM4S-Datasheet_09-Jun-15
588
31.6.1 PIO Enable Register
Name: PIO_PER
Address: 0x400E0E00 (PIOA), 0x400E1000 (PIOB), 0x400E1200 (PIOC)
Access: Write-only
This register can only be written if the WPEN bit is cleared in the PIO Write Protection Mode Register.
• P0–P31: PIO Enable
0: No effect.
1: Enables the PIO to control the corresponding pin (disables peripheral control of the pin).
31 30 29 28 27 26 25 24
P31 P30 P29 P28 P27 P26 P25 P24
23 22 21 20 19 18 17 16
P23 P22 P21 P20 P19 P18 P17 P16
15 14 13 12 11 10 9 8
P15 P14 P13 P12 P11 P10 P9 P8
76543210
P7 P6 P5 P4 P3 P2 P1 P0
589
SAM4S Series [DATASHEET]
Atmel-11100K-ATARM-SAM4S-Datasheet_09-Jun-15
31.6.2 PIO Disable Register
Name: PIO_PDR
Address: 0x400E0E04 (PIOA), 0x400E1004 (PIOB), 0x400E1204 (PIOC)
Access: Write-only
This register can only be written if the WPEN bit is cleared in the PIO Write Protection Mode Register.
• P0–P31 : PIO Disa ble
0: No effect.
1: Disables the PIO from controlling the corresponding pin (enables peripheral control of the pin).
31 30 29 28 27 26 25 24
P31 P30 P29 P28 P27 P26 P25 P24
23 22 21 20 19 18 17 16
P23 P22 P21 P20 P19 P18 P17 P16
15 14 13 12 11 10 9 8
P15 P14 P13 P12 P11 P10 P9 P8
76543210
P7 P6 P5 P4 P3 P2 P1 P0
SAM4S Series [DATASHEET]
Atmel-11100K-ATARM-SAM4S-Datasheet_09-Jun-15
590
31.6.3 PIO Status Register
Name: PIO_PSR
Address: 0x400E0E08 (PIOA), 0x400E1008 (PIOB), 0x400E1208 (PIOC)
Access: Read-only
• P0–P31: PIO Status
0: PIO is inactive on the corresponding I/O line (peripheral is active).
1: PIO is active on the corresponding I/O line (peripheral is inactive).
31 30 29 28 27 26 25 24
P31 P30 P29 P28 P27 P26 P25 P24
23 22 21 20 19 18 17 16
P23 P22 P21 P20 P19 P18 P17 P16
15 14 13 12 11 10 9 8
P15 P14 P13 P12 P11 P10 P9 P8
76543210
P7 P6 P5 P4 P3 P2 P1 P0
591
SAM4S Series [DATASHEET]
Atmel-11100K-ATARM-SAM4S-Datasheet_09-Jun-15
31.6.4 PIO Output Enable Register
Name: PIO_OER
Address: 0x400E0E10 (PIOA), 0x400E1010 (PIOB), 0x400E1210 (PIOC)
Access: Write-only
This register can only be written if the WPEN bit is cleared in the PIO Write Protection Mode Register.
• P0–P31: Output Enable
0: No effect.
1: Enables the output on the I/O line.
31 30 29 28 27 26 25 24
P31 P30 P29 P28 P27 P26 P25 P24
23 22 21 20 19 18 17 16
P23 P22 P21 P20 P19 P18 P17 P16
15 14 13 12 11 10 9 8
P15 P14 P13 P12 P11 P10 P9 P8
76543210
P7 P6 P5 P4 P3 P2 P1 P0
SAM4S Series [DATASHEET]
Atmel-11100K-ATARM-SAM4S-Datasheet_09-Jun-15
592
31.6.5 PIO Output Disable Register
Name: PIO_ODR
Address: 0x400E0E14 (PIOA), 0x400E1014 (PIOB), 0x400E1214 (PIOC)
Access: Write-only
This register can only be written if the WPEN bit is cleared in the PIO Write Protection Mode Register.
• P0–P31: Output Disable
0: No effect.
1: Disables the output on the I/O line.
31 30 29 28 27 26 25 24
P31 P30 P29 P28 P27 P26 P25 P24
23 22 21 20 19 18 17 16
P23 P22 P21 P20 P19 P18 P17 P16
15 14 13 12 11 10 9 8
P15 P14 P13 P12 P11 P10 P9 P8
76543210
P7 P6 P5 P4 P3 P2 P1 P0
593
SAM4S Series [DATASHEET]
Atmel-11100K-ATARM-SAM4S-Datasheet_09-Jun-15
31.6.6 PIO Output Status Register
Name: PIO_OSR
Address: 0x400E0E18 (PIOA), 0x400E1018 (PIOB), 0x400E1218 (PIOC)
Access: Read-only
• P0–P31: Output Status
0: The I/O line is a pure input.
1: The I/O line is enabled in output.
31 30 29 28 27 26 25 24
P31 P30 P29 P28 P27 P26 P25 P24
23 22 21 20 19 18 17 16
P23 P22 P21 P20 P19 P18 P17 P16
15 14 13 12 11 10 9 8
P15 P14 P13 P12 P11 P10 P9 P8
76543210
P7 P6 P5 P4 P3 P2 P1 P0
SAM4S Series [DATASHEET]
Atmel-11100K-ATARM-SAM4S-Datasheet_09-Jun-15
594
31.6.7 PIO Input Filter Enable Register
Name: PIO_IFER
Address: 0x400E0E20 (PIOA), 0x400E1020 (PIOB), 0x400E1220 (PIOC)
Access: Write-only
This register can only be written if the WPEN bit is cleared in the PIO Write Protection Mode Register.
• P0–P31: Input Filter Enable
0: No effect.
1: Enables the input glitch filter on the I/O line.
31 30 29 28 27 26 25 24
P31 P30 P29 P28 P27 P26 P25 P24
23 22 21 20 19 18 17 16
P23 P22 P21 P20 P19 P18 P17 P16
15 14 13 12 11 10 9 8
P15 P14 P13 P12 P11 P10 P9 P8
76543210
P7 P6 P5 P4 P3 P2 P1 P0
595
SAM4S Series [DATASHEET]
Atmel-11100K-ATARM-SAM4S-Datasheet_09-Jun-15
31.6.8 PIO Input Filter Disable Register
Name: PIO_IFDR
Address: 0x400E0E24 (PIOA), 0x400E1024 (PIOB), 0x400E1224 (PIOC)
Access: Write-only
This register can only be written if the WPEN bit is cleared in the PIO Write Protection Mode Register.
• P0–P31: Input Filter Disable
0: No effect.
1: Disables the input glitch filter on the I/O line.
31 30 29 28 27 26 25 24
P31 P30 P29 P28 P27 P26 P25 P24
23 22 21 20 19 18 17 16
P23 P22 P21 P20 P19 P18 P17 P16
15 14 13 12 11 10 9 8
P15 P14 P13 P12 P11 P10 P9 P8
76543210
P7 P6 P5 P4 P3 P2 P1 P0
SAM4S Series [DATASHEET]
Atmel-11100K-ATARM-SAM4S-Datasheet_09-Jun-15
596
31.6.9 PIO Input Filter Status Register
Name: PIO_IFSR
Address: 0x400E0E28 (PIOA), 0x400E1028 (PIOB), 0x400E1228 (PIOC)
Access: Read-only
• P0–P31: Input Filter Status
0: The input glitch filter is disabled on the I/O line.
1: The input glitch filter is enabled on the I/O line.
31 30 29 28 27 26 25 24
P31 P30 P29 P28 P27 P26 P25 P24
23 22 21 20 19 18 17 16
P23 P22 P21 P20 P19 P18 P17 P16
15 14 13 12 11 10 9 8
P15 P14 P13 P12 P11 P10 P9 P8
76543210
P7 P6 P5 P4 P3 P2 P1 P0
597
SAM4S Series [DATASHEET]
Atmel-11100K-ATARM-SAM4S-Datasheet_09-Jun-15
31.6.10 PIO Set Output Data Register
Name: PIO_SODR
Address: 0x400E0E30 (PIOA), 0x400E1030 (PIOB), 0x400E1230 (PIOC)
Access: Write-only
• P0–P31: Set Output Data
0: No effect.
1: Sets the data to be driven on the I/O line.
31 30 29 28 27 26 25 24
P31 P30 P29 P28 P27 P26 P25 P24
23 22 21 20 19 18 17 16
P23 P22 P21 P20 P19 P18 P17 P16
15 14 13 12 11 10 9 8
P15 P14 P13 P12 P11 P10 P9 P8
76543210
P7 P6 P5 P4 P3 P2 P1 P0
SAM4S Series [DATASHEET]
Atmel-11100K-ATARM-SAM4S-Datasheet_09-Jun-15
598
31.6.11 PIO Clear Output Data Register
Name: PIO_CODR
Address: 0x400E0E34 (PIOA), 0x400E1034 (PIOB), 0x400E1234 (PIOC)
Access: Write-only
• P0–P31: Clear Output Data
0: No effect.
1: Clears the data to be driven on the I/O line.
31 30 29 28 27 26 25 24
P31 P30 P29 P28 P27 P26 P25 P24
23 22 21 20 19 18 17 16
P23 P22 P21 P20 P19 P18 P17 P16
15 14 13 12 11 10 9 8
P15 P14 P13 P12 P11 P10 P9 P8
76543210
P7 P6 P5 P4 P3 P2 P1 P0
599
SAM4S Series [DATASHEET]
Atmel-11100K-ATARM-SAM4S-Datasheet_09-Jun-15
31.6.12 PIO Output Data Status Register
Name: PIO_ODSR
Address: 0x400E0E38 (PIOA), 0x400E1038 (PIOB), 0x400E1238 (PIOC)
Access: Read-only or Read/Write
• P0–P31 : Ou t put Data Status
0: The data to be driven on the I/O line is 0.
1: The data to be driven on the I/O line is 1.
31 30 29 28 27 26 25 24
P31 P30 P29 P28 P27 P26 P25 P24
23 22 21 20 19 18 17 16
P23 P22 P21 P20 P19 P18 P17 P16
15 14 13 12 11 10 9 8
P15 P14 P13 P12 P11 P10 P9 P8
76543210
P7 P6 P5 P4 P3 P2 P1 P0
SAM4S Series [DATASHEET]
Atmel-11100K-ATARM-SAM4S-Datasheet_09-Jun-15
600
31.6.13 PIO Pin Data Status Register
Name: PIO_PDSR
Address: 0x400E0E3C (PIOA), 0x400E103C (PIOB), 0x400E123C (PIOC)
Access: Read-only
• P0–P31 : Ou t put Data Status
0: The I/O line is at level 0.
1: The I/O line is at level 1.
31 30 29 28 27 26 25 24
P31 P30 P29 P28 P27 P26 P25 P24
23 22 21 20 19 18 17 16
P23 P22 P21 P20 P19 P18 P17 P16
15 14 13 12 11 10 9 8
P15 P14 P13 P12 P11 P10 P9 P8
76543210
P7 P6 P5 P4 P3 P2 P1 P0
601
SAM4S Series [DATASHEET]
Atmel-11100K-ATARM-SAM4S-Datasheet_09-Jun-15
31.6.14 PIO Interrupt Enable Register
Name: PIO_IER
Address: 0x400E0E40 (PIOA), 0x400E1040 (PIOB), 0x400E1240 (PIOC)
Access: Write-only
• P0–P31: Input Change Interrupt Enable
0: No effect.
1: Enables the input change interrupt on the I/O line.
31 30 29 28 27 26 25 24
P31 P30 P29 P28 P27 P26 P25 P24
23 22 21 20 19 18 17 16
P23 P22 P21 P20 P19 P18 P17 P16
15 14 13 12 11 10 9 8
P15 P14 P13 P12 P11 P10 P9 P8
76543210
P7 P6 P5 P4 P3 P2 P1 P0
SAM4S Series [DATASHEET]
Atmel-11100K-ATARM-SAM4S-Datasheet_09-Jun-15
602
31.6.15 PIO Interrupt Disable Register
Name: PIO_IDR
Address: 0x400E0E44 (PIOA), 0x400E1044 (PIOB), 0x400E1244 (PIOC)
Access: Write-only
• P0–P31: Input Change Interrupt Disable
0: No effect.
1: Disables the input change interrupt on the I/O line.
31 30 29 28 27 26 25 24
P31 P30 P29 P28 P27 P26 P25 P24
23 22 21 20 19 18 17 16
P23 P22 P21 P20 P19 P18 P17 P16
15 14 13 12 11 10 9 8
P15 P14 P13 P12 P11 P10 P9 P8
76543210
P7 P6 P5 P4 P3 P2 P1 P0
603
SAM4S Series [DATASHEET]
Atmel-11100K-ATARM-SAM4S-Datasheet_09-Jun-15
31.6.16 PIO Interrupt Mask Register
Name: PIO_IMR
Address: 0x400E0E48 (PIOA), 0x400E1048 (PIOB), 0x400E1248 (PIOC)
Access: Read-only
• P0–P31: Input Change Interrupt Mask
0: Input change interrupt is disabled on the I/O line.
1: Input change interrupt is enabled on the I/O line.
31 30 29 28 27 26 25 24
P31 P30 P29 P28 P27 P26 P25 P24
23 22 21 20 19 18 17 16
P23 P22 P21 P20 P19 P18 P17 P16
15 14 13 12 11 10 9 8
P15 P14 P13 P12 P11 P10 P9 P8
76543210
P7 P6 P5 P4 P3 P2 P1 P0
SAM4S Series [DATASHEET]
Atmel-11100K-ATARM-SAM4S-Datasheet_09-Jun-15
604
31.6.17 PIO Interrupt Status Register
Name: PIO_ISR
Address: 0x400E0E4C (PIOA), 0x400E104C (PIOB), 0x400E124C (PIOC)
Access: Read-only
• P0–P31: Input Change Interrupt Sta tus
0: No input change has been detected on the I/O line since PIO_ISR was last read or since reset.
1: At least one input change has been detected on the I/O line since PIO_ISR was last read or since reset.
31 30 29 28 27 26 25 24
P31 P30 P29 P28 P27 P26 P25 P24
23 22 21 20 19 18 17 16
P23 P22 P21 P20 P19 P18 P17 P16
15 14 13 12 11 10 9 8
P15 P14 P13 P12 P11 P10 P9 P8
76543210
P7 P6 P5 P4 P3 P2 P1 P0
605
SAM4S Series [DATASHEET]
Atmel-11100K-ATARM-SAM4S-Datasheet_09-Jun-15
31.6.18 PIO Multi-driver Enable Register
Name: PIO_MDER
Address: 0x400E0E50 (PIOA), 0x400E1050 (PIOB), 0x400E1250 (PIOC)
Access: Write-only
This register can only be written if the WPEN bit is cleared in the PIO Write Protection Mode Register.
• P0-P31: Multi-drive Enable
0: No effect.
1: Enables multi-drive on the I/O line.
31 30 29 28 27 26 25 24
P31 P30 P29 P28 P27 P26 P25 P24
23 22 21 20 19 18 17 16
P23 P22 P21 P20 P19 P18 P17 P16
15 14 13 12 11 10 9 8
P15 P14 P13 P12 P11 P10 P9 P8
76543210
P7 P6 P5 P4 P3 P2 P1 P0
SAM4S Series [DATASHEET]
Atmel-11100K-ATARM-SAM4S-Datasheet_09-Jun-15
606
31.6.19 PIO Multi-driver Disable Register
Name: PIO_MDDR
Address: 0x400E0E54 (PIOA), 0x400E1054 (PIOB), 0x400E1254 (PIOC)
Access: Write-only
This register can only be written if the WPEN bit is cleared in the PIO Write Protection Mode Register.
• P0–P31: Multi-drive Disable
0: No effect.
1: Disables multi-drive on the I/O line.
31 30 29 28 27 26 25 24
P31 P30 P29 P28 P27 P26 P25 P24
23 22 21 20 19 18 17 16
P23 P22 P21 P20 P19 P18 P17 P16
15 14 13 12 11 10 9 8
P15 P14 P13 P12 P11 P10 P9 P8
76543210
P7 P6 P5 P4 P3 P2 P1 P0
607
SAM4S Series [DATASHEET]
Atmel-11100K-ATARM-SAM4S-Datasheet_09-Jun-15
31.6.20 PIO Multi-driver Status Register
Name: PIO_MDSR
Address: 0x400E0E58 (PIOA), 0x400E1058 (PIOB), 0x400E1258 (PIOC)
Access: Read-only
• P0–P31: Multi-drive Status
0: The multi-drive is disabled on the I/O line. T he pin is drive n at high- and low-level.
1: The multi-drive is enabled on the I/O line. The pin is driven at low-level only.
31 30 29 28 27 26 25 24
P31 P30 P29 P28 P27 P26 P25 P24
23 22 21 20 19 18 17 16
P23 P22 P21 P20 P19 P18 P17 P16
15 14 13 12 11 10 9 8
P15 P14 P13 P12 P11 P10 P9 P8
76543210
P7 P6 P5 P4 P3 P2 P1 P0
SAM4S Series [DATASHEET]
Atmel-11100K-ATARM-SAM4S-Datasheet_09-Jun-15
608
31.6.21 PIO Pull-Up Disable Register
Name: PIO_PUDR
Address: 0x400E0E60 (PIOA), 0x400E1060 (PIOB), 0x400E1260 (PIOC)
Access: Write-only
This register can only be written if the WPEN bit is cleared in the PIO Write Protection Mode Register.
• P0–P31: Pull-Up Disable
0: No effect.
1: Disables the pull-up resistor on the I/O line.
31 30 29 28 27 26 25 24
P31 P30 P29 P28 P27 P26 P25 P24
23 22 21 20 19 18 17 16
P23 P22 P21 P20 P19 P18 P17 P16
15 14 13 12 11 10 9 8
P15 P14 P13 P12 P11 P10 P9 P8
76543210
P7 P6 P5 P4 P3 P2 P1 P0
609
SAM4S Series [DATASHEET]
Atmel-11100K-ATARM-SAM4S-Datasheet_09-Jun-15
31.6.22 PIO Pull-Up Enable Regi ster
Name: PIO_PUER
Address: 0x400E0E64 (PIOA), 0x400E1064 (PIOB), 0x400E1264 (PIOC)
Access: Write-only
This register can only be written if the WPEN bit is cleared in the PIO Write Protection Mode Register.
• P0–P31: Pull-Up Enable
0: No effect.
1: Enables the pull-up resistor on the I/O line.
31 30 29 28 27 26 25 24
P31 P30 P29 P28 P27 P26 P25 P24
23 22 21 20 19 18 17 16
P23 P22 P21 P20 P19 P18 P17 P16
15 14 13 12 11 10 9 8
P15 P14 P13 P12 P11 P10 P9 P8
76543210
P7 P6 P5 P4 P3 P2 P1 P0
SAM4S Series [DATASHEET]
Atmel-11100K-ATARM-SAM4S-Datasheet_09-Jun-15
610
31.6.23 PIO Pull-Up Status Register
Name: PIO_PUSR
Address: 0x400E0E68 (PIOA), 0x400E1068 (PIOB), 0x400E1268 (PIOC)
Access: Read-only
• P0–P31: Pull-Up Status
0: Pull-up resistor is enabled on the I/O line.
1: Pull-up resistor is disabled on the I/O line.
31 30 29 28 27 26 25 24
P31 P30 P29 P28 P27 P26 P25 P24
23 22 21 20 19 18 17 16
P23 P22 P21 P20 P19 P18 P17 P16
15 14 13 12 11 10 9 8
P15 P14 P13 P12 P11 P10 P9 P8
76543210
P7 P6 P5 P4 P3 P2 P1 P0
611
SAM4S Series [DATASHEET]
Atmel-11100K-ATARM-SAM4S-Datasheet_09-Jun-15
31.6.24 PIO Peripheral ABCD Select Register 1
Name: PIO_ABCDSR1
Access: Read/Write
This register can only be written if the WPEN bit is cleared in the PIO Write Protection Mode Register.
• P0–P31: Peripheral Select
If the same bit is set to 0 in PIO_ABCDSR2:
0: Assigns the I/ O line to the Peripheral A function .
1: Assigns the I/ O line to the Peripheral B function .
If the same bit is set to 1 in PIO_ABCDSR2:
0: Assigns the I/ O line to the Peripheral C function.
1: Assigns the I/ O line to the Peripheral D function.
31 30 29 28 27 26 25 24
P31 P30 P29 P28 P27 P26 P25 P24
23 22 21 20 19 18 17 16
P23 P22 P21 P20 P19 P18 P17 P16
15 14 13 12 11 10 9 8
P15 P14 P13 P12 P11 P10 P9 P8
76543210
P7 P6 P5 P4 P3 P2 P1 P0
SAM4S Series [DATASHEET]
Atmel-11100K-ATARM-SAM4S-Datasheet_09-Jun-15
612
31.6.25 PIO Peripheral ABCD Select Register 2
Name: PIO_ABCDSR2
Access: Read/Write
This register can only be written if the WPEN bit is cleared in the PIO Write Protection Mode Register.
• P0–P31: Peripheral Select
If the same bit is set to 0 in PIO_ABCDSR1:
0: Assigns the I/ O line to the Peripheral A function .
1: Assigns the I/O line to the Peripheral C function.
If the same bit is set to 1 in PIO_ABCDSR1:
0: Assigns the I/ O line to the Peripheral B function .
1: Assigns the I/O line to the Peripheral D function.
31 30 29 28 27 26 25 24
P31 P30 P29 P28 P27 P26 P25 P24
23 22 21 20 19 18 17 16
P23 P22 P21 P20 P19 P18 P17 P16
15 14 13 12 11 10 9 8
P15 P14 P13 P12 P11 P10 P9 P8
76543210
P7 P6 P5 P4 P3 P2 P1 P0
613
SAM4S Series [DATASHEET]
Atmel-11100K-ATARM-SAM4S-Datasheet_09-Jun-15
31.6.26 PIO Input Filter Slow Clock Disable Register
Name: PIO_IFSCDR
Address: 0x400E0E80 (PIOA), 0x400E1080 (PIOB), 0x400E1280 (PIOC)
Access: Write-only
• P0–P31: Peripheral Clock Glitch Filtering Select
0: No effect.
1: The glitch filter is able to filter glitches with a duration < tperipheral clock/2.
31 30 29 28 27 26 25 24
P31 P30 P29 P28 P27 P26 P25 P24
23 22 21 20 19 18 17 16
P23 P22 P21 P20 P19 P18 P17 P16
15 14 13 12 11 10 9 8
P15 P14 P13 P12 P11 P10 P9 P8
76543210
P7 P6 P5 P4 P3 P2 P1 P0
SAM4S Series [DATASHEET]
Atmel-11100K-ATARM-SAM4S-Datasheet_09-Jun-15
614
31.6.27 PIO Input Filter Slow Clock Enable Register
Name: PIO_IFSCER
Address: 0x400E0E84 (PIOA), 0x400E1084 (PIOB), 0x400E1284 (PIOC)
Access: Write-only
• P0–P31: Slow Clock Debouncing Filtering Select
0: No effect.
1: The debouncing filter is able to filter pulses with a duration < tdiv_slck/2.
31 30 29 28 27 26 25 24
P31 P30 P29 P28 P27 P26 P25 P24
23 22 21 20 19 18 17 16
P23 P22 P21 P20 P19 P18 P17 P16
15 14 13 12 11 10 9 8
P15 P14 P13 P12 P11 P10 P9 P8
76543210
P7 P6 P5 P4 P3 P2 P1 P0
615
SAM4S Series [DATASHEET]
Atmel-11100K-ATARM-SAM4S-Datasheet_09-Jun-15
31.6.28 PIO Input Filter Slow Clock Status Register
Name: PIO_IFSCSR
Address: 0x400E0E88 (PIOA), 0x400E1088 (PIOB), 0x400E1288 (PIOC)
Access: Read-only
• P0–P31: Glitch or Debouncing Filter Selection Statu s
0: The glitch filter is able to filter glitches with a duration < tperipheral clock/2.
1: The debouncing filter is able to filter pulses with a duration < tdiv_slck/2.
31 30 29 28 27 26 25 24
P31 P30 P29 P28 P27 P26 P25 P24
23 22 21 20 19 18 17 16
P23 P22 P21 P20 P19 P18 P17 P16
15 14 13 12 11 10 9 8
P15 P14 P13 P12 P11 P10 P9 P8
76543210
P7 P6 P5 P4 P3 P2 P1 P0
SAM4S Series [DATASHEET]
Atmel-11100K-ATARM-SAM4S-Datasheet_09-Jun-15
616
31.6.29 PIO Slow Clock Divider Debouncing Register
Name: PIO_SCDR
Address: 0x400E0E8C (PIOA), 0x400E108C (PIOB), 0x400E128C (PIOC)
Access: Read/Write
• DIV: Slow Clock Divider Selection for Debouncing
tdiv_slck = ((DIV + 1) × 2) × tslck
31 30 29 28 27 26 25 24
––––––––
23 22 21 20 19 18 17 16
––––––––
15 14 13 12 11 10 9 8
–– DIV
76543210
DIV
617
SAM4S Series [DATASHEET]
Atmel-11100K-ATARM-SAM4S-Datasheet_09-Jun-15
31.6.30 PIO Pad Pull-Down Disable Register
Name: PIO_PPDDR
Address: 0x400E0E90 (PIOA), 0x400E1090 (PIOB), 0x400E1290 (PIOC)
Access: Write-only
This register can only be written if the WPEN bit is cleared in the PIO Write Protection Mode Register.
• P0–P31: Pull-Down Disable
0: No effect.
1: Disables the pull-down resistor on the I/O line.
31 30 29 28 27 26 25 24
P31 P30 P29 P28 P27 P26 P25 P24
23 22 21 20 19 18 17 16
P23 P22 P21 P20 P19 P18 P17 P16
15 14 13 12 11 10 9 8
P15 P14 P13 P12 P11 P10 P9 P8
76543210
P7 P6 P5 P4 P3 P2 P1 P0
SAM4S Series [DATASHEET]
Atmel-11100K-ATARM-SAM4S-Datasheet_09-Jun-15
618
31.6.31 PIO Pad Pull-Down Enable Register
Name: PIO_PPDER
Address: 0x400E0E94 (PIOA), 0x400E1094 (PIOB), 0x400E1294 (PIOC)
Access: Write-only
This register can only be written if the WPEN bit is cleared in the PIO Write Protection Mode Register.
• P0–P31: Pull-Down Enable
0: No effect.
1: Enables the pull-down resistor on the I/O line.
31 30 29 28 27 26 25 24
P31 P30 P29 P28 P27 P26 P25 P24
23 22 21 20 19 18 17 16
P23 P22 P21 P20 P19 P18 P17 P16
15 14 13 12 11 10 9 8
P15 P14 P13 P12 P11 P10 P9 P8
76543210
P7 P6 P5 P4 P3 P2 P1 P0
619
SAM4S Series [DATASHEET]
Atmel-11100K-ATARM-SAM4S-Datasheet_09-Jun-15
31.6.32 PIO Pad Pull-Down Status Register
Name: PIO_PPDSR
Address: 0x400E0E98 (PIOA), 0x400E1098 (PIOB), 0x400E1298 (PIOC)
Access: Read-only
• P0–P31: Pull-Down Status
0: Pull-down resistor is enabled on the I/O line.
1: Pull-down resistor is disabled on the I/O line.
31 30 29 28 27 26 25 24
P31 P30 P29 P28 P27 P26 P25 P24
23 22 21 20 19 18 17 16
P23 P22 P21 P20 P19 P18 P17 P16
15 14 13 12 11 10 9 8
P15 P14 P13 P12 P11 P10 P9 P8
76543210
P7 P6 P5 P4 P3 P2 P1 P0
SAM4S Series [DATASHEET]
Atmel-11100K-ATARM-SAM4S-Datasheet_09-Jun-15
620
31.6.33 PIO Output Write Enable Register
Name: PIO_OWER
Address: 0x400E0EA0 (PIOA), 0x400E10A0 (PIOB), 0x400E12A0 (PIOC)
Access: Write-only
This register can only be written if the WPEN bit is cleared in the PIO Write Protection Mode Register.
• P0–P31: Output Write Enable
0: No effect.
1: Enables writing PIO_ODSR for the I/O line.
31 30 29 28 27 26 25 24
P31 P30 P29 P28 P27 P26 P25 P24
23 22 21 20 19 18 17 16
P23 P22 P21 P20 P19 P18 P17 P16
15 14 13 12 11 10 9 8
P15 P14 P13 P12 P11 P10 P9 P8
76543210
P7 P6 P5 P4 P3 P2 P1 P0
621
SAM4S Series [DATASHEET]
Atmel-11100K-ATARM-SAM4S-Datasheet_09-Jun-15
31.6.34 PIO Output Write Disable Register
Name: PIO_OWDR
Address: 0x400E0EA4 (PIOA), 0x400E10A4 (PIOB), 0x400E12A4 (PIOC)
Access: Write-only
This register can only be written if the WPEN bit is cleared in the PIO Write Protection Mode Register.
• P0–P31: Output Write Disable
0: No effect.
1: Disables writing PIO_ODSR for the I/O line.
31 30 29 28 27 26 25 24
P31 P30 P29 P28 P27 P26 P25 P24
23 22 21 20 19 18 17 16
P23 P22 P21 P20 P19 P18 P17 P16
15 14 13 12 11 10 9 8
P15 P14 P13 P12 P11 P10 P9 P8
76543210
P7 P6 P5 P4 P3 P2 P1 P0
SAM4S Series [DATASHEET]
Atmel-11100K-ATARM-SAM4S-Datasheet_09-Jun-15
622
31.6.35 PIO Output Write Status Register
Name: PIO_OWSR
Address: 0x400E0EA8 (PIOA), 0x400E10A8 (PIOB), 0x400E12A8 (PIOC)
Access: Read-only
• P0–P31 : Ou t pu t Write Stat u s
0: Writing PIO_ODSR does not affect the I/O line.
1: Writing PIO_ODSR affects the I/O line.
31 30 29 28 27 26 25 24
P31 P30 P29 P28 P27 P26 P25 P24
23 22 21 20 19 18 17 16
P23 P22 P21 P20 P19 P18 P17 P16
15 14 13 12 11 10 9 8
P15 P14 P13 P12 P11 P10 P9 P8
76543210
P7 P6 P5 P4 P3 P2 P1 P0
623
SAM4S Series [DATASHEET]
Atmel-11100K-ATARM-SAM4S-Datasheet_09-Jun-15
31.6.36 PIO Additional Interrupt Modes Enable Register
Name: PIO_AIMER
Address: 0x400E0EB0 (PIOA), 0x400E10B0 (PIOB), 0x400E12B0 (PIOC)
Access: Write-only
• P0–P31: Additional Interrupt Modes Enable
0: No effect.
1: The interrupt source is the event described in PIO_ELSR and PIO_FRLHSR.
31 30 29 28 27 26 25 24
P31 P30 P29 P28 P27 P26 P25 P24
23 22 21 20 19 18 17 16
P23 P22 P21 P20 P19 P18 P17 P16
15 14 13 12 11 10 9 8
P15 P14 P13 P12 P11 P10 P9 P8
76543210
P7 P6 P5 P4 P3 P2 P1 P0
SAM4S Series [DATASHEET]
Atmel-11100K-ATARM-SAM4S-Datasheet_09-Jun-15
624
31.6.37 PIO Additional Interrupt Modes Disable Register
Name: PIO_AIMDR
Address: 0x400E0EB4 (PIOA), 0x400E10B4 (PIOB), 0x400E12B4 (PIOC)
Access: Write-only
• P0–P31: Additional Interrupt Modes Disable
0: No effect.
1: The interrupt mode is set to the default interrupt mode (both-edge detection).
31 30 29 28 27 26 25 24
P31 P30 P29 P28 P27 P26 P25 P24
23 22 21 20 19 18 17 16
P23 P22 P21 P20 P19 P18 P17 P16
15 14 13 12 11 10 9 8
P15 P14 P13 P12 P11 P10 P9 P8
76543210
P7 P6 P5 P4 P3 P2 P1 P0
625
SAM4S Series [DATASHEET]
Atmel-11100K-ATARM-SAM4S-Datasheet_09-Jun-15
31.6.38 PIO Additional Interrupt Modes Mask Register
Name: PIO_AIMMR
Address: 0x400E0EB8 (PIOA), 0x400E10B8 (PIOB), 0x400E12B8 (PIOC)
Access: Read-only
• P0–P31: IO Line Index
Selects the IO event type triggering an interrupt.
0: The interrupt source is a both-edge detection event.
1: The interrupt source is described by the registers PIO_ELSR and PIO_FRLHSR.
31 30 29 28 27 26 25 24
P31 P30 P29 P28 P27 P26 P25 P24
23 22 21 20 19 18 17 16
P23 P22 P21 P20 P19 P18 P17 P16
15 14 13 12 11 10 9 8
P15 P14 P13 P12 P11 P10 P9 P8
76543210
P7 P6 P5 P4 P3 P2 P1 P0
SAM4S Series [DATASHEET]
Atmel-11100K-ATARM-SAM4S-Datasheet_09-Jun-15
626
31.6.39 PIO Edge Select Register
Name: PIO_ESR
Address: 0x400E0EC0 (PIOA), 0x400E10C0 (PIOB), 0x400E12C0 (PIOC)
Access: Write-only
• P0–P31: Edge Interrupt Selection
0: No effect.
1: The interrupt source is an edge-detection event.
31 30 29 28 27 26 25 24
P31 P30 P29 P28 P27 P26 P25 P24
23 22 21 20 19 18 17 16
P23 P22 P21 P20 P19 P18 P17 P16
15 14 13 12 11 10 9 8
P15 P14 P13 P12 P11 P10 P9 P8
76543210
P7 P6 P5 P4 P3 P2 P1 P0
627
SAM4S Series [DATASHEET]
Atmel-11100K-ATARM-SAM4S-Datasheet_09-Jun-15
31.6.40 PIO Level Select Register
Name: PIO_LSR
Address: 0x400E0EC4 (PIOA), 0x400E10C4 (PIOB), 0x400E12C4 (PIOC)
Access: Write-only
• P0–P31: Level Interrupt Selection
0: No effect.
1: The interrupt source is a level-detection event.
31 30 29 28 27 26 25 24
P31 P30 P29 P28 P27 P26 P25 P24
23 22 21 20 19 18 17 16
P23 P22 P21 P20 P19 P18 P17 P16
15 14 13 12 11 10 9 8
P15 P14 P13 P12 P11 P10 P9 P8
76543210
P7 P6 P5 P4 P3 P2 P1 P0
SAM4S Series [DATASHEET]
Atmel-11100K-ATARM-SAM4S-Datasheet_09-Jun-15
628
31.6.41 PIO Edge/Level Status Regist er
Name: PIO_ELSR
Address: 0x400E0EC8 (PIOA), 0x400E10C8 (PIOB), 0x400E12C8 (PIOC)
Access: Read-only
• P0–P31: Edge/Level Interrupt Source Selection
0: The interrupt source is an edge-detection event.
1: The interrupt source is a level-detection event.
31 30 29 28 27 26 25 24
P31 P30 P29 P28 P27 P26 P25 P24
23 22 21 20 19 18 17 16
P23 P22 P21 P20 P19 P18 P17 P16
15 14 13 12 11 10 9 8
P15 P14 P13 P12 P11 P10 P9 P8
76543210
P7 P6 P5 P4 P3 P2 P1 P0
629
SAM4S Series [DATASHEET]
Atmel-11100K-ATARM-SAM4S-Datasheet_09-Jun-15
31.6.42 PIO Falling Edge /Low-Level Select Register
Name: PIO_FELLSR
Address: 0x400E0ED0 (PIOA), 0x400E10D0 (PIOB), 0x400E12D0 (PIOC)
Access: Write-only
• P0–P31: Falling Edge/Low-Level Interrupt Selection
0: No effect.
1: The interrupt source is set to a falling edge detection or low-leve l detection event, depending on PIO_ELSR.
31 30 29 28 27 26 25 24
P31 P30 P29 P28 P27 P26 P25 P24
23 22 21 20 19 18 17 16
P23 P22 P21 P20 P19 P18 P17 P16
15 14 13 12 11 10 9 8
P15 P14 P13 P12 P11 P10 P9 P8
76543210
P7 P6 P5 P4 P3 P2 P1 P0
SAM4S Series [DATASHEET]
Atmel-11100K-ATARM-SAM4S-Datasheet_09-Jun-15
630
31.6.43 PIO Rising Edge/High-Level Select Register
Name: PIO_REHLSR
Address: 0x400E0ED4 (PIOA), 0x400E10D4 (PIOB), 0x400E12D4 (PIOC)
Access: Write-only
• P0–P31: Rising Edge/High-Level Interrupt Selection
0: No effect.
1: The interrupt source is set to a rising edge detection or high-level detection event, dependin g on PIO_ELSR.
31 30 29 28 27 26 25 24
P31 P30 P29 P28 P27 P26 P25 P24
23 22 21 20 19 18 17 16
P23 P22 P21 P20 P19 P18 P17 P16
15 14 13 12 11 10 9 8
P15 P14 P13 P12 P11 P10 P9 P8
76543210
P7 P6 P5 P4 P3 P2 P1 P0
631
SAM4S Series [DATASHEET]
Atmel-11100K-ATARM-SAM4S-Datasheet_09-Jun-15
31.6.44 PIO Fall/Rise - Low/High Status Register
Name: PIO_FRLHSR
Address: 0x400E0ED8 (PIOA), 0x400E10D8 (PIOB), 0x400E12D8 (PIOC)
Access: Read-only
• P0–P31: Edge/Level Interrupt Source Selection
0: The interrupt source is a falling edge detection (if PIO_ELSR = 0) or low-level detection event (if PIO_ELSR = 1).
1: The interrupt source is a rising edge detection (if PIO_ELSR = 0) or high-level detection event (if PIO_ELSR = 1).
31 30 29 28 27 26 25 24
P31 P30 P29 P28 P27 P26 P25 P24
23 22 21 20 19 18 17 16
P23 P22 P21 P20 P19 P18 P17 P16
15 14 13 12 11 10 9 8
P15 P14 P13 P12 P11 P10 P9 P8
76543210
P7 P6 P5 P4 P3 P2 P1 P0
SAM4S Series [DATASHEET]
Atmel-11100K-ATARM-SAM4S-Datasheet_09-Jun-15
632
31.6.45 PIO Lock Status Register
Name: PIO_LOCKSR
Address: 0x400E0EE0 (PIOA), 0x400E10E0 (PIOB), 0x400E12E0 (PIOC)
Access: Read-only
• P0–P31: Lock Status
0: The I/O line is not locked.
1: The I/O line is locked.
31 30 29 28 27 26 25 24
P31 P30 P29 P28 P27 P26 P25 P24
23 22 21 20 19 18 17 16
P23 P22 P21 P20 P19 P18 P17 P16
15 14 13 12 11 10 9 8
P15 P14 P13 P12 P11 P10 P9 P8
76543210
P7 P6 P5 P4 P3 P2 P1 P0
633
SAM4S Series [DATASHEET]
Atmel-11100K-ATARM-SAM4S-Datasheet_09-Jun-15
31.6.46 PIO Write Protection Mode Regis ter
Name: PIO_WPMR
Address: 0x400E0EE4 (PIOA), 0x400E10E4 (PIOB), 0x400E12E4 (PIOC)
Access: Read/Write
• WPEN: Write Protec ti on Ena b le
0: Disables the write protection if WPKEY corresponds to 0x50494F (“PIO” in ASCII).
1: Enables the write protection if WPKEY corresponds to 0x50494F (“PIO” in ASCII).
See Section 31.5.15 “Register Write Protection” for the list of registers that can be protected.
• WPKEY: Write Protection Key
31 30 29 28 27 26 25 24
WPKEY
23 22 21 20 19 18 17 16
WPKEY
15 14 13 12 11 10 9 8
WPKEY
76543210
–––––––WPEN
Value Name Description
0x50494F PASSWD Writing any other value in this field aborts the write operation of the WPEN bit. Always reads as
0.
SAM4S Series [DATASHEET]
Atmel-11100K-ATARM-SAM4S-Datasheet_09-Jun-15
634
31.6.47 PIO Write Protection Status Register
Name: PIO_WPSR
Address: 0x400E0EE8 (PIOA), 0x400E10E8 (PIOB), 0x400E12E8 (PIOC)
Access: Read-only
• WPVS: Write Protection Violation Status
0: No write protec tion v iola tio n ha s occ u rred since the last read of the PIO_WPSR.
1: A write protection violation has occurred since the last read of the PIO_WPSR. If this violation is an unauthorized
attempt to write a protected register, the associated violation is reported into field WPVSRC.
• WPVSRC: Write Protection Violation Source
When WPVS = 1, WPVSRC indicates the register address offset at which a write access has been attempted.
31 30 29 28 27 26 25 24
––––––––
23 22 21 20 19 18 17 16
WPVSRC
15 14 13 12 11 10 9 8
WPVSRC
76543210
–––––––WPVS
635
SAM4S Series [DATASHEET]
Atmel-11100K-ATARM-SAM4S-Datasheet_09-Jun-15
31.6.48 PIO Schmitt Trigger Register
Name: PIO_SCHMITT
Address: 0x400E0F00 (PIOA), 0x400E1100 (PIOB), 0x400E1300 (PIOC)
Access: Read/Write
• SCHMITTx [x=0..31]: Schmitt Trigger Control
0: Schmitt trigger is enabled.
1: Schmitt trigger is disabled.
31 30 29 28 27 26 25 24
SCHMITT31 SCHMITT30 SCHMITT29 SCHMITT28 SCHMITT27 SCHMITT26 SCHMITT25 SCHMITT24
23 22 21 20 19 18 17 16
SCHMITT23 SCHMITT22 SCHMITT21 SCHMITT20 SCHMITT19 SCHMITT18 SCHMITT17 SCHMITT16
15 14 13 12 11 10 9 8
SCHMITT15 SCHMITT14 SCHMITT13 SCHMITT12 SCHMITT11 SCHMITT10 SCHMITT9 SCHMITT8
76543210
SCHMITT7 SCHMITT6 SCHMITT5 SCHMITT4 SCHMITT3 SCHMITT2 SCHMITT1 SCHMITT0
SAM4S Series [DATASHEET]
Atmel-11100K-ATARM-SAM4S-Datasheet_09-Jun-15
636
31.6.49 PIO Parallel Capture Mode Register
Name: PIO_PCMR
Address: 0x400E0F50 (PIOA), 0x400E1150 (PIOB), 0x400E1350 (PIOC)
Access: Read/Write
This register can only be written if the WPEN bit is cleared in the PIO Write Protection Mode Register.
• PCEN: Parallel Capture Mode Enable
0: The parallel capture mode is disabled.
1: The parallel capture mode is enabled.
• DSIZE: Parallel Capture Mode Data Size
• ALWYS: Parallel Capture Mode Always Sampling
0: The parallel capture mode samples the data when both data enables are active.
1: The parallel capture mode samples the data whatever the data enables are.
• HALFS: Parallel Capture Mode Half Sampling
Independently from the ALWYS bit:
0: The parallel capture mode samples all the data.
1: The parallel capture mode samples the data only every other time.
• FRSTS: Parallel Capture Mode First Sample
This bit is useful only if the HALFS bit is set to 1. If data are numbered in the order that they are received with an index from
0 to n:
0: Only data with an even index are sampled.
1: Only data with an odd index are sampled.
31 30 29 28 27 26 25 24
––––––––
23 22 21 20 19 18 17 16
––––––––
15 14 13 12 11 10 9 8
––––FRSTSHALFSALWYS–
76543210
–– DSIZE –––PCEN
Value Name Description
0 BYTE The reception data in the PIO_PCRHR is a byte (8-bit)
1 HALF-WORD The receptio n data in the PIO_PCRHR is a half-word (16-bit)
2 WORD The reception data in the PIO_PCRHR is a word (32-bit)
3– Reserved
637
SAM4S Series [DATASHEET]
Atmel-11100K-ATARM-SAM4S-Datasheet_09-Jun-15
31.6.50 PIO Parallel Capture Interrupt Enable Register
Name: PIO_PCIER
Address: 0x400E0F54 (PIOA), 0x400E1154 (PIOB), 0x400E1354 (PIOC)
Access: Write-only
The following configuration values are valid for all listed bit names of this register:
0: No effect
1: Enables the corresponding interrupt
• DRDY: Parallel Capture Mode Data Ready Interrupt Enable
• OVRE: Parallel Capture Mode Overrun Error Interrupt Enable
• ENDRX: End of Reception Transfer Interrupt Enable
• RXBUFF: Reception Buffer Full Interrupt Enable
31 30 29 28 27 26 25 24
––––––––
23 22 21 20 19 18 17 16
––––––––
15 14 13 12 11 10 9 8
––––––––
76543210
––––RXBUFFENDRX OVRE DRDY
SAM4S Series [DATASHEET]
Atmel-11100K-ATARM-SAM4S-Datasheet_09-Jun-15
638
31.6.51 PIO Parallel Capture Interrupt Disable Register
Name: PIO_PCIDR
Address: 0x400E0F58 (PIOA), 0x400E1158 (PIOB), 0x400E1358 (PIOC)
Access: Write-only
The following configuration values are valid for all listed bit names of this register:
0: No effect
1: Disables the corresponding interrupt
• DRDY: Parallel Capture Mode Data Ready Interrupt Disable
• OVRE: Parallel Capture Mode Overrun Error Interrupt Disable
• ENDRX: End of Reception Transfer Interrupt Disable
• RXBUFF: Reception Buffer Full Interrupt Disable
31 30 29 28 27 26 25 24
––––––––
23 22 21 20 19 18 17 16
––––––––
15 14 13 12 11 10 9 8
––––––––
76543210
––––RXBUFFENDRX OVRE DRDY
639
SAM4S Series [DATASHEET]
Atmel-11100K-ATARM-SAM4S-Datasheet_09-Jun-15
31.6.52 PIO Parallel Capture Interrupt Mask Regi ster
Name: PIO_PCIMR
Address: 0x400E0F5C (PIOA), 0x400E115C (PIOB), 0x400E135C (PIOC)
Access: Read-only
The following configuration values are valid for all listed bit names of this register:
0: Corresponding interrupt is not enabled.
1: Corresponding interrupt is enabled.
• DRDY: Parallel Capture Mode Data Ready Interrupt Mask
• OVRE: Parallel Capture Mode Overrun Error Interrupt Mask
• ENDRX: End of Reception Transfer Interrupt Mask
• RXBUFF: Reception Buffer Full Interrupt Mask
31 30 29 28 27 26 25 24
––––––––
23 22 21 20 19 18 17 16
––––––––
15 14 13 12 11 10 9 8
––––––––
76543210
––––RXBUFFENDRX OVRE DRDY
SAM4S Series [DATASHEET]
Atmel-11100K-ATARM-SAM4S-Datasheet_09-Jun-15
640
31.6.53 PIO Parallel Capture Interrupt Status Register
Name: PIO_PCISR
Address: 0x400E0F60 (PIOA), 0x400E1160 (PIOB), 0x400E1360 (PIOC)
Access: Read-only
• DRDY: Parallel Capture Mode Data Ready
0: No new data is ready to be read since the last read of PIO_PCRHR.
1: A new data is ready to be read since the last read of PIO_PCRHR.
The DRDY flag is automatically reset when PIO_PCRHR is read or when the parallel capture mode is disabled.
• OVRE: Parallel Capture Mode Overrun Error
0: No overru n er ro r occurred since the last read of this register.
1: At least one overrun error occurred since the last read of this register.
The OVRE flag is automatically re set when this register is read or when the parallel capture mode is disabled.
31 30 29 28 27 26 25 24
––––––––
23 22 21 20 19 18 17 16
––––––––
15 14 13 12 11 10 9 8
––––––––
76543210
––––RXBUFFENDRX OVRE DRDY
• ENDRX: End of Reception Transfer
0: The End of Transfer signal from the reception PDC channel is inactive.
1: The End of Transfer signal from the reception PDC channel is active.
• RXBUFF: Reception Buffer Full
0: The signal Buffer Full from the reception PDC channel is inactive.
1: The signal Buffer Full from the reception PDC channel is active.
641
SAM4S Series [DATASHEET]
Atmel-11100K-ATARM-SAM4S-Datasheet_09-Jun-15
31.6.54 PIO Parallel Capture Reception Holding Register
Name: PIO_PCRHR
Address: 0x400E0F64 (PIOA), 0x400E1164 (PIOB), 0x400E1364 (PIOC)
Access: Read-only
• RDATA: Parallel Capture Mode Reception Data
If DSIZE = 0 in PIO_PCMR, only the 8 LSBs of RDATA are useful.
If DSIZE = 1 in PIO_PCMR, only the 16 LSBs of RDATA are useful.
31 30 29 28 27 26 25 24
RDATA
23 22 21 20 19 18 17 16
RDATA
15 14 13 12 11 10 9 8
RDATA
76543210
RDATA
SAM4S Series [DATASHEET]
Atmel-11100K-ATARM-SAM4S-Datasheet_09-Jun-15
642
32. Synchronous Serial Controller (SSC)
32.1 Description
The Synchronous Serial Controller (SSC) prov ides a synchronous communication link with external devices. It
supports many serial synchronous communication prot ocols generally used in audio and telecom applications
such as I2S, Short Frame Sync, Long Frame Sync, etc.
The SSC contains an independent receiver and transmitter and a common clock divider. The receiver and the
transmitter ea ch interface with thr ee signals: the TD/RD signal for data, the TK /RK signal for the clock and the
TF/RF signal for the Fra me Sync. The transfers can be program med to start automatically or on different events
detected on the Frame Sync signal.
The SSC high-level of program mability and its two dedicated PDC channels of up to 32 bits pe rmit a continuous
high bit rate data transfer without processor intervention.
Featuring connection to two PDC channels, the SSC permits interfacing with low processor overhead to the
following:
Codecs in master or slave mode
DAC through dedicated serial interface, particularly I2S
Magnetic card reader
643
SAM4S Series [DATASHEET]
Atmel-11100K-ATARM-SAM4S-Datasheet_09-Jun-15
32.2 Embedded Characteristics
Provides Serial Synchronous Communication Links Used in Audio and Telecom Applications
Contains an Independent Receiver and Transmitter and a Common Clock Divider
Interfaced with Two PDC Channels (DMA Access) to Reduce Processor Overhead
Offers a Configurable Frame Sync and Data Length
Receiver and Transmitter Can be Programmed to Start Automatically or on Detection of Different Events on
the Frame Sync Signal
Receiver and Transmitter Include a Data Signal, a Clock Signal and a Frame Synchronization Signal
32.3 Block Diagram
Figure 32-1. Block Diagram
32.4 Application Block Diagram
Figure 32-2. Application Block Diagram
SSC Interface PIO
PDC
Peripheral Bridge
Peripheral Clock
Peripheral
Bus TF
TK
TD
RF
RK
RD
System
Bus
Interrupt Control
SSC Interrupt
PMC
Bus Clock
Interrupt
Management
Power
Management
Test
Management
SSC
Serial AUDIO
OS or RTOS Driver
Codec Frame
Management Line Interface
Time Slot
Management
SAM4S Series [DATASHEET]
Atmel-11100K-ATARM-SAM4S-Datasheet_09-Jun-15
644
32.5 SSC Application Examples
The SSC can support several serial communication modes used in audio or high speed serial links. Some
standard applications are shown in the following figures. All serial link applications supported by the SSC are not
listed here.
Figure 32-3. Audio Application Block Diagram
Figure 32-4. Codec Application Block Diagram
SSC
RK
RF
RD
TD
TF
TK
Clock SCK
Word Select WS
Data SD
I2S
RECEIVER
Clock SCK
Word Select WS
Data SD
Right Channel
Left Channel
MSB MSB
LSB
SSC
RK
RF
RD
TD
TF
TK
Serial Data Clock (SCLK)
Frame sync (FSYNC)
Serial Data Out
Serial Data In
CODEC
Serial Data Clock (SCLK)
Frame sync (FSYNC)
Serial Data Out
Serial Data In
First Time Slot
Dstart Dend
645
SAM4S Series [DATASHEET]
Atmel-11100K-ATARM-SAM4S-Datasheet_09-Jun-15
Figure 32-5. Time Slot Application Block Diagram
32.6 Pin Name List
32.7 Product Dependencies
32.7.1 I/O Lines
The pins used for interfacing the compliant extern al devices may be multiplexed with PIO lines.
Before using the SSC receiver, the PIO controller must be configured to dedicate the SSC receiver I/O lines to the
SSC peripheral mode.
SSC
RK
RF
RD
TD
TF
TK SCLK
FSYNC
Data Out
Data In
CODEC
First
Time Slot
Serial Data Clock (SCLK)
Frame sync (FSYNC)
Serial Data Out
Serial Data in
CODEC
Second
Time Slot
First Time Slot Second Time Slot
Dstart Dend
Table 32-1. I/O Lines Description
Pin Name Pi n Description Type
RF Receiver Frame Synchro Input/Output
RK Receiver Clock Input/Output
RD Receiver Data Input
TF Transmitter Frame Synchro Input/Output
TK Transmitter Clock Input/Output
TD Transmitter Data Output
SAM4S Series [DATASHEET]
Atmel-11100K-ATARM-SAM4S-Datasheet_09-Jun-15
646
Before using the SSC transmitter, the PIO controller must be configured to dedicate the SSC transmitter I/O lines
to the SSC peripheral mode.
32.7.2 Power Management
The SSC is not continuously clocked. The SSC interface may be clocked through the Power Management
Controller (PMC), therefore the programmer must first configure the PMC to enable the SSC clock.
32.7.3 Interrupt
The SSC interface has an interrupt line connected to the interrupt controller. Handling interrupts requires
programming the interrupt controller before configuring the SSC.
All SSC interrupts can be en abled/disabled configuring the SSC Interrupt Mask Regist er. Each pending and
unmasked SSC interrupt will assert the SSC interrupt line. The SSC interrupt service routine can get the interrupt
origin by reading the SSC Interrupt Status Register.
Table 32-2. I/O Lines
Instance Signal I/O Line Periphera l
SSC RD PA18 A
SSC RF PA20 A
SSC RK PA19 A
SSC TD PA17 A
SSC TF PA15 A
SSC TK PA16 A
Table 32-3. Peripheral IDs
Instance ID
SSC 22
647
SAM4S Series [DATASHEET]
Atmel-11100K-ATARM-SAM4S-Datasheet_09-Jun-15
32.8 Functional Description
This chapter contains the func tional description of the following: SSC Functional Block, Clock Management, Data
format, Start, Transmitter, Receiver and Frame Sync.
The receiver and transmitter operate separately. However, they can work synchronously by programming the
receiver to use the transm it clock and /or to start a data transfer when transmission starts. Alternatively, this can be
done by programming the transmitter to use the receive clock and/or to start a data transfer when reception starts.
The transmitter and the rece iver can be pr ogrammed to operate with the clock signals pro vided on eithe r the TK or
RK pins. This allows the SSC to support many slave-mode data transfers. The maximum clock speed allowed on
the TK and RK pins is the peripheral clock divided by 2.
Figure 32-6. SSC Functional Block Diagram
User
Interface
APB
Peripheral
Clock
Receive Clock
Controller
TX Clock
RK Input
Clock Output
Controller
Frame Sync
Controller
Transmit Clock
Controller
Transmit Shift Register
Start
Selector
Start
Selector
Transmit Sync
Holding Register
Transmit Holding
Register
RX clock
TX clock
TK Input
RD
RF
RK
Clock Output
Controller
Frame Sync
Controller
Receive Shift Register
Receive Sync
Holding Register
Receive Holding
Register
TD
TF
TK
RX Clock
Receiver
Transmitter
Data
Controller
TXEN
Data
Controller
RF
TF
RX Start
RXEN
RC0R
TX Start
Interrupt Control
To Interrupt Controller
Clock
Divider
RX Start
TX Start
SAM4S Series [DATASHEET]
Atmel-11100K-ATARM-SAM4S-Datasheet_09-Jun-15
648
32.8.1 Clock Management
The transmitter clock can be generated by:
an external clock received on the TK I/O pad
the receiver clock
the internal clock divider
The receiver clock can be generated by:
an external clock received on the RK I/O pad
the transmitter clock
the internal clock divider
Furthermore, the transmitter block can generate an external clock on the TK I/O pad, and the receiver block can
generate an external clock on the RK I/O pad.
This allows the SSC to support many Master and Slave Mode data transfers.
32.8.1.1 Clock Divider
Figure 32-7. Divided Clock Block Diagram
The peripheral clock divider is determined by the 12-bit field DIV counter and comparator (so its maximal value is
4095) in the Clock Mode Register (SSC_ CMR), allowing a peripheral clock division by up to 8190. The Divided
Clock is provided to both the Receiver and Transmitter. When this field is programmed to 0, the Clock Divider is
not used and remains inactive.
When DIV is set to a value equal to or greater than 1, the Divided Clock has a frequency of perip heral clock divided
by 2 times DIV. Each level of the Divided Clock has a duration of the peripheral clock multiplied by DIV. This
ensures a 50% duty cycle for the Divided Clock regardless of whether the DIV value is even or odd.
Figure 32-8. Divided Clock Generation
Peripheral Clock
Divided Clock
Clock Divider
/ 2 12-bit Counter
SSC_CMR
Peripheral Clock
Divided Clock
DIV = 1
Peripheral Clock
Divided Clock
DIV = 3
Divided Clock Frequency = f
peripheral clock
/2
Divided Clock Frequency = f
peripheral clock
/6
649
SAM4S Series [DATASHEET]
Atmel-11100K-ATARM-SAM4S-Datasheet_09-Jun-15
32.8.1.2 Transmitter Clock Management
The transmitter cloc k is generated from the receiver clock or the divide r cloc k o r an ex tern al cloc k sc anned on t he
TK I/O pad. The transmitter clock is selected by the CKS field in the Transmit Clock Mode Register (SSC_TCMR).
Transmit Clock can be inverted independently by the CKI bits in the SSC_TCMR.
The transmitter can also drive the TK I/O pad cont inuously or be limited to the actual data transfer. The clock
output is configured by the SSC_TCMR. The Transmit Clock Inversion (CKI) bits h ave no effect on the clock
outputs. Program ming the SSC_TCMR to select T K pin (CKS field) and at the same time Continuous Transmit
Clock (CKO field) can lead to unpredictable results.
Figure 32-9. Transmitter Clock Management
TK (pin)
Receiver
Clock
Divider
Clock
MUX Tri_state
Controller Clock
Output
CKO Data Transfer
CKS INV
MUX
Tri_state
Controller
Transmitter
Clock
CKI CKG
SAM4S Series [DATASHEET]
Atmel-11100K-ATARM-SAM4S-Datasheet_09-Jun-15
650
32.8.1.3 Receiver Clock Management
The receiver clock is generated from the transmitter clock or the divider clock or an external clock scanned on the
RK I/O pad. The Receive Clock is selected by the CKS field in SSC_RCMR (Receive Clock Mode Register).
Receive Clocks can be inverted independently by the CKI bits in SSC_RCMR.
The receiver can also drive the RK I/O pad continuously or be limited to the actual data transfer. The clock output
is configured by the SSC_RCMR. The Receive Clock Inversion (CKI) bits have no effect on the clock outputs.
Programming the SSC_RCMR to select RK pin (CKS field) and at the same time Continuous Receive Clock (CKO
field) can lead to unpredictable results.
Figure 32-10. Receiver Clock Management
32.8.1.4 Serial Clock Ratio Considerations
The Transmitter and the Receiver can be programmed to operate with the clock signals provided on either the TK
or RK pins. This allows the SSC to support many slave-mode data transfers. In this case, the maximum clock
speed allowed on the RK pin is:
Peripheral clock divided by 2 if Receiver Frame Synchro is input
Peripheral clock divided by 3 if Receiver Frame Synchro is output
In addition, the maximum clock speed allowed on the TK pin is:
Peripheral clock divided by 6 if Transmit Frame Synchro is input
Peripheral clock divided by 2 if Transmit Frame Synchro is output
32.8.2 Transmitter Operations
A transmitted frame is triggered by a start event and can be followed by synchronization data before data
transmission.
The start event is configured by setting the SSC_TCMR. See Section 32.8.4 “Start” on page 652.
The frame synchronization is configured setting t he Transmit Frame Mode Register (SSC_TFMR). See Section
32.8.5 “Frame Sync” on page 654.
To transmit data, the transmitter uses a shift register clocked by the transmitter clock signal and the start mode
selected in the SSC_TCMR. Data is written by the application to the SSC_THR then transferred to the shift register
according to the data format se lect ed .
RK (pin)
Receive
r
Clock
Divider
Clock
MUX Tri_state
Controller Clock
Output
CKO Data Transfer
CKS INV
MUX
Tri_state
Controller
Transmitter
Clock
CKI CKG
651
SAM4S Series [DATASHEET]
Atmel-11100K-ATARM-SAM4S-Datasheet_09-Jun-15
When both the SSC_THR and the transmit shift register are empty, the status flag TXEMPTY is set in the
SSC_SR. When the Transm it Holding regis ter is transfer red in the transm it shift registe r, the status flag TX RDY is
set in the SSC_SR and additional data can be loaded in the holding register.
Figure 32-11. Transmitter Block Diagram
32.8.3 Receiver Operations
A received frame is triggered by a start event and can be followed by synchronization data before data
transmission.
The start event is configured setting the Receive Clock Mode Register (SSC_RCMR). See Section 32.8.4 “Start”
on page 652.
The frame synchronization is configured setting th e Receive Frame Mode Register (SSC_RFMR). See Section
32.8.5 “Frame Sync” on page 654.
The receiver uses a shift register clocked by the receiver clock signal and the start mode selected in the
SSC_RCMR. The data is transferred from the shift register depending on the data format selected.
When the receiver shift register is full, the SSC transfers this data in the holding register, the status flag RXRDY is
set in the SSC_SR and the data can be read in the receiver hold ing re gister. If an other tr ansfer occur s before r ead
of the Receive Holding Register (SSC_RHR), the status flag OVERUN is set in the SSC_SR and the receiver shift
register is transferred in the SSC_RHR.
Transmit Shift Register
TD
SSC_TFMR.FSLENSSC_TFMR.DATLEN
SSC_TCMR.STTDLY
SSC_TFMR.FSDEN
SSC_TFMR.DATNB
SSC_TFMR.DATDEF
SSC_TFMR.MSBF
SSC_TCMR.STTDLY != 0
SSC_TFMR.FSDEN 10
TX Controller
SSC_TCMR.START
RF
Start
Selector
TXEN
RX Start
TXEN
RF
Start
Selector
RXEN
RC0R
TX Start TX Start
Transmitter Clock
TX Controller counter reached STTDLY
SSC_RCMR.START
SSC_THR SSC_TSHR
SSC_CRTXEN
SSC_SRTXEN
SSC_CRTXDIS
SAM4S Series [DATASHEET]
Atmel-11100K-ATARM-SAM4S-Datasheet_09-Jun-15
652
Figure 32-12. Receiver Block Diagram
32.8.4 Start
The transmitter and receiver can both be programmed to start their operations when an event occurs, respectively
in the Transmit Start Selection (START) field of SSC_TCMR and in the Re ceive Start Selection (START) field of
SSC_RCMR.
Under the following conditions the start event is independently programmable:
Continuous. In this case, the transmission st art s as soon as a word is written in SSC_THR and the r eception
starts as soon as the Receiver is enabled.
Synchronously with the transmitter/receiver
On detection of a falling/rising edge on TF/RF
On detection of a low level/high level on TF/RF
On detection of a level change or an edge on TF/RF
A start can be programmed in the same manner on either side of the Transmit/Receive Clock Register
(SSC_RCMR/SSC_TCMR). Thus, the start could be on TF (Transmit) or RF (Receive).
Moreover, the Receiver can start when data is detected in the bit stream with the Compare Functions.
Detection on TF/RF input/output is done by the field FSOS of the Transmit/Receive Frame Mode Register
(SSC_TFMR/SSC_RFMR).
SSC_RFMR.MSBF
SSC_RFMR.DATNB
SSC_TCMR.START SSC_RCMR.START
SSC_RHRSSC_RSHR
SSC_RFMR.FSLEN SSC_RFMR.DATLEN
RX Controller counter reached STTDLY
RX Controller
RD
SSC_CR.RXEN
SSC_CR.RXDIS
SSC_SR.RXEN
Receiver Clock
RF
TXEN
RX Start
RF
RXEN
RC0R
SSC_RCMR.STTDLY != 0
Receive Shift Register
Start
Selector Start
Selector
RX Start
load load
653
SAM4S Series [DATASHEET]
Atmel-11100K-ATARM-SAM4S-Datasheet_09-Jun-15
Figure 32-13. Transmit Start Mode
Figure 32-14. Receive Pulse/Edge Start Modes
X
TK
TF
(Input)
TD
(Output)
TD
(Output)
TD
(Output)
TD
(Output)
TD
(Output)
TD
(Output)
X BO B1
XBO B1
BO B1
BO B1
BO B1BO B1
BO B1B1
BO
X
X
X
STTDLY
STTDLY
STTDLY
STTDLY
STTDLY
STTDLY
Start = Falling Edge on TF
Start = Rising Edge on TF
Start = Low Level on TF
Start = High Level on TF
Start = Any Edge on TF
Start = Level Change on TF
X
RK
RF
(Input)
RD
(Input) X BO B1
XBO B1
BO B1
BO B1
BO B1BO B1
BO B1B1
BO
X
X
X
STTDLY
STTDLY
STTDLY
STTDLY
STTDLY
STTDLY
Start = Falling Edge on RF
Start = Rising Edge on RF
Start = Low Level on RF
Start = High Level on RF
Start = Any Edge on RF
Start = Level Change on RF
RD
(Input)
RD
(Input)
RD
(Input)
RD
(Input)
RD
(Input)
SAM4S Series [DATASHEET]
Atmel-11100K-ATARM-SAM4S-Datasheet_09-Jun-15
654
32.8.5 Frame Sync
The Transmitter and Receiver Frame Sync pins, TF and RF, can be programmed to generate different kinds of
frame synchronization signals. The Frame Sync Output Selection (FSOS) field in the Receive Frame Mode
Register (SSC_RFMR) and in the Transmit Frame Mode Register (SSC_TFMR) are used to select the required
waveform.
Programmable low or high levels during data transfer are supported.
Programmable high levels before the start of data transfers or toggling are also supported.
If a pulse waveform is selected, the Frame Sync Length (F SLEN) field in SSC_RFMR and SSC_TFMR programs
the length of the pulse, from 1 bit time up to 256 bit times.
The periodicity of the Receive and Transmit Frame Sync pulse output can be programmed through the Period
Divider Selection (PERIOD) field in SSC_RCMR and SSC_TCMR.
32.8.5.1 Frame Sync Data
Frame Sync Data transmits or receives a specific tag during the Frame Sync signal.
During the Frame Sync signal, the Receiver can sample the RD line and store the data in the Receive Sync
Holding Register and the transmitter can transfer Transmit Sync Holding Register in the shift register. T he data
length to be sampled/shifted out during the Frame Sync signal is programmed by the FSLEN field in
SSC_RFMR/SSC_TFMR and has a maximum value of 256.
Concerning the Receive Frame Sync Data operation, if the Frame Sync Length is equal to or lower than the delay
between the start event and the actual data reception, the data sampling operation is performed in the Receive
Sync Holding Register through the receive shift register.
The Transmit Frame Sync Operation is performed by the transmitter only if the bit Frame Sync Data Enable
(FSDEN) in SSC_TFMR is set. If the Fr ame Sync length is equal to or lowe r than the delay betwee n the start event
and the actual data transmission, the n ormal tran smission has priority and the data contained in th e Transmit Sync
Holding Register is transferred in the Transmit Register, then shifted out.
32.8.5.2 Frame Sync Edge Detection
The Frame Sync Edge detection is programmed by the FSEDGE field in SSC_RFMR/SSC_TFM R. This sets the
corresponding flags RXSYN/TXSYN in the SSC Status Register (SSC_SR) on frame synchro edge detection
(signals RF/TF).
32.8.6 Receive Compare Modes
Figure 32-15. Receive Compare Modes
32.8.6.1 Compare Functions
The length of the comparison patterns (Compare 0, Compare 1) and thus the number of bits they are compared to
is defined by FSLEN, but with a maximum value of 256 bi ts. Compariso n is always done by co mparin g the last bits
received with th e comp ar iso n pa tter n. Co mpa re 0 ca n be one start e vent of the Receiver . In this case, the receiver
compares at each new sample the last bits received at the Compare 0 pattern contained in the Compare 0
Register (SSC_RC0R). When this start event is selected, the user can program the Receiver to start a new data
CMP0 CMP3
CMP2
CMP1 Ignored B0 B2
B1
Start
RK
RD
(Input)
FSLEN STDLY DATLEN
655
SAM4S Series [DATASHEET]
Atmel-11100K-ATARM-SAM4S-Datasheet_09-Jun-15
transfer either by writing a new Compare 0, or by receiving continuously until Compare 1 occurs. This selection is
done with the STOP bit in the SSC_RCMR.
32.8.7 Data Format
The data framing format of bo th the tra nsmitter and the r eceiver are pr og rammab le thr oug h the Tra nsmitte r F rame
Mode Register (SSC_TFMR) and the Receiver Frame Mode Register (SSC_RFMR). In either case, the user can
independently select the following parameters:
Event that starts the data transfer (START)
Delay in number of bit periods between the start event and the first data bit (STTDLY)
Length of the data (DATLEN)
Number of data to be transferred for each start event (DATNB)
Length of synchronization transferred for each st art event (FSLEN)
Bit sense: most or lowest significant bit first (MSBF)
Additionally, the transmitter can be used to transfer synchronization and select the level driven on the TD pin while
not in data transfer oper ation. Thi s is don e resp ectively by the Frame Sync Data Enable (FSDEN) and by the Data
Default Value (DATDEF) bits in SSC_TFMR.
Table 32-4. Data Frame Registers
Transmitter Receiver Field Length Comment
SSC_TFMR SSC_RFMR DATLEN Up to 32 Size of word
SSC_TFMR SSC_RFMR DATNB Up to 16 Number of words transmitted in frame
SSC_TFMR SSC_RFMR MSBF –Most significant bit first
SSC_TFMR SSC_RFMR FSLEN Up to 256 Size of Synchro data register
SSC_TFMR –DATDE
F0 or 1 Data default value ended
SSC_TFMR –FSDEN –Enable send SSC_TSHR
SSC_TCMR SSC_RCMR PERIOD Up to 512 Frame size
SSC_TCMR SSC_RCMR STTDLY Up to 255 Size of transmit start delay
SAM4S Series [DATASHEET]
Atmel-11100K-ATARM-SAM4S-Datasheet_09-Jun-15
656
Figure 32-16. Transmit and Receive Frame Fo rmat in Edge/Pulse Start Modes
In the example illustrated in Figu re 32-17 “Transmit Frame Format in Continuous Mode (STTDLY = 0)” , the
SSC_THR is loaded twice. The FSDEN value has no effect on the transmission. SyncData cannot be output in
continuous mode.
Figure 32-17. Transmit Frame Format in Continuous Mode (STTDLY = 0)
Figure 32-18. Receive Frame Format in Continuous Mo de (STTDLY = 0)
Sync Data Default
STTDLY
Sync Data Ignored
RD
Default
Data
DATLEN
Data
Data
Data
DATLEN
Data
Data Default
Default
Ignored
Sync Data
Sync Data
FSLEN
TF/RF
(1)
Start
Start
From SSC_TSHR From SSC_THR
From SSC_THR
From SSC_THR
From SSC_THR
To SSC_RHR To SSC_RHRTo SSC_RSHR
TD
(If FSDEN = 0)
TD
(If FSDEN = 1)
DATNB
PERIOD
From DATDEF From DATDEF
From DATDEF From DATDEF
Note: 1. Example of input on falling edge of TF/RF.
DATLEN
Data
DATLEN
Data Default
Start
From SSC_THR From SSC_THR
TD
Start: 1. TXEMPTY set to 1
2. Write into the SSC_THR
Data Data
Start = Enable Receiver
To SSC_RHR To SSC_RHR
RD
DATLEN DATLEN
657
SAM4S Series [DATASHEET]
Atmel-11100K-ATARM-SAM4S-Datasheet_09-Jun-15
32.8.8 Loop Mode
The receiver can be programmed to rece ive transmissions from the transmitter. This is done by setting the Loop
Mode (LOOP) bit in the SSC_RFMR. In this case, RD is connected to TD, RF is connected to TF and RK is
connected to TK.
32.8.9 Interrupt
Most bits in the SSC_SR have a corresponding bit in interrupt management registers.
The SSC can be program med to generate an interrupt when it detects an event. The interrupt is controlled by
writing the Interrupt Enable Register (SSC_IER) and Interrupt Disable Register (SSC_IDR). These registers
enable and disa ble, respectively, the correspo nding interrupt by setting and clearing the correspon ding bit in the
Interrupt Mask Register (SSC_IMR), which controls the generation of interrupts by asserting the SSC interrupt line
connected to the interrupt controller.
Figure 32-19. Interrupt Block Diagram
SSC_IMR
PDC
Interrupt
Control SSC Interrupt
Set
RXRDY
OVRUN
RXSYNC
Receiver
Transmitter
TXRDY
TXEMPTY
TXSYNC
TXBUFE
ENDTX
RXBUFF
ENDRX
Clear
SSC_IER SSC_IDR
SAM4S Series [DATASHEET]
Atmel-11100K-ATARM-SAM4S-Datasheet_09-Jun-15
658
32.8.10 Register Write Protection
To prevent any single software error from corrupting AIC behavior, certain registers in the address space can be
write-protected by setting the WPEN bit in the SSC Write Protection Mode Register (SSC_WPMR).
If a write access to a write-protected register is detected, the WPVS flag in the SSC Write Protection Status
Register (SSC_WPSR) is set and the field WPVSRC indicates the register in which the write access has been
attempted.
The WPVS bit is automatically cleared after reading the SSC_WPSR.
The following registers can be write-protected:
SSC Clock Mode Register
SSC Receive Clock Mode Register
SSC Receive Frame Mode Register
SSC Transmit Clock Mode Register
SSC Transmit Frame Mode Register
SSC Receive Compare 0 Register
SSC Receive Compare 1 Register
659
SAM4S Series [DATASHEET]
Atmel-11100K-ATARM-SAM4S-Datasheet_09-Jun-15
32.9 Synchronous Serial Controller (SSC) User Interface
Table 32-5 . Register Mapping
Offset Register Name Access Reset
0x0 Control Register SSC_CR Write-only –
0x4 Clock Mode Register SSC_CMR Read/Write 0x0
0x8–0xC Reserved – – –
0x10 Receive Clock Mode Register SSC_RCMR Read/Write 0x0
0x14 Receive Frame Mode Register SSC_RFMR Read/Write 0x0
0x18 Tr ansmit Clock Mode Register SSC_TCMR Read/Write 0x0
0x1C Transmit Frame Mode Register SSC_TFMR Read/Write 0x0
0x20 Receive Holding Register SSC_RHR Read-only 0x0
0x24 Tr ansmit Holding Register SSC_THR Write-only –
0x28–0x2C Reserved – – –
0x30 Receive Sync. Holding Register SSC_RSHR Read-only 0x0
0x34 Tr ansmit Sync. Holding Register SSC_TSHR Read/Write 0x0
0x38 Receive Compare 0 Register SSC_RC0R Read/Write 0x0
0x3C Receive Compare 1 Register SSC_RC1R Read/Write 0x0
0x40 Status Register SSC_SR Read-only 0x000000CC
0x44 Interrupt Enable Register SSC_IER Write-only –
0x48 Interrupt Disable Register SSC_IDR Write-only –
0x4C Interrupt Mask Register SSC_IMR Read-only 0x0
0x50–0xE0 Reserved – – –
0xE4 Write Protection Mode Register SSC_WPMR Read/Write 0x0
0xE8 Write Protection Status Register SSC_WPSR Read-only 0x0
0xEC–0xFC Reserved – – –
0x100–0x128 Reserved for PDC registers – – –
SAM4S Series [DATASHEET]
Atmel-11100K-ATARM-SAM4S-Datasheet_09-Jun-15
660
32.9.1 SSC Control Register
Name: SSC_CR
Address: 0x40004000
Access: Write-only
• RXEN: Rece iv e Enab le
0: No effect.
1: Enables Receive if RXDIS is not set.
• RXDIS: Receive Disable
0: No effect.
1: Disables Receive. If a character is currently being received, disables at end of current character reception.
• TXEN: Transmit Enable
0: No effect.
1: Enables Transmit if TXDIS is not set.
• TXDIS: Transmit Disable
0: No effect.
1: Disables Transmit. If a character is currently being transmitted, disables at end of current character transmission .
• SWRST: Software Reset
0: No effect.
1: Performs a software reset. Has priority on any other bit in SSC_CR.
31 30 29 28 27 26 25 24
––––––––
23 22 21 20 19 18 17 16
––––––––
15 14 13 12 11 10 9 8
SWRST–––––TXDISTXEN
76543210
––––––RXDISRXEN
661
SAM4S Series [DATASHEET]
Atmel-11100K-ATARM-SAM4S-Datasheet_09-Jun-15
32.9.2 SSC Clock Mode Register
Name: SSC_CMR
Address: 0x40004004
Access: Read/Write
This register can only be written if the WPEN bit is cleared in the SSC Write Protection Mode Register.
• DIV: Clock Divider
0: The Clock Divider is not active.
Any other value: The divided clock equals the per ipheral clock divided by 2 times DIV.
The maximum bit rate is fperipheral clock/2. The minimum bit rate is fperipheral clock/2 × 4095 = fperipheral clock/8190.
31 30 29 28 27 26 25 24
––––––––
23 22 21 20 19 18 17 16
––––––––
15 14 13 12 11 10 9 8
–––– DIV
76543210
DIV
SAM4S Series [DATASHEET]
Atmel-11100K-ATARM-SAM4S-Datasheet_09-Jun-15
662
32.9.3 SSC Receive Clock Mode Register
Name: SSC_RCMR
Address: 0x40004010
Access: Read/Write
This register can only be written if the WPEN bit is cleared in the SSC Write Protection Mode Register.
• CKS: Rece iv e Clo c k Sel ec ti on
• CKO: Receive Clock Output Mode Sele ction
• CKI: Receive Clock Inversion
0: The data inputs (Data and Frame Sync signals) are sampled on Receive Clock falling edge. The Frame Sync signal out-
put is shifted out on Receive Clock rising edge.
1: The data inputs (Data and Frame Sync signals) are sampled on Receive Clock rising edge. The Frame Sync signal out-
put is shifted out on Receive Clock falling edge.
CKI affects only the Receive Clock and not the output clock signal.
31 30 29 28 27 26 25 24
PERIOD
23 22 21 20 19 18 17 16
STTDLY
15 14 13 12 11 10 9 8
– – – STOP START
76543210
CKG CKI CKO CKS
Value Name Description
0 MCK Divided Clock
1TK TK Clock signal
2RK RK pin
Value Name Description
0 NONE None, RK pin is an input
1 CONTINUOUS Contin uous Receive Clock, RK pin is an output
2 TRANSFER Receive Clock only during data transfers, RK pin is an output
663
SAM4S Series [DATASHEET]
Atmel-11100K-ATARM-SAM4S-Datasheet_09-Jun-15
• CKG: Receive Clock Gating Selection
• START: Receive Start Selection
• STOP: Receive Stop Selection
0: After completion of a data transfer when starting with a Compare 0, the receiver stops the data transfer and waits for a
new compare 0.
1: After starting a receive with a Compare 0, the receiver operates in a continuous mode until a Compare 1 is detected.
• STTDLY: Receive Start Delay
If STTDLY is not 0, a dela y of STT DL Y c loc k cy cle s is inser te d be twee n th e sta rt even t an d th e ac tua l sta rt of rece ption .
When the Receiver is programmed to start synchronously with the Transmitter, the delay is also applied.
Note: It is very important that STTDLY be set carefully. If STTDLY must be set, it should be done in relation to TAG
(Receive Sync Data) reception.
• PERIOD: Receive Period Divider Selection
This field selects the divider to apply to the se lected Re ceive Clock in order to generate a ne w Fra me Sync Signal. If 0 , no
PERIOD signal is generated. If not 0, a PERIOD signal is generated each 2 x (PERIOD + 1) Receive Clock.
Value Name Description
0 CONTINUOUS None
1 EN_RF_LOW Receive Clock enabled only if RF Low
2 EN_RF_HIGH Receive Clock enabled only if RF High
Value Name Description
0CONTINUOUS
Continuous, as soon as the receiver is enabled, and immediately after the end of transfer of the
previous data.
1 TRANSMIT Transmit start
2RF_LOW Detection of a low level on RF signal
3 RF_HIGH Detection of a high level on RF signal
4RF_FALLING
Detection of a falling edge on RF signal
5 RF_RISING Detection of a rising edge on RF signal
6 RF_LEVEL Detection of any level change on RF signal
7RF_EDGE Detection of any edge on RF signal
8CMP_0 Compare 0
SAM4S Series [DATASHEET]
Atmel-11100K-ATARM-SAM4S-Datasheet_09-Jun-15
664
32.9.4 SSC Receive Frame Mode Register
Name: SSC_RFMR
Address: 0x40004014
Access: Read/Write
This register can only be written if the WPEN bit is cleared in the SSC Write Protection Mode Register.
• DATLEN: Data Length
0: Forbidden value (1-bit data length not supported).
Any other value: The bit stream contains DATLEN + 1 data bits. Moreover, it defines the transfer size performed by the
PDC assigned to the Receiver. If DATLEN is lower or equal to 7, data transfers are in bytes. If DATLEN is between 8 and
15 (included), half-words are transferred, and for any other value, 32-bit words are transferred.
• LOOP: Loop Mode
0: Normal operating mode.
1: RD is driven by TD, RF is driven by TF an d T K drive s RK.
• MSBF: Most Significant Bit First
0: The lowest significant bit of the data register is sampled first in the bit stream.
1: The most significant bit of the data register is sampled first in the bit stream.
• DATNB: Data Number per Frame
This field defines the number of data words to be received after each transfer start, which is equal to (DATNB + 1).
• FSLEN: Receive Frame Sync Length
This field defines the number of bi ts sampled and stored in the Receive Sync Data Register. Wh en this mode is selected by
the START field in the Receive Clock Mode Register , it also determines the length of the sampled data to be compared to
the Compare 0 or Compare 1 register.
This field is used with FSLEN_EXT to determine the pulse length of the Receive Frame Sync signal.
Pulse length is equal to FSLEN + (FSLEN_EXT × 16) + 1 Receive Clock periods.
31 30 29 28 27 26 25 24
FSLEN_EXT – – – FSEDGE
23 22 21 20 19 18 17 16
– FSOS FSLEN
15 14 13 12 11 10 9 8
–––– DATNB
76543210
MSBF – LOOP DATLEN
665
SAM4S Series [DATASHEET]
Atmel-11100K-ATARM-SAM4S-Datasheet_09-Jun-15
• FSOS: Receive Frame Sync Output Selection
• FSEDGE: Frame Sync Edge Detection
Determines which edge on Frame Sync will generate the interrupt RXSYN in the SSC Status Register.
• FSLEN_EXT: FSLEN Field Extension
Extends FSLEN field. For details, refer to FSLEN bit description on page 664.
Value Name Description
0 NONE None, RF pin is an input
1NEGATIVE Negative Pulse, RF pin is an output
2 POSITIVE Positive Pulse, RF pin is an output
3LOW Driven Low during data transfer, RF pin is an output
4HIGH Driven High during data transfer, RF pin is an output
5 TOGGLING Toggl ing at each start of data transfer, RF pin is an output
Value Name Description
0 POSITIVE Positive Edge Detection
1NEGATIVE Negative Edge Detection
SAM4S Series [DATASHEET]
Atmel-11100K-ATARM-SAM4S-Datasheet_09-Jun-15
666
32.9.5 SSC Transmit Clock Mod e Regist e r
Name: SSC_TCMR
Address: 0x40004018
Access: Read/Write
This register can only be written if the WPEN bit is cleared in the SSC Write Protection Mode Register.
• CKS: Transmit Clock Selection
• CKO: Trans m it Clo c k Ou tput Mode Selection
• CKI: Transmit Clock Inversion
0: The data outputs (Data and Frame Sync signals) are shifted out on Transmit Clock falling edge. The Frame sync signal
input is sampled on Transmit clock rising edge.
1: The data outputs (Data and Frame Sync signals) are shifted out on Transmit Clock rising edge. The Frame sync signal
input is sampled on Transmit clock falling edge.
CKI affects only the Transmit Clock and not the output clock signal.
• CKG: Transmit Clock Gating Selection
31 30 29 28 27 26 25 24
PERIOD
23 22 21 20 19 18 17 16
STTDLY
15 14 13 12 11 10 9 8
–––– START
76543210
CKG CKI CKO CKS
Value Name Description
0 MCK Divided Clock
1RK RK Clock signal
2TK TK pin
Value Name Description
0 NONE None, TK pin is an input
1 CONTINUOUS Contin uous Transmit Clock, TK pin is an output
2 TRANSFER Transmit Clock only during data transfers, TK pin is an output
Value Name Description
0 CONTINUOUS None
1EN_TF_LOWT ransmit Clock enabled only if TF Low
2EN_TF_HIGHT ransmit Clock enabled only if TF High
667
SAM4S Series [DATASHEET]
Atmel-11100K-ATARM-SAM4S-Datasheet_09-Jun-15
• START: Transmit Start Selection
• STTDLY: Transmit Start Delay
If STTDLY is not 0, a delay of STTDLY clock cycles is inserted between the start ev ent and the actual star t of transmission
of data. When the Transmitter is programmed to start synchronously with the Receiver, the delay is also applied.
Note: Note: STTDLY must be set carefully. If STTDLY is too short in respect to TAG (Transmit Sync Data) emission, data is emitted
instead of the end of TAG.
• PERIOD: Transmit Period Divider Selection
This field selects the divider to apply to the selected Transmit Clock to generate a new Frame Sync Signal. If 0, no period
signal is generated. If not 0, a period signal is generated at each 2 × (PERIOD + 1) Transmit Clock.
Value Name Description
0CONTINUOUS
Continuous, as soon as a word is written in the SSC_THR (if Transmit is enabled), and
immediately after the end of transfer of the previous data
1 RECEIVE Receive start
2TF_LOW Detection of a low level on TF signal
3TF_HIGH Detection of a high level on TF signal
4 TF_FALLING Detection of a falling edge on TF signal
5 TF_RISING Detection of a rising edge on TF signal
6 TF_LEVEL Detection of any level change on TF signa l
7TF_EDGE Detection of any edge on TF signal
SAM4S Series [DATASHEET]
Atmel-11100K-ATARM-SAM4S-Datasheet_09-Jun-15
668
32.9.6 SSC Transmit Frame Mode Register
Name: SSC_TFMR
Address: 0x4000401C
Access: Read/Write
This register can only be written if the WPEN bit is cleared in the SSC Write Protection Mode Register.
• DATLEN: Data Length
0: Forbidden value (1-bit data length not supported ).
Any other value: The bit stream contains DATLEN + 1 data bits. Moreover, it defines the transfer size performed by the
PDC assigned to the Transmit. If DATLEN is lower or equal to 7, data transfers are bytes, if DATLEN is betwe en 8 an d 15
(included), half-words are transferred, and for any other value, 32-bit words are transferred.
• DATDEF: Data Default Value
This bit defines the level driven on the TD pin while out of transmission. Note that if the pin is defined as multi-drive by the
PIO Controller, the pin is enabled only if the SCC TD output is 1.
• MSBF: Most Significant Bit First
0: The lowest significant bit of the data register is shifted out first in the bit stream.
1: The most significant bit of the data register is shifted out first in the bit stream.
• DATNB: Data Number per Frame
This field defines the number of data words to be transferred after each transfer start, which is equal to (DATNB + 1).
• FSLEN: Transmit Frame Sync Length
This field defines the length of the Transmit Frame Sync signal and the number of bits shifted out fro m the Transmit Sync
Data Register if FSDEN is 1.
This field is used with FSLEN_EXT to determine the pulse length of the Transmit Frame Sync signal.
Pulse length is equal to FSLEN + (FSLEN_EXT × 16) + 1 Transmit Clock period.
31 30 29 28 27 26 25 24
FSLEN_EXT –––FSEDGE
23 22 21 20 19 18 17 16
FSDEN FSOS FSLEN
15 14 13 12 11 10 9 8
–––– DATNB
76543210
MSBF – DATDEF DATLEN
669
SAM4S Series [DATASHEET]
Atmel-11100K-ATARM-SAM4S-Datasheet_09-Jun-15
• FSOS: Transmit Frame Sync Output Selection
• FSDEN: Frame Sync Data Enable
0: The TD line is driven with the default value during the Transmit Frame Sync signal.
1: SSC_TSHR value is shifted out during the transmission of the Transmit Frame Sync signal.
• FSEDGE: Frame Sync Edge Detection
Determines which edge on frame sync will generate the interrupt TXSYN (Status Register).
• FSLEN_EXT: FSLEN Field Extension
Extends FSLEN field. For details, refer to FSLEN bit description on page 668.
Value Name Description
0 NONE None, TF pin is an inpu t
1NEGATIVE Negative Pulse, TF pin is an output
2 POSITIVE Positive Pulse, TF pin is an output
3LOW Driven Low during data transfer
4 HIGH Driven High during data transfer
5 TOGGLING Togglin g at each start of data transfer
Value Name Description
0 POSITIVE Positive Edge Detection
1NEGATIVE Negative Edge Detection
SAM4S Series [DATASHEET]
Atmel-11100K-ATARM-SAM4S-Datasheet_09-Jun-15
670
32.9.7 SSC Receive Holding Register
Name: SSC_RHR
Address: 0x40004020
Access: Read-only
• RDAT: Rece iv e Data
Right aligned regardless of the number of data bits defined by DATLEN in SSC_RFMR.
31 30 29 28 27 26 25 24
RDAT
23 22 21 20 19 18 17 16
RDAT
15 14 13 12 11 10 9 8
RDAT
76543210
RDAT
671
SAM4S Series [DATASHEET]
Atmel-11100K-ATARM-SAM4S-Datasheet_09-Jun-15
32.9.8 SSC Transmit Holding Register
Name: SSC_THR
Address: 0x40004024
Access: Write-only
• TDAT: Transmit Data
Right aligned regardless of the number of data bits defined by DATLEN in SSC_TFMR.
31 30 29 28 27 26 25 24
TDAT
23 22 21 20 19 18 17 16
TDAT
15 14 13 12 11 10 9 8
TDAT
76543210
TDAT
SAM4S Series [DATASHEET]
Atmel-11100K-ATARM-SAM4S-Datasheet_09-Jun-15
672
32.9.9 SSC Receive Synchronization Holding Register
Name: SSC_RSHR
Address: 0x40004030
Access: Read-only
• RSDAT: Receive Synchronization Data
31 30 29 28 27 26 25 24
––––––––
23 22 21 20 19 18 17 16
––––––––
15 14 13 12 11 10 9 8
RSDAT
76543210
RSDAT
673
SAM4S Series [DATASHEET]
Atmel-11100K-ATARM-SAM4S-Datasheet_09-Jun-15
32.9.10 SSC Transmit Synchronization Holding Register
Name: SSC_TSHR
Address: 0x40004034
Access: Read/Write
• TSDAT: Transmit Synchronization Data
31 30 29 28 27 26 25 24
––––––––
23 22 21 20 19 18 17 16
––––––––
15 14 13 12 11 10 9 8
TSDAT
76543210
TSDAT
SAM4S Series [DATASHEET]
Atmel-11100K-ATARM-SAM4S-Datasheet_09-Jun-15
674
32.9.11 SSC Receive Compare 0 Register
Name: SSC_RC0R
Address: 0x40004038
Access: Read/Write
This register can only be written if the WPEN bit is cleared in the SSC Write Protection Mode Register.
• CP0: Receive Compare Data 0
31 30 29 28 27 26 25 24
––––––––
23 22 21 20 19 18 17 16
––––––––
15 14 13 12 11 10 9 8
CP0
76543210
CP0
675
SAM4S Series [DATASHEET]
Atmel-11100K-ATARM-SAM4S-Datasheet_09-Jun-15
32.9.12 SSC Receive Compare 1 Register
Name: SSC_RC1R
Address: 0x4000403C
Access: Read/Write
This register can only be written if the WPEN bit is cleared in the SSC Write Protection Mode Register.
• CP1: Receive Compare Data 1
31 30 29 28 27 26 25 24
––––––––
23 22 21 20 19 18 17 16
––––––––
15 14 13 12 11 10 9 8
CP1
76543210
CP1
SAM4S Series [DATASHEET]
Atmel-11100K-ATARM-SAM4S-Datasheet_09-Jun-15
676
32.9.13 SSC Status Register
Name: SSC_SR
Address: 0x40004040
Access: Read-only
• TXRDY: Transmit Ready
0: Data has been loaded in SSC_THR and is waiting to be loaded in the transmit shift register (TSR).
1: SSC_THR is empty.
• TXEMPTY: Transmit Empty
0: Data remains in SSC_THR or is currently transmitted from TSR.
1: Last data written in SSC_THR has been loaded in TSR and last data loaded in TSR has been transmitted.
• ENDTX: End of Transmission
0: The register SSC_TCR has not reached 0 since the last write in SSC_TCR or SSC_TNCR.
1: The register SSC_TCR has reached 0 since the last write in SSC_TCR or SSC_TNCR.
• TXBUFE: Transmit Buffer Empty
0: SSC_TCR or SSC_TNCR have a value other than 0.
1: Both SSC_TCR and SSC_TNCR have a value of 0.
• RXRDY: Receive Ready
0: SSC_RHR is empty.
1: Data has been received and loaded in SSC_RHR.
• OVRUN: Receive Overrun
0: No data has been loaded in SSC_RHR while previous data has not been read since the last read of the Status Re giste r.
1: Data has been loade d in SSC_RHR while previo us data has not yet bee n read since th e last rea d of the Sta tus Register.
• ENDRX: End of Reception
0: Data is written on the Receive Counter Register or Receive Next Counter Register.
1: End of PDC transfer when Receive Counter Register has arrived at zero.
31 30 29 28 27 26 25 24
––––––––
23 22 21 20 19 18 17 16
––––––RXENTXEN
15 14 13 12 11 10 9 8
––––RXSYN TXSYN CP1 CP0
76543210
RXBUFF ENDRX OVRUN RXRDY TXBUFE ENDTX TXEMPTY TXRDY
677
SAM4S Series [DATASHEET]
Atmel-11100K-ATARM-SAM4S-Datasheet_09-Jun-15
• RXBUFF: Receive Buffer Full
0: SSC_RCR or SSC_RNCR have a value other than 0.
1: Both SSC_RCR and SSC_RNCR have a value of 0.
•CP0: Compare 0
0: A compare 0 has not occurred since the last read of the Status Register.
1: A compare 0 has occurred since the last read of the Status Register.
•CP1: Compare 1
0: A compare 1 has not occurred since the last read of the Status Register.
1: A compare 1 has occurred since the last read of the Status Register.
• TXSYN: Transmit Sync
0: A Tx Sync has not occurred since the last read of the Status Register.
1: A Tx Sync has occurred since the last read of the Status Register.
• RXSYN: Receive Sync
0: An Rx Sync has not occurred since the last read of the Status Register.
1: An Rx Sync has occurred since the last read of the Status Register.
• TXEN: Transmit Enable
0: Transmit is disabled.
1: Transmit is enabled.
• RXEN: Rece iv e Enab le
0: Receive is disabled.
1: Receive is enabled.
SAM4S Series [DATASHEET]
Atmel-11100K-ATARM-SAM4S-Datasheet_09-Jun-15
678
32.9.14 SSC Interrupt Enable Register
Name: SSC_IER
Address: 0x40004044
Access: Write-only
• TXRDY: Transmit Ready Interrupt Enable
0: No effect.
1: Enables the Transmit Ready In terrupt.
• TXEMPTY: Transmit Empty Interrupt Enable
0: No effect.
1: Enables the Transmit Empty Interrupt.
• ENDTX: End of Transmission Interrupt Enable
0: No effect.
1: Enables the End of Transmission Interrupt.
• TXBUFE: Transmit Buffer Empty Interrupt Enable
0: No effect.
1: Enables the Transmit Buffer Empty Interrupt
• RXRDY: Receive Read y Interrupt Enable
0: No effect.
1: Enables the Receive Ready Interrupt.
• OVRUN: Receive Overrun Interrupt Enable
0: No effect.
1: Enables the Receive Overrun Interrupt.
• ENDRX: End of Reception Interrupt Enable
0: No effect.
1: Enables the End of Reception Interrupt.
31 30 29 28 27 26 25 24
––––––––
23 22 21 20 19 18 17 16
––––––––
15 14 13 12 11 10 9 8
––––RXSYN TXSYN CP1 CP0
76543210
RXBUFF ENDRX OVRUN RXRDY TXBUFE ENDTX TXEMPTY TXRDY
679
SAM4S Series [DATASHEET]
Atmel-11100K-ATARM-SAM4S-Datasheet_09-Jun-15
• RXBUFF: Receive Buffer Full Interrupt Enable
0: No effect.
1: Enables the Receive Buffer Full Interrupt.
• CP0: Compare 0 Interrupt Enable
0: No effect.
1: Enables the Com p ar e 0 In te rr up t.
• CP1: Compare 1 Interrupt Enable
0: No effect.
1: Enables the Com p ar e 1 In te rr up t.
• TXSYN: Tx Sync Interrupt Enable
0: No effect.
1: Enables the Tx Sync Interrupt.
• RXSYN: Rx Sync Interrupt Enable
0: No effect.
1: Enables the Rx Sync Interrupt.
SAM4S Series [DATASHEET]
Atmel-11100K-ATARM-SAM4S-Datasheet_09-Jun-15
680
32.9.15 SSC Interrupt Disable Register
Name: SSC_IDR
Address: 0x40004048
Access: Write-only
• TXRDY: Transmit Ready Interrupt Disable
0: No effect.
1: Disables the Transmit Ready Interrupt.
• TXEMPTY: Transmit Empty Interrupt Disable
0: No effect.
1: Disables the Transmit Empty Interrupt.
• ENDTX: End of Transmission Interrupt Disable
0: No effect.
1: Disables the End of Transmission Interrupt.
• TXBUFE: Transmit Buffer Empty Interrupt Disable
0: No effect.
1: Disables the Transmit Buffer Empty Interrupt.
• RXRDY: Receive Read y Interrupt Disable
0: No effect.
1: Disables the Receive Ready Interrupt.
• OVRUN: Receive Overrun Interrupt Disable
0: No effect.
1: Disables the Receive Overrun Interrupt.
• ENDRX: End of Reception Interrupt Disable
0: No effect.
1: Disables the End of Reception Interrupt.
31 30 29 28 27 26 25 24
––––––––
23 22 21 20 19 18 17 16
––––––––
15 14 13 12 11 10 9 8
––––RXSYN TXSYN CP1 CP0
76543210
RXBUFF ENDRX OVRUN RXRDY TXBUFE ENDTX TXEMPTY TXRDY
681
SAM4S Series [DATASHEET]
Atmel-11100K-ATARM-SAM4S-Datasheet_09-Jun-15
• RXBUFF: Receive Buffer Full Interrupt Disable
0: No effect.
1: Disables the Receive Buffer Full Interrupt.
• CP0: Compare 0 Interrupt Disable
0: No effect.
1: Disables the Compare 0 Interrupt.
• CP1: Compare 1 Interrupt Disable
0: No effect.
1: Disables the Compare 1 Interrupt.
• TXSYN: Tx Sync Interrupt Enable
0: No effect.
1: Disables the Tx Sync Interrupt.
• RXSYN: Rx Sync Interrupt Enable
0: No effect.
1: Disables the Rx Sync Interrupt.
SAM4S Series [DATASHEET]
Atmel-11100K-ATARM-SAM4S-Datasheet_09-Jun-15
682
32.9.16 SSC Interrupt Mask Register
Name: SSC_IMR
Address: 0x4000404C
Access: Read-only
• TXRDY: Transmit Ready Interrupt Mask
0: The Transmit Ready Interrupt is disabled.
1: The Transmit Ready Interrupt is enabled.
• TXEMPTY: Transmit Empty Interrupt Mask
0: The Transmit Empty Interrupt is disabled.
1: The Transmit Empty Interrupt is enabled.
• ENDTX: End of Transmission Interrupt Mask
0: The End of Transmission Interrupt is disabled.
1: The End of Transmission Interrupt is enabled.
• TXBUFE: Transmit Buffer Empty Interrupt Mask
0: The Transmit Buffer Empty Interrupt is disabled.
1: The Transmit Buffer Empty Interrupt is enabled.
• RXRDY: Receive Re ady Interrupt Mask
0: The Receive Read y Int er ru p t is disab led .
1: The Receive Ready Interrupt is enabled.
• OVRUN: Receive Overrun Inte rrupt Mask
0: The Receive Over ru n In te rr up t is disa ble d.
1: The Receive Over ru n In te rr up t is ena b led .
• ENDRX: End of Reception Interrupt Mask
0: The End of Reception Interrupt is disabled.
1: The End of Reception Interrupt is enabled.
31 30 29 28 27 26 25 24
––––––––
23 22 21 20 19 18 17 16
––––––––
15 14 13 12 11 10 9 8
––––RXSYN TXSYN CP1 CP0
76543210
RXBUFF ENDRX OVRUN RXRDY TXBUFE ENDTX TXEMPTY TXRDY
683
SAM4S Series [DATASHEET]
Atmel-11100K-ATARM-SAM4S-Datasheet_09-Jun-15
• RXBUFF: Receive Buffer Full Interrupt Mask
0: The Receive Buffer Full Interrupt is disabled.
1: The Receive Buffer Full Interrupt is enabled.
• CP0: Compare 0 Interrupt Mask
0: The Compare 0 Interrupt is disabled.
1: The Compare 0 Interrupt is enabled.
• CP1: Compare 1 Interrupt Mask
0: The Compare 1 Interrupt is disabled.
1: The Compare 1 Interrupt is enabled.
• TXSYN: Tx Sync Interrupt Mask
0: The Tx Sync Interrupt is disabled.
1: The Tx Sync Interrupt is enabled.
• RXSYN: Rx Sync Interrupt Mask
0: The Rx Sync Interrupt is disabled.
1: The Rx Sync Interrupt is enabled.
SAM4S Series [DATASHEET]
Atmel-11100K-ATARM-SAM4S-Datasheet_09-Jun-15
684
32.9.17 SSC Write Protection Mode Register
Name: SSC_WPMR
Address: 0x400040E4
Access: Read/Write
• WPEN: Write Protec ti on Ena b le
0: Disables the write protection if WPKEY corresponds to 0x535343 (“SSC” in ASCII).
1: Enables the write protection if WPKEY corresponds to 0x535343 (“SSC” in ASCII).
See Section 32.8.10 “Register Write Protection” for the list of registers that can be pro tected.
• WPKEY: Write Protection Key
31 30 29 28 27 26 25 24
WPKEY
23 22 21 20 19 18 17 16
WPKEY
15 14 13 12 11 10 9 8
WPKEY
76543210
–––––––WPEN
Value Name Description
0x535343 PASSWD Writing any other value in this field aborts the write operation of the WPEN bit.
Always reads as 0.
685
SAM4S Series [DATASHEET]
Atmel-11100K-ATARM-SAM4S-Datasheet_09-Jun-15
32.9.18 SSC Write Protection Status Register
Name: SSC_WPSR
Address: 0x400040E8
Access: Read-only
• WPVS: Write Protection Violation Status
0: No write protec tion v iola tio n ha s oc curred since the last read of the SSC_WPSR.
1: A write protection violation has occurred since the last read of the SSC_WPSR. If this violation is an unauthorized
attempt to write a protected register, the associated violation is reported into field WPVSRC.
• WPVSRC: Write Protect Violation Source
When WPVS = 1, WPVSRC indicates the register address offset at which a write access has been attempted.
31 30 29 28 27 26 25 24
––––––––
23 22 21 20 19 18 17 16
WPVSRC
15 14 13 12 11 10 9 8
WPVSRC
76543210
–––––––WPVS
SAM4S Series [DATASHEET]
Atmel-11100K-ATARM-SAM4S-Datasheet_09-Jun-15
686
33. Serial Peripheral Interface (SPI)
33.1 Description
The Serial Per ipheral Interface (SPI) circuit is a synchronous serial data link that provides communication with
external devices in Master or Slave mode. It also enables communication between processors if an external
processor is connected to the system.
The Serial Peripheral Interface is essentially a Shift register that serially transmits data bits to other SPIs. During a
data transfer, one SPI system acts as the “master”' which controls the data flow, while the other devices act as
“slaves'' which have data shifted into and out by the master. Different CPUs can take turn being masters (multiple
master protocol, contrary to single master protocol where one CPU is always the master while all of the others are
always slaves). One master can simultaneously shift data into multiple slaves. However, only one slave can drive
its output to write data back to the master at any given time.
A slave device is selected when the master asserts its NSS signal. If multiple slave devices exist , the master
generates a separate slave select signal for each slave (NPCS).
The SPI system consists of two data lines and two control lines:
Master Out Slave In (MOSI)—This data line supplies the output data from the master shifted into the input(s)
of the slave(s).
Master In Slave Out (MISO)—This data line sup plies the output data from a slave to the input of the master .
There may be no more than one slave transmitting data during any particular transfer.
Serial Clock (SPCK)—This control line is driven by the master and regulates the flow of the data bits. The
master can transmit data at a variety of baud rates; there is one SPCK pulse for each bit tha t is transmitted.
Slave Select (NSS)—This control line allows slaves to be turned on and off by hardware.
687
SAM4S Series [DATASHEET]
Atmel-11100K-ATARM-SAM4S-Datasheet_09-Jun-15
33.2 Embedded Characteristics
Master or Slave Serial Peripheral Bus Interface
8-bit to 16-bit programmable data length per chip select
Programmable phase and polarity per chip select
Programmable transfer delay between consecutive transfers and delay before SPI clock per chip
select
Programmable delay between chip selects
Selectable mode fault detection
Master Mode can drive SPCK up to Peripheral Clock
Master Mode Bit Rate can be Independent of the Processor/Peripheral Clock
Slave mode operates on SPCK, asynchronously with core and bus clock
Four chip selects with external decoder support allow communication with up to 15 peripherals
Communication with Serial External Devices Supported
Serial memories, such as DataFlash and 3-wire EEPROMs
Serial peripherals, such as ADCs, DACs, LCD controllers, CAN controllers and sensors
External copr oc ess or s
Connection to PDC Channel Capabilities, Optimizing Data Transfers
One channel for the receiver
One channel for the transmitter
Register Write Protection
SAM4S Series [DATASHEET]
Atmel-11100K-ATARM-SAM4S-Datasheet_09-Jun-15
688
33.3 Block Diagram
33.4 Application Block Diagram
Figure 33-2. Application Bloc k Diagram: Single Master/Multiple Slave Imp lementation
Figure 33-1. Block Diagram
PDC
SPI
Peripheral bridge
PMC
Peripheral
clock
Bus clock
AHB Matrix
Trigger
events
SPI Master
SPCK
MISO
MOSI
NPCS0
NPCS1
NPCS2
SPCK
MISO
MOSI
NSS
Slave 0
SPCK
MISO
MOSI
NSS
Slave 1
SPCK
MISO
MOSI
NSS
Slave 2
NC
NPCS3
689
SAM4S Series [DATASHEET]
Atmel-11100K-ATARM-SAM4S-Datasheet_09-Jun-15
33.5 Signal Description
33.6 Product Dependencies
33.6.1 I/O Lines
The pins used for interfacing the compliant exter nal devices can be multiplexed with PIO lines. The programmer
must first program the PIO controllers to assign the SPI pins to th eir peripheral functions.
33.6.2 Power Management
The SPI can be clocked through the Power Management Controller (PMC), thus the programmer must first
configure the PMC to enable the SPI clock.
Table 33-1. Signal Description
Pin Name Pin Description
Type
Master Slave
MISO Master In Slave Out Input Output
MOSI Master Out Slave In Output Input
SPCK Serial Clock Output Input
NPCS1–NPCS3 Peripheral Chip Selects Output Unused
NPCS0/NSS Peripheral Chip Select/Slave Select Output Input
Table 33-2. I/O Lines
Instance Signal I/O Line Peripheral
SPI MISO PA12 A
SPI MOSI PA13 A
SPI NPCS0 PA11 A
SPI NPCS1 PA9 B
SPI NPCS1 PA31 A
SPI NPCS1 PB14 A
SPI NPCS1 PC4 B
SPI NPCS2 PA10 B
SPI NPCS2 PA30 B
SPI NPCS2 PB2 B
SPI NPCS3 PA3 B
SPI NPCS3 PA5 B
SPI NPCS3 PA22 B
SPI SPCK PA14 A
SAM4S Series [DATASHEET]
Atmel-11100K-ATARM-SAM4S-Datasheet_09-Jun-15
690
33.6.3 Interrupt
The SPI interface has an interrupt line connected to the in terrupt controller. Handling the SPI interrupt requires
programming the interrupt controller before configuring the SPI.
33.6.4 Peripheral DMA Controller (PDC)
The SPI interface can be used in conjunction with the PDC in order to reduce processor overhead. For a full
description of the PDC, refer to the corresponding section in the full datasheet.
Table 33-3. Peripheral IDs
Instance ID
SPI 21
691
SAM4S Series [DATASHEET]
Atmel-11100K-ATARM-SAM4S-Datasheet_09-Jun-15
33.7 Functional Description
33.7.1 Modes of Operation
The SPI operates in Master mode or in Slave mode.
The SPI operates in Master mode by writing a 1 to the MSTR bit in the SPI Mode Register (SPI_MR):
Pins NPCS0 to NPCS3 are all configured as outputs
The SPCK pin is driven
The MISO line is wired on the receiver input
The MOSI line is driven as an output by the transmitter.
The SPI operates in Slave mode if the MSTR bit in the SPI_MR is written to 0:
The MISO line is driven by the tr an sm itte r outp u t
The MOSI line is wired on the receiver input
The SPCK pin is driven by the transmitter to synchronize the receiver.
The NPCS0 pin becomes an input, and is used as a slave select signal (NSS)
NPCS1 to NPCS3 are not driven and can be used for other purposes.
The data transfers are identically programmable for both modes of operations. The baud rate generator is
activated only in Master mode.
33.7.2 Data Transfer
Four combinations of polarity and phase are availab le for data transfers. The clock po larity is prog rammed with the
CPOL bit in the SPI Chip Select register (SPI_CSR). The clock phase is programmed with the NCPHA bit. These
two parameters determine the edges of the clock signal on which data is driven and sampled. Each of the two
parameters has two possible states, resu lting in four possible combinations that a re incompatible with one a nother.
Consequently, a master/slave pair must use the same parameter pair values to communicate. If multiple slaves
are connected and req uire different configurations, the master m ust reconfigure itself each time it needs to
communicate with a different slave.
Table 33-4 shows the four modes and corres po nd in g paramete r se ttin gs .
Figure 33-3 and Figure 33-4 show examples of data transfers.
Table 33-4. SPI Bus Protocol Mode
SPI Mode CPOL NCPHA Shift SPCK Edge Ca pture SPCK Edge SPCK Inactive Level
0 0 1 Falling Rising Low
1 0 0 Rising Falling Low
2 1 1 Rising Falling High
3 1 0 Falling Rising High
SAM4S Series [DATASHEET]
Atmel-11100K-ATARM-SAM4S-Datasheet_09-Jun-15
692
Figure 33-3. SPI Transfer Format (NCPHA = 1, 8 bits per transfer)
Figure 33-4. SPI Transfer Format (NCPHA = 0, 8 bits per transfer)
6
*
SPCK
(CPOL = 0)
SPCK
(CPOL = 1)
MOSI
(from master)
MISO
(from slave)
NSS
(to slave)
SPCK cycle (for reference)
MSB
MSB
LSB
LSB
6
6
5
5
4
4
3
3
2
2
1
1
* Not defined.
12345 786
SPCK
(CPOL = 0)
SPCK
(CPOL = 1)
1 2345 7
MOSI
(from master)
MISO
(from slave)
NSS
(to slave)
SPCK cycle (for reference) 8
MSB
MSB
LSB
LSB
6
6
5
5
4
4
3
3
1
1
* Not defined.
2
2
6
*
693
SAM4S Series [DATASHEET]
Atmel-11100K-ATARM-SAM4S-Datasheet_09-Jun-15
33.7.3 Master Mode Operations
When configured in Master mode, the SPI operates on the clock generated by the internal programmable baud
rate generator. It fu lly controls the data transfe rs to and from the slave (s) connected to the SPI bus. The SPI drives
the chip select line to the slave and the serial clock signal (SPCK).
The SPI features two holding registers, the Transmit Data Register (SPI_TDR) and the Receive Data Register
(SPI_RDR), and a single shift register. The holding registers maintain the data flow at a constant rate.
After enabling the SPI, a data transfer starts when the processor writes to the SPI_TDR. The written data is
immediately transferre d in the Shift register and the transfer on the SPI bus sta rts. While the data in the Shift
register is shifted on the MOSI line, the MISO line is sampled and shifted in the Shift register. Data cannot be
loaded in the SPI_RDR without transmitting data. If there is no data to transmit, dummy data can be used
(SPI_TDR filled with ones). When the SPI_MR.WDRBT bit is set, new data cannot be transmitted if the SPI_RDR
has not been read. If Receiving mode is not required, for example when communicating with a slave receiver only
(such as an LCD), the receive status flags in the SPI Status register (SPI_SR) ca n be discarded.
Before writing the SPI_TDR, the PCS field in the SPI_MR must be set in order to select a slave.
If new data is written in the SPI_TDR during the transfer, it is kept in the SPI_TDR until the current transfer is
completed. Then, the received data is tran sferr ed fro m the Shift register to the SPI_RDR, the data in the SPI_TDR
is loaded in the Shift register and a new transfer starts.
As soon as the SPI_TDR is written, the Tr ansmit Data Register Empty (TDRE) flag in the SPI_SR is cleared. When
the data written in the SPI_TDR is loaded into the Shift register, the TDRE flag in the SPI_SR is set. The TDRE bit
is used to trigger the Transmit PDC channel.
See Figure 33-5.
The end of transfer is indicated by the TXEMPTY flag in the SPI_SR. If a tra nsfe r de lay ( DLY BCT) is grea ter than
0 for the last transfer, TXEMPTY is set after the completion of this delay. The peripheral clock can be switched off
at this time.
Note: When the SPI is enabled, the TDRE and TXEMPTY flags are set.
Figure 33-5. TDRE and TXEMPTY flag behavior
The transfer of received data from the Sh ift register to the SPI_RDR is indicated by the Receive Data Register Full
(RDRF) bit in the SPI_SR. When the received data is read, the RDRF bit is cleared.
If the SPI_RDR has not been read before new da ta is received, the Overrun Error (OVRES) bit in the SPI_SR is
set. As long as this flag is set, data is loaded in the SPI_RDR. The user has to read the SPI_SR to clear the
OVRES bit.
Figure 33-6, shows a block diagram of the SPI when operating in Master mode. Figure 33-7 on page 695 shows a
flow chart describing how transfers are handled.
TDRE
TXEMPTY
Transfer
Write SPI_CR.SPIEN =1 Write SPI_TDR
Transfer Transfer
Write SPI_TDR Write SPI_TDR
automatic set
TDR loaded
in shifter
automatic set
TDR loaded
in shifter
automatic set
TDR loaded
in shifter
DLYBCT DLYBCT
DLYBCT
SAM4S Series [DATASHEET]
Atmel-11100K-ATARM-SAM4S-Datasheet_09-Jun-15
694
33.7.3.1 Master Mode Block Diagram
Figure 33-6. Master Mode Block Diagram
Shift Register
SPCK
MOSI
LSB MSB
MISO
SPI_RDR
RD
SPI
Clock
TDRE
SPI_TDR
TD
RDRF
OVRES
SPI_CSRx
CPOL
NCPHA
BITS
Peripheral clock Baud Rate Generator
SPI_CSRx
SCBR
NPCSx
NPCS0
NPCS0
0
1
PS
SPI_MR
PCS
SPI_TDR
PCS
MODF
Current
Peripheral
SPI_RDR
PCS
SPI_CSRx
CSAAT
PCSDEC
MODFDIS
MSTR
695
SAM4S Series [DATASHEET]
Atmel-11100K-ATARM-SAM4S-Datasheet_09-Jun-15
33.7.3.2 Master Mode Flow Diagram
Figure 33-7. Master Mode Flow Diagram
SPI Enable
TDRE/TXEMPTY are set
CSAAT ?
(HW check)
PS ?
(HW check)
1
0
0
1
1
NPCS <= SPI_TDR(PCS) NPCS <= SPI_MR(PCS)
Delay DLYBS
Shifter <= SPI_TDR(TD)
TDRE is set
Data Transfer
(SPI bus driven)
SPI_RDR(RD) <= Shifter
RDRF is set
TDRE ?
(HW check)
NPCS deasserted
Delay DLYBCS
Fixed
peripheral
Variable
peripheral
Delay DLYBCT
0 (i.e. a new write to SPI_TDR occured while data transfer or delay DLYBCT)
1CSAAT ?
(HW check)
0
PS ?
(HW check) 0
1
SPI_TDR(PCS)
= NPCS ?
(HW check)
no
yes SPI_MR(PCS)
= NPCS ?
(HW check)
no
NPCS deasserted
Delay DLYBCS
NPCS <= SPI_TDR(PCS)
NPCS deasserted
Delay DLYBCS
NPCS <= SPI_MR(PCS),
SPI_TDR(PCS)
Fixed
peripheral
Variable
peripheral
- NPCS defines the current Chip Select
- CSAAT, DLYBS, DLYBCT refer to the fields of the
Chip Select Register corresponding to the Current Chip Select
- ‘x <= y’ must be interpreted as ‘x is loaded with y’ where x,y
represent either register fields or SPI pins
- HW = hardware, SW = software
TDRE/TXEMPTY are cleared
Write SPI_TDR ? no
yes
TXEMPTY is set
TDRE ?
(SW check)
0
1
Read SPI_RDR(RD)
if read is required
From this step,
SPI_TDR can be
rewritten for the
next transfer
SAM4S Series [DATASHEET]
Atmel-11100K-ATARM-SAM4S-Datasheet_09-Jun-15
696
Figure 33-8 shows the behavior of Transmit Data Register Empty (TDRE), Receive Data Register (RDRF) and
Transmission Register Empty (TXEMPTY) statu s flags within the SPI_SR during an 8-bit data transfe r in Fixed
mode without the PDC involved.
Figure 33-8. Status Register Flags Behavior
6
SPCK
MOSI
(from master)
MISO
(from slave)
NPCS0
MSB
MSB
LSB
LSB
6
6
5
5
4
4
3
3
2
2
1
1
1 2345 786
RDRF
TDRE
TXEMPTY
Write in
SPI_TDR
RDR read
shift register empty
697
SAM4S Series [DATASHEET]
Atmel-11100K-ATARM-SAM4S-Datasheet_09-Jun-15
Figure 33-9 shows the behavior of Transmission Register Empty (TXEMPTY), End of RX buffer (ENDRX), End of
TX buffer (ENDTX), RX Buffer Full (RXBUFF ) and TX Buffer Empty (TXBUFE) status flags with in the SPI_SR
during an 8-bit data transfer in Fixed mode with the PDC involved. The PDC is programmed to transfer and receive
three units of data. Th e next pointer and coun ter are no t used. The RDRF and TDRE are n ot shown because these
flags are managed by the PDC when using the PDC.
Figure 33-9. PDC Status Register Flags Behavior
33.7.3.3 Clock Generation
The SPI Baud rate clock is generated by dividing the peripheral clock by a value between 1 and 255.
If the SCBR field in the SPI_CSR is programmed to 1, the operating baud rate is peripheral clock (see the
electrical characteristics section for the SPCK maximum frequency). Triggering a transfer while SCBR is at 0 can
lead to unpredictable results.
At reset, SCBR is 0 and the user has to program it to a valid value before performing the first transfer.
The divisor can be defined independently for each chip select, as it has to be programmed in the SCBR field. This
allows the SPI to automa tica lly ad ap t th e ba ud rat e for ea ch int er fa ce d pe rip h er al withou t re pr og ra m m ing .
33.7.3.4 Transfer Delays
Figure 33-10 shows a chip select transfer change and con secutive transfe rs on the same chip select. Three delays
can be programmed to modify the transfer waveforms:
Delay between the chip selects—programmable only once for all chip selects by writing the DLYBCS field in
the SPI_MR. The SPI slave device deac tivation delay is ma naged through DLYBCS. If there is only one SPI
slave device connected to the master, the DLYBCS field does not need to be configured. If several slave
devices are connected to a master, DLYBCS must be configured depending on the highest deactivation
delay. Refer to the SPI slave device electrical characteristics.
Delay before SPCK—independ ently pr ogra mma ble for e ach chip select by writing th e DLYBS field. The SPI
slave device activation delay is managed through DLYBS. Refer to the SPI slave device electrical
characteristics to define DLYBS.
654321
SPCK
MOSI
(from master)
NPCS0
MSB
LSB
654321
12 3
ENDTX
TXEMPTY
MSB
LSB
654321
654321
MISO
(from slave)
654321
654321
ENDRX
TXBUFE
RXBUFF
TDRE
(not required
if PDC is used) PDC loads first byte
PDC loads 2nd byte
(double buffer effect) PDC loads last byte
MSB
MSBMSB MSB
LSBLSB
LSB
LSB
SAM4S Series [DATASHEET]
Atmel-11100K-ATARM-SAM4S-Datasheet_09-Jun-15
698
Delay between consecutive transfers—independently programmable for each chip select by writing the
DLYBCT field. The time required by the SPI slave device to process received data is managed through
DLYBCT. This time depends on the SPI slave system activity.
These delays allow the SPI to be adapted to the interfaced peripherals and their speed and bus release time.
Figure 33-10. P rogrammable Delays
33.7.3.5 Peripheral Selection
The serial peripherals are selected through the assertion of the NPCS0 to NPCS3 signals. By default, all NPCS
signals are high before and after each transfer.
Fixed Peripheral Select Mode: SPI exchanges data with only one peripheral.
Fixed peripheral select mode is en abled by writing the PS bit to zero in the SPI_MR. In this case, the current
peripheral is defined by the PCS field in the SPI_MR and the PCS field in the SPI_TDR has no effect.
Variable Peripheral Select Mode: Data can be exchanged with mo re than one peripher al without havin g to
reprogram the NPCS field in the SPI_MR.
Variable peripheral select mode is enabled by setting the PS bit to 1 in the SPI_MR. The PCS field in the
SPI_TDR is used to select the current peripheral. This means that the peripheral selection can be d efined for
each new data. The v alue to write in the SPI_TDR has the following format:
[xxxxxxx(7-bit) + LASTXFER(1-bit)(1)+ xxxx(4-bit) + PCS (4-bit) + DATA (8 to 16-bit)] with PCS equals the
chip select to assert, as defined in Sectio n 33.8.4 “SPI Transmit Data Register” and LASTXFER bit at 0 or 1
depending on the CSAAT bit.
Note: 1. Optional
CSAAT, LASTXFER and CSNAAT bits are discussed in Section 33.7.3.9 “Peripheral Deselection with PDC”.
If LASTXFER is used, the command must be issued after writing the last character. Instead of LASTXFER,
the user can use the SPIDIS command. After the end of the PDC transfer, it is necessary to wait for the
TXEMPTY flag and then write SPIDIS into the SPI Control Register (SPI_CR). This does not change the
configuration register values). The NPCS is disabled after the last character transfer. Then, another PDC
transfer can be started if the SPIEN has previously been written in the SPI_CR.
33.7.3.6 SPI Peripheral DMA Controller (PDC)
In both Fixed and Variable peripheral select modes, the Peripheral DMA Controller (PDC) can be used to reduce
processor overhead.
The fixed peripheral selection allows buffer transfers with a single peripheral. Using the PDC is an optimal means,
as the size of the data transfer between the memory and the SPI is either 8 bits or 16 bits. However, if the
peripheral selection is modified, the SPI_MR must be reprogrammed.
DLYBCS DLYBS DLYBCT DLYBCT
Chip Select 1
Chip Select 2
SPCK
699
SAM4S Series [DATASHEET]
Atmel-11100K-ATARM-SAM4S-Datasheet_09-Jun-15
The variable peripheral selection allows bu ffer transfers with multiple peripherals without reprogramming the
SPI_MR. Data written in the SPI_TDR is 32 bits wide and defines the real data to be transmitted and the
destination peripheral. Using the PDC in this mode req uires 32 -bit wide buffers, with the data in the LSBs an d the
PCS and LASTXFER fields in the MSBs. However, the SPI still controls the number of bits (8 to16) to be
transferred through MISO and MOSI lines with the chip select configuration registers (SPI_CSRx). This is not the
optimal means in terms of memory si ze for the buffers, but it provides a very effective means to exchange data
with several peripherals without any intervention of the processor.
Transfer Size
Depending on the data size to transmit, from 8 to 16 bits, the PDC manages automatically t he type of pointer size
it has to point to. The PDC performs the following transfer, de pending on the mode and number of bits per data.
Fixed mode:
8-bit data:
1-Byte transfer, PDC pointer address = address + 1 byte,
PDC counter = counter - 1
9-bit to 16-bit data:
2-Byte transfer. n-bit data transfer with don’t care data (MSB) filled with 0’s,
PDC pointer address = address + 2 bytes,
PDC counter = counter - 1
Variable mode:
In Variable mode, PDC pointer a ddr ess = addr ess +4 byte s and PDC cou nter = counter - 1 fo r 8 to 16-
bit transfer size.
When using the PDC, the TDRE and RDRF flags are handled by the PDC. The user’s application
does not have to check th ese bit s. Only End of RX Buf fer (ENDRX), End of TX Buf fer (ENDTX), Buf fer
Full (RXBUFF), TX Buffer Empty (TXBUFE) are significant. For further details about the Peripheral
DMA Controller and user interface, refer to the PDC section of the product datasheet.
33.7.3.7 Peripheral Chip Select Decoding
The user can program the SPI to operate with up to 15 slave peripherals by decoding the four chip select lines,
NPCS0 to NPCS3 with an external decoder/demultipl exer (refer to Figure 33-11). This can be enabled by writing a
1 to the PCSDEC bit in the SPI_MR.
When oper ating without de coding, the SPI makes sure th at in any case only one chip select line is activated, i.e.,
one NPCS line driven low at a time. If two bits ar e defined lo w in a PCS field, only the lowest numbered chip select
is driven low.
When operating with d ecoding, the SPI directly outputs the value defined by the PCS field on the NPCS lines of
either SPI_MR or SPI_TDR (depending on PS).
As the SPI sets a default value of 0xF on the chip select lines (i.e., all chip select lines at 1) wh en not process ing
any transfer, only 15 peripherals can be decoded.
The SPI has four Chip Select registers. As a result, when external decoding is activated, each NPCS chip select
defines the characteristics of up to four peripherals. As an example, SPI_CRS0 defines the characteristics of the
externally decoded peripherals 0 to 3, corresponding to the PCS values 0x0 to 0x3. Consequently, the user has to
make sure to connect compatible peripherals on the de coded chip select lines 0 to 3, 4 to 7, 8 to 11 and 12 to 14.
Figure 33-11 shows this type of implementation.
If the CSAAT bit is used, with or without the PDC, the Mode Fault detection for NPCS0 line must be disabled. This
is not required for all ot he r chip select lines since mode fault detection is only on NPCS0.
SAM4S Series [DATASHEET]
Atmel-11100K-ATARM-SAM4S-Datasheet_09-Jun-15
700
Figure 33-11. Chip Select Decoding Application Block Diagram: Single Master/Multiple Slave Implementation
33.7.3.8 Peripheral Deselection without PDC
During a transfer of more than one unit of data on a Chip Select without the PDC, the SPI_TDR is loaded by the
processor, the TDRE flag rises as soon as the content of the SPI_TDR is transferred into the internal Shift register.
When this flag is detected h igh, the SPI_TDR can be reloaded. If this reload by the processor oc curs before the
end of the current transfer and if the next transfer is performed on the same chip select as the current tr ansfer, the
Chip Select is not de-asserted between the two transfers. But depending on the application software handling the
SPI status register flags (by interrupt or polling method) or servicing other interrupts or other tasks, the processor
may not reload the SPI_TDR in time to keep the chip select active (low). A null DLYBCT value (delay between
consecutive transfers) in the SPI_CSR, gives even less time for the processor to reload the SPI_TDR. With some
SPI slave peripherals, if the chip select line must remain active (low) during a full set of transfers, communication
errors can occur.
To facilitate interfacing with such devices, the Chip Select registers [CSR0...CSR3] can be programmed with the
Chip Select Active After Transfer (CSAAT) bit to 1. This allows the chip select lines to remain in their current state
(low = active) until a transfer to another chip sele ct is required. Even if the SPI_TDR is not reloaded, the ch ip select
remains active. To de-assert the chip select line at the end of the transfer, the Last Transfer (LASTXFER) bit in
SPI_CR must be set after writing the last data to transmit into SP I_TD R.
33.7.3.9 Peripheral Deselection with PDC
PDC provides faster reloads of the SPI_TDR compared to software. However, depending on the system activity, it
is not guaranteed that the SPI_TDR is written with the next data before the end of the current transfer.
Consequently, data can be lost by the de-assertion of the NPCS line for SPI slave peripherals requiring the chip
select line to remain active between two transfer s. The only way to guaran tee a safe transfer in this case is the use
of the CSAAT and LASTXFER bits.
When the CSAAT bit is configured to 0, the NPCS does not rise in all cases between two transfers on the same
peripheral. During a tra nsfer on a Chip Select, the TDRE flag rises as soon as the conten t of the SPI_TDR is
transferred into the internal shift register. When this flag is detected, the SPI_TDR can be reloaded. If this reload
occurs before the end of the current transfer and if the next transfer is performed on the same chip select as the
current transfer, the Chip Select is not de-asserted between the two transfers. This can lead to difficulties to
interface with some serial peripherals requiring th e chip select to be de-asserted after each transfer. To facilitate
SPI Master
SPCK
MISO
MOSI
NPCS0
NPCS1
NPCS2
SPCK MISO MOSI
NSS
Slave 0
SPCK MISO MOSI
NSS
Slave 1
SPCK MISO MOSI
NSS
Slave 14
NPCS3
Decoded chip select lines
External 1-of-n Decoder/Demultiplexer
701
SAM4S Series [DATASHEET]
Atmel-11100K-ATARM-SAM4S-Datasheet_09-Jun-15
interfacing with such devices, the SPI_CSR can be programmed with the Chip Select Not Active After Transfer
(CSNAAT) bit to 1. This allows the chip select lines to be de-asserted systematically during a time “DLYBCS” (the
value of the CSNAAT bit is processed only if the CSAAT bit is configured to 0 for the same chip select).
Figure 33-12 shows different peripheral deselection cases and the effect of the CSAAT and CSNAAT bits.
Figure 33-12. Peripheral Deselection
33.7.3.10 Mode Fault Detection
The SPI has the capability to operate in multi-master environment. Consequently, the NPCS0/NSS line must be
monitored. If one of the masters on the SPI bus is currently transm itting, the NPCS0/NSS line is low and the SPI
must not transmit any data. A mode fault is detected when the SPI is programmed in Master mode and a low level
A
NPCS[0..n]
Write SPI_TDR
TDRE
NPCS[0..n]
Write SPI_TDR
TDRE
NPCS[0..n]
Write SPI_TDR
TDRE
DLYBCS
PCS = A
DLYBCS
DLYBCT
A
PCS = B
B
DLYBCS
PCS = A
DLYBCS
DLYBCT
A
PCS = B
B
DLYBCS
DLYBCT
PCS=A
ADLYBCS
DLYBCT
A
PCS = A
AA
DLYBCT
AA
CSAAT = 0 and CSNAAT = 0
DLYBCT
AA
CSAAT = 1 and CSNAAT= 0 / 1
A
DLYBCS
PCS = A
DLYBCT
AA
CSAAT = 0 and CSNAAT = 1
NPCS[0..n]
Write SPI_TDR
TDRE
PCS = A
DLYBCT
AA
CSAAT = 0 and CSNAAT = 0
SAM4S Series [DATASHEET]
Atmel-11100K-ATARM-SAM4S-Datasheet_09-Jun-15
702
is driven by an exter nal master on the NPCS0 /NSS signal. In mu lti-master en vironment, NPCS0, MOSI, MISO and
SPCK pins must be configured in open drain (through the PIO controller). When a mode fault is detected, the
SPI_SR.MODF bit is set until SPI_SR is read and the SPI is automatically disabled until it is re-enabled by writing
a 1 to the SPI_CR.SPIEN bit.
By default, the mode fault detection is enabled. The user can disab le it by setting the SPI_MR.MODFDIS bit.
33.7.4 SPI Slave Mode
When operating in Slave mode, the SPI processes data bits on the clock provided on the SPI clock pin (SPCK).
The SPI waits until NSS goes active before receiving the serial clock fr om an extern al master. Whe n NSS falls, the
clock is validate d and th e data is loaded in the SPI_RDR depe nding on the BITS field configure d in the SPI_CSR0.
These bits are pro cessed following a phase and a p olarity defined respec tively by the NCPHA and CPOL bits in
the SPI_CSR0. Note that BITS, CPOL and NCPHA of the other Chip Select registers have no effect when the SPI
is programmed in Slave mode.
The bits are shifted out on the MISO line and sampled on the MOSI line.
Note: For mo re information on the BITS field, see also the note below the SPI_CSRx re gister bitmap (Section 33.8.9 “SPI
Chip Select Register”).
When all bits are processed, the received data is transferred in the SPI_RDR and the RDRF bit rises. If the
SPI_RDR has n ot been read be fore n ew data is r eceived , the Overrun Error Status (OVRES) bit in the SPI_SR is
set. As long as this flag is set, data is loaded in the SPI_RDR. The user must r ead SPI_SR to clear th e OVRES b it.
When a transfer starts, the data shifted out is the data present in the Shift register. If no data has been written in
the SPI_TDR, the last data received is transferred. If no data has been received since the last reset, all bits are
transmitted low, as the Shift register resets to 0.
When a first data is written in the SPI_TDR, it is transferred immediately in the Shift register and the TDRE flag
rises. If new data is written, it remains in the SPI_TDR until a transfer occurs, i.e., N SS falls and there is a valid
clock on the SPCK pin. When the transfer occurs, the last data written in the SPI_T DR is transferred in the Shift
register and the TDRE flag rises. This enables frequent updates of critical va riables with single transfers.
Then, new data is loaded in the Shift register from the SPI_TDR. If no character is ready to be transmitted, i.e., no
character has been written in the SPI_TDR since the last load from the SPI_TDR to the Shift register, the
SPI_TDR is retransmitted. In this case the Underrun Error Status Flag (UNDES) is set in the SPI_SR.
Figure 33-13 shows a block diagram of the SPI when operating in Slave mode.
Figure 33-13. Slave Mode Functional Block Diagram
Shift Register
SPCK
SPIENS
LSB MSB
NSS
MOSI
SPI_RDR RD
SPI
Clock
TDRE
SPI_TDR TD
RDRF
OVRES
SPI_CSR0
CPOL
NCPHA
BITS
SPIEN
SPIDIS
MISO
703
SAM4S Series [DATASHEET]
Atmel-11100K-ATARM-SAM4S-Datasheet_09-Jun-15
33.7.5 Register Write Protection
To prevent any single softwa re error from corrupting SPI behavior, certain registers in the address space can be
write-protected by setting the WPEN bit in the SPI Write Protection Mode Register (SPI_WPMR).
If a write access to a write-protected register is detected, the WPVS flag in the SPI Write Protection Status
Register (SPI_WPSR) is set and the WPVSRC field indicates the register in which the write access has been
attempted.
The WPVS bit is automatically cleared after reading SPI_WPSR.
The following registers can be write-protected:
SPI Mode Register
SPI Chip Select Register
SAM4S Series [DATASHEET]
Atmel-11100K-ATARM-SAM4S-Datasheet_09-Jun-15
704
33.8 Serial Peripheral Interface (SPI) User Interface
Table 33-5 . Register Mapping
Offset Register Name Access Rese t
0x00 Control Register SPI_CR Write-only –
0x04 Mode Register SPI_MR Read/Write 0x0
0x08 Receive Data Register SPI_RDR Read-only 0x0
0x0C Transmit Data Register SPI_TDR Write-only –
0x10 Status Register SPI_SR Read-only 0x000000F0
0x14 Interrupt Enable Register SPI_IER Write-only –
0x18 Interrupt Disable Register SPI_IDR Write-only –
0x1C Interrupt Mask Register SPI_IMR Read-only 0x0
0x20–0x2C Reserved – – –
0x30 Chip Select Register 0 SPI_CSR0 Read/Write 0x0
0x34 Chip Select Register 1 SPI_CSR1 Read/Write 0x0
0x38 Chip Select Register 2 SPI_CSR2 Read/Write 0x0
0x3C Chip Select Register 3 SPI_CSR3 Read/Write 0x0
0x40–0xE0 Reserved – – –
0xE4 Write Protection Mode Register SPI_WPMR Read/Write 0x0
0xE8 Write Protection Status Register SPI_WPSR Read-only 0x0
0xEC–0xF8 Reserved – – –
0xFC Reserved – – –
0x100–0x124 Reserved for PDC Registers – – –
705
SAM4S Series [DATASHEET]
Atmel-11100K-ATARM-SAM4S-Datasheet_09-Jun-15
33.8.1 SPI Control Register
Name: SPI_CR
Address: 0x40008000
Access: Write-only
• SPIEN: SPI Enable
0: No effect.
1: Enables the SPI to transfer and receive data.
• SPIDIS: SPI Disable
0: No effect.
1: Disables the SPI.
All pins are set in Input mode after completion of the transmission in progress, if any.
If a transfer is in progress when SPIDIS is set, the SPI completes the transmission of the shifter register an d does not start
any new transfer, even if the SPI_THR is loaded.
Note: If both SPIEN and SPIDIS are equal to one when the SPI_CR is written, the SPI is disabled.
• SWRST: SPI Software Reset
0: No effect.
1: Reset the SPI. A software-triggered hardware reset of the SPI interface is performed.
The SPI is in Slave mode after software reset.
PDC channels are not affected by software reset.
• LASTXFER: Last Transfer
0: No effect.
1: The current NPCS is de-asserted after the character written in TD has been transferred. When SPI_CSRx.CSAAT is set,
the communication with the curr ent serial peripher al can be closed by r aising the co rr espondin g NPCS line as soon as TD
transfer is completed.
Refer to Section 33.7.3.5 “Peripheral Selection” for more details.
31 30 29 28 27 26 25 24
–––––––LASTXFER
23 22 21 20 19 18 17 16
––––––––
15 14 13 12 11 10 9 8
––––––––
76543210
SWRST–––––SPIDISSPIEN
SAM4S Series [DATASHEET]
Atmel-11100K-ATARM-SAM4S-Datasheet_09-Jun-15
706
33.8.2 SPI Mode Register
Name: SPI_MR
Address: 0x40008004
Access: Read/Write
This register can only be written if the WPEN bit is cleared in the SPI Write Protection Mode Register.
• MSTR: Master/Slave Mode
0: SPI is in Slave mode
1: SPI is in Master mode
• PS: Peripheral Select
0: Fixed Peripheral Select
1: Variable Peripheral Select
• PCSDEC: Chip Select Decode
0: The chip selects are directly connected to a peripheral device.
1: The four NPCS chip select lines are connected to a 4-bit to 16-bit decoder.
When PCSDEC = 1, up to 15 Chip Select signals can be generated with the four NPCS lines using an external 4-bit to 16-
bit decoder. The Chip Select registers define the characteristics of the 15 chip selects, with the following rules:
SPI_CSR0 defines peripheral chip select signals 0 to 3.
SPI_CSR1 defines peripheral chip select signals 4 to 7.
SPI_CSR2 defines peripheral chip select signals 8 to 11.
SPI_CSR3 defines peripheral chip select signals 12 to 14.
• MODFDIS: Mode Fault Detection
0: Mode fault detection enabled
1: Mode fault detection disabled
• WDRBT: Wait Dat a Read Before Transfer
0: No Effect. In Master mode, a transfer can be initiated regardless of the SPI_RDR state.
1: In Master mode, a transfer can start only if the SPI_RDR is empty, i.e., does not contain any unread data. This mode
prevents overrun error in reception.
31 30 29 28 27 26 25 24
DLYBCS
23 22 21 20 19 18 17 16
–––– PCS
15 14 13 12 11 10 9 8
––––––––
76543210
LLB – WDRBT MODFDIS – PCSDEC PS MSTR
707
SAM4S Series [DATASHEET]
Atmel-11100K-ATARM-SAM4S-Datasheet_09-Jun-15
• LLB: Local Loopback Enable
0: Local loopback path disabled.
1: Local loopback path enabled.
LLB controls the local loopback on the data shift register for testing in Master mode only (MISO is internally connected on
MOSI).
• PCS: Peripheral Chip Select
This field is only used if fixed peripheral select is active (PS = 0).
If SPI_MR.PCSDEC = 0:
PCS = xxx0 NPCS[3:0] = 1110
PCS = xx01 NPCS[3:0] = 1101
PCS = x011 NPCS[3:0] = 1011
PCS = 0111 NPCS[3:0] = 0111
PCS = 1111 forbidden (no peripheral is selected)
(x = don’t care)
If SPI_MR.PCSDEC = 1:
NPCS[3:0] output signals = PCS.
• DLYBCS: Delay Between Chip Selects
This field defines the delay between the inactivation and the activation of NPCS. The DLYBCS time guara ntees non- ov er -
lapping chip selects and solves bus contentions in case of peripherals having long data float times.
If DLYBCS is lower than 6, six peripheral clock periods are inserted by default.
Otherwise, the following equation determines the delay:
Delay Between Chip Selects DLYBCS
fperipheral clock
---------------------------------
=
SAM4S Series [DATASHEET]
Atmel-11100K-ATARM-SAM4S-Datasheet_09-Jun-15
708
33.8.3 SPI Receive Data Register
Name: SPI_RDR
Address: 0x40008008
Access: Read-only
• RD: Receive Data
Data received by the SPI Interface is stored in this register in a right-justified format. Unused bits are read as zero.
• PCS: Peripheral Chip Select
In Master mode on ly, these bits indicate th e value on the NPCS pins at the end of a tra nsfer. Otherwise, these bits are read
as zero.
Note: When using Variable peripheral select mode (PS = 1 in SPI_MR), it is mandatory to set the SPI_MR.WD RBT bit to 1 if the PCS
field must be processed in SPI_RDR.
31 30 29 28 27 26 25 24
––––––––
23 22 21 20 19 18 17 16
–––– PCS
15 14 13 12 11 10 9 8
RD
76543210
RD
709
SAM4S Series [DATASHEET]
Atmel-11100K-ATARM-SAM4S-Datasheet_09-Jun-15
33.8.4 SPI Transmit Data Register
Name: SPI_TDR
Address: 0x4000800C
Access: Write-only
• TD: Transmit Data
Data to be transmitted by the SPI Interface is stored in this register. Information to be transmitted must be written to the
transmit data register in a right-justified format.
• PCS: Peripheral Chip Select
This field is only used if variable peripheral select is active (PS = 1).
If SPI_MR.PCSDEC = 0:
PCS = xxx0 NPCS[3:0] = 1110
PCS = xx01 NPCS[3:0] = 1101
PCS = x011 NPCS[3:0] = 1011
PCS = 0111 NPCS[3:0] = 0111
PCS = 1111 forbidden (no peripheral is selected)
(x = don’t care)
If SPI_MR.PCSDEC = 1:
NPCS[3:0] output signals = PCS.
• LASTXFER: Last Transfer
0: No effect
1: The current NPCS is de-asserted after the transfer of the charac ter written in TD. When SPI_CSRx.CSAAT is set, the
communication with the current serial peripheral can be closed by raising the corresponding NPCS line as soon as TD
transfer is completed.
This field is only used if variable peripheral select is active (SPI_MR.PS = 1).
31 30 29 28 27 26 25 24
–––––––LASTXFER
23 22 21 20 19 18 17 16
–––– PCS
15 14 13 12 11 10 9 8
TD
76543210
TD
SAM4S Series [DATASHEET]
Atmel-11100K-ATARM-SAM4S-Datasheet_09-Jun-15
710
33.8.5 SPI Status Register
Name: SPI_SR
Address: 0x40008010
Access: Read-only
• RDRF: Receive Data Register Full (cleared by reading SPI_RDR)
0: No data has been received since the last read of SPI_RDR.
1: Data has been received and the received data has been transferred from the shift register to SPI_RDR since the last
read of SPI_RDR.
• TDRE: Transmit Data Register Empty (cleared by writing SPI_TDR)
0: Data has been written to SPI_TDR and not yet transferred to the shift register.
1: The last data wr itten in the SPI_ TD R has been transferred to the shift register.
TDRE equals zero when the SPI is disabled or at reset. The SPI enable command sets this bit to 1.
• MODF: Mode Fault Error (cleared on read)
0: No mode fault has be en de te cte d sin ce th e las t rea d of SPI_SR .
1: A mode fault occurred since the last read of SPI_SR.
• OVRES: Overrun Error Status (cleared on read)
0: No overrun ha s be en de tec te d sin ce th e last rea d of SPI_SR .
1: An overrun has occurred since the last read of SPI_SR.
An overrun occurs when SPI_RDR is loaded at least twice from the shift register since the la st read of the SPI_RDR.
• ENDRX: End of RX Buffer (cleared by writing SPI_RCR or SPI_RNCR)
0: The Receive Counter register has not reached 0 since the last write in SPI_RCR(1) or SPI_RNCR(1).
1: The Receive Coun te r re gis te r ha s reached 0 since the last write in SPI_RCR(1) or SPI_RNCR(1).
• ENDTX: End of TX Buffer (cleared by writing SPI_TCR or SPI_TNCR)
0: The Transmit Counter register has not reached 0 since the last write in SPI_TCR(1) or SPI_TNCR(1).
1: The Transmit Counter register has reached 0 since the last write in SPI_TCR(1) or SPI_TNCR(1).
• RXBUFF: RX Buffer Full (cleared by writing SPI_RCR or SPI_RNCR)
0: SPI_RCR(1) or SPI_RNCR(1) has a value other than 0.
1: Both SPI_RCR(1) and SPI_RNCR(1) have a value of 0.
31 30 29 28 27 26 25 24
––––––––
23 22 21 20 19 18 17 16
–––––––SPIENS
15 14 13 12 11 10 9 8
–––––UNDES TXEMPTY NSSR
76543210
TXBUFE RXBUFF ENDTX ENDRX OVRES MODF TDRE RDRF
711
SAM4S Series [DATASHEET]
Atmel-11100K-ATARM-SAM4S-Datasheet_09-Jun-15
• TXBUFE: TX Buffer Empty (cleared by writing SPI_TCR or SPI_TNCR)
0: SPI_TCR(1) or SPI_TNCR (1) has a value other than 0.
1: Both SPI_TCR(1) and SPI_ T NCR (1) have a value of 0.
• NSSR: NSS Rising (cleared on read)
0: No rising edge detected on NSS pin since the last read of SPI_SR.
1: A rising edge occurred on NSS pin since the last read of SPI_SR.
• TXEMPTY: Transmission Registers Empty (cleared by writing SPI_TDR)
0: As soon as data is written in SPI_TDR.
1: SPI_TDR and internal shift r egister are empty. If a transfer delay has been defined, TXEMPTY is set after the e nd of this
delay.
• UNDES: Underrun Error Status (Slave mode only) (cleared on read)
0: No underrun has been detected since the last read of SPI_SR.
1: A transfer starts whereas no data has been loaded in SPI_TDR.
• SPIENS: SPI Enable Status
0: SPI is disabled.
1: SPI is enabled.
Note: 1. SPI_RCR, SPI_RNCR, SPI_TCR, SPI_TNCR are PDC registers.
SAM4S Series [DATASHEET]
Atmel-11100K-ATARM-SAM4S-Datasheet_09-Jun-15
712
33.8.6 SPI Interrupt Enable Register
Name: SPI_IER
Address: 0x40008014
Access: Write-only
The following configuration values are valid for all listed bit names of this register:
0: No effect.
1: Enables the corresponding interrupt.
• RDRF: Receive Data Register Full Interrupt Enable
• TDRE: SPI Transmit Data Register Empty Interrupt Enable
• MODF: Mode Fault Error Interrupt Enable
• OVRES: Overrun Error Interrupt Enable
• ENDRX: End of Receive Buffer Interrupt Enable
• ENDTX: End of Transmit Buffer Interrupt Enable
• RXBUFF: Receive Buffer Full Interrupt Enable
• TXBUFE: Transmit Buffer Empty Interrupt Enable
• NSSR: NSS Rising Interrupt Enable
• TXEMPTY: Transmission Registers Empty Enable
• UNDES: Underrun Error Interrupt Enable
31 30 29 28 27 26 25 24
––––––––
23 22 21 20 19 18 17 16
––––––––
15 14 13 12 11 10 9 8
–––––UNDES TXEMPTY NSSR
76543210
TXBUFE RXBUFF ENDTX ENDRX OVRES MODF TDRE RDRF
713
SAM4S Series [DATASHEET]
Atmel-11100K-ATARM-SAM4S-Datasheet_09-Jun-15
33.8.7 SPI Interrupt Disable Register
Name: SPI_IDR
Address: 0x40008018
Access: Write-only
The following configuration values are valid for all listed bit names of this register:
0: No effect.
1: Disables the corresponding interrupt.
• RDRF: Receive Data Register Full Interrupt Disable
• TDRE: SPI Transmit Data Register Empty Interrupt Disable
• MODF: Mode Fault Error Interrupt Disable
• OVRES: Overrun Error Interrupt Disable
• ENDRX: End of Receive Buffer Interrupt Disable
• ENDTX: End of Transmit Buffer Interrupt Disable
• RXBUFF: Receive Buffer Full Interrupt Disable
• TXBUFE: Transmit Buffer Empty Interrupt Disable
• NSSR: NSS Rising Interrupt Disable
• TXEMPTY: Transmission Registers Empty Disable
• UNDES: Underrun Error Interrupt Disable
31 30 29 28 27 26 25 24
––––––––
23 22 21 20 19 18 17 16
––––––––
15 14 13 12 11 10 9 8
–––––UNDES TXEMPTY NSSR
76543210
TXBUFE RXBUFF ENDTX ENDRX OVRES MODF TDRE RDRF
SAM4S Series [DATASHEET]
Atmel-11100K-ATARM-SAM4S-Datasheet_09-Jun-15
714
33.8.8 SPI Interrupt Mask Register
Name: SPI_IMR
Address: 0x4000801C
Access: Read-only
The following configuration values are valid for all listed bit names of this register:
0: The corresponding interrupt is not enabled.
1: The corresponding interrupt is enabled.
• RDRF: Receive Data Register Full Interrupt Mask
• TDRE: SPI Transmit Data Register Empty Interrupt Mask
• MODF: Mode Fault Error Interrupt Mask
• OVRES: Overrun Error Interrupt Mask
• ENDRX: End of Receive Buffer Interrupt Mask
• ENDTX: End of Transmit Buffer Interrupt Mask
• RXBUFF: Receive Buffer Full Interrupt Mask
• TXBUFE: Transmit Buffer Empty Interrupt Mask
• NSSR: NSS Rising Interrupt Mask
• TXEMPTY: Transmission Registers Empty Mask
• UNDES: Underrun Error Interrupt Mask
31 30 29 28 27 26 25 24
––––––––
23 22 21 20 19 18 17 16
––––––––
15 14 13 12 11 10 9 8
–––––UNDES TXEMPTY NSSR
76543210
TXBUFE RXBUFF ENDTX ENDRX OVRES MODF TDRE RDRF
715
SAM4S Series [DATASHEET]
Atmel-11100K-ATARM-SAM4S-Datasheet_09-Jun-15
33.8.9 SPI Chip Select Register
Name: SPI_CSRx[x=0..3]
Address: 0x40008030
Access: Read/Write
This register can only be written if the WPEN bit is cleared in the SPI Write Protection Mode Register.
Note: SPI_CSRx registers must be w ri tt en e v en i f th e user wants to use the default reset values. The BITS field is not updated with the
translated value unless the register is written.
• CPOL: Clock Polarity
0: The inactive state value of SPCK is logic level zero.
1: The inactive state value of SPCK is logic level one.
CPOL is used to determine the inactive state value of the serial clock (SPCK). It is used with NCPHA to produce the
required cloc k/d a ta re lat ion sh ip between master and slave devices.
• NCPHA: Clock Phase
0: Data is changed on the leading edge of SPCK and captured on the following edge of SPCK.
1: Data is captured on the leading edge of SPCK and changed on the following edge of SPCK.
NCPHA determines which edge of SPCK causes data to change and which edge causes data to be captured. NCPHA is
used with CPOL to produce the required clock/data relationship between master and slave devices.
• CSNAAT: Chip Select Not Active After Transfer (Ignored if CSAAT = 1)
0: The Peripheral Chip Select does not rise between two transfers if the SPI_TDR is reloaded before the end of the first
transfer and if the two transfers occur on the same Chip Select.
1: The Peripheral Chip Select rises systematically after each transfer performed on the same slave. It remains inactive
after the end of transfer for a minimal duration of:
• CSAAT: Chip Select Active After Transfer
0: The Peripheral Chip Select Line rises as soon as the last transfer is achieved.
1: The Peripheral Chip Select does not rise after the last transfer is achieved. It remains active until a new transfer is
requested on a different chip select.
• BITS: Bits Per Transfer
(See the note below the register bitmap.)
31 30 29 28 27 26 25 24
DLYBCT
23 22 21 20 19 18 17 16
DLYBS
15 14 13 12 11 10 9 8
SCBR
76543210
BITS CSAAT CSNAAT NCPHA CPOL
(If field DLYBCS is lower than 6, a minimum of six periods is introduced.)
DLYBCS
fperipheral clock
---------------------------------
SAM4S Series [DATASHEET]
Atmel-11100K-ATARM-SAM4S-Datasheet_09-Jun-15
716
The BITS field determines the number of data bits transferred. Reserved values should not be used.
• SCBR: Serial Clock Bit Rate
In Master mode, the SPI Interface uses a modulus counter to derive the SPCK bit rate from the peripheral clock. The bit
rate is selected by writing a value from1 to 255 in the SCBR field. The following equation determines the SPCK bit rate:
SCBR = fperipheral clock / SPCK Bit Rate
Programming the SCBR field to 0 is forbidden. Triggering a transfer while SCBR is at 0 can lead to unpredictable results.
If BRSRCCLK = 1 in SPI_MR, SCBR must be programmed with a value greater than 1.
At reset, SCBR is 0 and the user has to program it at a valid value before performing the first transfer.
Note: If one of the SCBR fields in SPI_CSRx is set to 1, the other SCBR fields in SPI_CSRx must be set to 1 as well, if they are used to
process transfers. If they are not used to transfer data, they can be set at any value.
• DLYBS: Delay Before SPCK
This field defines the delay from NPCS falling edge (activation) to the first valid SPCK transition.
When DLYBS = 0, the delay is half the SPCK clock period.
Otherwise, the following equation determines the delay:
DLYBS = Delay Before SPCK × fperipheral clock
• DLYBCT: Delay Between Consecutive Transfers
This field defines the delay between two consecutive transfers with the same peripheral without removing the chip select.
The delay is always inserted after each transfer and before removing the chip select if needed.
When DLYBCT = 0, no delay between consecutive transfers is inserted and the clock keeps its duty cycle over the charac-
ter transfers.
Otherwise, the following equation determines the delay:
DLYBCT = Delay Between Consecutive Transfers × fperipheral clock / 32
Value Name Description
0 8_BIT 8 bits for transfer
1 9_BIT 9 bits for transfer
2 10_BIT 10 bits for transfer
3 11_BIT 11 bits for transfer
4 12_BIT 12 bits for transfer
5 13_BIT 13 bits for transfer
6 14_BIT 14 bits for transfer
7 15_BIT 15 bits for transfer
8 16_BIT 16 bits for transfer
9– Reserved
10 – Reserved
11 – Reserved
12 – Reserved
13 – Reserved
14 – Reserved
15 – Reserved
717
SAM4S Series [DATASHEET]
Atmel-11100K-ATARM-SAM4S-Datasheet_09-Jun-15
33.8.10 SPI Write Protection Mode Register
Name: SPI_WPMR
Address: 0x400080E4
Access: Read/Write.
• WPEN: Write Protec ti on Ena b le
0: Disables the write protection if WPKEY corresponds to 0x535049 (“SPI” in ASCII)
1: Enables the write protection if WPKEY corresponds to 0x535049 (“SPI” in ASCII)
See Section 33.7.5 “Register Write Protection” for the list of registers that can be write-protected.
• WPKEY: Write Protection Key
31 30 29 28 27 26 25 24
WPKEY
23 22 21 20 19 18 17 16
WPKEY
15 14 13 12 11 10 9 8
WPKEY
76543210
–––––––WPEN
Value Name Description
0x535049 PASSWD Writing any other value in this field aborts the write operation of the WPEN bit.
Always reads as 0.
SAM4S Series [DATASHEET]
Atmel-11100K-ATARM-SAM4S-Datasheet_09-Jun-15
718
33.8.11 SPI Write Protection Status Register
Name: SPI_WPSR
Address: 0x400080E8
Access: Read-only
• WPVS: Write Protection Violation Status
0: No write protection violation has occurred since the last read of SPI_WPSR.
1: A write protection violation has occurre d sin ce the last r ead of SPI_WPSR. If this violation is an unautho rized attempt to
write a protected register, the associated violation is reported into field WPVSRC.
• WPVSRC: Write Protection Violation Source
When WPVS = 1, WPVSRC indicates the register address offset at which a write access has been attempted.
31 30 29 28 27 26 25 24
––––––––
23 22 21 20 19 18 17 16
––––––––
15 14 13 12 11 10 9 8
WPVSRC
76543210
–––––––WPVS
719
SAM4S Series [DATASHEET]
Atmel-11100K-ATARM-SAM4S-Datasheet_09-Jun-15
34. Two-wire Interface (TWI)
34.1 Description
The Atmel Two-wire Interface (TWI) interconnects components on a unique two-wire bus, made up of one clock
line and one data line with speeds of up to 400 Kbits per second, based on a byte-oriented transfer format. It can
be used with any Atmel Two-wire Interface bus Serial EEPROM and I²C compatible device such as a Real Time
Clock (RTC), Dot Matrix/Graphic LCD Controllers and temperature sensor. The TWI is programmable as a master
or a slave with sequential or single-byte access. Multiple master capability is supported.
A configurable baud rate g enerator permits the output data rate to be adapted to a wide range of core clock
frequencies.
Table 34-1 lists the compatibility level of the Atmel Two-wire Interface in Master mode and a full I2C compatible
device.
Note: 1. START + b000000001 + Ack + Sr
34.2 Embedded Characteristics
Compatible with Atmel Two-wire Interface Serial Memory and I²C Compatible Devices(1)
One, Two or Three Bytes for Slave Address
Sequential Read/Write Operations
Master, Multi-master and Slave Mode Operation
Bit Rate: Up to 400 Kbit/s
General Call Supported in Slave Mode
SMBus Quick Command Supported in Master Mode
Connection to Peripheral DMA Controller (PDC) Channel Capabilities Optimizes Data Transfers
One Channel for the Receiver, One Channel for the Transmitter
Note: 1. See Table 34-1 for details on compatibility with I²C Standard.
Table 34-1. Atmel TWI Compatibility with I2C Standard
I2C Standard Atmel TWI
Standard Mode S peed (100 kHz) Supported
Fast Mode Speed (400 kHz) Supported
7- or 10-bit Slave Addressing Supported
START byte(1) Not Supported
Repeated Start (Sr) Condition Supported
ACK and NACK Management Supported
Slope Control and Input Filte ri ng (Fast mode) Not Supported
Clock Stretching/Synchronization Supported
Multi Master Capability Supported
SAM4S Series [DATASHEET]
Atmel-11100K-ATARM-SAM4S-Datasheet_09-Jun-15
720
34.3 List of Abbreviations
34.4 Block Diagram
Figure 34-1. Block Diagram
34.5 I/O Lines Description
Table 34-2. Abbreviations
Abbreviation Description
TWI Two-wire Interface
A Acknowledge
NA Non Acknowledge
PStop
SStart
Sr Repeated Start
SADR Slave Address
ADR Any addre s s except SADR
RRead
WWrite
Peripheral Bridge
PMC
Peripheral
clock Two-wire Interface
PIO
Interrupt
Controller
TWI
Interrupt
TWCK
TWD
Bus clock
Table 34-3. I/O Lines Description
Name Description Type
TWD Two-wire Serial Data (drives external serial data line – SDA) Input/Output
TWCK Two-wire Seria l Clock (drives external serial clock line – SCL) Input/Output
721
SAM4S Series [DATASHEET]
Atmel-11100K-ATARM-SAM4S-Datasheet_09-Jun-15
34.6 Product Dependencies
34.6.1 I/O Lines
Both TWD and TWCK are bidirectional lines, connected to a positive supply voltage via a curren t sou rce or pu ll-u p
resistor. When the bus is free, both lines are high. The output stages of devices connected to the bus must have
an open-drain or open-collector to perform the wired-AND function.
TWD and T WCK pins may be m ultiplexed with PIO line s. To enable the TW I, the user must program the PIO
Controller to dedicate TWD and TWCK as peripheral lines.
The user must not program TWD and TWCK as open-drain. This is already do ne by the hardware.
34.6.2 Power Management
The TWI may be clocked through the Power Management Controller (PMC), thus the user must first configure the
PMC to enable the TWI clock.
34.6.3 Interrupt Sources
The TWI has an interrupt line conn ected to the Interrupt Controller. In order to handle interr upts, the Interrupt
Controller must be programmed before configuring the TWI.
34.7 Functional Description
34.7.1 Transfer Format
The data put on th e T W D line mu st b e 8 bits long. Data is transf erred MSB firs t; each by te must be followed by an
acknowledgement. The number of bytes per transfer is unlimited (see Figure 34-3).
Each transfer begins with a START condition and terminates with a STOP condition (see Figure 34-2).
A high-to-low transition on the TWD line while TWCK is high defines the START condition.
A low-to-high transition on the TWD line while TWCK is high defines the STOP condition.
Table 34-4. I/O Lines
Instance Signal I/O Line Periphera l
TWI0 TWCK0 PA4 A
TWI0 TWD0 PA3 A
TWI1 TWCK1 PB5 A
TWI1 TWD1 PB4 A
Table 34-5. Peripheral IDs
Instance ID
TWI0 19
TWI1 20
SAM4S Series [DATASHEET]
Atmel-11100K-ATARM-SAM4S-Datasheet_09-Jun-15
722
Figure 34-2. START and STOP Conditions
Figure 34-3. Transfer Format
34.7.2 Modes of Operation
The TWI has different modes of operations:
Master transmitter mode
Master receiver mode
Multi-master transmitter mode
Multi-master receiver mode
Slave transmitter mode
Slave receiver mode
These modes are described in the following sections.
TWD
TWCK
Start Stop
TWD
TWCK
Start Address R/W Ack Data Ack Data Ack Stop
723
SAM4S Series [DATASHEET]
Atmel-11100K-ATARM-SAM4S-Datasheet_09-Jun-15
34.7.3 Master Mode
34.7.3.1 Definition
The master is the device that starts a transfer, generates a clock and stops it.
34.7.3.2 Application Block Diagram
Figure 34-4. Master Mode Typical Application Block Diagram
34.7.3.3 Programming Master Mode
The following fields must be programmed before entering Master mode:
1. TWI_MMR.DADR (+ IADRSZ + IADR if a 10-bit device is addressed): The device address is used to
access slave devices in Read or Write mode.
2. TWI_CWGR.CKDIV + CHDIV + CLDIV: Clock waveform.
3. TWI_CR.SVDIS: Disables the S lave mode
4. TWI_CR.MSEN: Enables the Master mode
Note: If the TWI is already in Master mode, the device address (DADR) can be configured without disabling the Master
mode.
34.7.3.4 Master Transmitter Mode
After the master initiate s a START condition when writing in to the Transmit Holding register (TWI_THR), it sends a
7-bit slave address, configured in the Master Mode register (DADR in TWI_MMR), to notify the slave device. The
bit following the slave address indicates the tran sfer direction—0 in this case (MREAD = 0 in TWI_MMR).
The TWI transfers require the slave to acknowledge each received byte. During the acknowledge clock pulse (9th
pulse), the master releases the data line (HIGH), enabling the slave to pull it down in order to generate the
acknowledge. If the slave does not acknowledg e the byte, then the Not Acknowledge flag (NACK) is set in the TWI
Status Register (T WI_SR) of the master an d a STOP co ndition is sent. The NACK flag must b e cleare d b y re adin g
the TWI Status Register (TWI_SR) before the next write into the TWI Transmit Holding Register(TWI_THR). As
with the other status bits, an interrupt can be ge nerated if en abled in the Interru pt Enable re gister (TWI_IER). If the
slave acknowledges the b yte, the data written in the TWI_THR is then shifted in the intern al shifter a nd transfe rred.
When an acknowledge is detected, the TXRDY bit is set until a new write in the TWI_THR.
TXRDY is used as Transmit Ready for the PDC transmit channel.
While no new data is written in the TWI_THR, the serial clock line (SCL) is tied low. When new data is written in the
TWI_THR, the TWCK/SCL is released an d the data is sent. Setting the STOP bit in TWI_CR generates a STOP
condition.
Host with TWI
SDA
SCL
Atmel TWI
Serial EEPROM I²C RTC I²C LCD
Controller
Slave 1 Slave 2 Slave 3
VDD
I²C
Temperature
Sensor
Slave 4
* Rp: Pull-up value as given by the I²C Standard
Rp* Rp*
TWD
TWCK
SAM4S Series [DATASHEET]
Atmel-11100K-ATARM-SAM4S-Datasheet_09-Jun-15
724
After a master write transfer, the SCL is stretched (tied low) as long as no new data is written in the TWI_THR or
until a STOP command is performed.
See Figure 34-5, Figure 34-6, and Figure 34-7.
Figure 34-5. Master Write with One Data Byte
Figure 34-6. Master Write with Multiple Data Bytes
TXCOMP
TXRDY
Write THR (DATA)
STOP Command sent (write in TWI_CR)
TWD ADATAAS DADR W P
A DATA n AS DADR W DATA n+1 A PDATA n+2 A
TXCOMP
TXRDY
Write THR (Data n)
Write THR (Data n+1) Write THR (Data n+2)
Last data sent
STOP command performed
(by writing in the TWI_CR)
TWD
TWCK
725
SAM4S Series [DATASHEET]
Atmel-11100K-ATARM-SAM4S-Datasheet_09-Jun-15
Figure 34-7. Master Write with One Byte Internal Address and Multiple Data Bytes
34.7.3.5 Master Receiver Mode
The read sequence begins by setting the START bit. After the START condition has been sent, the master sends
a 7-bit slave address to notify the slave device. The bit following the slave address indicates the transfer
direction—1 in this case (MREAD = 1 in TWI_MMR). During the acknowledge clock pulse (9th pulse), the master
releases the data line (HIGH), enabling the slave to pull it down in order to generate the acknowledge. The master
polls the data line during this clock pulse and sets the NACK bit in the TWI_SR if the s lave d oes n ot ac knowled ge
the byte.
If an acknowledge is received, the master is then ready to receive data from the slave. After data has been
received, the master sends an acknowledge condition to notify the slave that the data has been received except
for the last da ta. See Figu re 34-8. When the RXRDY bit is set in the TWI_SR, a character ha s been received in the
Receive Holding Register (TWI_RHR). The RXRDY bit is reset when reading the TWI_RHR.
RXRDY is used as Receive Ready for the PDC receive channel.
When a single data byte read is performed, with or witho ut internal address (IADR), the START and STOP bits
must be set at the same time. See Figure 34-8. When a multiple data byte read is performed, with or without
internal address (IADR), the STOP bit must be set after the next-to-last data received. See Figure 34-9. For
internal addre ss usage, see Section 34.7.3.6.
Figure 34-8. Master Read with One Data Byte
A DATA n AS DADR W DATA n+1 A PDATA n+2 A
TXCOMP
TXRDY
Write THR (Data n)
Write THR (Data n+1) Write THR (Data n+2)
Last data sent
STOP command performed
(by writing in the TWI_CR)
TWD IADR A
TWCK
AS DADR R DATA NA P
TXCOMP
Write START &
STOP Bit
RXRDY
Read RHR
TWD
SAM4S Series [DATASHEET]
Atmel-11100K-ATARM-SAM4S-Datasheet_09-Jun-15
726
Figure 34-9. Master Read with Multiple Data Bytes
34.7.3.6 Internal Address
The TWI can perform transfers with 7-bit slave address devices and 10-bit sla ve address devices.
7-bit Slave Addressing
When addressing 7-bit slave devices, the internal address bytes are used to perform random address (read or
write) accesses to reach one or more data bytes, e.g. within a memory page location in a serial memory. When
performing read o perations with an interna l addr ess, the TWI perfor ms a write operation to set the intern al add ress
into the slave device, and then switch to Master receiver mode. Note that the second START condition (after
sending the IADR) is sometimes called “repeated start” (Sr) in I2C fully- compatible devices. See Figure 3 4-1 1. See
Figure 34-10 and Figure 34-12 for master write operatio n with inte rn al ad dr e ss.
The three internal address bytes are configurable through the Master Mode register (TWI_MMR).
If the slave device supports only a 7-bit address, i.e., no internal address, IADRSZ must be set to 0.
Table 34-6 shows the abbreviations used in Figu re 34-10 and Figure 34-11.
NA
AS DADR R DATA n A ADATA (n+1) A DATA (n+m)DATA (n+m)-1 PTWD
TXCOMP
Write START Bit
RXRDY
Write STOP Bit
after next-to-last data read
Read RHR
DATA n Read RHR
DATA (n+1) Read RHR
DATA (n+m)-1 Read RHR
DATA (n+m)
Table 34-6. Abbreviations
Abbreviation Definition
SStart
Sr Repeated Start
PStop
WWrite
RRead
A Acknowledge
NA Not Acknowledge
DADR Device Address
IADR Internal Address
727
SAM4S Series [DATASHEET]
Atmel-11100K-ATARM-SAM4S-Datasheet_09-Jun-15
Figure 34-10. Master Write with One, Two or Three Bytes Internal Address and One Data Byte
Figure 34-11. Master Read with One, Two or Three Bytes Internal Addr ess and One Data Byte
10-bit Slave Addressing
For a slave address higher than seven bits, the user must configure the address size (IADRSZ) and set the other
slave address bits in the Internal Address register (TWI_IADR). The two remaining internal address bytes,
IADR[15:8] and IADR[23:16] can be used the same way as in 7-bit slave addressing.
Example: Address a 10-bit device (10-bit device address is b1 b2 b3 b4 b5 b6 b7 b8 b9 b10)
1. Program IADRSZ = 1,
2. Program DADR with 1 1 1 1 0 b1 b2 (b1 is the MSB of the 10-bit address, b2, etc.)
3. Program TWI_IADR with b3 b4 b5 b6 b7 b8 b9 b10 (b10 is the LSB of the 10-bit address)
Figure 34-12 below shows a byte write to an Atmel AT24LC512 EEPROM. This demonstrates the use of internal
addresses to access the device.
Figure 34-12. Internal Address Usage
34.7.3.7 Using the Peripheral DMA Controller (PDC)
The use of the PDC significantly reduce s the CPU loa d.
To ensure correct implementation, proceed as fo llows.
Data Transmit with the PDC
1. Initialize the transmit PDC (memory pointers, transfer size - 1).
2. Configure the master (DADR, CKDIV, MREAD = 0, etc.)
3. Start the transfer by setting the PDC TXTEN bit.
S DADR W A IADR(23:16) A IADR(15:8) A IADR(7:0) A DATA A P
S DADR W A IADR(15:8) A IADR(7:0) A P
DATA A
A IADR(7:0) A P
DATA AS DADR W
TWD Three bytes internal address
Two bytes internal address
One byte internal address
TWD
TWD
S DADR WA IADR(23:16) A IADR(15:8) AIADR(7:0) A
S DADR W A IADR(15:8) A IADR(7:0) A
AIADR(7:0) A
S DADR W
DATA NA P
Sr DADR R A
Sr DADR R A DATA NA P
Sr DADR R A DATA NA P
TWD
TWD
TWD
Three bytes internal address
Two bytes internal address
One byte internal address
S
T
A
R
T
M
S
B
Device
Address
0
L
S
B
R
/
W
A
C
K
M
S
B
W
R
I
T
E
A
C
K
A
C
K
L
S
B
A
C
K
FIRST
WORD ADDRESS SECOND
WORD ADDRESS DATA
S
T
O
P
SAM4S Series [DATASHEET]
Atmel-11100K-ATARM-SAM4S-Datasheet_09-Jun-15
728
4. Wait for the PDC ENDTX Flag either by using the polling method or ENDTX interrupt.
5. Disable the PDC by setting the PDC TXTDIS bit.
6. Wait for the TXRDY flag in TWI_SR.
7. Set the STOP bit in TWI_CR.
8. Write the last character in TWI_THR.
9. (Only if peripheral clock must be disabled) Wait for the TXCOMP flag to be raised in TWI_SR.
Data Receive with the PDC
The PDC transfer size must be defined with the buffer size minus 2. The two remaining characters must be
managed without PDC to ensure that the exact number of bytes are received regardless of system bus latency
conditions encountered during the end of buffer transfer period.
In Slave mode, the number of characters to receive must be known in order to configure the PDC.
1. Initialize the receive PDC (memory pointers, transfer size - 2).
2. Configure the master (DADR, CKDIV, MREAD = 1, etc.)
3. Set the PDC RXTEN bit.
4. (Master Only) Write the START bit in the TWI_CR to start the transfer.
5. Wait for the PDC ENDRX Flag either by using polling method or ENDRX interrupt.
6. Disable the PDC by setting the PDC RXTDIS bit.
7. Wait for the RXRDY flag in TWI_SR.
8. Set the STOP bit in TWI_CR.
9. Read the penultimate character in TWI_RHR.
10. Wait for the RXRDY flag in TWI_SR.
11. R ead the last character in TWI_RHR.
12. (Only if peripheral clock must be disabled) Wait for the TXCOMP flag to be raised in TWI_SR.
34.7.3.8 SMBus Quick Command (Master Mode Only)
The TWI can perform a quick command:
1. Configure the Master mode (DADR, CKDIV, etc.).
2. Write the MREAD bit in the TWI_MMR at the value of the one-bit command to be sent.
3. Start the transfer by setting the QUICK bit in the TWI_CR.
Figure 34-13. SMBus Quick Command
34.7.3.9 Read/Write Flowcharts
The flowcharts in the following figures provide examples of read and write operations. A polling or interrupt method
can be used to check the status bits. The interrupt method requires that the Interrupt Enable Register (TWI_IER)
be configured first.
TXCOMP
TXRDY
Write QUICK command in TWI_CR
TWD AS DADR R/W P
729
SAM4S Series [DATASHEET]
Atmel-11100K-ATARM-SAM4S-Datasheet_09-Jun-15
Figure 34-14. TWI Write Operation with Single Data Byte without Internal Address
Set TWI clock
(CLDIV, CHDIV, CKDIV) in TWI_CWGR
(Needed only once)
Set the Control register:
- Master enable
TWI_CR = MSEN + SVDIS
Set the Master Mode register:
- Device slave address (DADR)
- Transfer direction bit
Write ==> bit MREAD = 0
Load T ransmit register
TWI_THR = Data to send
Read Status register
TXRDY = 1?
Read Status register
TXCOMP = 1?
Transfer finished
Yes
Yes
BEGIN
No
No
Write STOP Command
TWI_CR = STOP
SAM4S Series [DATASHEET]
Atmel-11100K-ATARM-SAM4S-Datasheet_09-Jun-15
730
Figure 34-15. TWI Write Oper atio n with Single Data Byte and Internal Address
BEGIN
Set TWI clock
(CLDIV, CHDIV, CKDIV) in TWI_CWGR
(Needed only once)
Set the Control register:
- Master enable
TWI_CR = MSEN + SVDIS
Set the Master Mode register:
- Device slave address (DADR)
- Internal address size (IADRSZ)
- Transfer direction bit
Write ==> bit MREAD = 0
Load transmit register
TWI_THR = Data to send
Read Status register
TXRDY = 1?
Read Status register
TXCOMP = 1?
Transfer finished
Set the internal address
TWI_IADR = address
Yes
Yes
No
No
Write STOP command
TWI_CR = STOP
731
SAM4S Series [DATASHEET]
Atmel-11100K-ATARM-SAM4S-Datasheet_09-Jun-15
Figure 34-16. TWI Write Operation with Multiple Data Bytes with or without Intern al Addr ess
Set the Control register:
- Master enable
TWI_CR = MSEN + SVDIS
Set the Master Mode register:
- Device slave address
- Internal address size (if IADR used)
- Transfer direction bit
Write ==> bit MREAD = 0
Internal address size = 0?
Load Transmit register
TWI_THR = Data to send
Read Status register
TXRDY = 1?
Data to send?
Read Status register
TXCOMP = 1?
END
BEGIN
Set the internal address
TWI_IADR = address
Yes
TWI_THR = data to send
Yes
Yes
Yes
No
No
No
Write STOP Command
TWI_CR = STOP
No
Set TWI clock
(CLDIV, CHDIV, CKDIV) in TWI_CWGR
(Needed only once)
SAM4S Series [DATASHEET]
Atmel-11100K-ATARM-SAM4S-Datasheet_09-Jun-15
732
Figure 34-17. TWI Read Op eration with Single Data Byte without Internal Address
Set the Control register:
- Master enable
TWI_CR = MSEN + SVDIS
Set the Master Mode register:
- Device slave address
- Transfer direction bit
Read ==> bit MREAD = 1
Start the transfer
TWI_CR = START | STOP
Read status register
RXRDY = 1?
Read Status register
TXCOMP = 1?
END
BEGIN
Yes
Yes
Set TWI clock
(CLDIV, CHDIV, CKDIV) in TWI_CWGR
(Needed only once)
Read Receive Holding Register
No
No
733
SAM4S Series [DATASHEET]
Atmel-11100K-ATARM-SAM4S-Datasheet_09-Jun-15
Figure 34-18. TWI Read Op eration with Single Data Byte and In tern al Address
Set the Control register:
- Master enable
TWI_CR = MSEN + SVDIS
Set the Master Mode register:
- Device slave address
- Internal address size (IADRSZ)
- Transfer direction bit
Read ==> bit MREAD = 1
Read Status register
TXCOMP = 1?
END
BEGIN
Yes
Set TWI clock
(CLDIV, CHDIV, CKDIV) in TWI_CWGR
(Needed only once)
Yes
Set the internal address
TWI_IADR = address
Start the transfer
TWI_CR = START | STOP
Read Status register
RXRDY = 1?
Read Receive Holding register
No
No
SAM4S Series [DATASHEET]
Atmel-11100K-ATARM-SAM4S-Datasheet_09-Jun-15
734
Figure 34-19. TWI Read Operation with Multiple Data Bytes with or without Internal Address
Internal address size = 0?
Start the transfer
TWI_CR = START
Stop the transfer
TWI_CR = STOP
Read Status register
RXRDY = 1?
Last data to read
but one?
Read status register
TXCOMP = 1?
END
Set the internal address
TWI_IADR = address
Yes
Yes
Yes
No
Yes
Read Receive Holding register (TWI_RHR)
No
Set the Control register:
- Master enable
TWI_CR = MSEN + SVDIS
Set the Master Mode register:
- Device slave address
- Internal address size (if IADR used)
- Transfer direction bit
Read ==> bit MREAD = 1
BEGIN
Set TWI clock
(CLDIV, CHDIV, CKDIV) in TWI_CWGR
(Needed only once)
No
No
Read Status register
RXRDY = 1?
Yes
Read Receive Holding register (TWI_RHR)
No
735
SAM4S Series [DATASHEET]
Atmel-11100K-ATARM-SAM4S-Datasheet_09-Jun-15
34.7.4 Multi-master Mode
34.7.4.1 Definition
In Multi-master mo de, more than one m aster may handle the bus at the sam e time without data corruption by u sing
arbitration.
Arbitration starts as soon as two or more masters place information on the bus at the same time, and stops
(arbitration is lost) for the master that intends to send a logical one while the other master sends a logical zero.
As soon as a master lose arbitration, it stops sending data and listens to the bus in order to detect a stop. When
the stop is detected, the master may put its data on the bus by performing arbitration.
Arbitration is illustrated in Figure 34-21.
34.7.4.2 Two Multi-master Modes
Two Multi-master modes may be distinguished:
1. TWI is considered as a master only and will never be addressed.
2. TWI may be either a master or a slave and may be addressed.
Note: Arbitration is supported in both Multi-master modes.
TWI as Master Only
In this mode, TWI is considered as a Master only (MSEN is always one) and must be driven like a Master with the
ARBLST (Arbitration Lost) flag in addition.
If arbitration is lost (ARBLST = 1), the user must reinitiate the data transfer.
If the user starts a transfer (ex.: DADR + START + W + Write in THR) and if the bus is busy, the TWI automatically
waits for a STOP condition on the bus to initiate the transfer (see Figure 34-20).
Note: The state of the bus (busy or free) is not shown in the user interface.
TWI as Master or Slave
The automatic reversal from Ma ster to Slave is not supported in case of a lost arbitration.
Then, in the case where TWI may be either a Master or a Slave, the user must manage the pseudo Multi-master
mode described in the steps below.
1. Progr am TWI in Sla ve mode (SADR + MSDIS + SVEN) and perform a slav e access (if TWI is addressed).
2. If the TWI has to be set in Master mode, wait until the TXCOMP flag is at 1.
3. Program the Master mode (DADR + SVDIS + MSEN) and start the transfer (ex: START + Write in THR).
4. As soon as the Master mode is enabled, the TWI scans the bus in order to detect if it is busy or free. When
the bus is considered free, TWI initiates the transfer.
5. As soon as the transfer is initiated and until a STOP cond ition is sent, the arbitration becomes relevant and
the user must monitor the ARBLST flag.
6. If the arbitration is lost (ARBLST is set to 1), the user must progr am the TWI in Slave mode in case the
Master that won the arbitration is required to access the TWI.
7. If the TWI has to be set in Slave mode, wait until TXCOMP flag is at 1 and then program the Slave mode.
Note: If the arbitration is lost and the TWI is addressed, the TWI will not acknowledge even if it is programmed in Slave mode
as soon as ARBLST is set to 1. Then the Master must repeat SADR.
SAM4S Series [DATASHEET]
Atmel-11100K-ATARM-SAM4S-Datasheet_09-Jun-15
736
Figure 34-20. Programmer Sends Data While the Bus is Busy
Figure 34-21. Arbitration Cases
The flowchart shown in Figure 34-22 gives an example of read and write operations in Multi-master mode.
TWCK
TWD DATA sent by a master
STOP sent by the master START sent by the TWI
DATA sent by the TWI
Bus is busy
Bus is free
A transfer is programmed
(DADR + W + START + Write THR) Transfer is initiated
TWI DATA transfer Transfer is kept
Bus is considered as free
TWCK
Bus is busy Bus is free
A transfer is programmed
(DADR + W + START + Write THR) Transfer is initiated
TWI DATA transfer Transfer is kept
Bus is considered as free
Data from a Master
Data from TWI S0
S0
0
1
1
1
ARBLST
S0
S 0 0
1
1
1
TWD S0
0
1
11
11
Arbitration is lost
TWI stops sending data
P
S0
1
P0
11
11
Data from the master Data from the TWI
Arbitration is lost
The master stops sending data
Transfer is stopped Transfer is programmed again
(DADR + W + START + Write THR)
TWCK
TWD
737
SAM4S Series [DATASHEET]
Atmel-11100K-ATARM-SAM4S-Datasheet_09-Jun-15
Figure 34-22. Multi-master Flowchart
34.7.5 Slave Mode
34.7.5.1 Definition
Slave mode is defined as a mode where the device receives the clock and the address from another device called
the master.
Programm the SLAVE mode:
SADR + MSDIS + SVEN
SVACC = 1 ?
TXCOMP = 1 ?
GACC = 1 ?
Decoding of the
programming sequence
Prog seq
OK ?
Change SADR
SVREAD = 1 ?
Read Status Register
RXRDY= 1 ?
Read TWI_RHR
TXRDY= 1 ?
EOSACC = 1 ?
Write in TWI_THR
Need to perform
a master access ?
Program the Master mode
DADR + SVDIS + MSEN + CLK + R / W
Read Status Register
ARBLST = 1 ?
MREAD = 1 ?
TXRDY= 0 ?
Write in TWI_THR
Data to send ?
RXRDY= 0 ?
Read TWI_RHR Data to read?
Stop transfer
Read Status Register
TXCOMP = 0 ?
GENERAL CALL TREATMENT
Yes
Yes
Yes
Yes
Yes
Yes
Yes
Yes
Yes
Yes
Yes
Yes
Yes
Yes
No
No
No
No
No
No
No
No
No
No
No
No No
No No
No
START
SAM4S Series [DATASHEET]
Atmel-11100K-ATARM-SAM4S-Datasheet_09-Jun-15
738
In this mode, the d evice never initiates and never com pletes the transmission (START, REPEATED START and
STOP conditions are always provided by the master).
34.7.5.2 Application Block Diagram
Figure 34-23. Slave Mode Typical Application Block Diagram
34.7.5.3 Programming Slave Mode
The following fields must be programmed before entering Slave mode:
1. TWI_SMR.SADR: The slav e device address is used in order to be accessed by master de vices in Read or
Write mode.
2. TWI_CR.MSDIS: Disables the Master mode.
3. TWI_CR.SVEN: Enables the Slave mode.
As the device receives the clock, values written in TWI_C WGR are ignored.
34.7.5.4 Receiving Data
After a START or REPEATED START condition is detected and if the addr ess sent by the Mast er matches with the
Slave address programmed in the SADR (Slave Address) field, SVACC (Slav e Access) flag is set and SVREAD
(Slave Read) indicates the direction of the transfer.
SVACC remains high until a STOP condition or a repeated START is dete cted. When such a condition is detected,
the EOSACC (End Of Slave Access) flag is set.
Read Sequence
In the case of a read se quence (SVREAD is high), TWI transfers data writte n in the TWI_THR (TWI Transmit
Holding Register) until a STOP condition or a REPEATED_START + an address different from SADR is detected.
Note that at the end of the read sequence TXCOMP (Transmission Complete) flag is set and SVACC reset.
As soon as data is written in the TWI_THR, the TXRDY (Transmit Holding Register Ready) flag is reset, and it is
set when the internal shifter is empty and the sent data acknowledged or not. If the data is not acknowledged, the
NACK flag is set.
Note that a STOP or a REPEATED START always follows a NACK.
See Figure 34-24.
Write Sequence
In the case of a write sequen ce (SVREAD is low), the RXRDY (Receive Holding Register Read y) flag is set as
soon as a character has been rece ived in the TWI_RHR (TWI Receive Holding Register). RXRDY is reset when
reading the TWI_RHR.
TWI continues receiving data until a STOP condition or a REPEATED_START + an address different from SADR
is detected. Note that at the end of the write sequence TXCOMP flag is set and SVACC reset.
LCD Controller
Slave 1 Slave 2 Slave 3
RR
V
DD
Host with TWI Host with TWI
Master
Host with TWI
SDA
SCL
TWD
TWCK
739
SAM4S Series [DATASHEET]
Atmel-11100K-ATARM-SAM4S-Datasheet_09-Jun-15
See Figure 34-25.
Clock Synchronization Sequence
If TWI_RHR is not read in time, the TWI performs a clock synchronization.
Clock synchronization information is given by the bit SCLWS (Clock Wait State).
See Figure 34-28.
Clock Stretching Sequence
If TWI_THR is not written in time, the TWI performs a clock stretching.
Clock stretching information is given by the bit SCLWS (Clock Wait State).
See Figure 34-27.
General Call
In the case where a GENERAL CALL is performed, the GACC (General Call Access) flag is set.
After GACC is set, the user must interpret the meaning of the GENERAL CALL and decode the new address
programming sequence.
See Figure 34-26.
34.7.5.5 Data Transfer
Read Operation
The Read mode is defined as a data requirement from the master.
After a START or a REPEATED START condition is detected, the decoding of the address starts. If the slave
address (SADR) is decoded, SVACC is set and SVREAD indicates the direction of the transfer.
Until a STOP or REPEATED START condition is detected, TWI continues sending data loaded in the TWI_THR.
If a STOP condition or a REPEATED START + an address different from SADR is detected, SVACC is reset.
Figure 34-24 describes the write operation.
Figure 34-24. Read Access Ordered by a Master
Notes: 1. When SVACC is low, th e state of SVREAD becomes irrelevant.
2. TXRDY is reset when data has been transmitted from TWI_THR to the internal shifter and set when this data has been
acknowledged or non acknowledged.
Write Operation
The Write mode is defined as a data transmission from the ma ster.
Write THR Read RHR
SVREAD has to be taken into account only while SVACC is active
TWD
TXRDY
NACK
SVACC
SVREAD
EOSACC
SADRS ADR R NA R A DATA A A DATA NA S/SrDATA NA P/S/Sr
SADR matches,
TWI answers with an ACK
SADR does not match,
TWI answers with a NACK ACK/NACK from the Master
SAM4S Series [DATASHEET]
Atmel-11100K-ATARM-SAM4S-Datasheet_09-Jun-15
740
After a START or a REPEATED START, the decoding of the address starts. If the slave address is decoded,
SVACC is set and SVREAD indicates the direction of the transfer (SVREAD is low in this case).
Until a STOP or REPEATED START condition is detected, TWI stores the received data in the TWI_RHR.
If a STOP condition or a REPEATED START + an address different from SADR is detected, SVACC is reset.
Figure 34-25 describes the write operation.
Figure 34-25. Write Access Ordered by a Master
Notes: 1. When SVACC is low, th e state of SVREAD becomes irrelevant.
2. RXRDY is set when data has been transmitted from the internal shifter to the TWI_RHR and reset when this data is read.
General Call
The general call is per fo rm ed in or de r to chan g e th e ad dres s of the s lav e.
If a GENERAL CALL is detected, GACC is set.
After the detection of GENERAL CALL, it is up to the programmer to decode the commands which come
afterwards.
In case of a WRITE command, the prog rammer has to decode the program ming sequence and program a ne w
SADR if the programming sequence matches.
Figure 34-26 describes the GENERAL CALL access.
Figure 34-26. Master Performs a General Call
Note: This method allows the user to create a personal programming sequence by choosing the programming bytes and the
number of them . Th e programming sequence has to be provi d ed to the master.
RXRDY
Read RHR
SVREAD has to be taken into account only while SVACC is active
TWD
SVACC
SVREAD
EOSACC
SADR does not match,
TWI answers with a NACK
SADRS ADR W NA W A DATA A A DATA NA S/SrDATA NA P/S/Sr
SADR matches,
TWI answers with an ACK
0000000 + W
GENERAL CALL P
SA
GENERAL CALL Reset or write DADD A New SADR
DATA1 ADATA2 A
A
New SADR
Programming sequence
TXD
GACC
SVACC
RESET command = 00000110X
WRITE command = 00000100X
Reset after read
741
SAM4S Series [DATASHEET]
Atmel-11100K-ATARM-SAM4S-Datasheet_09-Jun-15
Clock Synchronization/Stretching
In both Read and Write modes, it may occur that TWI_THR/TWI_RHR buffer is not filled /emptied before
transmission/reception of a new character. In this case, to avoid sending/receiving undesired data, a clock
stretching/synchronization mechanism is implemented.
Clock Stretching in Read Mode
The clock is tied low during the acknowledge phase if the internal shifter is empty and if a STOP or
REPEATED START condition was not detected. It is tied low until the internal shifter is loaded.
Figure 34-27 describes clock stretching in Read mode.
Figure 34-27. Clock Stretching in Read Mode
Notes: 1. TXRDY is reset when data has been written in the TWI_THR to the internal shifter and set when this data has been
acknowledged or non acknowledged.
2. At the end of the read sequence, TXCOMP is set after a STOP or after a REPEATED_START + an address different from
SADR.
3. SCLWS is automatically set when the clock stretching mechanism is started.
DATA1
The clock is stretched after the ACK, the state of TWD is undefined during clock stretching
SCLWS
SVACC
SVREAD
TXRDY
TWCK
TWI_THR
TXCOMP
The data is memorized in TWI_THR until a new value is written
TWI_THR is transmitted to the shift register Ack or Nack from the master
DATA0DATA0 DATA2
1
2
1
CLOCK is tied low by the TWI
as long as THR is empty
SSADR
SRDATA0AADATA1 ADATA2 NA S
XXXXXXX
2
Write THR
As soon as a START is detected
SAM4S Series [DATASHEET]
Atmel-11100K-ATARM-SAM4S-Datasheet_09-Jun-15
742
Clock Synchronization in Write Mode
The clock is tied low outside of the acknowledge phase if the internal shifter and the TWI_RHR is full. If a
STOP or REPEATED_START condition was not detected, it is tied low until TWI_RHR is read.
Figure 34-28 describes the clock synchronization in Write mode.
Figure 34-28. Clo ck Synchronization in Write Mod e
Notes: 1. At the end of the read sequence, TXCOMP is set after a STOP or after a REPEATED_START + an address different from
SADR.
2. SCLWS is automatically set when the clock synchronization mechanism is started and automatically reset when the
mechanism is finished.
Rd DATA0 Rd DATA1 Rd DATA2
SVACC
SVREAD
RXRDY
SCLWS
TXCOMP
DATA1 DATA2
TWCK is stretched on the last bit of DATA1
As soon as a START is detected
TWCK
TWD
TWI_RHR
CLOCK is tied low by the TWI as long as RHR is full
DATA0 is not read in the RHR
ADRS SADR W ADATA0A A DATA2DATA1 S
NA
743
SAM4S Series [DATASHEET]
Atmel-11100K-ATARM-SAM4S-Datasheet_09-Jun-15
Reversal After a Repea ted Star t
Reversal of Read to Write
The master initiates the communication by a read command and finishes it by a write command.
Figure 34-29 describes the repeated start + reversal from Read to Write mod e.
Figure 34-29. Repeated Start + Reversal from Re ad to Write Mode
Note: 1. TXCOMP is only set at the end of the transmission because after the repeated start, SADR is detected again.
Reversal of Write to Read
The master initiates the communication by a write command and finishes it by a read command.
Figure 34-30 describes the repeated start + reversal from Write to Read mode.
Figure 34-30. Repeated Start + Reversal from Write to Read Mode
Notes: 1. In this case, if TWI_THR has not been written at the end of the read command, the clock is automatically stre tched before
the ACK.
2. TXCOMP is only set at the end of the transmission because after the repeated start, SADR is detected again.
34.7.5.6 Using the Peripheral DMA Controller (PDC) in Slave Mode
The use of the PDC significantly reduce s the CPU loa d.
Data Transmit with the PDC in Slave Mode
The following procedure shows an example of data transmission with PDC.
S SADR R ADATA0A DATA1 SADRSr
NA
W A DATA2 A DATA3 A P
Cleared after read
DATA0 DATA1
DATA2 DATA3
SVACC
SVREAD
TWD
TWI_THR
TWI_RHR
EOSACC
TXRDY
RXRDY
TXCOMP
As soon as a START is detected
S SADR W ADATA0A DATA1 SADRSr
A
R A DATA2 A DATA3 NA P
Cleared after read
DATA0
DATA2 DATA3
DATA1
TXCOMP
TXRDY
RXRDY
As soon as a START is detected
Read TWI_RHR
SVACC
SVREAD
TWD
TWI_RHR
TWI_THR
EOSACC
SAM4S Series [DATASHEET]
Atmel-11100K-ATARM-SAM4S-Datasheet_09-Jun-15
744
1. Initialize the transmit PDC (memory pointers, transfer size).
2. Start the transfer by setting the PDC TXTEN bit.
3. Wait for the PDC ENDTX flag by using either the polling method or the ENDTX interrupt.
4. Disable the PDC by setting the PDC TXTDIS bit.
5. (Only if peripheral clock must be disabled) Wait for the TXCOMP flag to be raised in TWI_SR.
Data Receive with the PDC in Slave Mode
The following procedure shows an example of data transmission with PDC where the number of characters to be
received is known.
1. Initialize the receive PDC (memory pointers, transfer size).
2. Set the PDC RXTEN bit.
3. Wait for the PDC ENDRX flag by using either the polling method or the ENDRX interrupt.
4. Disable the PDC by setting the PDC RXTDIS bit.
5. (Only if peripheral clock must be disabled) Wait for the TXCOMP flag to be raised in TWI_SR.
34.7.5.7 Read Write Flowcharts
The flow chart shown in Figure 34-31 gives an example of re ad and write op erations in Slave mode. A polling or
interrupt method can be used to check the status bits. The interrupt method requires that the Interrupt Enable
Register (TWI _IE R) be con fig ur ed first .
745
SAM4S Series [DATASHEET]
Atmel-11100K-ATARM-SAM4S-Datasheet_09-Jun-15
Figure 34-31. Read Write Flowchart in Slave Mode
Set the SLAVE mode:
SADR + MSDIS + SVEN
SVACC = 1 ?
TXCOMP = 1 ?
GACC = 1 ?
Decoding of the
programming sequence
Prog seq
OK ?
Change SADR
SVREAD = 1 ?
Read Status Register
RXRDY= 1 ?
Read TWI_RHR
TXRDY= 1 ?
EOSACC = 1 ?
Write in TWI_THR
END
GENERAL CALL TREATMENT
No
No
No
No
No
No
No
No
SAM4S Series [DATASHEET]
Atmel-11100K-ATARM-SAM4S-Datasheet_09-Jun-15
746
34.8 Two-wire Interface (TWI) User Interface
Note: All unlisted offset values are considered as “reserved”.
Table 34-7 . Register Mapping
Offset Register Name Access Reset
0x00 Control Register TWI_CR Write-only –
0x04 Master Mode Register TWI_MMR Read/Write 0x00000000
0x08 Slave Mode Register TWI_SMR Read/Write 0x00000000
0x0C Internal Address Register TWI_IADR Read/Write 0x00000000
0x10 Clock Waveform Generator Register TWI_CWGR Read/Write 0x00000000
0x14–0x1C Reserved –––
0x20 Status Register TWI_SR Read-only 0x0000F009
0x24 Interrupt Enable Register TWI_IER Write-only –
0x28 Interrupt Disable Register TWI_IDR Write-only –
0x2C Interrupt Mask Register TWI_IMR R ead-only 0x00000000
0x30 R eceive Holding Register TWI_RHR Read-only 0x00000000
0x34 Transmit Holding Register TWI_T HR Write-only –
0xEC–0xFC Reserved – – –
0x100–0x128 Reserved for PDC registers – – –
747
SAM4S Series [DATASHEET]
Atmel-11100K-ATARM-SAM4S-Datasheet_09-Jun-15
34.8.1 TWI Control Register
Name: TWI_CR
Address: 0x40018000 (0), 0x4001C000 (1)
Access: Write-only
• START: Send a START Condition
0: No effect.
1: A frame beginning with a START bit is transmitted according to the features def i ne d in the TWI Master Mod e Reg ist er
(TWI_MMR).
This action is necessary for the TWI to read data from a slave. When configured in Master mode with a write operation, a
frame is sent as soon as the user writes a character in the Transmit Holding Register (TWI_THR).
• STOP: Send a STOP Condition
0: No effect.
1: STOP condition is sent just after completing the current byte transmission in Master read mode.
– In single data byte master read, the START and STOP must both be set.
– In multiple data bytes master read, the STOP must be set after the last data received but one.
– In Master read mode, if a NACK bit is received, the STOP is automatically performed.
– In master data write oper ation, a STOP condition is sent when transmission of the curr ent data has ended.
• MSEN: TWI Master Mode Enabled
0: No effect.
1: Enables the Master mode (MSDIS must be written to 0).
Note: Switching from Slave to Master mode is only permitted when TXCOMP = 1.
• MSDIS: TWI Master Mode Disabled
0: No effect.
1: The Master mode is disabled, all pending data is transmitted. The shifter and holding characters (if it contains data) are
transmitted in case of write operation. In read operation, the character being transferred must be completely received
before disabling.
31 30 29 28 27 26 25 24
––––––––
23 22 21 20 19 18 17 16
––––––––
15 14 13 12 11 10 9 8
––––––––
76543210
SWRST QUICK SVDIS SVEN MSDIS MSEN STOP START
SAM4S Series [DATASHEET]
Atmel-11100K-ATARM-SAM4S-Datasheet_09-Jun-15
748
• SVEN: TWI Slave Mode Enabled
0: No effect.
1: Enables the Slave mode (SVDIS must be written to 0)
Note: Switching from master to Slave mode is only permitted when TXCOMP = 1.
• SVDIS: TWI Slave Mode Disabled
0: No effect.
1: The Slave mode is disabled. The shifter and holding characters (if it contains data) are transmitted in case of read oper-
ation. In write operation, the character being transferred must be completely received before disabling.
• QUICK: SMBus Quick Command
0: No effect.
1: If Master mode is enabled, a SMBus Quick Command is sent.
• SWRST: Software Reset
0: No effect.
1: Equivalent to a system reset.
749
SAM4S Series [DATASHEET]
Atmel-11100K-ATARM-SAM4S-Datasheet_09-Jun-15
34.8.2 TWI Master Mode Register
Name: TWI_MMR
Address: 0x40018004 (0), 0x4001C004 (1)
Access: Read/Write
• IADRSZ: Internal Device Address Size
• MREAD: Master Read Direction
0: Master write direction.
1: Master read direction.
• DADR: Device Address
The device address is used to access slave devices in Read or Write mode. These bits are only used in Master mode.
31 30 29 28 27 26 25 24
––––––––
23 22 21 20 19 18 17 16
–DADR
15 14 13 12 11 10 9 8
–––MREAD–– IADRSZ
76543210
––––––––
Value Name Description
0 NONE No internal device address
1 1_BYTE One-byte internal devi c e address
2 2_BYTE Two-byte internal device address
3 3 _BYTE Three-byte internal device address
SAM4S Series [DATASHEET]
Atmel-11100K-ATARM-SAM4S-Datasheet_09-Jun-15
750
34.8.3 TWI Slave Mode Register
Name: TWI_SMR
Address: 0x40018008 (0), 0x4001C008 (1)
Access: Read/Write
• SADR: Slave Address
The slave device address is used in Slave mode in order to be accessed by master devices in Read or Write mode.
SADR must be programmed before enabling the Slave mode or after a general call. Writes at other times have no effect.
31 30 29 28 27 26 25 24
––––––––
23 22 21 20 19 18 17 16
– SADR
15 14 13 12 11 10 9 8
––––––
76543210
––––––––
751
SAM4S Series [DATASHEET]
Atmel-11100K-ATARM-SAM4S-Datasheet_09-Jun-15
34.8.4 TWI Internal Address Register
Name: TWI_IADR
Address: 0x4001800C (0), 0x4001C00C (1)
Access: Read/Write
• IADR: Internal Address
0, 1, 2 or 3 bytes depending on IADRSZ.
31 30 29 28 27 26 25 24
––––––––
23 22 21 20 19 18 17 16
IADR
15 14 13 12 11 10 9 8
IADR
76543210
IADR
SAM4S Series [DATASHEET]
Atmel-11100K-ATARM-SAM4S-Datasheet_09-Jun-15
752
34.8.5 TWI Clock Waveform Generator Register
Name: TWI_CWGR
Address: 0x40018010 (0), 0x4001C010 (1)
Access: Read/Write
TWI_CWGR is only used in Master mode.
• CLDIV: Clock Low Divider
The TWCK low period is defined as follows: tlow = ((CLDIV × 2CKDIV) + 4 × tperipheral clock
• CHDIV: Clock High Divider
The TWCK high period is defined as follows: thigh = ((CHDIV × 2CKDIV) + 4 × tperipheral clock
• CKDIV: Clock Divider
The TWCK is used to increase both SCL high and low periods.
31 30 29 28 27 26 25 24
––––––––
23 22 21 20 19 18 17 16
––––– CKDIV
15 14 13 12 11 10 9 8
CHDIV
76543210
CLDIV
753
SAM4S Series [DATASHEET]
Atmel-11100K-ATARM-SAM4S-Datasheet_09-Jun-15
34.8.6 TWI Status Register
Name: TWI_SR
Address: 0x40018020 (0), 0x4001C020 (1)
Access: Read-only
• TXCOMP: Transmission Completed (cleared by writing TWI_THR)
TXCOMP used in Master mode:
0: During the length of the current frame.
1: When both holding register and internal shifter ar e empty and STOP condition has been sent.
TXCOMP behavior in Master mode can be seen in Figure 34-7 and in Figure 34-9.
TXCOMP used in Slav e mo de :
0: As soon as a START is detected.
1: After a STOP or a REPEATED START + an address different from SADR is detected.
TXCOMP behavior in Slave mode can be seen in Figure 34-27, Figure 34-28, Figure 34-29 and Figure 34-30.
• RXRDY: Receive Holding Register Ready (cleared by reading TWI_RHR)
0: No character has been received since the last TWI_RHR read operation.
1: A byte has been received in the TWI_RHR since the last read.
RXRDY behavior in Master mode can be seen in Figure 34-9.
RXRDY behavior in Slav e mo d e can be seen in Figure 34-25, Figure 34-28, Figure 34-29 and Figure 34-30.
• TXRDY: Transmit Holding Register Ready (cleared by writing TWI_THR)
TXRDY used in Master mode:
0: The transmit holding register has not been transferred into internal shifter. Set to 0 when writing into TWI_THR.
1: As soon as a data byte is transferred from TWI _T HR to internal shifter or if a NACK error is detected, TXRDY is set at
the same time as TXCOMP and NACK. TXRDY is also set when MSEN is set (enable TWI).
TXRDY behavior in Master mode can be seen in Figure 34.7.3.4.
TXRDY used in Slave mode:
0: As soon as data is written in the TWI_THR, until this data has been transmitted and acknowledged (ACK or NACK).
1: It indicates that the TWI_THR is empty and that data has been transmitted and acknowledged.
31 30 29 28 27 26 25 24
––––––––
23 22 21 20 19 18 17 16
––––––––
15 14 13 12 11 10 9 8
TXBUFE RXBUFF ENDTX ENDRX EOSACC SCLWS ARBLST NACK
76543210
–OVREGACC SVACC SVREAD TXRDY RXRDY TXCOMP
SAM4S Series [DATASHEET]
Atmel-11100K-ATARM-SAM4S-Datasheet_09-Jun-15
754
If TXRDY is high and if a NACK has been detected, the transmission will be stopped. Thus when TRDY = NACK = 1, the
programmer must not fill TWI_THR to avoid losing it.
TXRDY behavior in Slave mode can be seen in Figure 34-24, Figure 34-27, Figure 34-29 and Figure 34-30.
• SVREAD: Slave Read
This bit is only used in Slave mode. When SVACC is low (no Slave access has been detected) SVREAD is irrelevant.
0: Indicates that a write access is performed by a Master.
1: Indicates that a read access is performed by a Master.
SVREAD behavior can be seen in Figure 34-24, Figure 34-25, Figure 34-29 and Figure 34-30.
• SVACC: Slave Access
This bit is only used in Slave mode.
0: TWI is not addressed. SVACC is automatically cleared after a NACK or a STOP condition is detected.
1: Indicates that the address decoding sequence has matched (A Master has sent SADR). SVACC remains high until a
NACK or a STOP condition is detected.
SVACC behavior can be seen in Figure 34-24, Figure 34-25, Figure 34-29 and Figure 34-30.
• GACC: General Call Access (cleared on read)
This bit is only used in Slave mode.
0: No General Call has been detected.
1: A General Call has been detected. After the detection of General Call, if need be, the programmer may acknowledge
this access and decode the following bytes and respond according to the value of the bytes.
GACC behavior can be seen in Figure 34-26.
• OVRE: Overrun Error (cleared on read)
This bit is only used in Master mode.
0: TWI_RHR has not been loaded while RXRDY was set
1: TWI_RHR has been loaded while RXRDY was set. Reset by read in TWI_SR when TXCOMP is set.
• NACK: Not Acknowledged (cleared on read)
NACK used in Master mode:
0: Each data byte has been correctly received by the far-end side TWI slave component.
1: A data byte or an address byte h as not been acknowledged by the slave component. Set at the same time as TXCOMP.
NACK used in Slave Read mode:
0: Each data byte has been correctly received by the Master.
1: In Read mode, a data byte has not been acknowledged by the Master. When NACK is set, the programmer must not fill
TWI_THR even if TXRDY is set, because that means that the Master will stop the data transfer or reinitiate it.
Note that in Slave write mode all data are acknowledged by the TWI.
755
SAM4S Series [DATASHEET]
Atmel-11100K-ATARM-SAM4S-Datasheet_09-Jun-15
• ARBLST: Arbitration Lost (cleared on read)
This bit is only used in Master mode.
0: Arbitration won.
1: Arbitration lost. Another master of the TWI bus has won the multi-master arbitration. TXCOMP is set at the same time.
• SCLWS: Clock Wait State
This bit is only used in Slave mode.
0: The clock is not stretched.
1: The clock is stretched. TWI_THR / TWI_RHR buffer is not filled / emptied before transmission / reception of a new
character.
SCLWS behavior can be seen in Figure 34-27 and Figure 34-28.
• EOSACC: End Of Slave Access (cleared on read)
This bit is only used in Slave mode.
0: A slave access is being performed.
1: The Slave access is finished. End Of Slave Access is automatically set as soon as SVACC is reset.
EOSACC behavior can be seen in Figure 34-29 and Figure 34-30.
• ENDRX: End of RX buffer (cleared by writing TWI_RCR or TWI_RNCR)
0: The Receive Counter Register has not reached 0 since the last write in TWI_RCR or TWI_RNCR.
1: The Receive Counter Register has reached 0 since the last write in TWI_RCR or TWI_RNCR.
• ENDTX: End of TX buffer (cleared by writing TWI_TCR or TWI_TNCR)
0: The Transmit Counter Register has not reached 0 since the last write in TWI_TCR or TWI_TNCR.
1: The Transmit Counter Register has reached 0 since the last write in TWI_TCR or TWI_TNCR.
• RXBUFF: RX Buffer Full (cleared by writing TWI_RCR or TWI_RNCR)
0: TWI_RCR or TWI_RNCR have a value other than 0.
1: Both TWI_RCR and TWI_RNCR have a value of 0.
• TXBUFE: TX Buffer Empty (cleared by writing TWI_TCR or TWI_TNCR)
0: TWI_TCR or TWI_TNCR have a value other than 0.
1: Both TWI_TCR and TWI_TNCR have a value of 0.
SAM4S Series [DATASHEET]
Atmel-11100K-ATARM-SAM4S-Datasheet_09-Jun-15
756
34.8.7 TWI Interrupt Enable Register
Name: TWI_IER
Address: 0x40018024 (0), 0x4001C024 (1)
Access: Write-only
The following configuration values are valid for all listed bit names of this register:
0: No effect.
1: Enables the corresponding interrupt.
• TXCOMP: Transmission Completed Interrupt Enable
• RXRDY: Receive Holding Register Ready Interrupt Enable
• TXRDY: Transmit Holding Register Ready Interrupt Enable
• SVACC: Slave Access Interrupt Enable
• GACC: General Call Access Interrupt Enable
• OVRE: Overrun Error Interrupt Enable
• NACK: Not Acknowledge Interrupt Enable
• ARBLST: Arbitration Lost Interrupt Enable
• SCL_WS: Clock Wait State Interrupt Enable
• EOSACC: End Of Slave Access Interrupt Enable
• ENDRX: End of Receive Buffer Interrupt Enable
• ENDTX: End of Transmit Buffer Interrupt Enable
• RXBUFF: Receive Buffer Full Interrupt Enable
• TXBUFE: Transmit Buffer Empty Interrupt Enable
31 30 29 28 27 26 25 24
––––––––
23 22 21 20 19 18 17 16
––––––––
15 14 13 12 11 10 9 8
TXBUFE RXBUFF ENDTX ENDRX EOSACC SCL_WS ARBLST NACK
76543210
–OVREGACC SVACC – TXRDY RXRDY TXCOMP
757
SAM4S Series [DATASHEET]
Atmel-11100K-ATARM-SAM4S-Datasheet_09-Jun-15
34.8.8 TWI Interrupt Disable Register
Name: TWI_IDR
Address: 0x40018028 (0), 0x4001C028 (1)
Access: Write-only
The following configuration values are valid for all listed bit names of this register:
0: No effect.
1: Disables the corresponding interrupt.
• TXCOMP: Transmission Completed Interrupt Disable
• RXRDY: Receive Holding Register Ready Interrupt Disable
• TXRDY: Transmit Holding Register Ready Interrupt Disable
• SVACC: Slave Access Interrupt Disable
• GACC: General Call Access Interrupt Disable
• OVRE: Overrun Error Interrupt Disable
• NACK: Not Acknowledge Interrupt Disable
• ARBLST: Arbitration Lost Interrupt Disable
• SCL_WS: Clock Wait State Interrupt Disable
• EOSACC: End Of Slave Access Interrupt Disable
• ENDRX: End of Receive Buffer Interrupt Disable
• ENDTX: End of Transmit Buffer Interrupt Disable
• RXBUFF: Receive Buffer Full Interrupt Disable
• TXBUFE: Transmit Buffer Empty Interrupt Disable
31 30 29 28 27 26 25 24
––––––––
23 22 21 20 19 18 17 16
––––––––
15 14 13 12 11 10 9 8
TXBUFE RXBUFF ENDTX ENDRX EOSACC SCL_WS ARBLST NACK
76543210
–OVREGACC SVACC – TXRDY RXRDY TXCOMP
SAM4S Series [DATASHEET]
Atmel-11100K-ATARM-SAM4S-Datasheet_09-Jun-15
758
34.8.9 TWI Interrupt Mask Register
Name: TWI_IMR
Address: 0x4001802C (0), 0x4001C02C (1)
Access: Read-only
The following configuration values are valid for all listed bit names of this register:
0: The corresponding interrupt is disabled.
1: The corresponding interrupt is enabled.
• TXCOMP: Transmission Completed Interrupt Mask
• RXRDY: Receive Holding Register Ready Interrupt Mask
• TXRDY: Transmit Holding Register Ready Interrupt Mask
• SVACC: Slave Access Interrupt Mask
• GACC: General Call Access Interrupt Mask
• OVRE: Overrun Error Interrupt Mask
• NACK: Not Acknowledge Interrupt Mask
• ARBLST: Arbitration Lost Interrupt Mask
• SCL_WS: Clock Wait State Interrupt Mask
• EOSACC: End Of Slave Access Interrupt Mask
• ENDRX: End of Receive Buffer Interrupt Mask
• ENDTX: End of Transmit Buffer Interrupt Mask
• RXBUFF: Receive Buffer Full Interrupt Mask
• TXBUFE: Transmit Buffer Empty Interrupt Mask
31 30 29 28 27 26 25 24
––––––––
23 22 21 20 19 18 17 16
––––––––
15 14 13 12 11 10 9 8
TXBUFE RXBUFF ENDTX ENDRX EOSACC SCL_WS ARBLST NACK
76543210
–OVREGACC SVACC – TXRDY RXRDY TXCOMP
759
SAM4S Series [DATASHEET]
Atmel-11100K-ATARM-SAM4S-Datasheet_09-Jun-15
34.8.10 TWI Receive Holding Register
Name: TWI_RHR
Address: 0x40018030 (0), 0x4001C030 (1)
Access: Read-only
• RXDATA: Master or Slave Receive Holding Data
31 30 29 28 27 26 25 24
––––––––
23 22 21 20 19 18 17 16
––––––––
15 14 13 12 11 10 9 8
––––––––
76543210
RXDATA
SAM4S Series [DATASHEET]
Atmel-11100K-ATARM-SAM4S-Datasheet_09-Jun-15
760
34.8.11 TWI Transmit Holding Register
Name: TWI_THR
Address: 0x40018034 (0), 0x4001C034 (1)
Access: Write-only
• TXDATA: Master or Slave Transmit Holding Data
31 30 29 28 27 26 25 24
––––––––
23 22 21 20 19 18 17 16
––––––––
15 14 13 12 11 10 9 8
––––––––
76543210
TXDATA
761
SAM4S Series [DATASHEET]
Atmel-11100K-ATARM-SAM4S-Datasheet_09-Jun-15
35. Universal Asynchronous Receiver Transmitter (UART)
35.1 Description
The Universal Asynchronous Receiver Transmitter (UART) features a two-pin UART that can be used for
communication and trace purposes and offers an ideal medium for in-situ progr amming solutions.
Moreover, the a ssociation with a peripheral DMA controll er (PDC) perm its packet handling for these tasks with
processor time reduced to a minimum.
35.2 Embedded Characteristics
Two-pin UART
Independent Receiver and Transmitter with a Common Programmable Baud Rate Generator
Even, Odd, Mark or Space Parity Generation
Parity, Fram in g an d Ov er ru n Err or Dete ct ion
Automatic Echo, Local Loopback and Remote Loopback Channel Modes
Interrupt Generation
Support for Two PDC Channels with Connection to Receiver and Transmitter
35.3 Block Diagram
Figure 35-1. UART Block Diagram
Peripheral DMA Controller Baud Rate
Generator
Transmit
Receive
Interrupt
Control
Parallel
Input/
Output
UTXD
URXD
uart_irq
APB
bus clock Bridge
peripheral clock
PMC
UART
Table 35-1. UART Pin Description
Pin Name Descrip ti on Type
URXD UART Receive Data Input
UTXD UART Transmit Data Output
SAM4S Series [DATASHEET]
Atmel-11100K-ATARM-SAM4S-Datasheet_09-Jun-15
762
35.4 Product Dependencies
35.4.1 I/O Lines
The UART pins are multiplexed with PIO lines. The user must first configure the corresponding PIO Co ntroller to
enable I/O line operations of the UART.
35.4.2 Power Management
The UART clock can be controlled through the Power Management Controller (PMC). In this case, the user must
first configure the PMC to enable the UART clock. Usually, the peripheral identifier used for this purpose is 1.
35.4.3 Interrupt Sources
The UART interrupt line is connected to one of the interrupt sources of the Interrupt Controller. Interrupt handling
requires programming of the Interrupt Controller before configuring the UART.
35.5 Functional Description
The UART operates in Asynchronous mode only and supports only 8-bit character handling (with parity). It has no
clock pin.
The UART is made up of a receiver and a transmitter that operate independently, and a common baud rate
generator. Receiver timeout and transmitter time guard are not implemented. However, all the implemented
features are compatible with those of a standard USART.
35.5.1 Baud Rate Generator
The baud rate generator provides the bit period clock named baud rate clock to both the receiver and the
transmitter. The baud rate clock is the peripheral clock divided by 16 times the clock divisor (CD) value written in
the Baud Rate Generator register (UART_BRGR). If UART_BRGR is set to 0, the baud rate clock is disabled and
the UART remains inactive. The maxim um allowable baud rate is peripheral clo ck divided by 16. The minimum
allowable baud rate is peripheral clock divided by (16 x 65536).
Table 35-2. I/O Lines
Instance Signal I/O Line Periphera l
UART0 URXD0 PA9 A
UART0 UTXD0 PA10 A
UART1 URXD1 PB2 A
UART1 UTXD1 PB3 A
Table 35-3. Peripheral IDs
Instance ID
UART0 8
UART1 9
763
SAM4S Series [DATASHEET]
Atmel-11100K-ATARM-SAM4S-Datasheet_09-Jun-15
Figure 35-2. Baud Rate Generator
35.5.2 Receiver
35.5.2.1 Receiver Reset, Enable and Disable
After device reset, the UART receiver is disabled and must be enabled before being used. The receiver can be
enabled by writing the Control Register (UART_CR) with the bit RXEN at 1. At this command, the receiver starts
looking for a start bit.
The programmer can d isable the receiver by writing UART_CR with the bit RXDIS at 1. If the receiver is waiting for
a start bit, it is immediately stopped. However, if the receiver has already detected a start bit and is receiving the
data, it waits for the stop bit before actually stopping its operation.
The receiver can be put in reset state by writing UART_C R with the bit RSTRX at 1. In this case, the receiver
immediately stops its current oper ations and is di sable d, wha tever its cu rren t state. If RSTRX is applied when data
is being process ed , th is dat a is lost.
35.5.2.2 Start Detection and Data Sampling
The UART only supports asynchron ous operations, and this affects only its receiver. The UART re ceiver detects
the start of a received character by samp ling the URXD signal until it detects a valid start bit. A low level (space) on
URXD is int erpreted a s a valid st art bit if it i s detected for more t han seve n cycles of t he sampli ng clock, wh ich is
16 times the baud rate. Hence, a space that is longer than 7/16 of the bit period is detected as a valid start bit. A
space which is 7/16 of a bit period or shorter is ignored and the receiver continues to wait for a valid start bit.
When a valid start bit has been detected, the receiver samples the URXD at the theoretical midpoint of each bit. It
is assumed that each bit lasts 16 cycles of the sampling clock (1-bit period) so the bit sampling point is eight cycles
(0.5-bit period) after the start of the bit. The first sampling point is therefore 24 cycles (1.5-bit periods) after
detecting the falling edge of the start bit.
Each subsequent bit is sampled 16 cycles (1-bit period) after the previous one.
Figure 35-3. Start Bit Detection
peripheral clock 16-bit Counter
0
Baud Rate
Clock
CD
CD
OUT
Divide
by 16
0
1
>1
Receiver
Sampling Clock
D0 D1 D2 D3 D4 D5 D6 D7 PSSD0 D1 D2 D3 D4 D5 D6 D7 P
URXD
RSTSTA
RXRDY
OVRE
stop stop
SAM4S Series [DATASHEET]
Atmel-11100K-ATARM-SAM4S-Datasheet_09-Jun-15
764
Figure 35-4. Character Reception
35.5.2.3 Receiver Ready
When a complete character is received, it is transferred to the Receive Holding Register (UART_RHR) and the
RXRDY status bit in the Status Register (UART_SR) is set. The bit RXRDY is automatically cleared when
UART_RHR is read.
Figure 35-5. Receiver Ready
35.5.2.4 Receiver Overrun
The OVRE status bit in UART_SR is set if UART_R HR has not been read by the software (or the PDC) since the
last transfer, the RXRDY bit is still set and a new character is received. OVRE is cleared when the software writes
a 1 to the bit RSTSTA (Reset Status) in UART_CR.
Figure 35-6. Receiver Overrun
35.5.2.5 Parity Error
Each time a character is received, the receiver calculates the parity of the received data bits, in accordance with
the field PAR in the Mode Register (UAR T_MR). It then compar es the result with the received parity bit. If different,
the parity error bit PARE in UART_SR is set at the same time RXRDY is set. The parity bit is cleared when
UART_CR is written with the bit RSTSTA (Reset Status) at 1. If a new character is received befo re the reset status
command is written, the PARE bit remains at 1.
D0 D1 D2 D3 D4 D5 D6 D7
URXD
True Start Detection
Sampling
Parity Bit
Stop Bit
Example: 8-bit, parity enabled 1 stop
1 bit
period
0.5 bit
period
D0 D1 D2 D3 D4 D5 D6 D7 PSSD0 D1 D2 D3 D4 D5 D6 D7 P
URXD
Read UART_RHR
RXRDY
D0 D1 D2 D3 D4 D5 D6 D7 PSSD0 D1 D2 D3 D4 D5 D6 D7 P
URXD
RSTST
A
RXRDY
OVRE
stop stop
765
SAM4S Series [DATASHEET]
Atmel-11100K-ATARM-SAM4S-Datasheet_09-Jun-15
Figure 35-7. Parity Error
35.5.2.6 Receiver Framing Error
When a start bit is detecte d, it generates a characte r reception whe n all the data bi ts have been sa mpled. The stop
bit is also sampled and when it is detected at 0, the FRAME (Framing Error) bit in UA RT_SR is set at the same
time the RXRDY bit is set. The FRAME bit remains high unt il the Control Register (UART_CR) is written with the
bit RSTSTA at 1.
Figure 35-8. Receiver Framing Error
35.5.3 Transmitter
35.5.3.1 Transmitter Reset, Enable and Disable
After device reset, the UART transmitter is disabled and must be enabled before being used. The transmitter is
enabled by writing UART_CR with the bit TXEN at 1. From this command, the transmitter waits for a character to
be written in the Transmit Holding Register (UART_THR) before actually starting the transmission.
The programmer can disable the transmitter by writing UART_CR with the bit TXDIS at 1. If the transmitter is not
operating, it is immediately stop ped. However, if a character is being processed into the in ternal shift register
and/or a character has been written in the UART_THR, the characters are completed before the transmitter is
actually stopped.
The programmer can also put the transmitter in its reset state by writing the UART_CR with the bit RSTTX at 1.
This immediately stops the transmitter, whether or not it is processing characters.
35.5.3.2 Transmit Format
The UART transmitter drives the pin UTXD at the baud rate clock speed. The line is driven depending on the
format defined in UART_MR and the data stored in the internal shift register. One start bit at level 0, then the 8
data bits, from the lowest to the highest bit, one optional parity bit and one stop bit at 1 are co nsecutively shifted
out as shown in the following figure. The field PARE in UART_MR defines whether or not a parity bit is shifted out.
When a parity bit is enable d, it can be selecte d between an odd pa rity, an even parity, or a fixed sp ace or mark b i t.
stop
D0 D1 D2 D3 D4 D5 D6 D7 PS
URXD
RSTSTA
RXRDY
PARE
Wrong Parity Bit
D0 D1 D2 D3 D4 D5 D6 D7 PS
URXD
RSTSTA
RXRDY
FRAME
Stop Bit
Detected at 0
stop
SAM4S Series [DATASHEET]
Atmel-11100K-ATARM-SAM4S-Datasheet_09-Jun-15
766
Figure 35-9. Character Transm ission
35.5.3.3 Transmitter Control
When the transmitter is enabled, the bit TXRDY (Transmitter Ready) is set in UART_SR. The transmission starts
when the programmer writes in the UART_THR, and after the written ch aracter is tran sferred fr om UART_THR to
the internal shift register. The TXRDY bit remains high until a second character is written in UART_THR. As soon
as the first character is completed, the last character written in UART_THR is transferred into the internal shift
register and TXRDY rises again, showing that the holding register is empty.
When both the intern al shift r egi ster a nd UART_ THR are emp ty, i.e., all the ch aracters written in UART_THR have
been processed, the TXEMPTY bit rises after the last stop bit has been completed.
Figure 35-10. Transmitter Control
35.5.4 Peripheral DMA Controller (PDC)
Both the receiver and the transmitter of the UART are connected to a PDC.
The PDC channels are programmed via registers that are mapped within the UART user interface from the offset
0x100. The status bits are reported in UART_SR and generate an interrupt.
The RXRDY bit triggers the PDC channel data transfer of the receiver. This results in a read of the data in
UART_RHR. The TXRDY bit triggers the PDC channel data transfer of the transmitter. This results in a write of
data in UART_THR.
35.5.5 Test Modes
The UART supports three test modes. These modes of operation are pro grammed by using the CHMO DE field in
UART_MR.
The Automatic echo mode allows a bit-by-bit retransmission. When a bit is received on the URXD line, it is sent to
the UTXD line. The transmitter operates normally, but has no effect on the UTXD line.
D0 D1 D2 D3 D4 D5 D6 D7
UTXD
Start
Bit
Parity
Bit
Stop
Bit
Example: Parity enabled
Baud Rate
Clock
UART_THR
Shift Register
UTXD
TXRDY
TXEMPTY
Data 0 Data 1
Data 0
Data 0
Data 1
Data 1SSPP
Write Data 0
in UART_THR
Write Data 1
in UART_THR
stop
stop
767
SAM4S Series [DATASHEET]
Atmel-11100K-ATARM-SAM4S-Datasheet_09-Jun-15
The Local loopback mode allows the transmitted characters to be receiv ed. UTXD and URXD p ins are not used
and the output of the transmitter is internally connected to the input of the receiver. The URXD pin level has no
effect and the UTXD line is held high, as in idle state.
The Remote loopback mode dir ectly connects the URXD pin to the UTXD lin e. The transmitter and the receiver are
disabled and have no effect. This mode allows a bit-by-bit retransmission.
Figure 35-11. Test Modes
Receiver
Transmitter Disabled
RXD
TXD
Receiver
Transmitter Disabled
RXD
TXD
V
DD
Disabled
Receiver
Transmitter Disabled
RXD
TXD
Disabled
Automatic Echo
Local Loopback
Remote Loopback V
DD
SAM4S Series [DATASHEET]
Atmel-11100K-ATARM-SAM4S-Datasheet_09-Jun-15
768
35.6 Universal Asynchronous Receiver Transmitter (UART) User Interface
Table 35-4 . Register Mapping
Offset Register Name Access Reset
0x0000 Control Register UART_CR Write-only –
0x0004 Mode Register UART_MR Read/Write 0x0
0x0008 Interrupt Enable Register U ART_IER Write-only –
0x000C Interrupt Disable Register UART_IDR Write-only –
0x0010 Interrupt Mask Register UART_IMR Read-only 0x0
0x0014 Status Register UART_SR Read-only –
0x0018 Receive Holding Register UART_ RHR Read-only 0x0
0x001C Transmit Hol ding Register UART_THR Write-only –
0x0020 Baud Rate Generator Registe r UART_BRGR Read/Write 0x0
0x0024 Reserved – – –
0x0028–0x003C Reserved – – –
0x0040–0x00E8 Reserved – – –
0x00EC–0x00FC Reserved – – –
0x0100–0x0128 Reserved for PDC registers – – –
769
SAM4S Series [DATASHEET]
Atmel-11100K-ATARM-SAM4S-Datasheet_09-Jun-15
35.6.1 UART Control Register
Name: UART_CR
Address: 0x400E0600 (0), 0x400E0800 (1)
Access: Write-only
• RSTRX: Reset Receiver
0: No effect.
1: The receiver logic is reset and disabled. If a character is being received, the reception is aborted.
• RSTTX: Reset Transmitter
0: No effect.
1: The transmitter logic is reset and disabled. If a character is being transmitted, the transmission is aborted.
• RXEN: Receiver Enable
0: No effect.
1: The receiver is enabled if RXDIS is 0.
• RXDIS: Receiver Disable
0: No effect.
1: The receiver is disabled. If a character is being processed and RSTRX is not set, the character is completed before the
receiver is stopped.
• TXEN: Transmitter Enable
0: No effect.
1: The transmitter is enabled if TXDIS is 0.
• TXDIS: Transmitter Disable
0: No effect.
1: The transmitter is disabled. If a character is being processed and a character has bee n written in the UART_THR and
RSTTX is not set, both characters are completed before the transmitter is stopped.
• RSTSTA: Reset Status
0: No effect.
1: Resets the status bits PARE, FRAME and OVRE in the UART_SR.
31 30 29 28 27 26 25 24
––––––––
23 22 21 20 19 18 17 16
––––––––
15 14 13 12 11 10 9 8
–––––––RSTSTA
76543210
TXDIS TXEN RXDIS RXEN RSTTX RSTRX – –
SAM4S Series [DATASHEET]
Atmel-11100K-ATARM-SAM4S-Datasheet_09-Jun-15
770
35.6.2 UART Mode Register
Name: UART_MR
Address: 0x400E0604 (0), 0x400E0804 (1)
Access: Read/Write
•PAR: Parity Type
• CHMODE: Channel Mode
31 30 29 28 27 26 25 24
––––––––
23 22 21 20 19 18 17 16
––––––––
15 14 13 12 11 10 9 8
CHMODE – – PAR –
76543210
––––––––
Value Name Description
0 EVEN Even Parity
1ODD Odd Parity
2SPACE Space: parity forced to 0
3MARK Mark: parity forced to 1
4NO No parity
Value Name Description
0 NORMAL Normal mode
1 AUTOMATIC Automatic echo
2 LOCAL_LOOPBACK Loca l loopback
3 REMOTE_LOOPBACK Remote loopback
771
SAM4S Series [DATASHEET]
Atmel-11100K-ATARM-SAM4S-Datasheet_09-Jun-15
35.6.3 UART Interrupt Enable Register
Name: UART_IER
Address: 0x400E0608 (0), 0x400E0808 (1)
Access: Write-only
The following configuration values are valid for all listed bit names of this register:
0: No effect.
1: Enables the corresponding interrupt.
• RXRDY: Enable RXRDY Interrupt
• TXRDY: Enable TXRDY Interrupt
• ENDRX: Enable End of Receive Transfer Interrupt
• ENDTX: Enable End of Transmit Interrupt
• OVRE: Enable Overrun Error Interrupt
• FRAME: Enable Framing Error Interrupt
• PARE: Enable Parity Error Interrupt
• TXEMPTY: Enable TXEMPTY Interrupt
• TXBUFE: Enable Buffer Empty Interrupt
• RXBUFF: Enable Buffer Full Interrupt
31 30 29 28 27 26 25 24
––––––––
23 22 21 20 19 18 17 16
––––––––
15 14 13 12 11 10 9 8
– – – RXBUFF TXBUFE – TXEMPTY –
76543210
PARE FRAME OVRE ENDTX ENDRX – TXRDY RXRDY
SAM4S Series [DATASHEET]
Atmel-11100K-ATARM-SAM4S-Datasheet_09-Jun-15
772
35.6.4 UART Interrupt Disable Register
Name: UART_IDR
Address: 0x400E060C (0), 0x400E080C (1)
Access: Write-only
The following configuration values are valid for all listed bit names of this register:
0: No effect.
1: Disables the corresponding interrupt.
• RXRDY: Disable RXRDY Interrupt
• TXRDY: Disable TXRDY Interrupt
• ENDRX: Disable End of Receive Transfer Interrupt
• ENDTX: Disable End of Transmit Interrupt
• OVRE: Disable Overrun Error Interrupt
• FRAME: Disable Framing Error Interrupt
• PARE: Disable Parity Error Interrupt
• TXEMPTY: Disable TXEMPTY Interrupt
• TXBUFE: Disable Buffer Empty Interrupt
• RXBUFF: Disable Buffer Full Interrupt
31 30 29 28 27 26 25 24
––––––––
23 22 21 20 19 18 17 16
––––––––
15 14 13 12 11 10 9 8
– – – RXBUFF TXBUFE – TXEMPTY –
76543210
PARE FRAME OVRE ENDTX ENDRX – TXRDY RXRDY
773
SAM4S Series [DATASHEET]
Atmel-11100K-ATARM-SAM4S-Datasheet_09-Jun-15
35.6.5 UART Interrupt Mask Register
Name: UART_IMR
Address: 0x400E0610 (0), 0x400E0810 (1)
Access: Read-only
The following configuration values are valid for all listed bit names of this register:
0: The corresponding interrupt is disabled.
1: The corresponding interrupt is enabled.
• RXRDY: Mask RXRDY Interrupt
• TXRDY: Disable TXRDY Interrupt
• ENDRX: Mask End of Receive Transfer Interrupt
• ENDTX: Mask End of Transmit Interrupt
• OVRE: Mask Overrun Error Interrupt
• FRAME: Mask Framing Error Interrupt
• PARE: Mask Parity Error Interrupt
• TXEMPTY: Mask TXEMPTY Interrupt
• TXBUFE: Mask TXBUFE Interrupt
• RXBUFF: Mask RXBUFF Interrupt
31 30 29 28 27 26 25 24
––––––––
23 22 21 20 19 18 17 16
––––––––
15 14 13 12 11 10 9 8
– – – RXBUFF TXBUFE – TXEMPTY –
76543210
PARE FRAME OVRE ENDTX ENDRX – TXRDY RXRDY
SAM4S Series [DATASHEET]
Atmel-11100K-ATARM-SAM4S-Datasheet_09-Jun-15
774
35.6.6 UART Status Register
Name: UART_SR
Address: 0x400E0614 (0), 0x400E0814 (1)
Access: Read-only
• RXRDY: Receiver Ready
0: No character has been received since the last read of the UART_RHR, or the receiver is disabled.
1: At least one complete character has been received, transferred to UART_RHR and not yet read.
• TXRDY: Transmitter Ready
0: A character has been written to UART_THR and not yet transferred to the internal shift register, or the transmitter is
disabled.
1: There is no character written to UART_THR not yet transferred to the internal shift register.
• ENDRX: End of Receiver Transfer
0: The end of transfer signal from the receiver PDC channel is inactive.
1: The end of transfer signal from the receiver PDC channel is active.
• ENDTX: End of Transmitter Transfer
0: The end of transfer signal from the transmitter PDC channel is inactive.
1: The end of transfer signal from the transmitter PDC channel is active.
• OVRE: Overrun Error
0: No overrun error has occur re d sin ce the las t R STSTA.
1: At least one overrun error has occurred since the last RSTSTA.
•FRAME: Framing Error
0: No framing error has occurred since the last RSTSTA.
1: At least one framing error has occurred since the last RSTSTA.
• PARE: Parity Error
0: No parity error has occurred since the last RSTSTA.
1: At least one parity error has occurred since the last RSTSTA.
• TXEMPTY: Transmitter Empty
0: There are characters in UART_THR, or characters being processed by the transmitter , or the transmitter is disabled.
1: There are no characters in UART_THR and there are no characters being processed by the transmitter.
31 30 29 28 27 26 25 24
––––––––
23 22 21 20 19 18 17 16
––––––––
15 14 13 12 11 10 9 8
– – – RXBUFF TXBUFE – TXEMPTY –
76543210
PARE FRAME OVRE ENDTX ENDRX – TXRDY RXRDY
775
SAM4S Series [DATASHEET]
Atmel-11100K-ATARM-SAM4S-Datasheet_09-Jun-15
• TXBUFE: Transmission Buffer Empty
0: The buffer empty signal from the transmitter PDC channel is inactive.
1: The buffer empty signal from the transmitter PDC channel is active.
• RXBUFF: Receive Buffer Full
0: The buffer full signal from the receiver PDC channel is inactive.
1: The buffer full signal from the receiver PDC channel is active.
SAM4S Series [DATASHEET]
Atmel-11100K-ATARM-SAM4S-Datasheet_09-Jun-15
776
35.6.7 UART Receiver Holding Register
Name: UART_RHR
Address: 0x400E0618 (0), 0x400E0818 (1)
Access: Read-only
• RXCHR: Received Character
Last received character if RXRDY is set.
31 30 29 28 27 26 25 24
––––––––
23 22 21 20 19 18 17 16
––––––––
15 14 13 12 11 10 9 8
––––––––
76543210
RXCHR
777
SAM4S Series [DATASHEET]
Atmel-11100K-ATARM-SAM4S-Datasheet_09-Jun-15
35.6.8 UART Transmit Holding Register
Name: UART_THR
Address: 0x400E061C (0), 0x400E081C (1)
Access: Write-only
• TXCHR: Chara cte r to be Transmi tt ed
Next character to be transmitted after the current character if TXRDY is not set.
31 30 29 28 27 26 25 24
––––––––
23 22 21 20 19 18 17 16
––––––––
15 14 13 12 11 10 9 8
––––––––
76543210
TXCHR
SAM4S Series [DATASHEET]
Atmel-11100K-ATARM-SAM4S-Datasheet_09-Jun-15
778
35.6.9 UART Baud Rate Generator Register
Name: UART_BRGR
Address: 0x400E0620 (0), 0x400E0820 (1)
Access: Read/Write
• CD: Clock Divisor
0: Baud rate clock is disabled
1 to 65,535:
31 30 29 28 27 26 25 24
––––––––
23 22 21 20 19 18 17 16
––––––––
15 14 13 12 11 10 9 8
CD
76543210
CD
CD fperipheral clock
16 Baud Rate×
---------------------------------- =
779
SAM4S Series [DATASHEET]
Atmel-11100K-ATARM-SAM4S-Datasheet_09-Jun-15
36. Universal Synchronous Asynchronous Receiver Transceiver (USART)
36.1 Description
The Universal Synchronous Asynchronous Receiver Transceiver (USART) provides one full duplex universal
synchronous asynchronous serial link. Data frame format is widely programmable (data length, parity, number of
stop bits) to support a maximum of standards. The receiver implements parity error, framing error and overrun
error detection. The receiver time-out enables handling variable-length frames and the transmitter timeguard
facilitates communications with slow remote devices. Multidrop communications are also supported through
address bit handling in reception and transmission.
The USART features three test modes: Remote loopback, Local loopback and Automatic echo.
The USART supports specific operating modes providing interfaces on RS485, and SPI buses, with ISO7816 T =
0 or T = 1 smart card slots, infrared tran sceivers and connection to modem ports. The hardware handshaking
feature enables an out-of-band flow control by automatic management of the pins RTS and CTS.
The USART supports the connection to the Peripheral DMA Controller, which enables data transfers to the
transmitter and from the receiver. The PDC provides chained buffer management without any intervention of the
processor.
36.2 Embedded Characteristics
Programmable Baud Rate Generator
5- to 9-bit Full-duplex Synchronous or Asynchronous Serial Communications
1, 1.5 or 2 Stop Bits in Asynchronous Mode or 1 or 2 Stop Bits in Synchronous Mode
Parity Generation and Error Detection
Framing Error Detection, Overrun Error Detection
Digital Filter on Receive Line
MSB- or LSB-first
Optional Break Generation and Detection
By 8 or by 16 Over-sampling Receiver Frequency
Optional Hardware Handshaking RTS-CTS
Optional Modem Signal Management DTR-DSR-DCD-RI
Receiver Time-out and Transmitter Timeguard
Optional Multidrop Mode with Address Generation and Detection
RS485 with Driver Control Signal
ISO7816, T = 0 or T = 1 Protocols for Interfacing with Smart Cards
NACK Handling, Error Counter with Repetition and Iteration Limit
IrDA Modulation and Demodulation
Communication at up to 115.2 kbit/s
SPI Mode
Master or Slave
Serial Clock Programmable Phase and Polarity
SPI Serial Clock (SCK) Frequency up to fperipheral clock/6
Test Modes
Remote Loopback, Local Loopback, Automatic Echo
Supports Connection of:
Two Peripheral DMA Controller Channels (PDC)
SAM4S Series [DATASHEET]
Atmel-11100K-ATARM-SAM4S-Datasheet_09-Jun-15
780
Offers Buffer Transfer without Processor Intervention
Register Write Protection
781
SAM4S Series [DATASHEET]
Atmel-11100K-ATARM-SAM4S-Datasheet_09-Jun-15
36.3 Block Diagram
Figure 36-1. USART Block Diagram
36.4 I/O Lines Description
(Peripheral)
DMA Controller
Channel
Channel
Interrupt
Controller
Receiver
USART Interrupt
RXD
TXD
SCK
USART PIO
Controller
CTS
RTS
DTR
DSR
DCD
RI
Transmitter
Modem
Signals
Control
Baud Rate
Generator
PMC
Peripheral clock
APB
Peripheral clock/DIV
Bus clock Bridge
User
Interface
Table 36-1. I/O Line Description
Name Descriptio n Type Active Level
SCK Serial Clock I/O —
TXD Transmit Serial Data
or Master Out Slave In (MOSI) in SPI master mode
or Master In Slave Out (MISO) in SPI slave mode I/O —
RXD Receive Serial Data
or Master In Slave Out (MISO) in SPI master mode
or Master Out Slave In (MOSI) in SPI slave mode Input —
RI Ring Indicator Input Lo w
DSR Data Set Ready Input Low
DCD Dat a Carrier Detect Input Low
DTR Data Terminal Ready Output Low
CTS Clear to Send
or Slave Select (NSS) in SPI slave mode Input Low
RTS Request to Send
or Slave Select (NSS) in SPI master mode Output Low
SAM4S Series [DATASHEET]
Atmel-11100K-ATARM-SAM4S-Datasheet_09-Jun-15
782
36.5 Product Dependencies
36.5.1 I/O Lines
The pins used for interfacing the USART may be multiplexed with the PIO lines. The programmer must first
program the PIO controller to assign the desired USART pins to their per iphera l function. If I/O lines of the USART
are not used by the application, they can be used for other purposes by the PIO Controller.
To prevent the TXD line from falling when the USART is disabled, the use of an internal pull up is mandatory. If the
hardware handshaking feature or Modem mode is used, the internal pull up on TXD must also be enabled.
All the pins of the modems may or may not be implemented on the USART. Only USART1 fully equipped with all
the modem signals. On USARTs not equ ipped with the corresp onding pin, the associated contr ol bits and statuses
have no effect on the behavior of the USART.
36.5.2 Power Management
The USART is not continuously clocked. The programmer must first enable the USART clock in the Power
Management Cont roller (PMC) before using the USART. However, if th e application does not require USART
operations, the USART clock can be stopped when not needed and be restarted later. In this case, the USART will
resume its operations where it left off.
36.5.3 Interrupt Sources
The USART interrupt line is connected on one of the internal sources of the Interrupt Controller. Using the USART
interrupt requires the Interrupt Controller to be programmed first.
Table 36-2. I/O Lines
Instance Signal I/O Line Periphera l
USART0 CTS0 PA8 A
USART0 RTS0 PA7 A
USART0 RXD0 PA5 A
USART0 SCK0 PA2 B
USART0 TXD0 PA6 A
USART1 CTS1 PA25 A
USART1 DCD1 PA26 A
USART1 DSR1 PA28 A
USART1 DTR1 PA27 A
USART1 RI1 PA29 A
USART1 RTS1 PA24 A
USART1 RXD1 PA21 A
USART1 SCK1 PA23 A
USART1 TXD1 PA22 A
Table 36-3. Peripheral IDs
Instance ID
USART0 14
USART1 15
783
SAM4S Series [DATASHEET]
Atmel-11100K-ATARM-SAM4S-Datasheet_09-Jun-15
36.6 Functional Description
36.6.1 Baud Rate Generator
The baud rate generato r provides the bit period clock, also named the ba ud rate clock, to both th e receive r and the
transmitter.
The baud rate generator clock source is selected by configuring the USCLKS field in the USART Mode Register
(US_MR) to one of the following:
The peripher al cloc k
A division of the peripheral clock, where the divider is product-dependent, but generally set to 8
The external clock, available on the SCK pin
The baud rate generator is based upon a 16-bit divider, which is programmed with the CD field of the Baud Rate
Generator register (US_BRGR). If a 0 is written to CD, the baud rate generator does not generate any clock. If a 1
is written to CD, the divider is bypassed and becomes inactive.
If the external SCK clock is selected, the duration of the low and high levels of the signal provided on the SCK pin
must be longer than a peripheral clo ck period. The frequency of the signal provided on SCK must be at least 3
times lower than the frequ ency p rovided on the peripher al clock in USART mode (f ield USART_MODE differs from
0xE or 0xF), or 6 times lower in SPI mode (field USART_MODE equals 0xE or 0xF).
Figure 36-2. Baud Rate Generator
36.6.1.1 Baud Rate in Asynchronous Mode
If the USART is programmed to operate in Asynchronous mod e, th e sele cted clock is first divide d by CD, wh ich is
field programmed in the US_BRGR. The resulting clock is provided to the receiver as a sampling clock and then
divided by 16 or 8, depending on how th e OVER bit in the US_MR is programmed.
If OVER is set, the receiver sampling is eight times higher than the baud rate clock. If OVER is cleared, the
sampling is performed at 16 times the baud rate clock.
The baud rate is calcu la te d as pe r th e fo llowin g form u la:
This gives a maximum baud rate of peripheral clock divided by 8, assum ing that the peripheral clock is the highest
possible clock and that the OVER bit is set.
Peripheral clock/DIV 16-bit Counter
0
Baud Rate
Clock
CD
CD
Sampling
Divider
0
1
>1
Sampling
Clock
Reserved
Peripheral clock
USCLKS
OVER SYNC
SYNC
USCLKS = 3
1
0
2
30
1
0
1
FIDI
SCK
(CLKO = 1)
SCK
(CLKO = 0)
Baudrate SelectedClock
82 Over–()CD()
--------------------------------------------
=
SAM4S Series [DATASHEET]
Atmel-11100K-ATARM-SAM4S-Datasheet_09-Jun-15
784
Baud Rate Calculation Examp le
Table 36-4 shows calculations of CD to obtain a baud rate at 38,400 bit/s for different source clock frequencies.
This table also shows the actual resulting baud ra te and the error.
The baud rate is calcu la te d with the following formula:
The baud rate error is calcula ted with the following formula. It is not recommended to work with an error higher
than 5%.
36.6.1.2 Fractional Baud Rate in Asynchronous Mode
The baud rate generator is subject to the following limitation: the output frequency changes only by integer
multiples of the reference fre quency. An a pproa ch to th is problem is to integrate a fraction al N clo ck gener ator that
has a high resolution. The generator architecture is modified to obtain baud rate changes by a fraction of the
reference source clock. This fractional part is programmed with the FP field in the US_BRGR. If FP is not 0, the
Table 36-4. Baud Rate Example (OVER = 0)
Source Clock
(MHz) Expected Baud Rate
(bit/s) Calculation Result CD Actual Baud Rate
(bit/s) Error
3,686,400 38,400 6.00 6 38,400.00 0.00%
4,915,200 38,400 8.00 8 38,400.00 0.00%
5,000,000 38,400 8.14 8 39,062.50 1.70%
7,372,800 38,400 12.00 12 38,400.00 0.00%
8,000,000 38,400 13.02 13 38,461.54 0.16%
12,000,000 38,400 19.53 20 37,500.00 2.40%
12,288,000 38,400 20.00 20 38,400.00 0.00%
14,318,180 38,400 23.30 23 38,908.10 1.31%
14,745,600 38,400 24.00 24 38,400.00 0.00%
18,432,000 38,400 30.00 30 38,400.00 0.00%
24,000,000 38,400 39.06 39 38,461.54 0.16%
24,576,000 38,400 40.00 40 38,400.00 0.00%
25,000,000 38,400 40.69 40 38,109.76 0.76%
32,000,000 38,400 52.08 52 38,461.54 0.16%
32,768,000 38,400 53.33 53 38,641.51 0.63%
33,000,000 38,400 53.71 54 38,194.44 0.54%
40,000,000 38,400 65.10 65 38,461.54 0.16%
50,000,000 38,400 81.38 81 38,580.25 0.47%
BaudRate fperipheral clock CD 16×⁄=
Error 1ExpectedBaudRate
ActualBaudRate
---------------------------------------------------


–=
785
SAM4S Series [DATASHEET]
Atmel-11100K-ATARM-SAM4S-Datasheet_09-Jun-15
fractional part is activated. The resolution is one eighth of the clock divider. This feature is only available when
using USART normal mode. The fractional baud rate is calculated using the following formula:
The modified arc hit ec tu re is pres en te d in the followin g Figure 36-3.
Figure 36-3. Fractional Baud Rate Generator
36.6.1.3 Baud Rate in Synchronous Mode or SPI Mode
If the USART is programmed to o per ate in Synchronous mode, the selected clock is simply divided by the field CD
in the US_BRGR.
In Synchronous mode, if the ex ternal clock is selected (USCLKS = 3), the clock is provided directly by the signal on
the USART SCK pin. No division is active. The value written in US_BRGR has no effect. The external clock
frequency must be at least 3 times lower than the system clock. In Synchronous mode master (USCLKS = 0 or 1,
CLKO set to 1), the receive part limits the SCK maximum frequency tofperipheral clock/3 in USART mode, or fperipheral
clock/6 in SPI mode.
When either the external clock SCK or the internal clock divided (peripheral clock/DIV) is selected, the value
programmed in CD must be even if the user has to ensure a 50:50 mark/space ratio on the SCK pin. When the
peripheral clock is selected, the baud rate generator ensures a 50:50 duty cycle on the SCK pin, even if the value
programmed in CD is odd.
Baudrate SelectedClock
82 Over–()CD FP
8
-------
+




----------------------------------------------------------------
=
MCK/DIV
16-bit Counter
0
Baud Rate
Clock
CD
CD
Sampling
Divider
0
1
>1
Sampling
Clock
Reserved
MCK
USCLKS
OVER SYNC
SYNC
USCLKS = 3
1
0
2
3
0
1
0
1
FIDI
Glitch-free
Logic
Modulus
Control
FP
FP SCK
(CLKO = 1)
SCK
(CLKO = 0)
BaudRate SelectedClock
CD
--------------------------------------
=
SAM4S Series [DATASHEET]
Atmel-11100K-ATARM-SAM4S-Datasheet_09-Jun-15
786
36.6.1.4 Baud Rate in ISO 7816 Mode
The ISO7816 specification defines the bit rate with the following formula:
where:
B is the bit rate
Di is the bit-rate adjustment factor
Fi is the clock frequency division factor
f is the ISO7816 clock frequency (Hz)
Di is a binary value encoded on a 4-bit field, named DI, as represented in Table 36-5.
Fi is a binary value encoded on a 4-bit field, named FI, as represented in Table 36-6.
Table 36-7 shows the resulting Fi/Di ratio, which is the ratio between the ISO7816 clock and the baud rate clock.
If the USART is configured in ISO7816 mode, the clock selected by the USCLKS field in US_MR is first divided by
the value programmed in the field CD in the US_BRGR. The resulting clock can be provided to the SCK pin to feed
the smart card clock inputs. This means that the CLKO bit can be set in US_MR.
This clock is then divided by the value programmed in the FI_DI_RATIO field in the FI_DI_Ratio register
(US_FIDI). This is performed by the Sampling Divider, which performs a division by up to 2047 in ISO7816 mode.
The non-integer va lue s of the Fi/Di Ratio ar e no t sup ported and the user must program the FI_DI_RAT IO fiel d to a
value as close as possible to the expected value.
The FI_DI _RATIO field r esets to the value 0x174 (372 in decimal) and is the most common divider between the
ISO7816 clock and the bit rate (Fi = 372, Di = 1).
Figure 36-4 shows the relation between the Elementary Time Unit, corr esponding to a bit time, and the ISO 7816
clock.
BDi
Fi
------f×=
Table 36-5. Binary and Decimal Values for Di
DI field 0001 0010 0011 0100 0101 0110 1000 1001
Di (decimal) 1 2 4 8 16 32 12 20
Table 36-6. Binary and Decimal Values for Fi
FI field 0000 0001 0010 0011 0100 0101 0110 1001 1010 1011 1100 1101
Fi (decimal) 372 372 558 744 1116 1488 1860 512 768 1024 1536 2048
Table 36-7 . Possible Values for the Fi/Di Ratio
Fi/Di 372 558 744 1116 1488 1806 512 768 1024 1536 2048
1 372 558 744 1116 1488 1860 512 768 1024 1536 2048
2 186 279 372 558 744 930 256 384 512 768 1024
4 93 139.5 186 279 372 465 128 192 256 384 512
8 46.5 69.75 93 139.5 186 232.5 64 96 128 192 256
16 23.25 34.87 46.5 69.75 93 116.2 32 48 64 96 128
32 11.62 17.43 23.25 34.87 46.5 58.13 16 24 32 48 64
12 31 46.5 62 93 124 155 42.66 64 85.33 128 170.6
20 18.6 27.9 37.2 55.8 74.4 93 25.6 38.4 51.2 76.8 102.4
787
SAM4S Series [DATASHEET]
Atmel-11100K-ATARM-SAM4S-Datasheet_09-Jun-15
Figure 36-4. Elementary Time Unit (ETU)
36.6.2 Receiver and Transmitter Control
After reset, the receiver is disabled. The user must enable the receiver by setting the RXEN bit in the Control
register (US_CR). However, the receiver registers can be programmed before the receiver clock is enabled.
After reset, the transmitter is disabled. T he user must enable it by setting the TXEN bit in the US_CR. However,
the transmitter registers can be programmed before being enabled.
The receiver and the transmitter can be enabled together or independently.
At any time, the software can perform a reset on the receiver or the transmitter of the USART by setting the
corresponding bit, RSTRX and RSTTX respectively, in the US_CR. The software resets clear the status flag and
reset internal state machines but the user interface configuration registers hold the value configured prior to
software reset. Regardless of what the receiver or the transmitter is performing, the communication is immediately
stopped.
The user can also independently disable the receiver or the transmitter by setting RXDIS and TXDIS respectively
in the US_CR. If t he receiver is disabled dur ing a charac ter recep tion, the USART waits until the end of rece ption
of the current character, then the reception is stopped. If the transmitter is disabled while it is operating, the
USART waits the end of transmission of both the current character and character being stored in the Transmit
Holding register (US_THR). If a timeguard is programmed, it is handled normally.
36.6.3 Synchronous and Asynchronous Modes
36.6.3.1 Transmitter Operations
The transmitter performs the same in both Synchronous and Asynchronous operating modes (SYNC = 0 or SYNC
= 1). One start bit, up to 9 data bits, one optional parity bit and up to two stop bits are successively shifted out on
the TXD pin at each falling edge of the programmed serial clock.
The number of data bits is selected by the CHRL field and the MODE 9 bit in U S_MR. Nine bits are selected by
setting the MODE 9 bit regardless of th e CHRL field. The pa rity bit is set according to the PAR field in US_MR. The
even, odd, space, marked or none parity bit can be configured. The MS BF field in the US_MR configures which
data bit is sent first. If written to 1, the most significant bit is sent first. If written to 0, the less significant bit is sent
first. The number of stop bits is selected by the NBSTOP field in the US_M R. The 1.5 stop bit is supported in
Asynchronous mode only.
1 ETU
ISO7816 Clock
on SCK
ISO7816 I/O Line
on TXD
FI_DI_RATIO
ISO7816 Clock Cycles
SAM4S Series [DATASHEET]
Atmel-11100K-ATARM-SAM4S-Datasheet_09-Jun-15
788
Figure 36-5. Character Transmit
The characters are sent by writing in the Transmit Hold ing register (US_THR). The transmitter reports two status
bits in the Channel Status regi ster (US_CSR): TXRDY (Transmitter Read y), which indicates that US_THR is empty
and TXEMPTY, which indica tes that a ll th e characte rs written in US_ THR have been processed. When the curr ent
character processing is completed, the last character written in US_THR is transferred into the Shift register of the
transmitter and US_THR becomes empty, thus TXRDY rises.
Both TXRDY and TXEMPTY bits are low when the transmitter is disabled. Writing a character in US_THR while
TXRDY is low has no effect and the written character is lost.
Figure 36-6. Transmitter Status
36.6.3.2 Manchester Encoder
When the Manchester encoder is in use, characters transmitted through the USART are encoded based on
biphase Manchester II format. To enable this mode, set the MAN bit in the US_MR to 1. Depending on polarity
configuratio n, a logic level (zero or one), is transmitt ed as a coded signal one-to-zero or zero-to-one. Thus, a
transition alwa ys occurs at th e midpoi nt of each bit time. It consumes mor e bandwidth than the original NRZ signal
(2x) but the receiver has more er ror control since the expected input must show a change at the ce nter of a bit cell.
An example of Man chester enco ded sequence i s: the byte 0xB1 o r 10110001 encodes to 10 01 10 10 01 01 01 10,
assuming the default polarity of the encoder. Figure 36-7 illustrates this coding scheme.
Figure 36-7. NRZ to Manchester Encoding
The Manchester encoded character can also be encapsulated by adding bo th a configurable preamble and a start
frame delimiter pattern. Depending on the configuration, the preamble is a training sequence, composed of a
D0 D1 D2 D3 D4 D5 D6 D7
TXD
Start
Bit Parity
Bit Stop
Bit
Example: 8-bit, Parity Enabled One Stop
Baud Rate
Clock
D0 D1 D2 D3 D4 D5 D6 D7
TXD
Start
Bit Parity
Bit Stop
Bit
Baud Rate
Clock
Start
Bit
Write
US_THR
D0 D1 D2 D3 D4 D5 D6 D7 Parity
Bit Stop
Bit
TXRDY
TXEMPTY
NRZ
encoded
data
Manchester
encoded
data
10110001
Txd
789
SAM4S Series [DATASHEET]
Atmel-11100K-ATARM-SAM4S-Datasheet_09-Jun-15
predefined pattern with a programmable length from 1 to 15 bit times. If the preamble length is set to 0, the
preamble waveform is not generated prior to any character. The preamble pattern is chosen among the following
sequences: ALL_ONE, ALL_ZERO, ONE_ZERO or ZERO_ONE, writing the field TX_PP in the US_MAN register,
the field TX_PL is used to configure the preamble length. Figure 36-8 illus trates and defines the valid patterns. To
improve flexibility, the encoding scheme can be configured using the TX_MPOL field in the US_MAN register. If
the TX_MPOL field is set to zero (default), a logic zero is encoded with a zero-to-one transition and a logic one is
encoded with a one-to-zero transition. If the TX_MPOL field is set to 1, a logic one is encoded with a one-to-zero
transition and a logic zero is encoded with a zero-to-one transition.
Figure 36-8. Preamble Patterns, Default Polarity Assumed
A start frame delimiter is to be configured using the ONEBIT bit in the US_MR. It consists of a user- defined patter n
that indicates the beginning of a valid data. Figure 36-9 illustrates these patterns. If the start frame delimiter, also
known as the start bit, is one bit, (ONEBIT = 1), a lo gic zero is Manchester encode d and indicates that a ne w
character is being sent serially on the line. If the start frame delimiter is a synchronization pattern also referred to
as sync (ONEBIT to 0), a sequence of three bit times is sent serially on the line to indicate the start of a new
character. The sync waveform is in itself an invalid Manchester waveform as the transition occurs at the middle of
the second bit time. Two distinct sync patterns ar e used: the command sync and the data sync. The co mmand
sync has a logic one level for one and a half bit times, then a transition to logic zero for the second one and a half
bit times. If the MODSYNC bit in the US_MR is set to 1, the next character is a command. If it is set to 0, the next
character is a data. When direct memory access is used, the MODSYNC field can be immediately updated with a
modified character located in memory. To enable this mode, VAR_SYNC bit in US_MR must be set to 1. In this
case, the MODSYNC bit in the US_MR is bypassed and the sync configuration is held in the TXSYNH in the
US_THR. The USART character format is modified and includes sync information.
Manchester
encoded
data Txd SFD DATA
8-bit width "ALL_ONE" Preamble
Manchester
encoded
data Txd SFD DATA
8-bit width "ALL_ZERO" Preamble
Manchester
encoded
data Txd SFD DATA
8-bit width "ZERO_ONE" Preamble
Manchester
encoded
data Txd SFD DATA
8-bit width "ONE_ZERO" Preamble
SAM4S Series [DATASHEET]
Atmel-11100K-ATARM-SAM4S-Datasheet_09-Jun-15
790
Figure 36-9. Start Frame Delimiter
Drift Compensation
Drift compensation is available only in 16X oversampling mode. An hardware recovery system allows a larger
clock drift. To enable the hardware system, the bit in the USART_MAN register must be set. If the RXD edge is
one 16X clock cyc le from th e exp ected edge , this is co nsidered as normal jitter and no corrective actions is taken.
If the RXD event is between 4 and 2 clock cycles before the expected edge, then the current period is shortened
by one clock cycle. If the RXD event is between 2 and 3 clock cycles after the expected edge, then the current
period is lengthened by one clock cycle. These intervals are considered to be drift and so corrective actions are
automatically taken.
Figure 36-10. Bit Resynchronization
36.6.3.3 Asynchronous Receiver
If the USART is programmed in Asynchronous op erating mode (SYNC = 0), the receiver oversamples the RXD
input line. The oversampling is e ither 16 or 8 times the b aud rate clock, d epending o n the OVER b it in the US_MR.
The receiver samples the RXD line. If the line is sampled during one half of a bit time to 0, a start bit is detected
and data, parity and stop bits are successively sampled on the bit rate clock.
If the oversampling is 16 (OVER = 0), a start is detected at the eighth sample to 0. Data bits, parity bit and stop bit
are assumed to have a duration corresponding to 16 oversampling clock cycle s. If the ov ersa mplin g is 8 (OVER =
1), a start bit is detected at the fourth sample to 0. Data bits, parity bit and stop bit are assumed to have a duration
corresponding to 8 oversampling clock cycles.
Manchester
encoded
data Txd
SFD
DATA
One bit start frame delimiter
Preamble Length
is set to 0
Manchester
encoded
data Txd
SFD
DATA
Command Sync
start frame delimiter
Manchester
encoded
data Txd
SFD
DATA
Data Sync
start frame delimiter
RXD
Oversampling
16x Clock
Sampling
point
Expected edge
Tolerance
Synchro.
Jump Sync
Jump
Synchro.
Error
Synchro.
Error
791
SAM4S Series [DATASHEET]
Atmel-11100K-ATARM-SAM4S-Datasheet_09-Jun-15
The number of data bits, first bit sent and Parity mode are selected by the same fields and bits as the transmitter,
i.e., respectively CHRL, M ODE9, MSBF and PAR. For the synchronization m echanism only, the number of stop
bits has no effect on the receiver as it considers only one stop bit, regardless of the field NBSTOP, so that
resynchronization between the receiver and the transmitter can occur. Moreover, as soon as the stop bit is
sampled, the receiver starts looking for a new start bi t so that resynchronization can also be accomplished when
the transmitter is operating with one stop bit.
Figure 36-11 and Figure 36-12 illustrate start detection and character reception when USART operates in
Asynchronous mode.
Figure 36-11. Asynchronous Start Detection
Figure 36-12. Asyn chronous Character Rec eption
36.6.3.4 Manchester Decoder
When the MAN bit in the US_MR is set to 1, the Manchester decoder is enabled. The decoder performs both
preamble and start frame delimiter detection. One input line is dedicated to Manchester encoded input data.
An optional preamble sequence can be defined, its length is user-defined and totally independent of the emitter
side. Use RX_PL in US_MAN register to co nfigure th e length of the preamble sequence. If the length is set to 0, no
preamble is detected an d the function is disabled. In addition, the polarity of the input stream is programmable with
RX_MPOL bit in US_MAN register. Depending on the desired application the preamble pattern matching is to be
defined via the RX_PP field in US_MAN. See Figure 36-8 for available preamble patterns.
Unlike preamble, the start frame delimiter is shared between Manchester Encoder and Decoder. So, if ONEBIT
field is set to 1 , o n ly a zer o en co de d Ma n ch est er ca n b e de te ct ed as a valid star t fr am e de lim ite r. If O NEBI T is se t
Sampling
Clock (x16)
RXD
Start
Detection
Sampling
Baud Rate
Clock
RXD
Start
Rejection
Sampling
12345678
123456701234
123456789 10111213141516D0
Sampling
D0 D1 D2 D3 D4 D5 D6 D7
RXD
Parity
Bit Stop
Bit
Example: 8-bit, Parity Enabled
Baud Rate
Clock
Start
Detection
16
samples 16
samples 16
samples 16
samples 16
samples 16
samples 16
samples 16
samples 16
samples 16
samples
SAM4S Series [DATASHEET]
Atmel-11100K-ATARM-SAM4S-Datasheet_09-Jun-15
792
to 0, only a sync pattern is detected as a valid start frame delim iter. Decoder operates by detecting tra nsition on
incoming stream. If RXD is sampled during one quarter of a bit time to zero, a start bit is detected. See Figure 36-
13. The sample pulse rejection mechanism applies.
Figure 36-13. Asynchro nous Start Bit Detection
The receiver is activated and starts preamble and frame delimiter detection, sampling the data at one quarter and
then three quarters. If a valid preamble pattern or start frame delimiter is detected, th e receiver continues decoding
with the same synchronization. If the strea m does not match a valid pattern or a valid start frame de limiter, the
receiver resynchronizes on the next valid edge.The minimum time threshold to estimate the bit value is three
quarters of a bit time.
If a valid preamble (if used) followed with a valid start frame delimiter is detected, the incoming stream is decoded
into NRZ data and passed to USART for processing. Figure 36-14 illustrates Manchester pattern mismatch. When
incoming data stream is passe d to the USART, the receiv er is also able to detect Manchester code violation. A
code violation is a la ck of transition in the mid dle o f a bit cell. In this case, MANE flag in the US_CSR is raised. It is
cleared by writing a 1 to the RSTSTA in the US_CR. See Figure 36-15 for an example of Manchester error
detection during data phase.
Figure 36-14. Preamble Pattern Mismatch
Figure 36-15. Manchester Error Flag
Manchester
encoded
data Txd
1234
Sampling
Clock
(16 x)
Start
Detection
Manchester
encoded
data Txd SFD DATA
Preamble Length is set to 8
Preamble Mismatch
invalid pattern
Preamble Mismatch
Manchester coding error
Manchester
encoded
data Txd
SFD
Preamble Length
is set to 4
Elementary character bit time
Manchester
Coding Error
detected
sampling points
Preamble subpacket
and Start Frame Delimiter
were successfully
decoded
Entering USART character area
793
SAM4S Series [DATASHEET]
Atmel-11100K-ATARM-SAM4S-Datasheet_09-Jun-15
When the start frame delimiter is a sync pattern (ONEBIT field to 0), both command and data delimiter are
supported. If a valid sync is detected, the received character is written as RXCHR field in the US_RHR and the
RXSYNH is updated. RXCHR is set to 1 when the received character is a command, and it is set to 0 if the
received character is a data. This mechanis m alleviates and simplifies the direct memory access as the character
contains its own sync field in the same register.
As the decoder is setup to be used in Unipolar mode, the first bit of the frame has to be a zero-to-one transition.
36.6.3.5 Radio Interface: Manchester Encoded USART Application
This section describes low data rate RF transmission systems and their integration with a Manchester encoded
USART. These systems are based on transmitter and receiver ICs that support ASK and FSK modulation
schemes.
The goal is to perform full duplex radio transmission of characters using two different frequency carriers. See the
configuration in Figure 36-16.
Figure 36-16. Ma nch ester Encoded Characters RF Transmission
The USART peripheral is configured as a Manchester encoder/decoder. Looking at the downstream
communication channel, Manch ester encoded characters are serially sent to the RF emitter . This may also includ e
a user defined preamble and a start frame delimiter. Mostly, preamble is used in the RF receiver to distinguish
between a valid data from a transmitter and signals due to noise. The Manche ster st ream is then mo dulated . See
Figure 36-17 for an example of ASK modu lation scheme. When a logic one is sent to the ASK modulator, the
power amplifier, referred to as PA, is enabled and transmits an RF signal at downstream frequency. When a logic
zero is transmitted, the RF signal is turned off. If the FSK modulator is activated, two different frequencies are used
to transmit data. When a logic 1 is sent, the modulator outputs an RF signal at frequency F0 and switches to F1 if
the data sent is a 0. See Figure 36-18.
From the receiver side, another carrier frequency is used. The RF receiver performs a bit check operation
examining demodulated data stream. If a valid pattern is detected, the receiver switches to Receiving mode. The
demodulated stream is sent to the Manchester decoder. Because of bit checking inside RF IC, the data tr ansferred
to the microcontroller is reduce d by a user-defined number of bits. The Manchester preamble length is to be
defined in accordance with the RF IC configuration.
LNA
VCO
RF filter
Demod
control bi-dir
line
PA
RF filter
Mod
VCO
control
Manchester
decoder
Manchester
encoder
USART
Receiver
USART
Emitter
ASK/FSK
Upstream Receiver
ASK/FSK
downstream transmitter
Upstream
Emitter
Downstream
Receiver
Serial
Configuration
Interface
Fup frequency Carrier
Fdown frequency Carrier
SAM4S Series [DATASHEET]
Atmel-11100K-ATARM-SAM4S-Datasheet_09-Jun-15
794
Figure 36-17. ASK Modulator Output
Figure 36-18. FSK Modulator Output
36.6.3.6 Synchronous Receiver
In Synchronous mod e (SYNC = 1), the receiver samples the RXD signal on each rising edge of the baud rate
clock. If a low level is detected, it is considered as a start. All data bits, the parity bit and the stop bits are sampled
and the receiver waits for the next start bit. Synchronous mode operations provide a high-speed transfer capability.
Configuration fields and bits are the same as in Asynchronous mode.
Figure 36-19 illus trates a charac ter reception in Synchronous mode.
Figure 36-19. Synchronous Mode Character Reception
36.6.3.7 Receiver Operations
When a character reception is completed, it is transferred to the Rece ive Holding register (US_RHR) and the
RXRDY bit in US_CSR rises. If a character is completed while the RXRDY is set, the OVRE (O verrun Er ror) bit is
set. The last character is transferred into US_RHR and ove rwrites the previous one. T he OVRE bit is cleared by
writing a 1 to the RSTSTA (Reset Status) bit in the US_CR.
Manchester
encoded
data
default polarity
unipolar output Txd
ASK Modulator
Output
Uptstream Frequency F0
NRZ stream 10 0 1
Manchester
encoded
data
default polarity
unipolar output
Txd
FSK Modulator
Output
Uptstream Frequencies
[F0, F0+offset]
NRZ stream 10 0 1
D0 D1 D2 D3 D4 D5 D6 D7
RXD
Start
Sampling
Parity Bit Stop Bit
Example: 8-bit, Parity Enabled 1 Stop
Baud Rate
Clock
795
SAM4S Series [DATASHEET]
Atmel-11100K-ATARM-SAM4S-Datasheet_09-Jun-15
Figure 36-20. Receiver Status
36.6.3.8 Parity
The USART supp orts five Parit y mode s that are se lected by writin g to t he PAR field in the U S_M R. T he PAR field
also enables the Multidrop mode, see Section 36.6.3.9 ”Multidrop Mode”. Even and odd parity bit generation and
error detection are supported.
If even parity is selected, the parity generator of the transmitter drives the parity bit to 0 if a number of 1s in the
character data bit is even, and to 1 if the number of 1s is odd. Accordingly, the receiver parity checker counts the
number of received 1s and reports a pa rity error if the sampled parity bit does not correspo nd. If odd parity is
selected, th e parity gen erator of the transmitt er drives the parity bit to 1 if a number of 1s in the character da ta bit
is even, and to 0 if the nu mber of 1 s is odd. Accordingl y, the r eceiver parity ch ecker counts the n umber of receive d
1s and reports a parity error if the sampled parity bit does not correspond. If the mark parity is used, the parity
generator of the transmitter drives the parity bit to 1 for all characters. The receiver parity checker reports an error
if the parity bit is sampled to 0. If the space parity is used, the parity generator of the transmitter drives the parity bit
to 0 for all characters. The receiver parity checker reports an error if the parity bit is sampled to 1. If parity is
disabled, the transmitter does not generate any parity bit and the receiver does not report any parity error.
Table 36-8 shows an example of the parity bit for the character 0x41 (character ASCII “A”) depending on the
configuration of the USART. Because there are two bits set to 1 in the character value, the parity bit is set to 1
when the parity is odd, or configured to 0 when the parity is even.
When the r eceiver detects a parity erro r, it sets the PA RE (Parity Error ) bit in the US_C SR. The PARE bit ca n be
cleared by writing a 1 to the RSTSTA bit the US_CR. Figu re 36-21 illustrates the parity bit status setting and
clearing.
D0 D1 D2 D3 D4 D5 D6 D7
RXD
Start
Bit Parity
Bit Stop
Bit
Baud Rate
Clock
Write
US_CR
RXRDY
OVRE
D0 D1 D2 D3 D4 D5 D6 D7
Start
Bit Parity
Bit Stop
Bit
RSTSTA = 1
Read
US_RHR
Table 36-8. Parity Bit Examples
Character Hexadecimal Binary Parity Bit Parity Mode
A 0x41 0100 0001 1 Odd
A 0x41 0100 0001 0 Even
A 0x41 0100 0001 1 Mark
A 0x41 0100 0001 0 Space
A 0x41 0100 0001 None None
SAM4S Series [DATASHEET]
Atmel-11100K-ATARM-SAM4S-Datasheet_09-Jun-15
796
Figure 36-21. Parity Error
36.6.3.9 Multidrop Mode
If the value 0x6 or 0x07 is written to the PAR field in the US_MR, the USART runs in Multidrop mode. This mode
differentiates the data characters an d the address characters. Data is transmitted with the parity bit at 0 and
addresses are transmitted with the parity bit at 1.
If the USART is configured in Multid rop m ode, the receiver sets th e PARE parity error bit when the parity bi t is high
and the transmitter is able to send a character with the parity bit hig h when a 1 is written to the SENTA bit in the
US_CR.
To handle parity error, the PARE bit is cleared when a 1 is written to the RSTSTA bit in the US_CR.
The transmitter sends an address byte (parity bit set) when SENDA is written to in the US_CR. In this case, the
next byte written to the US_THR is transmitted as an address. Any character written in the US_THR without having
written the command SENDA is transmitted no rm a lly w ith th e pa rit y at 0.
36.6.3.10 Transmitter Timeguard
The timeguard feature enables the USART interface with slow remote devices.
The timeguard function enables the transmitter to insert an idle state on the TXD line betwee n two characters. This
idle state actually acts as a long stop bit.
The duration of the idle state is programmed in the TG field of the Transmitter Timeg uard register (US_TTGR).
When this field is written to zero no timeguard is generated. Otherwise, the transmitter holds a high level on TXD
after each transmitted byte during the number of bit periods programmed in TG in addition to the number of stop
bits.
As illustrated in Figure 36-22, the behavior of TXRDY and TXEMPTY status bits is modified by the programming of
a timeguard. TXRDY rises only when the start bit of the next character is sent, and th us remains to 0 during the
timeguard transmission if a character has been written in US_THR. TXEMPTY re mains low until the timeguard
transmission is completed as the timeguard is part of the current character being transmitted.
D0 D1 D2 D3 D4 D5 D6 D7
RXD
Start
Bit Bad
Parity
Bit
Stop
Bit
Baud Rate
Clock
Write
US_CR
PARE
RXRDY
RSTSTA = 1
Parity Error
Detect
Time Flags
Report
Time
797
SAM4S Series [DATASHEET]
Atmel-11100K-ATARM-SAM4S-Datasheet_09-Jun-15
Figure 36-22. Timegua rd Operations
Table 36-9 indicates the maximum length of a timeguard period that the transmitter can handle in relation to the
function of the baud rate.
36.6.3.11 Receiver Time-out
The Receiver Time-out provides support in handling variable-length frames. This feature detects an idle condition
on the RXD line. When a time-out is detected, the bit TIMEOUT in the US_CSR rises and can generate an
interrupt, thus indicating to the driver an end of frame.
The time-out delay period (during which the receiver waits for a new character) is programm ed in the TO field of
the Receiver Time-out register (US_RTOR). If the TO field is written to 0, the Receiver Time-out is disabled and no
time-out is detected. The TIMEOUT bit in the US_CSR remains at 0. Otherwise, the receiver loads a 16-bit counter
with the value programmed in TO. This counter is decremented at each bit period and reloaded each time a new
character is received. If the counter reaches 0, the TIMEOUT bit in US_CSR rises. Then, the user can either:
S to p the counter clock until a new character is received. T his is performed by writing a 1 to the STT TO (Start
Time-out) bit in the US_CR. In this case, the idle state on RXD before a new character is received will not
provide a time-out. This prevents having to handle an interrupt before a character is received and allows
waiting for the next idle state on RXD after a frame is received.
Obtain an interrupt while no character is received. This is performed by writing a 1 to the RETTO (Reload
and Start Time-out) bit in the US_CR. If RETTO is performed, the cou nter starts countin g do wn imme diately
from the value T O. This enable s generation of a periodic interrupt so that a user time-out can be h andled, for
example when no key is pressed on a keyboard.
D0 D1 D2 D3 D4 D5 D6 D7
TXD
Start
Bit Parity
Bit Stop
Bit
Baud Rate
Clock
Start
Bit
TG = 4
Write
US_THR
D0 D1 D2 D3 D4 D5 D6 D7 Parity
Bit Stop
Bit
TXRDY
TXEMPTY
TG = 4
Table 36-9. Maximum Timeguard Length Depending on Baud Rate
Baud Rate (bit/s) Bit Time (µs) Timeguard (ms)
1,200 833 212.50
9,600 104 26.56
14,400 69.4 17.71
19,200 52.1 13.28
28,800 34.7 8.85
38,400 26 6.63
56,000 17.9 4.55
57,600 17.4 4.43
115,200 8.7 2.21
SAM4S Series [DATASHEET]
Atmel-11100K-ATARM-SAM4S-Datasheet_09-Jun-15
798
If STTTO is performed, th e counter cloc k is stopped until a first char acter is received. T he idle state on RXD befor e
the start of the frame does not provide a time-out. This pre vents having to obtain a period ic interrupt and ena bles a
wait of the end of frame when the idle state on RXD is detected.
If RETTO is performed, the counter starts counting down immediately from the value TO. This enables generation
of a periodic interrupt so that a user time-out can be handled, for example when no key is pressed on a keyboard.
Figure 36-23 shows the block diagram of the Receiver Time- out feature.
Figure 36-23. Receiver Time-out Block Diagram
Table 36-10 gives the maximum time-out period for some standard baud rates.
36.6.3.12 Framing Error
The receiver is capable of detecting framing errors. A framing e rror happens when the stop bit of a received
character is detected at level 0. This can occur if the receiver and the transmitter are fully desynchronized.
A framing error is reported on the FRAME bit of US_CSR. The FRAME bit is asserted in the middle of the stop bit
as soon as the framing error is detected. It is cleared by writing a 1 to the RSTSTA bit in the US_CR.
Table 36-10. Maximum Time-out Period
Baud Rate (bit/s) Bit Time (µs) Time-out (ms)
600 1,667 109,225
1,200 833 54,613
2,400 417 27,306
4,800 208 13,653
9,600 104 6,827
14,400 69 4,551
19,200 52 3,413
28,800 35 2,276
38,400 26 1,704
56,000 18 1,170
57,600 17 1,138
200,000 5 328
16-bit Time-out
Counter
0
TO
TIMEOUT
Baud Rate
Clock
=
Character
Received
RETTO
Load
Clock
16-bit
Value
STTTO
DQ
1
Clear
799
SAM4S Series [DATASHEET]
Atmel-11100K-ATARM-SAM4S-Datasheet_09-Jun-15
Figure 36-24. Framing Error Statu s
36.6.3.13 Transmit Break
The user can request the transmitter to generate a break condition on the TXD line. A break condition drives the
TXD line low during at least one complete character. It appears the same as a 0x00 character sent with the parity
and the stop bits at 0. However, the transmitter holds the TXD line at least during one character until the user
requests the break condition to be removed.
A break is transmitted by writing a 1 to the STTBRK bit in th e US_CR. This can be perform ed at any time, either
while the transmitter is empty (no character in either the Shift register or in US_THR) or when a character is being
transmitted. If a break is r equested while a character is being sh ifted out, the cha racter is first completed befo re the
TXD line is held low.
Once STTBRK command is requested further STTBRK comm ands are ignored until the end of the break is
completed.
The break condition is remo ved by writing a 1 to the STPBRK bit in the US_CR. If the STPBRK is requested before
the end of the minimum bre ak duration (one character, including start , data, parity and stop bits), the transmitter
ensures that the break condition completes.
The transmitter co nsiders the break as though it is a character, i.e., the STTBRK and STPBRK commands are
processed only if the TXRDY bit in US_CSR is to 1 and the start of the break condition clears the TXRDY and
TXEMPTY bits as if a character is processed.
Writing US_CR with both STTBRK and STPBRK bits to 1 can lead to an unpredictable result. All STPBRK
commands request ed wi thout a pr eviou s STTB RK comman d ar e ignored. A byte written into the Transmit Holding
register while a break is pending, but not started, is ignored.
After the break condition, the transmitter returns the TXD line to 1 for a minimum of 12 bit time s. Thus, the
transmitter ensures that the remote receiver detects correctly the end of break and the start of the next character.
If the timeguard is programmed with a value higher than 12, the TXD line is held high for the timeguard period.
After holding the TXD line for this period, the transmitter resumes normal operations.
Figure 36-25 illustrates the effect of both the Start Break (STTBRK) and Stop Break (STPBRK) commands on the
TXD line.
D0 D1 D2 D3 D4 D5 D6 D7
RXD
Start
Bit Parity
Bit Stop
Bit
Baud Rate
Clock
Write
US_CR
FRAME
RXRDY
RSTSTA = 1
SAM4S Series [DATASHEET]
Atmel-11100K-ATARM-SAM4S-Datasheet_09-Jun-15
800
Figure 36-25. Break Transmission
36.6.3.14 Receive Break
The receiv er dete cts a brea k con ditio n whe n all d ata, par ity a nd s top bi ts are lo w. Th is corresponds to detecting a
framing error with data to 0x00, but FRAME remains low.
When the low stop bit is detected, the receiver asserts the RXBRK bit in US_CSR. This bit may be cleared by
writing a 1 to the RSTSTA bit in the US_CR.
An end of receive b reak is detected by a high level for at least 2 /16 of a bit peri od in Asynchronous op erating mode
or one sample at high level in Synchronous operating mode. The end of break detection also asserts the RXBRK
bit.
36.6.3.15 Hardware Handshaking
The USART features a hardware handshaking out-of-band flow control. The RTS and CTS pins are used to
connect with the remote device, as shown in Figure 36-26.
Figure 36-26. Connection with a Remote Device for Hardware Handshaking
Setting the USART to operate with hardware handshaking is performed by writing the USART_MODE field in
US_MR to the value 0x2.
The USART behavior when hardware handshaking is enabled is the same as the behavior in standard
Synchronous or Asynchronous mode, except that the receiver drives the RTS pin as described below and the level
on the CTS pin modifies the behavior of the transmitter as described below. Using this mode requires using the
PDC channel for reception. The transmitter can handle hardware handshaking in any case.
Figure 36-27 shows how the receiver operates if hardware handshaking is enabled. The RTS pin is driven high if
the receiver is disabled or if the status RXBUFF (Receive Buffer Full) coming from the PDC channel is high.
Normally, the remote device does not start transmitting while its CTS pin (driven by RTS) is high. As soon as the
receiver is enabled, the RTS falls, indicating to the remote device that it can start transmitting. Defining a new
buffer in the PDC clears the status bit RXBUFF and, as a result, asserts the pin RTS low.
D0 D1 D2 D3 D4 D5 D6 D7
TXD
Start
Bit Parity
Bit Stop
Bit
Baud Rate
Clock
Write
US_CR
TXRDY
TXEMPTY
STPBRK = 1
STTBRK = 1
Break Transmission End of Break
USART
TXD
CTS
Remote
Device
RXD
TXDRXD
RTS
RTS
CTS
801
SAM4S Series [DATASHEET]
Atmel-11100K-ATARM-SAM4S-Datasheet_09-Jun-15
Figure 36-27. Receiver Behavior when Operating with Hardware Handshaking
Figure 36-28 shows how the transmitter operates if hardware handshaking is enabled. The CTS pin disables the
transmitter. If a character is being processed, the transmitter is disabled only after the completion of the current
character and transmission of the next character happens as soon as the pin CTS falls.
Figure 36-28. Transmitter Behavior when Operating with Har dware Handshaking
36.6.4 ISO7816 Mode
The USART features an ISO7816-compat ib le operat ing mode. This mo de permits inte rfacing with smart cards and
Security Access Modules (SAM) communicating through an ISO7816 link. Both T = 0 and T = 1 protocols defined
by the ISO7816 specification are supported.
Setting the USART in ISO7816 mode is performed by writing the USART_MODE field in US_MR to the value 0x4
for protocol T = 0 and to the value 0x5 for protocol T = 1.
36.6.4.1 ISO7816 Mode Overview
The ISO7816 is a half duplex commu nication on only one bidirectional line. The baud rate is determ ined by a
division of the clock provided to the remote device (see Section 36-2 ”Baud Rate Generator”).
The USART connects to a smart card a s shown in Figure 36-29. The TXD line becomes bidirection al and the baud
rate generator feeds the ISO7816 clock on the SCK pin. As the TXD pin becomes bidirectional, its output remains
driven by the output of the transmitter but only when the transmitter is active while its input is directed to the input
of the receiver. The USART is considered as the master of the communication as it generates the clock.
Figure 36-29. Connection of a Smart Card to the USART
When operatin g in ISO7816, either in T = 0 o r T = 1 modes, the charact er format is fixed. Th e configuration is 8
data bits, even parity and 1 or 2 stop bits, regardless of the values programmed in the CHRL, MODE9, PAR and
CHMODE fields. MSBF can be used to transmit LSB or MSB first. Parity Bit (PAR) can be used to transmit in
normal or inverse mode. Refer to Section 36.7.3 ”USART Mode Register” and “PAR: Parity Type” .
RTS
RXBUFF
Write
US_CR
RXEN = 1
RXD RXDIS = 1
CTS
TXD
Smart
Card
SCK CLK
TXD I/O
USART
SAM4S Series [DATASHEET]
Atmel-11100K-ATARM-SAM4S-Datasheet_09-Jun-15
802
The USART cannot operate concurrently in both Receiver and Transmitter modes as the communication is
unidirectional at a time. It has to be configured according to the required mode by enabling or disabling either the
receiver or the transmitter as desired. Enabling both the receiver and the transmitter at the same time in ISO7816
mode may lead to unpredictable results.
The ISO7816 specification defines an inverse transmission format. Data bits of the character must be transmitted
on the I/O line at their negative value.
36.6.4.2 Protocol T = 0
In T = 0 protocol, a character is made up of one start bit, eight data bits, one parity bit and one guard time, which
lasts two bit times. The transmitter shifts out the bits and does not drive the I/O line during the guard time.
If no parity error is detected, the I/O line re mains at 1 during the guard time and the transmitter can continue with
the transmission of the next character, as shown in Figure 36-30 .
If a parity error is detected by the receiver, it drives the I/O line to 0 during the guard time, as shown in Figure 36-
31. This error bit is also named NA CK, for Non Acknowledge. In this case, the character lasts 1 bit time more, as
the guard time length is the same and is added to the error bit time which lasts 1 bit time.
When the USART is the receiver and it detects an error, it does not load the erron eous character in the Receive
Holding register (US_RHR). It appropriately sets the PARE bit in the Status register (US_SR) so that the software
can handle the error.
Figure 36-30. T = 0 Protocol without Parity Error
Figure 36-31. T = 0 Protocol with Parity Error
Receive Error Counter
The USART receiver also records the total number of errors. This can be read in the Number of Error (US_NER)
register. The NB_ERRORS field can record up to 255 errors. Reading US_NER automatically clears the
NB_ERRORS field.
Receive NACK Inhibit
The USART can also be configured to inhibit an error. This can be achieved by setting the INACK bit in US_MR. If
INACK is to 1, no error signal is driven on the I/O line even if a parity bit is detected.
Moreover, if INACK is set, the erroneous received char acter is stored in the Receive Holding register, as if no er ror
occurred and the RXRDY bit does rise.
D0 D1 D2 D3 D4 D5 D6 D7
RXD
Parity
Bit
Baud Rate
Clock
Start
Bit Guard
Time 1 Next
Start
Bit
Guard
Time 2
D0 D1 D2 D3 D4 D5 D6 D7
I/O
Parity
Bit
Baud Rate
Clock
Start
Bit Guard
Time 1 Start
Bit
Guard
Time 2 D0 D1
Error
Repetition
803
SAM4S Series [DATASHEET]
Atmel-11100K-ATARM-SAM4S-Datasheet_09-Jun-15
Transmit Character Repetition
When the USART is transmitting a character and gets a NACK, it can automatically repeat the character before
moving on to the next one. Repetition is enabled by writing the MAX_ITERATION field in the US_MR at a value
higher than 0. Each character can be transmitted up to eight times; the first transmission plus seven repetitions.
If MAX_ITERATION does not equal zero, the USART repeats the character as many times as the value loaded in
MAX_ITERATION.
When the USART repetition number reaches MAX_ITERATION and the last repeated character is not
acknowledged, the ITER bit is set in US_CSR. If the repetition of the character is acknowledged by the receive r,
the repetitions are stopped and the iteration counter is cleared.
The ITER bit in US_CSR can be cleared by writing a 1 to the RSTIT bit in the US_CR.
Disable Successive Receive NACK
The receiver can limit the number of successive NACKs sent back to the remote transmitter. This is programmed
by setting the bit DSNACK in the US_MR. The maximu m number of NACKs transmitted is programmed in the
MAX_ITERATION field. As soon as MAX_ITERATION is reached, no error signal is driven on the I/O line and the
ITER bit in the US_CSR is set.
36.6.4.3 Protocol T = 1
When operating in ISO7816 protocol T = 1, the transmission is similar to an asynchronous format with only one
stop bit. The parity is generated when transmitting and checked when receiving. Parity error detection sets the
PARE bit in the US_CSR.
36.6.5 IrDA Mode
The USART features an IrDA mode supplying half-duplex point-to-point wireless communication. It embeds the
modulator and demodulator which allows a glueless connection to the infrared transceivers, as shown in Figure
36-32. The modulator and demodulator are compliant with the IrDA specification version 1.1 and support data
transfer speeds ranging from 2.4 kbit/s to 115.2 kbit/s.
The IrDA mode is enabled by setting the USART_MODE field in US_MR to the value 0x8. Th e IrDA Filt er regis ter
(US_IF) is used to configure the demodulator filter. The USART transmitter and receiver operate in a normal
Asynchronous mode and all parameters are accessible. Note that the modulator and the demodulator are
activated.
Figure 36-32. Connection to IrDA Transceivers
The receiver and the transmitter must be enabled or disabled depending on the direction of the transmission to be
managed.
To receive IrDA signals, the following needs to be done:
Disable TX and Enable RX
Configure th e TXD pin as PIO and set it as an output to 0 (to avoid LED emission). Disable the internal pull-
up (better for power consumption).
IrDA
Transceivers
RXD RX
TXD
TX
USART
Demodulator
Modulator
Receiver
Transmitter
SAM4S Series [DATASHEET]
Atmel-11100K-ATARM-SAM4S-Datasheet_09-Jun-15
804
Receive data
36.6.5.1 IrDA Modulation
For baud rates up to and including 115.2 kbit/s, the RZ I modulation scheme is used. “0” is represented by a light
pulse of 3/16th of a bit time. Some examples of signal pulse duration ar e shown in Table 36-11.
Figure 36-33 shows an example of character transmission.
Figure 36-33. IrDA Modulation
36.6.5.2 IrDA Baud Rate
Table 36-12 gives some examples of CD values, baud rate error and pulse duration. Note that the requirement on
the maximum acceptable error of ±1.87% must be met.
Table 36-11. IrDA Pulse Duratio n
Baud Rate Pulse Duration (3/16)
2.4 kbit/s 78.13 µs
9.6 kbit/s 19.53 µs
19.2 kbit/s 9.77 µs
38.4 kbit/s 4.88 µs
57.6 kbit/s 3.26 µs
115.2 kbit/s 1.63 µs
Bit Period 3/16 Bit Period
Start
Bit Data Bits Stop
Bit
00
000
111 1
1
Transmitter
Output
TXD
Table 36-12. IrDA Baud Rate Error
Peripheral Clock Baud Rate (bit/s) CD Baud Rate Error Pulse Time (µs)
3,686,400 115,200 2 0.00% 1.63
20,000,000 115,200 11 1.38% 1.63
32,768,000 115,200 18 1.25% 1.63
40,000,000 115,200 22 1.38% 1.63
3,686,400 57,600 4 0.00% 3.26
20,000,000 57,600 22 1.38% 3.26
32,768,000 57,600 36 1.25% 3.26
40,000,000 57,600 43 0.93% 3.26
3,686,400 38,400 6 0.00% 4.88
20,000,000 38,400 33 1.38% 4.88
32,768,000 38,400 53 0.63% 4.88
40,000,000 38,400 65 0.16% 4.88
805
SAM4S Series [DATASHEET]
Atmel-11100K-ATARM-SAM4S-Datasheet_09-Jun-15
36.6.5.3 IrDA Demodulator
The demodulator is based on the IrDA Receive filter comprised of an 8-bit down counter which is loaded with the
value programmed in US_IF. When a falling edge is detected on the RXD pin, the Filter Counter starts counting
down at the peripheral clock speed. If a rising ed ge is detected on the RXD pin, the counter stops and is reloaded
with US_IF. If no rising edge is detected when the counter reaches 0, the input of the receiver is driven low during
one bit time.
Figure 36-34 illus trates the operations of the IrDA demodulator.
Figure 36-34. IrDA Demodulator Operations
The program m ed valu e in the U S_I F re gister must always mee t th e follo wing crite ria :
tperipheral clock × (IRDA_FILTER + 3) < 1.41 µs
As the IrDA mode u ses the same lo gic as the ISO7 816 , no te that the FI_DI_RATIO field in US_FIDI must be set to
a value higher than 0 in order to make sure IrDA communications operate correctly.
36.6.6 RS485 Mode
The USART features the RS485 mode to enable line driver control. While operating in RS485 mode, the USART
behaves as though in Async hronous or Synchronous mode and configur ation of all the parameters is possible.
The differ ence is that the RTS pin is driven high w hen the transm itter is o perating . The behavior of the RTS pin is
controlled by the TXEMPTY bit. A typical connection of the USART to an RS485 bus is shown in Figure 36-35.
3,686,400 19,200 12 0.00% 9.77
20,000,000 19,200 65 0.16% 9.77
32,768,000 19,200 107 0.31% 9.77
40,000,000 19,200 130 0.16% 9.77
3,686,400 9,600 24 0.00% 19.53
20,000,000 9,600 130 0.16% 19.53
32,768,000 9,600 213 0.16% 19.53
40,000,000 9,600 260 0.16% 19.53
3,686,400 2,400 96 0.00% 78.13
20,000,000 2,400 521 0.03% 78.13
32,768,000 2,400 853 0.04% 78.13
Table 36-12. IrDA Baud Rate Error (Continued)
Peripheral Clock Baud Rate (bit/s) CD Baud Rate Error Pulse Time (µs)
MCK
RXD
Receiver
Input
Pulse
Rejected
65432 61
65432 0
Pulse
Accepted
Counter
Value
SAM4S Series [DATASHEET]
Atmel-11100K-ATARM-SAM4S-Datasheet_09-Jun-15
806
Figure 36-35. Typical Connection to a RS485 Bus
The USART is set in RS485 mode by writing the value 0x1 to the USART_MODE field in US_MR.
The RTS pin is at a level inverse to the TXEMPTY bit. Significantly, the RT S pin rem ains hi gh wh en a timeg uar d is
programmed so that the line can remain driven after the last character completion. Figure 36-36 gives an example
of the RTS waveform during a character transmission when the timeguard is enabled.
Figure 36-36. Example of RTS Drive with Timeguard
USART
RTS
TXD
RXD
Differential
Bus
D0 D1 D2 D3 D4 D5 D6 D7
TXD
Start
Bit Parity
Bit Stop
Bit
Baud Rate
Clock
TG = 4
Write
US_THR
TXRDY
TXEMPTY
RTS
1
807
SAM4S Series [DATASHEET]
Atmel-11100K-ATARM-SAM4S-Datasheet_09-Jun-15
36.6.7 Modem Mode
The USART features Modem mode, which enables control of the signals: DTR (Data Terminal Ready), DSR (Data
Set Ready), RTS (Request to Send), CTS (Clear to Send), DCD (Data Carrier Detect) and RI (Ring Indicator).
While operating in Mod em mo de, th e USART beha ves a s a DTE (Data Terminal Equipment) as it drives DTR and
RTS and can detect level change on DSR, DCD, CTS and RI.
Setting the USART in Modem mode is performed by writing the USART_MODE field in US_MR to the value 0x3.
While operating in Modem mode, the USART behaves as though in Asynchronous mode and all the parameter
configurat ion s ar e ava ila ble .
Table 36-13 gives the correspondence of the USART signals with modem connection standards.
The control of the DTR output pin is performed by writing a 1 to the DTRDIS and DTREN bits respectively in
US_CR. The disable command forces the corresponding pin to its inactive level, i.e., high. The enable command
forces the corresponding pin to its active level, i.e., low. The RTS output pin is automatically controlled in this
mode.
The level changes are detected on the RI, DSR, DCD and CTS pins. If an input change is detected, the RIIC,
DSRIC, DCDIC and CTSIC bits in US_CSR are set respectively and can trigger an interrupt. The status is
automatically cleared when US_CSR is read. Furthermore, the CTS automatically disables the transmitter when it
is detected at its in active st ate. If a char acter is being transm itted wh en the CT S rises, the cha racter tr ansmiss ion
is completed before the transmitter is actually disabled.
Table 36-13. Circuit References
USART Pin V24 CCITT Direction
TXD 2 103 From terminal to modem
RTS 4 105 From terminal to modem
DTR 20 108.2 From terminal to modem
RXD 3 104 Fro m mode m to terminal
CTS 5 106 From terminal to modem
DSR 6 107 From terminal to modem
DCD 8 109 From terminal to modem
RI 22 125 From terminal to modem
SAM4S Series [DATASHEET]
Atmel-11100K-ATARM-SAM4S-Datasheet_09-Jun-15
808
36.6.8 SPI Mode
The Serial Peripheral Interface (SPI) mode is a synchronous serial data link that provides communication with
external devices in Master or Slave mode. It also enables communication between processors if an external
processor is connected to the system.
The Serial Peripheral Interface is essentially a shift register that serially transmits data bits to other SPIs. During a
data transfer, one SPI system acts as the “master” which controls the data flow, while the other devices act as
“slaves'' which have data shifted into and out by the master. Different CPUs can take turns being masters and one
master may simultaneously shif t data into multiple slaves. (Multiple master protocol is the opposite of single
master protocol, where one CPU is always the master while all of the others are always slaves.) However, only
one slave may drive its output to write data back to the master at any given time.
A slave device is selected when its NSS signal is asserted by the master. The USART in SPI Master mode can
address only one SPI slave because it can generate only one NSS signal.
The SPI system consists of two data lines and two control lines:
Master Out Slave In (MOSI): This data line supplies the ou tput data from the ma ster shifted into the input of
the slave.
Master In Slave Out (MISO): This data line supplies the output data from a slave to the input of the master.
Serial Clock (SCK): This control line is driven by the master and regulates the flow of the da ta bits. The
master may transmit data at a variety of baud rates. The SCK line cycles once for each bit that is
transmitted.
Slave Select (NSS): This control line allows the master to select or deselect the slave.
36.6.8.1 Modes of Operation
The USART can operate in SPI Master mode or in SPI Slave mode.
Operation in SPI Master m ode is programmed by writing 0xE to the USART_MODE field in US_MR. In this case
the SPI lines must be connected as described below:
The MOSI line is driven by the output pin TX D
The MISO line drives the input pin RXD
The SCK line is driven by the output pin SCK
The NSS line is driven by the output pin RTS
Operation in SPI Slave mode is prog rammed by writing to 0xF the USART_ MODE field in US_MR. In this case the
SPI lines must be connected as described below:
The MOSI line drives the input pin RXD
The MISO line is driven by the output pin TX D
The SCK line drives the input pin SCK
The NSS line drives the input pin CTS
In order to avoid unpredictable behavior, any change of the SPI mode must be followed by a software reset of the
transmitter and of the receiver (except the initial configuration after a hardware reset). (See Section 36.6.8.4).
36.6.8.2 Baud Rate
In SPI mode, the baud rate generator operates in the same way as in USART Synchronous mode. See Section
36.6.1.3 ”Baud Rate in Synchronous Mode or SPI Mode”. However, there are some restrictions:
In SPI Master mode:
The external clock SCK must not be selected (USCLKS ≠ 0x3), and the bit CLKO must be set to 1 in the
US_MR, in order to generate correctly the serial clock on the SCK pin.
To obtain correct behavior of the rece iver and the tran smitter, the value programmed in CD must be superior
or equal to 6.
809
SAM4S Series [DATASHEET]
Atmel-11100K-ATARM-SAM4S-Datasheet_09-Jun-15
If the divided peripheral clock is selected, the value pro grammed in CD must be even to ensure a 50:50
mark/space ratio on the SCK pin, this value can be odd if the peripheral clock is selected.
In SPI Slave mode:
The external clock (SCK) selection is forced regardless of the value of the USCLKS field in the US_MR.
Likewise, the value written in US_BRGR has no effect, because the clock is provided directly by the signal
on the USART SCK pin.
To obtain correct beha vior of th e receiver and the transmitter, the external clock (SCK) frequ ency must be at
least 6 times lower than the system clock.
36.6.8.3 Data Transfer
Up to nine data bits are successively shifted out on the TXD pin at each rising or falling edge (depending of CPOL
and CPHA) of the programmed serial clock. There is no Start bit, no Parity bit and no Stop bit.
The number of data bits is selected by the CHRL field and the MODE 9 bit in the US_MR. The nine bits are
selected by setting the MODE 9 bit regard less of the CHRL fi eld. The MSB data bit is always sent first in SPI mode
(Master or Slave).
Four combinations of polarity and phase are availab le for data transfers. The clock po larity is prog rammed with the
CPOL bit in the US_MR. The clock phase is programmed with the CPHA bit. These two parameters determine the
edges of the clock signal upon which data is driven and sampled. Each of the two parameters has two possible
states, resulting in four possible combinations that are incompatible with one another. Thus, a master/slave pair
must use the same parameter pair values to communicate. If multiple slaves are used and fixed in different
configurations, the master must reconfigure itself each time it needs to communicate with a different slave.
Table 36-14. SPI Bus Protocol Mode
SPI Bus Protocol Mode CPOL CPHA
001
100
211
310
SAM4S Series [DATASHEET]
Atmel-11100K-ATARM-SAM4S-Datasheet_09-Jun-15
810
Figure 36-37. SPI Transfer Format (CPHA = 1, 8 bits per transfer)
Figure 36-38. SPI Transfer Format (CPHA = 0, 8 bits per transfer)
36.6.8.4 Receiver and Transmitter Control
See Section 36.6.2 ”Receiver and Transmitter Control”
36.6.8.5 Character Transmission
The characters are sent by writing in the Transmit Holding register (US_THR). An additional condition for
transmitting a character can be added when the USART is configured in SPI M aster mode. In the USART Mode
Register (SPI_MODE) (USART_MR), the value configured on the bit WRDBT can prevent any character
6
SCK
(CPOL = 0)
SCK
(CPOL = 1)
MOSI
SPI Master ->TXD
SPI Slave -> RXD
NSS
SPI Master -> RTS
SPI Slave -> CTS
SCK cycle (for reference)
MSB
MSB
LSB
LSB
6
6
5
5
4
4
3
3
2
2
1
1
1 2345 786
MISO
SPI Master -> RXD
SPI Slave -> TXD
SCK
(CPOL = 0)
SCK
(CPOL = 1)
1 2345 7
MOSI
SPI Master -> TXD
SPI Slave -> RXD
MISO
SPI Master -> RXD
SPI Slave -> TXD
NSS
SPI Master -> RTS
SPI Slave -> CTS
SCK cycle (for reference) 8
MSB
MSB
LSB
LSB
6
6
5
5
4
4
3
3
1
1
2
2
6
811
SAM4S Series [DATASHEET]
Atmel-11100K-ATARM-SAM4S-Datasheet_09-Jun-15
transmission (even if US_THR has been writte n) while the receiver side is not read y (character not read). Wh en
WRDBT equals 0, the character is transmitted whatever the receiver status. If WRDBT is set to 1, the transmitter
waits for the Receive Holding register (US_RHR) to be read before transmitting the character (RXRDY flag
cleared), thu s pr eventing any ov er flo w (cha r act er loss) on the re ce iver si de .
The transmitter reports two status bits in US_CSR: TXRDY (Transmitter Ready), which indicates that US_THR is
empty and TX EMPTY, which indicate s that all the char acters wr itten in US_THR h ave been pr ocessed . When the
current character processing is completed, the last character written in US_THR is transferred into the Shift
register of the transmitter and US_THR becomes empty, thus TXRDY rises.
Both TXRDY and TXEMPTY bits are low when the transmitter is disabled. Writing a character in US_THR while
TXRDY is low has no effect and the written character is lost.
If the USART is in SPI Slave mode and if a character must be sent while the US_THR is empty, the UNRE
(Underrun Error) bit is set. The TXD transmission line stays at high level during all this time. The UNRE bit is
cleared by writing a 1 to the RSTSTA (Reset Status) bit in US_CR.
In SPI Master mode, the slave select line (NSS) is asserted at low level one tbit (tbit being the nominal time required
to transmit a bit) before the transmission of the MSB bit and released at high level one tbit after the transmission of
the LSB bit. So, the slave select line (NSS) is always released between each character transmission and a
minimum delay of three tbit always inserted. Howe ver, in order to addre ss slave devices supportin g the CSAAT
mode (Chip Select Active After Transfer), the slave select line (NSS) can be forced at low level by writing a 1 to the
RTSEN bit in the US_CR. The slave select line (NSS) can be released at high level only by writing a 1 to the
RTSDIS bit in the US_CR (for example, when all data have been transferred to the slave device).
In SPI Slave mode, the transmitter does not require a falling edge of the slave select line (NSS) to initiate a
character transmission but only a low level. However, this low level must be present on the slave select line (NSS)
at least one tbit before the first serial clock cycle corresponding to the MSB bit.
36.6.8.6 Character Reception
When a character reception is completed, it is transferred to the Rece ive Holding register (US_RHR) and the
RXRDY bit in the Status register (US_CSR) rises. If a ch aracter is completed while RXRDY is set, the OVRE
(Overrun Error) bit is set. The last character is tran sferred into US_RHR and overwrites the previous one. The
OVRE bit is cleared by writing a 1 to the RSTSTA (Reset Status) bit in the US_CR.
To ensure correct behavior of the receiver in SPI Slave mode, the master device sending the frame must ensure a
minimum delay of one tbit between each character transmission. The receiver does not require a falling edge of the
slave select line (NSS) to initiate a character reception but only a low level. However, this low level must be
present on the slave select line (NSS) at least one tbit before the first serial cloc k cycle correspo nding to the MS B
bit.
36.6.8.7 Receiver Timeout
Because the receiver baud rate clock is active only during data transfers in SPI mode, a receiver timeout is
impossible in this mode, whatever the time-out value is (field TO) in the US_RTOR.
36.6.9 Test Modes
The USART can be programmed to operate in three different test modes. The internal loopback capability allows
on-board diagnostics. In Loopback mode, the USART interface pins are disconnected or not and reconfigured for
loopback internally or externally.
36.6.9.1 Normal Mode
Normal mode connects the RXD pin on the receiver input and the transmitter output on the TXD pin.
SAM4S Series [DATASHEET]
Atmel-11100K-ATARM-SAM4S-Datasheet_09-Jun-15
812
Figure 36-39. Normal Mode Configuration
36.6.9.2 Automatic Echo Mode
Automatic echo mode allows bit-by-bit retransmission. When a bit is received on the RXD pin, it is sent to the TXD
pin, as shown in Figure 36-40. Programming the transmitter has no effect on the TXD pin. The RXD pin is still
connected to the receiver input, thus the receiver remains active.
Figure 36-40. Automatic Echo Mode Configuration
36.6.9.3 Local Loopback Mode
Local loopback mode con nects the outpu t of the tra nsmitte r d ire ctly to the in put o f the rece ive r, as shown in Figure
36-41. The TXD and RXD pins are not used. The RXD pin has no effect on the receiver and the TXD pin is
continuously driven high, as in idle state.
Figure 36-41. Local Loopback Mode Configuration
36.6.9.4 Remote Loopback Mode
Remote loopback mode di rectly connects the RXD pin to the TXD pin, as shown in Figure 36-42 . The transmitter
and the receiver are disabled and have no effect. This mode allows bit-by-bit r etransmission.
Figure 36-42. Remote Loopback Mode Config uration
Receiver
Transmitter
RXD
TXD
Receiver
Transmitter
RXD
TXD
Receiver
Transmitter
RXD
TXD
1
Receiver
Transmitter
RXD
TXD
1
813
SAM4S Series [DATASHEET]
Atmel-11100K-ATARM-SAM4S-Datasheet_09-Jun-15
36.6.10 Register Write Protection
To prevent any single software error from corrupting USART behavior, certain registers in the address space can
be write-protected by setting the WPEN bit in the USART Write Protection Mode Register (US_WPMR).
If a write access to a write-protected register is dete cted, the WPVS flag in the USART Write Protection Status
Register (US_WPSR) is set and the field WPVSRC indicates the register in which the write access has been
attempted.
The WPVS bit is automatically cleared after reading the US_WPSR.
The following registers can be write-protected:
USART Mode Register
USART Baud Rate Generator Register
USART Receiver Time-out Register
USART Transmitter Timeguard Register
USART FI DI RATIO Register
USART IrDA Filter Register
USART Manchester Configuration Register
SAM4S Series [DATASHEET]
Atmel-11100K-ATARM-SAM4S-Datasheet_09-Jun-15
814
36.7 Universal Synchronous Asynchronous Receiver Transmitter (USART) User Interface
Table 36-1 5. Register Mapping
Offset Register Name Access Reset
0x0000 Control Register US_CR Write-only –
0x0004 Mode Register US_MR Rea d/Write 0x0
0x0008 Interrupt Enable Register US_IER Write-on ly –
0x000C Interrupt Disable Register US_IDR Write-only –
0x0010 Interrupt Mask Register US_IMR Read-only 0x0
0x0014 Channel Status Register US_CSR Read -only 0x0
0x0018 Receive Holding Register US_RHR Read-only 0x0
0x001C Transmit Holding Register US_THR Write-only –
0x0020 Baud Rate Generator Register US_BRGR Read/Write 0x0
0x0024 Receiver Time-out Register US_RTOR Read/Write 0x0
0x0028 Transmitter Timeguard Register US_TTGR Read/Write 0x0
0x002C–0x003C Reserved – – –
0x0040 FI DI Ratio Register US_FIDI Read/Write 0x174
0x0044 Number of Errors Register US_NER Read-only 0x0
0x0048 Reserved – – –
0x004C IrDA Filter Register US_IF Read/Write 0x0
0x0050 Manchester Configuration Register US_MAN Read/Write 0x30011004
0x0054–0x005C Reserved – – –
0x0060–0x00E0 Reserved – – –
0x00E4 Write Protection Mode Register US_WPMR Read/Write 0x0
0x00E8 Write Protection Status Register US_WPSR Read-only 0x0
0x00EC–0x00FC Reserved – – –
0x0100–0x0128 Reserved for PDC Registers – – –
815
SAM4S Series [DATASHEET]
Atmel-11100K-ATARM-SAM4S-Datasheet_09-Jun-15
36.7.1 USART Control Register
Name: US_CR
Address: 0x40024000 (0), 0x40028000 (1)
Access: Write-only
For SPI control, see Section 36.7.2 ”USART Control Register (SPI_MODE)”.
• RSTRX: Reset Receiver
0: No effect.
1: Resets the receiver.
• RSTTX: Reset Transmitter
0: No effect.
1: Resets the transmitter.
• RXEN: Receiver Enable
0: No effect.
1: Enables the receiver, if RXDIS is 0.
• RXDIS: Receiver Disable
0: No effect.
1: Disables the receiver.
• TXEN: Transmitter Enable
0: No effect.
1: Enables the transmitter if TXDIS is 0.
• TXDIS: Transmitter Disable
0: No effect.
1: Disables the transmitter.
• RSTSTA: Reset Status Bits
0: No effect.
1: Resets the status bits PARE, FRAME, OVRE, MANERR and RXBRK in US_CSR.
31 30 29 28 27 26 25 24
––––––––
23 22 21 20 19 18 17 16
––––RTSDISRTSENDTRDISDTREN
15 14 13 12 11 10 9 8
RETTO RSTNACK RSTIT SENDA STTTO STPBRK STTBRK RSTSTA
76543210
TXDIS TXEN RXDIS RXEN RSTTX RSTRX – –
SAM4S Series [DATASHEET]
Atmel-11100K-ATARM-SAM4S-Datasheet_09-Jun-15
816
• STTBRK: Start Break
0: No effect.
1: Starts transmission of a break after the characters present in US_THR and the Transmit Shift Register have been trans-
mitted. No effect if a break is already being transmitted.
• STPBRK: Stop Break
0: No effect.
1: Stops transmission of the break after a min imum of one character length and transmits a high level d uring 12-bit pe riods.
No effect if no break is being transmitted.
• STTTO: Clear TIMEOUT Flag and Start Time-out After Next Character Received
0: No effect.
1: Starts waiting for a character before enabling the time-out counter. Immediately disables a time-out period in progress.
Resets the status bit TIMEOUT in US_CSR.
• SENDA: Send Address
0: No effect.
1: In Multidrop mode only, the next character written to the US_THR is sent with the address bit set.
• RSTIT: Rese t Ite rat io n s
0: No effect.
1: Resets ITER in US_CSR. No effect if the ISO7816 is not enabled.
• RSTNACK: Reset Non Acknowledge
0: No effect
1: Resets NACK in US_CSR.
• RETTO: Start Time-out Immediately
0: No effect
1: Immediately restarts time-out period.
• DTREN: Data Terminal Ready Enable
0: No effect.
1: Drives the pin DTR to 0.
• DTRDIS: Data Terminal Ready Disable
0: No effect.
1: Drives the pin DTR to 1.
• RTSEN: Request to Send Pin Control
0: No effect.
1: Drives RTS pin to 0 if US_MR.USART_MODE field = 0.
• RTSDIS: Request to Send Pin Control
0: No effect.
1: Drives RTS pin to 1 if US_MR.USART_MODE field = 0.
817
SAM4S Series [DATASHEET]
Atmel-11100K-ATARM-SAM4S-Datasheet_09-Jun-15
36.7.2 USART Control Register (SPI_MODE)
Name: US_CR (SPI_MODE)
Address: 0x40024000 (0), 0x40028000 (1)
Access: Write-only
This configuration is relevant only if USART_MODE = 0xE or 0xF in the USART Mode Register.
• RSTRX: Reset Receiver
0: No effect.
1: Resets the receiver.
• RSTTX: Reset Transmitter
0: No effect.
1: Resets the transmitter.
• RXEN: Receiver Enable
0: No effect.
1: Enables the receiver, if RXDIS is 0.
• RXDIS: Receiver Disable
0: No effect.
1: Disables the receiver.
• TXEN: Transmitter Enable
0: No effect.
1: Enables the transmitter if TXDIS is 0.
• TXDIS: Transmitter Disable
0: No effect.
1: Disables the transmitter.
• RSTSTA: Reset Status Bits
0: No effect.
1: Resets the status bits OVRE, UNRE in US_CSR.
31 30 29 28 27 26 25 24
––––––––
23 22 21 20 19 18 17 16
––––RCSFCS––
15 14 13 12 11 10 9 8
–––––––RSTSTA
76543210
TXDIS TXEN RXDIS RXEN RSTTX RSTRX – –
SAM4S Series [DATASHEET]
Atmel-11100K-ATARM-SAM4S-Datasheet_09-Jun-15
818
• FCS: Force SPI Chip Select
Applicable if USART operates in SPI master mode (USART_MODE = 0xE):
0: No effect.
1: Forces the Slave Select Line NSS (RTS pin) to 0, even if USART is not transmitting, in order to address SPI slave
devices supporting the CSAAT mode (Chip Select Active After Transfer).
• RCS: Release SPI Chip Select
Applicable if USART operates in SPI master mode (USART_MODE = 0xE):
0: No effect.
1: Releases the Slave Select Line NSS (RTS pin).
819
SAM4S Series [DATASHEET]
Atmel-11100K-ATARM-SAM4S-Datasheet_09-Jun-15
36.7.3 USART Mode Register
Name: US_MR
Address: 0x40024004 (0), 0x40028004 (1)
Access: Read/Write
This register can only be written if the WPEN bit is cleared in the USART Write Protection Mode Register.
For SPI configuration, see Section 36.7.4 ”USART Mode Register (SPI_MODE)”.
• USART_MODE: USART Mode of Operation
The PDC transfers are supported in all USART modes of operation.
• USCLKS: Clock Selection
31 30 29 28 27 26 25 24
ONEBIT MODSYNC MAN FILTER – MAX_ITERATION
23 22 21 20 19 18 17 16
INVDATA VAR_SYNC DSNACK INACK OVER CLKO MODE9 MSBF
15 14 13 12 11 10 9 8
CHMODE NBSTOP PAR SYNC
76543210
CHRL USCLKS USART_MODE
Value Name Description
0x0 NORMAL Normal mode
0x1 RS485 RS485
0x2 HW_HANDSHAKING Hardware Handshaking
0x3 MODEM Modem
0x4 I S07816_T_0 IS078 16 Protocol: T = 0
0x6 I S07816_T_1 IS078 16 Protocol: T = 1
0x8 IRDA IrDA
0xE SPI_MASTER SPI master
0xF SPI_SLAVE SPI Slave
Value Name Description
0 MCK Peripheral clock is selected
1 DIV Peripheral clock divided (DIV=8) is selected
2—Reserved
3 SCK Serial clock (SCK) is selected
SAM4S Series [DATASHEET]
Atmel-11100K-ATARM-SAM4S-Datasheet_09-Jun-15
820
• CHRL: Character Length
• SYNC: Synchronous Mode Select
0: USART operates in Asynchronous mode.
1: USART operates in Synchronous mode.
•PAR: Parity Type
• NBSTOP: Number of Stop Bits
• CHMODE: Channel Mode
•MSBF: Bit Order
0: Least significant bit is sent/received first.
1: Most significant bit is sent/received first.
• MODE9: 9-bit Character Length
0: CHRL defines character length
1: 9-bit character length
Value Name Description
0 5_BIT Character length is 5 bits
1 6_BIT Character length is 6 bits
2 7_BIT Character length is 7 bits
3 8_BIT Character length is 8 bits
Value Name Description
0 EVEN Even parity
1 ODD Odd parity
2 SPACE Parity forced to 0 (Space)
3 MARK Parity forced to 1 (Mark)
4NONo parity
6 MULTIDROP Multidrop mode
Value Name Description
0 1_BIT 1 stop bit
1 1_5_ BIT 1.5 stop bit (SYNC = 0) or reserved (SYNC = 1)
2 2_BIT 2 stop bits
Value Name Description
0 NORMAL Normal mode
1 AUTOMATIC Automatic Echo. Receiver input is connected to the TXD pin.
2 LOCAL_LOOPBACK Local Loopback. Transmitter output is connected to the Receiver Input.
3 REMOTE_LOOPBACK Remote Loopb ack. RXD pin is internally connected to the TXD pin.
821
SAM4S Series [DATASHEET]
Atmel-11100K-ATARM-SAM4S-Datasheet_09-Jun-15
• CLKO: Clock Output Select
0: The USART does not drive the SCK pin.
1: The USART drives the SCK pin if USCLKS does not select the external clock SCK.
• OVER: Oversampling Mode
0: 16 × Oversampling
1: 8 × Oversampling
• INACK: Inhibit Non Acknowledge
0: The NACK is generated.
1: The NACK is not generated.
• DSNACK: Disable Successive NACK
0: NACK is sent on the ISO line as soon as a parity error occurs in the received character (unless INACK is set).
1: Successive parity errors are counted up to the value specified in the MAX_ITERATION field. These parity errors gener-
ate a NACK on the ISO line. As soon as th is value is reache d, no additional NACK is sent on the ISO line. The flag ITER is
asserted.
Note: MAX_ITERATION field must be set to 0 if DSNACK is cleared.
• INVDATA: Inverted Data
0: The data field transmitted on TXD line is the same as the one written in US_THR or the content read in US_RHR is the
same as RXD line. Normal mode of operation.
1: The data field transmitted on TXD line is inve rted (voltage polarity only) compared to the value written on US_THR or the
content read in US_RHR is inverted compared to what is received on RXD line (or ISO7816 IO line). Inverted mode of
operation, use fu l for co nt actless card applic at ion . To be us ed with co nf igu ra tio n bit MSBF .
• VAR_SYNC: Variable Synchronization of Command/Data Sync Start Frame Delimiter
0: User defined configuration of command or data sync field depending on MODSYNC value.
1: The sync field is updated when a character is written into US_THR.
• MAX_ITERATION: Maximum Number of Automatic Iteration
0–7: Defines the maximum number of iterations in mode ISO7816, protocol T = 0.
• FILTER: Receive Line Filter
0: The USART does not filter the receive line.
1: The USART filters the receive line using a three-sample filter (1/16-bit clock) (2 over 3 majority).
• MAN: Manchester Encoder/Decoder Enable
0: Manchester encoder/decoder are disabled.
1: Manchester encoder/decoder are enabled.
• MODSYNC: Manchester Synchronization Mode
0:The Manchester start bit is a 0 to 1 transition
1: The Manchester start bit is a 1 to 0 transition.
SAM4S Series [DATASHEET]
Atmel-11100K-ATARM-SAM4S-Datasheet_09-Jun-15
822
• ONEBIT: Start Frame Delimiter Selector
0: Start frame delimiter is COMMAND or DATA SYNC.
1: Start frame delimiter is one bit.
823
SAM4S Series [DATASHEET]
Atmel-11100K-ATARM-SAM4S-Datasheet_09-Jun-15
36.7.4 USART Mode Register (SPI_MODE)
Name: US_MR (SPI_MODE)
Address: 0x40024004 (0), 0x40028004 (1)
Access: Read/Write
This configuration is relevant only if USART_MODE = 0xE or 0xF in the USART Mode Register.
• USART_MODE: USART Mode of Operation
• USCLKS: Clock Selection
• CHRL: Character Length
• CPHA: SPI Clock Phase
– Applicable if USART operates in SPI mode (USART_MODE = 0xE or 0xF):
0: Data is changed on the leading edge of SPCK and captured on the following edge of SPCK.
1: Data is captured on the leading edge of SPCK and changed on the fo llowing edge of SPCK.
CPHA determines which e dge of SPCK causes data to change a nd which edge causes da ta to be captured. CPHA is used
with CPOL to produce the required clock/data relationship between master and slave devices.
• CPOL: SPI Clock Polarity
Applicable if USART operates in SPI mode (slave or master, USART_MODE = 0xE or 0xF):
0: The inactive state value of SPCK is logic level zero.
1: The inactive state value of SPCK is logic level one.
31 30 29 28 27 26 25 24
––––––––
23 22 21 20 19 18 17 16
– – – WRDBT – CLKO – CPOL
15 14 13 12 11 10 9 8
–––––––CPHA
76543210
CHRL USCLKS USART_MODE
This register can only be written if the WPEN bit is cleared in the USART Write Protection Mode Register.
Value Name Description
0xE SPI_MASTER SPI master
0xF SPI_SLAVE SPI Slave
Value Name Description
0 MCK Peripheral clock is selected
1 DIV Peripheral clock divided (DIV=8) is selected
3 SCK Serial Clock SLK is selected
Value Name Description
3 8_BIT Character length is 8 bits
SAM4S Series [DATASHEET]
Atmel-11100K-ATARM-SAM4S-Datasheet_09-Jun-15
824
CPOL is used to determine the inactive state value of the serial clock (SPCK). It is used with CPHA to prod uce the requir ed
clock/data relationship between master and slave devices.
• CLKO: Clock Output Select
0: The USART does not drive the SCK pin.
1: The USART drives the SCK pin if USCLKS does not select the external clock SCK.
• WRDBT: Wait Read Data Before Transfer
0: The character transmission starts as soon as a character is written into US_THR (assuming TXRDY was set).
1: The character transmission starts when a char acter is writte n and only if RXRDY flag is clear ed (Receive Holding Regis-
ter has been read).
825
SAM4S Series [DATASHEET]
Atmel-11100K-ATARM-SAM4S-Datasheet_09-Jun-15
36.7.5 USART Interrupt Enable Register
Name: US_IER
Address: 0x40024008 (0), 0x40028008 (1)
Access: Write-only
For SPI specific configuration, see Section 36.7.6 ”USART Interrupt Enable Register (SPI_MODE)”.
The following configuration values are valid for all listed bit names of this register:
0: No effect
1: Enables the corresponding interrupt.
• RXRDY: RXRDY Interrupt Enable
• TXRDY: TXRDY Interrupt Enable
• RXBRK: Receiver Break Interrupt Enable
• ENDRX: End of Receive Buffer Interrupt Enable (available in all USART modes of operation)
• ENDTX: End of Transmit Buffer Interrupt Enable (available in all USART modes of operation)
• OVRE: Overrun Error Interrupt Enable
• FRAME: Framing Error Interrupt Enable
• PARE: Parity Error Interrupt Enable
• TIMEOUT: Time-out Interrupt Enable
• TXEMPTY: TXEMPTY Interrupt Enable
• ITER: Max number of Repetitions Reached Interr upt Enable
• TXBUFE: Transmit Buffer Empty Interrupt Enable (available in all USART modes of operation)
• RXBUFF: Receive Buffer Full Interrupt Enable (available in all USART modes of operation)
• NACK: Non Acknowledge Interrupt Enable
• RIIC: Ring Indicator Input Change Enable
31 30 29 28 27 26 25 24
–––––––MANE
23 22 21 20 19 18 17 16
––––CTSICDCDIC DSRIC RIIC
15 14 13 12 11 10 9 8
– – NACK RXBUFF TXBUFE ITER TXEMPTY TIMEOUT
76543210
PARE FRAME OVRE ENDTX ENDRX RXBRK TXRDY RXRDY
SAM4S Series [DATASHEET]
Atmel-11100K-ATARM-SAM4S-Datasheet_09-Jun-15
826
• DSRIC: Data Set Ready Input Change Enable
• DCDIC: Data Carrier Detect Input Change Interrupt Enable
• CTSIC: Clear to Send Input Change Interrupt Enable
• MANE: Manchester Error Interrupt Enable
827
SAM4S Series [DATASHEET]
Atmel-11100K-ATARM-SAM4S-Datasheet_09-Jun-15
36.7.6 USART Interrupt Enable Register (SPI_MODE)
Name: US_IER (SPI_MODE)
Address: 0x40024008 (0), 0x40028008 (1)
Access: Write-only
This configuration is relevant only if USART_MODE = 0xE or 0xF in the USART Mode Register.
The following configuration values are valid for all listed bit names of this register:
0: No effect
1: Enables the corresponding interrupt.
• RXRDY: RXRDY Interrupt Enable
• TXRDY: TXRDY Interrupt Enable
• ENDRX: End of Receive Buffer Interrupt Enable
• ENDTX: End of Transmit Buffer Interrupt Enable
• OVRE: Overrun Error Interrupt Enable
• TXEMPTY: TXEMPTY Interrupt Enable
• UNRE: SPI Underrun Error Interrupt Enable
• TXBUFE: Transmit Buffer Empty Interrupt Enable
• RXBUFF: Receive Buffer Full Interrupt Enable
31 30 29 28 27 26 25 24
––––––––
23 22 21 20 19 18 17 16
––––––––
15 14 13 12 11 10 9 8
– – – RXBUFF TXBUFE UNRE TXEMPTY –
76543210
– – OVRE ENDTX ENDRX – TXRDY RXRDY
SAM4S Series [DATASHEET]
Atmel-11100K-ATARM-SAM4S-Datasheet_09-Jun-15
828
36.7.7 USART Interrupt Disable Register
Name: US_IDR
Address: 0x4002400C (0), 0x4002800C (1)
Access: Write-only
For SPI specific configuration, see Section 36.7.8 ”USART Interrupt Disable Register (SPI_MODE)”.
The following configuration values are valid for all listed bit names of this register:
0: No effect
1: Disables the corresponding interrupt.
• RXRDY: RXRDY Interrupt Disable
• TXRDY: TXRDY Interrupt Disable
• RXBRK: Receiver Break Interrupt Disable
• ENDRX: End of Receive Buffer Transfer Interrupt Disable (available in all USART modes of operation)
• ENDTX: End of Transmit Buffer Interrupt Disable (available in all USART modes of operation)
• OVRE: Overrun Error Interrupt Enable
• FRAME: Framing Error Interrupt Disable
• PARE: Parity Error Interrupt Disable
• TIMEOUT: Time-out Interrupt Disable
• TXEMPTY: TXEMPTY Interrupt Disable
• ITER: Max Number of Repetitions Reached Interrupt Disable
• TXBUFE: Transmit Buffer Empty Interrupt Disable (available in all USART modes of operation)
• RXBUFF: Receive Buffer Full Interrupt Disable (available in all USART modes of operation)
• NACK: Non Acknowledge Interrupt Disable
• RIIC: Ring Indicator Input Change Disable
31 30 29 28 27 26 25 24
–––––––MANE
23 22 21 20 19 18 17 16
––––CTSICDCDIC DSRIC RIIC
15 14 13 12 11 10 9 8
– – NACK RXBUFF TXBUFE ITER TXEMPTY TIMEOUT
76543210
PARE FRAME OVRE ENDTX ENDRX RXBRK TXRDY RXRDY
829
SAM4S Series [DATASHEET]
Atmel-11100K-ATARM-SAM4S-Datasheet_09-Jun-15
• DSRIC: Data Set Ready Input Change Disable
• DCDIC: Data Carrier Detect Input Change Interrupt Disable
• CTSIC: Clear to Send Input Change Interrupt Disable
• MANE: Manchester Error Interrupt Disable
SAM4S Series [DATASHEET]
Atmel-11100K-ATARM-SAM4S-Datasheet_09-Jun-15
830
36.7.8 USART Interrupt Disable Register (SPI_MODE)
Name: US_IDR (SPI_MODE)
Address: 0x4002400C (0), 0x4002800C (1)
Access: Write-only
This configuration is relevant only if USART_MODE = 0xE or 0xF in the USART Mode Register.
The following configuration values are valid for all listed bit names of this register:
0: No effect
1: Disables the corresponding interrupt.
• RXRDY: RXRDY Interrupt Disable
• TXRDY: TXRDY Interrupt Disable
• ENDRX: End of Receive Buffer Transfer Interrupt Disable
• ENDTX: End of Transmit Buffer Interrupt Disable
• OVRE: Overrun Error Interrupt Disable
• TXEMPTY: TXEMPTY Interrupt Disable
• UNRE: SPI Underrun Error Interrupt Disable
• TXBUFE: Transmit Buffer Empty Interrupt Disable
• RXBUFF: Receive Buffer Full Interrupt Disable
31 30 29 28 27 26 25 24
––––––––
23 22 21 20 19 18 17 16
––––––––
15 14 13 12 11 10 9 8
– – – RXBUFF TXBUFE UNRE TXEMPTY –
76543210
– – OVRE ENDTX ENDRX – TXRDY RXRDY
831
SAM4S Series [DATASHEET]
Atmel-11100K-ATARM-SAM4S-Datasheet_09-Jun-15
36.7.9 USART Interrupt Mask Register
Name: US_IMR
Address: 0x40024010 (0), 0x40028010 (1)
Access: Read-only
For SPI specific configuration, see Section 36.7.10 ”USART Interrupt Mask Register (SPI_MODE)”.
The following configuration values are valid for all listed bit names of this register:
0: The corresponding interrupt is not enabled.
1: The corresponding interrupt is enabled.
• RXRDY: RXRDY Interrupt Mask
• TXRDY: TXRDY Interrupt Mask
• RXBRK: Receiver Break Interrupt Mask
• ENDRX: End of Receive Buffer Interrupt Mask (available in all USART modes of operation)
• ENDTX: End of Transmit Buffer Interrupt Mask (available in all USART modes of operation)
• OVRE: Overrun Error Interrupt Mask
• FRAME: Framing Error Interrupt Mask
• PARE: Parity Error Interrupt Mask
• TIMEOUT: Time-out Interrupt Mask
• TXEMPTY: TXEMPTY Interrupt Mask
• ITER: Max Number of Repetitions Reached Interrupt Ma sk
• TXBUFE: Transmit Buffer Empty Interrupt Mask (available in all USART modes of operation)
• RXBUFF: Receive Buffer Full Interrupt Mask (available in all USART modes of operation)
• NACK: Non Acknowledge Interrupt Mask
• RIIC: Ring Indicator Input Change Mask
31 30 29 28 27 26 25 24
–––––––MANE
23 22 21 20 19 18 17 16
––––CTSICDCDIC DSRIC RIIC
15 14 13 12 11 10 9 8
– – NACK RXBUFF TXBUFE ITER TXEMPTY TIMEOUT
76543210
PARE FRAME OVRE ENDTX ENDRX RXBRK TXRDY RXRDY
SAM4S Series [DATASHEET]
Atmel-11100K-ATARM-SAM4S-Datasheet_09-Jun-15
832
• DSRIC: Data Set Ready Input Change Mask
• DCDIC: Data Carrier Detect Input Change Interrupt Mask
• CTSIC: Clear to Send Input Change Interrupt Mask
• MANE: Manchester Error Interrupt Mask
833
SAM4S Series [DATASHEET]
Atmel-11100K-ATARM-SAM4S-Datasheet_09-Jun-15
36.7.10 USART Interrupt Mask Register (SPI_MODE)
Name: US_IMR (SPI_MODE)
Address: 0x40024010 (0), 0x40028010 (1)
Access: Read-only
This configuration is relevant only if USART_MODE = 0xE or 0xF in the USART Mode Register.
The following configuration values are valid for all listed bit names of this register:
0: The corresponding interrupt is not enabled.
1: The corresponding interrupt is enabled.
• RXRDY: RXRDY Interrupt Mask
• TXRDY: TXRDY Interrupt Mask
• ENDRX: End of Receive Buffer Interrupt Mask
• ENDTX: End of Transmit Buffer Interrupt Mask
• OVRE: Overrun Error Interrupt Mask
• TXEMPTY: TXEMPTY Interrupt Mask
• UNRE: SPI Underrun Error Interrupt Mask
• TXBUFE: Transmit Buffer Empty Interrupt Mask
• RXBUFF: Receive Buffer Full Interrupt Mask
31 30 29 28 27 26 25 24
––––––––
23 22 21 20 19 18 17 16
––––––––
15 14 13 12 11 10 9 8
– – – RXBUFF TXBUFE UNRE TXEMPTY –
76543210
– – OVRE ENDTX ENDRX – TXRDY RXRDY
SAM4S Series [DATASHEET]
Atmel-11100K-ATARM-SAM4S-Datasheet_09-Jun-15
834
36.7.11 USART Channel Status Register
Name: US_CSR
Address: 0x40024014 (0), 0x40028014 (1)
Access: Read-only
For SPI specific configuration, see Section 36.7.12 ”USART Channel Status Register (S PI_MODE)”.
• RXRDY: Receiver Ready (c leared by reading US_RHR)
0: No complete character has been received since the last read of US_RHR or the receiver is disabled. If characters were
being received when the receiver was disabled, RXRDY changes to 1 when the receiver is enabled.
1: At least one complete character has been received and US_RHR has not yet been read.
• TXRDY: Transmitter Ready (cleared by writing US_THR)
0: A character is in the US_THR waiting to be transferred to the Transmit Shift Register, or an STTBRK command has
been requested, or the tra nsmitter is disabled. As soon as the trTable 36-15 “Register Mapping”ansmitter is enabled, TXRDY
becomes 1.
1: There is no character in the US_THR.
• RXBRK: Break Received/End of Break (cleared by writing a one to bit US_CR.RSTSTA)
0: No break received or end of break detected since the last RSTSTA.
1: Break received or end of break detected since the last RSTSTA.
• ENDRX: End of RX Buffer (cleared by writing US_RCR or US_RNCR)
0: The Receive Counter Register has not reached 0 since the last write in US_RCR or US_RNCR(1).
1: The Receive Counter Register has reached 0 since the last write in US_RCR or US_RNCR(1).
• ENDTX: End of TX Buffer (cleared by writing US_TCR or US_TNCR)
0: The Transmit Counter Register has not reached 0 since the last write in US_TCR or US_TNCR(1).
1: The Transmit Counter Register has reached 0 since the last write in US_TCR or US_TNCR(1).
• OVRE: Overrun Error (cleared by writing a one to bit US_CR.RSTSTA)
0: No overrun error has occur re d sin ce the las t R STSTA.
1: At least one overrun error has occurred since the last RSTSTA.
31 30 29 28 27 26 25 24
–––––––MANERR
23 22 21 20 19 18 17 16
CTS DCD DSR RI CTSIC DCDIC DSRIC RIIC
15 14 13 12 11 10 9 8
– – NACK RXBUFF TXBUFE ITER TXEMPTY TIMEOUT
76543210
PARE FRAME OVRE ENDTX ENDRX RXBRK TXRDY RXRDY
835
SAM4S Series [DATASHEET]
Atmel-11100K-ATARM-SAM4S-Datasheet_09-Jun-15
• FRAME: Framing Error (cleared by writing a one to bit US_CR.RSTSTA)
0: No stop bit has been detected low since the last RSTSTA.
1: At least one stop bit has been detected low since the last RSTSTA.
• PARE: Parity Error (cleared by writing a one to bit US_CR.RSTSTA)
0: No parity error has been detected since the last RSTSTA.
1: At least one parity error has been detected since the last RSTSTA.
• TIMEOUT: Receiver Time-out (cleared by writing a one to b it US_ CR.S TT TO)
0: There has not been a time-out since the last Start Time-out command (STTT O in US_CR) or the Ti me- out Regi ster is 0.
1: There has been a time-out since the last Start Time-out command (STTTO in US_CR).
• TXEMPTY: Transmitter Empty (cleared by writing US_THR)
0: There are characters in either US_THR or the Transmit Shift Register, or the transmitter is disabled .
1: There are no characters in US_THR, nor in the Transmit Shift Register.
• ITER: Max Number of Repetitions Reached (cleared by writing a one to bit US_CR.RSTIT)
0: Maximum number of repetitions has not been reached since the last RSTIT.
1: Maximum number of repetitions has been reached since the last RSTIT.
• TXBUFE: TX Buffer Empty (cleared by writing US_TCR or US_TNCR)
0: US_TCR or US_TNCR have a value other than 0(1).
1: Both US_TCR and US_TNCR have a value of 0(1).
• RXBUFF: RX Buffer Full (cleared by writing US_RCR or US_RNCR)
0: US_RCR or US_RNCR have a value other than 0(1).
1: Both US_RCR and US_RNCR have a value of 0(1).
Note: 1. US_RCR, US_RNCR, US_TCR and US_TNCR are PDC registers.
• NACK: Non Acknowledge Interrupt (cleared by writing a one to bit US_CR.RSTNACK)
0: Non acknowledge has not been detected since the last RSTNACK.
1: At least one non acknowledge has been detected since the last RSTNACK.
• RIIC: Ring Indicator Input Change Flag (cleared on read)
0: No input change has been detected on the RI pin since the last read of US_CSR.
1: At least one input change has been detected on the RI pin since the last read of US_CSR.
• DSRIC: Data Set Ready Input Change Flag (cleared on read)
0: No input change has been detected on the DSR pin since the last read of US_CSR.
1: At least one input change has been detected on the DSR pin since the last read of US_CSR.
• DCDIC: Data Carrier Detect Input Change Flag (cleared on read)
0: No input change has been detected on the DCD pin since the last read of US_CSR.
1: At least one input change has been detected on the DCD pin since the last read of US_CSR.
SAM4S Series [DATASHEET]
Atmel-11100K-ATARM-SAM4S-Datasheet_09-Jun-15
836
• CTSIC: Clear to Send Input Change Flag (cleared on read)
0: No input change has been detected on the CTS pin since the last read of US_CSR.
1: At least one input change has been detected on the CTS pin since the last read of US_CSR.
• RI: Image of RI Input
0: RI input is driven low.
1: RI input is driven high.
• DSR: Image of DSR Input
0: DSR input is driven low.
1: DSR input is driven high.
• DCD: Image of DCD Input
0: DCD input is driven low.
1: DCD input is driven high.
• CTS: Image of CTS Input
0: CTS input is driven low.
1: CTS input is driven high.
• MANERR: Manchester Error (cleared by writing a one to the bit US_CR.RSTSTA)
0: No Manchester error has been detected since the last RSTSTA.
1: At least one Manchester error has been detected since the last RSTSTA.
837
SAM4S Series [DATASHEET]
Atmel-11100K-ATARM-SAM4S-Datasheet_09-Jun-15
36.7.12 U SART C han ne l Status Register (SPI_MODE)
Name: US_CSR (SPI_MODE)
Address: 0x40024014 (0), 0x40028014 (1)
Access: Read-only
This configuration is relevant only if USART_MODE = 0xE or 0xF in the USART Mode Register.
• RXRDY: Receiver Ready (c leared by reading US_RHR)
0: No complete character has been received since the last read of US_RHR or the receiver is disabled. If characters were
being received when the receiver was disabled, RXRDY changes to 1 when the receiver is enabled.
1: At least one complete character has been received and US_RHR has not yet been read.
• TXRDY: Transmitter Ready (cleared by writing US_THR)
0: A character is in the US_THR waiting to be transferred to the Transmit Shift Register or the transmitter is disabled. As
soon as the tran sm itte r is enab led , T XRDY be co me s 1.
1: There is no character in the US_THR.
• ENDRX: End of RX Buffer (cleared by writing US_RCR or US_RNCR)
0: The Receive Counter Register has not reached 0 since the last write in US_RCR or US_RNCR(1).
1: The Receive Counter Register has reached 0 since the last write in US_RCR or US_RNCR(1).
• ENDTX: End of TX Buffer (cleared by writing US_TCR or US_TNCR)
0: The Transmit Counter Register has not reached 0 since the last write in US_TCR or US_TNCR(1).
1: The Transmit Counter Register has reached 0 since the last write in US_TCR or US_TNCR(1).
• OVRE: Overrun Error (cleared by writing a one to bit US_CR.RSTSTA)
0: No overrun error has occur re d sin ce the las t R STSTA.
1: At least one overrun error has occurred since the last RSTSTA.
• TXEMPTY: Transmitter Empty (cleared by writing US_THR)
0: There are characters in either US_THR or the Transmit Shift Register, or the transmitter is disabled .
1: There are no characters in US_THR, nor in the Transmit Shift Register.
31 30 29 28 27 26 25 24
––––––––
23 22 21 20 19 18 17 16
––––––––
15 14 13 12 11 10 9 8
– – – RXBUFF TXBUFE UNRE TXEMPTY –
76543210
– – OVRE ENDTX ENDRX – TXRDY RXRDY
SAM4S Series [DATASHEET]
Atmel-11100K-ATARM-SAM4S-Datasheet_09-Jun-15
838
• UNRE: Underrun Error (cleared by writin g a on e to bit US_ CR.RSTSTA)
0: No SPI underrun error has occurred since the last RSTSTA.
1: At least one SPI underrun error has occurred since the last RSTSTA.
• TXBUFE: TX Buffer Empty (cleared by writing US_TCR or US_TNCR)
0: US_TCR or US_TNCR have a value other than 0(1).
1: Both US_TCR and US_TNCR have a value of 0(1).
• RXBUFF: RX Buffer Full (cleared by writing US_RCR or US_RNCR)
0: US_RCR or US_RNCR have a value other than 0(1).
1: Both US_RCR and US_RNCR have a value of 0(1).
Note: 1. US_RCR, US_RNCR, US_TCR and US_TNCR are PDC registers.
839
SAM4S Series [DATASHEET]
Atmel-11100K-ATARM-SAM4S-Datasheet_09-Jun-15
36.7.13 USART Receive Holding Register
Name: US_RHR
Address: 0x40024018 (0), 0x40028018 (1)
Access: Read-only
• RXCHR: Received Character
Last character received if RXRDY is set.
• RXSYNH: Received Sync
0: Last character received is a data.
1: Last character received is a command.
31 30 29 28 27 26 25 24
––––––––
23 22 21 20 19 18 17 16
––––––––
15 14 13 12 11 10 9 8
RXSYNH ––––––RXCHR
76543210
RXCHR
SAM4S Series [DATASHEET]
Atmel-11100K-ATARM-SAM4S-Datasheet_09-Jun-15
840
36.7.14 USART Transmit Holding Register
Name: US_THR
Address: 0x4002401C (0), 0x4002801C (1)
Access: Write-only
• TXCHR: Chara cte r to be Transmi tt ed
Next character to be transmitted after the current character if TXRDY is not set.
• TXSYNH: Sync Field to be Transmitted
0: The next character sent is encoded as a data. Start frame delimiter is DATA SYNC.
1: The next character sent is encoded as a command. Start frame delimiter is COMMAND SYNC.
31 30 29 28 27 26 25 24
––––––––
23 22 21 20 19 18 17 16
––––––––
15 14 13 12 11 10 9 8
TXSYNH ––––––TXCHR
76543210
TXCHR
841
SAM4S Series [DATASHEET]
Atmel-11100K-ATARM-SAM4S-Datasheet_09-Jun-15
36.7.15 USART Baud Rate Generator Register
Name: US_BRGR
Address: 0x40024020 (0), 0x40028020 (1)
Access: Read/Write
This register can only be written if the WPEN bit is cleared in the USART Write Protection Mode Register.
• CD: Clock Divider
• FP: Fractional Part
0: Fractional divider is disabled.
1–7: Baud rate resolution, defined by FP × 1/8.
31 30 29 28 27 26 25 24
––––––––
23 22 21 20 19 18 17 16
––––– FP
15 14 13 12 11 10 9 8
CD
76543210
CD
CD
USART_MODE ≠ ISO7816
USART_MODE = ISO7816
SYNC = 0 SYNC = 1
or
USART_MODE = SPI
(Master or Slave)OVER = 0 OVER = 1
0 Baud Rate Clock Disabled
1 to 65535 CD = Selected Clock / (16 ×
Baud Rate) CD = Selected Clock / (8 ×
Baud Rate) CD = Selected Clock / Baud
Rate
CD = Selected Clock /
(FI_DI_RATIO × Baud
Rate)
SAM4S Series [DATASHEET]
Atmel-11100K-ATARM-SAM4S-Datasheet_09-Jun-15
842
36.7.16 USART Receiver Time-out Register
Name: US_RTOR
Address: 0x40024024 (0), 0x40028024 (1)
Access: Read/Write
This register can only be written if the WPEN bit is cleared in the USART Write Protection Mode Register.
• TO: Time-out Value
0: The receiver time-out is disabled.
1–65535: The receiver time-out is enabled and TO is Time-out Delay / Bit Period.
31 30 29 28 27 26 25 24
––––––––
23 22 21 20 19 18 17 16
––––––––
15 14 13 12 11 10 9 8
TO
76543210
TO
843
SAM4S Series [DATASHEET]
Atmel-11100K-ATARM-SAM4S-Datasheet_09-Jun-15
36.7.17 USART Transmitter Timeguard Register
Name: US_TTGR
Address: 0x40024028 (0), 0x40028028 (1)
Access: Read/Write
This register can only be written if the WPEN bit is cleared in the USART Write Protection Mode Register.
• TG: Timeguard Value
0: The transmitter timeguard is disabled.
1–255: The transmitter timeguard is enabled and TG is Timeguard Delay / Bit Period.
31 30 29 28 27 26 25 24
––––––––
23 22 21 20 19 18 17 16
––––––––
15 14 13 12 11 10 9 8
––––––––
76543210
TG
SAM4S Series [DATASHEET]
Atmel-11100K-ATARM-SAM4S-Datasheet_09-Jun-15
844
36.7.18 USART FI DI RATIO Register
Name: US_FIDI
Address: 0x40024040 (0), 0x40028040 (1)
Access: Read/Write
• FI_DI_RATIO: FI Over DI Ratio Value
0: If ISO7816 mode is selected, the baud rate generator ge nerates no signal.
1–2: Do not use.
3–2047: If ISO7816 mode is selected, the baud rate is the clock provided on SCK divided by FI_DI_RATIO.
31 30 29 28 27 26 25 24
––––––––
23 22 21 20 19 18 17 16
––––––––
15 14 13 12 11 10 9 8
––––– FI_DI_RATIO
76543210
FI_DI_RATIO
This register can only be written if the WPEN bit is cleared in the USART Write Protection Mode Register.
845
SAM4S Series [DATASHEET]
Atmel-11100K-ATARM-SAM4S-Datasheet_09-Jun-15
36.7.19 USART Number of Errors Register
Name: US_NER
Address: 0x40024044 (0), 0x40028044 (1)
Access: Read-only
This register is relevant only if USART_MODE = 0x4 or 0x 6 in the USART Mode Register.
• NB_ERRORS: Number of Errors
Total number of errors that occurred during an ISO7816 transfer. This register automatically clears when read.
31 30 29 28 27 26 25 24
––––––––
23 22 21 20 19 18 17 16
––––––––
15 14 13 12 11 10 9 8
––––––––
76543210
NB_ERRORS
SAM4S Series [DATASHEET]
Atmel-11100K-ATARM-SAM4S-Datasheet_09-Jun-15
846
36.7.20 USART IrDA Filter Register
Name: US_IF
Address: 0x4002404C (0), 0x4002804C (1)
Access: Read/Write
This register is relevant only if USART_MODE = 0x8 in the USART Mode Register.
• IRDA_FILTER: IrDA Filter
The IRDA_FIL TE R valu e m ust be defined to meet the following criteria:
tperipheral clock × (IRDA_FILTER + 3) < 1.41 µs
31 30 29 28 27 26 25 24
––––––––
23 22 21 20 19 18 17 16
––––––––
15 14 13 12 11 10 9 8
––––––––
76543210
IRDA_FILTER
This register can only be written if the WPEN bit is cleared in the USART Write Protection Mode Register.
847
SAM4S Series [DATASHEET]
Atmel-11100K-ATARM-SAM4S-Datasheet_09-Jun-15
36.7.21 USART Manchester Configuration Register
Name: US_MAN
Address: 0x40024050 (0), 0x40028050 (1)
Access: Read/Write
• TX_PL: Transmitter Preamble Length
0: The transmitter preamble pattern generation is disabled
1–15: The preamble length is TX_PL × Bit Period
• TX_PP: Transmitter Preamble Pattern
The following values assume that TX_MPOL field is not set:
• TX_MPOL: Transmitter Manchester Polarity
0: Logic zero is coded as a zero-to-one transition, Logic one is coded as a one-to-zero transition.
1: Logic zero is coded as a one-to-zero transition, Logic one is coded as a zero- to-one transition.
• RX_PL: Receiver Preamble Length
0: The receiver preamble pattern detection is disabled
1–15: The detected preamble length is RX_PL × Bit Period
31 30 29 28 27 26 25 24
–DRIFTONERX_MPOL– – RX_PP
23 22 21 20 19 18 17 16
–––– RX_PL
15 14 13 12 11 10 9 8
– – – TX_MPOL – – TX_PP
76543210
–––– TX_PL
This register can only be written if the WPEN bit is cleared in the USART Write Protection Mode Register.
Value Name Description
0 ALL_ONE The prea mble is composed of ‘1’s
1 ALL_ZERO The preamble is composed of ‘0’s
2 ZERO_ONE T he preamble is composed of ‘01’s
3 ONE_ZERO The preamble is composed of ‘10’s
SAM4S Series [DATASHEET]
Atmel-11100K-ATARM-SAM4S-Datasheet_09-Jun-15
848
• RX_PP: Receiver Preamble Pattern detected
The following values assume that RX_MPOL field is not set:
• RX_MPOL: Receiver Manchester Polarity
0: Logic zero is coded as a zero-to-one transition, Logic one is coded as a one-to-zero transition.
1: Logic zero is coded as a one-to-zero transition, Logic one is coded as a zero- to-one transition.
• ONE: Must Be Set to 1
Bit 29 must always be set to 1 when programming the US_MAN reg ister.
• DRIFT: Drift Compensation
0: The USART cannot recover from an important clock drift
1: The USART can recover from clock drift. The 16X clock mode must be enabled.
Value Name Description
00 ALL_ONE The preamble is composed of ‘1’s
01 ALL_ZERO The preamble is composed of ‘0’s
10 ZERO_ONE The preamble is composed of ‘01’s
11 ONE_ZERO The preamble is composed of ‘10’s
849
SAM4S Series [DATASHEET]
Atmel-11100K-ATARM-SAM4S-Datasheet_09-Jun-15
36.7.22 USART Write Protection Mode Register
Name: US_WPMR
Address: 0x400240E4 (0), 0x400280E4 (1)
Access: Read/Write
• WPEN: Write Protec ti on Ena b le
0: Disables the write protection if WPKEY corresponds to 0x555341 (“USA” in ASCII).
1: Enables the write protection if WPKEY corresponds to 0x555341 (“USA” in ASCII).
See Section 36.6.10 ”Register Write Protection” for the list of registers that can be write-protected.
• WPKEY: Write Protection Key
31 30 29 28 27 26 25 24
WPKEY
23 22 21 20 19 18 17 16
WPKEY
15 14 13 12 11 10 9 8
WPKEY
76543210
–––––––WPEN
Value Name Description
0x555341 PASSWD Writing any other value in this field aborts the write operation of the WPEN bit. Always reads as
0.
SAM4S Series [DATASHEET]
Atmel-11100K-ATARM-SAM4S-Datasheet_09-Jun-15
850
36.7.23 USART Write Protection Status Register
Name: US_WPSR
Address: 0x400240E8 (0), 0x400280E8 (1)
Access: Read-only
• WPVS: Write Protection Violation Status
0: No write protec tion v iola tio n ha s oc curred since the last read of the US_WPSR.
1: A write protection violation has occur red since the last rea d of the US_WPSR. If th is violation is an unauthorize d attempt
to write a protected register, the associated violation is reported into field WPVSRC.
• WPVSRC: Write Protection Violation Source
When WPVS = 1, WPVSRC indicates the register address offset at which a write access has been attempted.
31 30 29 28 27 26 25 24
––––––––
23 22 21 20 19 18 17 16
WPVSRC
15 14 13 12 11 10 9 8
WPVSRC
76543210
–––––––WPVS
851
SAM4S Series [DATASHEET]
Atmel-11100K-ATARM-SAM4S-Datasheet_09-Jun-15
37. Timer Counter (TC)
37.1 Description
A Timer Counter (TC) module includes three identical TC channels. The number of implemented TC modules is
device-specific.
Each TC channel can be independently programmed to perform a wide range of functions including frequency
measurement, event counting, interval measurement, pulse generation, delay timing and pulse width modulation.
Each channel has three external clock inputs, five internal clock inputs and two multi-purpose input/output signals
which can be configured by the user. Each cha nnel drive s an internal inter rupt signal which can be progra mmed to
generate processor interrupts.
The TC embeds a quadrature decoder (QDEC) connected in front of the timers and driven by TIOA0, TIOB0 and
TIOB1 inputs. When enabled, the QDEC performs the input lines filtering, decoding of quadrature signals and
connects to the timers/counters in order to read the posit i on an d spe e d of th e mo to r thro ug h the us er inte rfa ce .
The TC block has two global registers which act upon all TC channels:
Block Control Register (TC_BCR)—allows channels to be started simultaneously with the same instruction
Block Mode Register (TC_BMR)—defines the external clock inputs for each channel, allowing them to be
chained
37.2 Embedded Characteristics
Total number of TC channels: 6
TC channel size: 16-bit
Wide range of functions including:
Frequency measurement
Event counting
Interval measurement
Pulse generation
Delay timing
Pulse Width Modulation
Up/down capabilities
Quadrature decoder
2-bit gray up/down count for stepper motor
Each channel is user-configurable and contains:
Three exte rn al cloc k inp uts
Five Internal clock inputs
Two multi-purpose input/output signals acting as trigger event
Internal interrupt signal
Compare event fault generation for PWM
Register Write Protection
SAM4S Series [DATASHEET]
Atmel-11100K-ATARM-SAM4S-Datasheet_09-Jun-15
852
37.3 Block Diagram
Note: 1. When SLCK is selected for Peripheral Clock (CSS = 0 in PMC Master Clock Register), SLCK input is equivalent
to Peripheral Clock.
Figure 37-1. Timer Counter Block Diagram
Note: The QDEC connections are detailed in Figure 37-15.
Table 37-1. Timer Counter Clock Assig nment
Name Definition
TIMER_CLOCK1 MCK/2
TIMER_CLOCK2 MCK/8
TIMER_CLOCK3 MCK/32
TIMER_CLOCK4 MCK/128
TIMER_CLOCK5 SLCK
Timer/Counter
Channel 0
Timer/Counter
Channel 1
Timer/Counter
Channel 2
SYNC
Parallel I/O
Controller
TC1XC1S
TC0XC0S
TC2XC2S
INT0
INT1
INT2
TIOA0
TIOA1
TIOA2
TIOB0
TIOB1
TIOB2
XC0
XC1
XC2
XC0
XC1
XC2
XC0
XC1
XC2
TCLK0
TCLK1
TCLK2
TCLK0
TCLK1
TCLK2
TCLK0
TCLK1
TCLK2
TIOA1
TIOA2
TIOA0
TIOA2
TIOA0
TIOA1
Interrupt
Controller
TCLK0
TCLK1
TCLK2
TIOA0
TIOB0
TIOA1
TIOB1
TIOA2
TIOB2
Timer Counter
TIOA
TIOB
TIOA
TIOB
TIOA
TIOB
SYNC
SYNC
TIMER_CLOCK2
TIMER_CLOCK3
TIMER_CLOCK4
TIMER_CLOCK5
TIMER_CLOCK1
FAULT
PWM
853
SAM4S Series [DATASHEET]
Atmel-11100K-ATARM-SAM4S-Datasheet_09-Jun-15
37.4 Pin List
37.5 Product Dependencies
37.5.1 I/O Lines
The pins used for interfacing the compliant external devices may be multiplexed with PIO lines. The programmer
must first program the PIO controllers to assign the TC pins to thei r peripheral functions.
Table 37-2. Signal Description
Block/Channel Signal Name Description
Channel Signal
XC0, XC1, XC2 External Clock Inputs
TIOA Capture Mode: Timer Counter Input
Waveform Mode: Timer Counter Output
TIOB Capture Mode: Timer Counter Input
Waveform Mode: Timer Counter Input/Output
INT Interrupt Signal Output (internal sign al)
SYNC Syn chronization Input Signal (from configuration register)
Table 37-3 . Pin List
Pin Name Description Type
TCLK0–TCLK2 External Clock Input Input
TIOA0–TIOA2 I/O Line A I/O
TIOB0–TIOB2 I/O Line B I/O
Table 37-4. I/O Lines
Instance Signal I/O Line Periphera l
TC0 TCLK0 PA4 B
TC0 TCLK1 PA28 B
TC0 TCLK2 PA29 B
TC0 TIOA0 PA0 B
TC0 TIOA1 PA15 B
TC0 TIOA2 PA26 B
TC0 TIOB0 PA1 B
TC0 TIOB1 PA16 B
TC0 TIOB2 PA27 B
TC1 TCLK3 PC25 B
TC1 TCLK4 PC28 B
TC1 TCLK5 PC31 B
TC1 TIOA3 PC23 B
TC1 TIOA4 PC26 B
TC1 TIOA5 PC29 B
SAM4S Series [DATASHEET]
Atmel-11100K-ATARM-SAM4S-Datasheet_09-Jun-15
854
37.5.2 Power Management
The TC is clocked through the Power Management Controller (PMC), thus the programmer must first configure the
PMC to enable the Timer Counter clock of each channel.
37.5.3 Interrupt Sources
The TC has an interrupt line per channel connected to the interrupt controller. Handling the TC interrupt requires
programming the interrupt controller before configuring the TC.
37.5.4 Fault Output
The TC has the FAULT output internally connected to the fault input of PWM. Refer to Sectio n 37.6.16 “Fault
Mode” and to the implementatio n of the Puls e Wid th M odula tio n (PW M) in this pr od u ct.
37.6 Functional Description
37.6.1 Description
All channels of the Timer Counter are independent and identical in operation except when the QDEC is enabled.
The registers for channel programming are listed in Table 37-6 “Register Mapping”.
37.6.2 16-bit Counter
Each 16-bit channel is org ani ze d a round a 16 -bit co un ter. The value of the counter is incr eme nted at each po sitive
edge of the selected clock. When the counter has reached the value 216-1 and passes to ze ro , an ove r flow occurs
and the COVFS bit in the TC Status Register (TC_SR) is set.
The current value of the counter is accessible in real time by reading the TC Counter Value Reg ister (TC_CV). The
counter can be reset by a trigge r. In this case, the counter value passes to zero on the next valid edge of the
selected clock.
37.6.3 Clock Selection
At block level, input clock signals of each ch annel can ei ther be connected to the external inputs TCLK0, TCLK1 or
TCLK2, or be connected to the internal I/O signals TIOA0, TIOA1 or TIOA2 for chaining by programming the TC
Block Mode Register (TC_BMR). See Figure 37-2.
Each channel can independently select an internal or external clock source for its counter:
External clock si gn als (1): XC0, XC1 or XC2
Internal clock signals: MCK/2, MCK/8, MCK/32, MCK/128, SLCK
This selection is made by the TCCLKS bits in the TC Channel Mode Register (TC_CMR).
TC1 TIOB3 PC24 B
TC1 TIOB4 PC27 B
TC1 TIOB5 PC30 B
Table 37-4. I/O Lines
Table 37-5. Peripheral IDs
Instance ID
TC0 23
TC1 24
855
SAM4S Series [DATASHEET]
Atmel-11100K-ATARM-SAM4S-Datasheet_09-Jun-15
The selected clock can be inverted with the CLKI bit in the TC_CMR. This allows counting on the opposite edges
of the clock.
The burst function allows the clock to be validated when an external signal is high. The BURST parameter in the
TC_CMR defines this signal (none, XC0, XC1, XC2). See Figure 37-3.
Note: 1. In all cases, if an external clock is used, the duration of each of its levels must be longer than the peripheral clock
period. The external clock fre quency must be at least 2.5 times lower than the peripheral clock.
Figure 37-2. Clock Chaining Selection
Timer/Counter
Channel 0
SYNC
TC0XC0S
TIOA0
TIOB0
XC0
XC1 = TCLK1
XC2 = TCLK2
TCLK0
TIOA1
TIOA2
Timer/Counter
Channel 1
SYNC
TC1XC1S
TIOA1
TIOB1
XC0 = TCLK0
XC1
XC2 = TCLK2
TCLK1
TIOA0
TIOA2
Timer/Counter
Channel 2
SYNC
TC2XC2S
TIOA2
TIOB2
XC0 = TCLK0
XC1 = TCLK1
XC2
TCLK2
TIOA0
TIOA1
SAM4S Series [DATASHEET]
Atmel-11100K-ATARM-SAM4S-Datasheet_09-Jun-15
856
Figure 37-3. Clock Selection
37.6.4 Clock Control
The clock of each counter can be controlled in two different ways: it can be enabled/disabled and started/stopped.
See Figure 37-4.
The clock can be enabled or disabled by the user with the CLKEN and the CLKDIS comma nds in the TC
Channel Control Register (TC_CCR). In Capture mode it can be disabled by an RB load event if LDBDIS is
set to 1 in the TC_CMR. In W avefo rm mode, it can be disabled by an RC Comp are event if CPCDIS is set to
1 in TC_CMR. When disabled, the start or the stop actions have no effect: only a CLKEN command in the
TC_CCR can re-enable the clock. When the clock is enabled, the CLKSTA bit is set in the TC_SR.
The clock can also be started or stopped: a trigger (software, synchro, external or compare) always starts
the clock. The clock can be stopped by an RB load event in Capture mode (LDBSTOP = 1 in TC_CMR) or
an RC compare event in Waveform mode (CPCSTOP = 1 in TC_CMR). The start and the stop commands
are effective only if the clock is enabled.
TIMER_CLOCK1
TIMER_CLOCK2
TIMER_CLOCK3
TIMER_CLOCK4
TIMER_CLOCK5
XC0
XC1
XC2
TCCLKS
CLKI
Synchronous
Edge Detection
BURST
Peripheral Clock
1
Selected
Clock
857
SAM4S Series [DATASHEET]
Atmel-11100K-ATARM-SAM4S-Datasheet_09-Jun-15
Figure 37-4. Clock Control
37.6.5 Operating Modes
Each channel can operate independently in two different modes:
Capture mode provides measurement on signals.
Waveform mode provides wave generation.
The TC operating mode is programmed with the WAVE bit in the TC_CMR.
In Capture mode, TIOA and TIOB are configured as inputs.
In Waveform mode, TIOA is always configured to be an output and TIOB is an outp ut if it is not selected to be the
external trigger.
37.6.6 Trigger
A trigger resets the coun ter and star ts the counter clock. Three types of triggers are common to both modes, and a
fourth external trigger is available to each mode.
Regardless of the trigger used, it will be taken into account at the following active edge of the selected clock. This
means that the counte r value ca n be read differ ently from zer o just after a trigger, especially when a low frequen cy
signal is selected as the clock.
The following triggers are common to both modes:
Software Trigger: Each channel has a software trigger, available by setting SWTRG in TC_CCR.
SYNC: Each channel has a synchronization signal SYNC. When asserted, this signal has th e same effect as
a software trigger. The SYNC signals of all channels are asserted simult aneously by writing TC_BCR (Block
Control) with SYNC set.
Compar e RC Trigger: RC is implemented in each channel an d can pr ovide a trigg er wh en th e cou nter valu e
matches the RC value if CPCTRG is set in the TC_CMR.
The channel can also b e configured to ha ve an external trigger . In Capture mode, the external trigger signal can be
selected between TIOA and TIOB. In Waveform mode, an external even t can be programmed on one of the
following signals: TIOB, XC0, XC1 or XC2. This external event can then be programmed to perform a trigger by
setting bit ENETRG in the TC_CMR.
If an external trigger is used, the duration of the pulses must be longer than the peripheral clock period in order to
be detected.
QS
R
S
R
Q
CLKSTA CLKEN CLKDIS
Stop
Event Disable
Event
Counter
Clock
Selected
Clock Trigger
SAM4S Series [DATASHEET]
Atmel-11100K-ATARM-SAM4S-Datasheet_09-Jun-15
858
37.6.7 Capture Mode
Capture mode is entered by clearing the WAVE bit in the TC_CMR.
Capture mode allows the TC channel to perform measu rements such as pulse timing, frequency, period, duty
cycle and phase on TIOA and TIOB signals which are considered as inputs.
Figure 37-5 shows the configuration of the TC channel when programm ed in Capture mode.
37.6.8 Capture Registers A and B
Registers A and B (RA and RB) are used as capture registers. They can be load ed wit h the counte r valu e whe n a
programmable event occurs on the signal TIOA.
The LDRA field in the TC_CMR defines the TIOA selected edge for the loading of register A, and the LDRB field
defines the TIOA selected edge for the loading of Register B.
RA is loaded only if it has not been loaded since the last trigger or if RB has been loaded since the last loading of
RA.
RB is loaded only if RA has been loaded since the last trigger or the last loading of RB.
Loading RA or RB before the read of the last value loaded sets the Overrun Error Flag (LOVRS bit) in the TC_SR.
In this case, the old value is overwritten.
37.6.9 Trigger Conditions
In addition to the SYNC signal, the so ftware trigger and t he RC compare trigger, an exter nal trigger can be defined.
The ABETRG bit in the TC_CMR selects TIOA or TIOB input signal as an external trigger . The External Trigger
Edge Selection parameter (ETRGEDG field in TC_CMR) defines the edge (rising, falling, or both) detected to
generate an external trigger. If ETRGEDG = 0 (none), the external trigger is disabled.
859
SAM4S Series [DATASHEET]
Atmel-11100K-ATARM-SAM4S-Datasheet_09-Jun-15
Figure 37-5. Capture Mode
TIMER_CLOCK1
TIMER_CLOCK2
TIMER_CLOCK3
TIMER_CLOCK4
TIMER_CLOCK5
XC0
XC1
XC2
TCCLKS
CLKI
QS
R
S
R
Q
CLKSTA CLKEN CLKDIS
BURST
TIOB
Register C
Capture
Register A Capture
Register B Compare RC =
Counter
ABETRG
SWTRG
ETRGEDG CPCTRG
TC1_IMR
Trig
LDRBS
LDRAS
ETRGS
TC1_SR
LOVRS
COVFS
SYNC
1
MTIOB
TIOA
MTIOA
LDRA
LDBSTOP
If RA is not loaded
or RB is Loaded If RA is Loaded
LDBDIS
CPCS
INT
Edge
Detector
Edge
Detector
LDRB
Edge
Detector
CLK OVF
RESET
Timer/Counter Channel
Peripheral Clock
Synchronous
Edge Detection
SAM4S Series [DATASHEET]
Atmel-11100K-ATARM-SAM4S-Datasheet_09-Jun-15
860
37.6.10 Waveform Mode
Waveform mode is entered by setting the TC_CMRx.WAVE bit.
In Waveform mode, the TC channel generates one or two PWM signals with the same frequency and
independently progra mmable duty cycles, or generates different types of one-shot or repetitive pulses.
In this mode, TIOA is configured as an output and TIOB is defined as an output if it is not used as an external event
(EEVT parameter in TC_CMR).
Figure 37-6 shows the configuration of the TC channel when programmed in Waveform operating mode.
37.6.11 Waveform Selection
Depending on the WAVSEL parameter in TC_CMR, the behavior of TC_CV varies.
With any selection, TC_RA, TC_RB and TC_RC can all be used as compare registers.
RA Compare is used to control the TIOA output, RB Compare is used to control the TIOB output (if correctly
configured) and RC Compare is used to control TIOA and/or TIOB outputs.
861
SAM4S Series [DATASHEET]
Atmel-11100K-ATARM-SAM4S-Datasheet_09-Jun-15
Figure 37-6. Waveform Mode
TCCLKS
CLKI
QS
R
S
R
Q
CLKSTA CLKEN CLKDIS
CPCDIS
BURST
TIOB
Register A Register B Register C
Compare RA = Compare RB = Compare RC =
CPCSTOP
Counter
EEVT
EEVTEDG
SYNC
SWTRG
ENETRG
WAVSEL
TC1_IMR
Trig
ACPC
ACPA
AEEVT
ASWTRG
BCPC
BCPB
BEEVT
BSWTRG
TIOA
MTIOA
TIOB
MTIOB
CPAS
COVFS
ETRGS
TC1_SR
CPCS
CPBS
CLK OVF
RESET
Output Controller Output Controller
INT
1
Edge
Detector
Timer/Counter Channel
TIMER_CLOCK1
TIMER_CLOCK2
TIMER_CLOCK3
TIMER_CLOCK4
TIMER_CLOCK5
XC0
XC1
XC2
WAVSEL
Peripheral Clock
Synchronous
Edge Detection
SAM4S Series [DATASHEET]
Atmel-11100K-ATARM-SAM4S-Datasheet_09-Jun-15
862
37.6.11.1 WAVSEL = 00
When WAVSEL = 00, the value of TC_CV is incremented from 0 to 216-1. Once 216-1 has been reached, the valu e
of TC_CV is reset. Incrementation of TC_CV starts again and the cycle continues. See Figure 37-7.
An external event trigger or a software trigger can reset the value of TC_CV. It is important to note that the trigger
may occur at any time. See Figure 37-8.
RC Compare cannot be programmed to generate a trigger in this configuration. At the same time, RC Compare
can stop the counter clock (CPCSTOP = 1 in TC_CMR) and/or disable the counter clock (CPCDIS = 1 in
TC_CMR).
Figure 37-7. WAVSEL = 00 without Trigger
Figure 37-8. WAVSEL = 00 with Trigger
Time
Counter Value
RC
RB
RA
TIOB
TIOA
Counter cleared by compare match with 0xFFFF
0xFFFF
Waveform Examples
Time
Counter Value
R
C
R
B
R
A
TIOB
TIOA
Counter cleared by compare match with 0xFFFF
0xFFFF
Waveform Examples
Counter cleared by trigger
863
SAM4S Series [DATASHEET]
Atmel-11100K-ATARM-SAM4S-Datasheet_09-Jun-15
37.6.11.2 WAVSEL = 10
When WAVSEL = 10, the value of TC_CV is incremented from 0 to the value of RC, then automatically reset on a
RC Compare. Once the value of TC_CV has been reset, it is then incremented and so on. See Figure 37-9.
It is important to note that TC_CV can be reset at any time by an external event or a software trigger if both are
programmed correctly. See Figure 37-10.
In addition, RC Compare can stop the counter clock (CPCSTOP = 1 in TC_CMR) and/or disabl e the counter clock
(CPCDIS = 1 in TC_CMR).
Figure 37-9. WAVSEL = 10 without Trigger
Figure 37-10. WAVSEL = 10 with Trigger
Time
Counter Value
RC
RB
RA
TIOB
TIOA
Counter cleared by compare match with RC
Waveform Examples
2n-1
(n = counter size)
Time
Counter Value
R
C
R
B
R
A
TIOB
TIOA
Counter cleared by compare match with RC
Waveform Examples
Counter cleared by trigger
2n-1
(n = counter size)
SAM4S Series [DATASHEET]
Atmel-11100K-ATARM-SAM4S-Datasheet_09-Jun-15
864
37.6.11.3 WAVSEL = 01
When WAVSEL = 01, the value of TC_CV is incremented from 0 to 216-1 . Once 216-1 is reached, the value of
TC_CV is decremented to 0, then re-incremented to 216-1 and so on. See Figure 37-11.
A trigger such as an externa l event or a software trigger can mod ify TC_CV at any time. If a trigger occurs while
TC_CV is incrementing, TC_CV then decrements. If a trigger is received while TC_CV is decrementing, TC_CV
then increments. See Figure 37-12.
RC Compare cannot be programmed to generate a trigger in this configuration.
At the same time, RC Compare can stop the counter clock (CPCSTOP = 1) and/or disable the counter clock
(CPCDIS = 1).
Figure 37-11. WAVSEL = 01 without Trigger
Figure 37-12. WAVSEL = 01 with Trigger
Time
Counter Value
RC
RB
RA
TIOB
TIOA
Counter decremented by compare match with 0xFFFF
0xFFFF
Waveform Examples
Time
Counter Value
TIOB
TIOA
Counter decremented by compare match with 0xFFFF
0xFFFF
Waveform Examples
Counter decremented
by trigger
Counter incremented
by trigger
RC
RB
RA
865
SAM4S Series [DATASHEET]
Atmel-11100K-ATARM-SAM4S-Datasheet_09-Jun-15
37.6.11.4 WAVSEL = 11
When WAVSEL = 11, the value of TC_CV is incremented from 0 to RC. Once RC is reached, the value of TC_CV
is decremented to 0, then re-incremented to RC and so on. See F igure 37-13.
A trigger such as an externa l event or a software trigger can mod ify TC_CV at any time. If a trigger occurs while
TC_CV is incrementing, TC_CV then decrements. If a trigger is received while TC_CV is decrementing, TC_CV
then increments. See Figure 37-14.
RC Compare can stop the counter clock (CPCSTOP = 1) and/or disable the counter clock (CPCDIS = 1).
Figure 37-13. WAVSEL = 11 without Trigger
Figure 37-14. WAVSEL = 11 with Trigger
Time
Counter Value
RC
RB
RA
TIOB
TIOA
Counter decremented by compare match with RC
Waveform Examples
2n-1
(n = counter size)
Time
Counter Value
TIOB
TIOA
Counter decremented by compare match with RC
Waveform Examples
Counter decremented
by trigger
Counter incremented
by trigger
RC
RB
RA
2n-1
(n = counter size)
SAM4S Series [DATASHEET]
Atmel-11100K-ATARM-SAM4S-Datasheet_09-Jun-15
866
37.6.12 External Event/Trigger Conditions
An external event can be programmed to be detected on one of the clock sources (XC0, XC1, XC2) or TIOB. The
external event selected can then be used as a trigger.
The EEVT parameter in TC_CMR selects the external trigger. The EEVTEDG parameter defines the trigger edge
for each of the possible external triggers (r ising, falling or both) . If EEVTEDG is cleared (none), no external event
is defined.
If TIOB is defined as an external event signal (EEVT = 0), TIOB is no longer used as an output and the compare
register B is not used to generate waveforms and subsequently no IRQs. In this case the TC channel can only
generate a waveform on TIOA.
When an external event is defined, it can be used as a trigger by setting bit ENETRG in the TC_CMR.
As in Capture mode, the SYNC signal and the software trigger are also available as triggers. RC Compare can
also be used as a trigger depending on the parameter WAVSEL.
867
SAM4S Series [DATASHEET]
Atmel-11100K-ATARM-SAM4S-Datasheet_09-Jun-15
37.6.13 Output Controller
The output controller defines the output level changes on TIOA and TIOB following an event. TIOB control is used
only if TIOB is defined as output (not as an external event).
The following events control TIOA and TIOB: software trigger, external event and RC compare. RA compare
controls TIOA and RB co mpare contro ls TIOB. Each of th ese events can be programmed to set, clear or toggle th e
output as defined in the corresponding parameter in TC_CMR.
37.6.14 Quadrature Decoder
37.6.14.1 Description
The quadrature decoder (QDEC) is driven by TIOA0, TIOB0, TIOB1 input pins and drives the timer/counter of
channel 0 and 1. Ch annel 2 can be used as a time base in ca se of speed measurement req uirements (refer to
Figure 37-15).
When writing a 0 to bit QDEN of the TC_BMR, the QDEC is bypassed and the IO pins are directly routed to the
timer counte r fun ct i on . See
TIOA0 and TIOB0 are to be driven by the two dedicated quadrature signals from a rotary sensor mounted on the
shaft of the off-chip motor.
A third signal fr om the rotar y sensor can be processed th rough pin TIOB1 and is typically dedicated to be driven by
an index signal if it is provided by the sensor. This signal is not required to decode the quadrature signals PHA,
PHB.
Field TCCLKS of TC_CMRx must be configured to select XC0 input (i.e., 0x101). Field TC0XC0S has no effect as
soon as the QDEC is enabled.
Either speed or position/revolution can be measured. Position channel 0 accumulates the edges of PHA, PHB
input signa ls giving a high acc uracy on motor posit ion whereas channel 1 accumulates the index pulses of the
sensor, therefore the number of rotations. Concatenation of both values provides a high level of precision on
motion system position.
In Speed mode, position cannot be measured but revolution can be measured.
Inputs from the rotary sensor can be filtered prior to down-stream processing. Accommodation of input polarity,
phase definition and other factors are configurable.
Interruptions can be generated on different events.
A compare function (using TC _RC) is available on channel 0 (speed/position) or channel 1 (rotation) and can
generate an interrupt by means of the CPCS flag in the TC_SRx.
SAM4S Series [DATASHEET]
Atmel-11100K-ATARM-SAM4S-Datasheet_09-Jun-15
868
Figure 37-15. Predefined Connection of the Quadrature Decoder with Timer Counters
37.6.14.2 Input Pre-processing
Input pre-processing consists of capabilities to take into account rotary sensor factors such as polarities and phase
definition followed by configurable digital filtering.
Each input can be negated and swapping PHA, PHB is also configurable.
The MAXFILT field in the TC_BMR is used to configure a minimum duration for which the pulse is stated as valid.
When the filter is active, pulses with a duration lower than MAXFILT +1 ×tperipheral clock ns are not passed to down-
stream logic.
Timer/Counter
Channel 0
1
XC0
TIOA
TIOB
Timer/Counter
Channel 1
1
XC0
TIOB
QDEN
Timer/Counter
Channel 2
1
TIOB0
XC0
1
1
SPEEDEN
1
XC0
Quadrature
Decoder
(Filter + Edge
Detect + QD)
PHA
PHB
IDX
TIOA0
TIOB0
TIOB1
TIOB1
TIOA0
Index
Speed/Position
Rotation
Speed Time Base
Reset pulse
Direction
PHEdges QDEN
869
SAM4S Series [DATASHEET]
Atmel-11100K-ATARM-SAM4S-Datasheet_09-Jun-15
Figure 37-16. Input Stage
Input filtering can efficiently remove spurious pulses that might be generated by the presence of particulate
contamination on the optical or magnetic disk of the rotary sensor.
Spurious pulses can also occur in environments with high levels of electro-magnetic interference. Or, simply if
vibration occurs even when rotation is fully stopped and the shaft of the motor is in such a position that the
beginning of one of the reflective or ma gnetic bars on the rotary sensor disk is aligned with the light or magnetic
(Hall) receiver cell of the rotary sensor. Any vibration can make the PHA, PHB signals toggle for a short duration.
1
1
1
MAXFILT
PHA
PHB
IDX
TIOA0
TIOB0
TIOB1
INVA
1
INVB
1
INVIDX
SWAP
1
IDXPHB
Filter
Filter
Filter
1
Direction
and
Edge
Detection
IDX
PHedge
DIR
Input Pre-Processing
MAXFILT > 0
SAM4S Series [DATASHEET]
Atmel-11100K-ATARM-SAM4S-Datasheet_09-Jun-15
870
Figure 37-17. Filtering Examples
PHA,B
Filter Out
Peripheral Clock MAXFILT = 2
particulate contamination
PHA
PHB
motor shaft stopped in such a position that
rotary sensor cell is aligned with an edge of the disk
rotation
PHA
PHB
PHB Edge area due to system vibration
Resulting PHA, PHB electrical waveforms
PHA
Optical/Magnetic disk strips
stop
PHB
mechanical shock on system
vibration
stop
PHA, PHB electrical waveforms after filtering
PHA
PHB
871
SAM4S Series [DATASHEET]
Atmel-11100K-ATARM-SAM4S-Datasheet_09-Jun-15
37.6.14.3 Direction Status and Change Detection
After filtering, the quadratur e signal s are analyzed to extract the r otatio n di rectio n a nd ed ge s of the two qua dr atur e
signals detected in order to be counted by timer/counter logic downstream.
The direction status can be directly read at anytime in the TC_QISR. The polarity of the direction flag status
depends on the configuration written in TC_BMR. INVA, INVB, INVIDX, SWAP modify the polarity of DIR flag.
Any change in rotation direction is reported in the TC_QISR and can generate an interrupt.
The direction change co ndition is r epor ted as soon as two con secutive edg es on a phase sig nal have sam pled th e
same value on th e other phase sign al a nd the r e is an edge on the other signal. The two consecutive edges of one
phase signal sampling the same value on other phase signal is not sufficient to declare a direction change, for the
reason that particulate contamination may mask one or more reflective bars o n the op tical or magnetic disk of the
sensor. Refer to Figure 37-18 for waveforms.
Figure 37-18. Rotation Change Detec tion
The direction change detection is disabled when QDTRANS is set in the TC_BMR. In this case, the DIR flag report
must not be used.
A quadrature error is also reported by the Q DEC via the QERR flag in the TC_QISR. This error is reported if the
time difference between two edges on PHA, PHB is lower than a predefined value. This predefined value is
PHA
PHB
Direction Change under normal conditions
DIR
DIRCHG
change condition
Report Time
No direction change due to particulate contamination masking a reflective bar
PHA
PHB
DIR
DIRCHG
spurious change condition (if detected in a simple way)
same phase
missing pulse
SAM4S Series [DATASHEET]
Atmel-11100K-ATARM-SAM4S-Datasheet_09-Jun-15
872
configurable and corresp onds to (MAXFILT + 1) × tperipheral clock ns. After being filtered there is no reason to have
two edges closer than (MAXFILT + 1) × tperipheral clock ns under normal mode of operation.
Figure 37-19. Quadrature Error Detection
MAXFILT must be tuned according to several factors such as the peripheral clock frequency, type of rotary sensor
and rotation speed to be achieved.
37.6.14.4 Position and Rotation Measurement
When the POSEN bit is set in the TC_BMR, the motor axis position is processe d on channel 0 (by means of the
PHA, PHB edge detections) and the number of motor revolutions are recorded on channel 1 if the IDX signal is
provided on the TIOB1 input. The position measu rement can be read in the TC_CV0 re gister and the rotation
measurem e nt can be rea d in the TC _CV1 register.
Channel 0 and 1 must be configured in Capture mode (TC_CMR0.WAVE = 0). ‘Rising edge’ must be selected as
the External Trigger Edge ( TC_CMR.ETRGEDG = 0x01) and ‘TIOA’ must be selected as the External T rigger
(TC_CMR.ABETRG = 0x1).
In parallel, the number of edges are accumulated on timer/counter channel 0 and can be read on the TC_CV0
register.
Therefore, the accurate position can be read on both TC_CV registers and concatenated to form a 32-bit word.
The timer/counter channel 0 is cleared for each increment of IDX count value.
Peripheral Clock MAXFILT = 2
PHA
PHB
A
bnormally formatted optical disk strips (theoretical view)
PHA
PHB
strip edge inaccurary due to disk etching/printing process
resulting PHA, PHB electrical waveforms
PHA
PHB
Even with an abnorrmaly formatted disk, there is no occurence of PHA, PHB switching at the same time.
QERR
duration < MAXFILT
873
SAM4S Series [DATASHEET]
Atmel-11100K-ATARM-SAM4S-Datasheet_09-Jun-15
Depending on the q uadrature signals, the directio n is decoded and allows to count up or down in timer/counter
channels 0 and 1. The direction status is reported on TC_QISR.
37.6.14.5 Speed Measurement
When SPEEDEN is set in the TC_BMR, the speed measure is enabled on channel 0.
A time base must be defined on channel 2 by writing the TC_RC2 period register. Channel 2 must be configured in
Waveform mode (WAVE bit set) in TC_CMR2. The WAVSEL field must be defined with 0x10 to clear the counter
by comparison and matching with TC_RC value. Field ACPC must be defined at 0x11 to toggle TIOA outp u t.
This time base is automatically fed back to TIOA of channel 0 when QDEN and SPEEDEN are set.
Channel 0 must be configured in Capture mode (WAVE = 0 in TC_CMR0). The ABETRG bit of TC_CMR0 must be
configured at 1 to select TIOA as a trigger for this channel.
EDGTRG must be set to 0x01, to clear the counter on a rising ed ge of the TIOA signal and fie ld LDRA must be set
accordingly to 0x01, to load TC_RA0 at the same time as the counter is cleared (LDRB must be set to 0x01). As a
consequence, at the end of each time base period the differentiation required for the speed calculation is
performed.
The process must be started by configuring bits CLKEN and SWTRG in the TC_CCR.
The speed can be read on field RA in TC_RA0.
Channel 1 can still be used to count the number of revolutions of the motor.
37.6.15 2-bit Gray Up/Down Counter for Stepper Motor
Each channel can be independently configured to generate a 2-bit gray count waveform on corresponding TIOA,
TIOB outputs by means of the GCEN bit in TC_SMMRx.
Up or Down count can be defined by writing bit DOWN in TC_SMMRx.
It is mandatory to configure the channel in Waveform mode in the TC_CMR.
The period of the counters can be programmed in TC_RCx.
Figure 37-20. 2-bit Gray Up/Down Counter
37.6.16 Fault Mode
At any time, the TC_RCx registers can be used to perform a comparison o n the respective cu rrent ch annel counte r
value (TC_CVx) with the value of TC_RCx register.
The CPCSx flags can be set accordingly and an interrupt can be generated.
This interrupt is processed but requires an unpredictable amount of time to be achieve the required action.
It is possible to trigger the FAULT output of the TIMER1 with CPCS from TC_SR0 and/or CPCS from TC_SR1.
Each source can be independently enabled/disabled in the TC_FMR.
TIOAx
TIOBx
DOWNx
TC_RCx
WAVEx = GCENx =1
SAM4S Series [DATASHEET]
Atmel-11100K-ATARM-SAM4S-Datasheet_09-Jun-15
874
This can be useful to detect an overflow on speed and/or position when QDEC is processed and to act
immediately by using the FAULT output.
Figure 37-21. Fault Output Generation
37.6.17 Register Write Protection
To prevent any single software error from corrupting TC behavior, certain registers in the address space can be
write-protected by setting the WPEN bit in the TC Write Protection Mode Register (TC_WPMR).
The Timer Counter clock of the first channel must be enabled to access TC_WPMR.
TC_SR0 flag CPCS
TC_FMR / ENCF0
FAULT (to PWM input)
OR
AND
AND
TC_SR1 flag CPCS
TC_FMR / ENCF1
The following registers can be write-protected:
TC Block Mode Register
TC Channel Mode Register: Capture Mode
TC Channel Mode Register: Waveform Mode
TC Fault Mode Register
TC Stepper Motor Mode Register
TC Register A
TC Register B
TC Register C
875
SAM4S Series [DATASHEET]
Atmel-11100K-ATARM-SAM4S-Datasheet_09-Jun-15
37.7 Timer Counter (TC) User Interface
Notes: 1. Channel index ranges from 0 to 2.
2. Read-only if TC_CMRx.W AVE = 0
Table 37-6 . Register Mapping
Offset(1) Register Name Access Reset
0x00 + channel * 0x40 + 0x00 Channel Control Register TC_CCR Write-only –
0x00 + channel * 0x40 + 0x04 Channel Mode Register TC_CMR Read/Write 0
0x00 + channel * 0x40 + 0x08 Stepper Motor Mode Regi ster T C_SMMR Read/Write 0
0x00 + channel * 0x40 + 0x0C Reserved – – –
0x00 + channel * 0x40 + 0x10 Counter Value TC_CV Read-only 0
0x00 + channel * 0x40 + 0x14 Register A TC_RA Read /Write(2) 0
0x00 + channel * 0x40 + 0x18 Register B TC_RB Read /Write(2) 0
0x00 + channel * 0x40 + 0x1C Registe r C TC_RC Read/Write 0
0x00 + channel * 0x40 + 0x20 Status Register TC_SR Read-only 0
0x00 + channel * 0x40 + 0x24 Interrupt Enable Register TC_IER Write-only –
0x00 + channel * 0x40 + 0x28 Interrupt Disable Register TC_IDR Write-only –
0x00 + channel * 0x40 + 0x2C Interrupt Mask Register T C_IMR Read-only 0
0xC0 Block Control Register T C_BCR Write-only –
0xC4 Block Mode Register TC_BMR Read/Write 0
0xC8 QDEC Interrupt Enable Register TC_QIER Write-only –
0xCC QDEC Interrupt Disable Register T C_QIDR Write-only –
0xD0 QDEC Interrupt Mask Register T C_QIMR Read-only 0
0xD4 QDEC Interrupt Status Register TC_QISR Read-only 0
0xD8 Fault Mode Register TC_FMR Read/Write 0
0xE4 Write Protection Mode Register T C_WPMR Read/Write 0
0xE8–0xFC Reserved – – –
SAM4S Series [DATASHEET]
Atmel-11100K-ATARM-SAM4S-Datasheet_09-Jun-15
876
37.7.1 TC Channel Control Register
Name: TC_CCRx [x=0..2]
Address: 0x40010000 (0)[0], 0x40010040 (0)[1], 0x40010080 (0)[2], 0x40014000 (1)[0], 0x40014040 (1)[1],
0x40014080 (1)[2]
Access: Write-only
• CLKEN: Counter Clock Enable Command
0: No effect.
1: Enables the clock if CLKDIS is not 1.
• CLKDIS: Counter Clock Disable Command
0: No effect.
1: Disables the clock.
• SWTRG: Software Trigger Command
0: No effect.
1: A software trigger is performed: the counter is reset and the clock is started.
31 30 29 28 27 26 25 24
––––––––
23 22 21 20 19 18 17 16
––––––––
15 14 13 12 11 10 9 8
––––––––
76543210
–––––SWTRGCLKDISCLKEN
877
SAM4S Series [DATASHEET]
Atmel-11100K-ATARM-SAM4S-Datasheet_09-Jun-15
37.7.2 TC Channel Mode Register: Capture Mode
Name: TC_CMRx [x=0..2] (CAPTURE_MODE)
Address: 0x40010004 (0)[0], 0x40010044 (0)[1], 0x40010084 (0)[2], 0x40014004 (1)[0], 0x40014044 (1)[1],
0x40014084 (1)[2]
Access: Read/Write
This register can only be written if the WPEN bit is cleared in the TC Write Protection Mode Register.
• TCCLKS: Clock Selection
• CLKI: Clock Invert
0: Counter is incremented on rising edge of the clock.
1: Counter is incremented on falling edge of the clock.
• BURST: Burst Signal Selection
• LDBSTOP: Counter Clock Stopped with RB Loading
0: Counter clock is not stopped when RB loading occurs.
1: Counter clock is stopped when RB loading occurs.
31 30 29 28 27 26 25 24
––––––––
23 22 21 20 19 18 17 16
–––– LDRB LDRA
15 14 13 12 11 10 9 8
WAVE CPCTRG – – – ABETRG ETRGEDG
76543210
LDBDIS LDBSTOP BURST CLKI TCCLKS
Value Name Description
0 TIMER_CLOCK1 Clock selected: internal MCK/2 clock signal (from PMC)
1 TIMER_CLOCK2 Clock selected: internal MCK/8 clock signal (from PMC)
2 TIMER_CLOCK3 Clock selected: internal MCK/32 clock signal (from PMC)
3 TIMER_CLOCK4 Clock selected: internal MCK/128 clock signal (from PMC)
4 TIMER_CLOCK5 Clock selected: internal SLCK clock signal (from PMC)
5 XC0 Clock selected: XC0
6 XC1 Clock selected: XC1
7 XC2 Clock selected: XC2
Value Name Description
0 NONE The clock is not gated by an external signal.
1 XC0 XC0 is ANDed with the selected clock.
2 XC1 XC1 is ANDed with the selected clock.
3 XC2 XC2 is ANDed with the selected clock.
SAM4S Series [DATASHEET]
Atmel-11100K-ATARM-SAM4S-Datasheet_09-Jun-15
878
• LDBDIS: Counter Clock Disable with RB Loading
0: Counter clock is not disabled when RB loading occurs.
1: Counter clock is disabled when RB loading occurs.
• ETRGEDG: External Trigger Edge Selection
• ABETRG: TIOA or TIOB External Trigger Selection
0: TIOB is used as an external trigger.
1: TIOA is used as an external trigger.
• CPCTRG: RC Compare Trigger Enable
0: RC Compare has no effect on the counter and its clock.
1: RC Compare resets the counter and starts the counter clock.
• WAVE: Waveform Mode
0: Capture mode is enabled.
1: Capture mode is disabled (Waveform mode is enabled).
• LDRA: RA Loading Edge Selection
• LDRB: RB Loading Edge Selection
Value Name Description
0 NONE The clock is not gated by an external signa l.
1 RISING Rising edge
2 FALLING Falli n g edge
3 EDGE Each edge
Value Name Description
0 NONE None
1 RISING Rising edge of TIOA
2 FALLING Falling edge of TIOA
3 EDGE Each edge of TIOA
Value Name Description
0 NONE None
1 RISING Rising edge of TIOA
2 FALLING Falling edge of TIOA
3 EDGE Each edge of TIOA
879
SAM4S Series [DATASHEET]
Atmel-11100K-ATARM-SAM4S-Datasheet_09-Jun-15
37.7.3 TC Channel Mode Register: Waveform Mode
Name: TC_CMRx [x=0..2] (WAVEFORM_MODE)
Address: 0x40010004 (0)[0], 0x40010044 (0)[1], 0x40010084 (0)[2], 0x40014004 (1)[0], 0x40014044 (1)[1],
0x40014084 (1)[2]
Access: Read/Write
This register can only be written if the WPEN bit is cleared in the TC Write Protection Mode Register.
• TCCLKS: Clock Selection
• CLKI: Clock Invert
0: Counter is incremented on rising edge of the clock.
1: Counter is incremented on falling edge of the clock.
• BURST: Burst Signal Selection
• CPCSTOP: Counter Clock Stopped with RC Compare
0: Counter clock is not stopped when counter reaches RC.
1: Counter clock is stopped when counter reaches RC.
31 30 29 28 27 26 25 24
BSWTRG BEEVT BCPC BCPB
23 22 21 20 19 18 17 16
ASWTRG AEEVT ACPC ACPA
15 14 13 12 11 10 9 8
WAVE WAVSEL ENETRG EEVT EEVTEDG
76543210
CPCDIS CPCSTOP BURST CLKI TCCLKS
Value Name Description
0 TIMER_CLOCK1 Clock selected: intern al MCK/2 clock signal (from PMC)
1 TIMER_CLOCK2 Clock selected: internal MCK/8 clock signal (from PMC)
2 TIMER_CLOCK3 Clock selected: internal MCK/32 clock signal (from PMC)
3 TIMER_CLOCK4 Clock selected: internal MCK/128 clock signa l (from PMC)
4 TIMER_CLOCK5 Clock selected: internal SLCK clock signal (from PMC)
5 XC0 Clock selected: XC0
6 XC1 Clock selected: XC1
7 XC2 Clock selected: XC2
Value Name Description
0 NONE T he clock is not gated by an external signal.
1 XC0 XC0 is ANDed with the selected clock.
2 XC1 XC1 is ANDed with the selected clock.
3 XC2 XC2 is ANDed with the selected clock.
SAM4S Series [DATASHEET]
Atmel-11100K-ATARM-SAM4S-Datasheet_09-Jun-15
880
• CPCDIS: Counter Clock Disable with RC Compare
0: Counter clock is not disabled when counter reaches RC.
1: Counter clock is disabled when counter reaches RC.
• EEVTEDG: External Event Edge Selection
• EEVT: External Event Selection
Signal selected as external event.
Note: 1. If TIOB is chosen as the external event signal, it is configured as an input and no longer generates waveforms and
subsequently no IRQs.
• ENETRG: External Event Tr igger Enable
0: The external event has no effect on the counter and its clock.
1: The external event resets the counter and starts the counter clock.
Note: Whatever the value programmed in ENETRG, the selected external event only controls the TIOA output and TIOB if not used as
input (trigger event input or other input used).
• WAVSEL: Waveform Selection
• WAVE: Waveform Mode
0: Waveform mode is disabled (Capture mode is enabled).
1: Waveform mode is enabled.
• ACPA: RA Compare Effect on TIOA
Value Name Description
0 NONE None
1 RISING Rising edge
2 FALLING Falling edge
3 EDGE Each edge
Value Name Description TIOB Direction
0 TIOB TIOB(1) Input
1 XC0 XC0 Output
2 XC1 XC1 Output
3 XC2 XC2 Output
Value Name Description
0 UP UP mode without automatic trigger on RC Compare
1 UPDOWN UPDOWN mode without automatic trigger on RC Compare
2 UP_RC UP mode with automatic trigger on RC Compare
3 UPDOWN_RC UPDOWN mode with automatic trigger on RC Compare
Value Name Description
0 NONE None
881
SAM4S Series [DATASHEET]
Atmel-11100K-ATARM-SAM4S-Datasheet_09-Jun-15
• ACPC: RC Compare Effect on TIOA
• AEEVT: External Event Effect on TIOA
• ASWTRG: Software Trigger Effect on TIOA
• BCPB: RB Compare Effect on TIOB
• BCPC: RC Compare Effect on TIOB
1 SET Set
2 CLEAR Clear
3 TOGGLE Toggle
Value Name Description
0 NONE None
1 SET Set
2 CLEAR Clear
3 TOGGLE Toggle
Value Name Description
0 NONE None
1 SET Set
2 CLEAR Clear
3 TOGGLE Toggle
Value Name Description
0 NONE None
1 SET Set
2 CLEAR Clear
3 TOGGLE Toggle
Value Name Description
0 NONE None
1 SET Set
2 CLEAR Clear
3 TOGGLE Toggle
Value Name Description
0 NONE None
1 SET Set
2 CLEAR Clear
3 TOGGLE Toggle
SAM4S Series [DATASHEET]
Atmel-11100K-ATARM-SAM4S-Datasheet_09-Jun-15
882
• BEEVT: External Event Effect on TIOB
• BSWTRG: Software Trigger Effect on TIOB
Value Name Description
0 NONE None
1 SET Set
2 CLEAR Clear
3 TOGGLE Toggle
Value Name Description
0 NONE None
1 SET Set
2 CLEAR Clear
3 TOGGLE Toggle
883
SAM4S Series [DATASHEET]
Atmel-11100K-ATARM-SAM4S-Datasheet_09-Jun-15
37.7.4 TC Stepper Motor Mode Register
Name: TC_SMMRx [x=0..2]
Address: 0x40010008 (0)[0], 0x40010048 (0)[1], 0x40010088 (0)[2], 0x40014008 (1)[0], 0x40014048 (1)[1],
0x40014088 (1)[2]
Access: Read/Write
This register can only be written if the WPEN bit is cleared in the TC Write Protection Mode Register.
• GCEN: Gray Count Enable
0: TIOAx [x=0..2] and TIOBx [x=0..2] are driven by internal counter of channel x.
1: TIOAx [x=0..2] and TIOBx [x=0..2] are driven by a 2-bit gray counter.
• DOWN: Down Count
0: Up counter.
1: Down counter.
31 30 29 28 27 26 25 24
––––––––
23 22 21 20 19 18 17 16
––––––––
15 14 13 12 11 10 9 8
––––––––
76543210
––––––DOWNGCEN
SAM4S Series [DATASHEET]
Atmel-11100K-ATARM-SAM4S-Datasheet_09-Jun-15
884
37.7.5 TC Counter Value Register
Name: TC_CVx [x=0..2]
Address: 0x40010010 (0)[0], 0x40010050 (0)[1], 0x40010090 (0)[2], 0x40014010 (1)[0], 0x40014050 (1)[1],
0x40014090 (1)[2]
Access: Read-only
• CV: Counter Value
CV contains the cou n ter valu e in re al tim e.
IMPORTANT: For 16-bit channels, CV field size is limited to register bits 15:0.
31 30 29 28 27 26 25 24
CV
23 22 21 20 19 18 17 16
CV
15 14 13 12 11 10 9 8
CV
76543210
CV
885
SAM4S Series [DATASHEET]
Atmel-11100K-ATARM-SAM4S-Datasheet_09-Jun-15
37.7.6 TC Register A
Name: TC_RAx [x=0..2]
Address: 0x40010014 (0)[0], 0x40010054 (0)[1], 0x40010094 (0)[2], 0x40014014 (1)[0], 0x40014054 (1)[1],
0x40014094 (1)[2]
Access: Read-only if TC_CMRx.WAVE = 0, Read/Write if TC_CMRx.WAVE = 1
This register can only be written if the WPEN bit is cleared in the TC Write Protection Mode Register.
• RA: Regist er A
RA contains the Register A value in real time.
IMPORTANT: For 16-bit channels, RA field size is limited to register bits 15:0.
31 30 29 28 27 26 25 24
RA
23 22 21 20 19 18 17 16
RA
15 14 13 12 11 10 9 8
RA
76543210
RA
SAM4S Series [DATASHEET]
Atmel-11100K-ATARM-SAM4S-Datasheet_09-Jun-15
886
37.7.7 TC Register B
Name: TC_RBx [x=0..2]
Address: 0x40010018 (0)[0], 0x40010058 (0)[1], 0x40010098 (0)[2], 0x40014018 (1)[0], 0x40014058 (1)[1],
0x40014098 (1)[2]
Access: Read-only if TC_CMRx.WAVE = 0, Read/Write if TC_CMRx.WAVE = 1
This register can only be written if the WPEN bit is cleared in the TC Write Protection Mode Register.
• RB: Regist er B
RB contains the Register B value in real time.
IMPORTANT: For 16-bit channels, RB field size is limited to register bits 15:0.
31 30 29 28 27 26 25 24
RB
23 22 21 20 19 18 17 16
RB
15 14 13 12 11 10 9 8
RB
76543210
RB
887
SAM4S Series [DATASHEET]
Atmel-11100K-ATARM-SAM4S-Datasheet_09-Jun-15
37.7.8 TC Register C
Name: TC_RCx [x=0..2]
Address: 0x4001001C (0)[0], 0x4001005C (0)[1], 0x4001009C (0)[ 2], 0x4001401C (1)[0], 0x4001405C (1)[1],
0x4001409C (1)[2]
Access: Read/Write
This register can only be written if the WPEN bit is cleared in the TC Write Protection Mode Register.
• RC: Regist er C
RC contains the Register C value in real time.
IMPORTANT: For 16-bit channels, RC field size is limited to register bits 15:0.
31 30 29 28 27 26 25 24
RC
23 22 21 20 19 18 17 16
RC
15 14 13 12 11 10 9 8
RC
76543210
RC
SAM4S Series [DATASHEET]
Atmel-11100K-ATARM-SAM4S-Datasheet_09-Jun-15
888
37.7.9 TC Status Register
Name: TC_SRx [x=0..2]
Address: 0x40010020 (0)[0], 0x40010060 (0)[1], 0x400100A0 (0)[2], 0x40014020 (1)[0], 0x40014060 (1)[1],
0x400140A0 (1)[2]
Access: Read-only
• COVFS: Counter Overflow Status (cleared on read)
0: No counter overflow has occurred since the last read of the Status Register.
1: A counter overflow has occurred since the last read of the Status Register.
• LOVRS: Load Overrun Status (cle ared on read)
0: Load overrun has not occurred since the last read of the Status Register or TC_CMRx.WAVE = 1.
1: RA or RB have been loaded at least twice without any read of the corresponding register since the last read of the Sta-
tus Register, if TC_CMRx.WAVE = 0.
• CPAS: RA Compare Status (cleared on read)
0: RA Compare has not occurred since the last read of the Status Register or TC_CMRx.WAVE = 0.
1: RA Compare has occurred since the last read of the Status Register, if TC_CMRx.WAVE = 1.
• CPBS: RB Compare St atus (cleared on read)
0: RB Compare has not occurred since the last read of the Status Register or TC_CMRx.WAVE = 0.
1: RB Compare has occurred since the last read of the Status Register, if TC_CMRx.WAVE = 1.
• CPCS: RC Compare St atus (cleared on read)
0: RC Compare has not occurred since the last read of the Status Register.
1: RC Compare has occurred since the last read of the Status Register.
• LDRAS: RA Loading Status (cleared on read)
0: RA Load has not occurred since the last read of the Status Register or TC_CMRx.WAVE = 1.
1: RA Load has occurred since the last read of the Status Register, if TC_CMRx.WAVE = 0.
• LDRBS: RB Loading Status (cleared on read)
0: RB Load has not occurred since the last read of the Status Register or TC_CMRx.WAVE = 1.
1: RB Load has occurred since the last read of the Status Register, if TC_CMRx.WAVE = 0.
31 30 29 28 27 26 25 24
––––––––
23 22 21 20 19 18 17 16
–––––MTIOBMTIOACLKSTA
15 14 13 12 11 10 9 8
––––––––
76543210
ETRGS LDRBS LDRAS CPCS CPBS CPAS LOVRS COVFS
889
SAM4S Series [DATASHEET]
Atmel-11100K-ATARM-SAM4S-Datasheet_09-Jun-15
• ETRGS: Exte rn al Trig g er Status (cleared on read)
0: External trigger has not occurred since the last read of the Status Register.
1: External trigger has occurred since the last read of the Status Register.
• CLKSTA: Clock Enabling Status
0: Clock is disabled.
1: Clock is enabled.
• MTIOA: TIOA Mirror
0: TIOA is low. If TC_CMRx.WAVE = 0, this means that TIOA pin is low. If TC_CMRx.WAVE = 1, this means that TIOA is
driven low.
1: TIOA is high. If TC_CMRx.WAVE = 0, this means that TIOA pin is high. If TC_CMRx.WAVE = 1, this means that TIOA is
driven high.
• MTIOB: TIOB Mirror
0: TIOB is low. If TC_CMRx.WAVE = 0, this means that TIOB pin is low. If TC_CMRx.WAVE = 1, this means that TIOB is
driven low.
1: TIOB is high. If TC_CMRx.WAVE = 0, this means that TIOB pin is high. If TC_CMRx.WAVE = 1, this means that TIOB is
driven high.
SAM4S Series [DATASHEET]
Atmel-11100K-ATARM-SAM4S-Datasheet_09-Jun-15
890
37.7.10 TC Interrupt Enable Register
Name: TC_IERx [x=0..2]
Address: 0x40010024 (0)[0], 0x40010064 (0)[1], 0x400100A4 (0)[2], 0x40014024 (1)[0], 0x40014064 (1)[1],
0x400140A4 (1)[2]
Access: Write-only
• COVFS: Counter Overflow
0: No effect.
1: Enables the Counter Overflow Interrupt.
• LOVRS: Load Overrun
0: No effect.
1: Enables the Load Overrun Interrupt.
• CPAS: RA Compare
0: No effect.
1: Enables the RA Compare Interrupt.
• CPBS: RB Compare
0: No effect.
1: Enables the RB Compare Interrupt.
• CPCS: RC Compare
0: No effect.
1: Enables the RC Compare Interrupt.
• LDRAS: RA Loading
0: No effect.
1: Enables the RA Load Interrupt.
• LDRBS: RB Loading
0: No effect.
1: Enables the RB Load Interrupt.
31 30 29 28 27 26 25 24
––––––––
23 22 21 20 19 18 17 16
––––––––
15 14 13 12 11 10 9 8
––––––––
76543210
ETRGS LDRBS LDRAS CPCS CPBS CPAS LOVRS COVFS
891
SAM4S Series [DATASHEET]
Atmel-11100K-ATARM-SAM4S-Datasheet_09-Jun-15
• ETRGS: External Trigger
0: No effect.
1: Enables the External Trigger Interrupt.
SAM4S Series [DATASHEET]
Atmel-11100K-ATARM-SAM4S-Datasheet_09-Jun-15
892
37.7.11 TC Interrupt Disable Register
Name: TC_IDRx [x=0..2]
Address: 0x40010028 (0)[0], 0x40010068 (0)[1], 0x400100A8 (0)[2], 0x40014028 (1)[0], 0x40014068 (1)[1],
0x400140A8 (1)[2]
Access: Write-only
• COVFS: Counter Overflow
0: No effect.
1: Disables the Counter Overflow Interrupt.
• LOVRS: Load Overrun
0: No effect.
1: Disables the Load Overrun Interrupt (if TC_CMRx.WAVE = 0).
• CPAS: RA Compare
0: No effect.
1: Disables the RA Compare Interrupt (if TC_CMRx.WAVE = 1).
• CPBS: RB Compare
0: No effect.
1: Disables the RB Compare Interrupt (if TC_CMRx.WAVE = 1).
• CPCS: RC Compare
0: No effect.
1: Disables the RC Compare Interrupt.
• LDRAS: RA Loading
0: No effect.
1: Disables the RA Load Interrupt (if TC_CMRx.WAVE = 0).
• LDRBS: RB Loading
0: No effect.
1: Disables the RB Load Interrupt (if TC_CMRx.WAVE = 0).
31 30 29 28 27 26 25 24
––––––––
23 22 21 20 19 18 17 16
––––––––
15 14 13 12 11 10 9 8
––––––––
76543210
ETRGS LDRBS LDRAS CPCS CPBS CPAS LOVRS COVFS
893
SAM4S Series [DATASHEET]
Atmel-11100K-ATARM-SAM4S-Datasheet_09-Jun-15
• ETRGS: External Trigger
0: No effect.
1: Disables the External Trigger Interrupt.
SAM4S Series [DATASHEET]
Atmel-11100K-ATARM-SAM4S-Datasheet_09-Jun-15
894
37.7.12 TC Interrupt Mask Register
Name: TC_IMRx [x=0..2]
Address: 0x4001002C (0)[0], 0x4001006C (0)[1], 0x400100AC (0)[2], 0x4001402C (1)[0], 0x4001406C (1)[1],
0x400140AC (1)[2]
Access: Read-only
• COVFS: Counter Overflow
0: The Counter Overflow Interrupt is disabled.
1: The Counter Overflow Interrupt is enabled.
• LOVRS: Load Overrun
0: The Load Overrun Interrupt is disabled.
1: The Load Overrun Interrupt is enabled.
• CPAS: RA Compare
0: The RA Compare Interrupt is disabled.
1: The RA Compare Interrupt is enabled.
• CPBS: RB Compare
0: The RB Compare Interrupt is disabled.
1: The RB Compare Interrupt is enabled.
• CPCS: RC Compare
0: The RC Compare Interr upt is disabled.
1: The RC Compare Interr upt is enabled.
• LDRAS: RA Loading
0: The Load RA Interrupt is disabled.
1: The Load RA Interrupt is enabled.
• LDRBS: RB Loading
0: The Load RB Interrupt is disabled.
1: The Load RB Interrupt is enabled.
31 30 29 28 27 26 25 24
––––––––
23 22 21 20 19 18 17 16
––––––––
15 14 13 12 11 10 9 8
––––––––
76543210
ETRGS LDRBS LDRAS CPCS CPBS CPAS LOVRS COVFS
895
SAM4S Series [DATASHEET]
Atmel-11100K-ATARM-SAM4S-Datasheet_09-Jun-15
• ETRGS: External Trigger
0: The External Trigger Interrupt is disabled.
1: The External Trigger Interrupt is enabled.
SAM4S Series [DATASHEET]
Atmel-11100K-ATARM-SAM4S-Datasheet_09-Jun-15
896
37.7.13 TC Block Control Register
Name: TC_BCR
Address: 0x400100C0 (0), 0x400140C0 (1)
Access: Write-only
• SYNC: Synchro Command
0: No effect.
1: Asserts the SYNC signal which generates a software trigger simultaneously for each of the channels.
31 30 29 28 27 26 25 24
––––––––
23 22 21 20 19 18 17 16
––––––––
15 14 13 12 11 10 9 8
––––––––
76543210
–––––––SYNC
897
SAM4S Series [DATASHEET]
Atmel-11100K-ATARM-SAM4S-Datasheet_09-Jun-15
37.7.14 TC Block Mode Register
Name: TC_BMR
Address: 0x400100C4 (0), 0x400140C4 (1)
Access: Read/Write
This register can only be written if the WPEN bit is cleared in the TC Write Protection Mode Register.
• TC0XC0S: External Clock Signal 0 Selection
• TC1XC1S: External Clock Signal 1 Selection
• TC2XC2S: External Clock Signal 2 Selection
• QDEN: Quadrature Decoder Enabled
0: Disabled.
1: Enables the QDEC (filter, edge detection and quadrature decoding).
Quadrature decoding (direction change) can be disabled using QDTRANS bit.
31 30 29 28 27 26 25 24
–––––– MAXFILT
23 22 21 20 19 18 17 16
MAXFILT – – IDXPHB SWAP
15 14 13 12 11 10 9 8
INVIDX INVB INVA EDGPHA QDTRANS SPEEDEN POSEN QDEN
76543210
– – TC2XC2S TC1XC1S TC0XC0S
Value Name Description
0 TCLK0 Signal connected to XC0: TCLK0
1– Reserved
2 TIOA1 Signal connected to XC0: TIOA1
3 TIOA2 Signal connected to XC0: TIOA2
Value Name Description
0 TCLK1 Signal connected to XC1: TCLK1
1– Reserved
2 TIOA0 Signal connected to XC1: TIOA0
3 TIOA2 Signal connected to XC1: TIOA2
Value Name Description
0 TCLK2 Signal connected to XC2: TCLK2
1– Reserved
2 TIOA0 Signal connected to XC2: TIOA0
3 TIOA1 Signal connected to XC2: TIOA1
SAM4S Series [DATASHEET]
Atmel-11100K-ATARM-SAM4S-Datasheet_09-Jun-15
898
One of the POSEN or SPEEDEN bits must be also enabled.
• POSEN: Position Enabled
0: Disable position.
1: Enables the position measure on channel 0 and 1.
• SPEEDEN: Speed Enabled
0: Disabled.
1: Enables the speed measure on channel 0, the time base being provided by channel 2.
• QDTRANS: Quadrature Decoding Transparent
0: Full quadrature decoding logic is active (direction change detected).
1: Quadrature decoding logic is inactive (direction change inactive) but input filtering and edge detection are performed.
• EDGPHA: Edge on PHA Count Mode
0: Edges are detected on PHA only.
1: Edges are detected on both PHA and PHB.
• INVA: Inverted PHA
0: PHA (TIOA0) is directly driving the QDEC.
1: PHA is inverted before driving the QDEC.
• INVB: Inverted PHB
0: PHB (TIOB0) is directly driving the QDEC.
1: PHB is inverted before driving the QDEC.
• INVIDX: Inverted Index
0: IDX (TIOA1) is directly driving the QDEC.
1: IDX is inverted before driving the QDEC.
• SWAP: Swap PHA and PHB
0: No swap between PHA and PHB.
1: Swap PHA and PHB internally, prior to driving the QDEC.
• IDXPHB: Index Pin is PHB Pin
0: IDX pin of the rotary sensor must drive TIOA1.
1: IDX pin of the rotary sensor must drive TIOB0.
• MAXFILT: Maximum Filter
1–63: Defines the filtering capabilities.
Pulses with a period shorter than MAXFILT+1 peripheral clock cycles are discarded.
899
SAM4S Series [DATASHEET]
Atmel-11100K-ATARM-SAM4S-Datasheet_09-Jun-15
37.7.15 TC QDEC Interrupt Enable Register
Name: TC_QIER
Address: 0x400100C8 (0), 0x400140C8 (1)
Access: Write-only
• IDX: Index
0: No effect.
1: Enables the interrupt when a rising edge occurs on IDX input.
• DIRCHG: Direction Change
0: No effect.
1: Enables the interrupt when a change on rotation direction is detected.
• QERR: Quadrature Error
0: No effect.
1: Enables the interrupt when a quadrature error occurs on PHA, PHB.
31 30 29 28 27 26 25 24
––––––––
23 22 21 20 19 18 17 16
––––––––
15 14 13 12 11 10 9 8
––––––––
76543210
–––––QERRDIRCHGIDX
SAM4S Series [DATASHEET]
Atmel-11100K-ATARM-SAM4S-Datasheet_09-Jun-15
900
37.7.16 TC QDEC Interrupt Disable Register
Name: TC_QIDR
Address: 0x400100CC (0), 0x400140CC (1)
Access: Write-only
• IDX: Index
0: No effect.
1: Disables the interrupt when a rising edge occurs on IDX input.
• DIRCHG: Direction Change
0: No effect.
1: Disables the interrupt when a change on rotation direction is detected.
• QERR: Quadrature Error
0: No effect.
1: Disables the interrupt when a quadrature error occurs on PHA, PHB.
31 30 29 28 27 26 25 24
––––––––
23 22 21 20 19 18 17 16
––––––––
15 14 13 12 11 10 9 8
––––––––
76543210
–––––QERRDIRCHGIDX
901
SAM4S Series [DATASHEET]
Atmel-11100K-ATARM-SAM4S-Datasheet_09-Jun-15
37.7.17 TC QDEC Interrupt Mask Register
Name: TC_QIMR
Address: 0x400100D0 (0), 0x400140D0 (1)
Access: Read-only
• IDX: Index
0: The interrupt on IDX input is disabled.
1: The interrupt on IDX input is enabled.
• DIRCHG: Direction Change
0: The interrupt on rotation direction change is di sabled.
1: The interrupt on rotation direction change is enabled.
• QERR: Quadrature Error
0: The interrupt on quadrature error is disabled.
1: The interrupt on quadrature error is enabled.
31 30 29 28 27 26 25 24
––––––––
23 22 21 20 19 18 17 16
––––––––
15 14 13 12 11 10 9 8
––––––––
76543210
–––––QERRDIRCHGIDX
SAM4S Series [DATASHEET]
Atmel-11100K-ATARM-SAM4S-Datasheet_09-Jun-15
902
37.7.18 TC QDEC Interrupt Status Register
Name: TC_QISR
Address: 0x400100D4 (0), 0x400140D4 (1)
Access: Read-only
• IDX: Index
0: No Index input change since the last read of TC_QISR.
1: The IDX input has changed since the last read of TC_QISR.
• DIRCHG: Direction Change
0: No change on rota tio n dir ec tio n sinc e th e last rea d of TC_ QI S R.
1: The rotation direction changed since the last read of TC_QISR.
• QERR: Quadrature Error
0: No quadratur e er ro r sinc e th e last rea d of TC_ QISR.
1: A quadrature error occurred since the last read of TC_QISR.
•DIR: Direction
Returns an image of the actual rotation direction.
31 30 29 28 27 26 25 24
––––––––
23 22 21 20 19 18 17 16
––––––––
15 14 13 12 11 10 9 8
–––––––DIR
76543210
–––––QERRDIRCHGIDX
903
SAM4S Series [DATASHEET]
Atmel-11100K-ATARM-SAM4S-Datasheet_09-Jun-15
37.7.19 TC Fault Mode Register
Name: TC_FMR
Address: 0x400100D8 (0), 0x400140D8 (1)
Access: Read/Write
This register can only be written if the WPEN bit is cleared in the TC Write Protection Mode Register.
• ENCF0: Enable Compare Fault Channel 0
0: Disables the FAULT output source (CPCS flag) from channel 0.
1: Enables the FAULT output source (CPCS flag) from channel 0.
• ENCF1: Enable Compare Fault Channel 1
0: Disables the FAULT output source (CPCS flag) from channel 1.
1: Enables the FAULT output source (CPCS flag) from channel 1.
31 30 29 28 27 26 25 24
––––––––
23 22 21 20 19 18 17 16
––––––––
15 14 13 12 11 10 9 8
––––––––
76543210
––––––ENCF1ENCF0
SAM4S Series [DATASHEET]
Atmel-11100K-ATARM-SAM4S-Datasheet_09-Jun-15
904
37.7.20 TC Write Protection Mode Register
Name: TC_WPMR
Address: 0x400100E4 (0), 0x400140E4 (1)
Access: Read/Write
• WPEN: Write Protec ti on Ena b le
0: Disables the write protection if WPKEY corresponds to 0x54494D (“TIM” in ASCII).
1: Enables the write protection if WPKEY corresponds to 0x54494D (“TIM” in ASCII).
The Timer Counter clock of the first channel must be enabled to access this register.
See Section 37.6.17 “Register Write Protection” for a list of registers that can be write-protected and T ime r Co un te r clock
conditions.
• WPKEY: Write Protection Key
31 30 29 28 27 26 25 24
WPKEY
23 22 21 20 19 18 17 16
WPKEY
15 14 13 12 11 10 9 8
WPKEY
76543210
–––––––WPEN
Value Name Description
0x54494D PASSWD Writing any other value in this field aborts the write operation of the WPEN bit.
Always reads as 0.
905
SAM4S Series [DATASHEET]
Atmel-11100K-ATARM-SAM4S-Datasheet_09-Jun-15
38. High Speed Multimedia Card Interface (HSMCI)
38.1 Description
The High Speed M ultimedia Ca rd Interface (H SMCI) suppo rts the MultiMedia Card (MMC) Specification V4.3, the
SD Memory Card Specification V2.0, the SDIO V2.0 specification and CE-ATA V1.1.
The HSMCI includes a command register, response registers, data registers, timeout counters and error detection
logic that aut oma tica lly ha n dle th e tr an sm iss ion of c omm an d s an d, whe n req u ire d, the re ce pt ion of the as soc i at ed
responses and data with a limited processor overhead.
The HSMCI supports stream, block and multi block data read and write, and is comp atible with the Peripheral DMA
Controller (PDC) Channels, minimizing processor intervention for large buffer transfers.
The HSMCI operates at a rate of up to Master Clock divided by 2 and supports the interfacing of 1 slot(s). Each
slot may be used to interface with a High Speed MultiMedia Card bus (up to 30 Cards) or with an SD Memory
Card. A bit field in the SD Card Register performs this selection.
The SD Memory Card communica tion is based on a 9-pin interface (clock, command, four data and three power
lines) and the High Speed MultiMedia Card on a 7-pin interface (clock, command, one data, three power lines and
one reserved for future use).
The SD Memory Card interface also supports High Speed MultiMedia Card operations. The main differences
between SD and High Speed MultiMedia Cards are the initialization process and the bus topology.
HSMCI fully supports CE-ATA Revision 1.1, built on the MMC System Specification v4.0. The module includes
dedicated hardware to issue the command completion si gnal and capture the host command completion signal
disable.
38.2 Embedded Characteristics
Compatible with Mult iMedia Card Spec ification Version 4.3
Compatible with SD Memory Card Specification Version 2.0
Compatible with SDIO Specification Version 2.0
Compatible with CE-ATA Specification 1.1
Cards Clock Rate Up to Master Clock Divided by 2
Boot Operation Mode Support
High Speed Mode Support
Embedded Power Management to Slow Down Clock Rate When Not Used
Supports 1 Multiplexed Slot(s)
Each Slot for either a High Speed MultiMedia Card Bus (Up to 30 Cards) or an SD Memory Card
Support for Stream, Block and Multi-block Data Read and Write
Supports Connection to Peripheral DM A Controller (PDC)
Minimizes Processor Intervention for Large Buffer Transfers
Built in FIFO (from 16 to 256 bytes) with Large Memory Aperture Supporting Incremental Access
Support for CE-ATA Completion Signal Disable Command
Protection Aga ins t U nexp ected Modifica tio n On-t he -F ly of the Co nf igu ra tio n Re gis ter s
SAM4S Series [DATASHEET]
Atmel-11100K-ATARM-SAM4S-Datasheet_09-Jun-15
906
38.3 Block Diagram
Figure 38-1. Block Diagram (4-bit configuration)
Note: 1. When several HSMCI (x HSMCI) are embedded in a product, MCCK refers to HSMCIx_CK, MCCDA to HSMCIx_CDA,
MCDAy to HSMCIx_DAy.
HSMCI Interface
Interrupt Control
PIO
PDC
APB Bridge
PMC MCK
HSMCI Interrupt
MCCK(1)
MCCDA(1)
MCDA0(1)
MCDA1(1)
MCDA2(1)
MCDA3(1)
APB
907
SAM4S Series [DATASHEET]
Atmel-11100K-ATARM-SAM4S-Datasheet_09-Jun-15
38.4 Application Block Diagram
Figure 38-2. Application Block Diagram
38.5 Pin Name List
Notes: 1. When several HSMCI (x HSMCI) are embedded in a product, MCCK refers to HSMCIx_CK, MCCDA to HSMCIx_CDA,
MCDAy to HSMCIx_DAy.
2. I: Input, O: Ou tput, PP: Push/Pull, OD: Open Drain.
2345617
MMC
23456178
SDCard
9
Physical Layer
HSMCI Interface
Application Layer
ex: File System, Audio, Security, etc.
91011 12138
Table 38-1 . I/O Lines Description for 4-bit Configuration
Pin Name(1) Pin Description Type(2) Comments
MCCDA Command/response I/O/PP/OD CMD of an MMC or SDCard/SDIO
MCCK Clock I/O CLK of an MMC or SD Card/SDIO
MCDA0–MCDA3 Data 0..3 of Slot A I/O/PP DAT[0..3] of an MMC
DAT[0..3] of an SD Card/SDIO
SAM4S Series [DATASHEET]
Atmel-11100K-ATARM-SAM4S-Datasheet_09-Jun-15
908
38.6 Product Dependencies
38.6.1 I/O Lines
The pins used for interfacing the Hig h Speed MultiMedia Cards or SD Cards are multiplexed with PIO lines. The
programmer must first program the PIO controllers to assign the peripheral fu nct ion s to HSM C I pins.
38.6.2 Power Management
The HSMC I is clocked thro ugh the Po wer Managem ent Contro ller (PMC), s o the prog rammer mu st first conf igure
the PMC to enable the HSMCI clock.
38.6.3 Interrupt Sources
The HSMCI has an interrupt line connected to the interru pt controller.
Handling the HSMCI interrupt requires programm ing the interrupt controller before configuring the HSMCI.
38.7 Bus Topology
Figure 38-3. High Speed MultiMedia Memory Card Bus Topology
Table 38-2. I/O Lines
Instance Signal I/O Line Periphera l
HSMCI MCCDA PA28 C
HSMCI MCCK PA29 C
HSMCI MCDA0 PA30 C
HSMCI MCDA1 PA31 C
HSMCI MCDA2 PA26 C
HSMCI MCDA3 PA27 C
Table 38-3. Peripheral IDs
Instance ID
HSMCI 18
2345617
MMC
91011 12138
909
SAM4S Series [DATASHEET]
Atmel-11100K-ATARM-SAM4S-Datasheet_09-Jun-15
The High Speed MultiMedia Card communication is based on a 13-pin serial bus interface. It has three
communication lines and four supply lines.
Notes: 1. I: Input, O: Output, PP: Push/Pull, OD: Open Drain.
2. When several HSMCI (x HSMCI) are embedded in a product, MCCK refers to HSMCIx_CK, MCCDA to
HSMCIx_CDA, MCDAy to HSMCIx_DAy.
Figure 38-4. MMC Bus Connections (One Slot)
Note: When several HSMCI (x HSMCI) are embedded in a product, MCCK refers to HSMCIx_CK, MCCDA to HSMCIx_CDA
MCDAy to HSMCIx_DAy.
Table 38-4. Bus Topology
Pin Number Name Type(1) Description HSMCI Pin Name(2)
(Slot z)
1 DAT[3] I/O/PP Data MCDz3
2 CMD I/O/PP/OD Command/response MCCDz
3 VSS1 S Supply voltage ground VSS
4 VDD S Supply voltage VDD
5 CLK I/O Clock MCCK
6 VSS2 S Supply voltage ground VSS
7 DAT[0] I/O/PP Data 0 MCDz0
8 DAT[1] I/O/PP Data 1 MCDz1
9 DAT[2] I/O/PP Data 2 MCDz2
10 DAT[4] I/O/PP Data 4 MCDz4
11 DAT[5] I/O/PP Data 5 MCDz5
12 DAT[6] I/O/PP Data 6 MCDz6
13 DAT[7] I/O/PP Data 7 MCDz7
MCCDA
MCDA0
MCCK
HSMCI
2345617
MMC1
91011 12138
2345617
MMC2
91011 12138
2345617
MMC3
91011 12138
SAM4S Series [DATASHEET]
Atmel-11100K-ATARM-SAM4S-Datasheet_09-Jun-15
910
Figure 38-5. SD Memory Card Bus Topology
The SD Memory Card bus includes the signals listed in Table 38-5.
Notes: 1. I: input, O: output, PP: Push Pull, OD: Open Drain.
2. When several HSMCI (x HSMCI) are embedded in a product, MCCK refers to HSMCIx_CK, MCCDA to
HSMCIx_CDA, MCDAy to HSMCIx_DAy.
Figure 38-6. SD Card Bus Connections with One Slot
Note: When several HSMCI (x HSMCI) are embedded in a product, MCCK refers to HSMCIx_CK, MCCDA to HSMCIx_CDA
MCDAy to HSMCIx_DAy.
When the HSMCI is configured to operate with SD memory cards, the width of the data bu s can be selected in the
HSMCI_SDCR. Clearing the SDCBUS bit in this register means that the width is one bit; setting it mean s that the
width is four bits. In the case of High Speed Multi Media cards, only the data line 0 is used. The other data lines can
be used as independent PIOs.
Table 38-5. SD Memory Card Bus Signals
Pin Number Name Type(1) Description HSMCI Pin Name(2)
(Slot z)
1 CD/DAT[3] I/O/PP Card detect/ Data line Bit 3 MCDz3
2 CMD PP Command/response MCCDz
3 VSS1 S Supply voltage ground VSS
4 VDD S Supply voltage VDD
5 CLK I/O Clock MCCK
6 VSS2 S Supply voltage ground VSS
7 DAT[0] I/O/PP Data line Bit 0 MCDz0
8 DAT[1] I/O/PP Data line Bit 1 or Interrupt MCDz1
9 DAT[2] I/O/PP Data line Bit 2 MCDz2
23456178
SD CARD
9
2345617
MCDA0 - MCDA3
MCCDA
MCCK
8
SD CARD
9
911
SAM4S Series [DATASHEET]
Atmel-11100K-ATARM-SAM4S-Datasheet_09-Jun-15
38.8 High Speed MultiMedia Card Operations
After a power-on reset, the cards ar e initialized by a special message-based High Speed MultiMedia Card bus
protocol. Each message is represented by one of the following tokens:
Command—A command is a token that starts an operation. A command is sent from the host either to a
single card (addressed command) or to all connected cards (broadcast command). A command is
transferred serially on the CMD line.
Response—A response is a token which is sent from an addressed card or (synchronously) from all
connected cards to the host as an answer to a previously received command. A response is transferred
serially on the CMD line.
Data—Data can be transferred from the card to the host or vice versa. Data is transferred via the dat a line.
Card addressing is implemented using a session address assigned during the initialization phase by the bus
controller to all curr en tly co nn ected cards. Thei r unique CID number identifies individual cards.
The structure of commands, responses and data blocks is described in the High Speed MultiMedia Card System
Specification. See also Table 38-6 on page 912.
High Speed MultiMedia Card bus data transfers are composed of these tokens.
There are different types of operations. Addressed operations always contain a command and a response token.
In addition, some operat ions have a data token; the othe rs transfer their information directly with in the command or
response structure. In this case, no data token is present in an operation. The bits on the DAT and the CMD lines
are transferred synchronous to the clock HSMCI clock.
Two types of data transfer commands are defined:
Sequential commands—These commands initiate a contin uous data stream. They ar e terminated only when
a stop command follows on the CMD line. This mode reduces the command overhead to an absolute
minimum.
Block-oriented commands—These commands send a data block succeeded by CRC bits.
Both read and write operations allow either single or multiple block transmission. A multiple block transmission is
terminated when a stop command follows on the CMD lin e similar ly to the sequen tial read or when a mu ltiple block
transmission has a predefined block count (see Se ctio n 38 .8 .2 “Data Tr a nsf er Ope ra tio n”).
The HSMCI provides a set of registers to perform the entire range of High Speed MultiMedia Card operations.
38.8.1 Command - Response Operation
After reset, the HSMCI is disabled and becomes valid after setting the MCIEN bit in the HSMCI_CR.
The PWSEN bit saves power by dividing the HSMCI clock by 2PWSDIV + 1 when the bus is inactive.
The two bits, RDPROOF and WRPROOF in the HSMCI Mode Register (HSMCI_ MR) allow stopping the HSMCI
clock during read or write access if the internal FIFO is full. This will guarantee data integrity, not bandwidth.
All the timings for High Speed MultiMedia Card are defined in the High Speed MultiMedia Card System
Specification.
The two bus modes (open drain and push/pull) needed to process all the operations are defined in the HSMCI
Command Register (HSMCI_CMDR). The HSMCI_CMDR allows a command to be carried out.
For example, to perform an ALL_SEND_CID command:
Host Command NID Cycles Response High Impedance
State
CMD S T Content CRC E Z ****** Z S T CID
Content ZZZ
SAM4S Series [DATASHEET]
Atmel-11100K-ATARM-SAM4S-Datasheet_09-Jun-15
912
The command ALL_SEND_CID and the fields and values for the HSMCI_CMDR are described in Table 38-6 and
Table 38-7.
Note: 1. bcr means broadcast command with response.
The HSMCI_ARGR contains the argument field of the command.
To send a command, the user must perform the following steps:
Fill the argument register (HSMCI_ARGR) with the command argument.
Set the command register (HSMCI_CMDR) (see Table 38-7).
The command is sent immediately after writing the command register.
While the card maintains a busy indication (at the end of a STOP_TRANSMISSION command CMD12, for
example), a new comm and shall not be sent. The NOTBUSY flag in the Status Register (HSMCI_SR) is asserted
when the card rele ase s th e bu sy ind ica tio n.
If the command requires a response, it can be read in the HSMCI Response Register (HSMCI_RSPR). The
response size can be from 48 bits up to 136 bits depending on the command. The HSMCI embeds an error
detection to prevent any corrupted data during the transfer.
The following flowchart shows how to send a command to the card and read the response if needed. In this
example, th e stat us re gister bits ar e polled but se tting t he appr opr iate b its in the HSMCI I nterru pt Ena ble Regis ter
(HSMCI_IER) allows using an interrupt method.
Table 38-6. ALL_SEND_CID Command Description
CMD Index Type Argument Response Abbreviati on Command Description
CMD2 bcr(1) [31:0] stuff bits R2 ALL_SEND_CID Asks all cards to send
their CID numbers on the
CMD line
Table 38-7. Fields and Values for HSMCI_CMDR
Field Value
CMDNB (command number) 2 (CMD2)
RSPTYP (response type) 2 (R2: 136 bits respon se )
SPCMD (special command) 0 (not a special command)
OPCMD (open drain command) 1
MAXLAT (max latency for command to response) 0 (NID cycles ==> 5 cycles)
TRCMD (transfer command) 0 (No transfer)
TRDIR (transfer direction) X (availabl e only in transfer command)
TRTYP (transfer type) X (available only in transfer command)
IOSPCMD (SDIO special command) 0 (not a special command)
913
SAM4S Series [DATASHEET]
Atmel-11100K-ATARM-SAM4S-Datasheet_09-Jun-15
Figure 38-7. Command/Response Functional Flow Diagram
Note: If the command is SEND_OP_COND, the CRC error flag is always present (refer to R3 response in the High Speed
MultiMedia Card specification).
RETURN OK
RETURN ERROR(1)
RETURN OK
Set the command argument
HSMCI_ARGR = Argument
(1)
Set the command
HSMCI_CMDR = Command
Read HSMCI_SR
CMDRDY
Status error flags?
Read response if required
Yes
Wait for command
ready status flag
Check error bits in the
status register
(1)
0
1
Does the command involve
a busy indication?
No
Read HSMCI_SR
0
NOTBUSY
1
SAM4S Series [DATASHEET]
Atmel-11100K-ATARM-SAM4S-Datasheet_09-Jun-15
914
38.8.2 Data Transfer Operation
The High Speed MultiMedia Card allows several read/write operations (single block, multiple blocks, stream, etc.).
These kinds of transfer can be selected setting the Transfer Type (TRTYP) field in the HSMCI Command Register
(HSMCI_CMDR).
These operations can be done using the features of the Peripheral DMA Controller (PDC). If the PDCMODE bit is
set in HSMCI_MR, then all reads and writes use the PDC facilities.
In all cases, the block leng th (BLKLEN field) must be defined either in the HSMCI Mode Register (HSMCI_MR) or
in the HSMCI Block Register (HSMCI_BLKR). This field determines the size of the data block.
Consequent to MMC Specification 3.1, two types of multip le block rea d (or write) tran sactions are d efined (the host
can use either one at any time):
Open-ended/Infinite Multiple block read (or write):
The number of blocks for the read (or write) multiple block operation is not defined. The card will
continuously transfer (or program) data blocks until a stop transmission command is received.
Multiple block read (or write) with predefined block count (since version 3.1 and higher):
The card will transfer (or program) the requested number of data blocks and terminate the transaction. The
stop command is not requir ed at the end o f this type of multiple block read (or write), unless terminated with
an error. In orde r to start a m ultiple blo ck re ad (o r write) with predefined block count, the host must correctly
program the HSMCI Block Register (HSMCI_BLKR). Otherwise the card will start an open-ended multiple
block read. The BCNT field of the HSMCI_BLKR defines the number of blocks to transfer (from 1 to 65535
blocks). Programming the value 0 in the BCNT field corresponds to an infinite block transfer.
38.8.3 Read Operation
The following flowchart (Figure 38-8) shows how to read a single block with or without use of PDC facilities. In this
example, a polling method is used to wait for the end of read. Similarly, the user can configure the HSMCI Interrupt
Enable Register (HSMCI_IER) to trigger an interrupt at the end of read.
915
SAM4S Series [DATASHEET]
Atmel-11100K-ATARM-SAM4S-Datasheet_09-Jun-15
Figure 38-8. Read Functional Flow Diagram
Note: 1. It is assumed that this command has been correctly sent (see Figure 38-7).
Read status register HSMCI_SR
Send SELECT/DESELECT_CARD
command(1) to select the card
Send SET_BLOCKLEN command(1)
Read with PDC
Reset the PDCMODE bit
HSMCI_MR &= ~PDCMODE
Set the block length (in bytes)
HSMCI_BLKR |= (BlockLength <<16)
Number of words to read = 0 ?
Poll the bit
RXRDY = 0?
Read data = HSMCI_RDR
Number of words to read =
Number of words to read -1
Send READ_SINGLE_BLOCK
command(1)
Yes
Set the PDCMODE bit
HSMCI_MR |= PDCMODE
Set the block length (in bytes)
HSMCI_BLKR |= (BlockLength << 16)
Configure the PDC channel
HSMCI_RPR = Data Buffer Address
HSMCI_RCR = BlockLength/4
HSMCI_PTCR = RXTEN
Send READ_SINGLE_BLOCK
command(1)
Read status register HSMCI_SR
Poll the bit
ENDRX = 0? Yes
RETURN
RETURN
YesNo
No
No
Yes
No
Number of words to read = BlockLength/4
SAM4S Series [DATASHEET]
Atmel-11100K-ATARM-SAM4S-Datasheet_09-Jun-15
916
38.8.4 Write Operation
In write operation, the HSMCI Mode Register (HSMCI_MR) is used to define the padding value when writing non-
multiple block size. If the bit PADV is 0, then 0x00 value is used when padding data, otherwise 0xFF is used.
If set, the bit PDCMODE enables PDC transfer.
The flowchart in Figure 38-9 shows how to write a single block with or without use of PDC facilities. Polling or
interrupt method can be used to wait for the end of write according to the contents of the HSMCI Interrupt Mas k
Register (HSMCI_IMR).
917
SAM4S Series [DATASHEET]
Atmel-11100K-ATARM-SAM4S-Datasheet_09-Jun-15
Figure 38-9. Write Functional Flow Diagram
Note: 1. It is assumed that this command has been correctly sent (see Figure 38-7).
The flowchart in Figure 38-10 shows how to manage a multiple write block transfer with the PDC. Polling or
interrupt method can be used to wait for the end of write according to the contents of the HSMCI_IMR.
Send SELECT/DESELECT_CARD
command(1) to select the card
Send SET_BLOCKLEN command(1)
Write using PDC
Reset the PDCMODE bit
HSMCI_MR &= ~PDCMODE
Set the block length
HSMCI_BLKR |= (BlockLength <<16)
Send WRITE_SINGLE_BLOCK
command(1)
Set the PDCMODE bit
HSMCI_MR |= PDCMODE
Set the block length
HSMCI_BLKR |= (BlockLength << 16)
Configure the PDC channel
HSMCI_TPR = Data Buffer Address
HSMCI_TCR = BlockLength/4
Send WRITE_SINGLE_BLOCK
command(1)
Read status register HSMCI_SR
Poll the bit
NOTBUSY= 0? Yes
RETURN
No Yes
No
Read status register HSMCI_SR
Number of words to write = 0 ?
Poll the bit
TXRDY = 0?
HSMCI_TDR = Data to write
Number of words to write =
Number of words to write -1
Yes
RETURN
No
Yes
No
Number of words to write = BlockLength/4
HSMCI_PTCR = TXTEN
SAM4S Series [DATASHEET]
Atmel-11100K-ATARM-SAM4S-Datasheet_09-Jun-15
918
Figure 38-1 0. Multiple Write Functiona l Flow Diagram
Note: 1. It is assumed that this command has been correctly sent (see Figure 38-7).
38.9 SD/SDIO Card Operation
The High Speed MultiMedia Card Interface allows processing of SD Memory (Secure Digital Memory Card) and
SDIO (SD Input Output) Card commands.
SD/SDIO cards are based on the MultiMedia Card (M MC) format, but are physically sligh tly thicker and feature
higher data transfer rates, a lock switch on the side to prev ent accidental overwriting and security features. The
Send SELECT/DESELECT_CARD
command(1) to select the card
Send SET_BLOCKLEN command(1)
Set the PDCMODE bit
HSMCI_MR |= PDCMODE
Set the block length
HSMCI_BLKR |= (BlockLength << 16)
Configure the PDC channel
HSMCI_TPR = Data Buffer Address
HSMCI_TCR = BlockLength/4
Send WRITE_MULTIPLE_BLOCK
command(1)
Read status register HSMCI_SR
Poll the bit
BLKE = 0? Yes
No
HSMCI_PTCR = TXTEN
Poll the bit
NOTBUSY = 0? Yes
RETURN
No
Send STOP_TRANSMISSION
command(1)
919
SAM4S Series [DATASHEET]
Atmel-11100K-ATARM-SAM4S-Datasheet_09-Jun-15
physical form factor, pin assignment and data transfer protocol are forward-compatible with the High Speed
MultiMedia Card with some addition s. SD slots can actually be used for more than flash memory card s. Devices
that support SDIO can use small devic es designed for the SD form factor, such as GPS receivers, Wi-Fi or
Bluetooth adapter s, modems, barcode read ers, IrDA adapters, FM radio tu ners, RFID readers, digital came ras
and more.
SD/SDIO is covered by numerous patents and trad emarks, and licensing is only available through the Secure
Digital Card Association.
The SD/SDIO Card communication is based on a 9- pin interface (Clock, Command , 4 x Data and 3 x Power lines).
The communication protocol is defined as a part of this specification. The main diffe rence between the SD/SDIO
Card and the High Speed MultiMedia Card is the initialization process.
The SD/SDIO Card Register (HSMCI_SDCR) allows selection of the Card Slot and the data bus width.
The SD/SDIO Card bus allows dynamic configuration of the number of data lines. After power up, by default, the
SD/SDIO Card uses only DAT0 for data transfer. After initialization, the host can change the bus width (number of
active data lines).
38.9.1 SDIO Data Transfer Type
SDIO cards may transfer data in either a multi-byte (1 to 512 bytes) or an optional bloc k format (1 to 511 blocks),
while the SD memory cards are fixed in the block transfer mode. The TRTYP field in the HSMCI Command
Register (HSMCI_CMDR) allows to choose between SDIO Byte or SDIO Block transfer.
The number of bytes/blocks to tran sfer is set through the BCNT field in the HSMCI Block Reg ister (HSMCI_BLKR).
In SDIO Block mode, the field BLKLEN must be set to the data block size while this field is not used in SDIO Byte
mode.
An SDIO Card can have multiple I/O or combined I/O and memory (called Combo Card). Within a multi-function
SDIO or a Combo card, there are multiple devices (I/O and memory) that share access to the SD bus. In order to
allow the sharing of access to the host am ong multiple devices, SDIO and combo cards can implement the
optional concept of suspend/resume (Refer to the SDIO Specification for more details). To send a suspend or a
resume command, the host must set the SDIO Special Command field (IOSPCMD) in the HSMCI Command
Register.
38.9.2 SDIO Interrupts
Each function within an SDIO or Combo card may implement interrupt s (Refer to the SDIO Spe cification fo r more
details). In order to allow the SDIO card to interrupt the host, an interrupt func tion is added to a p in on the DAT[1]
line to signal the card’s interrupt to the host. An SD IO interrupt on each slot ca n be enabled through the HSMCI
Interrupt Enable Register. The SDIO interrupt is sampled regardless of the currently selected slot.
38.10 CE-ATA Operation
CE-ATA maps the streamlined ATA command set onto the MMC interface. The ATA task file is mapped onto MMC
register space.
CE-ATA utilizes five MMC commands:
GO_IDLE_STATE (CMD0): used for hard reset.
STOP_TRANSMISSION (CMD12): causes the ATA command currently executing to be aborted.
FAST_IO (CMD39): Used for single register access to the ATA taskfile registers, 8-bit access only.
RW_MULTIPLE_REGISTERS (CMD60): used to issue an ATA command or to access the control/status
registers.
RW_MULTIPLE_BLOCK (CMD61): used to transfer data for an ATA command.
CE-ATA utilizes the same MMC command sequences for initialization as traditional MMC devices.
SAM4S Series [DATASHEET]
Atmel-11100K-ATARM-SAM4S-Datasheet_09-Jun-15
920
38.10.1 Executing an ATA Polling Command
1. Issue READ_DMA_EXT with RW_MULTIPLE_REGISTER (CMD60) for 8 KB of DATA.
2. Read the ATA status register until DRQ is set.
3. Issue RW_MULTIPLE_BLOCK (C MD 61) to transfer DATA.
4. Read the ATA status register until DRQ && BSY are configured to 0.
38.10.2 Executing an ATA Interrupt Command
1. Issue READ_DMA_EXT with RW_MULTIPLE_REGISTER (CMD60) for 8 KB of DATA with nIEN field set
to zero to enable the command completion signal in the device.
2. Issue RW_MULTIPLE_BLOCK (C MD 61) to transfer DATA.
3. Wait for Completion Signal Received Interrupt.
38.10.3 Aborting an ATA Command
If the host needs to abort an AT A command prior to the com pletion signal it must send a special command to avoid
potential collision on the command line. The SPCMD field of the HSMCI_CMDR mu st be set to 3 to issue the CE-
ATA completion Signal Disable Command.
38.10.4 CE-ATA Error Recovery
Several methods of ATA command failure may occur, including:
No response to an MMC command, such as RW_MULTIPLE_REGISTER (CMD60).
CRC is invalid for an MMC command or response.
CRC16 is invalid for an MMC data packet.
ATA Status register reflects an error by setting the ERR bit to one.
The command completion signal does not arrive within a host specified time out period.
Error conditions are expected to happen infrequently. Thus, a rob ust error recovery mechanism may be used for
each error event. The recommended error recovery procedure after a timeout is:
Issue the command completion signal disable if nIEN was cleared to zero and the RW_MULTIPLE_BLOCK
(CMD61) response has been received.
Issue STOP_TRANSMISSION (CMD12) and successfully receive the R1 response.
Issue a software reset to the CE-ATA device using FAST_IO (CMD39).
If STOP_TRANMISSION (CMD12) is successful, then the device is again ready for ATA co mmands. However, if
the error re covery procedure do es not work as expected or there is another timeout, the next step is to issue
GO_IDLE_STATE (CMD0) to the device. GO_IDLE_STATE (CMD0) is a hard reset to the device and completely
resets all device states.
Note that after issuing GO_IDLE_STATE (CMD0), all device initialization needs to be completed again. If the CE-
ATA device completes all MMC commands correctly but fails the ATA command with the ERR bit set in the ATA
Status registe r, no error re covery ac tion is requir ed. The ATA command itself failed implying that the device could
not complete the action requested, however, there was no communication or protocol failure. After the device
signals an error by setting the ERR bit to one in the ATA Status register, the host may attempt to retry the
command.
38.11 HSMCI Boot Operation Mode
In boot operation mode, the processor can read boot data from the slave (MMC device) by keeping the CMD line
low after powe r-on befo re issuing CMD1. Th e data can be read fro m eithe r the boot ar ea or user ar ea, dep ending
on register setting. As it is not possible to boot directly on SD-CARD, a preliminary boot code must be stored in
internal Flash.
921
SAM4S Series [DATASHEET]
Atmel-11100K-ATARM-SAM4S-Datasheet_09-Jun-15
38.11.1 Boot Procedure, Processor Mode
1. C on fig ur e th e HSM C I da ta bus width programming SDCBUS Field in the HSMCI_SDCR. The
BOOT_BUS_WIDTH field located in the device Extended CSD register must be set accordingly.
2. Set the byte count to 512 bytes and the block count to the desired number of blocks, writing BLKLEN and
BCNT fields of the HSMCI_BLKR.
3. Issue the Boot Operation Request command by writing to the HSMCI_CMDR with SPCMD field set to
BOOTREQ, TRDIR set to READ and TRCMD set to “start data transfer”.
4. The BOOT_ACK field located in the HSMCI_CMDR must be set to one, if the BOOT_ACK field of the MMC
device located in the Extended CSD register is set to one.
5. Host processor can copy boot data sequentially as soon as the RXRDY flag is asserted.
6. When Data transfer is completed, host processor shall terminate the boot stream by writing the
HSMCI_CMDR with SPCMD field set to BOOTEND.
38.12 HSMCI Transfer Done Timings
38.12.1 Definition
The XFRDONE flag in the HSMCI_SR indicates exactly when the read or write sequence is finished.
38.12.2 Read Access
During a read ac ce ss, th e XFR D ONE flag behaves as shown in Figure 38-11.
Figure 38-11. XFRDONE During a Read Access
38.12.3 Write Access
During a write access, the XFRDONE flag behaves as shown in Figure 38-12.
CMD line
HSMCI read CMD
Card response
CMDRDY flag
Data
1st Block Last Block
Not busy flag
XFRDONE flag
The CMDRDY flag is released 8 tbit after the end of the card response.
SAM4S Series [DATASHEET]
Atmel-11100K-ATARM-SAM4S-Datasheet_09-Jun-15
922
Figure 38-12. XFRDONE Dur in g a Wr ite Access
CMD line
Card response
CMDRDY flag
Data bus - D0
1st Block
Not busy flag
XFRDONE flag
The CMDRDY flag is released 8 tbit after the end of the card response.
Last Block
D0
1st Block Last Block
D0 is tied by the card
D0 is released
HSMCI write CMD
923
SAM4S Series [DATASHEET]
Atmel-11100K-ATARM-SAM4S-Datasheet_09-Jun-15
38.13 Register Write Protection
To prevent any single software error from corrupting HSMCI behavior, certain registers in the address space can
be write-protected by setting the WPEN bit in the HSMCI Write Protectio n Mode Register (HSMCI_WPMR).
If a write access to a write-protected register is detected, the WPVS bit in the H SMCI Write Protection Status
Register (HSMCI_WPS R) is set and the field WPVSRC indicates the register in which the write access has been
attempted.
The WPVS bit is automatically cleared after reading the HSMCI_WPSR.
The following registers can be protected:
HSMCI Mode Register
HSMCI Data Timeout Register
HSMCI SDCard/SDIO Register
HSMCI Completion Signal Timeout Register
HSMCI Configuration Register
SAM4S Series [DATASHEET]
Atmel-11100K-ATARM-SAM4S-Datasheet_09-Jun-15
924
38.14 High Speed MultiMedia Card Interface (HSMCI) User Interface
Notes: 1. The Response Register can be read by N accesses at the same HSMCI_RSPR or at consecutive addresses (0x20 to
0x2C). N depends on the size of the response.
Table 38-8 . Register Mapping
Offset Register Name Access Reset
0x00 Control Register HSMCI_CR Write-only –
0x04 Mode Register HSMCI_MR Read/Write 0x0
0x08 Data Timeout Register HSMCI_DTOR Read/Write 0x0
0x0C SD/SDIO Card Register HSMCI_SDCR Read/Write 0x0
0x10 Argument Registe r HSMCI_ARGR Read/Write 0x0
0x14 Command Register HSMCI_CMDR Write-only –
0x18 Block Register HSMCI_BLKR Read/Write 0x0
0x1C Completion Sig nal Timeout Register HSMCI_CSTOR Read/Write 0x0
0x20 Response Register(1) HSMCI_RSPR Read-only 0x0
0x24 Response Register(1) HSMCI_RSPR Read-only 0x0
0x28 Response Register(1) HSMCI_RSPR Read-only 0x0
0x2C Response Register(1) HSMCI_RSPR Read-only 0x0
0x30 Receive Data Register HSMCI_RDR Read-only 0x0
0x34 Transmit Data Register HSMCI_TDR Write-only –
0x38–0x3C Reserved – – –
0x40 Status Register HSMCI_SR Read-only 0xC0E5
0x44 Interrupt Enable Register HSMCI_IER Write-only –
0x48 Interrupt Disable Register HSMCI_IDR Write-only –
0x4C Interrupt Mask Register HSMCI_IMR Read-only 0x0
0x50 Reserved – – –
0x54 Configuration Register HSMCI_CFG Read/Write 0x00
0x58–0xE0 Reserved – – –
0xE4 Write Protection Mode Register HSMCI_WPMR Read/Write –
0xE8 Write Protection Status Register HSMCI_WPSR Read-only –
0xEC–0xFC Reserved – – –
0x100–0x128 Reserved for PDC registers – – –
0x12C–0x1FC Reserved – – –
0x200 FIFO Memory Aperture0 HSMCI_FIFO0 Read/Write 0x0
... ... ... ... ...
0x5FC FIFO Memory Aperture255 HSMCI_FIFO255 Read/Write 0x0
925
SAM4S Series [DATASHEET]
Atmel-11100K-ATARM-SAM4S-Datasheet_09-Jun-15
38.14.1 HSMCI Control Register
Name: HSMCI_CR
Address: 0x40000000
Access: Write-only
• MCIEN: Multi-Media Interface Enable
0: No effect.
1: Enables the Multi-Media Interface if MCDIS is 0.
• MCIDIS: Multi-Media Interface Disable
0: No effect.
1: Disables the Multi-Media Interface.
• PWSEN: Power Save Mode Enable
0: No effect.
1: Enables the Power Saving Mode if PWSDIS is 0.
Warning: Before enabling this mode, the user must set a value different from 0 in the PWSDIV field of the HSMCI_MR.
• PWSDIS: Power Save Mode Disable
0: No effect.
1: Disables the Power Saving Mode.
• SWRST: Software Reset
0: No effect.
1: Resets the HSMCI. A software triggered hardware reset of the HSMCI is performed.
31 30 29 28 27 26 25 24
––––––––
23 22 21 20 19 18 17 16
––––––––
15 14 13 12 11 10 9 8
––––––––
76543210
SWRST – – – PWSDIS PWSEN MCIDIS MCIEN
SAM4S Series [DATASHEET]
Atmel-11100K-ATARM-SAM4S-Datasheet_09-Jun-15
926
38.14.2 HSMCI Mode Register
Name: HSMCI_MR
Address: 0x40000004
Access: Read/Write
This register can only be written if the WPEN bit is cleared in the HSMCI Write Protection Mode Register.
• CLKDIV: Clock Divider
High Speed MultiMedia Card Interface clock (MCCK or HSMCI_CK) is Master Clock (MCK) divided by (2*(CLKDIV+1)).
• PWSDIV: Power Saving Divider
High Speed MultiMedia Card Interface clock is divided by 2(PWSDIV) + 1 when entering Power Saving Mode.
Warning: This value must be different from 0 before enabling the Power Save Mode in the HSMCI_CR (HSMCI_PWSEN
bit).
• RDPROOF: Read Proof Enable
Enabling Read Proof allows to stop the HSMCI Clock during read access if the internal FIFO is full. This will guarantee data
integrity, not bandwidth.
0: Disables Read Proof.
1: Enables Read Proof.
• WRPROOF: Write Proof Enable
Enabling Write Proof allows to stop the HSMCI Clock during write access if the internal FIFO is full. This will guarantee
data integrity, not bandwidth.
0: Disables Write Proof.
1: Enables Write Proof.
• FBYTE: Force Byte Transfer
Enabling Force Byte Transfer allow byte transfers, so that transfer of blocks with a size different from modulo 4 can be
supported.
Warning: BLKLEN value depends on FBYTE.
0: Disables Force Byte Transfer.
1: Enables Force Byte Transfer.
31 30 29 28 27 26 25 24
––––––––
23 22 21 20 19 18 17 16
––––––––
15 14 13 12 11 10 9 8
PDCMODE PADV FBYTE WRPROOF RDPROOF PWSDIV
76543210
CLKDIV
927
SAM4S Series [DATASHEET]
Atmel-11100K-ATARM-SAM4S-Datasheet_09-Jun-15
• PADV: Padding Value
0: 0x00 value is used when padding data in write transfer.
1: 0xFF value is used when padding data in write transfer.
PADV may be only in manual transfer.
• PDCMODE: PDC-oriented Mode
0: Disables PDC transfer
1: Enables PDC transfer. In this case, UNRE and OVRE flags in the HSMCI Status Register (HSMCI_SR) are deactivated
after the PDC transfer has been complet ed .
SAM4S Series [DATASHEET]
Atmel-11100K-ATARM-SAM4S-Datasheet_09-Jun-15
928
38.14.3 HSMCI Data Timeout Register
Name: HSMCI_DTOR
Address: 0x40000008
Access: Read/Write
This register can only be written if the WPEN bit is cleared in the HSMCI Write Protection Mode Register.
• DTOCYC: Data Ti meout Cycle Number
This field determines the maxi mum number of Master Clock cycles that the HSMCI waits between two data block transfers.
It equals (DTOCYC x Multiplier).
• DTOMUL: Data Timeout Multiplier
If the data time-out set by DTOCYC and DTOM UL has been excee ded, the Data Time-out Erro r flag (DTOE) in the HSMCI
Status Register (HSMCI_SR) rises.
31 30 29 28 27 26 25 24
––––––––
23 22 21 20 19 18 17 16
––––––––
15 14 13 12 11 10 9 8
––––––––
76543210
– DTOMUL DTOCYC
Value Name Description
01DTOCYC
1 16 DTOCYC x 16
2 128 DTOCYC x 128
3 256 DTOCYC x 256
4 1024 DTOCYC x 1024
5 4096 DTOCYC x 4096
6 65536 DTOCYC x 65536
7 1 048576 DTOCYC x 1048576
929
SAM4S Series [DATASHEET]
Atmel-11100K-ATARM-SAM4S-Datasheet_09-Jun-15
38.14.4 HSMCI SDCard/SDIO Register
Name: HSMCI_SDCR
Address: 0x4000000C
Access: Read/Write
This register can only be written if the WPEN bit is cleared in the HSMCI Write Protection Mode Register.
• SDCSEL: SDCard/SDIO Slot
• SDCBUS: SDCard/SDIO Bus Width
31 30 29 28 27 26 25 24
––––––––
23 22 21 20 19 18 17 16
––––––––
15 14 13 12 11 10 9 8
––––––––
76543210
SDCBUS –––– SDCSEL
Value Name Description
0 SLOTA Slot A is selected.
1SLOTB–
2SLOTC–
3SLOTD–
Value Name Description
011 bit
1–Reserved
244 bits
388 bits
SAM4S Series [DATASHEET]
Atmel-11100K-ATARM-SAM4S-Datasheet_09-Jun-15
930
38.14.5 HSMCI Argument Register
Name: HSMCI_ARGR
Address: 0x40000010
Access: Read/Write
• ARG: Command Argument
31 30 29 28 27 26 25 24
ARG
23 22 21 20 19 18 17 16
ARG
15 14 13 12 11 10 9 8
ARG
76543210
ARG
931
SAM4S Series [DATASHEET]
Atmel-11100K-ATARM-SAM4S-Datasheet_09-Jun-15
38.14.6 HSMCI Command Register
Name: HSMCI_CMDR
Address: 0x40000014
Access: Write-only
This register is write-prote cted while CMDRDY is 0 in HSMCI_SR. If an Interrup t command is sen t, this register is only writ-
able by an interrupt response (field SPCMD). This means that the current command execution cannot be inte rrupted or
modified.
• CMDNB: Command Number
This is the command index.
• RSPTYP: Response Type
• SPCMD: Special Comm an d
31 30 29 28 27 26 25 24
––––BOOT_ACKATACS IOSPCMD
23 22 21 20 19 18 17 16
– – TRTYP TRDIR TRCMD
15 14 13 12 11 10 9 8
– – – MAXLAT OPDCMD SPCMD
76543210
RSPTYP CMDNB
Value Name Description
0 NORESP No response
1 48_BIT 48-bit response
2 136_BIT 136-bit response
3 R1B R1b response type
Value Name Description
0 STD No t a special CMD.
1INIT
Initialization CMD:
74 clock cycles for initialization sequence.
2 SYNC Synchronized CMD:
Wait for the end of the current data block transfer before sending the pending command.
3CE_ATA
CE-ATA Completion Signal disable Command.
The host cancels the ability for the device to return a command completion signal on the command line.
4IT_CMD
Interrupt command:
Corresponds to the Interrupt Mode (CMD40).
5 IT_RESP Interrupt response :
Corresponds to the Interrupt Mode (CMD40).
6BOR
Boot Operation Request.
Start a boot operation mode, the host processor can read boot data from the MMC device directly.
7 EBO End Boot Operation.
This command allows the host processor to terminate the boot operation mode.
SAM4S Series [DATASHEET]
Atmel-11100K-ATARM-SAM4S-Datasheet_09-Jun-15
932
• OPDCMD: Open Drain Command
0 (PUSHPULL): Push pull command.
1 (OPENDRAIN): Open drain command.
• MAXLAT: Max Latency for Command to Response
0 (5): 5-cycle max latency.
1 (64): 64-cycle max latency.
• TRCMD: Transfer Command
• TRDIR: Transfer Direction
0 (WRITE): Write.
1 (READ): Read.
• TRTYP: Transfer Type
• IOSPCMD: SDIO Special Command
• ATACS: ATA with Command Completion Signal
0 (NORMAL): Normal operation mode.
1 (COMPLETION): This bit indicates that a completion signal is expected within a programmed amount of time
(HSMCI_CSTOR).
• BOOT_ACK: Boot Operation Acknowledge
The master can choose to receive the boot acknowledge from the slave when a Boot Request command is issued. When
set to one this field indicates that a Boot acknowledge is expect e d with in a pr og rammabl e am ount of time defined with
DTOMUL and DTOCYC fields located in the HSMCI_DTOR. If the acknowledge pattern is not received then an acknowl-
edge timeout error is raised. If the acknowledge pattern is corrupted then an acknowledge pattern error is set.
Value Name Description
0 NO_DATA No data transfer
1START_DAT
AStart data transfer
2 STOP_DATA Stop data transfer
3–Reserved
Value Name Description
0 SINGLE MMC/SD Card Single Block
1 MULTIPLE MMC/SD Card Multiple Block
2 STREAM MMC Stream
4 BYTE SDIO Byte
5 BLOCK SDIO Block
Value Name Description
0 STD Not an SDIO Special Command
1 SUSPEND SDIO Suspend Command
2 RESUME SDIO Resume Co mma n d
933
SAM4S Series [DATASHEET]
Atmel-11100K-ATARM-SAM4S-Datasheet_09-Jun-15
38.14.7 HSMCI Block Register
Name: HSMCI_BLKR
Address: 0x40000018
Access: Read/Write
• BCNT: MMC/SDIO Block Count - SDIO Byte Count
This field determines the number of data byte(s) or block(s) to transfer.
The transfer data type and the authorized values for BCNT field are determined by the TRTYP field in the HSMCI Com-
mand Register (HSMCI_CMDR).
When TRTYP = 1 (MMC/SDCARD Multiple Block), BCNT can be programmed from 1 to 65535, 0 corresponds to an infi-
nite block transfer.
When TRTYP = 4 (SDIO Byte), BCNT can be programmed from 1 to 511, 0 corresponds to 512-byte transfer. Values in
range 512 to 65536 are forbidden.
When TRTYP = 5 (SDIO Block), BCNT can be programmed from 1 to 511, 0 corresponds to an infinite block transfer . Val-
ues in range 512 to 65536 are forbidden.
Warning: In SDIO Byte and Block modes (TRTYP = 4 or 5), writing the 7 last bits of BCNT field with a value which differs
from 0 is forbidden and may lead to unpredictable results.
• BLKLEN: Data Block Length
This field determines the size of the data block.
Bits 16 and 17 must be configured to 0 if FBYTE is disabled.
Note: In SDIO Byte mode, BLKLEN field is not used.
31 30 29 28 27 26 25 24
BLKLEN
23 22 21 20 19 18 17 16
BLKLEN
15 14 13 12 11 10 9 8
BCNT
76543210
BCNT
SAM4S Series [DATASHEET]
Atmel-11100K-ATARM-SAM4S-Datasheet_09-Jun-15
934
38.14.8 HSMCI Completion Signal Timeout Register
Name: HSMCI_CSTOR
Address: 0x4000001C
Access: Read/Write
This register can only be written if the WPEN bit is cleared in the HSMCI Write Protection Mode Register.
• CSTOCYC: Completion Signal Timeout Cycle Number
This field determines the maxi mum number of Master Clock cycles that the HSMCI waits between two data block transfers.
Its value is calculated by (CSTOCYC x Multiplier).
• CSTOMUL: Completion Signal Timeout Multiplier
This field determines the maxi mum number of Master Clock cycles that the HSMCI waits between two data block transfers.
Its value is calculated by (CSTOCYC x Multiplier).
These fields determine the maximum number of Master Clock cycles that the HSMCI waits between the end of the data
transfer and the assertio n of the completion signal. The data transfer comp rises data phase and the optio nal busy phase. If
a non-DATA ATA command is issued, the HSMCI starts waiting imme diately afte r the end of the response until the co mple-
tion signal.
Multiplier is defined by CSTOMUL as shown in the following table:
If the data time-out set by CSTOCYC and CSTOMUL has been exceede d, the Completion Signal Time-out Error flag
(CSTOE) in the HSMCI Status Register (HSMCI_SR) rises.
31 30 29 28 27 26 25 24
––––––––
23 22 21 20 19 18 17 16
––––––––
15 14 13 12 11 10 9 8
––––––––
76543210
– CSTOMUL CSTOCYC
Value Name Description
0 1 CSTOCYC x 1
1 16 CSTOCYC x 16
2 128 CSTOCYC x 128
3 256 CSTOCYC x 256
4 1024 CSTOCYC x 1024
5 4096 CSTOCYC x 4096
6 65536 CSTOCYC x 65536
7 1 048576 CSTOCYC x 1048576
935
SAM4S Series [DATASHEET]
Atmel-11100K-ATARM-SAM4S-Datasheet_09-Jun-15
38.14.9 HSMCI Response Register
Name: HSMCI_RSPR
Address: 0x40000020
Access: Read-only
• RSP: Response
Note: 1. The respon se regi ster ca n be re ad by N accesses at the same HSMCI_RSPR or at consecutive addresses (0x20 to 0x2C).
N depends on the size of the re sponse.
31 30 29 28 27 26 25 24
RSP
23 22 21 20 19 18 17 16
RSP
15 14 13 12 11 10 9 8
RSP
76543210
RSP
SAM4S Series [DATASHEET]
Atmel-11100K-ATARM-SAM4S-Datasheet_09-Jun-15
936
38.14.10HSMCI Receive Data Register
Name: HSMCI_RDR
Address: 0x40000030
Access: Read-only
• DATA: Data to Read
31 30 29 28 27 26 25 24
DATA
23 22 21 20 19 18 17 16
DATA
15 14 13 12 11 10 9 8
DATA
76543210
DATA
937
SAM4S Series [DATASHEET]
Atmel-11100K-ATARM-SAM4S-Datasheet_09-Jun-15
38.14.11HSMCI Transmit Data Register
Name: HSMCI_TDR
Address: 0x40000034
Access: Write-only
• DATA: Data to Write
31 30 29 28 27 26 25 24
DATA
23 22 21 20 19 18 17 16
DATA
15 14 13 12 11 10 9 8
DATA
76543210
DATA
SAM4S Series [DATASHEET]
Atmel-11100K-ATARM-SAM4S-Datasheet_09-Jun-15
938
38.14.12HSMCI Status Register
Name: HSMCI_SR
Address: 0x40000040
Access: Read-only
• CMDRDY: Command Ready (cleared by writing in HSMCI_CMDR)
0: A command is in progress.
1: The last command has been sent.
• RXRDY: Re ce iv er Rea d y (c le ared by reading HSMCI_RDR)
0: Data has not yet been received since the last read of HSMCI_RDR.
1: Data has been received since the last read of HSMCI_RDR.
• TXRDY: Transmit Ready (cleared by writing in HSMCI_TDR)
0: The last data written in HSMCI_TDR has not yet been transferred in the Shift Register.
1: The last data written in HSMCI_TDR has been transferred in the Shift Register.
• BLKE: Data Block Ended (cleared on read)
This flag must be used only for Write Operations.
0: A data block transfer is not yet finished.
1: A data block transfer has ended, including the CRC16 Status transmission. The flag is set for each transmitted CRC
Status.
Refer to the MMC or SD Specification for more details concerning the CRC Status.
• DTIP: Data Transfer in Progress (cleared at the end of CRC16 calculation)
0: No data transfer in progress.
1: The current data transfer is still in progress, including CRC16 calculation.
• NOTBUSY: HSMCI Not Busy
A block write operation uses a simple busy si gnalling of th e write opera tion duration on th e data (DAT0) line: durin g a data
transfer block, if the card does not have a free data receive buffer, the card indicates this condition by pulling down the data
line (DAT0) to LOW. The card stops pulling down the data line as soon as at least one receive buffer for the defined data
transfer block length becomes free.
Refer to the MMC or SD Specification for more details concerning the busy behavior.
31 30 29 28 27 26 25 24
UNRE OVRE ACKRCVE ACKRCV XFRDONE FIFOEMPTY – –
23 22 21 20 19 18 17 16
CSTOE DTOE DCRCE RTOE RENDE RCRCE RDIRE RINDE
15 14 13 12 11 10 9 8
TXBUFE RXBUFF CSRCV SDIOWAIT – – – SDIOIRQA
76543210
ENDTX ENDRX NOTBUSY DTIP BLKE TXRDY RXRDY CMDRDY
939
SAM4S Series [DATASHEET]
Atmel-11100K-ATARM-SAM4S-Datasheet_09-Jun-15
For all the read operations, the NOTBUSY flag is cleared at the end of the host command.
For the Infinite Read Multiple Blocks, the NOTBUSY flag is set at the end of the STOP_TRANSMISSION host command
(CMD12).
For the Single Block Reads, the NOTBUSY flag is set at the end of the data read block.
For the Multiple Block Reads with predefined block count, the NOTBUSY flag is set at the end of the last received data
block.
The NOTBUSY flag allows to deal with these different states.
0: The HSMCI is not ready for new data transfer. Cleared at the end of the card response.
1: The HSMCI is ready for new data transfer. Set when the busy state on the data line has ended. This corresponds to a
free internal data receive buffer of the card.
• ENDRX: End of RX Buffer (cleared by writing HSMCI_RCR or HSMCI_RNCR(1))
0: The Receive Counter Register has not reached 0 since the last write in HSMCI_RCR or HSMCI_RNCR.
1: The Receive Counter Register has reached 0 since the last write in HSMCI_RCR or HSMCI_RNCR.
• ENDTX: End of TX Buffer (cleared by writing HSMCI_TCR or HSMCI_TNCR(1))
0: The Transmit Counter Register has not reached 0 since the last write in HSMCI_TCR or HSMCI_TNCR.
1: The Transmit Counter Register has reached 0 since the last write in HSMCI_TCR or HSMCI_TNC R.
Note: BLKE and NOTBUSY flags can be used to check that the data has been successfully transmitted on the data lines and not only
transferred from the PDC to the HSMCI Controller.
• SDIOIRQA: SDIO Interrupt for Slot A (cleared on read)
0: No interrupt detected on SDIO Slot A.
1: An SDIO Interrupt on Slot A occurred.
• SDIOWAIT: SDIO Read Wait Operation Status
0: Normal Bus operation.
1: The data bus has entered IO wait state.
• CSRCV: CE-ATA Completion Signal Received (cleared on read)
0: No completion sign a l rece ive d sin ce las t s tat us rea d op er atio n.
1: The device has issued a command completion signal on the command line.
• RXBUFF: RX Buffer Full (cleared by writing HSMCI_RCR or HSMCI_RNCR(1))
0: HSMCI_RCR or HSMCI_RNCR has a value other than 0.
1: Both HSMCI_RCR and HSMCI_RNCR have a value of 0.
• TXBUFE: TX Buffer Empty (cleared by writing HSMCI_TCR or HSMCI_TNCR(1))
0: HSMCI_TCR or HSMCI_TNCR has a value other than 0.
1: Both HSMCI_TCR and HSMCI_TNCR have a value of 0.
Note: BLKE and NOTBUSY flags can be used to check that the data has been successfully transmitted on the data lines and not only
transferred from the PDC to the HSMCI Controller.
• RINDE: Response Index Error (cleared by writing in HSMCI_CMDR)
0: No error.
1: A mismatch is detected between the command index sent and the response index received.
SAM4S Series [DATASHEET]
Atmel-11100K-ATARM-SAM4S-Datasheet_09-Jun-15
940
• RDIRE: Response Direction Error (cleared by writing in HSMCI_CMDR)
0: No error.
1: The direction bit from card to host in the response has not been detected.
• RCRCE: Response CRC Error (cleared by writing in HSMCI_CMDR)
0: No error.
1: A CRC7 error has been detected in the response.
• RENDE: Response End Bit Error (cleared by writing in HSMCI_CMDR)
0: No error.
1: The end bit of the response has not been detected.
• RTOE: Response Time-out Error (cleared by writing in HSMCI_CMDR)
0: No error.
1: The response time-out set by MAXLAT in the HSMCI_CMDR has been exceeded.
• DCRCE: Data CRC Error (cleared on read)
0: No error.
1: A CRC16 error has been detected in the last data block.
• DTOE: Data Time-out Error (cleared on read)
0: No error.
1: The data time-out set by DTOCYC and DTOMUL in HSMCI_DTOR has been exceeded.
• CSTOE: Completion Signal Time-out Error (cleared on read)
0: No error.
1: The completion signal time-out set by CSTOCYC and CSTOMUL in HSMCI_CSTOR has been exceeded.
• FIFOEMPTY: FIFO empty flag
0: FIFO contains at least one byte.
1: FIFO is empty.
• XFRDONE: Transfer Done flag
0: A transfer is in progress.
1: Command Register is ready to operate and the data bus is in the idle state.
• ACKRCV: Boot Operation Acknowledge Received (cleared on read)
0: No Boot acknowledge received since the last read of the HSMCI_SR.
1: A Boot acknowledge signal has been received since the last read of HSMCI_SR.
• ACKRCVE: Boot Operation Acknowledge Error (cleared on read)
0: No boot operation error since the last read of HSMCI_SR
1: Corrupted Boot Acknowledge signal received since the last rea d of HSMCI _SR .
941
SAM4S Series [DATASHEET]
Atmel-11100K-ATARM-SAM4S-Datasheet_09-Jun-15
• OVRE: Overrun (if FERRCTRL = 1, cleared by writing in HSMCI_CMDR or cleared on read if FERRCTRL = 0)
0: No error.
1: At least one 8-bit received data has been lost (not read).
If FERRCTRL = 1 in HSMCI_CFG, OVRE is cleared on read.
If FERRCTRL = 0 in HSMCI_CFG, OVRE is cleared by writing HSMCI_CMDR.
• UNRE: Underrun (if FERRCTRL = 1, cleared by writing in HSMCI_CMDR or cleared on read if FERRCTRL = 0)
0: No error.
1: At least one 8-bit data has been sent without valid information (not written).
If FERRCTRL = 1 in HSMCI_CFG, OVRE is cleared on read.
If FERRCTRL = 0 in HSMCI_CFG, OVRE is cleared by writing HSMCI_CMDR.
Note: 1. HSMCI_RCR, HSMCI_RNCR, HSMCI_TCR, HSMCI_TNCR are PDC registers.
SAM4S Series [DATASHEET]
Atmel-11100K-ATARM-SAM4S-Datasheet_09-Jun-15
942
38.14.13HSMCI Interrupt Enable Register
Name: HSMCI_IER
Address: 0x40000044
Access: Write-only
The following configuration values are valid for all listed bit names of this register:
0: No effect.
1: Enables the corresponding interrupt.
• CMDRDY: Command Ready Interrupt Enable
• RXRDY: Re ce iv er Rea d y Inte rrup t Enable
• TXRDY: Transmit Ready Interrupt Enable
• BLKE: Data Block Ended Interrupt Enable
• DTIP: Data Transfer in Progress Interrupt Enab le
• NOTBUSY: Data Not Busy Interrupt Enable
• ENDRX: End of Receive Buffer Interrupt Enable
• ENDTX: End of Transmit Buffer Interrupt Enable
• SDIOIRQA: SDIO Interrupt for Slot A Interrupt Enable
• SDIOWAIT: SDIO Read Wait Operation Status Interrupt Enable
• CSRCV: Completion Signal Received Interrupt Enable
• RXBUFF: Receive Buffer Full Interrupt Enable
• TXBUFE: Transmit Buffer Empty Interrupt Enable
• RINDE: Response Index Error Interrupt Enable
• RDIRE: Response Direction Error Interrupt Enable
• RCRCE: Response CRC Error Interrupt Enable
• RENDE: Response End Bit Error Interrupt Enable
31 30 29 28 27 26 25 24
UNRE OVRE ACKRCVE ACKRCV XFRDONE FIFOEMPTY – –
23 22 21 20 19 18 17 16
CSTOE DTOE DCRCE RTOE RENDE RCRCE RDIRE RINDE
15 14 13 12 11 10 9 8
TXBUFE RXBUFF CSRCV SDIOWAIT – – – SDIOIRQA
76543210
ENDTX ENDRX NOTBUSY DTIP BLKE TXRDY RXRDY CMDRDY
943
SAM4S Series [DATASHEET]
Atmel-11100K-ATARM-SAM4S-Datasheet_09-Jun-15
• RTOE: Response Time-out Error Interrupt Enable
• DCRCE: Data CRC Error Interrupt Enable
• DTO E: Data Time -o ut Error Interrupt Enable
• CSTOE: Completion Signal Timeout Error Interrupt Enable
• FIFOEMPTY: FIFO empty Interrupt enable
• XFRDONE: Transfer Done Interrupt enable
• ACKRCV: Boot Acknowledge Interrupt Enable
• ACKRCVE: Boot Acknowledge Error Interrupt Enable
• OVRE: Overrun Interrupt Enable
• UNRE: Underrun Interrupt Enable
SAM4S Series [DATASHEET]
Atmel-11100K-ATARM-SAM4S-Datasheet_09-Jun-15
944
38.14.14HSMCI Interrupt Disable Register
Name: HSMCI_IDR
Address: 0x40000048
Access: Write-only
The following configuration values are valid for all listed bit names of this register:
0: No effect.
1: Disables the corresponding interrupt.
• CMDRDY: Command Ready Interrupt Disable
• RXRDY: Receiver Ready Interrupt Disable
• TXRDY: Transmit Ready Interrupt Disable
• BLKE: Data Block Ended Interrupt Disable
• DTIP: Data Transfer in Progress Interrupt Disable
• NOTBUSY: Data Not Busy Interrupt Disable
• ENDRX: End of Receive Buffer Interrupt Disable
• ENDTX: End of Transmit Buffer Interrupt Disable
• SDIOIRQA: SDIO Interrupt for Slot A Interrupt Disable
• SDIOWAIT: SDIO Read Wait Operation Status Interrupt Disable
• CSRCV: Completion Signal received interrupt Disable
• RXBUFF: Receive Buffer Full Interrupt Disable
• TXBUFE: Transmit Buffer Empty Interrupt Disable
• RINDE: Response Index Error Interrupt Disable
• RDIRE: Response Direction Error Interrupt Disable
• RCRCE: Response CRC Error Interrupt Disable
• RENDE: Response End Bit Error Interrupt Disable
31 30 29 28 27 26 25 24
UNRE OVRE ACKRCVE ACKRCV XFRDONE FIFOEMPTY – –
23 22 21 20 19 18 17 16
CSTOE DTOE DCRCE RTOE RENDE RCRCE RDIRE RINDE
15 14 13 12 11 10 9 8
TXBUFE RXBUFF CSRCV SDIOWAIT – – – SDIOIRQA
76543210
ENDTX ENDRX NOTBUSY DTIP BLKE TXRDY RXRDY CMDRDY
945
SAM4S Series [DATASHEET]
Atmel-11100K-ATARM-SAM4S-Datasheet_09-Jun-15
• RTOE: Response Time-out Error Interrupt Disable
• DCRCE: Data CRC Error Interrupt Disable
• DTOE: Data Time-out Error Interrupt Disable
• CSTOE: Completion Signal Time out Error Interrupt Disable
• FIFOEMPTY: FIFO empty Interrupt Disable
• XFRDONE: Transfer Done Interrupt Disable
• ACKRCV: Boot Acknowledge Interrupt Disable
• ACKRCVE: Boot Acknowledge Error Interrupt Disable
• OVRE: Overrun Interrupt Disable
• UNRE: Underrun Interrupt Disable
SAM4S Series [DATASHEET]
Atmel-11100K-ATARM-SAM4S-Datasheet_09-Jun-15
946
38.14.15HSMCI Interrupt Mask Register
Name: HSMCI_IMR
Address: 0x4000004C
Access: Read-only
The following configuration values are valid for all listed bit names of this register:
0: The corresponding interrupt is not enabled.
1: The corresponding interrupt is enabled.
• CMDRDY: Command Ready Inte rrupt Mask
• RXRDY: Re ce iv er Rea d y Inte rrup t Mas k
• TXRDY: Transmit Ready Interrupt Mask
• BLKE: Data Block Ended Interrupt Mask
• DTIP: Data Transfer in Progress Interrupt Mask
• NOTBUSY: Data Not Busy Interrupt Mask
• ENDRX: End of Receive Buffer Interrupt Mask
• ENDTX: End of Transmit Buffer Interrupt Mask
• SDIOIRQA: SDIO Interrupt for Slot A Interrupt Mask
• SDIOWAIT: SDIO Read Wait Operation Status Interrupt Mask
• CSRCV: Completion Signal Received Interrupt Mask
• RXBUFF: Receive Buffer Full Interrupt Mask
• TXBUFE: Transmit Buffer Empty Interrupt Mask
• RINDE: Response Index Error Interrupt Mask
• RDIRE: Response Direction Error Interrupt Mask
• RCRCE: Response CRC Error Interrupt Mask
• RENDE: Response End Bit Error Interrupt Mask
31 30 29 28 27 26 25 24
UNRE OVRE ACKRCVE ACKRCV XFRDONE FIFOEMPTY – –
23 22 21 20 19 18 17 16
CSTOE DTOE DCRCE RTOE RENDE RCRCE RDIRE RINDE
15 14 13 12 11 10 9 8
TXBUFE RXBUFF CSRCV SDIOWAIT – – – SDIOIRQA
76543210
ENDTX ENDRX NOTBUSY DTIP BLKE TXRDY RXRDY CMDRDY
947
SAM4S Series [DATASHEET]
Atmel-11100K-ATARM-SAM4S-Datasheet_09-Jun-15
• RTOE: Response Time-out Error Interrupt Mask
• DCRCE: Data CRC Error Interrupt Mask
• DTOE: Data Time-out Error Interrupt Mask
• CSTOE: Completion Signal Time-out Error Interrupt Mask
• FIFOEMPTY: FIFO Empty Interrupt Mask
• XFRDONE: Transfer Done Interrupt Mask
• ACKRCV: Boot Operation Acknowledge Received Interrupt Mask
• ACKRCVE: Boot Operation Acknowledge Error Interrupt Mask
• OVRE: Overrun Interrupt Mask
• UNRE: Underrun Interrupt Mask
SAM4S Series [DATASHEET]
Atmel-11100K-ATARM-SAM4S-Datasheet_09-Jun-15
948
38.14.16HSMCI Configuration Register
Name: HSMCI_CFG
Address: 0x40000054
Access: Read/Write
This register can only be written if the WPEN bit is cleared in the HSMCI Write Protection Mode Register.
• FIFOMODE: HSMCI Internal FIFO control mode
0: A write transfer starts when a sufficient amount of data is written into the FIFO.
When the block length is greater than or equal to 3/4 of the HSMCI inter nal FIFO si ze, then the write transfer starts as soon
as half the FIFO is filled. When the block length is greater than or equal to half the internal FIFO size, then the write trans-
fer starts as soon as one quarter of the FIFO is filled. In other cases, the transfer starts as soon as the total amount of data
is written in the internal FIFO.
1: A write transfer starts as soon as one data is written into the FIFO.
• FERRCTRL: Flow Error flag reset control mode
0: When an underflow/overflow condition flag is set, a new Write/Read command is needed to reset the flag.
1: When an underflow/overflow condition flag is set, a read status resets the flag.
• HSMODE: High Speed Mode
0: Default bus timing mode.
1: If set to one, the host controller outputs command line and data lines on the rising edge of the card clock. The Host
driver shall check the high speed support in the card registers.
• LSYNC: Synchronize on the last block
0: The pending command is sent at the end of the current data block.
1: The pending command is sent at the end of the block transfer when the transfer length is not infinite (block count shall
be different from zero).
31 30 29 28 27 26 25 24
––––––––
23 22 21 20 19 18 17 16
––––––––
15 14 13 12 11 10 9 8
–––LSYNC–––HSMODE
76543210
– – – FERRCTRL – – – FIFOMODE
949
SAM4S Series [DATASHEET]
Atmel-11100K-ATARM-SAM4S-Datasheet_09-Jun-15
38.14.17HSMCI Write Protection Mode Register
Name: HSMCI_WPMR
Address: 0x400000E4
Access: Read/Write
• WPEN: Write Protec t En ab le
0: Disables the Write Protection if WPKEY corresponds to 0x4D4349 (“MCI” in ASCII).
1: Enables the Write Protection if WPKEY corresponds to 0x4D4349 (“MCI” in ASCII).
See Section 38.13 “Register Writ e Protection” for the list of registers that can be write-protected.
• WPKEY: Write Protect Key
31 30 29 28 27 26 25 24
WPKEY
23 22 21 20 19 18 17 16
WPKEY
15 14 13 12 11 10 9 8
WPKEY
76543210
–––––––WPEN
Value Name Description
0x4D4349 PASSWD Writing any other value in this field aborts the write operation of the WPEN bit.
Always reads as 0.
SAM4S Series [DATASHEET]
Atmel-11100K-ATARM-SAM4S-Datasheet_09-Jun-15
950
38.14.18HSMCI Write Protection Status Register
Name: HSMCI_WPSR
Address: 0x400000E8
Access: Read-only
• WPVS: Write Protection Violation Status
0: No write protec tion v iola tio n ha s occ u rred since the last read of the HSMCI_WPSR.
1: A write protection violation has occurred since the last read of the HSMCI_WPSR. If this violation is an unauthorized
attempt to write a protected register, the associated violation is reported into field WPVSRC.
• WPVSRC: Write Protection Violation Source
When WPVS = 1, WPVSRC indicates the register address offset at which a write access has been attempted.
31 30 29 28 27 26 25 24
––––––––
23 22 21 20 19 18 17 16
WPVSRC
15 14 13 12 11 10 9 8
WPVSRC
76543210
–––––––WPVS
951
SAM4S Series [DATASHEET]
Atmel-11100K-ATARM-SAM4S-Datasheet_09-Jun-15
38.14.19HSMCI FIFOx Memory Aperture
Name: HSMCI_FIFOx [x=0..255]
Address: 0x40000200
Access: Read/Write
• DATA: Data to Read or Data to Write
31 30 29 28 27 26 25 24
DATA
23 22 21 20 19 18 17 16
DATA
15 14 13 12 11 10 9 8
DATA
76543210
DATA
SAM4S Series [DATASHEET]
Atmel-11100K-ATARM-SAM4S-Datasheet_09-Jun-15
952
39. Pulse Width Modulation Controller (PWM)
39.1 Description
The Pulse Width Modulation Controller (PWM) generates output pulses on 4 channels independently according to
parameters defined per channel. Each channel controls two complementary square output waveforms.
Characteristics of the output waveforms such as period, duty-cycle, polarity and dead-times (also called dead-
bands or non-overlapping times) are configured through the user interface. Each channel selects and uses one of
the clocks provided by the clock generator. The clock generator provides several clocks resulting from the division
of the PWM peripheral clock.
All accesses to the PWM are made through registers mapped on the peripheral bus. All channels integrate a
double buffering system in order to prevent an unexpec ted output waveform while modifying the period, the duty-
cycle or the dead-times.
Channels can be linked together as synchronous channels to be able to update their duty-cycle or dead-times at
the same time.
The update of duty-cycles of synchronous channels can be performed by the Peripheral DMA Controller channel
which offers buffer transfer without processor Interven tio n .
The PWM provides 8 independent comparison units capable of compar ing a programmed value to the counter of
the synchronous channels (counter of channel 0). These comparisons are intended to generate software
interrupts, to trigger pulses on the 2 independe nt event lines (in order to synchronize ADC conversions with a lot of
flexibility independently of the PWM outputs) and to trigger Peripheral DMA Controllertransfer requests.
PWM outputs can be overridden synchronously or asynchronously to their channel counter.
The PWM provides a fault protection mech anism with 8 fault inputs, capable to detect a fault cond ition and to
override the PWM outputs asynchronously (outputs forced to ‘0’, ‘1’).
For safety usage, some configuration registers are write-protected.
953
SAM4S Series [DATASHEET]
Atmel-11100K-ATARM-SAM4S-Datasheet_09-Jun-15
39.2 Embedded Characteristics
4 Channels
Common Clock Generator Providing Thirteen Different Clocks
A Modulo n Counter Providing Eleven Clocks
Two Independent Linear Dividers Working on Modulo n Counter Outputs
Independent Channels
Independent 16-bit Counter for Each Channel
Independent Complementary Outputs with 12-bit Dead-Time Generator (Also Called Dead-Band or
Non-Overlapping Time) for Each Channel
Independent Enable Disable Command for Each Channel
Independent Clock Selection for Each Channel
Independent Period, Duty-Cycle and Dead-Time for Each Channel
Independent Double Buffering of Period, Duty-Cycle and Dead-Times for Each Channel
Independent Programmable Selection of The Output Waveform Polarity for Each Channel
Independent Programmable Center- or Left-aligned Output Waveform for Each Channel
Independent Output Override for Each Channel
Independent Interrupt for Each Channel, at Each Period for Left-Aligned or Center- Aligned
Configuration
2 2-bit Gray Up/Down Channels for Stepper Motor Control
Synchrono us Ch an ne l Mo de
Synchronous Channels Share the Same Counter
Mode to Update the Synchronous Channels Registers after a Programmable Number of Periods
Synchronous Chann els Supports Co nnection of one Periph eral DMA Controller Channel Which Of fers
Buffer Transfer Without Processor Intervention To Update Duty-Cycle Registers
2 Independent Events Lines Intended to Synchronize ADC Conversions
Programmable delay for Events Lines to delay ADC measurements
8 Comparison Units Intended to Generate Interrupts, Pulses on Event Lines and Peripheral DMA Controller
Transfer Requests
8 Programmable Fault Inputs Providing an Asynchronous Protection of PWM Outputs
3 User Driven through PIO Inputs
PMC Driven when Crystal Oscillator Clock Fails
ADC Controller Driven through Configurable Comparison Function
Analog Comparator Controller Driven
Timer/Counter Driven through Configurable Comparison Function
Register Write Protection
SAM4S Series [DATASHEET]
Atmel-11100K-ATARM-SAM4S-Datasheet_09-Jun-15
954
39.3 Block Diagram
39.4 I/O Lines Description
Each channel outputs two complementary external I/O lines.
39.5 Product Dependencies
39.5.1 I/O Lines
The pins used for inter f acing the PWM ar e m ultiplexe d with PIO line s. The progr amm er mu st first prog ra m the PIO
controller to assign the desired PWM pins to their peripheral function. If I/O lines of the PWM are not used by the
application, they can be used for other purposes by the PIO controller.
Figure 39-1. Pulse Width Modulation Controller Block Diagram
APB
ADC
Comparison
Units
Interrupt
Controller
Interrupt Generator
event line 0
event line 1
Events
Generator event line x
Comparator
Clock
Selector Counter
Channel 0
Duty-Cycle
Period
Update
APB
Interface
CLOCK
Generator
PIO
PMC
Dead-Time
Generator Output
Override Fault
Protection
PIO
Comparator Dead-Time
Generator Output
Override Fault
Protection
Counter
Channel x
Duty-Cycle
Period
Update
Clock
Selector
Channel x
OCx
DTOHx
DTOLx
OOOHx PWMHx
PWMLx
OOOLx
MUX
SYNCx
PWM Controller
Peripheral Clock
Channel 0
OC0
DTOH0
DTOL0
OOOH0 PWMH0
PWML0
OOOL0
PWMHx
PWMLx
PWMH0
PWML0
PWMFI0
PWMFIx
Table 39-1. I/O Line Description
Name Description Type
PWMHx PWM Waveform Output High for channel x Output
PWMLx PWM Waveform Output Low for channel x Output
PWMFIx PWM Fault Input x Input
955
SAM4S Series [DATASHEET]
Atmel-11100K-ATARM-SAM4S-Datasheet_09-Jun-15
All of the P WM outputs ma y or may not be enabled. If an application requires only four channels, then only four
PIO lines will be assigned to PWM outputs.
Table 39-2. I/O Lines
Instance Signal I/O Line Periphera l
PWM PWMFI0 PA9 C
PWM PWMFI1 PA10 C
PWM PWMFI2 PA18 D
PWM PWMH0 PA0 A
PWM PWMH0 PA11 B
PWM PWMH0 PA23 B
PWM PWMH0 PB0 A
PWM PWMH0 PC18 B
PWM PWMH1 PA1 A
PWM PWMH1 PA12 B
PWM PWMH1 PA24 B
PWM PWMH1 PB1 A
PWM PWMH1 PC19 B
PWM PWMH2 PA2 A
PWM PWMH2 PA13 B
PWM PWMH2 PA25 B
PWM PWMH2 PB4 B
PWM PWMH2 PC20 B
PWM PWMH3 PA7 B
PWM PWMH3 PA14 B
PWM PWMH3 PA17 C
PWM PWMH3 PB14 B
PWM PWMH3 PC21 B
PWM PWML0 PA19 B
PWM PWML0 PB5 B
PWM PWML0 PC0 B
PWM PWML0 PC13 B
PWM PWML1 PA20 B
PWM PWML1 PB12 A
PWM PWML1 PC1 B
PWM PWML1 PC15 B
PWM PWML2 PA16 C
PWM PWML2 PA30 A
PWM PWML2 PB13 A
PWM PWML2 PC2 B
SAM4S Series [DATASHEET]
Atmel-11100K-ATARM-SAM4S-Datasheet_09-Jun-15
956
39.5.2 Power Management
The PWM is not continuously clocked. The programmer must first enable the PWM clock in the Power
Management Controller (PMC) before using the PWM. However, if the application does not require PWM
operations, the PWM clock can be stopped when not ne eded and be restarted later. In this case, the PWM will
resume its operations where it left off.
39.5.3 Interrupt Sources
The PWM int errupt line is connec ted on one of the in ternal sources of the Interrupt Controller. Using the PWM
interrupt requires the Interrupt Controller to be programmed first.
39.5.4 Fault Inputs
The PWM has the fault inputs connected to the different modules. Please refer to the implementation of these
module within the product for detailed information about the fault generation procedure. The PWM receives faults
from PIO inputs, the PMC, the ADC controller, the Analog Comparator Controller and Timer/Counters.
Note: 1. FPOL field in PWMC_FMR.
PWM PWML3 PA15 C
PWM PWML3 PC3 B
PWM PWML3 PC22 B
Table 39-2. I/O Lines
Table 39-3. Peripheral IDs
Instance ID
PWM 31
Table 39-4. Fault Inputs
Fault Generator External PWM Fault Input Number Polarity Level(1) Fault Input ID
PA9 PWMFI0 User-defined 0
Main OSC (PMC) – To be configured to 1 1
ADC – To be configured to 1 2
Analog Comparator – To be con figured to 1 3
Time r0 – To be configured to 1 4
Time r1 – To be configured to 1 5
957
SAM4S Series [DATASHEET]
Atmel-11100K-ATARM-SAM4S-Datasheet_09-Jun-15
39.6 Functional Description
The PWM controller is primarily composed of a clock generator module an d 4 channels.
Clocked by the peripheral clock, the clock generator module provides 13 clocks.
Each channel can independently choose one of the clock generator outputs.
Each channel generates an output waveform with attributes that can be defined independently for each
channel through the user interface registers.
39.6.1 PWM Clock Generator
Figure 39-2. Functional View of the Clock Generator Block Diagram
The PWM peripheral clock is divided in the clock generator module to provide different clocks available for all
channels. Each channel can independently select one of the divided clocks.
The clock generator is divided into different blocks:
a modulo n counter which provides 11 clocks: fperipheral clock, fperipheral clock/2, fperipheral clock/4, fperipheral
clock/8, fperipheral clock/16, fperipheral cloc k/32, fperipheral clock/64, fperipheral clock/128, fperipheral clock/256, fperipheral
clock/512, fper ipheral clock/1024
two linear dividers (1, 1/2, 1/3, ... 1/255) that provide two separate clocks: clkA and clkB
Each linear divider can independently divide one of the clocks of the mod ulo n counte r. The selectio n of the cloc k
to be divided is made according to the PREA (PREB) field of the PWM Clock register (PWM_CLK). The resulting
clock clkA (clkB) is the clock selected divided by DIVA (DIVB) field value.
modulo n counter
peripheral clock/2
peripheral clock/4
peripheral clock/16
peripheral clock/32
peripheral clock/64
peripheral clock/8
Divider A clkA
DIVA
PWM_MR
peripheral clock
peripheral clock/128
peripheral clock/256
peripheral clock/512
peripheral clock/1024
PREA
Divider B clkB
DIVB
PWM_MR
PREB
Peripheral Clock
SAM4S Series [DATASHEET]
Atmel-11100K-ATARM-SAM4S-Datasheet_09-Jun-15
958
After a reset of the PWM controller, DIVA (DIVB) and PREA (PREB) are set to ‘0’. This implies that after reset clkA
(clkB) are turned off.
At reset, all clocks provided by the modulo n counter are turned off except the peripheral clock. This situation is
also true when the PWM peripheral clock is turned off through the Power Management Controller.
CAUTION:
Before using the PWM contr oller, the programmer mu st fi rst enable the perip heral clock in the Power Management
Controller (PMC).
39.6.2 PWM Channel
39.6.2.1 Channel Block Diagram
Figure 39-3. Functional View of the Channel Block Diagram
Each of the 4 channels is composed of six blocks:
A clock selector which selects one o f the clocks provided by the clock genera tor (described in Section 39.6.1
“PWM Clock Generator”).
A counter clocked by the output of the clock se lector . This co unter is incremented or decremen ted according
to the channel configuration and comparators matches. The size of the counter is 16 bits.
A comparator used to compute the OCx output waveform according to the counter value and the
configuration. The counter value can be the one of the channel counter or the one of the channel 0 counter
according to SYNCx bit in the PWM Sync Channels Mode Register (PWM_SCM).
A 2-bit configurable gray counter enables the stepper motor driver. One gray counter drives 2 channels.
A dead-time generator providing two complementary outputs (DTOHx/DTOLx) which allows to drive external
power control switches safely.
An output override block that can force the two complementary outputs to a programmed value
(OOOHx/OOOLx).
An asynchronous fault protection mechanism that has the highest priority to override the two complementary
outputs (PWMHx/PWMLx) in case of fault detection (outputs forced to ‘0’, ‘1’).
Comparator
x
Clock
Selector
Channel x
Dead-Time
Generator
Output
Override
OCx
DTOHx
DTOLx
Fault
Protection
OOOHx PWMHx
PWMLx
OOOLx
Counter
Channel x
Duty-Cycle
Period
Update
Counter
Channel 0
MUX SYNCx
Dead-Time
Generator
Output
Override
OCy
DTOHy
DTOLy
Fault
Protection
OOOHy PWMHy
PWMLy
OOOLy
Channel y (= x+1)
MUX MUX
2-bit gray
counter z
Comparator
y
from
Clock
Generator
from APB
Peripheral Bus
z = 0 (x = 0, y = 1),
z = 1 (x = 2, y = 3),
z = 2 (x = 4, y = 5),
z = 3 (x = 6, y = 7)
959
SAM4S Series [DATASHEET]
Atmel-11100K-ATARM-SAM4S-Datasheet_09-Jun-15
39.6.2.2 Comparator
The comparator continuously compares its counter value with the channel period defined by CPRD in the PWM
Channel Period Register (PWM_CPRDx) and the duty-cycle defined by CDTY in the PWM Channel Duty Cycle
Register (PWM_CDTYx) to generate an output signal OCx accordingly.
The different properties of the waveform of the output OCx are:
the clock selection. The channel counter is clocked by one of the clocks provided by the clock generator
described in the previous section. Th is channel parameter is defined in the CPRE field of the PWM Channel
Mode Register (PWM_CMRx). This field is reset at ‘0’.
the waveform period. This channel parameter is define d in th e CPRD field of the PWM _C PRDx register.
If the waveform is left-aligned, then the output waveform period depends on the counter source clock and
can be calculated:
By using the PWM peri pheral clock divided by an X given prescaler val ue (with X being 1, 2, 4, 8, 16, 32, 64,
128, 256, 512, or 1024), the result ing period formula will be :
By using the PWM peripheral clock divided by one of both DIVA or DIVB divider, the formula becomes,
respectively:
or
If the waveform is center-align ed then the output wave form per iod depend s on the counter source clock and
can be calculated:
By using the PWM peripheral clock divided by an X given prescaler value
(with X being 1, 2, 4, 8, 16, 32, 64, 128, 256, 512, or 1024). The resulting period formula will be:
By using the PWM peripheral clock divided by one of both DIVA or DIVB divider, the formula becomes,
respectively:
or
the waveform duty-cycle. This channel parameter is defined in the CDTY field of the PWM_CDTYx
register.
If the waveform is left-aligned then:
If the waveform is center-aligned, then:
the waveform polarity. At the beginning of the period, the sign al can be at high or low level. This prop erty is
defined in the CPOL bit of the PWM_CMRx. By default the signal starts by a low level. the waveform
XCPRD×()
fperipheral clock
--------------------------------
XC×RPD DIVA×()
fperipheral clock
----------------------------------------------------
XC×RPD DIVB×()
fperipheral clock
----------------------------------------------------
2XCPRD××()
fperipheral clock
----------------------------------------
2XC×PRD DIVA××()
fperipheral clock
-------------------------------------------------------------
2XC×PRD×DIVB×()
fperipheral clock
-------------------------------------------------------------
duty cycle period 1 fchannel_x_clock CDTY×⁄–()
period
----------------------------------------------------------------------------------------------------
=
duty cycle period 2⁄()1 fchannel_x_clock CDTY×⁄–())
period 2⁄()
-------------------------------------------------------------------------------------------------------------------
=
SAM4S Series [DATASHEET]
Atmel-11100K-ATARM-SAM4S-Datasheet_09-Jun-15
960
alignment. The output waveform can be left or center-aligned. Center-aligned waveforms can be used to
generate non-overlapped waveforms. This property is defined in the CALG bit of the PWM_CMRx. The
default mode is left-aligned.
Figure 39-4. Non-Overlapped Center-Aligned Waveforms
Note: 1. See Figure 39-5 for a detailed description of center-aligned waveforms.
When center-aligned, the channel counter increases up to CPRD and decreases down to 0. This ends the period.
When left-aligned, the channel counter increases up to CPRD and is reset. This ends the period.
Thus, for the same CPRD value, the period for a center-aligned channel is twice the period for a left-aligned
channel.
Waveforms are fixed at 0 when:
CDTY = CPRD and CPOL = 0
CDTY = 0 and CPOL = 1
Waveforms are fixed at 1 (once the channel is enabled) when:
CDTY = 0 and CPOL = 0
CDTY = CPRD and CPOL = 1
The waveform polarity must be set befo re enabling the chan nel. This imme diately affects the ch annel output leve l.
Modifying CPOL in PWM Channel Mode Register while the channel is enabled can lead to an unexpected
behavior of the device being driven by PWM.
In addition to generating the output signals OCx, the comparator generates interrupts depending on the counter
value. When the out put waveform is left-align ed, the interrupt occur s at the end of the counte r period. When the
output waveform is ce nter-alig ned, the bit CES o f PWM_CMRx define s when the chan nel counter inte rrupt occur s.
If CES is set to ‘0’, the inte rrupt occurs at the end of the counter period. If CES is set to ‘1’, the interrupt occurs at
the end of the counter period and at half of the counter period.
Figure 39-5 illustrates the counter interrupts depending on the configuration.
OC0
OC1
Period
No overlap
961
SAM4S Series [DATASHEET]
Atmel-11100K-ATARM-SAM4S-Datasheet_09-Jun-15
Figure 39-5. Waveform Properties
Channel x
slected clock
CHIDx(PWM_SR)
Center Aligned
CPRD(PWM_CPRDx)
CDTY(PWM_CDTYx)
PWM_CCNTx
Output Waveform OCx
CPOL(PWM_CMRx) = 0
Output Waveform OCx
CPOL(PWM_CMRx) = 1
Counter Event
CHIDx(PWM_ISR)
CES(PWM_CMRx) = 0
Left Aligned
CPRD(PWM_CPRDx)
CDTY(PWM_CDTYx)
PWM_CCNTx
Output Waveform OCx
CPOL(PWM_CMRx) = 0
Output Waveform OCx
CPOL(PWM_CMRx) = 1
CALG(PWM_CMRx) = 0
CALG(PWM_CMRx) = 1
Period
Period
CHIDx(PWM_ENA)
CHIDx(PWM_DIS)
Counter Event
CHIDx(PWM_ISR)
CES(PWM_CMRx) = 1
Counter Event
CHIDx(PWM_ISR)
SAM4S Series [DATASHEET]
Atmel-11100K-ATARM-SAM4S-Datasheet_09-Jun-15
962
39.6.2.3 2-bit Gray Up/Down Counter for Stepper Motor
A pair of channels may provide a 2-bit gray count waveform on two outputs. Dead-time generator and other
downstream logic can be configured on these channels.
Up or Down Count mode can be configured on-the-fly by means of PWM_SMMR configuration registers.
When GCEN0 is set to ‘1’, channels 0 and 1 outputs are driven with gray counter.
Figure 39-6. 2-bit Gray Up/Down Counter
39.6.2.4 Dead-Time Generator
The dead -ti me g ener ator us es th e c omp arat or ou tput OCx to provide the two complementary outputs DTOHx and
DTOLx, which allows the PWM macrocell to drive external power control switches safely. When the dead-time
generator is enabled by setting the bit DTE to 1 or 0 in the PWM Channel Mode Register (P WM_CMRx), dead-
times (also called dead-bands or non-overlapping times) are inserted between the edges of the two
complementary outputs DTOHx and DTOLx. Note that enabling or disabling the dead-time generator is allowed
only if the channel is disabled.
The dead-time is adjustable by the PWM Channel Dead Time Register ( PWM_DTx). Both out puts of the dead-tim e
generator can be adjusted separately by DTH and DTL. The dea d-time values can be updated synchronously to
the PWM period by using the PWM Channel Dead Time Update Register (PWM_DTUPDx).
The dead-time is based on a specific counter which uses the same selected clock that feeds the channel counter
of the comparator. Depending on the edge and the configuration of the dead-time, DTOHx and DTOLx are delayed
until the counter has r ea ched the va lue d efined b y DTH o r DTL. An inverted configuration bit (DTHI an d DTLI b it in
the PWM_CMRx) is provided for each output to invert the dead-time outputs. The follo wing figure shows the
waveform of th e de ad - tim e ge ne ra to r .
PWMH0
DOWNx
GCEN0 = 1
PWMH1
PWML0
PWML1
963
SAM4S Series [DATASHEET]
Atmel-11100K-ATARM-SAM4S-Datasheet_09-Jun-15
Figure 39-7. Complementary Output Waveforms
39.6.2.5 Output Override
The two complementary outputs DTOHx and DTOLx of the dead-time generator can be forced to a value defined
by the software.
DTHx DTLx
Output waveform OCx
CPOLx = 0
Output waveform DTOHx
DTHIx = 0
Output waveform DTOLx
DTLIx = 0
Output waveform DTOHx
DTHIx = 1
Output waveform DTOLx
DTLIx = 1
DTHx DTLx
Output waveform OCx
CPOLx = 1
Output waveform DTOHx
DTHIx = 0
Output waveform DTOLx
DTLIx = 0
Output waveform DTOHx
DTHIx = 1
Output waveform DTOLx
DTLIx = 1
SAM4S Series [DATASHEET]
Atmel-11100K-ATARM-SAM4S-Datasheet_09-Jun-15
964
Figure 39-8. Override Output Selection
The fields O SHx and OSL x in the PWM Output Selection Register (PWM_OS) allow the outputs of the dead-time
generator DTOHx and DTOLx to be overridden by the value defined in the fields OOVHx and OOVLx in the PWM
Output Override Value Register (PWM_OOV).
The set registers PWM Output Selection Set Register (PWM_OSS) and PWM Output Selection Set Update
Register (PWM_OSSUPD) enable the ove rride of the outputs of a channel regardless of other channels. In the
same way, the clear registers PWM Output Selection Clear Register (PWM_OSC) and PWM Output Selection
Clear Update Register (PWM_OSCUPD) disable the override of the outputs of a channel regardless of other
channels.
By using buffer registers PWM_OSSUPD an d PWM_OSCUPD, the output selection of PWM outputs is done
synchronously to the channel counter, at the beginning of the next PWM period.
By using registers PWM_OSS and PWM_OSC, the output selection of PWM outputs is done asynchronously to
the channel counter, as soon as the register is written.
The value of the current output selection can be read in PWM_OS.
While overriding PWM outputs, the channel coun ters continue to run, only the PWM outputs are forced to user
defined values.
DTOHx
OOVHx
OOOHx
OSHx
0
1
DTOLx
OOVLx
OOOLx
OSLx
0
1
965
SAM4S Series [DATASHEET]
Atmel-11100K-ATARM-SAM4S-Datasheet_09-Jun-15
39.6.2.6 Fault Protection
8 inputs provide fault protection which can force any of the PWM output pairs to a programmable value. This
mechanism has priority over output overriding.
The polarity level of the fault inputs is configured by the FPOL field in the PWM Fault Mode Register (PWM_FMR).
For fault inputs coming from internal peripherals such as ADC or Timer Counter, the polarity level must be FPOL =
1. For fault inputs coming from external GPIO pins the polarity level depends on the user's implementation.
The configuration of the Fault Activation mode (FMOD field in PWMC_F MR) dep ends on the p eri phera l gene ratin g
the fault. If the corr esponding peripher al does not have “Fault Clear” management, then the FMOD configuration to
use must be FMOD = 1, to avoid spurious fault detection. Refer to the corresponding peripheral documentation for
details on handling fault generation.
Fault inputs may or may not be glitch-filtered depending on the FFIL field in the PWM_FMR. When the filter is
activated, glitches on fault inputs with a width inferior to the PWM peripheral clock period are rejected.
A fault becomes active as soon as its corr esponding fault input has a transition to the prog ramme d po larity level. If
the corres ponding bit F MOD is set to ‘0’ in the PWM_FMR, the fault remains active as long as the fault input is at
this polarity level. If the corresponding FMOD field is set to ‘1’, the fault remains active until the fault input is no
longer at this polarity level and until it is cleared by writing the correspond ing bit FCLR in the PWM Fault Clear
Register (PWM_FCR). In the PWM Fault Status Register (PWM_FSR), the field FIV indicates the current level of
the fault inputs and the field FIS indicates whether a fault is currently active.
Each fault can be taken into account or not by the fault protection mechanism in each channel. To b e taken into
account in the channel x, the fault y must be enabled by the bit FPEx[y] in the PWM Fault Protection Enable
registers (PWM_FPE1). However, synchronous channels (see Section 39.6.2.7 “Synchronous Channels”) do not
use their own fault enable bits, but those of the channel 0 (bits FPE0[y]).
The fault protection on a channel is trig gered whe n this channe l is en abled a nd when any o ne of th e fau lts th at are
enabled for this channel is active. It can be triggered even if the PWM peripheral clock is n ot run ni ng bu t on ly by a
fault input that is not glitch-filtered.
When the fault protection is triggered on a channel, the fault protection mechanism resets the counter of this
channel and force s the channel outputs to the values defined by th e fields FPVHx and FPVLx in the PWM Fault
Protection Value Register (PWM_FPV) . The output forcing is made asynchronously to the channel counter.
CAUTION:
To prevent any unexpected activation of the status flag FSy in the PWM_FSR, the FMODy bit can be set to
‘1’ only if the FPOLy bit has been previously configured to its final value.
Figure 39-9. Fault Protection
FIV0
fault input 0
Fault protection
on PWM
channel x
Glitch
Filter
FFIL0
from fault 0
from fault y
1
0
=
FPOL0 FMOD0
1
0Fault 0 Status
FS0
FIV1
Glitch
Filter
FFIL1
1
0
=
FPOL1
SET
CLR
FMOD1
1
0
OUT
Fault 1 Status
FS1
fault input 1 from fault 1 1
0
0
1
From Output
Override
OOHx
OOLx
From Output
Override
FPVHx
FPVLx
PWMHx
PWMLx
fault input y
FMOD1
SET
CLR
Write FCLR0 at 1
OUT
FMOD0
Write FCLR1 at 1
SYNCx
1
0
FPEx[0]
FPE0[0]
SYNCx
1
0
FPEx[1]
FPE0[1]
SAM4S Series [DATASHEET]
Atmel-11100K-ATARM-SAM4S-Datasheet_09-Jun-15
966
To prevent any unexpected activation of the Fault Protection on the channel x, the bit FPEx[y] can be set to
‘1’ only if the FPOLy bit has been previously configured to its final value.
If a comparison unit is e nabled (see Section 39.6.3 “PWM Comparison Units”) and if a fault is triggered in the
channel 0, then the comparison cannot match.
As soon as th e fault p rotect ion is trig gered on a chan nel, an interrupt (different from the interrupt generated at the
end of the PWM period) can be generate d but only if it is ena bled and not masked. The interrupt is rese t by reading
the interrupt status register, even if the fault which has caused the trigger of the fault protection is kept active.
39.6.2.7 Synchronous Channels
Some channels can be linked together as synchronous channels. They have the same source clock, the same
period, the same alignment and are started together. In this way, their counters are syn chronized together.
The synchronous channels are defined by the SYNCx bits in the PWM Sync Channels Mode Register
(PWM_SCM). Only one group of synchronous channels is allowed.
When a channel is defined as a synchronous channel, the channel 0 is also automatically defined as a
synchronous channel. This is because the channel 0 counter configuration is used by all the synchronous
channels.
If a channel x is defined as a synchronous channel, the fields /bits for the channel 0 are used instead of those of
channel x:
CPRE in PWM_CMR0 instead of CPRE in PWM_CMRx (same source clock)
CPRD in PWM_CPRD0 instead of CPRD in PWM_CPRDx (same period)
CALG in PWM_CMR0 instead of CALG in PWM_CMRx (same alignment)
Modifying the fields CPRE, CPRD and CALG of for channels with index greater than 0 has no effect on output
waveforms.
Because counters of synchronous channels must start at the same time, they are all enabled together by enabling
the channel 0 (by the CHID0 bit in PWM_ENA register). In the same way, they are all disabled together by
disabling channel 0 (b y the CHID0 bit in PWM_DIS register). However, a synchronous chan nel x different from
channel 0 can be enabled or disabled independently from others (by the CHIDx bit in PWM_ENA and PWM_DIS
registers).
Defining a channel as a synchronous channel while it is an asynchronous channel (by writing the bit SYNCx to ‘1’
while it was at ‘0’) is allowed only if the channel is disabled at this time (CHIDx = 0 in PWM_SR). In the same way,
defining a channel as an asynchronous channel while it is a synch ronous chann el (by writing the SYNCx bit to ‘0’
while it was ‘1’) is allowed only if the channel is disable d at this time.
The UPDM field (Update Mode) in the PWM_SCM register selects one of the three methods to update the
registers of the synchronous channels:
Method 1 (UPDM = 0): The period value, the duty-cycle values and the dead-time values must be written by
the processor in their respective update registers (respectively PWM_CPRDUPDx, PWM_CDTYUPDx and
PWM_DTUPDx).The update is trigg ered at the next PWM period as soon as the bit UPDULOCK in the PWM
Sync Channels Update Control Register (PWM_SCUC) is set to ‘1’ (see “Method 1: Manual write of duty-
cycle values and manual trigger of the update” ).
Method 2 (UPDM = 1 ): The per iod valu e, the du ty- cycle va lue s, the d ead-time valu es an d the upd ate per iod
value must be written by the processor in their respective update registers (respectively PWM_CPRDUPDx,
PWM_CDTYUPDx and PWM_DTUPD). The update of the period value and of the dead-time values is
triggered at the next PWM period as soon as the bit UPDULOCK in the PWM_SCUC register is set to ‘1’.
The update of the duty-cycle values and the update period value is triggered automatically after an update
period defined by the field UPR in the PWM Sync Channels Update Period Register (PWM_SCUP) (see
“Method 2: Manual write of duty-cycle valu es and automatic trigger of the update” ).
967
SAM4S Series [DATASHEET]
Atmel-11100K-ATARM-SAM4S-Datasheet_09-Jun-15
Method 3 (UPDM = 2): Same as Method 2 apart from the fact that the duty-cycle values of ALL synchronous
channels are written by the Peripheral DMA Controller (see “Method 3: Automatic write of duty-cycle values
and automatic trigger of the update” ). The user can choose to synchronize the Peripheral DMA Controller
transfer request with a comparison match (see Section 39.6.3 “PWM Comparison Units”), by the fields
PTRM and PTRCS in the PWM_SCM register.
Method 1: Manual write of duty-cycle values and manual trigger of the update
In this mode, the update of the period value, the duty-cycle values and the dead-time values must be done by
writing in their respective update registers with the processor (respectively PWM_CPRDUPDx, PWM_CDTYUPDx
and PWM_DTUPDx).
To trigger the update, the user must use the bit UPDULOCK in the PWM_SCUC register which allows to update
synchronously (at the same PWM period) the synchronous channels:
If the bit UPDULOCK is set to ‘1’, the update is don e at the ne xt PWM pe rio d of th e syn ch rono u s chann e l s.
If the UPDULOCK bit is not set to ‘1’, the update is locked and cannot be performed.
After writing the UPDULOCK bit to ‘1’, it is held at this value until the update occurs, then it is read 0.
Sequence for Method 1:
1. Select the manual write of duty-cycle v alues and the man ual updat e b y setting the UPDM field to ‘0’ in t he
PWM_SCM register
2. Define the synchronous channels by the SYNCx bits in the PWM_SCM register.
3. Enable the synchronous channels by writing CHID0 in the PWM_ENA register.
4. If an update of the period value and/or the duty-cycle values and/or the dead-time values is required, write
registers that need to be updated (PWM_CPRDUPDx, PWM_CDTYUPDx and PWM_DTUPDx).
5. Set UPDULOCK to ‘1’ in PWM_SCUC.
6. The update of the registers will occur at the beginning of the next PWM period. When the UPDULOCK bit is
reset, go to Step 4. for new values.
Table 39-5. Summary of the Update of Registers of Synchronous Channel s
Register UPDM = 0 UPDM = 1 UPDM = 2
Period Value
(PWM_CPRDUPDx)
Write by the processor
Update is triggered at the next PWM period as soon as the bit UPDULOCK is set to ‘1’
Dead-Time Values
(PWM_DTUPDx) Write by the processor
Update is triggered at the next PWM period as soon as the bit UPDULOCK is set to ‘1’
Duty-Cycle Values
(PWM_CDTYUPDx)
Write by the processor Write by the processor Write by the Peripheral DMA
Controller
Update is triggered at the next
PWM period as soon as the bit
UPDULOCK is set to ‘1’
Update is triggered at the next PWM perio d as soon as the update
period counter has reached the value UPR
Update Period Value
(PWM_SCUPUPD)
Not applicable Write by the processor
Not applicable Update is triggered at the next PWM period as soon as the upda te
period counter has reached the value UPR
SAM4S Series [DATASHEET]
Atmel-11100K-ATARM-SAM4S-Datasheet_09-Jun-15
968
Figure 39-10. Metho d 1 (UPDM = 0)
Method 2: Manual write of duty-cycle values and automatic trigger of the update
In this mode, the update of the period value, the duty-cycle values, the dead-time values and the update period
value must be done by writing in their respective update registers with the processor (respectively
PWM_CPRDUPDx, PWM_CDTYUPDx, PWM_DTUPDx and PWM_SCUPUPD).
To trigger the update of the period value and the dead-time values, the user must use the bit UPDULOCK in the
PWM_SCUC register, which updates synchronously (at the same PWM period) the synchronous channels:
If the bit UPDULOCK is set to ‘1’, the update is don e at the ne xt PWM pe rio d of th e syn ch rono u s chann e l s.
If the UPDULOCK bit is not set to ‘1’, the update is locked and cannot be performed.
After writing the UPDULOCK bit to ‘1’, it is held at this value until the update occurs, then it is read 0.
The update of the duty-cycle values and the update period is triggered automatically after an update period.
To configure the automatic update, the user must de fine a value for the update period by the UPR field in the
PWM_SCUP register. The PWM controller waits UPR+1 period of synchronous channels before updating
automatically the duty values and the update period value.
The status of the duty-cycle value write is reported in the PWM Interrupt Status Register 2 (PWM_ISR2) by the
following flags:
WRDY: this flag is set to ‘1’ when the PWM Controller is ready to receive new duty-cycle values and a new
update period value. It is reset to ‘0’ when the PWM_ISR2 register is read.
Depending on the interrupt mask in the PWM Interrupt Mask Register 2 (PWM_IMR2), an interrupt can be
generated by these flags.
Sequence for Method 2:
1. Select the manual write of duty-cycle values and the automatic update by setting the field UPDM to ‘1’ in
the PWM_SCM register
2. Define the synchronous channels by the bits SYNCx in the PWM_SCM register.
3. Define the update period by the fi eld UPR in the P WM_SC UP register.
4. Enable the synchronous channels by writing CHID0 in the PWM_ENA register.
5. If an update of the period value and/or of the dead-time values is required, write registers that need to be
updated (PWM_CPRDUPDx, PWM_DTUPDx), else go to Step 8.
6. Set UPDULOCK to ‘1’ in PWM_SCUC.
7. The update of these registers will occur at the beginning of the next PWM period. At this moment the bit
UPDULOCK is reset, go to Step 5. for new value s.
8. If an update of the duty-cycle values and/or the update period is required, check first that write of new update
values is possible by polling the flag WRDY (or by waiting for the corresponding interrupt) in the PWM_ISR2.
9. Write registers that need to be updated (PWM_CDTYUPDx, PWM_SCUPUPD).
CCNT0
CDTYUPD 0x20 0x40 0x60
UPDULOCK
CDTY 0x20 0x40 0x60
969
SAM4S Series [DATASHEET]
Atmel-11100K-ATARM-SAM4S-Datasheet_09-Jun-15
10. The update of these registers will occur at the next PWM period of the synchronous channels when the
Update Period is elapsed. Go to Step 8. for new values.
Figure 39-11. Method 2 (UPDM = 1)
Method 3: Automatic write of duty-cycle values and automatic trigger of the update
In this mode, the update of the duty cycle v alues is made automatica lly by the Peripheral DMA Con troller. The
update of the period value, the dead-time values and the update period value must be done by writing in their
respective update registers with the processor (respectively PWM_CPRDUPDx, PWM_DTUPDx and
PWM_SCUPUPD).
To trigger the update of the period value and the dead-time values, the user must use the bit UPDULOCK which
allows to update synchronously (at the same PWM period) the synchronous channels:
If the bit UPDULOCK is set to ‘1’, the update is don e at the ne xt PWM pe rio d of th e syn ch rono u s chann e l s.
If the UPDULOCK bit is not set to ‘1’, the update is locked and cannot be performed.
After writing the UPDULOCK bit to ‘1’, it is held at this value until the update occurs, then it is read 0.
The update of the duty-cycle values and the update period value is triggered automatically after an update period.
To configure the automatic update, the user must define a value for the Update Period by the field UPR in the
PWM_SCUP register. The PWM controller waits UPR+1 periods of synchronous channels before updating
automatically the duty values and the update period value.
Using the Perip h er al DMA Co n tro lle r re m ov es pr ocessor over head by reducing its intervention du ring the transfer.
This significantly reduces the number of clock cycles required for a data transfer, which improves microcontroller
performance.
The Peripheral DMA Controller must write the duty-cycle values in the synchronous channels index order. For
example if the channels 0, 1 and 3 are synchronous channels, the Peripheral DMA Controller must write the duty-
cycle of the channel 0 first, then the duty-cycle of the channel 1, and finally the duty-cycle of the channel 3.
The status of the Peripheral DMA Controller transfer is reported in the PWM_ISR2 by the following flags:
WRDY: this flag is set to ‘1’ when the PWM Controller is ready to receive new duty-cycle values and a new
update period value. It is reset to ‘0’ when the PWM_ISR2 is read. The user can choose to synchronize the
WRDY flag and the Peripheral DMA Controller transfer request with a comparison match (see Section
39.6.3 “PWM Comparison Units”), by the fields PTRM and PTRCS in the PWM_SCM register.
ENDTX : this flag is set to ‘1’ w hen a PDC transfer is completed
TXBUFE : this flag is set to ‘1’ when the PDC buffer is empty (no pending PDC transfers)
CCNT0
CDTYUPD 0x20 0x40 0x60
UPRCNT 0x0 0x1 0x0 0x1 0x0 0x1
CDTY 0x20 0x40
UPRUPD 0x1 0x3
WRDY
0x60
0x0 0x1 0x2 0x3 0x0 0x1 0x2
UPR 0x1 0x3
SAM4S Series [DATASHEET]
Atmel-11100K-ATARM-SAM4S-Datasheet_09-Jun-15
970
UNRE: this flag is set to ‘1’ when the update period defined by the UPR field has elapsed while the whole
data has not been written by the Peripheral DMA Controller. It is reset to ‘0’ when the PWM_ISR2 is read.
Depending on the interrupt mask in the PWM_IMR2, an interrupt can be generated by these flags.
Sequence for Method 3:
1. Select the automatic write of du ty-cycle v alues an d automatic u pdate b y setting the field UPDM t o 2 in the
PWM_SCM register.
2. Define the synchronous channels by the bits SYNCx in the PWM_SCM register.
3. Define the update period by the fi eld UPR in the P WM_SC UP register.
4. Define when the WRDY flag and the corresponding Peripheral DMA Controller transfer request must be set
in the update period by the PTRM bit and the PTRCS field in the PWM_SCM register (at the end of the
update period or when a comparison matches).
5. Define the Peripheral DMA Controller transfer settings for the duty-cycle values and enable it in the
Peripheral DMA Controller registers
6. Enable the synchronous channels by writing CHID0 in the PWM_ENA register.
7. If an update of the period value and/or of the dead-time values is required, write registers that need to be
updated (PWM_CPRDUPDx, PWM_DTUPDx), else go to Step 10.
8. Set UPDULOCK to ‘1’ in PWM_SCUC.
9. The update of these registers will occur at the beginning of the next PWM period. At this moment the bit
UPDULOCK is reset, go to Step 7. for new value s.
10. If an update of the update p eriod value is r equired, check fir st that write of a new update value is possible by
polling the flag WRDY (or by waiting for the corresponding interrupt) in the PWM_ISR2, else go to Step 13.
11. Write the register that needs to be updated (PWM_SCUPUPD).
12. The update of this register will occur at the next PWM period of the synchronous channels when the Update
Period is elapsed. Go to Step 10. for new values.
13. Check the end of the PDC tr an sfer by th e fla g ENDTX. If the tran sfer h as ende d, d efine a new PDC tr ansfer
in the PDC registers for new duty-cycle values. Go to Step 5.
Figure 39-1 2. Method 3 (UPDM = 2 and PTRM = 0)
CCNT0
CDTYUPD 0x20 0x40 0x60
UPRCNT 0x0 0x1 0x0 0x1 0x0 0x1
CDTY
UPRUPD 0x1 0x3
transfer request
WRDY
0x0 0x1 0x2 0x3 0x0 0x1 0x2
UPR 0x1 0x3
0x80 0xA0 0xB0
0x20 0x40 0x60 0x80 0xA0
971
SAM4S Series [DATASHEET]
Atmel-11100K-ATARM-SAM4S-Datasheet_09-Jun-15
Figure 39-1 3. Method 3 (UPDM = 2 and PTRM = 1 and PTR C S = 0)
39.6.3 PWM Comparison Units
The PWM provides 8 independent co mparison units able to co mpare a pr ogrammed va lue with the curren t value of
the channel 0 counter (which is the channel counter of all synchronous channels, Section 39.6.2.7 “Synchronous
Channels”). These comparisons are intended to generate pulses on the event lines (used to synchronize ADC, see
Section 39.6.4 “PWM Event Lines”), to generate software interrupts and to trigger Peripheral DMA Controller
transfer requests for the synchronous channels (see “Method 3: Automatic write of duty-cycle values and
automatic trigger of the update” ).
Figure 39-14. Comparison Unit Block Diagram
The comparison x matches when it is enabled by the bit CEN in the PWM Comparison x Mode Register
(PWM_CMPMx for the comparison x) and when the counter of the channel 0 reaches the comparison value
defined by the field CV in PWM Compar ison x Value Register (PWM_CMPVx for the comparison x). If the c ounter
CCNT0
CDTYUPD 0x20 0x40 0x60
UPRCNT 0x0 0x1 0x0 0x1 0x0 0x1
CDTY
UPRUPD 0x1 0x3
CMP0 match
transfer request
WRDY
0x0 0x1 0x2 0x3 0x0 0x1 0x2
UPR 0x1 0x3
0x80 0xA0 0xB0
0x20 0x40 0x60 0x80 0xA0
=
fault on channel 0
CNT [PWM_CCNT0]
CNT [PWM_CCNT0] is decrementing
CALG [PWM_CMR0]
CV [PWM_CMPVx]
=1
0
1
Comparison x
CVM [PWM_CMPVx]
=
CPRCNT [PWM_CMPMx]
CTR [PWM_CMPMx]
CEN [PWM_CMPMx]
SAM4S Series [DATASHEET]
Atmel-11100K-ATARM-SAM4S-Datasheet_09-Jun-15
972
of the channel 0 is ce nter-aligned (CALG = 1 in PWM Channel Mode Register), the bit CVM in PWM_CMPVx
defines if the co mparison is made when the coun ter is counting up or counting do wn (in Left-alignment mode
CALG = 0, this bit is useless).
If a fault is active on the channel 0, the comparison is disabled and cannot match (see Section 39.6.2.6 “Fault
Protection”).
The user can define the periodicity of the comparison x by the fields CTR and CPR in PWM_CMPMx. The
comparison is performed periodically o nce every CPR+1 peri ods of the counter of the ch annel 0, when the value of
the comparison period counter CPRCNT in PWM_CMPMx reaches the value defined by CTR. CPR is the
maximum value of the comparison period counter CPRCNT. If CPR = CTR = 0, the comparison is performed at
each period of the counter of the channel 0.
The comparison x configuration can be modified while the channel 0 is enabled by using the PWM Comparison x
Mode Update Register (PWM_CMPMUPDx registers for the comparison x). In the same way, the comparison x
value can be modified while the channel 0 is enabled by using the PWM Comparis on x Value Update Register
(PWM_CMPVUPDx registers for the comparison x).
The update of the comparison x configuration and the comparison x value is triggered periodically after the
comparison x update period. It is defined by the field CUPR in the PWM_CMPMx. The compariso n unit has an
update period counter independent from the period counter to trigger this update. When the value of the
comparison update period counter CUPRCNT (in PWM_CMPMx) reaches the value defined by CUPR, the update
is triggered. The comparison x update period CUPR itself can be updated while the channel 0 is enabled by using
the PWM_CMPMUPDx register.
CAUTION: The write of PWM_CMPVUPDx must be followed by a write of PWM_CMPMUPDx.
The comparison match and the comparison update can be source of an interrupt, but only if it is enabled and not
masked. These interrupts can be enabled by the PWM Interrupt Enable Register 2 and disabled by the PWM
Interrupt Disable Register 2. The compa rison match interrupt and the comparison update interrup t are reset by
reading the PWM Interrupt Status Register 2.
973
SAM4S Series [DATASHEET]
Atmel-11100K-ATARM-SAM4S-Datasheet_09-Jun-15
Figure 39-15. Comparison Waveform
39.6.4 PWM Event Lines
The PWM provides 2 independent event lines intended to trigger actions in other peripherals (e.g., for the Analog-
to-Digital Converter (ADC)).
A pulse (one cycle of the peripheral clock) is generated on an event line, whe n at least one of the selected
comparisons is matching. The comparisons can be selected or unselected independently by the CSEL bits in the
PWM Event Line x Register (PWM_ELMRx for the Event Line x).
An example of event generation is provided in Figure 39-17.
CCNT0
CVUPD 0x6 0x2
CVMVUPD
CV 0x6 0x2
0x6
0x6
CVM
Comparison Update
CMPU
CTRUPD 0x1 0x2
CPR 0x1 0x3
0x0 0x1 0x0 0x1 0x0 0x1 0x2 0x3 0x0 0x1 0x2 0x3
CPRCNT
0x0 0x1 0x2 0x3 0x0 0x1 0x2
0x0
0x1 0x2 0x0 0x1
CUPRCNT
CPRUPD 0x1 0x3
CUPRUPD 0x3 0x2
CTR 0x1 0x2
CUPR 0x3 0x2
Comparison Match
CMPM
SAM4S Series [DATASHEET]
Atmel-11100K-ATARM-SAM4S-Datasheet_09-Jun-15
974
Figure 39-16. Event Line Block Diagram
Figure 39-17. Event Line Generation Waveform (Example)
39.6.5 PWM Controller Operations
39.6.5.1 Initialization
Before enabling the channels, they must be configured by the software application as described below:
Unlock User Interface by writing the WPCMD field in the PWM_WPCR.
Configuration of the clock generator (DIVA, PREA, DIVB, PREB in the PWM_CLK register if required).
Selection of the clock for each channel (CPRE field in PWM_CMRx)
Configuration of the waveform alignment for each channel (CALG field in PWM_CMRx)
Selection of the counter event selection (if CALG = 1) for each channel (CES field in PWM_CMRx)
Configuration of the output waveform polarity for each channel (CPOL bit in PWM_CMRx)
PULSE
GENERATOR Event Line x
CSEL0 (PWM_ELMRx)
CMPM0 (PWM_ISR2)
CSEL1 (PWM_ELMRx)
CMPM1 (PWM_ISR2)
CSEL2 (PWM_ELMRx)
CMPM2 (PWM_ISR2)
CSEL7 (PWM_ELMRx)
CMPM7 (PWM_ISR2)
CPRD(PWM_CPRD0)
CDTY(PWM_CDTY0)
PWM_CCNTx
Waveform OC2
CDTY(PWM_CDTY1)
CDTY(PWM_CDTY2)
Waveform OC1
Waveform OC0
CV (PWM_CMPV0)
CV (PWM_CMPV1)
Comparison
Unit 0 Output
PWM_CMPM0.CEN = 1
Comparison
Unit 1 Output
PWM_CMPM0.CEN = 1
Event Line 0
(trigger event for ADC)
PWM_ELMR0.CSEL0 = 1
PWM_ELMR0.CSEL1 = 1 configurable delay
PWM_CMPV0.CV configurable delay
PWM_CMPV1.CV
ADC conversion ADC conversion
975
SAM4S Series [DATASHEET]
Atmel-11100K-ATARM-SAM4S-Datasheet_09-Jun-15
Configuration of the pe riod for each chan nel (CPRD in the PWM_CPRDx register). W r iting in PWM_CPRDx
register is possible while the channel is disabled. After validation of the channel, the user must use
PWM_CPRDUPDx register to update PWM_CPRDx as explained below.
Configuration of the duty-cycle for each channel (CDTY in the PWM_CDTYx register). Writing in
PWM_CDTYx register is possible while the channel is disabled. After validation of the channel, the user
must use PWM_CDTYUPDx register to update PWM_CDTYx as explained below.
Configuration of the de ad-time gene rator for e ach chan nel (DTH and DTL in PWM_DTx) if enab led (DTE bi t
in the PWM_CMRx). Writing in the PWM_DTx register is possible while the channel is disabled. After
validation of the channel, the user must use PWM_D TU PDx re gis te r to up date PW M_ DTx
Selection of the synchronous channels (SYNCx in the PWM_SCM register)
Selection of the moment when the WRDY flag and the corresponding Peripheral DMA Contr oller transfer
request are set (PTRM and PTRCS in the PWM_SCM register)
Configuration of the Update mode (UPDM in PWM_SCM register)
Configuration of the update period (UPR in PWM_SCUP register) if needed
Configuration of the comparisons (PWM_CMPVx and PWM_CMPMx)
Configuration of the event lines (PWM_ELMRx)
Configuration of the fault inputs polarity (FPOL in PWM_FMR)
Configuration of the fault protection (FMOD and FFIL in PWM_FMR, PWM_FPV and PWM_FPE1)
Enable of the interrupts (writing CHIDx and FCHIDx in PWM_IER1, and writing WRDYE, ENDTXE,
TXBUFE, UNRE, CMPMx and CMPUx in PWM_IER2)
Enable of the PWM channels (writing CHIDx in the PWM_ENA register)
39.6.5.2 Source Clock Selection Criteria
The large number of source clocks can make selection difficult. The relationship between the value in the PWM
Channel Period Register (PWM_CPRDx) and the PWM Channel Duty Cycle Register (PWM_CDTYx) helps the
user select the appropriate clock. The event number written in the Period Register gives the PWM accuracy. The
Duty-Cycle quantum cannot be lower than 1/CPRDx value. The higher the value of PWM_CPRDx, the greater the
PWM accuracy.
For example, if the user sets 15 (in decimal) in PWM_CPRDx, the user is able to set a value from between 1 up to
14 in PWM_CDTYx. The resulting duty-cycle quantum cannot be lower than 1/15 of the PWM period.
39.6.5.3 Changing the Duty-Cycle, the Period and the Dead-Times
It is possible to modulate the output waveform duty-cycle, period and dead-times.
To prevent unexpected output waveform, the user must use the PWM Channel Duty Cycle Update Register
(PWM_CDTYUPDx), the PWM Channel Period Update Register (PWM_CPRDUPDx) and the PWM Channel
Dead Time Update Register (PWM_DTUPDx) to change waveform parameters while the channel is still enabled.
If the channel is an asynchronous channel (SYNCx = 0 in PWM Sync Channels Mode Register
(PWM_SCM)), these registers hold the new period, duty-cycle and dead-times values until the end of the
current PWM period and update the values for the next period.
If the channel is a synchronous channel and update method 0 is selected (SYNCx = 1 and UPDM = 0 in
PWM_SCM regist er ), thes e re gisters hold the new period, duty-cycle and dead-times values until the bit
UPDULOCK is written at ‘1’ (in PWM Sync Channels Update Control Register (PWM_SC UC) ) and th e en d
of the current PWM period, then update the values for the next period.
If the channel is a synchronous chan nel and update method 1 or 2 is selected (SYNCx = 1 and UPDM = 1 or
2 in PWM_SCM register):
registers PWM_CPRDUPDx and PWM_DTUPDx hold the new period and dead-time s values until the
bit UPDULOCK is written at ‘1’ (in PWM_SCUC) and the e nd of the current PWM period, then update
the values for the next period.
SAM4S Series [DATASHEET]
Atmel-11100K-ATARM-SAM4S-Datasheet_09-Jun-15
976
register PWM_CDTYUPDx holds the new duty-cycle value until the end of the update period of
synchronous channels (when UPRCNT is equal to UPR in PWM Sync Channels Update Period
Register (PWM_SCUP)) and the end of the current PWM period, then updates the value for the next
period.
Note: If the update registers PWM_CDTYUPDx, PWM_CPRDUPDx and PWM_DTUPDx are written several times between
two updates, only the last written value is taken into account.
Figure 39-18. Sync hro nized Period, Duty-Cycle and Dea d-T ime Update
39.6.5.4 Changing the Update Period of Synchronous Channels
It is possible to change the update period of synchronous channels while they are enabled. See “Method 2:
Manual write of duty-cycle values and automatic trigger of the update” and “Method 3: Automatic write of duty-
cycle values and automatic trigger of the update” .
To prevent an unexpected update of the synchronou s channels registers, the user must us e the PWM Sync
Channels Update Period Update Register (PWM_SCUPUPD) to change the update period of synchronous
channels while they are still enabled. This register holds the new value until the end of the update period of
synchronous channels (when UPRCNT is equal to UPR in PWM_SCUP) and the end of the current PWM period,
then updates the value for the next period.
Note: If the update register PWM_SCUPUPD is written several times between two updates, only the last written value is
taken i nt o account.
Note: Changing the update period does make sense only if there is one or more synchronous channels and if the up date
method 1 or 2 is selected (UPDM = 1 or 2 in PWM Sync Channels Mode Register).
PWM_CPRDUPDx Value
PWM_CPRDx PWM_CDTYx
- If Asynchronous Channel
-> End of PWM period
- If Synchronous Channel
-> End of PWM period and UPDULOCK = 1
User's Writing
PWM_DTUPDx Value
User's Writing
PWM_DTx
- If Asynchronous Channel
-> End of PWM period
- If Synchronous Channel
- If UPDM = 0
-> End of PWM period and UPDULOCK = 1
- If UPDM = 1 or 2
-> End of PWM period and end of Update Period
PWM_CDTYUPDx Value
User's Writing
977
SAM4S Series [DATASHEET]
Atmel-11100K-ATARM-SAM4S-Datasheet_09-Jun-15
Figure 39-19. Synchronized Update of Update Period Value of Synchronous Channels
39.6.5.5 Changing the Comparison Value and the Comparison Configuration
It is possible to change the comparison values and the comparison configurations while the channel 0 is enabled
(see Section 39.6.3 “PWM Comparison Units”).
To prevent unexpected comparison match, the user must use the PWM Comparison x Value Update Register
(PWM_CMPVUPDx) and the PWM Comparison x Mode Update Register (PWM_CMPMUPDx) to change,
respectively, the comparison values and the comparison c onfigurations while the channel 0 is still enabled. These
registers hold the new valu es until the end of the comparison update period (when CUPRCNT is equal to CUPR in
PWM Comparison x Mode Register (PWM_CMPMx) and the end of the cur rent PWM period, then update the
values for the next pe rio d .
CAUTION: The write of the register PWM_CMPVUPDx must be followed by a write of the register
PWM_CMPMUPDx.
Note: If the update registers PWM_CMPVUPDx and PWM_CMPMUPDx are written several times between two updates,
only the last written value are taken into account.
End of PWM period and
end of update period
of synchronous channels
PWM_SCUPUPD Value
User's Writing
PWM_SCUP
SAM4S Series [DATASHEET]
Atmel-11100K-ATARM-SAM4S-Datasheet_09-Jun-15
978
Figure 39-20. Synchronized Upd ate of Compa rison Values a nd Configu rations
39.6.5.6 Interrupts
Depending on the interrupt mask in the PWM_IMR1 and PWM_IMR2, an interrupt can be generated at the end of
the corresponding channe l period (CHIDx in the PWM Interrupt Status Register 1 (PWM_ISR1)), after a fault event
(FCHIDx in the PWM_ISR1), after a comparison match (CMPMx in the PWM_ISR2), after a comparison update
(CMPUx in the PWM_ISR2) or according to the Transfer mode of the synchronous channels (WRDY, ENDTX,
TXBUFE and UNRE in the PWM_ISR2).
If the interrupt is generated by the flags CHIDx or FCHIDx, the interrupt remains active until a read operation in the
PWM_ISR1 occurs.
If the interrupt is generated by the flags WRDY or UNRE or CMPMx or CMPUx, the interrupt remains active until a
read operation in the PWM_ISR2 occurs.
A channel int errupt is enabled by setting t he corresponding bit i n PWM_IER1 and PWM_I ER2. A chan n el interrupt
is disabled by setting the corresponding bit in PWM_IDR1 and PWM _IDR2.
PWM_CMPVUPDx Value
Comparison value
for comparison x
User's Writing
PWM_CMPVx
End of channel0 PWM period and
end of comparison update period
PWM_CMPMUPDx Value
Comparison configuration
for comparison x
PWM_CMPMx
User's Writing
End of channel0 PWM period and
end of comparison update period and
and PWM_CMPMx written
979
SAM4S Series [DATASHEET]
Atmel-11100K-ATARM-SAM4S-Datasheet_09-Jun-15
39.6.6 Register Write Protection
To prevent any single softwar e error that may corrupt PWM behavio r, the registers listed below can be write-
protected by writing the field WPCMD in the PWM Write Protection Control Register (PWM_WPCR). They are
divided into six groups:
Register group 0:
PWM Clock Register
Register group 1:
PWM Disable Register
Register group 2:
PWM Sync Channels Mode Register
PWM Channel Mode Register
PWM Stepper Motor Mode Register
Register group 3:
PWM Channel Period Register
PWM Channel Period Update Register
Register group 4:
PWM Channel Dead Time Register
PWM Channel Dea d T ime Upd at e Register
Register group 5:
PWM Fault Mode Register
PWM Fault Protection Value Register
There are two ty pe s of write pro tection:
SW write protection—can be enabled or disabled by software
HW write protection—can be enabled by software but only disabled by a hardware reset of the PWM
controller
Both types of write protection can be app lied independ ently to a p articular register group by means of the WPCMD
and WPRGx fields in the PWM_WPCR. If at least one type of write protection is active, the register group is write-
protected. The value of field WPCMD defines the action to be pe rformed:
0: Disables SW write protection of the register group s of which the bit WPRGx is at ‘1’
1: Enables SW write protection of the register groups of wh ich the bit WPRGx is at ‘1’
2: Enables HW write protection of the register groups of which the bit WPRGx is at ‘1’
At any time, the user can determine whether SW or HW write protection is active in a particular register group by
the fields WPSWS and WPHWS in the PWM Write Protection Status Register (PWM_WPSR).
If a write access to a write-protected register is detected, the WPVS flag in the PWM_WPSR is set and the field
WPVSRC indicates the register in which the write access has been attempted.
The WPVS and WPVSRC fields are automatically cleared after reading the PWM_WPSR.
SAM4S Series [DATASHEET]
Atmel-11100K-ATARM-SAM4S-Datasheet_09-Jun-15
980
39.7 Pulse Width Modulation Controller (PWM) User Interface
Table 39-6 . Register Mapping
Offset Register Name Access Reset
0x00 PWM Clock Register PWM_CLK Read/Write 0x0
0x04 PWM Enable Register PWM_ENA Write-only –
0x08 PWM Disable Register PWM_DIS Write-only –
0x0C PWM Status Register PWM_SR Read-only 0x0
0x10 PWM Interrupt Enable Registe r 1 PWM_IER1 Write-only –
0x14 PWM Interrupt Disable Register 1 PWM_IDR1 Write-only –
0x18 PWM Interrupt Mask Register 1 PWM_IMR1 Read-only 0x0
0x1C PWM Interrupt Status Register 1 PWM_ISR1 Read-only 0x0
0x20 PWM Sync Channels Mode Register PWM_SCM Read/Write 0x0
0x24 Reserved – – –
0x28 PWM Sync Channels Update Control Register PWM_SCUC Read/Write 0x0
0x2C PWM Sync Channels Update Period Register PWM_SCUP Read/Write 0x0
0x30 PWM Sync Channels Update Period Update Register PWM_SCU PUP D Write-only –
0x34 PWM Interrupt Enable Registe r 2 PWM_IER2 Write-only –
0x38 PWM Interrupt Disable Register 2 PWM_IDR2 Write-only –
0x3C PWM Interrupt Mask Register 2 PWM_IMR2 Read-only 0x0
0x40 PWM Interrupt Status Register 2 PWM_ISR2 Read-only 0x0
0x44 PWM Output Override Value Register PWM_OOV Read/Write 0x0
0x48 PWM Output Selection Register PWM_OS Read/Write 0x0
0x4C PWM Output Selection Set Register PWM_OSS Write-only –
0x50 PWM Output Selection Clear Register PWM_OSC Write-only –
0x54 PWM Output Selection Set Update Register PWM_OSSUPD Write-only –
0x58 PWM Output Selection Clear Update Register PWM_OSCUPD Write-only –
0x5C PWM Fault Mode Registe r PWM_FMR Read/Write 0x0
0x60 PWM Fault Status Register PWM_FSR Read-only 0x0
0x64 PWM Fault Clear Register PWM_FCR Write-only –
0x68 PWM Fault Protection Value Register PWM_FPV Rea d/Write 0x0
0x6C PWM Fault Protection Enable Register PWM_FPE Read/Write 0x0
0x70–0x78 Reserved – – –
0x7C PWM Event Line 0 Mode Register PWM_ELMR0 Read/Write 0x0
0x80 PWM Event Line 1 Mode Register PWM_ELMR1 Read/Write 0x0
0x84–0x9C Reserved – – –
0xA0–0xAC Reserved – – –
0xB0 PWM Ste pper Motor Mode Regi ster PWM_SMMR Read/Write 0x0
0xB4–0xBC Reserved – – –
981
SAM4S Series [DATASHEET]
Atmel-11100K-ATARM-SAM4S-Datasheet_09-Jun-15
0xC0–0xE0 Reserved – – –
0xE4 PWM Write Protection Control Register PWM_WPCR Write-only –
0xE8 PWM Write Protection Status Register PWM_WPSR Read-only 0x0
0xEC–0xFC Reserved – – –
0x100–0x128 Reserved for PDC registe rs – – –
0x12C Reserved – – –
0x130 PWM Comparison 0 Value Register PWM_CMPV0 Read/Write 0x0
0x134 PWM Comparison 0 Value Update Register PWM_CMPVUPD0 Write-only –
0x138 PWM Comparison 0 Mode Register PWM_CMPM0 Read/Write 0x0
0x13C PWM Comparison 0 Mode Update Register PWM_CMPMUPD0 Write-only –
0x140 PWM Comparison 1 Value Register PWM_CMPV1 Read/Write 0x0
0x144 PWM Comparison 1 Value Update Register PWM_CMPVUPD1 Write-only –
0x148 PWM Comparison 1 Mode Register PWM_CMPM1 Read/Write 0x0
0x14C PWM Comparison 1 Mode Update Register PWM_CMPMUPD1 Write-only –
0x150 PWM Comparison 2 Value Register PWM_CMPV2 Read/Write 0x0
0x154 PWM Comparison 2 Value Update Register PWM_CMPVUPD2 Write-only –
0x158 PWM Comparison 2 Mode Register PWM_CMPM2 Read/Write 0x0
0x15C PWM Comparison 2 Mode Update Register PWM_CMPMUPD2 Write-only –
0x160 PWM Comparison 3 Value Register PWM_CMPV3 Read/Write 0x0
0x164 PWM Comparison 3 Value Update Register PWM_CMPVUPD3 Write-only –
0x168 PWM Comparison 3 Mode Register PWM_CMPM3 Read/Write 0x0
0x16C PWM Comparison 3 Mode Update Register PWM_CMPMUPD3 Write-only –
0x170 PWM Comparison 4 Value Register PWM_CMPV4 Read/Write 0x0
0x174 PWM Comparison 4 Value Update Register PWM_CMPVUPD4 Write-only –
0x178 PWM Comparison 4 Mode Register PWM_CMPM4 Read/Write 0x0
0x17C PWM Comparison 4 Mode Update Register PWM_CMPMUPD4 Write-only –
0x180 PWM Comparison 5 Value Register PWM_CMPV5 Read/Write 0x0
0x184 PWM Comparison 5 Value Update Register PWM_CMPVUPD5 Write-only –
0x188 PWM Comparison 5 Mode Register PWM_CMPM5 Read/Write 0x0
0x18C PWM Comparison 5 Mode Update Register PWM_CMPMUPD5 Write-only –
0x190 PWM Comparison 6 Value Register PWM_CMPV6 Read/Write 0x0
0x194 PWM Comparison 6 Value Update Register PWM_CMPVUPD6 Write-only –
0x198 PWM Comparison 6 Mode Register PWM_CMPM6 Read/Write 0x0
0x19C PWM Comparison 6 Mode Update Register PWM_CMPMUPD6 Write-only –
0x1A0 PWM Comparison 7 Value Register PWM_CMPV7 Read/Write 0x0
0x1A4 PWM Comparison 7 Value Update Register PWM_CMPVUPD7 Write-only –
0x1A8 PWM Comparison 7 Mode Register PWM_CMPM7 Read/Write 0x0
Table 39-6. Register Mapping (Continued)
Offset Register Name Access Reset
SAM4S Series [DATASHEET]
Atmel-11100K-ATARM-SAM4S-Datasheet_09-Jun-15
982
Notes: 1. Some registers are indexed with “ch_num” in dex ranging from 0 to 3.
0x1AC PWM Comparison 7 Mode Update Register PWM_CMPMUPD7 Write-only –
0x1B0–0x1FC Reserved – – –
0x200 + ch_num *
0x20 + 0x00 PWM Channel Mode Register(1) PWM_CMR Read/Write 0x0
0x200 + ch_num *
0x20 + 0x04 PWM Channel Duty Cycle Register(1) PWM_CDTY Read/Write 0x0
0x200 + ch_num *
0x20 + 0x08 PWM Channel Duty Cycle Update Register(1) PWM_CDTYUPD Write-only –
0x200 + ch_num *
0x20 + 0x0C PWM Channel Period Registe r(1) PWM_CPRD Read/Write 0x0
0x200 + ch_num *
0x20 + 0x10 PWM Channel Period Update Register (1) PWM_CPRDUPD Write-only –
0x200 + ch_num *
0x20 + 0x14 PWM Channel Counter Register(1) PWM_CCNT Read-only 0x0
0x200 + ch_num *
0x20 + 0x18 PWM Channel Dead Time Register(1) PWM_DT Read/Write 0x0
0x200 + ch_num *
0x20 + 0x1C PWM Channel Dead Time Update Register(1) PWM_DTUPD Write-only –
Table 39-6. Register Mapping (Continued)
Offset Register Name Access Reset
983
SAM4S Series [DATASHEET]
Atmel-11100K-ATARM-SAM4S-Datasheet_09-Jun-15
39.7.1 PWM Clo c k Reg i st er
Name: PWM_CLK
Address: 0x40020000
Access: Read/Write
This register can only be written if bits WPSWS0 and WPHWS0 are cleared in the PWM Write Protection Status Register.
• DIVA: CLKA Divide Factor
• DIVB: CLKB Divide Factor
• PREA: CLKA Source Clock Selection
31 30 29 28 27 26 25 24
–––– PREB
23 22 21 20 19 18 17 16
DIVB
15 14 13 12 11 10 9 8
–––– PREA
76543210
DIVA
Value Name Description
0 CLKA_POFF CLKA clock is turned off
1 PREA CLKA clock is clock selected by PREA
2–255 PREA_DIV CLKA clock is clock selected by PREA divided by DIVA factor
Value Name Description
0 CLKB_POFF CLKB clock is turned off
1 PREB CLKB clock is clock selected by PREB
2–255 PREB_DIV CLKB clock is clock selected by PREB divided by DIVB factor
Value Name Description
0 CLK Periphe ral clock
1 CLK_DIV2 Peripheral clock/2
2 CLK_DIV4 Peripheral clock/4
3 CLK_DIV8 Peripheral clock/8
4 CLK_DIV16 Periphe ral clock/16
5 CLK_DIV32 Periphe ral clock/32
6 CLK_DIV64 Periphe ral clock/64
7 CLK_DIV128 Peripheral clock/128
8 CLK_DIV256 Peripheral clock/256
SAM4S Series [DATASHEET]
Atmel-11100K-ATARM-SAM4S-Datasheet_09-Jun-15
984
• PREB: CLKB Source Clock Selection
9 CLK_DIV512 Peripheral clock/512
10 CLK_DIV1024 Peripheral clock/1024
Other – Reserved
Value Name Description
0 CLK Periphe ral clock
1 CLK_DIV2 Peripheral clock/2
2 CLK_DIV4 Peripheral clock/4
3 CLK_DIV8 Peripheral clock/8
4 CLK_DIV16 Periphe ral clock/16
5 CLK_DIV32 Periphe ral clock/32
6 CLK_DIV64 Periphe ral clock/64
7 CLK_DIV128 Peripheral clock/128
8 CLK_DIV256 Peripheral clock/256
9 CLK_DIV512 Peripheral clock/512
10 CLK_DIV1024 Peripheral clock/1024
Other – Reserved
985
SAM4S Series [DATASHEET]
Atmel-11100K-ATARM-SAM4S-Datasheet_09-Jun-15
39.7.2 PWM Enable Register
Name: PWM_ENA
Address: 0x40020004
Access: Write-only
• CHIDx: Channel ID
0: No effect.
1: Enable PWM output for channel x.
31 30 29 28 27 26 25 24
––––––––
23 22 21 20 19 18 17 16
––––––––
15 14 13 12 11 10 9 8
––––––––
76543210
––––CHID3CHID2CHID1CHID0
SAM4S Series [DATASHEET]
Atmel-11100K-ATARM-SAM4S-Datasheet_09-Jun-15
986
39.7.3 PWM Disable Register
Name: PWM_DIS
Address: 0x40020008
Access: Write-only
This register can only be written if bits WPSWS1 and WPHWS1 are cleared in the PWM Write Protection Status Register.
• CHIDx: Channel ID
0: No effect.
1: Disable PWM output for channel x.
31 30 29 28 27 26 25 24
––––––––
23 22 21 20 19 18 17 16
––––––––
15 14 13 12 11 10 9 8
––––––––
76543210
––––CHID3CHID2CHID1CHID0
987
SAM4S Series [DATASHEET]
Atmel-11100K-ATARM-SAM4S-Datasheet_09-Jun-15
39.7.4 PWM Status Register
Name: PWM_SR
Address: 0x4002000C
Access: Read-only
• CHIDx: Channel ID
0: PWM output for channel x is disabled.
1: PWM output for channel x is enabled.
31 30 29 28 27 26 25 24
––––––––
23 22 21 20 19 18 17 16
––––––––
15 14 13 12 11 10 9 8
––––––––
76543210
––––CHID3CHID2CHID1CHID0
SAM4S Series [DATASHEET]
Atmel-11100K-ATARM-SAM4S-Datasheet_09-Jun-15
988
39.7.5 PWM Interrupt Enable Register 1
Name: PWM_IER1
Address: 0x40020010
Access: Write-only
• CHIDx: Counter Event on Channel x Interrupt Enable
• FCHIDx: Fault Protection Trigger on Channel x Interrupt Enable
31 30 29 28 27 26 25 24
––––––––
23 22 21 20 19 18 17 16
––––FCHID3FCHID2FCHID1FCHID0
15 14 13 12 11 10 9 8
––––––––
76543210
––––CHID3CHID2CHID1CHID0
989
SAM4S Series [DATASHEET]
Atmel-11100K-ATARM-SAM4S-Datasheet_09-Jun-15
39.7.6 PWM Interrupt Disable Register 1
Name: PWM_IDR1
Address: 0x40020014
Access: Write-only
• CHIDx: Counter Event on Channel x Interrupt Disable
• FCHIDx: Fault Protection Trigger on Channel x Interrupt Disable
31 30 29 28 27 26 25 24
––––––––
23 22 21 20 19 18 17 16
––––FCHID3FCHID2FCHID1FCHID0
15 14 13 12 11 10 9 8
––––––––
76543210
––––CHID3CHID2CHID1CHID0
SAM4S Series [DATASHEET]
Atmel-11100K-ATARM-SAM4S-Datasheet_09-Jun-15
990
39.7.7 PWM Interrupt Mask Register 1
Name: PWM_IMR1
Address: 0x40020018
Access: Read-only
• CHIDx: Counter Event on Channel x Interrupt Mask
• FCHIDx: Fault Protection Trigger on Channel x Interrupt Mask
31 30 29 28 27 26 25 24
––––––––
23 22 21 20 19 18 17 16
––––FCHID3FCHID2FCHID1FCHID0
15 14 13 12 11 10 9 8
––––––––
76543210
––––CHID3CHID2CHID1CHID0
991
SAM4S Series [DATASHEET]
Atmel-11100K-ATARM-SAM4S-Datasheet_09-Jun-15
39.7.8 PWM Interrupt Status Register 1
Name: PWM_ISR1
Address: 0x4002001C
Access: Read-only
• CHIDx: Counter Event on Channel x
0: No new counter event has occurred since the last read of the PWM_ISR1.
1: At least one counter event has occurred since the last read of the PWM_ISR1.
• FCHIDx: Fault Protection Trigger on Channel x
0: No new trigger of the fault protection since the last read of the PWM_ISR1.
1: At least one trigger of the fault protection since the last read of the PWM_ISR1.
Note: Reading PWM_ISR1 automatically clears CHIDx and FCHIDx flags.
31 30 29 28 27 26 25 24
––––––––
23 22 21 20 19 18 17 16
––––FCHID3FCHID2FCHID1FCHID0
15 14 13 12 11 10 9 8
––––––––
76543210
––––CHID3CHID2CHID1CHID0
SAM4S Series [DATASHEET]
Atmel-11100K-ATARM-SAM4S-Datasheet_09-Jun-15
992
39.7.9 PWM Sync Channels Mode Register
Name: PWM_SCM
Address: 0x40020020
Access: Read/Write
This register can only be written if bits WPSWS2 and WPHWS2 are cleared in the PWM Write Protection Status Register.
• SYNCx: Synchronous Channel x
0: Channel x is not a synchronous channel.
1: Channel x is a synchronous channel.
• UPDM: Synchronous Channels Update Mode
Notes: 1. The update occurs at the beginning of the next PWM period, when the UPDULOCK bit in PWM Sync Channel s Update
Control Register is set.
2. The update occurs when the Update Period is elapsed.
• PTRM: Peripheral DMA Controller Transfer Request Mode
• PTRCS: Peripheral DMA Controller Transfer Request Comparison Selection
Selection of the comparison used to set the flag WRDY and the corr espond ing Pe ripheral DMA Control ler tran sfer requ est.
31 30 29 28 27 26 25 24
––––––––
23 22 21 20 19 18 17 16
PTRCS PTRM – – UPDM
15 14 13 12 11 10 9 8
––––––––
76543210
––––SYNC3SYNC2SYNC1SYNC0
Value Name Description
0 MODE0 Manual write of double buffer registers and manual update of synchronous channels(1)
1 MODE1 Manual write of double buffer registers and automatic update of synchronous channels(2)
2MODE2
Automatic write of duty-cycle update registers by the Peripheral DMA Controller and automati c
update of synchronous channels(2)
UPDM PTRM WRDY Flag and Peripheral DMA Controller Transfer Request
0x
The WRDY flag in PWM Interrupt Status Register 2 and the PDC transfer request are never set to
‘1’.
1x
The WRDY flag in PWM Interrupt Status Register 2 is set to ‘1’ as soon as the update period is
elapsed, the Peripheral DMA Controller transfer request is never set to ‘1’.
20The WRDY flag in PWM Interrupt Status Regist er 2 and the PDC transfer request are set to ‘1’ as
soon as the update period is elapsed.
1The WRDY flag in PWM Interrupt Status Regist er 2 and the PDC transfer request are set to ‘1’ as
soon as the selected comparison matches.
993
SAM4S Series [DATASHEET]
Atmel-11100K-ATARM-SAM4S-Datasheet_09-Jun-15
39.7.10 PWM Sync Channels Update Control Register
Name: PWM_SCUC
Address: 0x40020028
Access: Read/Write
• UPDULOCK: Synchronous Channels Update Unlock
0: No effect
1: If the UPDM field is set to ‘0’ in PWM Sync Channels Mode Register, writing the UPDULOCK bit to ‘1’ triggers the update
of the period value, the duty-cycle and the dead-time values of synchronous channels at the beginning of the next PWM
period. If the field UPDM is set to ‘1’ or ‘2’, writing the UPDULOCK bit to ‘1’ triggers only the upd ate of the period value and
of the dead-time values of synchronous channels.
This bit is automatically reset when the update is done.
31 30 29 28 27 26 25 24
––––––––
23 22 21 20 19 18 17 16
––––––––
15 14 13 12 11 10 9 8
––––––––
76543210
–––––––UPDULOCK
SAM4S Series [DATASHEET]
Atmel-11100K-ATARM-SAM4S-Datasheet_09-Jun-15
994
39.7.11 PWM Sync Channels Update Period Register
Name: PWM_SCUP
Address: 0x4002002C
Access: Read/Write
•UPR: Update Period
Defines the time between each update of the synchronous channels if automatic trigger of the update is activated
(UPDM = 1 or UPDM = 2 in PWM Sync Channels Mode Register). This time is equal to UPR+1 periods of the synchronous
channels.
• UPRCNT: Update Period Counter
Reports the value of the update period counter.
31 30 29 28 27 26 25 24
––––––––
23 22 21 20 19 18 17 16
––––––––
15 14 13 12 11 10 9 8
––––––––
76543210
UPRCNT UPR
995
SAM4S Series [DATASHEET]
Atmel-11100K-ATARM-SAM4S-Datasheet_09-Jun-15
39.7.12 PWM Sync Channels Update Period Update Register
Name: PWM_SCUPUPD
Address: 0x40020030
Access: Write-only
This register acts as a double buffer for the UPR value. This prevents an unexpected automatic trigger of the update of
synchronous channels.
• UPRUPD: Update Period Update
Defines the wanted time between each update of the synchronous channels if automatic trigger of the update is activated
(UPDM = 1 or UPDM = 2 in PWM Sync Channe ls Mode Register). This time is equal to UPR+1 periods of the synchronous
channels.
31 30 29 28 27 26 25 24
––––––––
23 22 21 20 19 18 17 16
––––––––
15 14 13 12 11 10 9 8
––––––––
76543210
–––– UPRUPD
SAM4S Series [DATASHEET]
Atmel-11100K-ATARM-SAM4S-Datasheet_09-Jun-15
996
39.7.13 PWM Interrupt Enable Register 2
Name: PWM_IER2
Address: 0x40020034
Access: Write-only
• WRDY: Write Ready for Synchronous Channels Update Interrupt Enable
• ENDTX: PDC End of TX Buffer Interrupt Enable
• TXBUFE: PDC TX Buffer Empty Interrupt Enable
• UNRE: Synchronous Channels Update Underrun Error Interrupt Enable
• CMPMx: Comparison x Match Interrupt Enable
• CMPUx: Comparison x Update Interrupt Enable
31 30 29 28 27 26 25 24
––––––––
23 22 21 20 19 18 17 16
CMPU7 CMPU6 CMPU5 CMPU4 CMPU3 CMPU2 CMPU1 CMPU0
15 14 13 12 11 10 9 8
CMPM7 CMPM6 CMPM5 CMPM4 CMPM3 CMPM2 CMPM1 CMPM0
76543210
––––UNRE TXBUFE ENDTX WRDY
997
SAM4S Series [DATASHEET]
Atmel-11100K-ATARM-SAM4S-Datasheet_09-Jun-15
39.7.14 PWM Interrupt Disable Register 2
Name: PWM_IDR2
Address: 0x40020038
Access: Write-only
• WRDY: Write Ready for Synchronous Channels Update Interrupt Disa ble
• ENDTX: PDC End of TX Buffer Interrupt Disable
• TXBUFE: PDC TX Buffer Empty Interrupt Disable
• UNRE: Synchronous Channels Update Underrun Error Interrupt Disable
• CMPMx: Comparison x Match Interrupt Disable
• CMPUx: Comparison x Update Interrupt Disable
31 30 29 28 27 26 25 24
––––––––
23 22 21 20 19 18 17 16
CMPU7 CMPU6 CMPU5 CMPU4 CMPU3 CMPU2 CMPU1 CMPU0
15 14 13 12 11 10 9 8
CMPM7 CMPM6 CMPM5 CMPM4 CMPM3 CMPM2 CMPM1 CMPM0
76543210
––––UNRE TXBUFE ENDTX WRDY
SAM4S Series [DATASHEET]
Atmel-11100K-ATARM-SAM4S-Datasheet_09-Jun-15
998
39.7.15 PWM Interrupt Mask Register 2
Name: PWM_IMR2
Address: 0x4002003C
Access: Read-only
• WRDY: Write Ready for Synchronous Channels Update Interrupt Mask
• ENDTX: PDC End of TX Buffer Interrupt Mask
• TXBUFE: PDC TX Buffer Empty Interrupt Mask
• UNRE: Synchronous Channels Update Underrun Error Interrupt Mask
• CMPMx: Comparison x Match Interrupt Mask
• CMPUx: Comparison x Update Interrupt Mask
31 30 29 28 27 26 25 24
––––––––
23 22 21 20 19 18 17 16
CMPU7 CMPU6 CMPU5 CMPU4 CMPU3 CMPU2 CMPU1 CMPU0
15 14 13 12 11 10 9 8
CMPM7 CMPM6 CMPM5 CMPM4 CMPM3 CMPM2 CMPM1 CMPM0
76543210
––––UNRE TXBUFE ENDTX WRDY
999
SAM4S Series [DATASHEET]
Atmel-11100K-ATARM-SAM4S-Datasheet_09-Jun-15
39.7.16 PWM Interrupt Status Register 2
Name: PWM_ISR2
Address: 0x40020040
Access: Read-only
• WRDY: Write Ready for Synchronous Channels Update
0: New duty-cycle and dead-time values for the synchronous channels cannot be written.
1: New duty-cycle and dead-time values for the synchronous channels can be written.
• ENDTX: PDC End of TX Buffer
0: The Transmit Counter register has not reached 0 since the last write of the PDC.
1: The Transmit Counter register has reached 0 since the last write of the PDC.
• TXBUFE: PDC TX Buffer Empty
0: PWM_TCR or PWM_TCNR has a value other than 0.
1: Both PWM_TCR and PWM_TCNR have a value other than 0.
• UNRE: Synchronous Channels Update Underrun Error
0: No Synchronous Channels Update Underrun has occurred since the last read of the PWM_ISR2 register.
1: At least one Synchronous Channels Update Underrun has occurred since the last read of the PWM_ISR2 register.
• CMPMx: Comparison x Match
0: The comparison x has not matched since the last read of the PWM_ISR2 register.
1: The comparison x has matched at least one time since the last read of the PWM_ISR2 register.
• CMPUx: Comparison x Update
0: The comparison x has not been updated since the last read of the PWM_ISR2 register.
1: The comparison x has been updated at least one time since the last read of the PWM_ISR2 register.
Note: Reading PWM_ISR2 automatically clears flags WRDY, UNRE and CMPSx.
31 30 29 28 27 26 25 24
––––––––
23 22 21 20 19 18 17 16
CMPU7 CMPU6 CMPU5 CMPU4 CMPU3 CMPU2 CMPU1 CMPU0
15 14 13 12 11 10 9 8
CMPM7 CMPM6 CMPM5 CMPM4 CMPM3 CMPM2 CMPM1 CMPM0
76543210
––––UNRE TXBUFE ENDTX WRDY
SAM4S Series [DATASHEET]
Atmel-11100K-ATARM-SAM4S-Datasheet_09-Jun-15
1000
39.7.17 PWM Output Override Value Register
Name: PWM_OOV
Address: 0x40020044
Access: Read/Write
• OOVHx: Output Override Value for PWMH output of the channel x
0: Override value is 0 for PWMH output of channel x.
1: Override value is 1 for PWMH output of channel x.
• OOVLx: Output Override Value for PWML output of the channel x
0: Override value is 0 for PWML output of channel x.
1: Override value is 1 for PWML output of channel x.
31 30 29 28 27 26 25 24
––––––––
23 22 21 20 19 18 17 16
––––OOVL3OOVL2OOVL1OOVL0
15 14 13 12 11 10 9 8
––––––––
76543210
––––OOVH3OOVH2OOVH1OOVH0
1001
SAM4S Series [DATASHEET]
Atmel-11100K-ATARM-SAM4S-Datasheet_09-Jun-15
39.7.18 PWM Output Selection Re gi st er
Name: PWM_OS
Address: 0x40020048
Access: Read/Write
• OSHx: Output Selection for PWMH output of the channel x
0: Dead-time generator output DTOHx selected as PWMH output of channel x.
1: Output override value OOVHx selected as PWMH output of channel x.
• OSLx: Output Selection for PWML output of the channel x
0: Dead-time generator output DTOLx selected as PWML output of channel x.
1: Output override value OOVLx selected as PWML output of channel x.
31 30 29 28 27 26 25 24
––––––––
23 22 21 20 19 18 17 16
––––OSL3OSL2OSL1OSL0
15 14 13 12 11 10 9 8
––––––––
76543210
––––OSH3OSH2OSH1OSH0
SAM4S Series [DATASHEET]
Atmel-11100K-ATARM-SAM4S-Datasheet_09-Jun-15
1002
39.7.19 PWM Output Selection Set Register
Name: PWM_OSS
Address: 0x4002004C
Access: Write-only
• OSSHx: Output Selection Set for PWMH output of the channel x
0: No effect.
1: Output override value OOVHx selected as PWMH output of channel x.
• OSSLx: Output Selection Set for PWML output of the channel x
0: No effect.
1: Output override value OOVLx selected as PWML output of channel x.
31 30 29 28 27 26 25 24
––––––––
23 22 21 20 19 18 17 16
––––OSSL3OSSL2OSSL1OSSL0
15 14 13 12 11 10 9 8
––––––––
76543210
––––OSSH3OSSH2OSSH1OSSH0
1003
SAM4S Series [DATASHEET]
Atmel-11100K-ATARM-SAM4S-Datasheet_09-Jun-15
39.7.20 PWM Output Selection Clear Register
Name: PWM_OSC
Address: 0x40020050
Access: Write-only
• OSCHx: Output Selection Clear for PWMH output of the channel x
0: No effect.
1: Dead-time generator output DTOHx selected as PWMH output of channel x.
• OSCLx: Output Selection Clear for PWML output of the channel x
0: No effect.
1: Dead-time generator output DTOLx selected as PWML output of channel x.
31 30 29 28 27 26 25 24
––––––––
23 22 21 20 19 18 17 16
––––OSCL3OSCL2OSCL1OSCL0
15 14 13 12 11 10 9 8
––––––––
76543210
––––OSCH3OSCH2OSCH1OSCH0
SAM4S Series [DATASHEET]
Atmel-11100K-ATARM-SAM4S-Datasheet_09-Jun-15
1004
39.7.21 PWM Output Selection Set U pdate Register
Name: PWM_OSSUPD
Address: 0x40020054
Access: Write-only
• OSSUPHx: Output Selection Set for PWMH output of the channel x
0: No effect.
1: Output override value OOVHx selected as PWMH output of channel x at the beginning of the next channel x PWM
period.
• OSSUPLx: Output Selection Set for PWML output of the channel x
0: No effect.
1: Output override value OOVLx selected as PWML output of channel x at the beginning of the next channel x PWM
period.
31 30 29 28 27 26 25 24
––––––––
23 22 21 20 19 18 17 16
––––OSSUPL3OSSUPL2OSSUPL1OSSUPL0
15 14 13 12 11 10 9 8
––––––––
76543210
––––OSSUPH3OSSUPH2OSSUPH1OSSUPH0
1005
SAM4S Series [DATASHEET]
Atmel-11100K-ATARM-SAM4S-Datasheet_09-Jun-15
39.7.22 PWM Output Selection Clear Update Register
Name: PWM_OSCUPD
Address: 0x40020058
Access: Write-only
• OSCUPHx: Output Selection Clear for PWMH output of the channel x
0: No effect.
1: Dead-time generator output DTOHx selecte d as PWMH output o f channel x at the begi nning of the next channel x PWM
period.
• OSCUPLx: Output Selection Clear for PWML output of the channel x
0: No effect.
1: Dead-time generato r ou tp ut DT OLx selected as PWML output of channel x at th e beginn ing of the next channel x PWM
period.
31 30 29 28 27 26 25 24
––––––––
23 22 21 20 19 18 17 16
––––OSCUPL3OSCUPL2OSCUPL1OSCUPL0
15 14 13 12 11 10 9 8
––––––––
76543210
––––OSCUPH3OSCUPH2OSCUPH1OSCUPH0
SAM4S Series [DATASHEET]
Atmel-11100K-ATARM-SAM4S-Datasheet_09-Jun-15
1006
39.7.23 PWM Fault Mode Register
Name: PWM_FMR
Address: 0x4002005C
Access: Read/Write
This register can only be written if bits WPSWS5 and WPHWS5 are cleared in the PWM Write Protection Status Register.
• FPOL: Fault Polarity
For each bit y of FPOL, wh er e y is the fa ult inp u t num b er:
0: The fault y becomes active when the fault input y is at 0.
1: The fault y becomes active when the fault input y is at 1.
• FMOD: Fault Activation Mode
For each bit y of FMOD, where y is the fault input number:
0: The fault y is active until the fault condition is removed at the peripheral(1) level.
1: The fault y stays active until the fault condition is removed at the peripheral(1) level AND until it is cleared in the PWM
Fault Clear Register.
Note: 1. The peripheral generating the fault.
• FFIL: Fault Filtering
For each bit y of FFIL, where y is the fault input number:
0: The fault input y is not filtered.
1: The fault input y is filtered.
CAUTION: To prevent an unexpected activation of the status flag FSy in the PWM Fault Status Register, the bit FMODy
can be set to ‘1’ only if the FPOLy bit has been previously configured to its final value.
31 30 29 28 27 26 25 24
–
23 22 21 20 19 18 17 16
FFIL
15 14 13 12 11 10 9 8
FMOD
76543210
FPOL
1007
SAM4S Series [DATASHEET]
Atmel-11100K-ATARM-SAM4S-Datasheet_09-Jun-15
39.7.24 PWM Fault Status Register
Name: PWM_FSR
Address: 0x40020060
Access: Read-only
• FIV: Fault Input Value
For each bit y of FIV, where y is the fault input number:
0: The current sampled value of the fault input y is 0 (after filtering if enabled).
1: The current sampled value of the fault input y is 1 (after filtering if enabled).
• FS: Fault Status
For each bit y of FS, where y is the fault input number:
0: The fault y is not currently active.
1: The fault y is currently active.
31 30 29 28 27 26 25 24
–
23 22 21 20 19 18 17 16
–
15 14 13 12 11 10 9 8
FS
76543210
FIV
SAM4S Series [DATASHEET]
Atmel-11100K-ATARM-SAM4S-Datasheet_09-Jun-15
1008
39.7.25 PWM Fault Clear Register
Name: PWM_FCR
Address: 0x40020064
Access: Write-only
• FCLR: Fault Clear
For each bit y of FCLR, where y is the fault input number:
0: No effect.
1: If bit y of FMOD field is set to ‘1’ and if t he fault inp ut y is not at the level defined by th e bit y of FPOL field, the fa ult y
is cleared and becomes inactive (FMOD and FPOL fields belong to PW M Fault Mo de Registe r), else writing this bit to
‘1’ has no effect.
31 30 29 28 27 26 25 24
–
23 22 21 20 19 18 17 16
–
15 14 13 12 11 10 9 8
–
76543210
FCLR
1009
SAM4S Series [DATASHEET]
Atmel-11100K-ATARM-SAM4S-Datasheet_09-Jun-15
39.7.26 PWM Fault Protection Value Register
Name: PWM_FPV
Address: 0x40020068
Access: Read/Write
This register can only be written if bits WPSWS5 and WPHWS5 are cleared in the PWM Write Protection Status Register.
• FPVHx: Fault Protection Value for PWMH output on channel x
0: PWMH output of channel x is forced to ‘0’ when fault occurs.
1: PWMH output of channel x is forced to ‘1’ when fault occurs.
• FPVLx: Fault Protection Value for PWML output on channel x
0: PWML output of channel x is forced to ‘0’ when fault occurs.
1: PWML output of channel x is forced to ‘1’ when fault occurs.
31 30 29 28 27 26 25 24
––––––––
23 22 21 20 19 18 17 16
––––FPVL3FPVL2FPVL1FPVL0
15 14 13 12 11 10 9 8
––––––––
76543210
––––FPVH3FPVH2FPVH1FPVH0
SAM4S Series [DATASHEET]
Atmel-11100K-ATARM-SAM4S-Datasheet_09-Jun-15
1010
39.7.27 PWM Fault Protection Enable Regis ter
Name: PWM_FPE
Address: 0x4002006C
Access: Read/Write
This register can only be written if bits WPSWS5 and WPHWS5 are cleared in the PWM Write Protection Status Register.
Only the first 8 bits (number of fault input pins) of fields FPE0, FPE1, FPE2 and FPE3 are significant.
• FPEx: Fault Protection Enable for channel x
For each bit y of FPEx, where y is the fault input number:
0: Fault y is not used for the f ault protection of channel x.
1: Fault y is used for the fault protection of channel x.
CAUTION: To prevent an unexpected activation of the fault protection, the bit y of FPEx field can be set to ‘1’ only if the
corresponding FPOL field has been previously config ured to its final value in PWM Fault Mode Register.
31 30 29 28 27 26 25 24
FPE3
23 22 21 20 19 18 17 16
FPE2
15 14 13 12 11 10 9 8
FPE1
76543210
FPE0
1011
SAM4S Series [DATASHEET]
Atmel-11100K-ATARM-SAM4S-Datasheet_09-Jun-15
39.7.28 PWM Event Line x Register
Name: PWM_ELMRx
Address: 0x4002007C
Access: Read/Write
• CSELy: Comparison y Selection
0: A pulse is not generated on the event line x when the comparison y matches.
1: A pulse is generated on the event line x when the comparison y match.
31 30 29 28 27 26 25 24
––––––––
23 22 21 20 19 18 17 16
––––––––
15 14 13 12 11 10 9 8
––––––––
76543210
CSEL7 CSEL6 CSEL5 CSEL4 CSEL3 CSEL2 CSEL1 CSEL0
SAM4S Series [DATASHEET]
Atmel-11100K-ATARM-SAM4S-Datasheet_09-Jun-15
1012
39.7.29 PWM Stepper Motor Mode Register
Name: PWM_SMMR
Address: 0x400200B0
Access: Read/Write
• GCENx: Gray Count ENable
0: Disable gray count generation on PWML[2*x], PWMH[2*x], PWML[2*x +1], PWMH[2*x +1]
1: Enable gray count generation on PWML[2*x], PWMH[2*x], PWML[2*x +1], PWMH[2*x +1.
• DOWNx: DOWN Count
0: Up counter.
1: Down counter.
31 30 29 28 27 26 25 24
––––––––
23 22 21 20 19 18 17 16
––––––DOWN1DOWN0
15 14 13 12 11 10 9 8
––––––––
76543210
––––––GCEN1GCEN0
1013
SAM4S Series [DATASHEET]
Atmel-11100K-ATARM-SAM4S-Datasheet_09-Jun-15
39.7.30 PWM Write Protection Control Regi ster
Name: PWM_WPCR
Address: 0x400200E4
Access: Write-only
See Section 39.6.6 “Register Write Protection” for the list of registers that can be write-protected.
• WPCMD: Write Protection Command
This command is performed only if the WPKEY corresp onds to 0x50574D (“PWM” in ASCII).
• WPRGx: Write Protecti o n Register Group x
0: The WPCMD command has no effect on the register group x.
1: The WPCMD command is applied to the register group x.
• WPKEY: Write Protection Key
31 30 29 28 27 26 25 24
WPKEY
23 22 21 20 19 18 17 16
WPKEY
15 14 13 12 11 10 9 8
WPKEY
76543210
WPRG5WPRG4WPRG3WPRG2WPRG1WPRG0 WPCMD
Value Name Description
0 DISABLE_SW_PROT Disables the software write protection of the register groups of which the bit WPRGx is at ‘1’.
1 ENABLE_SW_PROT Enables the software write protection of the register groups of which the bit WPRGx is at ‘1’.
2 ENABLE_HW_PROT
Enables the hardware write protection of the register groups of which the bit WPRGx is at ‘1’.
Only a hardware reset of the PWM controller can disable the hardw are write protection.
Moreover, to meet security requirements, the PIO lines associated with the PWM can not be
configured through the PIO interface.
Value Name Description
0x50574D PASSWD Writing any othe r val u e in this field abo rts the write operation of th e WPCMD field.
Always reads as 0
SAM4S Series [DATASHEET]
Atmel-11100K-ATARM-SAM4S-Datasheet_09-Jun-15
1014
39.7.31 PWM Write Protection Status Register
Name: PWM_WPSR
Address: 0x400200E8
Access: Read-only
• WPSWSx: Write Protect SW Status
0: The SW write protection x of the register group x is disabled.
1: The SW write protection x of the register group x is enabled.
• WPHWSx: Write Protect HW Status
0: The HW write protection x of the register group x is disabled.
1: The HW write protection x of the register group x is enabled.
• WPVS: Write Protect Violation Status
0: No write protec tion v iola tio n ha s occ u rred since the last read of the PWM_WPSR.
1: At least one write protection violation has occurred since the last read of the PWM_WPSR. If this violation is an unau -
thorized attempt to write a protected register, the associated violation is reported into field WPVSRC.
• WPVSRC: Write Protect Violation Source
When WPVS = 1, WPVSRC indicates the register address offset at which a write access has been attempted.
31 30 29 28 27 26 25 24
WPVSRC
23 22 21 20 19 18 17 16
WPVSRC
15 14 13 12 11 10 9 8
– – WPHWS5 WPHWS4 WPHWS3 WPHWS2 WPHWS1 WPHWS0
76543210
WPVS – WPSWS5 WPSWS4 WPSWS3 WPSWS2 WPSWS1 WPSWS0
1015
SAM4S Series [DATASHEET]
Atmel-11100K-ATARM-SAM4S-Datasheet_09-Jun-15
39.7.32 PWM Comparison x Value Register
Name: PWM_CMPVx
Address: 0x40020130 [0], 0x40020140 [1], 0x40020150 [2], 0x40020160 [3], 0x40020170 [4], 0x40020180 [5],
0x40020190 [6], 0x400201A0 [7]
Access: Read/Write
Only the first 16 bits (channel counter size) of field CV are significant.
• CV: Comparison x Value
Define the comparison x value to be compared with the counter of the channel 0.
• CVM: Comparison x Value Mode
0: The comparison x between the counter of the channel 0 and the comparison x value is performed when this counter is
incrementing.
1: The comparison x between the counter of the channel 0 and the comparison x value is performed when this counter is
decrementing.
Note: This bit is not relevant if the counter of the channel 0 is left-aligned (CALG = 0 in PWM Channel Mode Register)
31 30 29 28 27 26 25 24
–––––––CVM
23 22 21 20 19 18 17 16
CV
15 14 13 12 11 10 9 8
CV
76543210
CV
SAM4S Series [DATASHEET]
Atmel-11100K-ATARM-SAM4S-Datasheet_09-Jun-15
1016
39.7.33 PWM Comparison x Value Update Register
Name: PWM_CMPVUPDx
Address: 0x40020134 [0], 0x40020144 [1], 0x40020154 [2], 0x40020164 [3], 0x40020174 [4], 0x40020184 [5],
0x40020194 [6], 0x400201A4 [7]
Access: Write-only
This register acts as a double buffer for the CV and CVM values. This prevents an unexpected comparison x match.
Only the first 16 bits (channel counter size) of field CVUPD are significant.
• CVUPD: Comparison x Value Update
Define the comparison x value to be compared with the counter of the channel 0.
• CVMUPD: Comparison x Value Mode Update
0: The comparison x between the counter of the channel 0 and the comparison x value is performed when this counter is
incrementing.
1: The comparison x between the counter of the channel 0 and the comparison x value is performed when this counter is
decrementing.
Note: This bit is not relevant if the counter of the channel 0 is left-aligned (CALG = 0 in PWM Channel Mode Register)
CAUTION: The write of the register PWM_CMPVUPDx must be followed by a write of the register PWM_CMPMUPDx.
31 30 29 28 27 26 25 24
–––––––CVMUPD
23 22 21 20 19 18 17 16
CVUPD
15 14 13 12 11 10 9 8
CVUPD
76543210
CVUPD
1017
SAM4S Series [DATASHEET]
Atmel-11100K-ATARM-SAM4S-Datasheet_09-Jun-15
39.7.34 PWM Comparison x Mode Register
Name: PWM_CMPMx
Address: 0x40020138 [0], 0x40020148 [1], 0x40020158 [2], 0x40020168 [3], 0x40020178 [4], 0x40020188 [5],
0x40020198 [6], 0x400201A8 [7]
Access: Read/Write
• CEN: Comparison x Enable
0: The comparison x is disabled and can not match.
1: The comparison x is enabled and can match.
• CTR: Comparison x Trigger
The comparison x is performed when the value of the comparison x period counter (CPRCNT) reaches the value defined
by CTR.
• CPR: Comparison x Period
CPR defines the maximum value of the comparison x period counter (CPRCNT). The comparison x value is performed
periodically once every CPR+1 periods of the channel 0 counter.
• CPRCNT: Comparison x Period Counter
Reports the value of the comparison x period counter.
Note: The field CPRCNT is read-only
• CUPR: Comparison x Update Period
Defines the time between each update of the comparison x mode and the comparison x value. This time is equal to
CUPR+1 periods of the channel 0 counter.
• CUPRCNT: Comparison x Update Period Counter
Reports the value of the comparison x update period counter .
Note: The field CUPRCNT is read-only
31 30 29 28 27 26 25 24
––––––––
23 22 21 20 19 18 17 16
CUPRCNT CUPR
15 14 13 12 11 10 9 8
CPRCNT CPR
76543210
CTR –––CEN
SAM4S Series [DATASHEET]
Atmel-11100K-ATARM-SAM4S-Datasheet_09-Jun-15
1018
39.7.35 PWM Comparison x Mode Update Register
Name: PWM_CMPMUPDx
Address: 0x4002013C [0], 0x4002014C [1], 0x4002015C [2], 0x4002016C [3], 0x4002017C [4], 0x4002018C [5],
0x4002019C [6], 0x400201AC [7]
Access: Write-only
This register acts as a double buffer for the C EN, CT R, C PR an d C UPR v al ue s. Th is preven ts an une xpected comp ar ison
x match.
• CENUPD: Comparison x Enable Update
0: The comparison x is disabled and can not match.
1: The comparison x is enabled and can match.
• CTRUPD: Comparison x Trigger Update
The comparison x is performed when the value of the comparison x period counter (CPRCNT) reaches the value defined
by CTR.
• CPRUPD: Comparison x Period Update
CPR defines the maximum value of the comparison x period counter (CPRCNT). The comparison x value is performed
periodically once every CPR+1 periods of the channel 0 counter.
• CUPRUPD: Comparison x Update Period Update
Defines the time between each update of the comparison x mode and the comparison x value. This time is equal to
CUPR+1 periods of the channel 0 counter.
31 30 29 28 27 26 25 24
––––––––
23 22 21 20 19 18 17 16
–––– CUPRUPD
15 14 13 12 11 10 9 8
–––– CPRUPD
76543210
CTRUPD – – – CENUPD
1019
SAM4S Series [DATASHEET]
Atmel-11100K-ATARM-SAM4S-Datasheet_09-Jun-15
39.7.36 PWM Channel Mode Register
Name: PWM_CMRx [x=0..3]
Address: 0x40020200 [0], 0x40020220 [1], 0x40020240 [2], 0x40020260 [3]
Access: Read/Write
This register can only be written if bits WPSWS2 and WPHWS2 are cleared in the PWM Write Protection Status Register.
• CPRE: Channel Pre-scaler
• CALG: Channel Alignment
0: The period is left-aligned.
1: The period is center-aligned.
• CPOL: Channel Polarity
0: The OCx output waveform (output from the comparator) starts at a low level.
1: The OCx output waveform (output from the comparator) starts at a high level.
31 30 29 28 27 26 25 24
––––––––
23 22 21 20 19 18 17 16
–––––DTLIDTHIDTE
15 14 13 12 11 10 9 8
–––––CESCPOLCALG
76543210
–––– CPRE
Value Name Description
0 MCK Peripheral clock
1 MCK_DIV_2 Peripheral clock/2
2 MCK_DIV_4 Peripheral clock/4
3 MCK_DIV_8 Peripheral clock/8
4 MCK_DIV_16 Peripheral clock/16
5 MCK_DIV_32 Peripheral clock/32
6 MCK_DIV_64 Peripheral clock/64
7 MCK_DIV_128 Peripheral clock/128
8 MCK_DIV_256 Peripheral clock/256
9 MCK_DIV_512 Peripheral clock/512
10 MCK_DIV_1024 Peripheral clock/1024
11 CLKA Clock A
12 CLKB Clock B
SAM4S Series [DATASHEET]
Atmel-11100K-ATARM-SAM4S-Datasheet_09-Jun-15
1020
• CES: Counter Event Selection
The bit CES defines when the cha nn e l coun te r ev en t occurs when the period is center-aligned (flag CHIDx in PWM Inter-
rupt Status Register 1).
CALG = 0 (Left Alignme n t):
0/1: The channel counter event occurs at the end of the PWM period.
CALG = 1 (Center Alignment):
0: The channel counter event occurs at the end of the PWM period.
1: The channel counter event occurs at the end of the PWM period and at half the PWM period.
• DTE: Dead-Time Generator Enable
0: The dead-time generator is disabled.
1: The dead-tim e ge n er at or is enab le d.
• DTHI: Dead-Time PWMHx Output Inverted
0: The dead-tim e PWM Hx ou tp ut is not inve r ted .
1: The dead-tim e PWM Hx ou tp ut is inver te d.
• DTLI: Dead-Time PWMLx Output Inverted
0: The dead-time PWMLx output is not inverted.
1: The dead-time PWMLx output is inverted.
1021
SAM4S Series [DATASHEET]
Atmel-11100K-ATARM-SAM4S-Datasheet_09-Jun-15
39.7.37 PWM Channel Duty Cycle Register
Name: PWM_CDTYx [x=0..3]
Address: 0x40020204 [0], 0x40020224 [1], 0x40020244 [2], 0x40020264 [3]
Access: Read/Write
Only the first 16 bits (channel counter size) are signific an t.
• CDTY: Channel Duty-Cycle
Defines the waveform duty-cycle. This value must be defined between 0 and CPRD (PWM_CPRDx).
31 30 29 28 27 26 25 24
––––––––
23 22 21 20 19 18 17 16
CDTY
15 14 13 12 11 10 9 8
CDTY
76543210
CDTY
SAM4S Series [DATASHEET]
Atmel-11100K-ATARM-SAM4S-Datasheet_09-Jun-15
1022
39.7.38 PWM Channel Duty Cycle Update Register
Name: PWM_CDTYUPDx [x=0..3]
Address: 0x40020208 [0], 0x40020228 [1], 0x40020248 [2], 0x40020268 [3]
Access: Write-only.
This register acts as a double buffer for the CDTY value. This prevents an unexp e cte d wa ve fo rm whe n mo d ifyin g th e
waveform duty-cycle.
Only the first 16 bits (channel counter size) are signific an t.
• CDTYUPD: Channel Duty-Cycle Update
Defines the waveform duty-cycle. This value must be defined between 0 and CPRD (PWM_CPRDx).
31 30 29 28 27 26 25 24
––––––––
23 22 21 20 19 18 17 16
CDTYUPD
15 14 13 12 11 10 9 8
CDTYUPD
76543210
CDTYUPD
1023
SAM4S Series [DATASHEET]
Atmel-11100K-ATARM-SAM4S-Datasheet_09-Jun-15
39.7.39 PWM Channel Period Register
Name: PWM_CPRDx [x=0..3]
Address: 0x4002020C [0], 0x4002022C [1], 0x4002024C [2], 0x4002026C [3]
Access: Read/Write
This register can only be written if bits WPSWS3 and WPHWS3 are cleared in the PWM Write Protection Status Register.
Only the first 16 bits (channel counter size) are signific an t.
• CPRD: Channel Period
If the waveform is left-aligned, then the output waveform period depends on th e channel counter source clock and can be
calculated:
– By using the PWM periphera l clock divided by an X given prescaler value (with X being 1, 2, 4, 8, 16, 32, 64,
128, 256, 512, or 1024). The resulting period formula will be:
– By using the PWM peripher al clock divided by one of both DIVA or DIVB divider, the formula becomes,
respectively:
or
If the waveform is center-aligned, then the output waveform period depends on the channel counter source clock and can
be calculated:
– By using the PWM periphera l clock divided by an X given prescaler value (with X being 1, 2, 4, 8, 16, 32, 64,
128, 256, 512, or 1024). The resulting period formula will be:
– By using the PWM peripher al clock divided by one of both DIVA or DIVB divider, the formula becomes,
respectively:
or
31 30 29 28 27 26 25 24
––––––––
23 22 21 20 19 18 17 16
CPRD
15 14 13 12 11 10 9 8
CPRD
76543210
CPRD
XCPRD×()
fperipheral clock
--------------------------------
CRPD DIVA×()
fperipheral clock
------------------------------------------
CRPD DIVB×()
fperipheral clock
------------------------------------------
2XCPRD××()
fperipheral clock
----------------------------------------
2CPRD DIVA××()
fperipheral clock
---------------------------------------------------
2CPRD×DIVB×()
fperipheral clock
---------------------------------------------------
SAM4S Series [DATASHEET]
Atmel-11100K-ATARM-SAM4S-Datasheet_09-Jun-15
1024
39.7.40 PWM Channel Period Update Register
Name: PWM_CPRDUPDx [x=0..3]
Address: 0x40020210 [0], 0x40020230 [1], 0x40020250 [2], 0x40020270 [3]
Access: Write-only
This register can only be written if bits WPSWS3 and WPHWS3 are cleared in the PWM Write Protection Status Register.
This register acts as a double buffer for the CPRD value. This prevents an unexpected waveform when modifying the
waveform period.
Only the first 16 bits (channel counter size) are signific an t.
• CPRDUPD: Channel Period Update
If the waveform is left-aligned, then the output waveform period depends on th e channel counter source clock and can be
calculated:
– By using the PWM periphera l clock divided by an X given prescaler value (with X being 1, 2, 4, 8, 16, 32, 64,
128, 256, 512, or 1024). The resulting period formula will be:
– By using the PWM peripher al clock divided by one of both DIVA or DIVB divider, the formula becomes,
respectively:
or
If the waveform is center-aligned, then the output waveform period depends on the channel counter source clock and can
be calculated:
– By using the PWM periphera l clock divided by an X given prescaler value (with X being 1, 2, 4, 8, 16, 32, 64,
128, 256, 512, or 1024). The resulting period formula will be:
– By using the PWM peripher al clock divided by one of both DIVA or DIVB divider, the formula becomes,
respectively:
or
31 30 29 28 27 26 25 24
––––––––
23 22 21 20 19 18 17 16
CPRDUPD
15 14 13 12 11 10 9 8
CPRDUPD
76543210
CPRDUPD
X CPRDUPD×()
fperipheral clock
--------------------------------------------
CRPDUPD DIVA×()
fperipheral clock
--------------------------------------------------------
CRPDUPD DIVB×()
fperipheral clock
--------------------------------------------------------
2X CPRDUPD××()
fperipheral clock
------------------------------------------------------
2CPRDUPD DIVA××()
fperipheral clock
-----------------------------------------------------------------
2CPRDUPD×DIVB×()
fperipheral clock
-----------------------------------------------------------------
1025
SAM4S Series [DATASHEET]
Atmel-11100K-ATARM-SAM4S-Datasheet_09-Jun-15
39.7.41 PWM Channel Counter Register
Name: PWM_CCNTx [x=0..3]
Address: 0x40020214 [0], 0x40020234 [1], 0x40020254 [2], 0x40020274 [3]
Access: Read-only
Only the first 16 bits (channel counter size) are signific an t.
• CNT: Channel Counter Register
Channel counter value. This register is reset when:
• the channel is enabled (writing CHIDx in the PWM_ENA register ).
• the channel co un te r re ac he s C PRD value defined in th e PWM_CPRDx register if the waveform is left-aligned.
31 30 29 28 27 26 25 24
––––––––
23 22 21 20 19 18 17 16
CNT
15 14 13 12 11 10 9 8
CNT
76543210
CNT
SAM4S Series [DATASHEET]
Atmel-11100K-ATARM-SAM4S-Datasheet_09-Jun-15
1026
39.7.42 PWM Channel Dead Time Register
Name: PWM_DTx [x=0..3]
Address: 0x40020218 [0], 0x40020238 [1], 0x40020258 [2], 0x40020278 [3]
Access: Read/Write
This register can only be written if bits WPSWS4 and WPHWS4 are cleared in the PWM Write Protection Status Register.
Only the first 12 bits (dead-time counter size) of fields DTH and DTL are significant.
• DTH: Dead-Time Value for PWMHx Output
Defines the dead-time value for PWMHx output. This value must be defined between 0 and the value (CPRD – CDTY)
(PWM_CPRDx and PWM_CDTYx).
• DTL: Dead-Time Value for PWMLx Output
Defines the dead-time value for PWMLx output. This value must be defined betwee n 0 and CDTY (PWM_CDTYx).
31 30 29 28 27 26 25 24
DTL
23 22 21 20 19 18 17 16
DTL
15 14 13 12 11 10 9 8
DTH
76543210
DTH
1027
SAM4S Series [DATASHEET]
Atmel-11100K-ATARM-SAM4S-Datasheet_09-Jun-15
39.7.43 PWM Channel Dead Time Update Register
Name: PWM_DTUPDx [x=0..3]
Address: 0x4002021C [0], 0x4002023C [1], 0x4002025C [2], 0x4002027C [3]
Access: Write-only
This register can only be written if bits WPSWS4 and WPHWS4 are cleared in the PWM Write Protection Status Register.
This register acts as a double buffer for the DTH and DTL values. This prevents an unexpected waveform wh en modifying
the dead-time values.
Only the first 12 bits (dead-time counter size) of fields DTHUPD and DTLUPD are significant.
• DTHUPD: Dead-Time Value Update for PWMHx Output
Defines the dead-time value for PWMHx output. This value must be defined between 0 and the value (CPRD – CDTY)
(PWM_CPRDx and PWM_CDTYx). This value is applied only at the beginning of the next channel x PWM period.
• DTLUPD: Dead-Time Value Update fo r PWMLx Output
Defines the dead-time value for PWMLx output. This value must be defined between 0 and CDTY (PWM_CDTYx). This
value is applied only at th e be gin n ing of the next channel x PWM period.
31 30 29 28 27 26 25 24
DTLUPD
23 22 21 20 19 18 17 16
DTLUPD
15 14 13 12 11 10 9 8
DTHUPD
76543210
DTHUPD
SAM4S Series [DATASHEET]
Atmel-11100K-ATARM-SAM4S-Datasheet_09-Jun-15
1028
40. USB Device Port (UDP)
40.1 Description
The USB Device Port (UDP) is compliant with the Universal Serial Bus (USB) 2.0 full-speed device specification.
Each endpoint can be configured in one of several USB transfer types. It can be associated with one or two banks
of a dual-port RAM used to store the current data payload. If two banks are used, one DPR bank is read or written
by the processor, while the other is read or written by the USB device per ipheral. This feature is mandatory for
isochronous endpoints. Thus the device maintains the maximum bandwidth (1 Mbyte/s) by working with endpoints
with two banks of DPR.
Note: 1. The Dual-Bank function provides two banks for an endpoint. This feature is used for ping-pong mode.
Suspend and resume are automatically detected by the USB device, which notifies the processor by raising an
interrupt. Depending on the product, an external signal can be used to send a wakeup request to the USB host
controller.
40.2 Embedded Characteristics
USB 2.0 Full-speed Compliant, 12 Mbit/s
Embedded USB 2.0 Full-speed Transceiver
Integrated Pull-up on DDP
Integrated Pull-down on DDM
8 Endpoints
Embedded Dual-port RAM for Endpoints
Suspend/Resume Logic
Ping-pong Mode (2 Memory Banks) for Isochronous and Bulk Endpoints
Table 40-1. USB Endpoint Description
Endpoint No. Mne monic Dual-Bank(1) Max. Endpoint Size Endpoint Type
0 EP0 No 64 Control/Bulk/Interrupt
1 EP1 Yes 64 Bulk/Iso/Interrupt
2 EP2 Yes 64 Bulk/Iso/Interrupt
3 EP3 No 64 Control/Bulk/Interrupt
4 EP4 Yes 512 Bulk/Iso/Interrupt
5 EP5 Yes 512 Bulk/Iso/Interrupt
6 EP6 Yes 64 Bulk/Iso/Interrupt
7 EP7 Yes 64 Bulk/Iso/Interrupt
1029
SAM4S Series [DATASHEET]
Atmel-11100K-ATARM-SAM4S-Datasheet_09-Jun-15
40.3 Block Diagram
Figure 40-1. Block Diagram
Access to the UDP is via the APB bus interface. Read and write to the data FIFO are done by reading and writing
8-bit values to APB registers.
The UDP peripheral requires two clocks: one peripheral clock used by the Master Clock domain (MCK) and a 48
MHz clock (UDPCK) used by the 12 MHz domain.
A USB 2.0 full-speed pad is embedded and controlled by th e Ser i al Inte rfa c e Engine (S IE) .
The signal external_resume is optional. It allows the UDP peripheral to wake up once in system mode. The host is
then notified that the device asks for a resume. This optional feature must also be negotiated with the host during
the enumeration.
40.3.1 Signal Description
Atmel Bridge
12 MHz
Suspend/Resume Logic
Serial
Interface
Engine
SIE
MCK
Master Clock
Domain
Dual
Port
RAM
FIFO
UDPCK
Recovered 12 MHz
Domain
udp_int
(interrupt line)
USB Device
Embedded
USB
Transceiver
DDP
DDM
APB
to
MCU
Bus
txoen
eopn
txd
rxdm
rxd
rxdp
Wrapper
Wrapper
User
Interface
Table 40-2. Signal Names
Signal Name Description Type
UDPCK 48 MHz clock Input
MCK Master clock Input
udp_int Interrupt line connected to the Interru pt Controller Input
DDP USB D+ line I/O
DDM USB D- line I/O
SAM4S Series [DATASHEET]
Atmel-11100K-ATARM-SAM4S-Datasheet_09-Jun-15
1030
40.4 Product Dependencies
For further details on the USB Device hardware implementation, see the specific Product Properties document.
The USB physical transceiver is integrated into the product. The bidirectional differential signals DDP and DDM
are available from the product boundary.
One I/O line may be used by the application to check that VBUS is still available from the host. Self-po wered
devices may use this entry to be notified that the host has been powered off. In this case, the pull-up on DDP must
be disabled in order to prevent feeding current to the host. The application should disconnect the tran scei ve r, then
remove the pull-up.
40.4.1 I/O Lines
The USB pins are shared with PIO lines. By default, the USB function is activated, and pins DDP and DDM are
used for USB. To configure DDP or DDM as PIOs, the user needs to configure the system I/O configuration
register (CCFG_SYSIO) in the MATRIX.
40.4.2 Power Management
The USB device peripheral requires a 48 MHz clock. This clock must be generated by a PLL driven by a clock
source with an accuracy of ± 0.25% (note that the fast RC oscillator cannot be used).
Thus, the USB device receives two clocks from the Power Manag eme nt Contro ller (PMC): the master clock, MCK,
used to drive the per iph eral u ser interfa ce, an d th e UDPCK, used to interface with the bus USB signals (recovered
12 MHz domain).
WARNING: The UDP peripheral clock in the Power Management Controller (PMC) must be enabled before any
read/write operations to the UDP registers including the UDP_TXVC register.
40.4.3 Interrupt
The USB device interface has an interrupt line connected to the Interrupt Controller.
Handling the USB device inte rr up t re qu ire s pr og ra m m ing the Interrupt Controller before configuring the UDP.
40.5 Typical Connection
Figure 40-2. Board Schematic to Interface Dev ice Peripheral
Table 40-3. Peripheral IDs
Instance ID
UDP 34
REXT
REXT
DDM
DDP
PIO 27 K
47 K
Type B
Connector
12
34
5V Bus Monitoring
1031
SAM4S Series [DATASHEET]
Atmel-11100K-ATARM-SAM4S-Datasheet_09-Jun-15
40.5.1 USB Device Transceiver
The USB device transceiver is embedded in the product. However, discrete components are required for each of
the following actions:
to monitor VBUS voltage
for line termination
to disconnect the host for reduced power consumption
40.5.2 VBUS Monitoring
VBUS monitoring is required to detect host connection. VBUS monitoring is done using a standard PIO with
internal pull-up disabled. When the host is switched off, it should be cons idered as a disconnect, the pull-up must
be disabled in order to prevent powering the host through the pull-up resistor.
When the host is disconnected and the transceiver is enabled, then DDP and DDM are floating. This may lead to
over consumption. A solution is to enable the integrated pull-down by disabling the transceiver
(UDP_TXVC.TXVDIS = 1) and then remove the pull-up (UDP_TXVC.PUON = 0).
A termination serial resistor must be connected to DDP and DDM. The resistor value is defined in the electrical
specification of the product (REXT).
SAM4S Series [DATASHEET]
Atmel-11100K-ATARM-SAM4S-Datasheet_09-Jun-15
1032
40.6 Functional Description
40.6.1 USB 2.0 Full-speed Introduction
The USB 2.0 full-speed provides commu nication services between host and attached USB devices. Each device is
offered with a collection of communication flows (pipes) associated with each endpoint. Software on the host
communicates with a USB device through a set of communication flows.
Figure 40-3 . Example of USB 2.0 Full-speed Communication Co ntro l
The Control Transfer endpoint EP0 is always used when a USB device is first configured (USB 2.0 specifications).
40.6.1.1 USB 2.0 Full-speed Transfer Types
A communication flow is carried over one of four transfer types defined by the USB device.
40.6.1.2 USB Bus Transactions
Each transfer results in one or more transactions over the USB bus. There are three kinds of transactions flowing
across the bus in packets:
Setup Transaction
Data IN Transaction
Data OUT Transaction
EP0
USB Host V2.0
Software Client 1 Software Client 2
Data Flow: Bulk Out Transfer
Data Flow: Bulk In Transfer
Data Flow: Control Transfer
Data Flow: Control Transfer
EP1
EP2
USB Device 2.0
Block 1
USB Device 2.0
Block 2
EP5
EP4
EP0
Data Flow: Isochronous In Transfer
Data Flow: Isochronous Out Transfer
USB Device endpoint configuration requires that
in the first instance Control Transfer must be EP0.
Table 40-4 . USB Communication Flow
Transfer Direction Bandwidth Supported
Endp oint Size Error Detection Retrying
Control Bidirectional Not guaranteed 8, 16, 32, 64 Yes Automatic
Isochronous Unidirectional Guaranteed 512 Yes No
Interrupt Unidirectional Not guaranteed ≤ 64 Yes Yes
Bulk Unidirectional Not guaranteed 8, 16, 32, 64 Yes Yes
1033
SAM4S Series [DATASHEET]
Atmel-11100K-ATARM-SAM4S-Datasheet_09-Jun-15
40.6.1.3 USB Transfer Event Definitions
As indicated below, transfers are sequential events carried out on the USB bus.
Notes: 1. Control transfer must use endpoints with no ping-pong attributes.
2. Isochronous transfers must use endpoints with ping-pong attributes.
3. Control transfers can be aborted using a stall handshake.
A status transaction is a special type of host-to-device tran saction used only in a control transfer. The control
transfer must be performed using endpoints with no ping-pong attributes. According to the control sequence (read
or write), the USB device sends or receives a status transaction.
Figure 40-4. Control Read an d Write Sequences
Notes: 1. During the Status IN stage, the host waits for a zero length packet (Data IN transaction with no data) from the
device using DATA1 PID. Refer to Chapter 8 of the Universal Serial Bus Specification, Rev. 2.0, for more
information on the protocol layer.
Table 40-5 . USB Transfer Events
Transfer
TransactionDirection Type
CONTROL (bidirectional) Control(1)(3)
Setup transaction → Data IN transactions → Status OUT transaction
Setup transaction → Data OUT transactions → Status IN transaction
Setup transaction → Status IN transaction
IN (device toward host)
Interrupt IN
Data IN transaction → Data IN transactionIsochronous IN(2)
Bulk IN
OUT (host toward device)
Interrupt OUT
Data OUT transaction → Data OUT transactionIsochronous OUT(2)
Bulk OUT
Control Read Setup TX Data OUT TX Data OUT TX
Data Stage
Control Write
Setup Stage
Setup Stage
Setup TX
Setup TX
No Data Control
Data IN TX Data IN TX
Status Stage
Status Stage
Status IN TX
Status OUT TX
Status IN TX
Data Stage
Setup Stage Status Stage
SAM4S Series [DATASHEET]
Atmel-11100K-ATARM-SAM4S-Datasheet_09-Jun-15
1034
2. During the Status OUT stage, the host emits a zero length packet to the device (Data OUT transaction with no
data).
40.6.2 Handling Transactions with USB 2.0 Device Peripheral
40.6.2.1 Setup Transaction
Setup is a special type of host-to-device transaction us ed during control transfers. Control transfers must be
performed using endpoints with no ping-pong attributes. A setup transaction needs to be handled as soon as
possible by the fir mware. It is used to transmit request s from the host to the device. Th ese requests are then
handled by the USB device and m ay require more arguments. The arguments are sent to the device by a Data
OUT transaction which follows the setup transaction. These requests may also return data. The data is car ried out
to the host by the next Data IN transaction which follows the setup transaction. A status transaction ends the
control transfer.
When a setup transfer is received by the USB endpoint:
The USB device automatically acknowledges the setup packet
RXSETUP is set in the UDP_CSRx
An endpoint interrupt is generated while the RXSETUP is not cleared. This interrupt is carried out to the
microcontr olle r if inte rr up ts are enab le d for this endpoint.
Thus, firmware must detect the RXSETUP polling the UDP_CSRx or catching an interrupt, read the setup packet
in the FIFO, then clear the RXSETUP. RXSETUP cannot be cleared before the setup packet has been read in the
FIFO. Otherwise, the USB device would accept the next Data OUT transfer and overwrite the setup packet in the
FIFO.
Figure 40-5. Setup Transaction Followed by a Data OUT Transaction
RX_Data_BKO
(UDP_CSRx)
ACK
PID
Data OUT
Data OUT
PID
NAK
PID
ACK
PID
Data SetupSetup PID
USB
Bus Packets
RXSETUP Flag
Set by USB Device Cleared by Firmware Set by USB
Device Peripheral
FIFO (DPR)
Content Data Setup Data
XX XX OUT
Interrupt Pending
Setup Received Setup Handled by Firmware Data Out Received
Data OUT
Data OUT
PID
1035
SAM4S Series [DATASHEET]
Atmel-11100K-ATARM-SAM4S-Datasheet_09-Jun-15
40.6.2.2 Data IN Transaction
Data IN transactions are used in control, isochronous, bulk and interrupt transfers and conduct the transfer of data
from the device to the host. Data IN transactions in isochronous transfer m ust be done usin g endp oints wit h ping-
pong attributes.
Using Endpoints Without Ping-pong Attributes
To perform a Data IN transaction using a non ping-pong endpoin t:
1. The application checks if it is possible to write in the FIFO by polling TXPKTRDY in the endpoint’s
UDP_CSRx (TXPKTRDY must be cleared).
2. The application writes the first packet of data to be sent in the endpoint’s FIFO, writing zero or more byte
values in the endpoint’s UDP_FDRx.
3. The application notifies the USB peripheral it has finished by setting the TXPKTRDY in the endpoint’s
UDP_CSRx.
4. The application is notified that the e nd point ’ s FIFO has been r eleased by the USB device when TXCOMP in
the endpoint’s UDP_CSRx has been set. Then an interrupt for the corresponding endpoint is pending while
TXCOMP is set.
5. The microcontroller writes the second packet of data to be sent in the endpoint’s FIFO, writing zero or more
byte values in the endpoint’s UDP_FDRx.
6. The microcontroller notifie s the USB peripheral it has finished by setting the TXPKTRDY in the endpoint’s
UDP_CSRx.
7. The application clears the TXCOMP in the endpoint’s UDP_CSRx.
After the last packet has been sent, the application must clear TXCOMP once this has been set.
TXCOMP is set by the USB device when it has received an ACK PID signal for the Data IN packet. An interrupt is
pending while TXCOMP is set.
Warning: TX_COMP must be cleared after TX_ PKTRDY has been set.
Note: Refe r to Chapter 8 of the Universal Serial Bus Specification, Rev 2.0, for more informatio n on the Data IN protocol
layer.
Figure 40-6. Data IN Transfer for Non Ping-pong Endpoint
USB Bus Packets Data IN 2
Data IN NAK
ACK
Data IN 1
FIFO (DPR)
Content Data IN 2Load In ProgressData IN 1
Cleared by Firmware
DPR access by the firmware
Payload in FIFO
TXCOMP Flag
(UDP_CSRx)
TXPKTRDY Flag
(UDP_CSRx)
PID
Data IN Data IN
PIDPID PIDPID ACK
PID
Prevous Data IN TX Microcontroller Load Data in FIFO Data is Sent on USB Bus
Interrupt
Pending
Interrupt Pending
Set by the firmware Set by the firmware
Cleared by
Firmware
Cleared by HW
Cleared by HW
DPR access by the hardware
SAM4S Series [DATASHEET]
Atmel-11100K-ATARM-SAM4S-Datasheet_09-Jun-15
1036
Using Endpoints With Ping-pong Attribute
The use of an endpoint with ping-pong attributes is necessary during isochronous transfer. This also allows
handling the maximum ba ndwidth defined in the USB specification during bu lk transfer. To be able to guarantee a
constant or the maximum bandwidth, the microcontroller must prepare the next data payload to be sent while the
current one is being sent by the USB device. Thus two banks of memory are used. While one is available for the
microcontroller, the other one is locked by the USB device.
Figure 40-7. Bank Swapping Data IN Transfer for Ping-pong Endpoints
When using a ping-pong endpoint, the following procedures are required to perform Data IN transactions:
1. The microcontroller checks if it is possible to write in the FIFO by polling TXPKTRDY to be cleared in the
endpoint’s UDP_CSRx.
2. The microcontroller writes the first data payload to be sent in the FIFO (Bank 0), writing zero or more byte
values in the endpoint’s UDP_FDRx.
3. The microcontroller notifie s the USB peripheral it has finished writing in Bank 0 of the FIFO by setting the
TXPKTRDY in the endpoint’s UDP_CSRx.
4. Without waiting for TXPKTRDY to be cleared, the microcontroller writes the second data payload to be sent
in the FIFO (Bank 1), writing zero or more byte values in the endpoint’s UDP_FDRx.
5. The microcontroller is notified that the first Bank h as been released by the USB device when TXCOMP in the
endpoint’s UDP_CSRx is set. An interrupt is pending while TXCOMP is being set.
6. Once the microcontroller has received TXCOMP for the first Bank, it notifies the USB device that it has
prepared the second Bank to be sent, raising TXPKTRDY in the endpoint’s UDP_CSRx.
7. At this step, Bank 0 is available and the microcontro ller can prepare a third data payload to be sent.
USB Device USB Bus
Read
Write
1st Data Payload
2nd Data Payload
3rd Data Payload
3rd Data Payload
2nd Data Payload
1st Data Payload
Data IN Packet
Data IN Packet
Data IN Packet
Microcontroller
Endpoint 1
Bank 0
Endpoint 1
Bank 1
Endpoint 1
Bank 0
Endpoint 1
Bank 0
Endpoint 1
Bank 0
Endpoint 1
Bank 1
Simultaneous
Write and Read
1037
SAM4S Series [DATASHEET]
Atmel-11100K-ATARM-SAM4S-Datasheet_09-Jun-15
Figure 40-8. Data IN Transfer for Ping-pong Endpoint
Warning: There is software critical path due to the fact that once the second bank is filled, the driver has to wait for
TX_COMP to set TX_PKTRDY. If the delay between receiving TX_COMP is set and TX_PKTRDY is set too long,
some Data IN packets may be NACKed, reducing the bandwidth.
Warning: TX_COMP must be cleared after TX_ PKTRDY has been set.
40.6.2.3 Data OUT Transaction
Data OUT transactions are used in control, isochronous, bulk and interrupt transfers and conduct the transfer of
data from the host to the device. Data OUT transa ctions in isochronous transf ers must be done using en dpoints
with ping-pong attributes.
Data OUT Transaction Without Ping-pong Attributes
To perform a Data OUT transaction, using a non ping-pong endpo int:
1. The host generates a Data OUT packet.
2. This packet is received by the USB device endpoin t. While the FIFO associated to this endpoint is being
used by the microcontroller, a NAK PID is returned to the host. Once the FIFO is available, data are written
to the FIFO by the USB device and an ACK is automatically carried out to the host.
3. The microcontroller is notified that the USB device has received a data pa yload polling RX_DATA_BK0 in the
endpoint’s UDP_CSRx. An interrupt is pending for this endpoint while RX_DATA_BK0 is set.
4. The number of bytes available in the FIFO is made available by reading RXBYTECNT in the endpoint’s
UDP_CSRx.
5. The microcontroller carrie s out data received from the endpoint’s memory to its memory. Data received is
available by reading the endpoint’s UDP_FDRx.
6. The microcontroller notifies th e USB device that it has finished the transfer by clearing RX_DATA_BK0 in the
endpoint’s UDP_CSRx.
7. A new Data OUT packet can be accepted by the USB device.
Data INData IN
Read by USB Device
Read by USB Device
FIFO (DPR)
Bank 0
TXCOMP Flag
(UDP_CSRx) Interrupt Cleared by Firmware
Set by USB
Device
TXPKTRDY Flag
(UDP_MCSRx)
ACK
PID Data IN
PID ACK
PID
Set by Firmware,
Data Payload Written in FIFO Bank 1
Cleared by USB Device,
Data Payload Fully Transmitted
Data IN
PID
USB Bus
Packets
Set by USB Device
Set by Firmware,
Data Payload Written in FIFO Bank 0
Written by MCU
FIFO (DPR)
Bank 1
Written by MCU Written by MCU
Microcontroller
Load Data IN Bank 0 Microcontroller Load Data IN Bank 1
USB Device Send Bank 0 Microcontroller Load Data IN Bank 0
USB Device Send Bank 1
Interrupt Pending
SAM4S Series [DATASHEET]
Atmel-11100K-ATARM-SAM4S-Datasheet_09-Jun-15
1038
Figure 40-9. Data OUT Transfer for Non Ping-pong En dpoints
An interrupt is pending while the flag RX_DATA_BK0 is set. Memory tr ansfer between the USB device, the FIFO
and microcontroller memory is not possible after RX_DATA_BK0 has been cleared. Otherwise, the USB device
would accep t th e ne xt Data OU T tran sfer and overwrite the current Data OUT packet in the FIFO .
Using Endpoints With Ping-pong Attributes
During isochronous transfer, using an endpoint with p ing-pong attributes is obligatory. To be able to guarantee a
constant bandwidth, the microcontroller must read the previous data payload sent by the host, while the current
data payload is received by the USB device. Thus two banks of memory are used. Wh ile one is available for the
microcontroller, the other one is locked by the USB device.
Figure 40-10. Bank Swap ping in Data OUT Transfers for Ping-po ng Endpoints
When using a ping-pong endpoint, the following procedures are required to perform Data OUT transactions:
1. The host generates a Data OUT packet.
2. This packet is received by the USB device endpoint. It is written in the endpoint’s FIFO Bank 0.
3. The USB device sends an ACK PID packet to the host. The ho st can imm edia te ly se nd a se co nd Da ta OUT
packet. It is accepted by the device and copied to FIFO Bank 1.
4. The microcontroller is notified that the USB device has received a data payload, polling RX_DATA_BK0 in
the endpoint’s UDP_CSRx. An interru pt is pending for this endpoint while RX_DATA_BK0 is set.
ACK
PID
Data OUTNAK PIDPIDPIDPIDPID Data OUT2ACKData OUT Data OUT 1
USB Bus
Packets
RX_DATA_BK0
Set by USB Device Cleared by Firmware,
Data Payload Written in FIFO
FIFO (DPR)
Content Written by USB Device Microcontroller Read
Data OUT 1 Data OUT 1 Data OUT 2
Host Resends the Next Data Payload
Microcontroller Transfers Data
Host Sends Data Payload
Data OUT2 Data OUT2
Host Sends the Next Data Payload
Written by USB Device
(UDP_CSRx) Interrupt Pending
USB Device USB Bus
Read
Write
Simultaneous
Write and Read
1st Data Payload
2nd Data Payload
3rd Data Payload
3rd Data Payload
2nd Data Payload
1st Data Payload
Data IN Packet
Data IN Packet
Data IN Packet
Microcontroller
Endpoint 1
Bank 0
Endpoint 1
Bank 1
Endpoint 1
Bank 0
Endpoint 1
Bank 0
Endpoint 1
Bank 0
Endpoint 1
Bank 1
1039
SAM4S Series [DATASHEET]
Atmel-11100K-ATARM-SAM4S-Datasheet_09-Jun-15
5. The number of bytes available in the FIFO is made available by reading RXBYTECNT in the endpoint’s
UDP_CSRx.
6. The microcontroller transfers out data re ceived from the endpoint’ s memory to the microcon troller’s memory.
Data received is made available by reading the endpoint’ s UDP_FDRx.
7. The microcontroller notifie s the USB peripheral device that it has finished the transfer by clearing
RX_DATA_BK0 in the endpoint’s UDP_CSRx.
8. A third Data OUT packet can be accepted by the USB peripher al device and copied in the FIFO Bank 0.
9. If a second Data OUT p acket has been received, the microcontroller is notified by the flag RX_DATA_BK1
set in the endpoint’s UDP_CSRx. An interrupt is pending for this endpoint while RX_DATA_BK1 is set.
10. The microcontroller transfers out dat a received from the end point’s memory to the mi crocontroller’s memory.
Data received is available by reading the endpoint’s UDP_FDRx.
11. The microcontroller notifies the USB device it has finished the transfer by clearing RX_DATA_BK1 in the
endpoint’s UDP_CSRx.
12. A fourth Data OUT pa cket can be accepted by the USB device and copied in the FIFO Bank 1.
Figure 40-11. Data OUT Transfer for Ping-pong Endp oint
Note: An interrupt is pending whil e the RX_DATA_BK0 or RX_DATA_BK1 flag is set.
Warning: When RX_DATA_BK0 and RX_DATA_BK1 are both set, there is no way to determine which one to
clear first. Thus the software must keep an internal counter to be sure to clear alternatively RX_DATA_BK0 then
RX_DATA_BK1. This situation may occur when the software application is busy elsewhere and the two banks are
filled by the USB host. Once the application comes back to the USB driver, the two flags are set.
A
Data OUT PID
ACK Data OUT 3
Data OUT
Data OUT 2
Data OUT
Data OUT 1
PID
Data OUT 3Data OUT 1Data OUT1
Data OUT 2 Data OUT 2
PID PID PID
ACK
Cleared by Firmware
USB Bus
Packets
RX_DATA_BK0 Flag
RX_DATA_BK1 Flag
Set by USB Device,
Data Payload Written
in FIFO Endpoint Bank 1
FIFO (DPR)
Bank 0
Bank 1
Write by USB Device Write In Progress
Read By Microcontroller
Read By Microcontroller
Set by USB Device,
Data Payload Written
in FIFO Endpoint Bank 0
Host Sends First Data Payload Microcontroller Reads Data1 in Bank 0,
Host Sends Second Data Payload Microcontroller Reads Data2 in Bank 1,
Host Sends Third Data Payload
Cleared by Firmware
Write by USB Device
FIFO (DPR)
(UDP_CSRx)
(UDP_CSRx)
Interrupt Pending
Interrupt Pending
SAM4S Series [DATASHEET]
Atmel-11100K-ATARM-SAM4S-Datasheet_09-Jun-15
1040
40.6.2.4 Stall Handshake
A stall handshake can be used in one of two distinct occasions. (For more information on the stall handshake, refe r
to Chapter 8 of the Universal Serial Bus Specification, Rev 2.0.)
A functional stall is used when the halt feature associated with the endpoint is set. (Refer to Chapter 9 of the
Universal Serial Bus Specification, Rev 2.0, for more information on the halt feature.)
To abort the current request, a protocol stall is used, but uniquely with control transfer.
The following procedure generates a stall packet:
1. The microcontroller sets the FORCESTALL flag in the UDP_CSRx endpoint’s register.
2. The host receives the stall packet.
3. The microcontroller is notified that the device has sent the stall by polling the STALLSENT to be set. An
endpoint interrupt is pending while STALLSENT is set. The microcontroller must clear STALLSENT to clear
the interrupt.
When a setup transaction is received after a stall handshake, STALLSENT must be clea red in order to prevent
interrupts due to STALLSENT being set.
Figure 40-12. Sta ll Handshake (Data IN Transfer)
Figure 40-13. Sta ll Handshake (Data OUT Transfer)
Data IN Stall PIDPID
USB Bus
Packets
Cleared by Firmware
Set by Firmware
FORCESTALL
STALLSENT Set by
USB Device
Cleared by Firmware
Interrupt Pending
Data OUT PID Stall PID
Data OUT
USB Bus
Packets
Cleared by Firmware
Set by Firmware
FORCESTALL
STALLSENT
Set by USB Device
Interrupt Pending
1041
SAM4S Series [DATASHEET]
Atmel-11100K-ATARM-SAM4S-Datasheet_09-Jun-15
40.6.2.5 Transmit Data Cancellation
Some endpoints have dual-banks whereas some endpoints have only one bank. The procedure to cancel
transmission data held in these banks is described below.
To see the organization of dual-bank availability refer to Table 40-1 ”USB Endpoint Description”.
Endpoints Without Dual-Banks
The cancellation procedure depends on the TXPKTRDY flag value in the UDP_CSR:
TXPKTRDY is not set:
Reset the endpoint to clear the FIFO (pointers). (See Section 40.7.9 ”UDP Reset Endpoint Register”.)
TXPKTRDY has already been set:
Clear TXPK TR DY s o that no packet is read y to be sen t
Reset the endpoint to clear the FIFO (pointers). (See Section 40.7.9 ”UDP Reset Endpoint Register”.)
Endpoints With Dual-Banks
The cancellation procedure depends on the TXPKTRDY flag value in the UDP_CSR:
TXPKTRDY is not set:
Reset the endpoint to clear the FIFO (pointers). (See Section 40.7.9 ”UDP Reset Endpoint Register”.)
TXPKTRDY has already been set:
Clear TXPKTRDY and read it back until actually read at 0.
Set TXPKTRDY and read it back until actually read at 1.
Clear TXPK TR DY s o that no packet is read y to be sen t.
Reset the endpoint to clear the FIFO (pointers). (See Section 40.7.9 ”UDP Reset Endpoint Register”.)
SAM4S Series [DATASHEET]
Atmel-11100K-ATARM-SAM4S-Datasheet_09-Jun-15
1042
40.6.3 Controlling Device States
A USB device has several possible states. Refer to Chapter 9 of the Universal Serial Bus Specification, Rev 2.0.
Figure 40-14. USB Device State Diagram
Movement from one state to another depends on the USB bus state or on standard requests sent through control
transactions via the default endpoint (endpoint 0).
After a period of bus inactivity, the USB device enters Suspend Mode. Accepting Suspend/Resume requests from
the USB host is mandato ry. Constraints in Suspend Mode are very strict for bus-powered applications; devices
must not consume more than 2.5 mA on the USB bus.
While in Suspend Mode, the host may wake up a device by sending a resume signal (bus activity) or a USB device
may send a wakeup request to the host, e.g., waking up a PC by moving a USB mouse.
The wakeup feature is not mandatory for all devices and must be negotiated with the host.
40.6.3.1 Not Powered State
Self powered devices can detect 5V VBUS using a PIO as described in the typical connection section. When the
device is not connected to a host, device power consumption can be reduced by disabling MCK for the UDP,
disabling UDPCK and disabling the transceiver . DDP and DDM lines are pulled down by 330 KΩ resistors.
Attached
Suspended
Suspended
Suspended
Suspended
Hub Reset
or
Deconfigured
Hub
Configured
Bus Inactive
Bus Activity
Bus Inactive
Bus Activity
Bus Inactive
Bus Activity
Bus Inactive
Bus Activity
Reset
Reset
Address
Assigned
Device
Deconfigured Device
Configured
Powered
Default
Address
Configured
Power
Interruption
1043
SAM4S Series [DATASHEET]
Atmel-11100K-ATARM-SAM4S-Datasheet_09-Jun-15
40.6.3.2 Entering Attached State
To enable integrated pull-up, the PUON bit in the UDP_TXVC register must be set.
Warning: To write to the UDP_TXVC register, MCK clock must be enabled on the UDP. This is done in the Power
Managemen t Co nt ro ller .
After pull-up connectio n, th e device enter s the po were d st ate. In this state, the UDPCK and MCK must be enabled
in the Power Management Controller. The transceiver can remain disabled.
40.6.3.3 From Powered State to Default State
After its connection to a USB host, the USB device waits for an end-of-bus reset. The unmaskable flag
ENDBUSRES is set in the UDP_ISR and an interrupt is triggered.
Once the ENDBUSRES interrupt has been triggered, the device enters Default State. In this state, the UDP
software must:
Enable the default endpoint, setting the EPEDS flag in the UDP_CSR0 and, optionally, enabling the interrupt
for endpoint 0 by writing 1 to the UDP_IER. The enumeration then begins by a control transfer.
Configure the interrupt mask register which has been reset by the USB reset detection
Enable the transceiver clearing the TXVDIS flag in the UDP_TXVC register.
In this state UDPCK and MCK must be enabled.
Warning: Each time an ENDBUSRES interrupt is triggered, the Interrupt Mask Register and UDP_CSRs have
been reset.
40.6.3.4 From Default State to Address State
After a set address standard device request, the USB host peripheral enters the address state.
Warning: Before the device enters in address state, it must achieve th e Status IN transaction of the control
transfer, i.e., the UDP device sets its new address once the TXCOMP flag in the UDP_CSR0 has been received
and cleared.
To move to address state, the driver software sets the FADDEN flag in the UDP_GLB_STAT register, sets its new
address, and sets the FEN bit in the UDP_FADDR register.
40.6.3.5 From Address State to Configured State
Once a valid Set Configuration standard request has been received and acknowledged, the device enables
endpoints corresponding to the current configuration. This is done by setting the EPEDS and EPTYPE fields in the
UDP_CSRx and, optionally, enabling corresponding interrupts in the UDP_IER.
40.6.3.6 Entering in Suspend State
When a Suspend (no bus activity on the USB bus) is detected, the RXSUSP signal in the UDP_ISR is set. This
triggers an interrupt if the corresponding bit is set in the UDP_IMR. This flag is cleared by writing to the UDP_ICR.
Then the device enters Suspend Mode.
In this state bus powered devices must drain no more than 2.5 mA from the 5V VBUS. As an example, the
microcontroller switches to slow clock, disables the PLL and main oscillator, and goes into Idle Mode. It may also
switch off other devices on the board.
The USB device peripheral clocks can be switched off. Resume event is asynchronously detected. MCK and
UDPCK can be switched off in the Power Management controller and the USB transceiver can be disabled by
setting the TXVDIS bit in the UDP_TXVC register.
Warning: Read, write operations to the UDP registers are allowed only if MCK is enabled for the UDP peripheral.
Switching off MCK for the UDP peripheral m ust be one of the last operations after writing to the UDP_TXVC
register and acknowledging the RXSUSP.
SAM4S Series [DATASHEET]
Atmel-11100K-ATARM-SAM4S-Datasheet_09-Jun-15
1044
40.6.3.7 Receiving a Host Resume
In suspend mode, a resume event on the USB bus lin e is detected asynchronously, transceiver and clocks are
disabled (however the pull-up shall not be removed).
Once the resume is detected on the bus, the WAKEUP signal in the UDP_ISR is set. It may generate an interrupt
if the corresponding bit in the UDP_IMR is set. T his interrupt may be used to wake up the core , enable PLL and
main oscillators and configure clocks.
Warning: Read, write operations to the UDP registers are allowed only if MCK is enabled for the UDP peripheral.
MCK for the UDP must be enabled before clearing the WAKEUP bit in the UDP_ICR and clearing TXVDIS in the
UDP_TXVC register.
40.6.3.8 Sending a Device Remote Wakeup Request
In Suspend state it is possible to wake up the host sending an external resume.
The device must wait at least 5 ms after being entered in suspend before sendin g an external resume.
The device has 10 ms from the moment it starts to drain current and it forces a K state to resume the host.
The device must force a K state from 1 to 15 ms to resume the host
Before sending a K state to the host, MCK, UDPCK and the transceiver must be enabled. The n to enable the
remote wakeup feature, the RMWUPE bit in the UDP_GLB_STAT register must be enabled. To force the K state
on the line, a transition of the ESR bit from 0 to 1 has to be done in the UDP_GLB_STAT register by first writing a
0 in the ESR bit and then writing a 1.
The K state is automatically generated and released according to th e USB 2.0 spe cific at ion .
1045
SAM4S Series [DATASHEET]
Atmel-11100K-ATARM-SAM4S-Datasheet_09-Jun-15
40.7 USB Device Port (UDP) User Interface
WARNING: The UDP pe ripheral clock in the Power Manageme nt Controller (PMC) m ust be enabled before any r ead/write
operations to the UDP registers, including the UDP_TXVC register.
Notes: 1. Reset values are not defined for UDP_ISR or UDP_FDRx. UDP_FDRs reflect Dual Port RAM memory locations which are
not affected by any reset signals.
2. See Warnin g above the ”Register Mapping” on this page.
Table 40-6 . Register Mapping
Offset Register Name Access Reset
0x000 Frame Number Register UDP_FRM_NUM Read-only 0x0000_0000
0x004 Glo bal State Register UDP_GLB_STAT Re ad/Write 0x0000_0010
0x008 Function Address Register UDP_FADDR Read/Write 0x0000_0100
0x00C Reserved – – –
0x010 Interrupt Enable Register UDP_IER Write-only
0x014 Interrupt Disable Reg ister UDP_IDR Write-only
0x018 Interrupt Mask Register UDP_IMR Read-only 0x0000_1200
0x01C Interrupt Status Register UDP_ISR Read-only –(1)
0x020 Interrupt Cle ar Register UDP_ICR Write-only
0x024 Reserved – – –
0x028 Reset Endpoint Register UDP_RST_EP Read/Write 0x0000_0000
0x02C Reserved – – –
0x030 Endpoint Control and Status Register 0 UDP_CSR0 Read/Write 0x0000_0000
... ... ... ... ...
0x030 + 0x4 * 7 Endpoint Control and Status Register 7 UDP_CSR7 Read/Write 0x0000_0000
0x050 Endpoint FIFO Data Register 0 UDP_FDR0 Read/Write –(1)
... ... ... ... ...
0x050 + 0x4 * 7 Endpoint FIFO Data Register 7 UDP_FDR7 Read/Wr ite –(1)
0x070 Reserved – – –
0x074 Transceiver Control Register UDP_TXVC(2) Read/Write 0x0000_0100
0x078–0xFC Reserved – – –
SAM4S Series [DATASHEET]
Atmel-11100K-ATARM-SAM4S-Datasheet_09-Jun-15
1046
40.7.1 UDP Frame Number Register
Name: UDP_FRM_NUM
Address: 0x40034000
Access: Read-only
• FRM_NUM[10:0]: Frame Number as Defined in the Packet Field Formats
This 11-bit value is incremented by the host on a per frame basis. This value is updated at each start of frame.
Value updated at the SOF_EOP (Start of Frame End of Packet).
• FRM_ERR: Frame Error
This bit is set at SOF_EOP when the SOF packet is received containing an error.
This bit is reset upon receipt of SOF_PID.
• FRM_OK: Frame OK
This bit is set at SOF_EOP when the SOF packet is received without any error.
This bit is reset upon receipt of SOF_PID (Packet Identification).
In the Interrupt Status Register, the SOF interrupt is updated upon receiving SOF_PID. This bit is set without waiting for
EOP.
Note: In the 8-bit Register Interface, FRM_OK is bit 4 of FRM_NUM_H and FRM_ERR is bit 3 of FRM_NUM_L.
31 30 29 28 27 26 25 24
--- --- --- --- --- --- --- ---
23 22 21 20 19 18 17 16
––––––FRM_OKFRM_ERR
15 14 13 12 11 10 9 8
––––– FRM_NUM
76543210
FRM_NUM
1047
SAM4S Series [DATASHEET]
Atmel-11100K-ATARM-SAM4S-Datasheet_09-Jun-15
40.7.2 UDP Global State Register
Name: UDP_GLB_STAT
Address: 0x40034004
Access: Read/Write
This register is used to get and set the device state as specified in Cha pter 9 of the USB Serial Bus Specification, Rev.2.0.
• FADDEN: Function Address Enable
Read:
0: Device is not in address state
1: Device is in address state
Write:
0: No effect, only a reset can bring back a device to th e defa ult state .
1: Sets device in address state. This occurs after a successful Set Address request. Beforehand, the UDP_FADDR register
must have been initialized with Set Address parameters. Se t Ad dress m ust co mplete th e Status Stage befo re setting FAD-
DEN. Refer to chapter 9 of the Universal Serial Bus Specification, Rev. 2.0 for more details.
• CONFG: Configured
Read:
0: Device is not in configured state
1: Device is in configured state
Write:
0: Sets device in a non configured state
1: Sets device in configured state
The device is set in configured state when it is in address state and receives a successful Set Co nfiguration request. Refer
to Chapter 9 of the Universal Serial Bus Specification, Rev. 2.0 for more details.
• ESR: Enable Send Resume
0: Mandatory value prior to starting any Remote Wakeup procedure
1: Starts the Remote Wakeup procedure if this bit value was 0 and if RMWUPE is enabled
• RMWUPE: Remote Wakeup Enable
0: The Remote Wakeup feature of the device is disabled.
1: The Remote Wakeup feature of the device is enabled.
31 30 29 28 27 26 25 24
––––––––
23 22 21 20 19 18 17 16
––––––––
15 14 13 12 11 10 9 8
––––––––
76543210
– – – RMWUPE RSMINPR ESR CONFG FADDEN
SAM4S Series [DATASHEET]
Atmel-11100K-ATARM-SAM4S-Datasheet_09-Jun-15
1048
40.7.3 UDP Function Address Register
Name: UDP_FADDR
Address: 0x40034008
Access: Read/Write
• FADD[6:0 ]: Fu nct io n Ad d res s Value
The Function Address Value must be programmed by firmware once the device receives a set address request from the
host, and has achieved the status stage of the no-data control sequence. Refer to the Universal Serial Bus Specification,
Rev. 2.0 for more information. After power up or reset, the function address value is set to 0.
• FEN: Function Enable
Read:
0: Function endpoint disabled
1: Function endpoint enabled
Write:
0: Disables function endpoint
1: Default value
The Function Ena b le bit (F EN) allow s the micr oc on tr olle r to e nable or disable the function endpoints. The microcontroller
sets this bit after receipt of a reset from the host. Once this bit is set, the USB device is able to accept and transfer data
packets from and to the host.
31 30 29 28 27 26 25 24
––––––––
23 22 21 20 19 18 17 16
––––––––
15 14 13 12 11 10 9 8
–––––––FEN
76543210
–FADD
1049
SAM4S Series [DATASHEET]
Atmel-11100K-ATARM-SAM4S-Datasheet_09-Jun-15
40.7.4 UDP Interrupt Enable Register
Name: UDP_IER
Address: 0x40034010
Access: Write-only
• EP0INT: Enable Endpoint 0 Interrupt
• EP1INT: Enable Endpoint 1 Interrupt
• EP2INT: Enable Endpoint 2Interrupt
• EP3INT: Enable Endpoint 3 Interrupt
• EP4INT: Enable Endpoint 4 Interrupt
• EP5INT: Enable Endpoint 5 Interrupt
• EP6INT: Enable Endpoint 6 Interrupt
• EP7INT: Enable Endpoint 7 Interrupt
0: No effect
1: Enables corresponding Endpoint Interrupt
• RXSUSP: Enable UDP Suspend Interrupt
0: No effect
1: Enables UDP Suspend Interrupt
• RXRSM: Enable UDP Resume Interrupt
0: No effect
1: Enables UDP Resume Interrupt
31 30 29 28 27 26 25 24
––––––––
23 22 21 20 19 18 17 16
––––––––
15 14 13 12 11 10 9 8
– – WAKEUP – SOFINT EXTRSM RXRSM RXSUSP
76543210
EP7INT EP6INT EP5INT EP4INT EP3INT EP2INT EP1INT EP0INT
SAM4S Series [DATASHEET]
Atmel-11100K-ATARM-SAM4S-Datasheet_09-Jun-15
1050
• SOFINT: Enable Start Of Frame Interrupt
0: No effect
1: Enables Start Of Frame Interrupt
• WAKEUP: Enable UDP Bus Wakeup Interrupt
0: No effect
1: Enables USB bus Interrupt
1051
SAM4S Series [DATASHEET]
Atmel-11100K-ATARM-SAM4S-Datasheet_09-Jun-15
40.7.5 UDP Interrupt Disable Register
Name: UDP_IDR
Address: 0x40034014
Access: Write-only
• EP0INT: Disable Endpoint 0 Interrupt
• EP1INT: Disable Endpoint 1 Interrupt
• EP2INT: Disable Endpoint 2 Interrupt
• EP3INT: Disable Endpoint 3 Interrupt
• EP4INT: Disable Endpoint 4 Interrupt
• EP5INT: Disable Endpoint 5 Interrupt
• EP6INT: Disable Endpoint 6 Interrupt
• EP7INT: Disable Endpoint 7 Interrupt
0: No effect
1: Disables corresponding Endpoint Interrupt
• RXSUSP: Disable UDP Suspend Interrupt
0: No effect
1: Disables UDP Suspend Interrupt
• RXRSM: Disable UDP Resume Interrupt
0: No effect
1: Disables UDP Resume Interrupt
• SOFINT: Disable Start Of Frame Interrupt
0: No effect
1: Disables Start Of Frame Interrupt
31 30 29 28 27 26 25 24
––––––––
23 22 21 20 19 18 17 16
––––––––
15 14 13 12 11 10 9 8
– – WAKEUP – SOFINT EXTRSM RXRSM RXSUSP
76543210
EP7INT EP6INT EP5INT EP4INT EP3INT EP2INT EP1INT EP0INT
SAM4S Series [DATASHEET]
Atmel-11100K-ATARM-SAM4S-Datasheet_09-Jun-15
1052
• WAKEUP: Disable USB Bus Interrupt
0: No effect
1: Disables USB Bus Wakeup Interrupt
1053
SAM4S Series [DATASHEET]
Atmel-11100K-ATARM-SAM4S-Datasheet_09-Jun-15
40.7.6 UDP Interrupt Mask Register
Name: UDP_IMR
Address: 0x40034018
Access: Read-only
• EP0INT: Mask Endpoint 0 Interrupt
• EP1INT: Mask Endpoint 1 Interrupt
• EP2INT: Mask Endpoint 2 Interrupt
• EP3INT: Mask Endpoint 3 Interrupt
• EP4INT: Mask Endpoint 4 Interrupt
• EP5INT: Mask Endpoint 5 Interrupt
• EP6INT: Mask Endpoint 6 Interrupt
• EP7INT: Mask Endpoint 7 Interrupt
0: Corresponding Endpoint Interrupt is disabled
1: Corresponding Endpoint Interrupt is enabled
• RXSUSP: Mask UDP Suspend Interrupt
0: UDP Suspend Interrupt is disabled
1: UDP Suspend Interrupt is enabled
• RXRSM: Mask UDP Resume Interrupt.
0: UDP Resume Interrupt is disabled
1: UDP Resume Interrupt is enabled
• SOFINT: Mask Start Of Frame Interrupt
0: Start of Frame Interrupt is disabled
1: Start of Frame Interrupt is enabled
• BIT12: UDP_IMR Bit 12
Bit 12 of UDP_IMR cannot be masked and is always read at 1.
31 30 29 28 27 26 25 24
––––––––
23 22 21 20 19 18 17 16
––––––––
15 14 13 12 11 10 9 8
– – WAKEUP BIT12 SOFINT EXTRSM RXRSM RXSUSP
76543210
EP7INT EP6INT EP5INT EP4INT EP3INT EP2INT EP1INT EP0INT
SAM4S Series [DATASHEET]
Atmel-11100K-ATARM-SAM4S-Datasheet_09-Jun-15
1054
• WAKEUP: USB Bus W akeup Interrupt
0: USB Bus Wakeup Interrupt is disabled
1: USB Bus Wakeup Interrupt is enabled
Note: When the USB block is in suspend mode, the application may power down the USB logic. In this case, any USB HOST resume
request that is made must be taken into account and, thus, the reset value of the RXRSM bit of the register UDP_IMR is enabled.
1055
SAM4S Series [DATASHEET]
Atmel-11100K-ATARM-SAM4S-Datasheet_09-Jun-15
40.7.7 UDP Interrupt Status Register
Name: UDP_ISR
Address: 0x4003401C
Access: Read-only
• EP0INT: Endpoint 0 Interrupt Status
• EP1INT: Endpoint 1 Interrupt Status
• EP2INT: Endpoint 2 Interrupt Status
• EP3INT: Endpoint 3 Interrupt Status
• EP4INT: Endpoint 4 Interrupt Status
• EP5INT: Endpoint 5 Interrupt Status
• EP6INT: Endpoint 6 Interrupt Status
• EP7INT: Endpoint 7Interru pt Stat us
0: No Endpoint0 Interrupt pending
1: Endpoint0 Interrupt has been raised
Several signals can generate this interrupt. The reason can be found by reading UDP_CSR0:
RXSETUP set to 1
RX_DATA_BK0 set to 1
RX_DATA_BK1 set to 1
TXCOMP set to 1
STALLSENT set to 1
EP0INT is a sticky bit. Interrupt remains valid until EP0INT is cleared by writing in the corresponding UDP_CSR0 bit.
• RXSUSP: UDP Suspend Interrupt Status
0: No UDP Suspend Interrupt pending
1: UDP Suspend Interrupt has been raised
The USB device sets this bit when it detects no activity for 3 ms. The USB device enters Suspend mod e.
31 30 29 28 27 26 25 24
––––––––
23 22 21 20 19 18 17 16
––––––––
15 14 13 12 11 10 9 8
– – WAKEUP ENDBUSRES SOFINT EXTRSM RXRSM RXSUSP
76543210
EP7INT EP6INT EP5INT EP4INT EP3INT EP2INT EP1INT EP0INT
SAM4S Series [DATASHEET]
Atmel-11100K-ATARM-SAM4S-Datasheet_09-Jun-15
1056
• RXRSM: UDP Resume Interrupt Status
0: No UDP Resume Interrupt pending
1: UDP Resume Interrupt has been raised
The USB device sets this bit when a UDP resume signal is detected at its port.
After reset, the state of this bit is undefined, the application must clear this bit by setting the RXRSM flag in the UDP_ICR.
• SOFINT: Start of Frame Interrupt Status
0: No Start of Frame Interrupt pending
1: Start of Frame Interrupt has been raised
This interrupt is raised each time a SOF token has been detected. It can be used as a synchronization signal by using iso-
chronous endpoints.
• ENDBUSRES: End of BUS Reset Interrupt Status
0: No End of Bus Reset Interrupt pending
1: End of Bus Reset Interrupt has be en rais ed
This interrupt is raised at the end of a UDP reset sequence. The USB device must prepare to receive requ ests on the end-
point 0. The host starts the enumeration, then performs the configuration.
• WAKEUP: UDP Resume Interrupt Status
0: No Wakeup Interrupt pending
1: A Wakeup Interrupt (USB Host Sent a RESUME or RESET) occurred since the last clear.
After reset the state of this bit is undefined; the application must clear this bit by setting the WAKEUP flag in the UDP_ICR.
1057
SAM4S Series [DATASHEET]
Atmel-11100K-ATARM-SAM4S-Datasheet_09-Jun-15
40.7.8 UDP Interrupt Clear Register
Name: UDP_ICR
Address: 0x40034020
Access: Write-only
• RXSUSP: Clear UDP Suspend Interrupt
0: No effect
1: Clears UDP Suspend Interrupt
• RXRSM: Clear UDP Resume Interrupt
0: No effect
1: Clears UDP Resume Interrupt
• SOFINT: Clear Start Of Frame Interrupt
0: No effect
1: Clears Start Of Frame Interrupt
• ENDBUSRES: Clear End of Bus Reset Interrupt
0: No effect
1: Clears End of Bus Reset Interrupt
• WAKEUP: Clear Wakeup Interrupt
0: No effect
1: Clears Wakeup Interrupt
31 30 29 28 27 26 25 24
––––––––
23 22 21 20 19 18 17 16
––––––––
15 14 13 12 11 10 9 8
– – WAKEUP ENDBUSRES SOFINT EXTRSM RXRSM RXSUSP
76543210
––––––––
SAM4S Series [DATASHEET]
Atmel-11100K-ATARM-SAM4S-Datasheet_09-Jun-15
1058
40.7.9 UDP Reset Endpoint Register
Name: UDP_RST_EP
Address: 0x40034028
Access: Read/Write
• EP0: Reset Endpoint 0
• EP1: Reset Endpoint 1
• EP2: Reset Endpoint 2
• EP3: Reset Endpoint 3
• EP4: Reset Endpoint 4
• EP5: Reset Endpoint 5
• EP6: Reset Endpoint 6
• EP7: Reset Endpoint 7
This flag is used to reset the FIFO associated with the endpoint and the bit RXBYTECOUNT in the UDP_CSRx. It also
resets the data toggle to DATA0. It is useful after removing a HALT condition on a BULK endpoint. Refer to Chapter 5.8.5
in the USB Serial Bus Specification, Rev.2.0.
Warning: This flag must be cleared at the end of the reset. It does not clear UDP_CSRx flags.
0: No reset
1: Forces the corresponding endpoint FIF0 pointers to 0, therefore RXBYTECNT field is read at 0 in UDP_CSRx
Resetting the endpoint is a two-step operation:
1. Set the corresponding EPx field.
2. Clear the corresponding EPx field.
31 30 29 28 27 26 25 24
––––––––
23 22 21 20 19 18 17 16
––––––––
15 14 13 12 11 10 9 8
––––––––
76543210
EP7 EP6 EP5 EP4 EP3 EP2 EP1 EP0
1059
SAM4S Series [DATASHEET]
Atmel-11100K-ATARM-SAM4S-Datasheet_09-Jun-15
40.7.10 UDP Endpoint Control and Status Register (CONTROL_BULK)
Name: UDP_CSRx [x = 0..7] (CONTROL_BU LK)
Address: 0x40034030
Access: Read/Write
WARNING: Due to synchronization between MCK and UDPCK, the software application must wait fo r th e end of the write
operation before executing another write by polling the bits which must be set/cleared.
As an example, to perform a control operation on the endpoint without modifying the status flags while accessing the con-
trol bits and fields of this register, the status flag bits must first be defined with the “No effect” value ‘1’. Once the overall
UDP_CSR value is defined, the register can be written and then the synchronization wait procedure must be executed.
• TXCOMP: Generates an IN Packet with Data Previously Written in the DPR
This flag generates an interrupt while it is set to one.
Write (cleared by the firmware):
0: Clear the flag, clear the interrupt
1: No effect
Read (Set by the USB peripheral):
0: Data IN transaction has not been acknowledged by the Host
1: Data IN transaction is achieved, acknowledged by the Host
After having issued a Data IN transaction setting TXPKTRDY, the device firmware waits for TXCOMP to be sure that the
host has acknowledged the transaction.
• RX_DATA_BK0: Receive Data Bank 0
This flag generates an interrupt while it is set to one.
Write (cleared by the firmware):
0: Notify USB peripheral device that data have be en read in the FIFO’s Bank 0.
1: To leave the read value unchanged.
Read (Set by the USB peripheral):
0: No data packet has been received in the FIFO’s Bank 0.
1: A data packet has been received, it has been stored in the FIFO’s Bank 0.
When the device firmware has polled this bit or has been interrupted by this signal, it must transfer data from the FIFO to
the microcontroller memory. The number of bytes received is available in RXBYTCENT field. Bank 0 FIFO values are read
31 30 29 28 27 26 25 24
––––– RXBYTECNT
23 22 21 20 19 18 17 16
RXBYTECNT
15 14 13 12 11 10 9 8
EPEDS – – – DTGLE EPTYPE
76543210
DIR RX_DATA_BK1 FORCESTALL TXPKTRDY STALLSENT RXSETUP RX_DATA_
BK0 TXCOMP
SAM4S Series [DATASHEET]
Atmel-11100K-ATARM-SAM4S-Datasheet_09-Jun-15
1060
through the UDP_FDRx. Once a transfer is done, the device firmware must release Bank 0 to the USB peripheral device
by clearing RX_DATA_BK0.
After setting or clearing this bit, a wait time of 3 UDPCK clock cycles and 3 peripheral clock cycles is required before
accessing DPR.
• RXSETUP: Received Setup
This flag generates an interrupt while it is set to one.
Read:
0: No setup packet available.
1: A setup data packet has been sent by the host and is available in the FIFO.
Write:
0: Device firmware notifies the USB peripheral device that it has read the setup data in the FIFO.
1: No effect.
This flag is used to notify the USB device firmware that a valid Setup data packet has been sent by the host and success-
fully received by the USB de vice . Th e USB de vice firm wa re may tra nsf er Setu p da ta from th e FI FO by re ad ing the
UDP_FDRx to the microcontroller memory. Once a transfer has been done, RXSETUP must be cleared by the device
firmware.
Ensuing Data OUT transaction is not accepted while RXSETUP is set.
• STALLSENT: Stall Sent
This flag generates an interrupt while it is set to one.
This ends a STALL handshake.
Read:
0: Host has not acknowledged a stall
1: Host has acknowledged the stall
Write:
0: Resets the STALLSENT flag, clears the interrupt
1: No effect
This is mandatory for the device firmware to clear this flag. Otherwise the interrupt remains.
Refer to chapters 8.4.5 and 9.4.5 of the Universal Serial Bus Specification, Rev. 2.0 for more information on the STALL
handshake.
• TXPKTRDY: Transmit Packet Ready
This flag is cleared by the USB device.
This flag is set by the USB device firmware.
Read:
0: There is no data to send.
1: The data is waiting to be sent upon reception of token IN.
Write:
0: Can be used in the procedur e to can cel tran sm ission data. ( See Section 40.6.2.5 “Transmit Data Cancellation” on page
1041)
1: A new data payload has been written in the FIFO by the firmware and is ready to be sent.
1061
SAM4S Series [DATASHEET]
Atmel-11100K-ATARM-SAM4S-Datasheet_09-Jun-15
This flag is used to generate a Data IN transaction (device to host). Device firmware checks that it can write a data payload
in the FIFO, checking that TXPKTRDY is cleared. Transfer to the FIFO is done by writing in the UDP_FDRx. Once the data
payload has been transfe rred to the FIFO, the firmware n otifies the USB device setting TXPKTRDY to one. USB bus trans-
actions can start. TXCOMP is set once the data payload has been received by the host.
After setting or clearing this bit, a wait time of 3 UDPCK clock cycles and 3 peripheral clock cycles is required before
accessing DPR.
• FORCESTALL: Force Stall (used by Control, Bulk and Isochronous Endpoints)
Read:
0: Normal state
1: Stall state
Write:
0: Return to normal state
1: Send STALL to the host
Refer to chapters 8.4.5 and 9.4.5 of the Universal Serial Bus Specification, Rev. 2.0 for more information on the STALL
handshake.
Control endpoints: During the data stage and status stage, this bit indicates that the microcontroller cannot complete the
request.
Bulk and interrupt endpoints: This bit notifies the host that the endpoint is halted.
The host acknowledges the STALL, device firmware is notified by the STALLSENT flag.
• RX_DATA_BK1: Receive Data Bank 1 (only used by endpoints with ping-pong attributes)
This flag generates an interrupt while it is set to one.
Write (cleared by the firmware):
0: Notifies USB device that data have been read in the FIFO’s Bank 1.
1: To leave the read value unchanged.
Read (Set by the USB peripheral):
0: No data packet has been received in the FIFO’s Bank 1.
1: A data packet has been received, it has been stored in FI FO ’s Ban k 1.
When the device firmware has polled this bit or has been interrupted by this signal, it must transfer data from the FIFO to
microcontroller memory. The number of bytes received is available in RXBYTECNT field. Bank 1 FIFO values are read
through UDP_FDRx. Once a transfer is done, the device firmware must release Bank 1 to the USB device by clearing
RX_DATA_BK1.
After setting or clearing this bit, a wait time of 3 UDPCK clock cycles and 3 peripheral clock cycles is required before
accessing DPR.
• DIR: Transfer Direction (only available for control endpoints) (Read/Write)
0: Allows Data OUT transactions in the control data stage.
1: Enables Data IN transactions in the control data stage.
Refer to Chapter 8.5.3 of the Universal Serial Bus Specification, Rev. 2.0 for more information on the control data stage.
This bit must be set before UDP_CSRx/RXSETUP is cleared at the end of the setup stage. According to the request sent
in the setup data packet, the d ata stage is either a device to host (DIR = 1) or host to device (DIR = 0) data transfer. It is not
necessary to check this bit to reverse direction for the status stage.
SAM4S Series [DATASHEET]
Atmel-11100K-ATARM-SAM4S-Datasheet_09-Jun-15
1062
• EPTYPE[2:0]: Endpoint Type (Read/Write)
• DTGLE: Data Toggle (Read-only)
0: Identifies DATA0 packet
1: Identifies DATA1 packet
Refer to Chapter 8 of the Universal Serial Bus Specification, Rev. 2.0 for more information on DATA0, DATA1 packet
definitions.
• EPEDS: Endpoint Enable Disable
Read:
0: Endpoint disabled
1: Endpoint enabled
Write:
0: Disables endpoint
1: Enables endpoint
Control endpoints are always enabled. Reading or writing this field has no effect on control endpoints.
Note: After reset, all endpoints are config ured as control endpoints (zero).
• RXBYTECNT[10:0]: Number of Bytes Available in the FIFO (Read-only)
When the host sends a data packet to the device, the USB device stores the data in the FIFO and notifies the microcon-
troller. The microcontroller can load the data from the FIFO by reading RXBYTECENT bytes in the UDP_FDRx.
Value Name Description
0 CTRL Control
1 ISO_OUT Isochronous OUT
5 ISO_IN Isochronous IN
2 BULK_OUT Bulk OUT
6 BULK_IN Bulk IN
3 INT_OUT Interrupt OUT
7 INT_IN Interrupt IN
1063
SAM4S Series [DATASHEET]
Atmel-11100K-ATARM-SAM4S-Datasheet_09-Jun-15
40.7.11 UDP Endpoint Control and Status Register (ISOCHRONOUS)
Name: UDP_CSRx [x = 0..7] (ISOCHRONOUS)
Address: 0x40034030
Access: Read/Write
• TXCOMP: Generates an IN Packet with Data Previously Written in the DPR
This flag generates an interrupt while it is set to one.
Write (cleared by the firmware):
0: Clear the flag, clear the interrupt.
1: No effect.
Read (Set by the USB peripheral):
0: Data IN transaction has not been acknowledged by the Host.
1: Data IN transaction is achieved, acknowledged by the Host.
After having issued a Data IN transaction setting TXPKTRDY, the device firmware waits for TXCOMP to be sure that the
host has acknowledged the transaction.
• RX_DATA_BK0: Receive Data Bank 0
This flag generates an interrupt while it is set to one.
Write (cleared by the firmware):
0: Notify USB peripheral device that data have be en read in the FIFO’s Bank 0.
1: To leave the read value unchanged.
Read (Set by the USB peripheral):
0: No data packet has been received in the FIFO’s Bank 0.
1: A data packet has been received, it has been stored in the FIFO’s Bank 0.
When the device firmware has polled this bit or has been interrupted by this signal, it must transfer data from the FIFO to
the microcontroller memory. The number of bytes received is available in RXBYTCENT field. Bank 0 FIFO values are read
through the UDP_FDRx. Once a transfer is done, the device firmware must release Bank 0 to the USB peripheral device
by clearing RX_DATA_BK0.
After setting or clearing this bit, a wait time of 3 UDPCK clock cycles and 3 peripheral clock cycles is required before
accessing DPR.
31 30 29 28 27 26 25 24
––––– RXBYTECNT
23 22 21 20 19 18 17 16
RXBYTECNT
15 14 13 12 11 10 9 8
EPEDS – – – DTGLE EPTYPE
76543210
DIR RX_DATA_BK1 FORCESTALL TXPKTRDY ISOERROR RXSETUP RX_DATA_
BK0 TXCOMP
SAM4S Series [DATASHEET]
Atmel-11100K-ATARM-SAM4S-Datasheet_09-Jun-15
1064
• RXSETUP: Received Setup
This flag generates an interrupt while it is set to one.
Read:
0: No setup packet available.
1: A setup data packet has been sent by the host and is available in the FIFO.
Write:
0: Device firmware notifies the USB peripheral device that it has read the setup data in the FIFO.
1: No effect.
This flag is used to notify the USB device firmware that a valid Setup data packet has been sent by the host and success-
fully received by the USB de vice . Th e USB de vice firm wa re may tra nsf er Setu p da ta from th e FI FO by re ad ing the
UDP_FDRx to the microcontroller memory. Once a transfer has been done, RXSETUP must be cleared by the device
firmware.
Ensuing Data OUT transaction is not accepted while RXSETUP is set.
• ISOERROR: A CRC error has been detected in an isochronous transfer
This flag generates an interrupt while it is set to one.
Read:
0: No error in the previous isochronous transfer.
1: CRC error has been detected, data available in the FIFO are corrupted.
Write:
0: Resets the ISOERROR flag, clears the interrupt.
1: No effect.
• TXPKTRDY: Transmit Packet Ready
This flag is cleared by the USB device.
This flag is set by the USB device firmware.
Read:
0: There is no data to send.
1: The data is waiting to be sent upon reception of token IN.
Write:
0: Can be used in the procedur e to can cel tran sm ission data. ( See Section 40.6.2.5 “Transmit Data Cancellation” on page
1041)
1: A new data payload has been written in the FIFO by the firmware and is ready to be sent.
This flag is used to generate a Data IN transaction (device to host). Device firmware checks that it can write a data payload
in the FIFO, checking that TXPKTRDY is cleared. Transfer to the FIFO is done by writing in the UDP_FDRx. Once the data
payload has been transfe rred to the FIFO, the firmware n otifies the USB device setting TXPKTRDY to one. USB bus trans-
actions can start. TXCOMP is set once the data payload has been received by the host.
After setting or clearing this bit, a wait time of 3 UDPCK clock cycles and 3 peripheral clock cycles is required before
accessing DPR.
1065
SAM4S Series [DATASHEET]
Atmel-11100K-ATARM-SAM4S-Datasheet_09-Jun-15
• FORCESTALL: Force Stall (used by Control, Bulk and Isochronous Endpoints)
Read:
0: Normal state.
1: Stall state.
Write:
0: Return to normal state.
1: Send STALL to the host.
Refer to chapters 8.4.5 and 9.4.5 of the Universal Serial Bus Specification, Rev. 2.0 for more information on the STALL
handshake.
Control endpoints: During the data stage and status stage, this bit indicates that the microcontroller cannot complete the
request.
Bulk and interrupt endpoints: This bit notifies the host that the endpoint is halted.
The host acknowledges the STALL, device firmware is notified by the STALLSENT flag.
• RX_DATA_BK1: Receive Data Bank 1 (only used by endpoints with ping-pong attributes)
This flag generates an interrupt while it is set to one.
Write (cleared by the firmware):
0: Notifies USB device that data have been read in the FIFO’s Bank 1.
1: To leave the read value unchanged.
Read (set by the USB peripheral):
0: No data packet has been received in the FIFO’s Bank 1.
1: A data packet has been received, it has been stored in FI FO ’s Ban k 1.
When the device firmware has polled this bit or has been interrupted by this signal, it must transfer data from the FIFO to
microcontroller memory. The number of bytes received is available in RXBYTECNT field. Bank 1 FIFO values are read
through UDP_FDRx. Once a transfer is done, the device firmware must release Bank 1 to the USB device by clearing
RX_DATA_BK1.
After setting or clearing this bit, a wait time of 3 UDPCK clock cycles and 3 peripheral clock cycles is required before
accessing DPR.
• DIR: Transfer Direction (only available for control endpoints) (Read/Write)
0: Allows Data OUT transactions in the control data stage.
1: Enables Data IN transactions in the control data stage.
Refer to Chapter 8.5.3 of the Universal Serial Bus Specification, Rev. 2.0 for more information on the control data stage.
This bit must be set before UDP_CSRx/RXSETUP is cleared at the end of the setup stage. According to the request sent
in the setup data packet, the d ata stage is either a device to host (DIR = 1) or host to device (DIR = 0) data transfer. It is not
necessary to check this bit to reverse direction for the status stage.
• EPTYPE[2:0]: Endpoint Type (Read/Write)
Value Name Description
0 CTRL Control
1 ISO_OUT Isochronous OUT
5 ISO_IN Isochronous IN
2 BULK_OUT Bulk OUT
SAM4S Series [DATASHEET]
Atmel-11100K-ATARM-SAM4S-Datasheet_09-Jun-15
1066
• DTGLE: Data Toggle (Read-only)
0: Identifies DATA0 packet
1: Identifies DATA1 packet
Refer to Chapter 8 of the Universal Serial Bus Specification, Rev. 2.0 for more information on DATA0, DATA1 packet
definitions.
• EPEDS: Endpoint Enable Disable
Read:
0: Endpoint disabled
1: Endpoint enabled
Write:
0: Disables endpoint
1: Enables endpoint
Control endpoints are always enabled. Reading or writing this field has no effect on control endpoints.
Note: After reset, all endpoints are config ured as control endpoints (zero).
• RXBYTECNT[10:0]: Number of Bytes Available in the FIFO (Read-only)
When the host sends a data packet to the device, the USB device stores the data in the FIFO and notifies the microcon-
troller. The microcontroller can load the data from the FIFO by reading RXBYTECENT bytes in the UDP_FDRx.
6 BULK_IN Bulk IN
3 INT_OUT Interrupt OUT
7 INT_IN Interrupt IN
Value Name Description
1067
SAM4S Series [DATASHEET]
Atmel-11100K-ATARM-SAM4S-Datasheet_09-Jun-15
40.7.12 UDP FIFO Data Register
Name: UDP_FDRx [x = 0..7]
Address: 0x40034050
Access: Read/Write
• FIFO_DATA[7:0]: FIFO Data Value
The microcontroller can push or pop values in the FIFO through this register.
RXBYTECNT in the corresponding UDP_CSRx is the number of bytes to be read from the FIFO (sent by the host).
The maximum number of bytes to write is fixed by the Max Packet Size in the Standar d Endpoint Descriptor. It can not be
more than the physical memory size associated to the endpoint. Refer to the Universal Serial Bus Specification, Rev. 2.0
for more information.
31 30 29 28 27 26 25 24
––––––––
23 22 21 20 19 18 17 16
––––––––
15 14 13 12 11 10 9 8
––––––––
76543210
FIFO_DATA
SAM4S Series [DATASHEET]
Atmel-11100K-ATARM-SAM4S-Datasheet_09-Jun-15
1068
40.7.13 UDP Transceiver Control Register
Name: UDP_TXVC
Address: 0x40034074
Access: Read/Write
WARNING: The UDP peripheral clock in the Power Ma nagement Contr oller (PMC) must b e enabled be fore any rea d/write
operations to the UDP registers including the UDP_TXVC register.
• TXVDIS: Tran sceiver Disable
When UDP is disabled, power consumption can be reduced significantly by disabling the embedded transceiver. This can
be done by setting TXVDIS bit.
To enable the transceiver, TXVDIS must be cleared.
• PUON: Pull-up On
0: The 1.5KΩ integrated pull-up on DDP is disconnected.
1: The 1.5 KΩ integrated pull-up on DDP is connected.
NOTE: If the USB pull-up is not connected on DDP, the user should not write in any UDP register other than the
UDP_TXVC register. This is because if DDP and DDM are floating at 0, or pulled down, th en SE0 is received by the d evice
with the consequence of a USB Reset.
31 30 29 28 27 26 25 24
––––––––
23 22 21 20 19 18 17 16
––––––––
15 14 13 12 11 10 9 8
––––––
PUON TXVDIS
76543210
––––––––
1069
SAM4S Series [DATASHEET]
Atmel-11100K-ATARM-SAM4S-Datasheet_09-Jun-15
41. Analog Comparator Controller (ACC)
41.1 Description
The Analog Comparator Controller (ACC) configur es the analog com parator an d gene rates an inter rupt depe nding
on user settings. The analog comparator embeds two 8-to-1 multiplexers that generate two internal inputs. These
inputs are compared, resulting in a compare output. The hysteresis level, edge detection and polarity are
configurable.
The ACC also generates a compare event which can be used by the Pulse Width Modulator (PWM).
41.2 Embedded Characteristics
Eight User Analog Inputs Selectable for Comparison
Four Voltage Referenc es Se lectable for Com parison: Temp er at ur e Sen so r (TS) , ADVREF, DAC0 and DAC1
Interrupt Generation
Compare Event Fault Generation for PWM
41.3 Block Diagram
Figure 41-1. Analog Comparator Controller Block Diagram
Note: 1. Refer to Table 41-1 for the list of external analog data inputs.
Mux
External
Analog
Data
Inputs
Mux
TS
DAC0
DAC1
+
-
inp
inn
Analog Comparator
on
bias
Regulator
AND
Peripheral
Clock
Synchro
and
Edge
Detect
Write Detect
and Mask Timer
INVSELMINUSSELPLUS ACEN EDGETYP SCOWrite
ACC_CR
ACC_MR/ACR
SELFS
SCO
PWM PMC
HYSTISEL
Interrupt Controller
FE
User Interface
AND
AND
CE
on
on
on
1)
External 1)
Analog
Data
Inputs
Peripheral Clock
AND
ACC_IMR.
CE
Digital
Controller
SAM4S Series [DATASHEET]
Atmel-11100K-ATARM-SAM4S-Datasheet_09-Jun-15
1070
41.4 Pin Name List
41.5 Product Dependencies
41.5.1 I/O Lines
41.5.2 Power Management
The ACC is clocked through the Power Management Controller (PMC), thus the programmer must first configure
the PMC to enable the ACC clock.
Note that the voltage regulator must be activated to use the analog comparator.
41.5.3 Interrupt
The ACC has an interrupt line connected to the Interrup t Controller ( IC ). I n or de r to h andle interrupts, the Interrupt
Controller must be programmed before configuring the ACC.
41.5.4 Fault Output
The ACC has the FAULT output connected to the FAULT input of PWM. Please refer to chapter Section 41.6.4
”Fault Mode” and the implementation of the PWM in the product.
Table 41-1. List of External Analog Data Inputs
Pin Name Description
AD0..AD7 ACC Analog PLUS inputs
AD0..AD3 ACC Analog MINUS inputs
ADVREF ADCVoltage reference
Table 41-2. ACC Pin List
Pin Name Description Type
AD0..AD7 External analog data inputs Input
TS On-chip temperature sensor Input
ADVREF ADC voltage reference Input
DAC0, DAC1 On-chip DAC inputs Input
The analog input pins (AD0–AD7 and DAC0–1) are multiplexed with digital functions (PIO) on
the IO line. By writing the SELMINUS and SELPLUS fields in the ACC Mode Register
(ACC_MR), the associated IO lines are set to Analog mode.
Table 41-3. Peripheral IDs
Instance ID
ACC 33
1071
SAM4S Series [DATASHEET]
Atmel-11100K-ATARM-SAM4S-Datasheet_09-Jun-15
41.6 Functional Description
41.6.1 Description
The Analog Comparator Controller (ACC) controls the analog comparator settings and performs post-processing
of the analog comparator output.
When the analog comparator settings are modified, the output of the analog cell may be invalid. The ACC masks
the output for the invalid period.
A comparison flag is triggered by an event on the output of the analog comparator and an interrupt is generated.
The event on the analog comparator output can be selected among falling edge, rising edge or any edge.
The ACC register s ar e lis te d in Table 41-4.
41.6.2 Analog Settings
The user can selec t the inpu t hys te re sis an d co nf igu re two dif fe re nt optio n s, cha r act er ize d as follows:
High-speed: shortest propagation delay/highest current consumption
Low-power: longest propagation delay/lowest current consumption
41.6.3 Output Masking Period
As soon as the analog comparator settings change, the output is invalid for a duration depending on ISEL current.
A masking period is automatically triggered as soon as a write access is performed on the ACC_MR or ACC
Analog Control Register (ACC_ACR) (whatever the register data content).
When ISEL = 0, the mask period is 8 × tperipheral clock.
When ISEL = 1, the mask period is 128 × tperipheral clock.
The masking p eriod is reported by re ading a negative value (bit 31 set) on the ACC Inte rrupt Status Register
(ACC_ISR).
41.6.4 Fault Mode
In Fault mode, a comparison match event is communicated by the ACC fault output which is directly and internally
connected to a PWM fault input.
The source of the fault output can be configured as either a combinational value derived from the analog
comparator output or as th e peripheral clock resynchronized value (Refer to Figure 41-1 “Analog Comparator
Controller Block Diagram”).
41.6.5 Register Write Protection
To prevent any single softwar e error from cor rupting ACC be havior, cer tain registe rs in the address sp ace can be
write-protected by setting the WPEN bit in the ACC Write Protection Mode Register (ACC_WPMR).
If a write access to a write-protected register is detected, the WPVS flag in the ACC Write Protection Status
Register (ACC_WPSR) is set and the field WPVSRC indicates the register in which the write access has been
attempted.
The WPVS bit is automatically cleared after reading the ACC_WPSR.
The following registers can be write-protected:
ACC Mode Register
ACC Analog Control Register
SAM4S Series [DATASHEET]
Atmel-11100K-ATARM-SAM4S-Datasheet_09-Jun-15
1072
41.7 Analog Comparator Controller (ACC) User Interface
Table 41-4 . Register Mapping
Offset Register Name Access Reset
0x00 Control Register ACC_CR Write-only –
0x04 Mode Register ACC_MR Read/Write 0
0x08–0x20 Reserved – – –
0x24 Interrupt Enable Register ACC_IER Write-only –
0x28 Interrupt Disable Register ACC_IDR Write-only –
0x2C Interrupt Mask Register ACC_IMR Read-only 0
0x30 Interrupt Status Register ACC_ISR Read-only 0
0x34–0x90 Reserved – – –
0x94 Analog Control Register ACC_ACR Read/Write 0
0x98–0xE0 Reserved – – –
0xE4 Write Protection Mode Register ACC_WPMR Read/Write 0
0xE8 Write Protection Status Register ACC_WPSR Read-only 0
0xEC–0xFC Reserved – – –
1073
SAM4S Series [DATASHEET]
Atmel-11100K-ATARM-SAM4S-Datasheet_09-Jun-15
41.7.1 ACC Control Register
Name: ACC_CR
Address: 0x40040000
Access: Write-only
• SWRST: Software Reset
0: No effect.
1: Resets the module.
31 30 29 28 27 26 25 24
––––––––
23 22 21 20 19 18 17 16
––––––––
15 14 13 12 11 10 9 8
––––––––
76543210
–––––––SWRST
SAM4S Series [DATASHEET]
Atmel-11100K-ATARM-SAM4S-Datasheet_09-Jun-15
1074
41.7.2 ACC Mode Register
Name: ACC_MR
Address: 0x40040004
Access: Read/Write
This register can only be written if the WPEN bit is cleared in the ACC Write Protection Mode Register.
• SELMINUS: Selection for Minus Comparator Input
0..7: Selects the input to apply on analo g comparator SELMINUS comparison input.
• SELPLUS: Selection For Plus Comparator Input
0..7: Selects the input to apply on analo g comparator SELPLUS compariso n input.
• ACEN: Analog Comparator Enable
0 (DIS): Analog comparator disabled.
1 (EN): Analog comparator enabled.
31 30 29 28 27 26 25 24
––––––––
23 22 21 20 19 18 17 16
––––––––
15 14 13 12 11 10 9 8
–FESELFSINV– EDGETYP ACEN
76543210
– SELPLUS – SELMINUS
Value Name Description
0TS Select TS
1 ADVREF Select ADVREF
2 DAC0 Select DAC0
3 DAC1 Select DAC1
4 AD0 Select AD0
5 AD1 Select AD1
6 AD2 Select AD2
7 AD3 Select AD3
Value Name Description
0 AD0 Select AD0
1 AD1 Select AD1
2 AD2 Select AD2
3 AD3 Select AD3
4 AD4 Select AD4
5 AD5 Select AD5
6 AD6 Select AD6
7 AD7 Select AD7
1075
SAM4S Series [DATASHEET]
Atmel-11100K-ATARM-SAM4S-Datasheet_09-Jun-15
• EDGETYP: Edge Type
• INV: Invert Comparator Output
0 (DIS): Analog comparator output is directly processed.
1 (EN): Analog comparator output is inverted prior to being processed.
• SELFS: Selection Of Fault Source
0 (CE): The CE flag is used to drive the FAULT output.
1 (OUTPUT): The output of the analog comparator flag is used to drive the FAULT output.
• FE: Fault Enable
0 (DIS): The FAULT output is tied to 0.
1 (EN): The FAULT output is driven by the signal defined by SELFS.
Value Name Description
0 RISING Only rising edge of comparator output
1 FALLING Falling edge of comparator output
2 ANY Any edge of comparator output
SAM4S Series [DATASHEET]
Atmel-11100K-ATARM-SAM4S-Datasheet_09-Jun-15
1076
41.7.3 ACC Interrupt Enable Register
Name: ACC_IER
Address: 0x40040024
Access: Write-only
• CE: Comparison Edge
0: No effect.
1: Enables the interrupt when the selected edge (defined by EDGETYP) occurs.
31 30 29 28 27 26 25 24
––––––––
23 22 21 20 19 18 17 16
––––––––
15 14 13 12 11 10 9 8
––––––––
76543210
–––––––CE
1077
SAM4S Series [DATASHEET]
Atmel-11100K-ATARM-SAM4S-Datasheet_09-Jun-15
41.7.4 ACC Interrupt Disable Register
Name: ACC_IDR
Address: 0x40040028
Access: Write-only
• CE: Comparison Edge
0: No effect.
1: Disables the interrupt when the selected edge (defined by EDGETYP) occurs.
31 30 29 28 27 26 25 24
––––––––
23 22 21 20 19 18 17 16
––––––––
15 14 13 12 11 10 9 8
––––––––
76543210
–––––––CE
SAM4S Series [DATASHEET]
Atmel-11100K-ATARM-SAM4S-Datasheet_09-Jun-15
1078
41.7.5 ACC Interrupt Mask Register
Name: ACC_IMR
Address: 0x4004002C
Access: Read-only
• CE: Comparison Edge
0: The interrupt is disabled.
1: The interrupt is enabled.
31 30 29 28 27 26 25 24
––––––––
23 22 21 20 19 18 17 16
––––––––
15 14 13 12 11 10 9 8
––––––––
76543210
–––––––CE
1079
SAM4S Series [DATASHEET]
Atmel-11100K-ATARM-SAM4S-Datasheet_09-Jun-15
41.7.6 ACC Interrupt Status Regist er
Name: ACC_ISR
Address: 0x40040030
Access: Read-only
• CE: Comparison Edge (cleared on read)
0: No edge occurred (defined by EDGETYP) on analog comparator output since the last read of ACC_ISR.
1: A selected edge (defined by EDGETYP) on analog comparator output occurred since the last read of ACC_ISR.
• SCO: Synchronized Comparator Output
Returns an image of the analog comparator output after being pre-processed (refer to Figure 41-1 on page 1069).
If INV = 0
SCO = 0 if inn > inp
SCO = 1 if inp > inn
If INV = 1
SCO = 1 if inn > inp
SCO = 0 if inp > inn
• MASK: Flag Mask
0: The CE flag and SCO value are valid.
1: The CE flag and SCO value are invalid.
31 30 29 28 27 26 25 24
MASK–––––––
23 22 21 20 19 18 17 16
––––––––
15 14 13 12 11 10 9 8
––––––––
76543210
––––––SCOCE
SAM4S Series [DATASHEET]
Atmel-11100K-ATARM-SAM4S-Datasheet_09-Jun-15
1080
41.7.7 ACC Analog Control Register
Name: ACC_ACR
Address: 0x40040094
Access: Read/Write
This register can only be written if the WPEN bit is cleared in ACC Write Protection Mode Register.
• ISEL: Current Selection
Refer to the section on ACC electrical characteristics in the datasheet.
0 (LOPW): Low-power option.
1 (HISP): High-speed option.
• HYST: Hysteresis Selection
0 to 3: Refer to the section on ACC electrical characteristics in the datasheet.
31 30 29 28 27 26 25 24
––––––––
23 22 21 20 19 18 17 16
––––––––
15 14 13 12 11 10 9 8
––––––––
76543210
––––– HYST ISEL
1081
SAM4S Series [DATASHEET]
Atmel-11100K-ATARM-SAM4S-Datasheet_09-Jun-15
41.7.8 ACC Write Protection Mode Register
Name: ACC_WPMR
Address: 0x400400E4
Access: Read/Write
• WPEN: Write Protec ti on Ena b le
0: Disables the write protection if WPKEY corresponds to 0x414343 (“ACC” in ASCII).
1: Enables the write protection if WPKEY corresponds to 0x414343 (“ACC” in ASCII).
See “Register Write Protection” on page 1071 for the list of registers that can be write-protected.
• WPKEY: Write Protection Key
31 30 29 28 27 26 25 24
WPKEY
23 22 21 20 19 18 17 16
WPKEY
15 14 13 12 11 10 9 8
WPKEY
76543210
–––––––WPEN
Value Name Description
0x414343 PASSWD Writing any other value in this field aborts the write operation of the WPEN bit.
Always reads as 0.
SAM4S Series [DATASHEET]
Atmel-11100K-ATARM-SAM4S-Datasheet_09-Jun-15
1082
41.7.9 ACC Write Protection Status Register
Name: ACC_WPSR
Address: 0x400400E8
Access: Read-only
• WPVS: Write Protection Violation Status
0: No write protec tion v iola tio n ha s oc curred since the last read of ACC_WPSR.
1: A write protection violation (WPEN = 1) has occurred since the last read of ACC_WPSR.
31 30 29 28 27 26 25 24
––––––––
23 22 21 20 19 18 17 16
––––––––
15 14 13 12 11 10 9 8
––––––––
76543210
–––––––WPVS
1083
SAM4S Series [DATASHEET]
Atmel-11100K-ATARM-SAM4S-Datasheet_09-Jun-15
42. Analog-to-Digital Converter (ADC)
42.1 Description
The ADC is based on a 12-bit Analog-to-Digital Converter (ADC) managed by an ADC Controller. Refer to Figure
42-1, “Analog-to-Digital Converte r Block Diagram ”. It also integrates a 16-to-1 analog multiplexer, making possible
the analog-to-digital conversions of 16 analog lines.The conversions extend from 0V to the voltage carried on pin
ADVREF.
Conversion results are reported in a common register for all channels, as well as in a channel-dedicated register.
The last channel is internally connected by a temperature sensor.
Software trigger, external trigge r on r ising edge of the ADTRG pin or intern al trigge rs from Timer Coun ter output( s)
are configurable.
The comparison circuitry allows automatic detection of values below a threshold, higher than a threshold, in a
given range or outside the range, thresholds and ranges being fully configurable.
The ADC Controller internal fault output is directly connected to PWM fault input. This input can be asserted by
means of comparison circuitry in order to immediately put the PWM output in a safe state (pure combinational
path).
The ADC also integrates a Sleep mode and a conversion sequencer and connects with a PDC channel. These
features reduce both power consumption and processor intervention.
This ADC has a selectable single-ended or fully differential input and benefits from a 2-bit programmable gain.
A digital error correction circuit based on the multi-bit redundant signed digit (R SD) algorithm is em p loyed in order
to reduce INL and DNL errors.
Finally, the user can configure ADC timings, such as startup time and tracking time.
SAM4S Series [DATASHEET]
Atmel-11100K-ATARM-SAM4S-Datasheet_09-Jun-15
1084
42.2 Embedded Characteristics
12-bit Resolution
1 MHz Conversion Rate
On-chip Temperature Sensor Management
Wide Range of Power Supply Operation
Selectable Single-Ended or Differential Input Voltage
Programmable Gain For Maximum Full-Scale Input Range 0–VDD
Integrated Multiplexer Offering Up to 16 Independent Analog Inputs
Individual Enable and Disable of Each Channel
Hardware or Software Trigger
External Trigger Pin
Timer Counter Outputs (Corresponding TIOA Trigger)
PWM Event Line
Drive of PWM Fault Input
PDC Support
Possibility of ADC Timings Configuration
Two Sleep Modes and Conversion Sequencer
Automatic Wakeup on Trigger and Back to Sleep Mode after Conversions of all Enabled Channels
Possibility of Customized Channel Sequence
Standby Mode for Fast Wakeup Time Response
Power Down Capability
Automatic Window Comparison of Converted Values
Register Write Protection
1085
SAM4S Series [DATASHEET]
Atmel-11100K-ATARM-SAM4S-Datasheet_09-Jun-15
42.3 Block Diagram
Figure 42-1. Analog-to-Digital Converter Block Diagram
Note: DMA may be referred to as PDC (Peripheral DMA Controller).
42.4 Signal Description
Note: 1. AD15 is not an actual pin but is internally connected to a temperature sensor.
ADCCLK
ADTRG
ADVREF
GND
Trigger
Selection
Timer
Counter
Channels
AD0
AD1
ADn
A
nalog
Inputs
ADC Interrupt
ADC 12-bit Controller
ADC cell
Control
Logic
User
Interface
Interrupt
Controller
Peripheral Bridge
APB
PDC
AHB
IN+
IN- S/H
OFFSET PGA
PIO
Cyclic Pipeline
12-bit Analog-to-Digital
Converter
CHx
Peripheral Clock
PMC
Bus Clock
Table 42-1. ADC Pin Description
Pin Name Description
ADVREF ref e rence voltage
AD0–AD15(1) Analog input channels
ADTRG External trigger
SAM4S Series [DATASHEET]
Atmel-11100K-ATARM-SAM4S-Datasheet_09-Jun-15
1086
42.5 Product Dependencies
42.5.1 Power Management
The ADC Controller is not continuously clocked. The programmer must first enable the ADC Cont roller peripheral
clock in the Power Management Co ntroller (PMC) before using the ADC Controller. However, if the application
does not require ADC operations, the ADC Controller clock can be stopped when not needed and restarted when
necessary. Configuring the ADC Controller does not require the ADC Controller clo ck to be enabled.
42.5.2 Interrupt Sources
The ADC interrupt line is connected on one of the internal sources of the Interrupt Controller. Using the ADC
interrupt requires the interrupt controller to be programmed first.
42.5.3 Analog Inputs
The analog input pins can be multiplexed with PIO lines. In this case, the assignment of the ADC input is
automatically done as soon as the corresponding channel is enabled by writing the Channel Enable register
(ADC_CHER). By default, after reset, the PIO line is configured as input with its pull-up enabled an d the ADC input
is connected to the GND.
42.5.4 Temperature Sensor
The temperature sensor is internally connected to channel index 15 of the ADC.
The temperature sensor provides an output voltage VT that is proportional to the absolute temperature (PTAT). To
activate the temperature sensor, the TSON bit in ADC_ACR must be set. After setting the bit, the startup time of
the temperature sensor must be achieved prior to initiating any measurem e nts.
42.5.5 I/O Lines
The pin ADTRG may be shared with other peripheral functions through t he PIO Controller . In this case, the PIO
Controller should be set accordingly to assign the pin ADTRG to the ADC function.
Table 42-2. Peripheral IDs
Instance ID
ADC 29
Table 42-3. I/O Lines
Instance Signal I/O Line Periphera l
ADC ADTRG PA8 B
ADC AD0 PA17 X1
ADC AD1 PA18 X1
ADC AD2/WKUP9 PA19 X1
ADC AD3/WKUP10 PA20 X1
ADC AD4/RTCOUT0 PB0 X1
ADC AD5/RTCOUT1 PB1 X1
ADC AD6/WKUP12 PB2 X1
ADC AD7 PB3 X1
ADC AD8 PA21 X1
ADC AD9 PA22 X1
1087
SAM4S Series [DATASHEET]
Atmel-11100K-ATARM-SAM4S-Datasheet_09-Jun-15
42.5.6 Timer Triggers
Timer Counters may or may not be used as hardware triggers depending on user requirements. Thus, some or all
of the timer counters may be unconnected.
42.5.7 PWM Event Line
PWM event lines may or may not be used as hardware triggers depending on user requirements.
42.5.8 Fault Output
The ADC Controller has the FAULT output connected to the FAULT input of PWM. Refer to Section 42.6.14 “Fault
Output” an d implementation of the PWM in the product datasheet.
42.5.9 Conversion Performances
For performance and electrical characteristics of the ADC, see the section ‘Electrical Characteristics’.
42.6 Functional Description
42.6.1 Analog-to-Digital Conversion
ADC conversions are sequenced by two operating times: the tracking time and the con version time.
The tracking time represents the time between the channel selection change and the time for the controller
to start the ADC. The tracking time is set using the TRACKTIM field of the Mode Register (ADC_M R).
The conversion time represents the time for the ADC to convert the analog signal.
In order to guarantee a conversion with minimum error, after any start of conversion, the ADC controller waits a
number of ADC clock cycles (called hold time) before changing the channel selection again (and so starts a new
tracking operation).
ADC AD10 PC13 X1
ADC AD11 PC15 X1
ADC AD12 PC12 X1
ADC AD13 PC29 X1
ADC AD14 PC30 X1
Table 42-3. I/O Lines (Continued )
SAM4S Series [DATASHEET]
Atmel-11100K-ATARM-SAM4S-Datasheet_09-Jun-15
1088
Figure 42-2. Sequence of ADC Conversions When Tracking Time > Conve rsion Time
Figure 42-3. Sequence of ADC Conversions When Tracking Time < Conversion Time
ADCCLK
LCDR
ADC_ON
Trigger event (Hard or Soft)
ADC_SEL
DRDY
ADC_Start
CH0 CH1
CH0
CH2
CH1
Hold Time Hold TimeStart Up
Time
(and tracking of CH0)
Conversion
of CH0
Conversion
of CH1
Tracking of CH1 Tracking of CH2
Commands
from controller
to analog cell
ADCCLK
LCDR
ADC_ON
Trigger event (Hard or Soft)
ADC_SEL
DRDY
ADC_Start
CH0 CH1
CH0
CH2
CH1
CH3
CH2
Hold Time Hold Time Hold TimeStart Up
Time
&
Tracking
of CH0
Conversion
of CH0
&
Tracking
of CH1
Conversion
of CH1
&
Tracking
of CH2
Conversion
of CH2
&
Tracking
of CH3
Read the
ADC_LCDR
Commands
from controller
to analog cell
1089
SAM4S Series [DATASHEET]
Atmel-11100K-ATARM-SAM4S-Datasheet_09-Jun-15
42.6.2 ADC Clock
The ADC uses the ADC clock (ADCCLK) to perform conversions. The ADC clock frequency is selected in the
PRESCAL field of ADC_MR.
The ADC clock frequen cy is betwee n fperipheral clock/2, if PRESCAL is 0, and fperipheral clock/512, if PRESCAL is set to
255 (0xFF).
PRESCAL must be programmed to provide the ADC clock frequency parameter given in the section ‘Electrical
Characteristics’.
42.6.3 ADC Reference Voltage
The conversion is performed on a full range between 0V and the reference voltage pin ADVREF. Analog inputs
between these voltages convert to values based on a linear conversion.
42.6.4 Conversion Resolution
The ADC analog cell features12-bit resolution.
42.6.5 Conversion Results
When a conversion is comple ted, the resultin g digita l value is stored in the Channel Data register (ADC_CDRx) of
the current channel and in the ADC Last Converted Data register (ADC_LCDR). By setting the TAG option in the
Extended Mode Register (ADC_EMR), the ADC_LCDR presents the channel number associated with the last
converted data in the CHNB field.
The channel EOC bit and the DRDY bit in the Interrupt Status register (ADC_ISR) are set. In the case of a
connected PDC channel, DRDY rising triggers a data request. In any case, either EOC and DRDY can trigger an
interrupt.
Reading one of the ADC_CDRx clears the corresponding EOC bit. Reading ADC_LCDR clears the DRDY bit.
Figure 42-4. EOCx and DRDY Flag Behavior
If ADC_CDR is not read before further incoming data is converted, the corresponding OVREx flag is set in the
Overrun Status register (ADC_OVER).
New data converted when DRDY is high sets the GOVRE bit in ADC_ISR.
Read the ADC_CDRx
EOCx
DRDY
Read the ADC_LCDR
CHx
(ADC_CHSR)
(ADC_ISR)
(ADC_ISR)
Write the ADC_CR
with START = 1
Write the ADC_CR
with START = 1
SAM4S Series [DATASHEET]
Atmel-11100K-ATARM-SAM4S-Datasheet_09-Jun-15
1090
The OVREx flag is automatically cleared when ADC_OVER is read, and the GOVRE flag is automatically cleared
when ADC_ISR is read.
Figure 42-5. EOCx, OVREx and GOVREx Flag Beha v ior
Warning: If the corresponding channel is disabled during a conversion or if it is disabled and then reenabled during a con-
version, its associated data and co rrespo nding EOCx and GOVRE flags i n ADC_ISR and OVREx fla gs in ADC_OVER are
unpredictable.
EOC0
GOVRE
CH0
(ADC_CHSR)
(ADC_ISR)
(ADC_ISR)
Trigger event
EOC1
CH1
(ADC_CHSR)
(ADC_ISR)
OVRE0
(ADC_OVER)
Undefined Data Data A Data B
ADC_LCDR
Undefined Data Data A
ADC_CDR0
Undefined Data Data B
ADC_CDR1
Data C
Data C
Conversion C
Conversion A
DRDY
(ADC_ISR)
Read ADC_CDR1
Read ADC_CDR0
Conversion B
Read ADC_OVER
Read ADC_ISR
OVRE1
(ADC_OVER)
1091
SAM4S Series [DATASHEET]
Atmel-11100K-ATARM-SAM4S-Datasheet_09-Jun-15
42.6.6 Conversion Triggers
Conversions of the active analog channels are started with a software or hardware trigger. The software trigger is
provided by writing the Control register (ADC_CR) with the START bit at 1.
The hardware trigger can be one of the TIOA output s of the Timer Counte r channels, PWM Event line, or the
external trigger input of the ADC (ADTRG). The hardware trigger is selected with the TRGSEL field in the
ADC_MR. The selected hardware trigger is enabled with the TRGEN bit in the ADC_MR.
The minimum time between two consecutive trigger events must be strictly greater than the duration of the longest
conversion sequence depending on the configuration of the ADC_MR, ADC_CHSR and ADC_SEQRx.
If a hardware trigger is selected, the start of a conversion is triggered after a delay starting at each rising edge of
the selected signal. Due to asynchronous handling, the delay may vary in a range of two peripheral clock periods
to one ADC clock period.
Figure 42-6. Hardware Trigger Delay
If one of the TIOA outputs is selected, the corresponding Timer Counter channel must be programmed in
Waveform mode.
Only one start command is ne cessary to initiate a conversion sequ ence on all the channels. The ADC hard ware
logic automatically pe rforms the conver sions on the active chann els, then waits for a new reque st. The Channel
Enable (ADC_CHER) and Channel Disable (ADC_CHDR) registers permit the analog channels to be enabled or
disabled independently.
If the ADC is used with a PDC, only th e tran sfer s of con verte d data fr om en able d chann els are perform ed a nd the
resulting data buffers should be interpreted accordingly.
42.6.7 Sleep Mode and Conversion Sequencer
The ADC Sleep mode maximizes power saving by automatically deactivating the ADC when it is not being used for
conversions. Sleep mode is selected by setting the SLEEP bit in ADC_MR.
Sleep mode is managed by a conversion sequencer, which automatically processes the conversions of all
channels at lowest power consumption.
This mode can be used when the minimum period of time between two successive trigger events is greater than
the startup period of the ADC. See the section ‘ADC Characteristics’ in the ‘Electrical Characteristics’.
When a start conversion request occurs, the ADC is automatically activated. As the analog cell requires a startup
time, the logic waits during this time and starts the conversion on the enabled channels. When all conversions are
complete, the ADC is deactivated until the next trigger. Triggers occurring during the se quence are ignored.
A Fast wake-up mode is available in ADC_MR as a compromise between power-saving strategy and
responsiveness. Setting the FWUP bit enables the Fast wake-up mode. In Fast wake-up mode the ADC cell is not
fully deactivated while no conversion is requested, thereby providing less power saving but faster wakeup.
The conversion sequencer allows automatic processing with minimum processor inte rvention and optim ized power
consumption. Conversion sequences can be performed periodically using a Timer/Counter output or the PWM
event line. The periodic acquisition of several samples can be processed automatically without any intervention of
the processor via the PDC.
trigger
start
delay
SAM4S Series [DATASHEET]
Atmel-11100K-ATARM-SAM4S-Datasheet_09-Jun-15
1092
The sequence can be customized by programming the Sequence Channel Registers ADC_SEQR1 and
ADC_SEQR2 and setting the USEQ bit of the Mode Register (ADC_MR). The user can choose a specific order of
channels and can program up to 16 conversions by sequence. The user is free to cr eate a pers onal se quence by
writing channel numbers in ADC_SEQR1 and ADC_SEQR2. Not only can channel numbers be written in any
sequence, channel numbers can b e repeated several times. When the bit USEQ in ADC_MR is set, the fields
USCHx in ADC_SEQR1 and ADC_SEQR2 are used to define the sequence. Only enabled USCHx fields will be
part of the sequence. Each USCHx field has a corresponding enable, CHx, in ADC_CHER (USCHx field with the
lowest x index is associated with bit CHx of the lowest index).
If all ADC channels (i.e., 16) are used on an application board, there is no restriction of usage of the user
sequence. However, if some ADC channels are not enabled for conversion but rather used as pure digital inputs,
the respective indexes of these channels cannot be used in the user sequence fields (see ADC_SEQRx). For
example, if channel 4 is disabled (ADC_CSR[4] = 0), ADC_SEQRx fields USCH1 up to USCH16 must no t cont ain
the value 4. Thus the length of the user sequence may be limited by this behavior.
As an example, if only four channels over 16 (CH0 up to CH3) are selected for ADC conversions, the user
sequence length cannot exceed four channels. Each trigger event may launch up to four successive conversions
of any combination of channels 0 up to 3 but no more (i.e., in this case the sequence CH0, CH0, CH1, CH1, CH1
is impossible).
A sequence that repeats the same channel several times requires more enabled channels than channels actually
used for conversion. For example, the sequence CH0, CH0, CH1, CH1 requires four enabled channels (four free
channels on application boards) whereas only CH0, CH1 are really converted.
Note: The referen ce voltage pins always remain connected in Normal mode as in Sleep mode.
42.6.8 Comparison Window
The ADC Controller features automatic comparison functions. It compares converted values to a low threshold, a
high threshold or both, depending on the value of the CMPMODE bit in ADC_EMR. The comparison can be done
on all channels or only on the channel specified in the CMPSEL field of ADC_EMR. To compare all channels, the
CMPALL bit of ADC_EMR must be set.
The flag can be read on the COMPE bit of the Interrupt Status register (ADC_ISR) and can trigger an interrupt.
The high threshold and the low threshold can be read/write in the Compare Window register (ADC_CWR).
42.6.9 Differential Inputs
The ADC can be used either as a single-ended ADC (DIFF bit = 0 in ADC_COR) or as a fully differential ADC
(DIFF bit = 1 in ADC_COR) as shown in Figure 42-7. By default, after a reset, the ADC is in Single-ended mode.
If ANACH is set in ADC_MR, the ADC can apply a different mode on each channel. Otherwise the parameters of
CH0 are applied to all channels.
The same inputs are used in Single-ended or Differential mode.
In Single-ended m ode, inputs are managed b y a 16:1 -channel analog multiplexer. In Fully Differential mode, inputs
are managed by an 8:1-channel analog multiplexer . See Table 42-4.
Table 42-4. Input Pins and Channel Numbers
Input Pin
Channel Number
Single-ended Mode Differential Mode
AD0 CH0 CH0
AD1 CH1
AD2 CH2 CH1
AD3 CH3
1093
SAM4S Series [DATASHEET]
Atmel-11100K-ATARM-SAM4S-Datasheet_09-Jun-15
42.6.10 Input Gain and Offset
The ADC has a built-in programmable gain amplifier (PGA) and programmable offset.
The programmable gain amplifier can be set to gains of 1/2, 1, 2 and 4 and can be used either for single-ended
applications or for fully differential applications.
If ANACH is set in ADC_MR, the ADC can apply different gain and offset on each channel. Otherwise the
parameters of CH0 are applied to all channels.
The gain is configurable through the GAIN bit of the Channel Gain register (ADC_CGR) as shown in Table 42-5.
To allow the full range , the analog offset of the ADC can be configured by the OFFx bit o f the Channel Offset
register (ADC_COR). The offset is only available in Single-ended mode .
AD4 CH4 CH2
AD5 CH5
AD6 CH6 CH3
AD7 CH7
AD8 CH8 CH4
AD9 CH9
AD10 CH10 CH5
AD11 CH11
AD12 CH12 CH6
AD13 CH13
AD14 CH14 CH7
AD15 CH15
Table 42-4. Input Pins and Channel Numbers (Continued)
Input Pin
Channel Number
Single-ended Mode Differential Mode
Table 42-5. Gain of the Sample and Hold Unit
GAIN[1:0] Gain (DIFFx = 0) Gain (DIFFx = 1)
01 0.5
11 1
22 2
34 2
Table 42-6. Offset of the Sample and Hold Unit
OFFx Bit Offset (DIFFx = 0) Offset (DIFFx = 1)
00 0
1(G-1)V
ADVREF/2
SAM4S Series [DATASHEET]
Atmel-11100K-ATARM-SAM4S-Datasheet_09-Jun-15
1094
Figure 42-7. Analog Full Scale Ranges in Single-Ended/Differential Applications Versus Gain and Offset
VIN+
gain=0.5
gain=1
gain=2
gain=4
Single ended
se0fd1=0
ully differential
se0fd1=1
same as
gain=1
same as
gain=2
0
0
0
offset=0offset=1
offset=0offset=1
0
(00)
(01)
(10)
(11)
VIN+
VIN+
VIN+
VIN+
VIN+
VIN+
VIN-
VIN+
VIN-
VIN+
VIN-
VIN+
VIN-
V
ADVREF
½)V
ADVREF
)
(¾) V
ADVREF
V
ADVREF
V
ADVREF
V
ADVREF
½)V
ADVREF
)
½)V
ADVREF
)
½)V
ADVREF
)
½)V
ADVREF
)
(¼) V
ADVREF
(¼) V
ADVREF
(¼) V
ADVREF
58
)(
V
ADVREF
(¾) V
ADVREF
38
)(
V
ADVREF
18
)(
V
ADVREF
58
)(
V
ADVREF
38
)(
V
ADVREF
F
1095
SAM4S Series [DATASHEET]
Atmel-11100K-ATARM-SAM4S-Datasheet_09-Jun-15
42.6.11 ADC Timings
Each ADC has its own minimal startup time that is programmed through the field STARTUP in ADC_MR.
A minimal tracking time is necessary for the ADC to guar antee th e best con verted final value betwee n two channel
selections. This time must be programmed in the TRACKTIM field in ADC_MR.
When the gain, offset or differential input parameters of the analog cell change between two channels, the analog
cell may need a specific settling time before starting the tracking phase. In that case, the controller automatically
waits during the settling time defined in ADC_MR. Obviously, if the ANACH option is not set, this time is unused.
Warning: No input buffer amplifier to isolate the source is included in the ADC. This must be taken into
consideration to program a precise value in the TRACKTIM field. See the section ‘ADC Characteristics’ in the
‘Electrical Characteristics’.
42.6.12 Automatic Calibration
The ADC features an Automatic calibration (AUTOCALIB) mode for gain errors (calibration).
The automatic calibration sequence can be started at any time by writing a ‘1’ to the AUTOCA L bit of ADC_CR.
The automatic calibration sequence requires a software reset command (SWRST in ADC_CR) prior to writing the
AUTOCAL bit. The end of calibration sequence is given by the EOCAL bit in ADC_ISR, and an interrupt is
generated if EOCAL interrupt has been enabled (ADC_IER).
The calibration sequence performs an automatic calibration on all enabled channels. The channels required for
conversion do not need to be all enabled during the calibration process if they are programmed with the same
gain. Only channels with different gain settings need to be enabled . The gain settings of all enabled channels must
be set before starting the AUTOCAL IB sequence. If the gain s ettings (ADC_CGR and ADC_COR) for a given
channel are changed, the AUTOCALIB sequence must then be started again.
The calibration data on one or more enabled channels is stored in the internal ADC memory.
Then, when a new conversion is started on one or more enabled channels, the converted value (in ADC_LCDR or
ADC_CDRx) is a calibrated value.
Autocalibration is for settings, not for channels. Therefore, if a specifi c combination of gain has already been
calibrated and a new channel with the same settings is enabled after the initial calibration, there is no need to
restart a calibration. If dif f erent enabled cha nnels have di f fer ent g ain setting s, the corr esponding cha nnels must b e
enabled before starting the calibration.
If a software reset is performed (bit SWRST = 1 in ADC_CR) or after power-up (or wake-up from Backup mode),
the calibration data in the ADC memory is lost.
Changing the ADC reference voltage (ADVREF pin) requires a new calibration sequence.
For calibration time and gain error after calibration, refer to the section on the 12-bit ADC in the Electrical
Characteristics.
42.6.13 Buffer Structure
The PDC read channel is triggered each time a new data is stored in ADC_LCDR. The same structure of data is
repeatedly stored in ADC_LCDR each time a trigger event occurs. Depending on user mode of operation
(ADC_MR, ADC_CHSR, ADC_SEQR1, ADC_SEQR2) the structure differs. Each data read to PDC buffer, carried
on a half-word (16-bit), co nsists of last converted data right aligned and wh en TAG is set in ADC_EMR, the four
most significant bits are carrying the channel number thus allowing an easier post-processing in the PDC buffer or
better checking the PDC buffer integrity.
SAM4S Series [DATASHEET]
Atmel-11100K-ATARM-SAM4S-Datasheet_09-Jun-15
1096
Figure 42-8. Buffer Structure
42.6.14 Fault Output
The ADC Controller internal fault output is directly connected to PWM fault input. Fault output may be asserted
depending on the configuration of ADC_EMR and ADC_CW R and converted values. When the compare occurs,
the ADC fault output generates a pulse of one peripheral clock cycle to the PWM fault input. This fault line can be
enabled or disabled within PWM. Should it be activated and asserted by the ADC Controller, the PWM outputs are
immediately placed in a safe state (pure combinational path). Note that the ADC fault output connected to the
PWM is not the COMPE bit. Thus the Fault mode (FMOD) within the PWM configuration must be FMOD = 1.
42.6.15 Register Write Protection
To prevent any single softwar e error from cor rupting ADC be havior, cer tain registe rs in the address sp ace can be
write-protected by setting the WPEN bit in the “ADC Write Protection Mode Register” (ADC_WPMR).
If a write access to the protected registers is detected, the WPVS flag in the “ADC Write Protection Status
Register” (ADC_WPSR) is set and the field WPVSRC indicates the register in which the write access has been
attempted.
The WPVS flag is automatically reset by reading the ADC_WPSR.
The following registers can be write-protected:
ADC Mode Register
ADC Channel Sequence 1 Register
ADC Channel Sequence 2 Register
ADC Channel Enable Register
ADC Channel Disable Register
ADC Extended Mode Register
ADC Compare Window Register
ADC Channel Gain Register
ADC Channel Offset Register
ADC Analog Control Register
Base Address (BA)
BA + 0x02
ADC_CDR66
ADC_CDR55
ADC_CDR88BA + 0x04
ADC_CDR66
ADC_CDR55
ADC_CDR88
BA + 0x06
BA + 0x08
BA + 0x0A
ADC_CDR66
ADC_CDR55
ADC_CDR88
BA + [(N-1) * 6]
BA + [(N-1) * 6]+ 0x02
BA + [(N-1) * 6]+ 0x04
Assuming ADC_CHSR = 0x000_01600
ADC_EMR(TAG) = 1
trig.event1
ADC_CDR60
ADC_CDR50
ADC_CDR80
ADC_CDR60
ADC_CDR50
ADC_CDR80
ADC_CDR60
ADC_CDR50
ADC_CDR80
Assuming ADC_CHSR = 0x000_01600
ADC_EMR(TAG) = 0
DMA Buffer
Structure DMA Buffer
Structure
trig.event2
trig.event1
trig.event2
trig.eventN
trig.eventN
DMA Transfer
1097
SAM4S Series [DATASHEET]
Atmel-11100K-ATARM-SAM4S-Datasheet_09-Jun-15
42.7 Analog-to-Digital (ADC) User Interface
Note: Any offset not listed in the table must be considered as “reserved”.
Table 42-7 . Register Mapping
Offset Register Name Access Reset
0x00 Control Register ADC _CR Write-only –
0x04 Mode Register ADC _MR Read/Write 0x00000000
0x08 Channel Sequence Register 1 ADC_SEQR1 Read/Write 0x00000000
0x0C Channel Sequence Register 2 ADC_SEQR2 Read/Write 0x00000000
0x10 Channel Enable Register ADC_CHER Write-only –
0x14 Channel Disable Register ADC_CHDR W rite-only –
0x18 Channel Status Register ADC_CHSR Read-only 0x00000000
0x1C Reserved – – –
0x20 Last Converted Data Register ADC_LCDR R ead-only 0x00000000
0x24 Interrupt Enable Register ADC_IER Write-only –
0x28 Interrupt Disable Register ADC_IDR W rite-only –
0x2C Interrupt Mask Register ADC_IMR Read-only 0x00000000
0x30 Interrupt Status Register ADC_ISR Read-only 0x00000000
0x3C Overrun Status Register ADC_OVER Read-only 0x00000000
0x40 Extended Mode Register ADC_EMR Read/Write 0x00000000
0x44 Compare Window Register ADC_CWR Read/Write 0x00000000
0x48 Channel Gain Register ADC_CGR Read/Write 0x00000000
0x4C Channel Offset Register ADC_COR Read/Write 0x00000000
0x50 Channel Data Register 0 ADC_CDR0 Read-only 0x00000000
0x54 Channel Data Register 1 ADC_CDR1 Read-only 0x00000000
... ... ... ... ...
0x8C Channel Data Register 15 ADC_CDR15 Read-only 0x00000000
0x90–0x90 Reserved – – –
0x94 Analog Control Register ADC_ACR Read/Write 0x00000100
0x98–0xAC Reserved – – –
0xC4–0xE0 Reserved – – –
0xE4 Write Protection Mode Register ADC_WPMR Read/Write 0x00000000
0xE8 Write Protection Status Register ADC_WPSR Read-only 0x00000000
0xEC–0xFC Reserved – – –
0x100–0x124 Reserved for PDC registers – – –
SAM4S Series [DATASHEET]
Atmel-11100K-ATARM-SAM4S-Datasheet_09-Jun-15
1098
42.7.1 ADC Control Register
Name: ADC_CR
Address: 0x40038000
Access: Write-only
• SWRST: Software Reset
0: No effect.
1: Resets the ADC, simulating a hardware reset.
• START: Start Conversion
0: No effect.
1: Begins analog-to-digital conversion.
• AUTOCAL: Automatic Calibrat ion of ADC
0: No effect.
1: Launches an automatic calibration of the ADC cell on the next sequence.
31 30 29 28 27 26 25 24
––––––––
23 22 21 20 19 18 17 16
––––––––
15 14 13 12 11 10 9 8
––––––––
76543210
––––AUTOCAL–STARTSWRST
1099
SAM4S Series [DATASHEET]
Atmel-11100K-ATARM-SAM4S-Datasheet_09-Jun-15
42.7.2 ADC Mode Register
Name: ADC_MR
Address: 0x40038004
Access: Read/Write
This register can only be written if the WPEN bit is cleared in the ADC Write Protection Mode Register.
• TRGEN: Trigger Enable
• TRGSEL: Trigger Selection
• SLEEP: Sleep Mode
• FWUP: Fast Wake Up
31 30 29 28 27 26 25 24
USEQ – TRANSFER TRACKTIM
23 22 21 20 19 18 17 16
ANACH – SETTLING STARTUP
15 14 13 12 11 10 9 8
PRESCAL
76543210
FREERUN FWUP SLEEP – TRGSEL TRGEN
Value Name Description
0 DIS Hardware triggers are disabled. Starting a conversion is only possible by software.
1 EN Hardware trig ger selected by TRGSEL field is enabled.
Value Name Description
0 ADC_TRIG0 External trigger
1 ADC_TRIG1 TIO Output of the Timer Counter Channel 0
2 ADC_TRIG2 TIO Output of the Timer Counter Channel 1
3 ADC_TRIG3 TIO Output of the Timer Counter Channel 2
4 ADC_TRIG4 PWM Event Line 0
5 ADC_TRIG5 PWM Event Line 1
6 ADC_TRIG6 Reserved
7 ADC_TRIG7 Reserved
Value Name Description
0 NORMAL Normal Mode: The ADC core and reference voltage circuitry are kept ON between conversions.
1 SLEEP Sleep Mode: The wake-up time can be modified by programming FWUP bit.
Value Name Description
0 OFF If SLEEP is 1, then both ADC core and reference voltage circuitry are OFF betwe en conversions
1ON
If SLEEP is 1, then Fast Wake-up Sleep mode: The voltage reference is ON between conversions
and ADC core is OFF
SAM4S Series [DATASHEET]
Atmel-11100K-ATARM-SAM4S-Datasheet_09-Jun-15
1100
• FREERUN: Free Run Mode
• PRESCAL: Prescaler Rate Selection
PRESCAL = (fperipheral clock / (2 × fADCCLK)) – 1.
• STARTUP: Startup Time
• SETTLING: Analog Settling Time
• ANACH: Analog Change
• TRACKTIM: Tracking Time
Tracking Time = (TRACKTIM + 1) × ADCCLK periods
Value Name Description
0 OFF Normal Mode
1 ON Free Run Mode: Never wait for any trigger.
Value Name Description
0 SUT0 0 periods of ADCCLK
1 SUT8 8 periods of ADCCLK
2 SUT16 16 periods of ADCCLK
3 SUT24 24 periods of ADCCLK
4 SUT64 64 periods of ADCCLK
5 SUT80 80 periods of ADCCLK
6 SUT96 96 periods of ADCCLK
7 SUT112 112 periods of ADCCLK
8 SUT512 512 periods of ADCCLK
9 SUT576 576 periods of ADCCLK
10 SUT640 640 peri ods of ADCCLK
11 SUT704 704 periods of ADCCLK
12 SUT768 768 peri ods of ADCCLK
13 SUT832 832 peri ods of ADCCLK
14 SUT896 896 peri ods of ADCCLK
15 SUT960 960 peri ods of ADCCLK
Value Name Description
0 AST3 3 periods of ADCCLK
1 AST5 5 periods of ADCCLK
2 AST9 9 periods of ADCCLK
3 AST17 17 periods of ADCCLK
Value Name Description
0 NONE No analog change on channel switching: DIFF0, GAIN0 and OFF0 are used for all channels.
1 ALLOWED Allows different analog settings for each channel. See ADC_CGR and ADC_COR registers.
1101
SAM4S Series [DATASHEET]
Atmel-11100K-ATARM-SAM4S-Datasheet_09-Jun-15
• TRANSFER: Hold Time
The TRANSFER field should be set to 2 to guarantee the optimal hold time.
• USEQ: Use Sequence Enable
Value Name Description
0 NUM_ORDER Normal Mode: The controller converts channels in a simple numeric order depending only on the
channel index.
1 REG_ORDER User Sequence Mode: The sequence respects what is defined in ADC_SEQR1 and ADC_SEQR2
registers and can be used to convert the same channel several times.
SAM4S Series [DATASHEET]
Atmel-11100K-ATARM-SAM4S-Datasheet_09-Jun-15
1102
42.7.3 ADC Channel Sequence 1 Register
Name: ADC_SEQR1
Address: 0x40038008
Access: Read/Write
This register can only be written if the WPEN bit is cleared in the ADC Write Protection Mode Register.
• USCHx: User Sequence Number x
The sequence number x (USCHx) can be programmed by the channel number CHy where y is the value written in this
field. The allowed range is 0 up to 15, thus only the sequencer from CH0 to CH15 can be used.
This register activates only if the USEQ field in ADC_MR field is set to ‘1’.
Any USCHx field is processed only if the CHx field in ADC_CHSR reads logical ‘1’, else any value written in USCHx does
not add the corresponding channel in the conversion sequence.
Configuring the same value in different fields leads to multiple samples of the same channel during the conversion
sequence. This can be done consecutively, or not, according to user needs.
When configuring consecutive fie lds with the same value, the associated channe l is samp led as m any time a s th e n umber
of consecutive values, this part of the conversion sequence being triggered by a unique event.
31 30 29 28 27 26 25 24
USCH8 USCH7
23 22 21 20 19 18 17 16
USCH6 USCH5
15 14 13 12 11 10 9 8
USCH4 USCH3
76543210
USCH2 USCH1
1103
SAM4S Series [DATASHEET]
Atmel-11100K-ATARM-SAM4S-Datasheet_09-Jun-15
42.7.4 ADC Channel Sequence 2 Register
Name: ADC_SEQR2
Address: 0x4003800C
Access: Read/Write
This register can only be written if the WPEN bit is cleared in the ADC Write Protection Mode Register.
• USCHx: User Sequence Number x
The sequence number x (USCHx) can be programmed by the Channel number CHy where y is the value written in this
field. The allowed range is 0 up to 15. So it is only possible to use the sequencer from CH0 to CH15.
This register activates only if the USEQ field in ADC_MR is set to ‘1’.
Any USCHx field is processed only if the CHx field in ADC_CHSR reads logical ‘1’. Else any value written in USCHx does
not add the corresponding channel in the conversion sequence.
Configuring the same value in different fields leads to multiple samples of the same channel during the conversion
sequence. This can be done consecutively, or not, according to user needs.
31 30 29 28 27 26 25 24
– USCH15
23 22 21 20 19 18 17 16
USCH14 USCH13
15 14 13 12 11 10 9 8
USCH12 USCH11
76543210
USCH10 USCH9
SAM4S Series [DATASHEET]
Atmel-11100K-ATARM-SAM4S-Datasheet_09-Jun-15
1104
42.7.5 ADC Channel Enable Register
Name: ADC_CHER
Address: 0x40038010
Access: Write-only
This register can only be written if the WPEN bit is cleared in the ADC Write Protection Mode Register.
• CHx: Channel x Enable
0: No effect.
1: Enables the corresponding channel.
Note: If USEQ = 1 in the ADC_MR, CHx corresponds to the xth channel of the sequence described in ADC_SEQR1 and ADC_SEQR2.
31 30 29 28 27 26 25 24
––––––––
23 22 21 20 19 18 17 16
––––––––
15 14 13 12 11 10 9 8
CH15 CH14 CH13 CH12 CH11 CH10 CH9 CH8
76543210
CH7 CH6 CH5 CH4 CH3 CH2 CH1 CH0
1105
SAM4S Series [DATASHEET]
Atmel-11100K-ATARM-SAM4S-Datasheet_09-Jun-15
42.7.6 ADC Channel Disable Register
Name: ADC_CHDR
Address: 0x40038014
Access: Write-only
This register can only be written if the WPEN bit is cleared in the ADC Write Protection Mode Register.
• CHx: Channel x Disable
0: No effect.
1: Disables the corresponding channel.
Warning: If the corresponding channel is disabled during a conversion or if it is disabled and then reenabled during a con-
version, its associated data and co rrespo nding EOCx and GOVRE flags i n ADC_ISR and OVREx fla gs in ADC_OVER are
unpredictable.
31 30 29 28 27 26 25 24
––––––––
23 22 21 20 19 18 17 16
––––––––
15 14 13 12 11 10 9 8
CH15 CH14 CH13 CH12 CH11 CH10 CH9 CH8
76543210
CH7 CH6 CH5 CH4 CH3 CH2 CH1 CH0
SAM4S Series [DATASHEET]
Atmel-11100K-ATARM-SAM4S-Datasheet_09-Jun-15
1106
42.7.7 ADC Channel Status Register
Name: ADC_CHSR
Address: 0x40038018
Access: Read-only
• CHx: Chan ne l x Status
0: The corresponding channel is disabled.
1: The corresponding channel is enabled.
31 30 29 28 27 26 25 24
––––––––
23 22 21 20 19 18 17 16
––––––––
15 14 13 12 11 10 9 8
CH15 CH14 CH13 CH12 CH11 CH10 CH9 CH8
76543210
CH7 CH6 CH5 CH4 CH3 CH2 CH1 CH0
1107
SAM4S Series [DATASHEET]
Atmel-11100K-ATARM-SAM4S-Datasheet_09-Jun-15
42.7.8 ADC Last Converted Data Register
Name: ADC_LCDR
Address: 0x40038020
Access: Read-only
• LDATA: Last Data Converted
The analog-to-digital conversion data is placed into this register at the end of a conversion and re mains until a new conver-
sion is completed.
• CHNB: Channel Number
Indicates the last converted channel when the TAG bit is set in the ADC_EMR. If the TAG bit is not set, CHNB = 0.
31 30 29 28 27 26 25 24
––––––––
23 22 21 20 19 18 17 16
––––––––
15 14 13 12 11 10 9 8
CHNB LDATA
76543210
LDATA
SAM4S Series [DATASHEET]
Atmel-11100K-ATARM-SAM4S-Datasheet_09-Jun-15
1108
42.7.9 ADC Interrupt Enable Register
Name: ADC_IER
Address: 0x40038024
Access: Write-only
The following configuration values are valid for all listed bit names of this register:
0: No effect.
1: Enables the corresponding interrupt.
• EOCx: End of Conversion Interrupt Enable x
• EOCAL: End of Calibration Sequence
• DRDY: Data Ready Interrupt Enable
• GOVRE: General Overrun Error Interrupt Enable
• COMPE: Comparison Event Interrupt Enable
• ENDRX: End of Receive Buffer Interrupt Enable
• RXBUFF: Receive Buffer Full Interrupt Enable
31 30 29 28 27 26 25 24
– – – RXBUFF ENDRX COMPE GOVRE DRDY
23 22 21 20 19 18 17 16
EOCAL–––– –––
15 14 13 12 11 10 9 8
EOC15 EOC14 EOC13 EOC12 EOC11 EOC10 EOC9 EOC8
76543210
EOC7 EOC6 EOC5 EOC4 EOC3 EOC2 EOC1 EOC0
1109
SAM4S Series [DATASHEET]
Atmel-11100K-ATARM-SAM4S-Datasheet_09-Jun-15
42.7.10 ADC Interrupt Disable Register
Name: ADC_IDR
Address: 0x40038028
Access: Write-only
The following configuration values are valid for all listed bit names of this register:
0: No effect.
1: Disables the corresponding interrupt.
• EOCx: End of Conversion Interrupt Disable x
• EOCAL: End of Calibration Sequence
• DRDY: Data Ready Interrupt Disable
• GOVRE: General Overrun Error Interrupt Disable
• COMPE: Comparison Event Interrupt Disable
• ENDRX: End of Receive Buffer Interrupt Disable
• RXBUFF: Receive Buffer Full Interrupt Disable
31 30 29 28 27 26 25 24
– – – RXBUFF ENDRX COMPE GOVRE DRDY
23 22 21 20 19 18 17 16
EOCAL–––––––
15 14 13 12 11 10 9 8
EOC15 EOC14 EOC13 EOC12 EOC11 EOC10 EOC9 EOC8
76543210
EOC7 EOC6 EOC5 EOC4 EOC3 EOC2 EOC1 EOC0
SAM4S Series [DATASHEET]
Atmel-11100K-ATARM-SAM4S-Datasheet_09-Jun-15
1110
42.7.11 ADC Interrupt Mask Register
Name: ADC_IMR
Address: 0x4003802C
Access: Read-only
The following configuration values are valid for all listed bit names of this register:
0: The corresponding interrupt is disabled.
1: The corresponding interrupt is enabled.
• EOCx: End of Conversion Interrupt Mask x
• EOCAL: End of Calibration Sequence
• DRDY: Data Ready Interrupt Mask
• GOVRE: General Overrun Error Interrupt Mask
• COMPE: Comparison Event Interrupt Mask
• ENDRX: End of Receive Buffer Interrupt Mask
• RXBUFF: Receive Buffer Full Interrupt Mask
31 30 29 28 27 26 25 24
– – – RXBUFF ENDRX COMPE GOVRE DRDY
23 22 21 20 19 18 17 16
EOCAL–––––––
15 14 13 12 11 10 9 8
EOC15 EOC14 EOC13 EOC12 EOC11 EOC10 EOC9 EOC8
76543210
EOC7 EOC6 EOC5 EOC4 EOC3 EOC2 EOC1 EOC0
1111
SAM4S Series [DATASHEET]
Atmel-11100K-ATARM-SAM4S-Datasheet_09-Jun-15
42.7.12 ADC Interrupt Status Register
Name: ADC_ISR
Address: 0x40038030
Access: Read-only
• EOCx: End of Conversion x (automatically set / cleared)
0: The corresponding analog channel is disabled, or the conversion is not finished. This flag is cleared when reading the
corresponding ADC_CDRx registers.
1: The corresponding analog channel is enabled and conversion is complete.
• EOCAL: End of Calibration Sequence
0: Calibration sequence is ongoing, or no calibration sequence has been requested.
1: Calibration sequence is complete.
• DRDY: Data Ready (automatically set / cleared)
0: No data has been converted since the last read of ADC_LCDR.
1: At least one data has been converted and is available in ADC_LCDR.
• GOVRE: General Overrun Error (cleared on read)
0: No general overrun error occurred since the last read of ADC_ISR.
1: At least one general overrun error has occurred since the last read of ADC_ISR.
• COMPE: Comparison Event (cleared on read)
0: No comparison ev ent since the last read of ADC_ISR.
1: At least one comparison event (defined in the ADC_EMR and ADC_CWR) has occurred sinc e the last read of ADC_ISR.
• ENDRX: End of Receive Transfer (cleared by writing ADC_RCR or ADC_RNCR)
0: The Receive Counter Register has not reached 0 since the last write in ADC_RCR or ADC_RNCR(1).
1: The Receive Counter Register has reached 0 since the last write in ADC_RCR or ADC_RNCR(1).
• RXBUFF: Receive Buffer Full (cleared by writing ADC_RCR or ADC_RNCR)
0: ADC_RCR or ADC_RNCR(1) has a value other than 0.
1: Both ADC_RCR and ADC_RNCR(1) have a value of 0.
Note: 1. ADC_RCR and ADC_RNCR are PDC registers
31 30 29 28 27 26 25 24
– – – RXBUFF ENDRX COMPE GOVRE DRDY
23 22 21 20 19 18 17 16
EOCAL–––––––
15 14 13 12 11 10 9 8
EOC15 EOC14 EOC13 EOC12 EOC11 EOC10 EOC9 EOC8
76543210
EOC7 EOC6 EOC5 EOC4 EOC3 EOC2 EOC1 EOC0
SAM4S Series [DATASHEET]
Atmel-11100K-ATARM-SAM4S-Datasheet_09-Jun-15
1112
42.7.13 ADC Overrun Status Register
Name: ADC_OVER
Address: 0x4003803C
Access: Read-only
• OVREx: Overrun Error x
0: No overrun error on the corresponding channel since the last read of ADC_OVER.
1: An overrun error has occurred on the corresponding channel since the last read of ADC_OVER.
31 30 29 28 27 26 25 24
––––––––
23 22 21 20 19 18 17 16
––––––––
15 14 13 12 11 10 9 8
OVRE15 OVRE14 OVRE13 OVRE12 OVRE11 OVRE10 OVRE9 OVRE8
76543210
OVRE7 OVRE6 OVRE5 OVRE4 OVRE3 OVRE2 OVRE1 OVRE0
1113
SAM4S Series [DATASHEET]
Atmel-11100K-ATARM-SAM4S-Datasheet_09-Jun-15
42.7.14 ADC Extended Mode Register
Name: ADC_EMR
Address: 0x40038040
Access: Read/Write
This register can only be written if the WPEN bit is cleared in the ADC Write Protection Mode Register.
• CMPMODE: Comparison Mode
• CMPSEL: Comparison Selected Channel
If CMPALL = 0: CMPSEL indicates which channel has to be compared.
If CMPALL = 1: No effect.
• CMPALL: Compare All Channels
0: Only channel indicated in CMPSEL field is compared.
1: All channels are compared.
• TAG: Tag of the ADC_LCDR
0: Sets CHNB field to zero in ADC_LCDR.
1: Appends the channel number to the conversion result in ADC_LCDR.
31 30 29 28 27 26 25 24
–––––––TAG
23 22 21 20 19 18 17 16
––––––––
15 14 13 12 11 10 9 8
––––––CMPALL–
76543210
CMPSEL – – CMPMODE
Value Name Description
0 LOW Generates an event when the converted data is lower than the low threshold of the window.
1 HIGH Generates an event when the converted data is higher than the high threshold of the win dow.
2 IN Generates an event when the converted data is in the comparison window.
3 OUT Generates an event when the converted data is out of the comparison window.
SAM4S Series [DATASHEET]
Atmel-11100K-ATARM-SAM4S-Datasheet_09-Jun-15
1114
42.7.15 ADC Compare Windo w Register
Name: ADC_CWR
Address: 0x40038044
Access: Read/Write
This register can only be written if the WPEN bit is cleared in the ADC Write Protection Mode Register.
• LOWTHRES: Low Threshold
Low threshold associated to compare settings of the ADC_EMR.
• HIGHTHRES: High Threshold
High threshold associated to compare settings of the ADC_EMR.
31 30 29 28 27 26 25 24
–––– HIGHTHRES
23 22 21 20 19 18 17 16
HIGHTHRES
15 14 13 12 11 10 9 8
–––– LOWTHRES
76543210
LOWTHRES
1115
SAM4S Series [DATASHEET]
Atmel-11100K-ATARM-SAM4S-Datasheet_09-Jun-15
42.7.16 ADC Channel Gain Register
Name: ADC_CGR
Address: 0x40038048
Access: Read/Write
This register can only be written if the WPEN bit is cleared in the ADC Write Protection Mode Register.
• GAINx: Gain for Channel x
Gain applied on input of analog-to-digital converter.
The DIFFx bit in this table is described in Section 42.7.17 “ADC Channel Offset Register”.
31 30 29 28 27 26 25 24
GAIN15 GAIN14 GAIN13 GAIN12
23 22 21 20 19 18 17 16
GAIN11 GAIN10 GAIN9 GAIN8
15 14 13 12 11 10 9 8
GAIN7 GAIN6 GAIN5 GAIN4
76543210
GAIN3 GAIN2 GAIN1 GAIN0
Value Name Description
0SE1_DIFF0_5 Single-ended gain = 1 (ADC_COR.DIFFx = 0), differential gain = 0.5 (ADC_COR.DIFFx = 1)
1SE1_DIFF1 Single-ended gain = 1 (ADC_COR.DIFFx = 0), differential gain = 1 (ADC_COR.DIFFx = 1)
2SE2_DIFF2 Single-ended gain = 2 (ADC_COR.DIFFx = 0), differential gain = 2 (ADC_COR.DIFFx = 1)
3SE4_DIFF2 Single-ended gain = 4 (ADC_COR.DIFFx = 0), differential gain = 2 (ADC_COR.DIFFx = 1)
SAM4S Series [DATASHEET]
Atmel-11100K-ATARM-SAM4S-Datasheet_09-Jun-15
1116
42.7.17 ADC Channel Offset Register
Name: ADC_COR
Address: 0x4003804C
Access: Read/Write
This register can only be written if the WPEN bit is cleared in the ADC Write Protection Mode Register.
• OFFx: Offset for Channel x
0: No offset.
1: Centers the analog signal on VADVREF/2 before the gain scaling. The offset applied is
(G-1)VADVREF/2
where G is the gain applied (see Section 42.7.16 “ADC Channel Gain Register”).
• DIFFx: Differential Inputs for Channel x
0: Single-ended mode.
1: Fully differential mode.
31 30 29 28 27 26 25 24
DIFF15 DIFF14 DIFF13 DIFF12 DIFF11 DIFF10 DIFF9 DIFF8
23 22 21 20 19 18 17 16
DIFF7 DIFF6 DIFF5 DIFF4 DIFF3 DIFF2 DIFF1 DIFF0
15 14 13 12 11 10 9 8
OFF15 OFF14 OFF13 OFF12 OFF11 OFF10 OFF9 OFF8
76543210
OFF7 OFF6 OFF5 OFF4 OFF3 OFF2 OFF1 OFF0
1117
SAM4S Series [DATASHEET]
Atmel-11100K-ATARM-SAM4S-Datasheet_09-Jun-15
42.7.18 ADC Channel Data Register
Name: ADC_CDRx [x=0..15]
Address: 0x40038050
Access: Read/Write
• DATA: Converted Data
The analog-to-digital conversion data is placed into this register at the end of a conversion and re mains until a new conver-
sion is completed. ADC_CDRx is only loaded if the corresponding analog channel is enabled.
31 30 29 28 27 26 25 24
––––––––
23 22 21 20 19 18 17 16
––––––––
15 14 13 12 11 10 9 8
–––– DATA
76543210
DATA
SAM4S Series [DATASHEET]
Atmel-11100K-ATARM-SAM4S-Datasheet_09-Jun-15
1118
42.7.19 ADC Analog Control Register
Name: ADC_ACR
Address: 0x40038094
Access: Read/Write
This register can only be written if the WPEN bit is cleared in the ADC Write Protection Mode Register.
• TSON: Te mperature Sensor On
0: Temperature sensor is off.
1: Temperature sensor is on.
• IBCTL: ADC Bias Current Control
Adapts performance versus power consumption. See the section ‘Electrical Characteristics’ for further details.
31 30 29 28 27 26 25 24
––––––––
23 22 21 20 19 18 17 16
––––––––
15 14 13 12 11 10 9 8
–––––– IBCTL
76543210
–––TSON––––
1119
SAM4S Series [DATASHEET]
Atmel-11100K-ATARM-SAM4S-Datasheet_09-Jun-15
42.7.20 ADC Write Protection Mode Register
Name: ADC_WPMR
Address: 0x400380E4
Access: Read/Write
• WPEN: Write Protec ti on Ena b le
0: Disables the write protection if WPKEY value corresponds to 0x414443 (“ADC” in ASCII).
1: Enables the write protection if WPKEY value corresponds to 0x414443 (“ADC” in ASCII).
See Section 42.6.15 “Register Write Protection” for the list of write-protected registers.
• WPKEY: Write Protection Key
31 30 29 28 27 26 25 24
WPKEY
23 22 21 20 19 18 17 16
WPKEY
15 14 13 12 11 10 9 8
WPKEY
76543210
–––––––WPEN
Value Name Description
0x414443 PASSWD Writing any other value in this field aborts the write operation of the WPEN bit.
Always reads as 0
SAM4S Series [DATASHEET]
Atmel-11100K-ATARM-SAM4S-Datasheet_09-Jun-15
1120
42.7.21 ADC Write Protection Status Register
Name: ADC_WPSR
Address: 0x400380E8
Access: Read-only
• WPVS: Write Protection Violation Status
0: No write protec tion v iola tio n ha s occ u rred since the last read of the ADC_WPSR.
1: A write protection violation has occurred since the last read of the ADC_WPSR. If this violation is an unauthorized
attempt to write a protected register, the associated violation is reported into field WPVSRC.
• WPVSRC: Write Protection Violation Source
When WPVS = 1, WPVSRC indicates the register address offset at which a write access has been attempted.
31 30 29 28 27 26 25 24
––––––––
23 22 21 20 19 18 17 16
WPVSRC
15 14 13 12 11 10 9 8
WPVSRC
76543210
–––––––WPVS
1121
SAM4S Series [DATASHEET]
Atmel-11100K-ATARM-SAM4S-Datasheet_09-Jun-15
43. Digital-to-Analog Converter Controller (DACC)
43.1 Description
The Digital-to-Analog Converter Controller (DACC) provides up to 2 analog outputs, making it possible for the
digital-to-a na lo g co nve r sion to drive up to 2 ind ep end e nt an a log lines .
The DACC supports 12-bit resolution. Data to be converted are sent in a common register for all channels.
External triggers or free-running mode are configurable.
43.2 Embedded Characteristics
Up to Two Independent Analog Outputs
12-bit Resolution
Individual Enable and Disable of Each Analog Channel
Hardware Trigger
External Trigger Pins
PDC Support
Internal FIFO
Register Write Protection
SAM4S Series [DATASHEET]
Atmel-11100K-ATARM-SAM4S-Datasheet_09-Jun-15
1122
43.3 Block Diagram
Figure 43-1. DACC Block Diagram
43.4 Signal Description
43.5 Product Dependencies
43.5.1 Power Management
The user must first enable the DAC Controller Clock in the Power Management Controller (PMC) before using the
DACC.
The DACC becomes active as soon as a con ver sio n is r eq ue st ed an d at lea s t o ne ch an ne l is en ab le d. Th e DAC C
is automatically deactivated when no channels are enabled.
DAC0
Analog Cell (DAC)
DAC Controller (DACC)
Control
Logic
Interrupt
Controller
PDC
Peripheral Bridge
User
Interface
Sample & Hold 0
DATRG
DAC Core
Sample & Hold 1
DAC1
PMC
peripheral clock
Timer Counter (TC)
Trigger
Selection DAC Clock
External triggers
Table 43-1. DACC Pin Description
Pin Name Description
DAC0–DAC1 Analog output channels
DATRG External triggers
1123
SAM4S Series [DATASHEET]
Atmel-11100K-ATARM-SAM4S-Datasheet_09-Jun-15
For power-saving options, see Section 43.6.6 ”DACC Timings”.
43.5.2 Interrupt Sources
The DACC interrupt line is connected to one of the interna l sources of the interrupt contr oller. Using the DACC
interrupt requires the interrupt controller to be programmed first.
43.5.3 Conversion Performances
For performance and electrical characteristics of the DACC, see the product DC Characteristics section of the
datasheet.
Table 43-2. Peripheral IDs
Instance ID
DACC 30
SAM4S Series [DATASHEET]
Atmel-11100K-ATARM-SAM4S-Datasheet_09-Jun-15
1124
43.6 Functional Description
43.6.1 Digital-to-Analog Conversion
The DACC uses the peripher al clock divi d ed by two to perform conversions. This clock is named DAC clock. Once
a conversion starts, the DACC takes 25 clock periods to provide the analog result on the selected analog output .
43.6.2 Conversion Results
When a conversion is completed, the resulting analog value is available at the selected DACC channel output and
the EOC bit in the DACC Interrupt Status Register (DACC_ISR) is set.
Reading the DACC_ISR clears the EOC bit.
43.6.3 Conversion Triggers
In free-running mod e, conversion starts as soo n as at least one channel is enable d and data is written in the DACC
Conversion Data Register (DACC_CDR). 25 DAC clock periods later, the converted data is available at the
corresponding analog output as stated above.
In external trigger mode, the conversion waits for a rising edge on the selecte d trigger to begin.
Warning: Disabling the external trigger mode automatically sets the DACC in free-running mode.
43.6.4 Conversion FIFO
A four half-word FIFO is used to handle the data to be converted.
If the TXRDY flag in the DACC_ISR is active, the DACC is ready to accept conversion re quests by writing d ata into
the DATA field in the DACC_CDR. Data which cannot be converted immediately is stored in the DACC FIFO.
When the FIFO is full or when the DACC is not ready to accept conversion requests, the TXRDY flag is inactive.
The WORD field of the DACC Mode Register (DACC_MR) allows the us er to switch between half-word and word
transfers in order to write into the FIFO.
In half-word tr ansfer mode, only the 16 LSBs of DACC_CDR data are processed. Bits DATA[15:0] are stor ed in the
FIFO. Bits DATA [11 :0] ar e us ed as da ta. Bits DATA[15:12] are used for channel selection if the TAG field is set in
DACC_MR.
In word transfer mode, each time DACC_CDR is written, two data items are stored in the FIFO. The first data item
sampled for conversion is DATA[1 5:0] and the second is DATA[31:16]. Bits DATA[15:12] and DATA[3 1:28] are
used for channel selection if the TAG field is set in DACC_MR.
Warning: Writing in the DACC_CDR while the TXRDY flag is inactive will corrupt FI FO data.
43.6.5 Channel Selection
There are two ways to select the channel to perform data conversion.
By default, the USER_SEL field of the DACC_MR is used. Data requests are converted to the channel
selected with the USER_SEL field.
Alternatively, the tag mode can be used by setting the TAG field of the DACC_MR to 1. In this mode, the two
bits, DACC_CDR[13:12], which are otherwise unused, are employed to select the channel in the same way
as with the USER_SEL field. Finally, if the WORD field is set, the two bits, DACC_CDR[13:12] are used for
channel selection of the first data and the two bits, DACC_CDR[29:28] for channel selection of the second
data.
43.6.6 DACC Timings
The DACC start-up time must be defined by the user in the STARTUP field of the DACC_MR.
1125
SAM4S Series [DATASHEET]
Atmel-11100K-ATARM-SAM4S-Datasheet_09-Jun-15
A maximum speed mode is available by setting the MAXS bit in the DACC_MR. In this mode, the DACC no longer
waits to sample the end-of-cycle signal coming from the DACC block to start the next conversion. An internal
counter is used instead, thus gaining two peripheral clock periods between each consecutive conversion.
Warning: If the maximum speed mode is used, the EOC interrupt of the DACC_IER should not be used as it is two
peripheral clock periods late.
The accuracy of the analog voltage resulting from the data conversion process cannot be guaranteed due to
leakage. To ensure accuracy, the channel must be refreshed on a regular basis. A value is correctly refreshed if
the correct sampling period is selected (see DACC electrical characteristics) and the software or PDC is able to
sustain writing to DACC_CDR at the rate imposed by the trigger period.
Figure 43-2. Conversion Sequ ence
43.6.7 Register Write Protection
To prevent any single software er ror from corrupting DACC behavior, certain re gisters in the address space can be
write-protected by setting the WPEN bit in the DACC Write Protection Mode Register (DACC_WPMR).
If a write access to a write-protected register is detected, the WPVS flag in the DACC Write Protection Status
Register (DACC_WPSR) is set and the field WPVSRC in dicates the register in which the write access has been
attempted.
The WPVS bit is automatically cleared after reading the DACC_WPSR.
The following registers can be write-protected:
DACC Mode Register
DACC Channel Enable Register
DACC Channel Disable Register
DACC Analog Current Register
Peripheral clock
Write USER_SEL
field
Selected Channel
Write DACC_CDR
DAC Channel 0
Output
DAC Channel 1
Output
EOC
Read DACC_ISR
Select Channel 0
Channel 0 Channel 1
Data 0Data 1Data 2
Data 0Data 1
Data 2
Select Channel 1
None
TXRDY CDR FIFO not full
SAM4S Series [DATASHEET]
Atmel-11100K-ATARM-SAM4S-Datasheet_09-Jun-15
1126
43.7 Digital-to-Analog Converter Controller (DACC) User Interface
Table 43-3 . Register Mapping
Offset Register Name Access Reset
0x00 Control Register D ACC_CR Write-only –
0x04 Mode Register D AC C_MR Read/Write 0x00000000
0x08–0x0C Reserved – – –
0x10 Channel Enable Register DACC_CHER Write-only –
0x14 Channel Disable Register DACC_CHDR Write-only –
0x18 Channel Status Register DACC_CHSR Read-only 0x00000000
0x1C Reserved – – –
0x20 Conversion Data Register DACC_CDR Write-only –
0x24 Interrupt Enable Register DACC_IER Write-only –
0x28 Interrupt Disable Register DACC_IDR Write-only –
0x2C Interrupt Mask Register DACC_IMR Read-only 0x00000000
0x30 Interrupt Status Register DACC_ISR Read-only 0x00000000
0x34–0x90 Reserved – – –
0x94 Analog Current Registe r DACC_ACR Read/Write 0x00000000
0x98–0xE0 Reserved – – –
0xE4 Write Protection Mode Register DACC_WPMR Read/Write 0x00000000
0xE8 Write Protection Status Register DACC_WPSR Read-only 0x00000000
0xEC–0xFC Reserved – – –
1127
SAM4S Series [DATASHEET]
Atmel-11100K-ATARM-SAM4S-Datasheet_09-Jun-15
43.7.1 DACC Control Register
Name: DACC_CR
Address: 0x4003C000
Access: Write-only
• SWRST: Software Reset
0: No effect
1: Resets the DACC, simulating a hardware reset
31 30 29 28 27 26 25 24
––––––––
23 22 21 20 19 18 17 16
––––––––
15 14 13 12 11 10 9 8
––––––––
76543210
–––––––SWRST
SAM4S Series [DATASHEET]
Atmel-11100K-ATARM-SAM4S-Datasheet_09-Jun-15
1128
43.7.2 DACC Mode Register
Name: DACC_MR
Address: 0x4003C004
Access: Read/Write
This register can only be written if the WPEN bit is cleared in the DACC Write Protection Mode Register.
• TRGEN: Trigger Enable
• TRGSEL: Tr igger Selection
• WORD: Word Transfer
• ONE: Must Be Set to 1
Bit 8 must always be set to 1 when programming the DACC_MR
• USER_SEL: User Channel Selection
31 30 29 28 27 26 25 24
– – STARTUP
23 22 21 20 19 18 17 16
– – MAXS TAG – – USER_SEL
15 14 13 12 11 10 9 8
–––––––ONE
76543210
–––WORD TRGSEL TRGEN
Value Name Description
0 DIS External trigge r mode disabled. DACC in free-running mode.
1 EN External trigger mode enabled.
Value Name Description
0TRGSEL0 External trigger
1TRGSEL1 TIO Output of the Timer Counter Channel 0
2TRGSEL2 TIO Output of the Timer Counter Channel 1
3TRGSEL3 TIO Output of the Timer Counter Channel 2
4TRGSEL4 PWM Event Line 0
5TRGSEL5 PWM Event Line 1
6TRGSEL6 Reserved
Value Name Description
0 HALF Half-word transfer
1 WORD Word transfer
Value Name Description
0 CHANNEL0 Channel 0
1 CHANNEL1 Channel 1
1129
SAM4S Series [DATASHEET]
Atmel-11100K-ATARM-SAM4S-Datasheet_09-Jun-15
• TAG: Tag Selection Mode
• MAXS: Maximum Speed Mode
• STARTUP: Startup Time Selection
Value Name Description
0 DIS Tag selection mode disabled. Using USER_SEL to select the channel for the conversion.
1 EN Tag selection mode enabled
Value Name Description
0 NORMAL Normal mode
1 MAXIMUM Maximum speed mode enabled
Value Name Description
0 0 0 periods of peripheral clock
1 8 8 periods of peripheral clock
2 16 16 periods of peripheral clock
3 24 24 periods of peripheral clock
4 64 64 periods of peripheral clock
5 80 80 periods of peripheral clock
6 96 96 periods of peripheral clock
7 112 112 periods of peripheral clock
8 512 512 periods of peripheral clock
9 576 576 periods of peripheral clock
10 640 640 periods of peripheral clock
11 704 704 periods of peripheral clock
12 768 768 periods of peripheral clock
13 832 832 periods of peripheral clock
14 896 896 periods of peripheral clock
15 960 960 periods of peripheral clock
16 1024 1024 periods of peripheral clock
17 1088 1088 periods of peripheral clock
18 1152 1152 periods of peripheral clock
19 1216 1216 periods of peripheral clock
20 1280 1280 periods of peripheral clock
21 1344 1344 periods of peripheral clock
22 1408 1408 periods of peripheral clock
23 1472 1472 periods of peripheral clock
24 1536 1536 periods of peripheral clock
25 1600 1600 periods of peripheral clock
26 1664 1664 periods of peripheral clock
27 1728 1728 periods of peripheral clock
SAM4S Series [DATASHEET]
Atmel-11100K-ATARM-SAM4S-Datasheet_09-Jun-15
1130
Note: Refer to the DAC electrical characteristics section in the datasheet for start-up time value.
28 1792 1792 periods of peripheral clock
29 1856 1856 periods of peripheral clock
30 1920 1920 periods of peripheral clock
31 1984 1984 periods of peripheral clock
32 2048 2048 periods of peripheral clock
33 2112 2112 periods of peripheral clock
34 2176 2176 periods of peripheral clock
35 2240 2240 periods of peripheral clock
36 2304 2304 periods of peripheral clock
37 2368 2368 periods of peripheral clock
38 2432 2432 periods of peripheral clock
39 2496 2496 periods of peripheral clock
40 2560 2560 periods of peripheral clock
41 2624 2624 periods of peripheral clock
42 2688 2688 periods of peripheral clock
43 2752 2752 periods of peripheral clock
44 2816 2816 periods of peripheral clock
45 2880 2880 periods of peripheral clock
46 2944 2944 periods of peripheral clock
47 3008 3008 periods of peripheral clock
48 3072 3072 periods of peripheral clock
49 3136 3136 periods of peripheral clock
50 3200 3200 periods of peripheral clock
51 3264 3264 periods of peripheral clock
52 3328 3328 periods of peripheral clock
53 3392 3392 periods of peripheral clock
54 3456 3456 periods of peripheral clock
55 3520 3520 periods of peripheral clock
56 3584 3584 periods of peripheral clock
57 3648 3648 periods of peripheral clock
58 3712 3712 periods of peripheral clock
59 3776 3776 periods of peripheral clock
60 3840 3840 periods of peripheral clock
61 3904 3904 periods of peripheral clock
62 3968 3968 periods of peripheral clock
63 4032 4032 periods of peripheral clock
Value Name Description
1131
SAM4S Series [DATASHEET]
Atmel-11100K-ATARM-SAM4S-Datasheet_09-Jun-15
43.7.3 DACC Channel Enable Register
Name: DACC_CHER
Address: 0x4003C010
Access: Write-only
This register can only be written if the WPEN bit is cleared in the DACC Write Protection Mode Register.
• CHx: Channel x Enable
0: No effect
1: Enables the corresponding channel
31 30 29 28 27 26 25 24
––––––––
23 22 21 20 19 18 17 16
––––––––
15 14 13 12 11 10 9 8
––––––––
76543210
––––––CH1CH0
SAM4S Series [DATASHEET]
Atmel-11100K-ATARM-SAM4S-Datasheet_09-Jun-15
1132
43.7.4 DACC Channel Disable Register
Name: DACC_CHDR
Address: 0x4003C014
Access: Write-only
This register can only be written if the WPEN bit is cleared in the DACC Write Protection Mode Register.
• CHx: Channel x Disable
0: No effect
1: Disables the corresponding channel
Warning: If the corresponding channel is disabled during a conversion, or disabled then re-enabled during a conversion,
the associated analog value and the corresponding EOC flags in the DACC_ISR are unpredictable.
31 30 29 28 27 26 25 24
––––––––
23 22 21 20 19 18 17 16
––––––––
15 14 13 12 11 10 9 8
––––––––
76543210
––––––CH1CH0
1133
SAM4S Series [DATASHEET]
Atmel-11100K-ATARM-SAM4S-Datasheet_09-Jun-15
43.7.5 DACC Channel Status Register
Name: DACC_CHSR
Address: 0x4003C018
Access: Read-only
• CHx: Chan ne l x Status
0: Corresponding channel is disabled
1: Corresponding channel is enabled
31 30 29 28 27 26 25 24
––––––––
23 22 21 20 19 18 17 16
––––––––
15 14 13 12 11 10 9 8
––––––––
76543210
––––––CH1CH0
SAM4S Series [DATASHEET]
Atmel-11100K-ATARM-SAM4S-Datasheet_09-Jun-15
1134
43.7.6 DACC Conversion Data Register
Name: DACC_CDR
Address: 0x4003C020
Access: Write-only
• DATA: Data to Convert
When the WORD bit in DACC_MR is cleared, only DATA[15:0] is used; else DATA[31:0] is used to write two data to be
converted.
31 30 29 28 27 26 25 24
DATA
23 22 21 20 19 18 17 16
DATA
15 14 13 12 11 10 9 8
DATA
76543210
DATA
1135
SAM4S Series [DATASHEET]
Atmel-11100K-ATARM-SAM4S-Datasheet_09-Jun-15
43.7.7 DACC Interrupt Enable Register
Name: DACC_IER
Address: 0x4003C024
Access: Write-only
The following configuration values are valid for all listed bit names of this register:
0: No effect
1: Enables the corresponding interrupt
• TXRDY: Transmit Ready Interrupt Enable
• EOC: End of Conversion Interrupt Enable
• ENDTX: End of Transmit Buffer Interrupt Enable
• TXBUFE: Transmit Buffer Empty Interrupt Enable
31 30 29 28 27 26 25 24
––––––––
23 22 21 20 19 18 17 16
––––––––
15 14 13 12 11 10 9 8
––––––––
76543210
––––TXBUFEENDTXEOCTXRDY
SAM4S Series [DATASHEET]
Atmel-11100K-ATARM-SAM4S-Datasheet_09-Jun-15
1136
43.7.8 DACC Interrupt Disable Register
Name: DACC_IDR
Address: 0x4003C028
Access: Write-only
The following configuration values are valid for all listed bit names of this register:
0: No effect
1: Disables the corresponding interrupt
• TXRDY: Transmit Ready Interrupt Disable.
• EOC: End of Conversion Interrupt Disable
• ENDTX: End of Transmit Buffer Interrupt Disable
• TXBUFE: Transmit Buffer Empty Interrupt Disable
31 30 29 28 27 26 25 24
––––––––
23 22 21 20 19 18 17 16
––––––––
15 14 13 12 11 10 9 8
––––––––
76543210
––––TXBUFEENDTXEOCTXRDY
1137
SAM4S Series [DATASHEET]
Atmel-11100K-ATARM-SAM4S-Datasheet_09-Jun-15
43.7.9 DACC Interrupt Mask Register
Name: DACC_IMR
Address: 0x4003C02C
Access: Read-only
The following configuration values are valid for all listed bit names of this register:
0: Corresponding interrupt is not enabled
1: Corresponding interrupt is enabled
• TXRDY: Transmit Ready Interrupt Mask
• EOC: End of Conversion Interrupt Mask
• ENDTX: End of Transmit Buffer Interrupt Mask
• TXBUFE: Transmit Buffer Empty Interrupt Mask
31 30 29 28 27 26 25 24
––––––––
23 22 21 20 19 18 17 16
––––––––
15 14 13 12 11 10 9 8
––––––––
76543210
––––TXBUFEENDTXEOCTXRDY
SAM4S Series [DATASHEET]
Atmel-11100K-ATARM-SAM4S-Datasheet_09-Jun-15
1138
43.7.10 DACC Interrupt Status Register
Name: DACC_ISR
Address: 0x4003C030
Access: Read-only
• TXRDY: Transmit Ready Interrupt Flag
0: DACC is not ready to accept new conversion requests.
1: DACC is ready to accept new conversion requests.
• EOC: End of Conversion Interrupt Flag
0: No conversion has been performed since the last DACC_ISR read.
1: At least one conversion has been performed since the last DACC_ISR read.
• ENDTX: End of DMA Interrupt Flag
0: The Transmit Counter register has not reached 0 since the last write in DACC_TCR or DACC_TNCR.
1: The Transmit Counter register has reached 0 since the last write in DACC _TCR or DACC_TNCR.
• TXBUFE: Transmit Buffer Empty
0: The Transmit Counter register has not reached 0 since the last write in DACC_TCR or DACC_TNCR.
1: The Transmit Counter register has reached 0 since the last write in DACC _TCR or DACC_TNCR.
31 30 29 28 27 26 25 24
––––––––
23 22 21 20 19 18 17 16
––––––––
15 14 13 12 11 10 9 8
––––––––
76543210
––––TXBUFEENDTXEOCTXRDY
1139
SAM4S Series [DATASHEET]
Atmel-11100K-ATARM-SAM4S-Datasheet_09-Jun-15
43.7.11 DACC Analog Current Register
Name: DACC_ACR
Address: 0x4003C094
Access: Read/Write
This register can only be written if the WPEN bit is cleared in the DACC Write Protection Mode Register.
• IBCTLCHx: Analog Output Current Control
Used to modify the slew rate of the analog output (See the product Electrical Characteristics section for further details.)
• IBCTLDACCORE: Bias Current Control for DAC Core
Used to modify performance versus power consumption (See the product Electrical Characteristics section for further
details.)
31 30 29 28 27 26 25 24
––––––––
23 22 21 20 19 18 17 16
––––––––
15 14 13 12 11 10 9 8
––––––IBCTLDACCORE
76543210
–––– IBCTLCH1 IBCTLCH0
SAM4S Series [DATASHEET]
Atmel-11100K-ATARM-SAM4S-Datasheet_09-Jun-15
1140
43.7.12 DACC Write Protection Mode Register
Name: DACC_WPMR
Address: 0x4003C0E4
Access: Read/Write
• WPEN: Write Protec ti on Ena b le
0: Disables the write protection if WPKEY corresponds to 0x444143 (“DAC” in ASCII).
1: Enables the write protection if WPKEY corresponds to 0x444143 (“DAC” in ASCII).
See Section 43.6.7 ”Register Write Protection” for the list of registers that can be write-protected.
• WPKEY: Write Protection Key
31 30 29 28 27 26 25 24
WPKEY
23 22 21 20 19 18 17 16
WPKEY
15 14 13 12 11 10 9 8
WPKEY
76543210
–––––––WPEN
Value Name Description
0x444143 PASSWD Writing any other value in this field aborts the write operation of the WPEN bit.
Always reads as 0.
1141
SAM4S Series [DATASHEET]
Atmel-11100K-ATARM-SAM4S-Datasheet_09-Jun-15
43.7.13 DACC Write Protection Status Register
Name: DACC_WPSR
Address: 0x4003C0E8
Access: Read-only
• WPVS: Write Protection Violation Status
0: No write protec tion v iola tio n ha s occ u rred since the last read of the DACC_WPSR.
1: A write protection violation has occurred since the last read of the DACC_WPSR. If this violation is an unauthorized
attempt to write a protected register, the associated violation is reported into field WPVSRC.
• WPVSRC: Write Protection Violation Source
When WPVS = 1, WPVSRC indicates the register address offset at which a write access has been attempted.
31 30 29 28 27 26 25 24
––––––––
23 22 21 20 19 18 17 16
––––––––
15 14 13 12 11 10 9 8
WPVSRC
76543210
–––––––WPVS
SAM4S Series [DATASHEET]
Atmel-11100K-ATARM-SAM4S-Datasheet_09-Jun-15
1142
44. Electrical Characteristics
44.1 Absolute Maximum Ratings
44.2 Recommended Operating Conditions
Table 44-1. Absolute Maximum Ratings*
Storage Temperature................... ... ............ -60°C to + 150°C *Notice: Stresses beyond those listed under “Absolute Maximum
Ratings” may cause permanent damage to the device. This
is a stress rating only and functional operation of the device
at these or other conditions beyond those indicated in the
operational sections of this specification is not implied.
Exposure to absolute maximum rating conditions for
extended periods may affec t device reliability.
Solder Temperature......................................................260°C
Voltage on all input pins
with Respect to Ground..................-0.3V to + VDDIO + 0.4V
Maximum Operating Voltage
(VDDCORE)...................................................................1.32V
Maximum Operating Voltage
(VDDIO)...........................................................................4.0V
Total DC Output Current on all I/O lines
100-lead LQFP............................................................150 mA
100-ball TFBGA..........................................................150 mA
100-ball VFBGA..........................................................150 mA
64-lead LQFP.......................................... ... ... ..............100 mA
64-lead QFN.......... ...... ..... ...... ..... ...... ... ...... ..... ...... ..... .100 mA
64-lead WLCSP..................... ............................ ... ... ....100 mA
Table 44-2 . Recommended Operating Conditions
Symbol Parameter Conditions Min Typ Max Unit
TAAmbient Temperature Range -40 – +105 °C
VDDCORE DC Supply Core 1.08 1 .20 1.32 V
VDDIO DC Supply I/Os 1.62 3.3 3.6 V
VDDPLL PLL A, PLLB and Main Oscillator Supply 1.08 – 1.32 V
Vrip(VDDIO) Supply Ripple Voltage (on VDDIO ) RMS value, 10 kHz to 10 MHz – – 30 mV
Vrip(VDDPLL) Supply Ripple V oltage (on VDDPLL) RMS value, 10 kHz to 10 MHz – – 20 mV
RMS value > 10 MHz – – 10
Vrip(VDDIN) Supply Ripple Voltage (on VDDIN) RMS value, 10 kHz to 20 MHz – – 20 mV
fMCK Master Clock Frequency VDDCORE @ 1.20V – – 120 MHz
VDDCORE @ 1.08V – – 100
1143
SAM4S Series [DATASHEET]
Atmel-11100K-ATARM-SAM4S-Datasheet_09-Jun-15
44.3 DC Characteristics
The following characteristics are applicable to the operating temperature range -40°C to 105°C, unless otherwise
specified.
Table 44-3 . DC Characteristics
Symbol Parameter Conditions Min Typ Max Unit
VDDCORE DC Supply Core 1.08 1.2 1.32 V
VDDIO DC Supply I/Os (2) 1.62 3.3 3.6 V
VDDPLL PLL A, PLLB and Main
Oscillator Supply 1.08 – 1.32 V
VIL Input Low-level Voltage PA0–PA31, PB0-PB14, PC0–PC31, NRST -0.3 – MIN
[0.8V:0.3 ×
VDDIO]V
VIH Input High-level Voltage PA0–PA31, PB0–PB14, PC0–PC31, NRST MIN[2.0V:0.7
× VDDIO]–VDDIO
+0.3V V
VOH Output High-level
Voltage
PA0–PA31, PB0–PB9, PB12–PB14, PC0–PC31 VDDIO - 0.4V – –
V
VDDIO [3.0V–3.6V]
PB10–PB11 VDDIO -0.15V – –
VOL Output Low-level Voltage
PA0–PA31, PB0–PB9, PB12–PB14, PC0–PC31 –
V
––
VDDIO [3.0V–3.6V]
PB10–PB11 – – 0.15
Vhys Hysteresis Voltage PA0–PA31, PB0–PB9, PB12–PB14, PC0–PC31
(Hysteresis mode enabled) 150 – – mV
IOH Source Current
VDDIO [1.65V–3.6V]; VOH = VDDIO - 0.4
- PA14 (SPCK), PA29 (MCCK) pins
- PA[12–13], PA[26–28], PA[30–31] pins
- PA[0–3]
- NRST
- Other pins(1)
VDDIO [3.0V–3.6V]
- PB[10–11]
––
-4
-4
-2
-2
-2
-30
mA
IOL Sink Current
VDDIO [1.65V–3.6V]; VOL = 0.4V
- PA14 (SPCK), PA29 (MCCK) pins
- PA[12–13], PA[26–28], PA[30–31] pins
- PA[0–3]
- NRST
- Other pins(1)
VDDIO [3.0V–3.6V]
- PB[10–11]
––
4
4
2
2
2
30
mA
IIL Input Low Pull_up OFF -1 – 1 µA
Pull_up ON 10 – 50
IIH Input High Pull-down OFF -1 – 1 µA
Pull-down ON 10 – 50
RPULLUP Pull-up Resistor PA0–PA31, PB0–PB14, PC0–PC31, NRST 70 100 130 kΩ
SAM4S Series [DATASHEET]
Atmel-11100K-ATARM-SAM4S-Datasheet_09-Jun-15
1144
Note: 1. PA[4–11], PA[15–25], PB[0–9], PB[1 2–14], PC[0–31]
2. Refer to Section 5.2.2 “VDDIO Versus VDDIN”
3. The Flash programming characteristics are applicable at operating temperature range: TA = -40 to 85 °C.
RPULLDOWN Pull-down Resistor PA0–PA31, PB0–PB14, PC0–PC31, NRST 70 100 130 kΩ
RODT On-die Series
Termination Resistor PA4–PA31, PB0–PB9, PB12–PB14, PC0–PC31 – 36 – Ω
PA0–PA3 – 18 –
ICC Flash Active Current on
VDDCORE
Random 144-bit Read @ 25°C:
Maximum read frequency at VDDCORE = 1.2V,
VDDIO = 3.3V –1625
mA
Random 72-bit Read @ 25°C:
Maximum read frequency at VDDCORE = 1.2V,
VDDIO = 3.3V –1018
Program(3) onto VDDCORE = 1.2V,
VDDIO = 3.3V @ 25°C –35
ICC33 Flash Active Current on
VDDIO
Random 144-bit read:
Maximum read frequency at VDDCORE = 1.2V,
VDDIO = 3.3V @ 25°C –316
mA
Random 72-bit read:
Maximum read frequency at VDDCORE = 1.2V,
VDDIO = 3.3V @ 25°C –35
Program(3) onto VDDCORE = 1.2V,
VDDIO = 3.3V @ 25°C –1015
Table 44-3 . DC Characteristics (Continued)
Symbol Parameter Conditions Min Typ Max Unit
1145
SAM4S Series [DATASHEET]
Atmel-11100K-ATARM-SAM4S-Datasheet_09-Jun-15
Notes: 1. A 4.7µF or higher ceramic capacitor must be connected between VDDIN and the closest GND pin of the device.
This large decoupling capacitor is mandatory to reduce startup current, improving transient response and noise rejection.
2. To ensure stability, an external 2.2 µF output capacitor, CDOUT must be connected between the VDDOUT and the closest
GND pin of the device. The ESR (Equivalent Series Resistance) of the capacitor must be in the range 0.1 to 10 Ω.
Solid tantalum, and multilayer ceramic capacitors are all suitable as output capacitor.
A 100 nF bypass capacitor between VDDOUT and the closest GND pin of the device helps decrease output noise and
improves the load transient response.
3. Defined as the current needed to charge external bypass/decoupling capacitor network.
4. See Section 5.2.2 “VDDIO Versus VDDIN”
Table 44-4 . 1.2V Voltage Regulator Characteris tics
Symbol Parameter Conditions Min Typ Max Unit
VDDIN DC Input Voltage (4) 1.6 3.3 3.6 V
VDDOUT DC Output Voltage Normal Mode – 1.2 – V
Standby Mode – 0 –
VO(accuracy) Output Voltage Accuracy ILOAD = 0.8mA to 80mA (after trimming) -3 3 %
ILOAD Maximum DC Output Current VDDIN > 1.8V – – 80
mA
VDDIN ≤ 1.8V – – 40
ILOAD-START Maximum Peak Current during
Startup (3) ––400
VDROPOUT Dropout Voltage VDDIN = 1.6V, ILOAD = Max – 400 – mV
VLINE Line Regulation VDDIN from 2.7V to 3.6V; ILOAD MAX – 10 30 mV
VLINE-TR Transient Line Regulation VDDIN from 2.7V to 3.6V; tr = tf = 5µs; ILOAD Max – 50 150
VLOAD Load Regulation VDDIN ≥ 1.8V; ILOAD = 10% to 90% MAX – 20 40 mV
VLOAD-TR Transient Load Regul ation VDDIN ≥ 1.8V ; I LOAD = 10% to 90% MAX;
tr = tf = 5 µs –50150mV
IQQuiescent Current
Normal Mode, ILOAD = 0 mA – 5 –
µANormal Mode, ILOAD = 80 mA – 500 –
Standby Mode – 500 1
CDIN Input Decoupling Capacitor (1) –4.7–µF
CDOUT Output Decoupling Capacitor (2) 1.85 2.2 5.9 µF
ESR 0.1 10 Ω
ton Turn-on Time CDOUT = 2.2µF, VDDOUT reaches 1.2V (± 3%) – 300 – µs
toff Turn-off Time CDOUT = 2.2µF – – 40 ms
SAM4S Series [DATASHEET]
Atmel-11100K-ATARM-SAM4S-Datasheet_09-Jun-15
1146
Note: 1. The product is guaranteed to be functional at VT-
Figure 44-1. Core Brownout Output Waveform
Table 44-5. Core Power Supply Brownout Detec t or Characteristics
Symbol Parameter Conditions Min Typ Max Unit
VT- Supply Falling Threshold(1) 0.98 1.0 1.04 V
Vhys Hysteresis Voltage – – 110 m V
VT+ Supply Rising Threshold 0.8 1.0 1.08 V
tRST Reset Period VDDIO rising from 0 to 1.2V ± 10% 90 – 320 µs
IDDON Current Consumption on VDDCORE Brownout Detector enabled – – 24 µA
IDDOFF Brownout Detector disabled – – 2
IDD33ON Current Consumption on VDDIO Brownout Detector enabled – – 24 µA
IDD33OFF Brownout Detector disabled – – 2
td- VT- Detection Propagation Time VDDCORE = VT+ to (VT- - 100mV) – 200 300 ns
tSTART Startup Time From disabled state to enabled state – – 300 µs
t
VDDCORE
VT-
VT+
BOD OUTPUT
t
td+
td-
Table 44-6. VDDIO Supply Monitor
Symbol Parameter Conditions Min Typ Max Unit
VTSupply Monitor Threshold 16 selectable steps 1.6 – 3.4 V
VT(accuracy) Threshold Level Accuracy [-40/+105°C] -2.5 – +2.5 %
Vhys Hysteresis Voltage – – 20 30 mV
IDDON Current Consumption Enabled – 23 40 µA
IDDOFF Disabled – 0.02 2
tSTART Startup Time From disabled state to enabled state – – 300 µs
1147
SAM4S Series [DATASHEET]
Atmel-11100K-ATARM-SAM4S-Datasheet_09-Jun-15
Figure 44-2. VDDIO Supply Monitor
Table 44-7. Threshold Selection
Digital Code Threshold Min (V) Threshol d Typ (V) Threshold Max (V)
0000 1.56 1.6 1.64
0001 1.68 1.72 1.76
0010 1.79 1.84 1.89
00111.911.962.01
0100 2.03 2.08 2.13
0101 2.15 2.2 2.23
0110 2.26 2.32 2.38
0111 2.38 2.44 2.50
1000 2.50 2.56 2.62
1001 2.61 2.68 2.75
1010 2.73 2.8 2.87
10112.852.922.99
1100 2.96 3.04 3.12
1101 3.08 3.16 3.24
1110 3.20 3.28 3.36
1111 3.32 3.4 3.49
VT
VT
+
Vhys
VDDIO
Reset
SAM4S Series [DATASHEET]
Atmel-11100K-ATARM-SAM4S-Datasheet_09-Jun-15
1148
Figure 44-3. Zero-Power-on Reset Cha racteristics
Table 44-8. Zero-Power-on Reset Characteristics
Symbol Parameter Conditions Min Typ Max Unit
VT+ Threshold Voltage Rising At startup 1.45 1.53 1.59 V
VT- Threshold Voltage Fa ll ing – 1.35 1.45 1.55 V
tRST Reset Period – 100 340 580 µs
VT-
VT+
VDDIO
Reset
1149
SAM4S Series [DATASHEET]
Atmel-11100K-ATARM-SAM4S-Datasheet_09-Jun-15
44.4 Power Consumption
Power consumption of the device according to the different low-power mode capabilities (Backup, Wait,
Sleep) and Active mode
Power consumption on power supply in different modes: Backup, Wait, Sleep and Active
Power consumption by peripheral: ca lculated as the dif ference in current measurement after having enabled
then disabled the corresponding clock
All power consumption values are based on characterization. Power consumption values are not covered by
test limits in production.
44.4.1 Backup Mode Current Consumption
The Backup mode configuration and measurements are defined as follows.
Figure 44-4. Measurement Setup
44.4.1.1 Configuration A: Embedded Slow Clock RC Oscillator Enabled
Supply Monitor on VDDIO is disabled
RTC is running
RTT is enabled on 1Hz mode
BOD disabled
One WKUPx enabled
Current measurement on AMP1 (see Figure 44-4)
44.4.1.2 Configuration B: 32.768 kHz Crystal Oscillator Enabled
Supply Monitor on VDDIO is disabled
RTC is running
RTT is enabled on 1Hz mode
BOD disabled
One WKUPx enabled
Current measurement on AMP1 (see Figure 44-4)
VDDIO
VDDOUT
VDDCORE
VDDIN
Voltage
Regulator
VDDPLL
3.3V
AMP1
SAM4S Series [DATASHEET]
Atmel-11100K-ATARM-SAM4S-Datasheet_09-Jun-15
1150
Table 44-9 . Typical Power Consumption for Backup Mode (SAM4S4/S2 rev A)
Conditions
@ 25°C @ 85°C @ 105°C
Unit
(AMP1)
Configuration A (AMP1)
Configuration B (AMP1)
Configuration A (AMP1)
Configuration A
VDDIO = 3.6V
VDDIO = 3.3V
VDDIO = 3.0V
VDDIO = 2.5V
VDDIO = 1.8V
1.9
1.7
1.5
1.3
0.9
1.8
1.6
1.4
1.2
0.8
6.8
6.2
5.7
5.1
4.4
14.6
13.4
12.5
11.3
9.9
µA
Table 44-10. Typical Power Consumption for Backup Mode (SAM4SD32/SD16/SA16 rev A)
Conditions
@ 25°C @ 85°C @ 105°C
Unit
(AMP1)
Configuration A (AMP1)
Configuration B (AMP1)
Configuration A (AMP1)
Configuration A
VDDIO = 3.6V
VDDIO = 3.3V
VDDIO = 3.0V
VDDIO = 2.5V
VDDIO = 1.8V
2.1
1.8
1.7
1.3
0.9
2.0
1.8
1.6
1.3
0.9
13.9
–
–
–
–
22.5
–
–
–
–
µA
Table 44-11. Typical Power Consumption for Backup Mode (SAM4S16/S8 rev A)
Conditions
@ 25°C @ 85°C @ 105°C
Unit
(AMP1)
Configuration A (AMP1)
Configuration B (AMP1)
Configuration A (AMP1)
Configuration A
VDDIO = 3.6V
VDDIO = 3.3V
VDDIO = 3.0V
VDDIO = 2.5V
VDDIO = 1.8V
2.7
2.0
1.8
1.5
1
2.5
1.8
1.7
1.4
0.9
12.1
–
–
–
–
20.1
–
–
–
–
µA
1151
SAM4S Series [DATASHEET]
Atmel-11100K-ATARM-SAM4S-Datasheet_09-Jun-15
44.4.2 Sleep and Wait Mode Current Consumption
The Wait mode and Sleep mode configuration and measurements are defined below.
Figure 44-5. Measurement Setup for Sleep Mode
44.4.2.1 Sleep Mode
Core clock off
VDDIO = VDDIN = 3.3V
Master clock (MCK) running at various frequencies with PLLA or the fast RC oscillator
Fast start-up through pins WKUP0–15
Current measurement as shown in Figure 44-5
All peripheral clocks deactivated
TA = 25°C
Figure 44-6.
SAM4S4/2
Current Consump t ion in Sleep Mode (AMP1) vs Master Clock Ranges (refer to Table 44-1 2 )
VDDIO
VDDOUT
VDDCORE
VDDIN
Voltage
Regulator
VDDPLL
3.3V
AMP1
AMP2
0.000
2.000
4.000
6.000
8.000
0 102030405060708090100110120
IDDCORE
MHz
Sleep Mode SAM4S4/S2
SAM4S Series [DATASHEET]
Atmel-11100K-ATARM-SAM4S-Datasheet_09-Jun-15
1152
Table 44-12. SAM4S4/S2 Typical Sleep Mode Current Consum ption vs Master Clock (MCK) Variation with PLLA
Core Clock/MCK (MHz)
Typical Value @ 25°C
Unit
VDDCORE Consumption
(AMP1) Total Consumption
(AMP2)
120 5.1 6.9
mA
100 4.3 5.8
84 3.7 5.0
64 2.8 3.9
32 1.5 2.2
24 1.2 1.8
Table 44-13. SAM4S4/2 Typical Sleep Mode Current Consumption vs Master Clock (MCK) Variation with Fast RC
Core Clock/MCK (MHz)
Typical Value @ 25°C
Unit
VDDCORE Consumption
(AMP1) Total Consumption
(AMP2)
12 0.6 0.8
mA
80.40.7
40.20.5
2 0.17 0.41
1 0.13 0.34
0.5 0.11 0.35
1153
SAM4S Series [DATASHEET]
Atmel-11100K-ATARM-SAM4S-Datasheet_09-Jun-15
Figure 44-7.
SAM4S16/S8
Current Consumpt ion in Sleep Mode (AMP1) vs Master Clock Ranges (refer to Table 44-14)
0.000
2.000
4.000
6.000
8.000
10.000
12.000
0 102030405060708090100110120
IDDCORE
MHz
Sleep Mode SAM4S16/S8
Table 44-14. SAM4S16/S8 Typical Sleep Mode Current Consumption vs Master Clock (MCK) Variation with PLLA
Core Clock/MCK (MHz)
Typical Value @ 25°C
Unit
VDDCORE Consumption
(AMP1) Total Consumption
(AMP2)
120 8.1 9.6
mA
100 7.1 8.1
84 6.0 6.8
64 4.7 5.2
48 3.5 3.9
32 2.4 2.6
24 1.8 2.0
SAM4S Series [DATASHEET]
Atmel-11100K-ATARM-SAM4S-Datasheet_09-Jun-15
1154
Figure 44-8.
SAM4SD32/SD16/SA16 Typical
Current Consumption in Sleep Mode (AMP1) vs Master Clock Ranges (refer to
Table 44-16)
Table 44-15. SAM4S16/S8 Typical Sleep Mode Current Consumption vs Master Clock (MCK) Variat io n with Fast RC
Core Clock/MCK (MHz)
Typical Value @ 25°C
Unit
VDDCORE Consumption
(AMP1) Total Consumption
(AMP2)
12 1.1 1.5
mA
80.71.2
40.40.7
20.30.7
10.20.5
0.5 0.2 0.4
0.00
1.00
2.00
3.00
4.00
5.00
6.00
7.00
8.00
9.00
0 20406080100120140
IDDCORE
MHz
Sleep Mode SAM4SD32/SD16/SA16
1155
SAM4S Series [DATASHEET]
Atmel-11100K-ATARM-SAM4S-Datasheet_09-Jun-15
44.4.2.2 Wait Mode
Figure 44-9. Measurement Setup for Wait Mode
VDDIO = VDDIN = 3.6V
Core clock and master clock stopped
Current measurement as shown in the above figure
BOD disabled
All peripheral clocks deactivated
Table 44-18 gives current consumption in typical conditions.
Table 44-1 6. SAM4SD32/SD16/SA16 Typical Sleep Mode Current Consumption vs Master Clock (MCK) Variation with PL LA
Core Clock/MCK (MHz)
Typical Value @ 25°C
Unit
VDDCORE Consumption
(AMP1) Total Consumption
(AMP2)
120 8.4 10.6
mA
100 7.1 8.9
84 6.0 7.5
64 4.6 5.8
48 3.5 4.4
32 2.4 3.1
24 1.8 2.4
Table 44-17. SAM4SD32/SD16/SA16 Typical Sleep Mode Current Consumption vs Master Clock (MCK) Variation with Fast RC
Core Clock/MCK (MHz)
Typical Value @ 25°C
Unit
VDDCORE Consumption
(AMP1) Total Consumption
(AMP2)
12 1.1 1.8
mA
80.81.2
40.40.7
20.30.7
10.20.5
0.5 0.2 0.5
VDDIO
VDDOUT
VDDCORE
VDDIN
Voltage
Regulator
VDDPLL
3.6V
AMP1
AMP2
SAM4S Series [DATASHEET]
Atmel-11100K-ATARM-SAM4S-Datasheet_09-Jun-15
1156
Table 44-18. SAM4S4/S2 Typical Curren t Consumption in Wait Mode
Conditions
@ 25°C @ 85°C @ 105°C
Unit
VDDOUT
Consumption
(AMP1)
Total
Consumption
(AMP2)
Total
Consumption
(AMP2)
Total
Consumption
(AMP2
See Figure 44-9 on page 1155
There is no activity on the I/ Os of the
device. With the Flash in standby mode 14.9 28.4 211 436
µA
See Figure 44-9 on page 1155
There is no activity on the I/ Os of the
device. With the Flash in deep power
down mode
14.9 24.1 205 432
Table 44-19. SAM4S16/S8 Typical Current Consumption in Wait Mode
Conditions
@ 25°C @ 85°C @ 105°C
Unit
VDDOUT
Consumption
(AMP1)
Total
Consumption
(AMP2)
Total
Consumption
(AMP2)
Total
Consumption
(AMP2
See Figure 44-9 on page 1155
There is no activity on the I/ Os of the
device. With the Flash in standby mode 20.5 32.7 344 654
µA
See Figure 44-9 on page 1155
There is no activity on the I/ Os of the
device. With the Flash in deep power
down mode
20.5 27.8 438 589
Table 44-20. SAM4SD32/SD16/SA16 Typical Current Consumption in Wait Mode
Conditions
@ 25°C @ 85°C @ 105°C
Unit
VDDOUT
Consumption
(AMP1)
Total
Consumption
(AMP2)
Total
Consumption
(AMP2
Total
Consumption
(AMP2
See Figure 44-9 on page 1155
There is no activity on the I/ Os of the
device. With the Flash in standby mode – 42.1 633 1105
µA
See Figure 44-9 on page 1155
There is no activity on the I/ Os of the
device. With the Flash in deep power
down mode
– 35.3 608 1085
1157
SAM4S Series [DATASHEET]
Atmel-11100K-ATARM-SAM4S-Datasheet_09-Jun-15
44.4.3 Active Mode Power Consumption
The active mode configuration and measurements are defined as follows:
VDDIO = VDDIN = 3.3V
VDDCORE = 1.2V (internal voltage regulator used)
TA = 25°C
Application running from Flash memory with128-bit access mode
All peripheral clocks ar e de a ctiva te d .
Master Clock (MCK) running at various frequencies with PLLA or the fast RC oscillator.
Current measurement on AMP1 (VDDCORE) and total current on AMP2
Figure 44-10. Active Mode Measurement Setup
The following tables give Active mode current consumption in typical conditions.
VDDCORE at 1.2V
TA = 25°C
VDDIO
VDDOUT
VDDCORE
VDDIN
Voltage
Regulator
VDDPLL
3.3V
AMP1
AMP2
SAM4S Series [DATASHEET]
Atmel-11100K-ATARM-SAM4S-Datasheet_09-Jun-15
1158
44.4.3.1 SAM4S4/2 Active Power Consumption
Note: 1. Flash Wait State (FWS) in EEFC_FMR adjusted versus core frequency
44.4.3.2 SAM4S16/S8 Active Power Consumption
Note: 1. Flash Wait State (FWS) in EEFC_FMR adjusted versus core frequency
Table 44-21. SAM4S4/2 Active Power Consumption with VDDCORE @ 1.2V Running from Flash Memory or SRAM
Core Clock (MHz)
CoreMark
Unit
128-bit Flash access (1) 64-bit Flash access(1) SRAM
AMP1 AMP2 AMP1 AMP2 AMP2
120 17.7 21.2 12.8 16.4 16.2
mA
100 16.1 19.4 11.6 14.8 13.5
84 13.6 16.8 9.9 13.1 12.0
64 11.6 14.6 8.5 10.9 9.0
32 7.3 9.8 5.8 8.0 5.2
24 6.0 8.3 5.2 7.4 3.9
12 3.6 5.2 2.7 4.1 2.2
8 2.4 4.6 2.2 3.5 1.5
4 1.5 2.3 1.2 2.8 1.0
2 0.7 1.8 0.6 1.9 0.8
1 0.4 1.1 0.3 1.2 0.7
0.5 0.2 0.9 0.2 0.9 0.6
Table 44-2 2. SAM4S16/S8 Active Power Consumption with VDDCORE @ 1.2V Running from Flash Memory or SRAM
Core Clock (MHz)
CoreMark
Unit
128-bit Flash access(1) 64-bit Flash access(1) SRAM
AMP1 AMP2 AMP1 AMP2 AMP2
120 24.9 28.8 18 21.4 19.6
mA
100 21.9 25.4 16.3 19.5 16.5
84 18.5 21.4 13.8 16.6 13.9
64 15.0 17.6 11.4 13.9 10.7
48 11.9 14.3 9.6 11.8 8
32 8.1 9.9 7.4 9.3 5.4
24 6.0 7.7 5.8 7.5 4.1
12 3.4 6.1 3.2 6.0 2
8 2.3 4.5 2.2 4.5 1.2
4 1.2 2.6 1.2 2.9 1.2
2 0.7 1.9 0.7 2.0 0.7
10.41.30.41.6–
0.5 0.3 1.1 0.3 1.3 –
1159
SAM4S Series [DATASHEET]
Atmel-11100K-ATARM-SAM4S-Datasheet_09-Jun-15
Figure 44-11.
SAM4S16/S8
Current Consumption in Active Mode (AMP1) versus Master Clock Ranges
0
5
10
15
20
25
30
050100150
IDDCORE (mA)
Frequency MHz
128-bit Flash access
64-bit Flash access(1)
SRAM
SAM4S Series [DATASHEET]
Atmel-11100K-ATARM-SAM4S-Datasheet_09-Jun-15
1160
44.4.3.3 SAM4SD32/SD16/SA16 Active Power Consumption
Note: 1. Flash Wait State (FWS) in EEFC_FMR adjusted versus core frequency
Figure 44-12.
SAM4SD32/SD16/SA16
Current Cons umption in Active Mode (AMP1) versus Master Clock Ranges
Table 44-2 3. SAM4SD32/SA16/SD16 Active Power Consumption with VDDCORE @ 1.2V run ning from Flash Memory
(IDDCORE- AMP1) or SRAM
Core Clock (MHz)
CoreMark
Unit
Cache Enable (CE) Cache Disable (CD)
SRAM
128-bit Flash
access(1) 64-bit Flash
access(1) 128-bit Flash
access(1) 64-bit Flash
access(1)
120 20.7 20.7 24.8 18.1 19.9
mA
100 17.5 17.4 21.6 16.5 16.8
84 14.7 14.7 18.3 13.9 14.2
64 11.3 11.3 14.4 11.5 10.9
48 8.5 8.5 11.3 9.4 8.3
32 5.7 5.7 8.0 7.1 5.6
24 4.3 4.3 6.3 5.9 4.2
12 2.5 2.5 3.5 3.3 1.9
8 1.7 1.7 2.4 2.3 1.7
4 0.9 0.9 1.2 1.2 0.7
2 0.5 0.5 0.7 0.7 0.5
1 0.4 0.4 0.5 0.5 0.4
0.5 0.3 0.3 0.3 0.3 0.3
0.0
5.0
10.0
15.0
20.0
25.0
0 2040 6080100120
Flash128 (CD) mA
Flash64 (CE) mA
Flash128 (CE) mA
Flash64 (CD ) mA
SR AM mA
1161
SAM4S Series [DATASHEET]
Atmel-11100K-ATARM-SAM4S-Datasheet_09-Jun-15
Note: 1. Flash Wait State (FWS) in EEFC_FMR adjusted versus core frequency
Table 44-2 4. SAM4SD32/SA16/SD16 Typical Active Power Consumption with VDDCORE@ 1.2V running from Flash Memory
(AMP2) or SRAM
Core Clock (MHz)
CoreMark
Unit
Cache Enable (CE) Cache Disable (CD)
SRAM
128-bit Flash
access(1) 64-bit Flash
access(1) 128-bit Flash
access(1) 64-bit Flash
access(1)
120 23.2 23.2 27.8 20.9 22.1
mA
100 19.6 19.6 25.3 19.0 18.5
84 16.6 16.5 21.6 16.2 15.7
64 12.8 12.8 18.0 13.7 12.1
48 9.7 9.7 14.9 11.9 9.2
32 6.7 6.7 11.2 9.5 6.3
24 5.2 5.2 9.5 8.4 4.9
12 2.5 2.5 5.4 4.6 2.4
8 1.8 1.8 4.5 3.9 1.7
4 1.1 1.1 2.8 2.8 1.0
2 0.7 0.7 2.0 2.0 0.7
1 0.5 0.5 1.2 1.2 0.5
0.5 0.4 0.4 0.8 0.8 0.4
SAM4S Series [DATASHEET]
Atmel-11100K-ATARM-SAM4S-Datasheet_09-Jun-15
1162
44.4.4 Peripheral Power Consumption in Active Mode
Table 44-25. Typical Power Consumption on VDDCORE (VDDIO = 3.3V, TA = 25°C)
Peripheral Consumption
VDDCORE 1.08V Consumption
VDDCORE 1.2V Consumption
VDDCORE 1.32V Unit
PIO Controller A (PIOA) 4.2 4.7 5.3
µA/MHz
PIO Controller B (PIOB) 1.2 1.4 1.5
PIO Controller C (PIOC) 2.6 3.0 3.2
UART 3.8 4.2 4.6
USART 5.6 6.2 7.0
PWM 10.2 11.5 12.5
TWI 4.0 4.4 5.0
SPI 4.2 4.7 5.1
Timer Counter (TCx) 4.2 4.7 5.2
ADC 2.9 3.3 3.6
DACC 2.7 3.1 3.4
ACC 0.4 0.5 0.6
HSMCI 5.5 6.1 6.8
CRCCU 0.2 0.3 0.3
SMC 1.9 2.1 2.3
SSC 4.9 5.4 6.2
UDP 4.7 5.2 5.8
1163
SAM4S Series [DATASHEET]
Atmel-11100K-ATARM-SAM4S-Datasheet_09-Jun-15
44.5 Oscillator Characteristics
44.5.1 32 kHz RC Oscillator Characteristics
44.5.2 4/8/12 MHz RC Oscillators Characteristics
Notes: 1. Frequency range can be configured in the Supply Controller registers
2. Not trimmed from factory
3. After trimming from factory
The 4/8/12 MHz Fast RC oscillator is calibrated in production. This calibration can be read through the Get CALIB bit com-
mand (refer to th e EEFC sect ion ) an d th e fre q ue n cy can be trimm e d by softw ar e th ro ug h the PM C.
Table 44-26. 32 kHz RC Oscillator Characteristics
Symbol Parameter Conditions Min Typ Max Unit
fOSC RC Oscillator Frequency 20 32 44 kHz
Frequency Supply Dependency -3 – 3 %/V
Frequency Temp erature Dependency Over temperature range (-40 to 105 °C) versus
TA 25°C -7 – 7 %
Duty Duty Cycle 45 50 55 %
tSTART Startup Time – – 100 µs
IDDON Current Consumption After startup time
Temp. range = -40 to 125 °C
Typical consumption at 2.2V supply and TA 25°C – 540 860 nA
Table 44-2 7. 4/8/12 MHz RC Oscillators Characteristics
Symbol Parameter Conditions Min Typ Max Unit
fOSC RC Oscillator Frequency Range (1) 412MHz
ACC44 MHz Total Accuracy -40°C < Temp < +105°C
4 MHz output selected (1)(2) ––±30 %
ACC88 MHz Total Accuracy -40°C < Temp < +105°C
8 MHz output selected (1)(3) ––±5 %
ACC12 12 MHz Total Accuracy -40°C < Temp < +105°C
12 MHz output selected (1)(3) ––±5 %
Frequency Deviation versus Trimming Code 8 MHz
12 MHz –47
64 – kHz/trimming code
Duty Duty Cycle 45 50 55 %
tSTART Startup Time – – 10 µs
IDDON Active Current Consumption(2) 4 MHz
8 MHz
12 MHz –50
65
82
75
95
118 µA
SAM4S Series [DATASHEET]
Atmel-11100K-ATARM-SAM4S-Datasheet_09-Jun-15
1164
44.5.3 32.768 kHz Crystal Oscillator Characteristics
Note: 1. RS is the series resistor.
Figure 44-13. 32.768 kHz Crystal Oscillator Schematic
CLEXT = 2 × (Ccrystal – Cpara – CPCB)
where:
CPCB is the capacitance of the printed circuit board (PCB) track layout from the crystal to the SAM4 pin.
44.5.4 32.768 kHz Crystal Characteristics
Table 44-2 8. 32.768 kHz Crystal Oscillator Characteristics
Symbol Parameter Conditions Min Typ Max Unit
fOSC Operating Frequency Normal mode with crystal – – 32.768 kHz
Duty Cycle 40 50 60 %
tSTART Startup Time
RS < 50 kΩ (1) Ccrystal = 12.5 pF
Ccrystal = 6 pF ––
900
300 ms
RS < 100 kΩ (1) Ccrystal = 12.5 pF
Ccrystal = 6 pF ––
1200
500
IDDON Current Consumption
RS < 50 kΩ (1) Ccrystal = 12.5 pF
Ccrystal = 6 pF –550
380 1150
980 nA
RS < 100 kΩ (1) Ccrystal = 12.5 pF
Ccrystal = 6 pF –820
530 1600
1350
PON Drive Level ––0.1µW
RfInternal Resistor Between XIN32 and XOUT32 – 10 – MΩ
CLEXT Maximum External Capacitor
on XIN32 and XOUT32 – – 20 pF
Ccrystal Allowed Crystal Capacitance Load From crystal specification 6 – 12.5 pF
Cpara Internal Parasitic Capacitance 0.6 0.7 0.8 pF
XIN32XOUT32
CLEXT CcrystalCLEXT
SAM4
Table 44-29. Crystal Characteristic s
Symbol Parameter Conditions Min Typ Max Unit
ESR Equival ent Series Resistor (RS) Crystal @ 32.768 kHz – 50 100 kΩ
CmMotional Capacitance Crystal @ 32.768 kHz 0.6 – 3 fF
CSHUNT Shunt Capacitance Crystal @ 32.768 kHz 0.6 – 2 pF
1165
SAM4S Series [DATASHEET]
Atmel-11100K-ATARM-SAM4S-Datasheet_09-Jun-15
44.5.5 32.768 kHz XIN32 Clock Input Characteristics in Bypass Mode
Note: 1. These characteristics apply only when the 32.768 kHz crystal oscillator is in Bypass mode (i.e., when
OSCBYPASS = 1 in SUPC_MR and XTALSEL = 1 in SUPC_CR).
Figure 44-14. XIN32 Clock Timing
Table 44-30. XIN32 Clock Electrical Characteristics (In Bypass Mode)
Symbol Parameter Conditions Min Max Unit
1/(tCPXIN32) XIN32 Clock Frequen cy (1) 44 kHz
tCPXIN32 XIN32 Clock Period (1) 22 µs
tCHXIN32 XIN32 Clock High Half-period (1) 11 µs
tCLXIN32 XIN32 Clock Low Half-period (1) 11 µs
tCLCH Rise Time 400 ns
tCHCL Fall Time 400 ns
CiXIN32 Input Capacitance 6 pF
RIN XIN32 Pull-down Resistor 3 5 MΩ
VXIN32_IL VXIN32 Input Low-level Voltage -0.3 0.3 × VDDIO V
VXIN32_IH VXIN32 Input High-level Voltage 0.7 × VDDIO VDDIO + 0.3 V
t
CPXIN32
t
CLXIN32
t
CHXIN32
t
CLCH
t
CHCL
V
XIN32_IL
V
XIN32_IH
SAM4S Series [DATASHEET]
Atmel-11100K-ATARM-SAM4S-Datasheet_09-Jun-15
1166
44.5.6 3 to 20 MHz Crystal Oscillator Characteristics
Figure 44-15. 3 to 20 MHz Crystal Oscillato r Schem atic
CLEXT = 2 × (Ccrystal – CLOAD – CPCB).
Where CPCB is the capacitance of the printed circuit board (PCB) track layout from the crystal to the SAM4 pin.
Table 44-31. 3 to 20 MHz Crystal Oscillator Characteristics
Symbol Parameter Conditions Min Typ Max Unit
fOSC Operating Frequency Normal mode with crystal 3 16 20 MHz
Duty Cycle 40 50 60 %
tSTART Startup Time
3 MHz, CSHUNT = 3 pF
8 MHz, CSHUNT = 7 pF
16 MHz, CSHUNT = 7 pF with Cm = 8 fF
16 MHz, CSHUNT = 7 pF with Cm = 1.6 fF
20 MHz, CSHUNT = 7 pF
––
14.5
4
1.4
2.5
1
ms
IDDON Current Consumption (on VDDIO)
3 MHz
8 MHz
16 MHz
20 MHz
–
230
300
390
450
350
400
470
560
µA
PON Drive Level 3 MHz
8 MHz
16 MHz, 20 MHz ––15
30
50 µW
RfInternal Resistor Between XIN and XOUT – 0.5 – MΩ
CLEXT Maximum External Capacitor
on XIN and XOUT – – 17 pF
Ccrystal Allowed Crystal Capacitance Load From crystal specification 12.5 – 17.5 pF
CLOAD Internal Equivalent Load Capacitance Integrated load capacitance
(XIN and XOUT in series) 7.5 9.5 10.5 pF
XIN XOUT
CLEXT
CLOAD
CLEXT Ccrystal
SAM4
R = 1K if crystal frequency is lower than 8 MHz
1167
SAM4S Series [DATASHEET]
Atmel-11100K-ATARM-SAM4S-Datasheet_09-Jun-15
44.5.7 3 to 20 MHz Crystal Characteristics
44.5.8 3 to 20 MHz XIN Clock Input Characteristics in Bypass Mode
Note: 1. These characteristics apply only when the 3–20 MHz crystal oscillator is in Bypass mode.
Figure 44-16. XIN Cloc k Timing
Table 44-3 2. 3 to 20 MHz Crystal Characteristics
Symbol Parameter Conditions Min Typ Max Unit
ESR Equivalent Series Resistor (Rs)
Fundamental @ 3 MHz
Fundamental @ 8 MHz
Fundamental @ 12 MHz
Fundamental @ 16 MHz
Fundamental @ 20 MHz
––
200
100
80
80
50
Ω
CmMotional Capacitance – – 8 fF
CSHUNT Shunt Capacitance – – 7 pF
Table 44-33. XIN Clo ck Electrical Characteristics (In Bypass Mode)
Symbol Parameter Conditions Min Typ Max Unit
1/(tCPXIN) XIN Clock Freque ncy (1) ––50MHz
tCPXIN XIN Clock Period (1) 20 – – ns
tCHXIN XIN Clock High Half-period (1) 8––ns
tCLXIN XIN Clock Low Half-period (1) 8––ns
tCLCH Rise Time (1) 2.2 – – ns
tCHCL Fall Time (1) 2.2 – – ns
VXIN_IL VXIN Input Low-level Voltage (1) -0.3 – [0.8V:0.3 × VDDIO]V
VXIN_IH VXIN Input Hi gh-level Voltage (1) [2.0V:0.7 × VDDIO]– V
DDIO + 0.3V V
Cpara(standby) Internal Parasitic Capacitance
During Standby (1) –5.56.3pF
Rpara(standby) Internal Parasitic Resistance
During Standby (1) – 300 – Ω
tCPXIN
tCLXIN
tCHXIN tCLCH tCHCL
VXIN_IL
VXIN_IH
SAM4S Series [DATASHEET]
Atmel-11100K-ATARM-SAM4S-Datasheet_09-Jun-15
1168
44.5.9 Crystal Oscillator Design Considerations Information
44.5.9.1 Choosing a Crystal
When choosing a crystal for the 32.768 kHz Slow Clock Oscillator or for the 3–20 MHz Oscillator, several
parameters must be taken into account. Important parameters of crystal and SAM4S specifications are as follows:
Load Capacitance
Ccrystal is the equivalent capacitor value the oscillator must “show” to the crystal in order to oscillate at the
target frequency. The crystal must be chosen according to the internal load capacitance (CLOAD) of the on-
chip oscillator. Any mismatch in the load capacitance will result in a frequency drift.
Drive Level
Crystal drive level ≥ Oscillator drive level. Having a crystal drive level number lower than the oscillator
specification may damage the crystal.
Equivalent Series Resistor (ESR)
Crystal ESR ≤ Oscillator ESR Max. Having a crystal with ESR value higher than the oscillator may cause the
oscillator to not start.
Shunt Capacitance
Max. crystal Shunt Capacitance ≤ Oscillator Shunt Capacitance (CSHUNT). Having a crystal with ESR value
higher than the oscillator may cause the oscillator to not start.
44.5.9.2 Printed Circuit Board (PCB)
SAM4S oscillators are low-power oscillators requiring particular attention when designing PCB systems.
1169
SAM4S Series [DATASHEET]
Atmel-11100K-ATARM-SAM4S-Datasheet_09-Jun-15
44.6 PLLA, PLLB Characteristics
Table 44-34. Supply Voltage Phase Lock Loop Characteristics
Symbol Parameter Conditions Min Typ Max Unit
VDDPLLR Supply Voltage Range 1.08 1.2 1.32 V
Table 44-35. PLLA and PLLB Cha racteristics
Symbol Parameter Conditions Min Typ Max Unit
fIN Input Frequency 3 – 32 MHz
fOUT Output Frequency 80 – 240 MHz
IPLL Current Consumption
Active mode @ 80 MHz @ 1.2V
Active mode @ 96 MHz @ 1.2V
Active mode @ 160 MHz @ 1.2V
Active mode @ 240 MHz @ 1.2V
–
0.94
1.2
2.1
3.34
1.2
1.5
2.5
4
mA
tsSettling Time – 60 150 µs
SAM4S Series [DATASHEET]
Atmel-11100K-ATARM-SAM4S-Datasheet_09-Jun-15
1170
44.7 USB Transceiver Characteristics
44.7.1 Typical Connection
For details on a typical connection, refer to Section 40. “USB Device Port (UDP)”.
44.7.2 USB Electrical Characteristics
44.7.3 Switching Characteristics
Table 44-3 6. USB Electrical Characteristics
Symbol Parameter Conditions Min Typ Max Unit
Input Levels
VIL Low Level ––0.8V
VIH High Level 2.0 – – V
VDI Differential Input Sens itivity |(D+) - (D-)| 0.2 – – V
VDICR Differential Input Comm o n Mo de
Range 0.8–2.5V
CiTra nsceiver Capacitance Capacitance to ground on each line – – 9.18 pF
Ilkg Hi-Z State Data Line Leakage 0V < VI < 3.3V -10 – +10 µA
REXT Recommended External USB Series
Resistor In series with each USB pin with ± 5 % – 27 – Ω
Output Levels
VOL Low Level Output Measured with RL of 1.425 kΩ tied to 3.6V 0.0 – 0.3 V
VOH High Level Output Measured with RL of 14.25 kΩ tied to GND 2.8 – 3.6 V
VCRS Output Signal Crossover Voltage Measurement conditions described in Figure
44-17 “USB Data Signal Rise and Fall Times” 1.3–2.0V
Consumption
IVDDIO Current Consumption Transceiver enabled in input mode
DDP = 1 and DDM = 0 – 105 200 µA
IVDDCORE Current Consumption – 80 150 µA
Pull-up Resistor
RPUI Bus Pull-up Resistor on Upstream Port
(idle bus) 0.900 – 1.575 kΩ
RPUA Bus Pull-up Resistor on Upstream Port
(upstream port receiving) 1.425 – 3.090 kΩ
Table 44-37. In Full Speed
Symbol Parameter Conditions Min Typ Max Unit
trTransition Rise Time CLOAD = 50 pF 4 – 20 ns
tfTransition Fall Time CLOAD = 50 pF 4 – 20 ns
trfm Rise/Fall T ime Matching 90 – 111.11 %
1171
SAM4S Series [DATASHEET]
Atmel-11100K-ATARM-SAM4S-Datasheet_09-Jun-15
Figure 44-17. USB Data Signal Rise and Fa ll Times
10% 10%
90%
VCRS
trtf
Differential
Data Lines
Rise T ime Fall Time
fOSC = 6 MHz/750 kHz REXT = 27 
CLOAD
Buffer
(b)
(a)
SAM4S Series [DATASHEET]
Atmel-11100K-ATARM-SAM4S-Datasheet_09-Jun-15
1172
44.8 12-bit ADC Characteristics
Electrical data are in accordance with the following standard conditions unless otherwise specified:
Operating temperature range from -40°C to + 105°C
Min and max data are defined as three times the standard deviation of the manufacturing process
44.8.1 ADC Power Supply
Notes: 1. See Section “Low Voltage Supply”.
2. In Sleep mode the ADC core, sample and hold, and internal reference operational amplifier are off.
3. In Fast W ake-up mode, only the ADC core is off.
44.8.1.1 ADC Bias Current
All current consumption is performed when the field IBCTL in the ADC Analog Control Register (ADC_ACR) is set
to 01.
IBCTL controls the ADC biasing current, with the nominal setting IBCTL = 01.
IBCTL = 00 is the required value for a sampling frequency below 500 kHz, and IBCTL = 01 for a sampling
frequency between 500 kHz and 1 MHz.
Table 44-38. Analog Power Supply Characteristics
Symbol Parameter Conditions Min Typ Max Unit
VDDIN Supply Voltage Range Full operational 2.4 – 3.6 V
(1) 2–2.4
IVDDIN Analog Current Consumption ADC Sleep Mode(2)
ADC Fast Wake-up Mode(3)
ADC Normal Mode –2
2.4
4.3
4
3.5
6
µA
mA
mA
IVDDcore Digital Current Consumption ADC Sleep Mode (all off)(2)
ADC Normal Mode ––
0.2 0.1
0.4 µA
mA
Table 44-39. ADC Bias Current Adjustment
IBCTL = 00 IBCTL = 01 IBCTL = 10 IB CTL = 11
Typ-22% Typ Reserved Reserved
1173
SAM4S Series [DATASHEET]
Atmel-11100K-ATARM-SAM4S-Datasheet_09-Jun-15
44.8.2 External Reference Voltage
VADVREF is an external reference voltage applied on the pin ADVREF. The quality of the reference voltage VADVREF
is critical to the performance of the ADC. A DC variation of the re ference voltage VADVREF is converted to a gain
error by the ADC. The noise generated by VADVREF is converted by the ADC to count noise.
Notes: 1. See Section “Low Voltage Supply”.
2. Over a bandwidth from 20 Hz to 20 MHz.
3. DIFF is Differential mode.
4. SE is Single-ended mode.
5. When the ADC is in Sleep mode, the ADVREF impedance has a minimum of 10 MΩ.
44.8.3 ADC Timings
Notes: 1. If ADC_MR.TRACKTIM is programmed with a val ue < 15, then the min. value is applied by default.
2. Refer to Figure 44-21 “Simplified Acquisition Path” for the max. tracking time computation.
3. Sampling frequency fs=1/tCONV in FREERUN mode. Oherwise, fs is defined by the trigger ti ming.
If TRACKTIM >14: tCONV = tHOLD +(TRACKTIM+1) x tCP_ADC with hold time tHOLD=5 tCP_ADC.
Table 44-40. ADVREF Electrical Characteristics
Symbol Parameter Conditions Min Typ Max Unit
VADVREF ADVREF Voltage Range Full operational 2.4 – 3.6 V
(1) 2–2.4
VnInput Voltage Noise(2)
Gain = 0.5, DIFF(3) mode – – 1100
µVrms
Gain = 1, SE(4) and DIFF(3) – – 550
Gain = 2, SE(4) and DIFF(3) – – 274
Gain = 4, SE(4) mode – – 137
RADVREF ADVREF Input DC Impedance ADC reference resistor bridge(5) 6810kΩ
Table 44-4 1. ADC Timing Characteristics
Symbol Parameter Conditions Min Typ Max Unit
fADC Clock Frequency 1 20 22 MHz
tCP_ADC Clock Period 45 50 1000 ns
fSSampling Frequency 0.05 1 1.1 MHz
tSTART ADC Startup time Sleep mode to Normal mode
Fast Wake-up mode to Normal mode 20
430
840
12 µs
tTRACKTIM Tracking T ime Refer to notes 1 and 2. 15(1) ––
(2) tCP_ADC
tCONV Conversion Time (3) Number of ADC clock pulses to
perform a conversion.
TRACKTIM < 15 –20–t
CP_ADC
tCAL Calibration time Calibration time given for one channel
and one gain/one offset. –306–t
CP_ADC
SAM4S Series [DATASHEET]
Atmel-11100K-ATARM-SAM4S-Datasheet_09-Jun-15
1174
44.8.4 ADC Transfer Function
The first operation of the ADC is a samplin g function relative to a common mode voltage. The common mode
voltage (VCM) is equal to VADVREF/2 when the bits OFFx = 1, in Differential and in Single-ended mod e. When the
bits OFFx = 0, sampling is done versus VADVREF/4 for gain = 2, and VADVREF/8 for gain = 4, in Single-ended mode
only.
The code in ADC_CDRx is a 12-bit positive integer.
44.8.4.1 Differential Mode
A differential input voltage VI = VI+ - VI- can be applied between two selected differential pins, e.g., AD0 and AD1.
The ideal code Ci is calculated by using the following formula and rounding the result to the nearest positive
integer.
Table 44-42 is a computation example for the above formula , where VADVREF = 3V.
44.8.4.2 Single-ended Mode
A single input voltage VI can be applied to selected pins, e.g., AD0 or AD1. The ideal code Ci is calculated by using
the following formula and rounding the result to the nearest positive integer.
The single-ended ideal code conversion formula for OFFx = 1 is:
Table 44-43 is a computation example for the above formula , where VADVREF = 3V.
The single-ended ideal code conversion formula for OFFx = 0 is:
Table 44-42. Input Voltage Values in Differential Mode
Ci Gain = 0.5 Gain = 1 Gain = 2
0 -3 -1.5 -0.75
2047 0 0 0
4095 3 1.5 0.75
Ci 4096
VADVREF
----------------------- VI
×Gain 2047+×=
Table 44-43. Input Voltage Values in Single-ended Mode, OFFx = 1
Ci Gain = 1 Gai n = 2 Gain = 4
0 0 0.75 1.125
2047 1.5 1.5 1.5
4095 3 2.25 1.875
Ci 4096
VADVREF
----------------------- VIVADVREF
2
-----------------------
–


×Gain 2047+×=
Ci VIGain 4096
VADVREF
----------------------- 1–××=
1175
SAM4S Series [DATASHEET]
Atmel-11100K-ATARM-SAM4S-Datasheet_09-Jun-15
Table 44-44 is a computation example for the above formula , where VADVREF = 3V.
44.8.4.3 Example of LSB Computation
The LSB is relative to the analog scale VADVREF.
The term LSB expresses the quantization step in volts, also used for one ADC code variation.
Single-ended (SE) (ex: VADVREF = 3.0V)
Gain = 1, LSB = (3.0V / 4096) = 732 µV
Gain = 2, LSB = (1.5V / 4096) = 366 µV
Gain = 4, LSB = (750 mV / 4096) = 183 µV
Differential (DIFF) (ex: VADVREF = 3.0V)
Gain = 0.5, LSB = (6.0V / 4096) = 1465 µV
Gain = 1, LSB = (3.0V / 4096) = 732 µV
Gain = 2, LSB = (1.5V / 4096) = 366 µV
44.8.5 ADC Electrical Characteristics
The gain error depends on the gain value and the OFFx bit. The data are given with and without autocorrection at
TA 27°C. The data include the ADC performances as the PGA and ADC core cannot be separated. The
temperature and voltage dependency are given as separate parameters.
44.8.5.1 Gain and Offset Errors
For:
a given gain erro r: EG (%)
a given ideal code (Ci)
a given offset error: EO (LSB)
the actual code (Ca) is calculated using the following formula:
Table 44-44. Input Voltage Values in Single-ended Mode, OFFx = 0
Ci Gain = 1 Gai n = 2 Gain = 4
0000
2047 1.5 0.75 0.375
4095 3 1.5 0.75
Table 44-45. Voltage an d Temperature Dependen cies
Symbol Parameter Conditions Min Typ Max Unit
α
GGain Temperature dependency -40°C to 105°C – – 5 ppm/°C
α
GV Gain Supply dependency VDDIN – – 0.025 %/V
α
OOffset Temperature dependency -40°C to 105°C – – 5 ppm/°C
α
OV Offset Supply dependency VDDIN – – 0.025 %/V
Ca 1EG
100
---------
+


Ci 2047–()×2047 EO
++=
SAM4S Series [DATASHEET]
Atmel-11100K-ATARM-SAM4S-Datasheet_09-Jun-15
1176
Differential Mode
In differential mode, the offset is defined when the differential input voltage is zero.
Figure 44-18. Gain and Offset Errors in Differential Mode
where:
FSe = (FSe+) - (FSe-) is for full-scale error, unit is LSB code
Offset error EO is the offset error measured for VI = 0V
Gain error EG = 100 × FSe / 4096, unit in %
The error va lu es in Table 44-46 and Table 44-47 include the sample and hold error as well as the PGA gain error.
Table 44-46. Differential Gain Error EG
Gain Mode 0.5 1 2
Auto Correction No Yes No Yes No Yes
Aver age Gain Error (%) -0.107 0.005 0.444 0.112 0.713 0.005
Standard Deviation (%) 0.410 0.210 0.405 0.229 0.400 0.317
Gain Min Value (%) -1.338 -0.625 -0.771 -0.576 -0.488 -0.947
Gain Max Value (%) 1.123 0.635 1.660 0.801 1.914 0.957
Table 44-47. Differential Output Offset Error EO
Gain 0.5 1 2
Aver age Offset Error (LSB) -1.2 -1.2 -0.6
Standard Deviation (LSB) 0.3 0.4 0.4
Offset Min value (LSB) -2.1 -2.4 -1.8
Offset Max value (LSB) -0.3 0 0.6
V
I
Differential
4095
ADVREF/2
-ADVREF/2 0
0
ADC codes
FSe-
E
O
= Offset error
2047
FSe+
1177
SAM4S Series [DATASHEET]
Atmel-11100K-ATARM-SAM4S-Datasheet_09-Jun-15
Single-ended Mode
Figure 44-19 illustrates the ADC output code relative to an input voltage VI between 0V (Ground) and VADVREF. The
ADC is configured in Single-ended mode by connecting internally the negative differential input to VADVREF/2. As
the ADC continues to work internally in Differential mode , the offset is measured at VADVREF/2.
Figure 44-19. Gain and Offset Errors in Single-ended Mode
where:
FSe = (FSe+) - (FSe-) is for full-scale error, unit is LSB code
Offset error EO is the offset error measured for VI = 0V
Gain error EG = 100 × FSe / 4096, unit in %
The error value s in Table 44-48 and Table 44-49 include the sample and hold error as well as the PGA gain error.
VI Single-ended
4095
ADVREF/2 ADVREF
0
0
ADC codes
FSe-
EO = Offset error
2047
FSe+
Table 44-48. Single-ended Gain Error
Offset Mode OFFx = 0 OFFx = 0 OFFx = 1 OFFx = 0 OF Fx = 1
Gain Mode 1 2 2 4 4
AutoCorrection No Yes No Yes No Yes No Yes No Yes
Aver age Gain Error (%) 0.449 0.078 0.771 -0.010 0.781 0.117 1.069 -0.029 1.064 0.151
Standard Deviation (%) 0.420 0.200 0.430 0.313 0.425 0.327 0.420 0.415 0.415 0.371
Min Value (%) -0.811 -0.522 -0.518 -0.947 -0.493 -0.864 -0.190 -1.274 -0.181 -0.962
Max Value (%) 1.709 0.679 2.061 0.928 2.056 1.099 2.329 1.216 2.310 1.265
Table 44-4 9. Single-ended Output Offset Error
Offset Mode OFFx = 0 OFFx = 0 OFFx = 1 OFFx = 0 OFFx = 1
Gain 1 2 2 4 4
Aver age Offset Error (LSB) -5.7 -7.7 -10.3 -7.3 -18.7
Standard Deviation (LSB) 1.8 3.9 3.4 6 7
Min Value (LSB) -11.1 -19.4 -20.5 -25.3 -39.7
Max Value (LSB) -0.3 4 -0.1 10.7 2.3
SAM4S Series [DATASHEET]
Atmel-11100K-ATARM-SAM4S-Datasheet_09-Jun-15
1178
44.8.5.2 ADC Electrical Performances
Single-ended Static Performances
Single-ended Dynamic Performances
Differential Static Performances
Differential Dynamic Performances
Table 44-50. Single-ended Static Electrical Characteristics
Symbol Parameter Conditions Min Typ Max Unit
INL ADC Integral Non-linearity -2 ± 1 2 LSB
DNL ADC Differential Non-linearity -1 ±0.5 1 LSB
Table 44-51. Single-end ed Dynamic Electrical Characteristics
Symbol Parameter Conditions Min Typ Max Unit
SNR Signal to Noise Ratio ADC Clock (fADC) = 20 MHz,
fS = 1 MHz,
fIN = 127 kHz,
Frequency band = [1 kHz–500 kHz]
Nyquist conditions fulfilled
56 64 72 dB
THD Total Harmonic Distortion 66 74 84 dB
SINAD Signal to Noise and Distortion 55 62 71 dB
ENOB Effective Number of Bits 9 10.5 12 bits
Table 44-52. Differential Static Electrical Characteristic s
Symbol Parameter Conditions Min Typ Max Unit
INL Integral Non-linearity -2 ±1 2 LSB
DNL Differential Non-linearity -1 ±0.5 1 LSB
Table 44-53. Differential Dynamic Electrical Characteristics
Symbol Parameter Conditions Min Typ Max Unit
SNR Signal to Noise Ratio ADC Clock (fADC) = 20 MHz,
fS = 1 MHz,
fIN = 127 kHz,
Frequency band = [1 kHz–500 kHz]
Nyquist conditions fulfilled
60 70 74 dB
THD Total Harmonic Distortion 72 80 84 dB
SINAD Signal to Noise and Distortion 60 68 73 dB
ENOB Effective Number of Bits 9.5 11 12 bits
1179
SAM4S Series [DATASHEET]
Atmel-11100K-ATARM-SAM4S-Datasheet_09-Jun-15
10-bit ADC Mode
In 10-bit mode, the ADC produces 12-bit ou tput but th e outp ut data in the register ADC_CDRx is shifted two bits to
the right, removing the two LSBs of the 12-bit ADC.
The gain and offset have the same values as for 12-bit mode, with digital full-scale output code range reduced to
1024 (vs 4096).
The INL and DNL have the same values as for 12-bit mode.
The dynamic performances are the 12-bit mode values, reduced by 12 dB.
Low Voltage Supply
The ADC performs in 10-bit mode or in 12-bit mode. Working at low voltage (VDDIN or/and VADVREF) be tween 2 an d
2.4V is subject to the following restrictions:
The field IBCTL must be 00 to reduce the bi asing of th e ADC unde r low volt age. See Se ction 44.8.1.1 “ADC
Bias Current”.
In 10-bit mode, the ADC clock should not exceed 5 MHz (max signal bandwidth is 250 kHz).
In 12-bit mode, the ADC clock should not exceed 2 MHz (max signal bandwidth is 100 kHz).
44.8.5.3 ADC Channel Input Impedance
Figure 44-20. Input Channel Model
where:
Zi is input impedance in single-ended or differential mode
Ci = 1 to 8 pF ±20% depending on the gain value and mode (SE or DIF F); temperature dependency is
negligible
RON is typical 2 kΩ and 8 kΩ max (worst case process an d high temperature)
RON is negligible regarding the value of Zi
The following formula is used to calculate input impedance:
where:
fS is the sampling freque n cy of the ADC ch anne l
Typ values are used to compute ADC input impedance Zi
Ci
Zi
RON
GND
Single-ended model
Ci
RON
Differential model
Zi
RON
Zi1
fSCi
×
----------------
=
SAM4S Series [DATASHEET]
Atmel-11100K-ATARM-SAM4S-Datasheet_09-Jun-15
1180
Track and Hold Time versus Source Output Impedance
Figure 44-21 shows a simplified acquisition path.
Figure 44-2 1. Simplified Acquisition Path
In 12-bit mode, during the tracking phase, the ADC needs to track the input signal during the tracking time shown
below:
tTRACK = 0.054 × ZSOURCE + 205
with tTRACK expressed in ns and ZSOURCE expressed in Ω.
The ADC already includes a tracking time of 15 tCP_ADC.
Two cases must be considered:
If the calculated tracking time (tTRACK) is lower than 15 tCP_ADC, then ADC_MR.TRACKTIM can be set to 0.
If the calculated tracking time (tTRACK) is higher than 15 tCP_ADC, then ADC_MR.TRACKTIM must be set to
the correct value.
Table 44-54. Input Capacitance Values
Gain Selection Single-ended Differential
0.5 – 2 pF
1 2 pF 4 pF
2 2 pF 8 pF
44 pF–
Table 44-55. Zi Input Impedance
fS (MHz) 1 0.5 0.25 0.125 0.0625 0.03125 0.015625 0.007813
Ci = 2 pF
Zi (MΩ)0.5 1 2 4 8 16 32 64
Ci = 4 pF
Zi (MΩ)0.25 0.5 1 2 4 8 16 32
Ci = 8 pF
Zi (MΩ)0.125 0.25 0.5 1 2 4 8 16
Sample & HoldMux.
ZSOURCE RON
Ci
ADC
Input
12-bit ADC
1181
SAM4S Series [DATASHEET]
Atmel-11100K-ATARM-SAM4S-Datasheet_09-Jun-15
44.9 12-bit DAC Characteristics
External voltage referen ce for DAC is VADVREF. See the ADC voltage reference characteristics in Table 44-40 on
page 1173.
Table 44-5 6. Analog Powe r Supply Characteristics
Symbol Parameter Conditions Min Typ Max Unit
VDDIN Analog Supply 2.4 3.0 3.6 V
IVDDIN Current
Consumption
Sleep Mode (Clock OFF) – 3 µA
Fast Wake Up (Standby Mode, clock ON) – 2 3 mA
Normal Mode with 1 output ON
(DACC_ACR.IBCTLDACCORE = 01, DACC_ACR.IBCTLCHx = 10) –4.35.6mA
Normal Mode with 2 outputs ON
(DACC_ACR.IBCTLDACCORE = 01, DACC_ACR.IBCTLCHx = 10) –56.5mA
Table 44-5 7. Channel Conversion Time and DAC Clock
Symbol Parameter Conditions Min Typ Max Unit
fDAC Clock Frequency 1 – 50 MHz
tCP_DAC Clock Period ––20ns
tREFRESH Refresh Time 8-bit Accuracy 24 – – us
tSTART Startup Time
From Sleep Mode to Normal Mode:
- Voltage reference OFF
- DAC core OFF 20 30 40
µs
From Fast Wake Up to Normal Mode:
- Voltage reference ON
- DAC core OFF 2.5 3.75 5
tCONV Conversion Time – – 25 tCP_DAC
Table 44-5 8. Static Performance Characteristics
Symbol Parameter Conditions Min Typ Max Unit
Resolution
DAC Clock (fDAC) = 5 MHz,
fS = 200 kHz,
ADC_ACR.IBCTL = 01
––12–bit
INL Integral Non-li nearity 2.4V < VDDIN < 2.7V -6 – +6 LSB
2.7V < VDDIN < 3.6V -2 ±1 +2
DNL Differential Non-linearity 2.4V < VDDIN < 2.7V -2.5 ±1 +2.5 LSB
2.7V < VDDIN < 3.6V
EOOffset Error – -32 ±8 32 LSB
EGGain Error – -32 ±2 32 LSB
SAM4S Series [DATASHEET]
Atmel-11100K-ATARM-SAM4S-Datasheet_09-Jun-15
1182
Table 44-59. Dynamic Performance Characteristics
Symbol Parameter Conditions Min Typ Max Unit
SNR Signal to Noise Ratio
DAC Clock (fDAC) = 50 MHz,
fS = 2 MHz,
fIN = 241 kHz,
ADC_ACR.IBCTL = 01,
FFT using 1024 points or more,
Frequency band = [10 kHz–1 MHz]
Nyquist conditions fulfilled
2.4V < VDDIN < 2.7V 50 62 70 dB
2.7V < VDDIN < 3.6V 62 70 74
THD Total Harmonic Distortion 2.4V < VDDIN < 2.7V -78 -64 -60 dB
2.7V < VDDIN < 3.6V -80 -74 -72
SINAD Signal to Noise and Distortion 2.4V < VDDIN < 2.7V 50 60 70 dB
2.7V < VDDIN < 3.6V 62 68 73
ENOB Effective Number of Bits 2.4V < VDDIN < 2.7V 8 10 12 bit
2.7V < VDDIN < 3.6V 10 11 12
Table 44-60. Analog Outputs
Symbol Parameter Conditions Min Typ Max Unit
VOR Voltage Range (1/6) × VADVREF – (5/6) × VADVREF V
SR Slew Rate
Channel output current versus slew rate
(IBCTL for DAC0 or DAC1, noted
IBCTLCHx)
RLOAD = 10 kΩ, 0 pF < CLOAD< 50 pF
IBCTLCHx = 00
IBCTLCHx = 01
IBCTLCHx = 10
IBCTLCHx = 11
–2.7
5.3
8
10.7
–V/µs
Output Channel
Current Consumption
No resistive load
IBCTLCHx = 00
IBCTLCHx = 01
IBCTLCHx = 10
IBCTLCHx = 11
–0.23
0.45
0.67
0.89
–mA
tsa Settling Time RLOAD = 10 kΩ, 0 pF < CLOAD< 50 pF – – 0.5 µs
RLOAD Output load resistor 10 – – kΩ
CLOAD Output load capacitor – 30 50 pF
1183
SAM4S Series [DATASHEET]
Atmel-11100K-ATARM-SAM4S-Datasheet_09-Jun-15
44.10 Analog Comparator Characteristics
44.11 Temperature Sensor
The temperature sensor is connected to channel 15 of the ADC.
The temp erature sen sor provides an output voltage (VO_TS) that is proportional to absolute temperature (PTAT).
VO_TS linearly varies with a temperature slope dVO_TS/dT = 4.7 mV/°C.
VO_TS equals 1.44 V at TA 27°C, with a ±60 mV accuracy. The VO_TS slope versus temperature dVO_TS/dT = 4.7
mV/°C only shows a ±7% slight variation over process, mismatch and supply voltage.
The user needs to calibrate it (offset calibration) at ambient temperature in order to get rid of the VO_TS spread at
ambient temperature (±15%).
Note: 1. The value of TS only (the value does not take into account the ADC offset/gain/errors)
2. The temperature accuracy takes into account the ADC offset error and gain error in single-ended mode with Gain = 1.
Table 44-6 1. Analog Comp arator Characteristics
Symbol Parameter Conditions Min Typ Max Unit
VRVoltage Range Analog comparator is supplied by VDDIN 1.62 3.3 3.6 V
VIR Input Voltage Range GND + 0.2 – VDDIN - 0.2 V
VIO Input Offset Voltage – – 20 mV
IVDDIN Current Consumption
(VDDIN) Low-Power Option (ACC_ACR.ISEL = 0) – – 25 µA
High-Speed Option (ACC_ACR.ISEL = 1) – – 170
Vhys Hysteresis Voltage ACC_ACR.HYST = 0x01 or 0x10 – 15 50 mV
ACC_ACR.HYST = 0x11 – 30 90
tsa Settling Time Overdrive > 100 mV; Low-power option – – 1 µs
Overdrive > 100 mV; High-speed option – – 0.1
Table 44-62. Temperature Sensor Cha racteristics
Symbol Parameter Conditions Min Typ Max Unit
VO_TS Output Voltage TA = 27°C (1) 1.44 – V
VO_TS(accuracy) Output Voltage Accuracy TA = 27°C (1) -60 – 60 mV
dVO_TS/dT Temperature Sensitivity (Slope
Voltage vs Temperature) (1) –4.7–mV/°C
Slope Accuracy Ove r te mperature range -40 to 105 °C (1) -7 – 7 %
Temperatur e Accu racy(2)
After offset cal ibration
over temperature range -40 to 105 °C -6–6°C
After offset cal ibration
over temperature range 0 to 80 °C -5–5°C
tSTART Startup Time After ADC_ACR.TSON = 1 (1) –510µs
IVDDCORE Current Consumption (1) 50 70 80 µA
SAM4S Series [DATASHEET]
Atmel-11100K-ATARM-SAM4S-Datasheet_09-Jun-15
1184
44.12 AC Characteristics
44.12.1 Master Clock Characteristics
44.12.2 I/O Characteristics
Criteria used to define the maximum frequency of the I/Os:
Output duty cycle (40%–60%)
Minimum output swing: 100 mV to VDDIO - 100 mV
Minimum output swing: 100 mV to VDDIO - 100 mV
Addition of rising and falling time inferior to 75% of the period
Notes: 1. Pin Group 1 = PA1 4, PA29
Table 44-6 3. Master Clock Waveform Parameters
Symbol Parameter Conditions Min Max Unit
1/(tCPMCK) Master Clock Frequency VDDCORE @ 1.20V – 120 MHz
VDDCORE @ 1.08V – 100
Table 44-64. I/O Characteristics
Symbol Parameter Conditions Min Max Unit
FreqMax1 Pin Group 1(1) Maximum Output Frequency 10 pF
VDDIO = 1.62V
–70
MHz
30 pF – 45
PulseminH1 Pin Group 1(1) High Level Pulse Width 10 pF – ns
–
30 pF 11 –
PulseminL1 Pin Group 1(1) Low Level Pulse Width 10 pF 7.2 – ns
30 pF 11 –
FreqMax2 Pin Group 2(2) Maximum Output Frequency 10 pF – 46 MHz
25 pF – 23
PulseminH2 Pin Group 2(2) High Level Pulse Width 10 pF 11 – ns
25 pF 21.8 –
PulseminL2 Pin Group 2(2) Low Level Pulse Width 10 pF 11 – ns
25 pF 21.8 –
FreqMax3 Pin Group3(3) Maximum Output Frequency 10 pF – 70 MHz
25 pF – 35
PulseminH3 Pin Group 3(3) High Level Pulse Width 10 pF 7.2 – ns
25 pF 14.2 –
PulseminL3 Pin Group 3(3) Low Level Pulse Width 10 pF 7.2 – ns
25 pF 14.2 –
FreqMax4 Pin Group 4(4) Maximum Output Frequency 10 pF – 58 MHz
25 pF – 29
PulseminH4 Pin Group 4(4) High Level Pulse Width 10 pF 8.6 – ns
25 pF 17.2 –
PulseminL4 Pin Group 4(4) Low Level Pulse Width 10 pF 8.6 – ns
25 pF 17.2 –
FreqMax5 Pin Group 5(5) Maximum Output Frequency 25 pF – 25 MHz
tsk(io) Maximum I/O skew for all I/Os except PB0 30 pF –800
ps
Maximum I/O skew for PB0 – 1200
1185
SAM4S Series [DATASHEET]
Atmel-11100K-ATARM-SAM4S-Datasheet_09-Jun-15
2. Pin Group 2 = PA[4–11], PA[15–25], PA[30–31], PB[0– 9], PB[12–14], PC[0–31]
3. Pin Group 3 = PA[12–13], PA[26–28], PA[30–31]
4. Pin Group 4 = PA[0–3]
5. Pin Group 5 = PB[10–11]
SAM4S Series [DATASHEET]
Atmel-11100K-ATARM-SAM4S-Datasheet_09-Jun-15
1186
44.12.3 SPI Characteristics
Figure 44-22. SPI Master Mode with (CPOL = NCPHA = 0) or (CPOL = NCPHA = 1)
Figure 44-23. SPI Master Mode with (CPOL = 0 and NCPHA = 1) or (CPOL = 1 and NCPHA = 0)
Figure 44-24. SPI Slave Mod e with (CPOL = 0 and NCPHA = 1) or (CPOL = 1 and NCPHA = 0)
SPCK
MISO
MOSI
SPI
2
SPI
0
SPI
1
SPCK
MISO
MOSI
SPI5
SPI3SPI4
SPCK
MISO
MOSI
SPI
6
SPI
7
SPI
8
NPCSS
SPI
12
SPI
13
1187
SAM4S Series [DATASHEET]
Atmel-11100K-ATARM-SAM4S-Datasheet_09-Jun-15
Figure 44-25. SPI Slave Mode with (CPOL = NCPHA = 0) or (CPOL = NCPHA = 1)
44.12.3.1 Maximum SPI Frequency
The following formulas give maximum SPI frequency in master read and write modes and in slave read and write
modes.
Master Write Mode
The SPI only sends data to a slave device such as a n LCD, for examp le. Th e limit is given by SPI 2 (o r SPI 5)
timing. Since it gives a ma xim u m freq ue n cy above the maximu m pa d speed (s ee Section 44.12.2 “I/O
Characteristics”), the maximum SPI frequency is defined by the pin FreqMax value.
Master Read Mode
tvalid is the slave tim e response to output da ta after dete cting a n SPCK edge. For a non-volati le me mory with
tvalid (or tV) = 12 ns Max, fSPCKMax = 35.5 MHz @ VDDIO = 3.3V.
Slave Read Mode
In slave mode, SPCK is the input clock for the SPI. The maximum SPCK frequency is given by setup and
hold timings SPI7/SPI8 (or SPI10/SPI11). Since this gives a frequency well above the pad limit, the limit in
slave read mode is given by SPCK pad.
Slave Write Mode
For 3.3V I/O domain and SPI6, fSPCKMax = 25 MHz. tsu is the setup time from the master before sampling
data.
SPCK
MISO
MOSI
SPI9
SPI10 SPI11
NPCS0
SPI14
SPI15
fSPCKMax 1
SPI0orSPI3
()tvalid
+
------------------------------------------------------
=
fSPCKMax 1
2xS(PI6max orSPI9max
()tsu)+
------------------------------------------------------------------------------
=
SAM4S Series [DATASHEET]
Atmel-11100K-ATARM-SAM4S-Datasheet_09-Jun-15
1188
44.12.3.2 SPI Timings
SPI timings are given for the following domains:
1.8V domain: VDDIO from 1.65 to 1.95 V, maximum external capacitor = 20 pF
3.3V domain: VDDIO from 2.85 to 3.6 V, maximum external capacitor = 40 pF
Table 44-65. SPI Timings
Symbol Parameter Conditions Min Max Unit
SPI0MISO Setup Time before SPCK Rises (Master) 3.3V domain 11.3 – ns
1.8V domain 13.3 – ns
SPI1MISO Hold Time after SPCK Rises (Master) 3.3V domain 0 – ns
1.8V domain 0 – ns
SPI2SPCK Rising to MOSI Delay (Master) 3.3V domain -2.0 1.9 ns
1.8V domain -1.9 1.0 ns
SPI3MISO Setup Time before SPCK Falls (Master) 3.3V domain 16 .2 – ns
1.8V domain 21.6 – ns
SPI4MISO Hold Time after SPCK Falls (Master) 3.3V domain 0 – ns
1.8V domain 0 – ns
SPI5SPCK Falling to MOSI Delay (Master) 3.3V domain -7 -3.6 ns
1.8V domain -6.7 -4.2 ns
SPI6SPCK Falling to MISO Delay (Slave) 3.3V domain 3.4 11.1 ns
1.8V domain 4.1 13.1 ns
SPI7MOSI Setup Time before SPCK Rises (Slave) 3.3V domain 0 – ns
1.8V domain 0 – ns
SPI8MOSI Hold Time after SPCK Rises (Slave) 3.3V domain 1.3 – ns
1.8V domain 0.9 – ns
SPI9SPCK Rising to MISO Delay (Slave) 3.3V domain 3.6 11.5 ns
1.8V domain 4.1 12.9 ns
SPI10 MOSI Setup Time before SPCK Falls (Slave) 3.3V domai n 0 – ns
1.8V domain 0 – ns
SPI11 MOSI Hold Time after SPCK Falls (Slave) 3.3V domain 0.8 – ns
1.8V domain 0.9 – ns
SPI12 NPCS Setup to SPCK Rising (Slave) 3.3V domain 3.3 – ns
1.8V domain 3.5 – ns
SPI13 NPCS Hold after SPCK Falling (Slave) 3.3V domain 0 – ns
1.8V domain 0 – ns
SPI14 NPCS Setup to SPCK Falling (Slave) 3.3V domain 4 – ns
1.8V domain 3.6 – ns
SPI15 NPCS Hold after SPCK Falling (Slave) 3.3V domain 0 – ns
1.8V domain 0 – ns
1189
SAM4S Series [DATASHEET]
Atmel-11100K-ATARM-SAM4S-Datasheet_09-Jun-15
Note that in SPI Master Mode the SAM4S does not sample the data (MISO) on the opposite edge where data
clocks out (MOSI) but the same edge is used. This is shown in Figure 44-22 and Figure 44-23.
44.12.4 HSMCI Timings
The High-speed MultiMedia Card Interface ( HSMCI) supports the MultiMedia Card (MMC) Specification V4.3, the
SD Memory Card Specification V2.0, the SDIO V2.0 specification and CE-ATA V1.1.
44.12.5 SSC Timings
SSC timings are given for the following domains:
1.8V domain: VDDIO from 1.65 to 1.95 V, maximum exte rn al ca pacitor = 20 pF
3.3V domain: VDDIO from 2.85 to 3.6 V, maximum external capacitor = 30 pF
Figure 44-26. SSC Transmitter, TK and TF as Outpu t
Figure 44-27. SSC Transmitter, TK as Input and TF as Output
TK (CKI =1)
TF/TD
SSC
0
TK (CKI =0)
TK (CKI =1)
TF/TD
SSC
1
TK (CKI =0)
SAM4S Series [DATASHEET]
Atmel-11100K-ATARM-SAM4S-Datasheet_09-Jun-15
1190
Figure 44-28. SSC Transmitter, TK as Output and TF as Input
Figure 44-29. SSC Transmitter, TK and TF as Inpu t
Figure 44-30. SSC Receiver RK and RF as Input
TK (CKI=1)
TF
SSC
2
SSC
3
TK (CKI=0)
TD
SSC
4
TK (CKI=0)
TF
SSC
5
SSC
6
TK (CKI=1)
TD
SSC
7
RK (CKI=1)
RF/RD
SSC8SSC9
RK (CKI=0)
1191
SAM4S Series [DATASHEET]
Atmel-11100K-ATARM-SAM4S-Datasheet_09-Jun-15
Figure 44-31. S SC Receiver, RK as Input and RF as Output
Figure 44-32. S SC Receiver, RK and RF as Outp ut
Figure 44-33. SSC Receiver, RK as Output and RF as Input
RK (CKI=0)
RD
SSC
8
SSC
9
RK (CKI=1)
RF
SSC
10
RK (CKI=0)
RD
SSC11 SSC12
RK (CKI=1)
RF
SSC13
RK (CKI=1)
RF/RD
SSC11 SSC12
RK (CKI=0)
SAM4S Series [DATASHEET]
Atmel-11100K-ATARM-SAM4S-Datasheet_09-Jun-15
1192
Table 44-6 6. SSC Timings
Symbol Parameter Conditions Min Max Unit
Transmitter
SSC0TK Edge to TF/TD
(TK Output, TF Output) 1.8V domain
3.3V domain -3
-2.6 5.4
5.0 ns
SSC1TK Edge to TF/TD
(TK Input, TF Output) 1.8V domain
3.3V domain 4.5
3.8 19.6
13.3 ns
SSC2TF Setup T ime before TK Edge
(TK Output) 1.8V domain
3.3V domain 18.9
12.0 –ns
SSC3TF Hold Time after TK Edge
(TK Output) 1.8V domain
3.3V domain 0–ns
SSC4TK Edge to TF/TD
(TK Output, TF Input)
1.8V
domain
–2.65.4
ns
STTDLY = 0
START = 4, 5 or 7 2.6 + (2 × tCPMCK)(1) 5.4 + (2 × tCPMCK)(1)
3.3V
domain
–2.35.0
STTDLY = 0
START = 4, 5 or 7 2.3 + (2 × tCPMCK)(1) 5.0 + (2 × tCPMCK)(1)
SSC5TF Setup T ime before TK Edge
(TK Input) 1.8V domain
3.3V domain 0–ns
SSC6TF Hold Time after TK edge
(TK Input) 1.8V domain
3.3V domain tCPMCK –ns
SSC7TK Edge to TF/TD
(TK Input, TF Input)
1.8V
domain
–4.516.3
ns
STTDLY = 0
START = 4, 5 or 7 4.5 + (3 × tCPMCK)(1) 16.3 + (3 × tCPMCK)(1)
3.3V
domain
–3.813.3
STTDLY = 0
START = 4, 5 or 7 3.8 + (3 × tCPMCK)(1) 13.3 + (3 × tCPMCK)(1)
Receiver
SSC8RF/RD Setup Time before RK
Edge (RK Input) 1.8V domain
3.3V domain 0–ns
SSC9RF/RD Hold T ime after RK
Edge (RK Input) 1.8V domain
3.3V domain tCPMCK –ns
SSC10 RK Edge to RF (RK Input) 1.8V domain
3.3V domain 4.7
416.1
12.8 ns
SSC11 RF/RD Setup Time before RK
Edge (RK Output) 1.8V domain
3.3V domain 15.8 - tCPMCK
12.5 - tCPMCK –ns
SSC12 RF/RD Hold T ime after RK
Edge (RK Output) 1.8V domain
3.3V domain tCPMCK - 4.3
tCPMCK - 3.6 –ns
SSC13 RK Edge to RF (RK Output) 1.8V domain
3.3V domain -3
-2.6 4.3
3.8 ns
1193
SAM4S Series [DATASHEET]
Atmel-11100K-ATARM-SAM4S-Datasheet_09-Jun-15
Note: 1. For output signals (TF, TD, RF), Min and Max access times are defined. The Min access time is the time between the TK (or
RK) edge and the signal change. The Max access time is the time between the TK edge and the signal stabilization. Figure
44-34 illustrates Min and Max accesses for SSC0. This also applies for SSC1, SSC4, and SSC7, SSC10 and SSC13.
Figure 44-34. Min and Max Access Time of Output Signals
TK (CKI = 0)
TF/TD
SSC0min
TK (CKI = 1)
SSC0max
SAM4S Series [DATASHEET]
Atmel-11100K-ATARM-SAM4S-Datasheet_09-Jun-15
1194
44.12.6 SMC Timings
SMC timings are give n in the follow i ng doma ins :
1.8V domain: VDDIO from 1.65 to 1.95 V, maximum exte rn al ca pacitor = 30 pF
3.3V domain: VDDIO from 2.85 to 3.6 V, maximum external capacitor = 50 pF
Timings are given assuming a capacitance load on data, contr ol and address pads.
In the following tables tCPMCK is MCK period.
44.12.6.1 Read Timings
Table 44-6 7. SMC Read Signals - NRD Controlled (READ_MODE = 1)
Symbol
Parameter Min Max
UnitVDDIO Supply 1.8V Domain 3.3V Domain 1.8V Domain 3.3V Domain
NO HOLD Settings (NRD_HOLD = 0)
SMC1Data Setup before NRD High 24.5 21.3 – – ns
SMC2Data Hold after NRD High 0 0 – – ns
HOLD Settings (NRD_HOLD ≠ 0)
SMC3Data Setup before NRD High 19.5 14.0 – – ns
SMC4Data Hold after NRD High 0 0 – – ns
HOLD or NO HOLD Settings (NRD_HOLD ≠ 0, NRD_HOLD = 0)
SMC5 A0–A22 Valid before NRD High (NRD_SETUP +
NRD_PULSE) × tCPMCK - 6.5 (NRD_SETUP +
NRD_PULSE) × tCPMCK - 6.3 ––ns
SMC6NCS Low before NRD High
(NRD_SETUP +
NRD_PULSE -
NCS_RD_SETUP) ×
tCPMCK - 4.5
(NRD_SETUP +
NRD_PULSE -
NCS_RD_SETUP) ×
tCPMCK - 5.1
––ns
SMC7NRD Pulse Width NRD_PULSE × tCPMCK - 7.2 NRD_PULSE × tCPMCK - 6.2 – – ns
Table 44-6 8. SMC Read Signals - NCS Controlled (READ_ MODE = 0)
Symbol
Parameter Min Max
UnitVDDIO Supply 1.8V Domain 3.3V Domain 1.8V
Domain 3.3V
Domain
NO HOLD Settings (NCS_RD_HOLD = 0)
SMC8Data Setup before NCS High 20.7 18.4 – – ns
SMC9Data Hold after NCS High 0 0 – – ns
HOLD Settings (NCS_RD_HOLD ≠ 0)
SMC10 Data Setup before NCS High 16.8 14.5 – – ns
SMC11 Data Hold after NCS High 0 0 – – ns
1195
SAM4S Series [DATASHEET]
Atmel-11100K-ATARM-SAM4S-Datasheet_09-Jun-15
44.12.6.2 Write Timings
Notes: 1. Hold length = total cycle duration - setup duration - pulse duration. “Hold length” is for “NCS_WR_HOLD length” or
“NWE_HOLD length”.
HOLD or NO HOLD Settings (NCS_RD_HOLD ≠ 0, NCS_RD_HOLD = 0)
SMC12 A0–A22 Valid before NCS High (NCS_RD_SETUP +
NCS_RD_PULSE) ×
tCPMCK - 6.5
(NCS_RD_SETUP +
NCS_RD_PULSE) ×
tCPMCK - 6.3 ––ns
SMC13 NRD Low before NCS Hig h
(NCS_RD_SETUP +
NCS_RD_PULSE -
NRD_SETUP) × tCPMCK -
5.6
(NCS_RD_SETUP +
NCS_RD_PULSE -
NRD_SETUP) × tCPMCK - 5.4 ––ns
SMC14 NCS Pulse Width NCS_RD_PULSE length ×
tCPMCK -7.7 NCS_RD_PULSE length ×
tCPMCK - 6.7 ––ns
Table 44-6 9. SMC Write Signals - NWE Controlled (WRITE_MODE = 1)
Symbol Parameter
Min Max
Unit1.8V Domain 3.3V Domain 1.8V
Domain 3.3V
Domain
HOLD or NO HOLD Settings (NWE_HOLD ≠ 0, NWE_HOLD = 0)
SMC15 Data Out Valid before NWE High NWE_PULSE × tCPMCK - 6.9 NWE_PULSE × tCPMCK - 3.3 – – ns
SMC16 NWE Pulse Width NWE_PULSE × tCPMCK - 7.3 NWE_PULSE × tCPMCK - 6.3 – – ns
SMC17 A0–A22 Valid before NWE Low NWE_SETUP × tCPMCK - 7.2 NWE_SETUP × tCPMCK - 7.0 – – ns
SMC18 NCS Low befo re NWE High (NWE_SETUP -
NCS_RD_SETUP +
NWE_PULSE) × tCPMCK - 4.1
(NWE_SETUP -
NCS_RD_SETUP +
NWE_PULSE) × tCPMCK - 3.1 ––ns
HOLD Settings (NWE_HOLD ≠ 0)
SMC19
NWE High to Data OUT,
NBS0/A0 NBS1, NBS2/A1,
NBS3, A2–A25 change NWE_HOLD × tCPMCK - 12.2 NWE_HOLD × tCPMCK - 6.9– –ns
SMC20 NWE High to NCS Inactive(1) (NWE_HOLD -
NCS_WR_HOLD) × tCPMCK -
8.6
(NWE_HOLD -
NCS_WR_HOLD) × tCPMCK -
5.0 ––ns
NO HOLD Settings (NWE_HOLD = 0)
SMC21
NWE High to Data OUT,
NBS0/A0 NBS1, NBS2/A1,
NBS3, A2–A25, NCS change(1) 3.0 2.8 – – ns
Table 44-6 8. SMC Read Signals - NCS Controlled (READ_MODE = 0) (Continued )
Symbol
Parameter Min Max
UnitVDDIO Supply 1.8V Domain 3.3V Domain 1.8V
Domain 3.3V
Domain
SAM4S Series [DATASHEET]
Atmel-11100K-ATARM-SAM4S-Datasheet_09-Jun-15
1196
Figure 44-35. SMC Timin gs - NCS Controlled Read and Write
Table 44-7 0. SMC Write Signals - NCS Controlled (WRITE_MODE = 0)
Symbol Parameter
Min Max
Unit1.8V Domain 3.3 V Domain 1.8V
Domain 3.3V
Domain
SMC22 Data Out Valid before NCS High NCS_WR_PULSE
× tCPMCK - 6.3 NCS_WR_PULSE
× tCPMCK - 6.2 ––ns
SMC23 NCS Pulse Width NCS_WR_PULSE
× tCPMCK - 7.7 NCS_WR_PULSE
× tCPMCK - 6.7 ––ns
SMC24 A0–A22 Valid before NCS Low NCS_WR_SETUP
× tCPMCK - 6.5 NCS_WR_SETUP
× tCPMCK - 6.3 ––ns
SMC25 NWE Low before NCS High (NCS_WR_SETUP -
NWE_SETUP + NCS pulse)
× tCPMCK - 5.1
(NCS_WR_SETUP -
NWE_SETUP + NCS pulse)
× tCPMCK - 4.9 ––ns
SMC26 NCS High to Data Out, A0–A25,
Change NCS_WR_HOLD
× tCPMCK - 10.2 NCS_WR_HOLD
× tCPMCK - 8.4 ––ns
SMC27 NCS High to NWE Inactive (NCS_WR_HOLD -
NWE_HOLD) × tCPMCK - 2.1 (NCS_WR_HOLD -
NWE_HOLD) × tCPMCK - 1.6 ––ns
NRD
NCS
DATA
NWE
NCS Controlled READ
with NO HOLD
NCS Controlled READ
with HOLD
NCS Controlled WRITE
SMC22 SMC26
SMC10 SMC11
SMC12
SMC9
SMC8
SMC14 SMC14 SMC23
SMC27
SMC26
A
0–A23
SMC24
SMC25
SMC12
SMC13 SMC13
1197
SAM4S Series [DATASHEET]
Atmel-11100K-ATARM-SAM4S-Datasheet_09-Jun-15
Figure 44-36. SMC Timings - NRD Controlled Read and NWE Controlled Write
NRD
NCS
DATA
NWE
A0–A23
NRD Controlled READ
with NO HOLD
NWE Controlled WRITE
with NO HOLD
NRD Controlled READ
with HOLD
NWE Controlled WRITE
with HOLD
SMC1 SMC2 SMC15
SMC21
SMC3 SMC4 SMC15 SMC19
SMC20
SMC7
SMC21
SMC16
SMC7
SMC16
SMC19
SMC21
SMC17
SMC18
SMC5
SMC5
SMC6 SMC6
SMC17
SMC18
SAM4S Series [DATASHEET]
Atmel-11100K-ATARM-SAM4S-Datasheet_09-Jun-15
1198
44.12.7 USART in SPI Mode Timings
Timings are given in the following domain:
1.8V domain: VDDIO from 1.65 to 1.95 V, maximum exte rn al ca pacitor = 20 pF
3.3V domain: VDDIO from 2.85 to 3.6 V, maximum external capacitor = 40 pF
Figure 44-37. USART SPI Master Mode
Figure 44-38. USART SPI Slave Mode: (Mode 1 or 2)
NSS
SPI0
MSB LSB
SPI1
CPOL = 1
CPOL = 0
MISO
MOSI
SCK
SPI5
SPI2
SPI3
SPI4
SPI4
• MOSI line is driven by the output pin TXD
• MISO line drives the input pin RXD
• SCK line is driven by the output pin SCK
• NSS line is driven by the output pin RTS
SCK
MISO
MOSI
SPI6
SPI7SPI8
NSS
SPI12 SPI13
• MOSI line drives the input pin RXD
• MISO line is driven by the output pin TXD
• SCK line drives the input pin SCK
• NSS line drives the input pin CTS
1199
SAM4S Series [DATASHEET]
Atmel-11100K-ATARM-SAM4S-Datasheet_09-Jun-15
Figure 44-39. USART SPI Slave Mode: (Mode 0 or 3)
SCK
MISO
MOSI
SPI9
SPI10 SPI11
NSS
SPI14
SPI15
SAM4S Series [DATASHEET]
Atmel-11100K-ATARM-SAM4S-Datasheet_09-Jun-15
1200
44.12.7.1 USART SPI TImings
Table 44-71. USART SPI Timings
Symbol Parameter Conditions Min Max Unit
Master Mode
SPI0SCK Period 1.8V domain
3.3V domain MCK/6 – ns
SPI1Input Data Setup Time 1.8V doma in
3.3V domain 0.5 × MCK + 0.8
0.5 × MCK + 1.0 –ns
SPI2Input Data Hold Time 1.8V do main
3.3V domain 1.5 × MCK + 0.3
1.5 × MCK + 0.1 –ns
SPI3Chip Select Active to Serial Clock 1.8V domain
3.3V domain 1.5 × SPCK - 1.5
1.5 × SPCK - 2.1 –ns
SPI4Output Data Setup Time 1.8V domain
3.3V domain - 7.9
- 7.2 9.9
10.7 ns
SPI5Serial Clock to Chip Select Inactive 1.8V domain
3.3V domain 1 × SPCK - 7.7
1 × SPCK - 11.8 –ns
Slave Mode
SPI6SCK Falling to MISO 1.8V domain
3.3V domain 4.7
417.3
15.2 ns
SPI7MOSI Setup Time before SCK Rises 1.8V domain
3.3V domain 2 × MCK + 0.7
2 × MCK –ns
SPI8MOSI Hold Time after SCK Rises 1.8V domain
3.3V domain 0
0.1 –ns
SPI9SCK Rising to MISO 1.8V domain
3.3V domain 4.7
4.1 20.1
15.5 ns
SPI10 MOSI Setup Time before SCK Falls 1.8V domain
3.3V domain 2 × MCK + 0.7
2 × MCK + 0.6 –ns
SPI11 MOSI Hold Time after SCK Falls 1.8V domain
3.3V domain 0.2
0.1 –ns
SPI12 NPCS0 Setup to SCK Rising 1.8V domain
3.3V domain 2.5 × MCK + 0.5
2.5 × MCK –ns
SPI13 NPCS0 Hold after SCK Falling 1.8V domain
3.3V domain 1.5 × MCK + 0.2
1.5 × MCK –ns
SPI14 NPCS0 Setup to SCK Falling 1.8V domain
3.3V domain 2.5 × MCK + 0.5
2.5 × MCK + 0.3 –ns
SPI15 NPCS0 Hold after SCK Rising 1.8V domain
3.3V domain 1.5 × MCK
1.5 × MCK –ns
1201
SAM4S Series [DATASHEET]
Atmel-11100K-ATARM-SAM4S-Datasheet_09-Jun-15
44.12.8 Two-wire Serial Interface Characteristics
Table 44-72 describes the requirements for devices connected to the two-wire serial bus. For timing symbols refer to Fig-
ure 44-40.
Notes: 1. Required only for fTWCK > 100 kHz
2. Cb = capacitance of one bus line in pF. Per I2C Standard, Cb Max = 400 pF
3. The TWCK low period is defined as follows: tLOW = ((CLDIV × 2CKDIV) + 4) × tMCK
4. The TWCK high period is defined as follows: tHIGH = ((CHDIV × 2CKDIV) + 4) × tMCK
5. tCPMCK = MCK bus period.
Table 44-7 2. Two-wire Serial Bus Requirements
Symbol Parameter Condition Min Max Unit
VIL Input Low-voltage -0.3 0.3 × VDDIO V
VIH Input High-voltage 0.7 × VDDIO VCC + 0.3 V
Vhys Hysteresis of Schmitt Trigger Inputs 0.150 – V
VOL Output Low-voltage 3 mA sink current - 0.4 V
trRise Time for both TWD and T WCK 20 + 0.1Cb(1)(2) 300 ns
tfo Output Fall Time from VIHmin to VILmax 10 pF < Cb < 400 pF
Figure 44-40 20 + 0.1Cb(1)(2) 250 ns
Ci(1) Capacitance for each I/O Pin – 10 pF
fTWCK TWCK Clock Frequency 0 400 kHz
Rp Value of Pull-up Resistor fTWCK ≤ 100 kHz (VDDIO - 0.4V) ÷ 3mA 1000ns ÷ CbΩ
fTWCK > 100 kHz (VDDIO - 0.4V) ÷ 3mA 3 00ns ÷ CbΩ
tLOW Low Period of the TWCK Clock fTWCK ≤ 100 kHz (3) –µs
fTWCK > 100 kHz (3) –µs
tHIGH High Period of the TWCK Clock fTWCK ≤ 100 kHz (4) –µs
fTWCK > 100 kHz (4) –µs
th(start) Hold Time (repeated) START Condition fTWCK ≤ 100 kHz tHIGH –µs
fTWCK > 100 kHz tHIGH –µs
tsu(start) Set-up Time for a Repeated START
Condition fTWCK ≤ 100 kHz tHIGH –µs
fTWCK > 100 kHz tHIGH –µs
th(data) Data Hold Time fTWCK ≤ 100 kHz 0 3 × tCPMCK(5) µs
fTWCK > 100 kHz 0 3 × tCPMCK(5) µs
tsu(data) Data Setup Time fTWCK ≤ 100 kHz tLOW - 3 × tCPMCK(5) –ns
fTWCK > 100 kHz tLOW - 3 × tCPMCK(5) –ns
tsu(stop) Setup Time for STOP Condition fTWCK ≤ 100 kHz tHIGH –µs
fTWCK > 100 kHz tHIGH –µs
tBUF Bus Free Time between a STOP and
START Condition fTWCK ≤ 100 kHz tLOW –µs
fTWCK > 100 kHz tLOW –µs
SAM4S Series [DATASHEET]
Atmel-11100K-ATARM-SAM4S-Datasheet_09-Jun-15
1202
Figure 44-40. Two-wire Serial Bus Timing
tsu(start)
tLOW
tHIGH
tLOW
tfo
th(start) th(data) tsu(data) tsu(stop)
tBUF
TWCK
TWD
tr
1203
SAM4S Series [DATASHEET]
Atmel-11100K-ATARM-SAM4S-Datasheet_09-Jun-15
44.12.9 Embedded Flash Characteristics
The maximum operating frequency given in Table 44-73 is limited by the embedded Flash access time when the processor
is fetching code out of it. The table provides the device maximum operating frequency defined by th e value of the field FWS
in the EEFC_FMR. This field defines the number of wait states required to access the embedded Flash memory.
The embedded Flash is fully tested during production test. The Flash contents are not set to a known state prior to ship-
ment. Therefore, the Flash contents should be erased prior to programming an application.
Notes: 1. Only the read operation is characterized between -40 and 105 °C.
Other operations are characterized between -40 and 85 °C.
2. All bits in the word(s) are set to 0.
Table 44-73. Embedded Flash Wait State at 105°C
FWS Read Operations
Maximum Operating Frequency (MHz)
VDDCORE 1.08V VDDCORE 1.2V
VDDIO 1.62–3.6 V VDDIO 2.7–3.6 V VDDIO 1.62–3.6 V VDDIO 2.7–3.6 V
0 1 cycle 16 20 17 21
1 2 cycles 33 40 34 42
2 3 cycles 50 60 52 63
3 4 cycles 67 80 69 84
4 5 cycles 84 100 87 105
5 6 cycles 100 – 104 120
Table 44-7 4. AC Flash Ch aracteristics
Parameter Conditions(1) Min Typ Max Unit
Program Cycle Time
Erase Page Mode – 10 50 ms
Erase Block Mode (by 4 Kbytes) – 50 200 ms
Erase Sector Mode – 400 950 ms
Erase Pin Assertion Time Erase pin high 220 – – ms
Full Chip Erase
1 Mbyte – 9 18
s
512 Kbytes – 5.5 11
256 Kbytes – 3 6
128 Kbytes – 2 4
Data Retention Not powered or powered – 20 – years
Page Program Time(2)
1 word changed in the page – – 75 µs
2 words changed in the page – – 120 µs
4 words changed in the page – – 210 µs
16 words changed in the page – – 740 µs
32 words changed in the page – – 1.45 ms
Full page – – 3 ms
Endurance
Write/Erase cycles per page, block or
sector @ 85°C 10k ––
cycles
Write/Erase cycles per page, block or
sector @ 50°C 50k – –
SAM4S Series [DATASHEET]
Atmel-11100K-ATARM-SAM4S-Datasheet_09-Jun-15
1204
45. Mechanical Characteristics
All packages of the SAM4S devices respect the recommendations of the NEMI User Group.
45.1 100-lead LQFP Mechanical Characteristics
Figure 45-1. 100-lead LQFP Package Mechanical Drawing
Note : 1. This drawing is for general information only. Refer to JEDEC Drawing MS-026 for additional information.
CONTROL DIMENSIONS ARE IN MILLIMETERS
Table 45-1. Device and LQFP Package Maximum We ight
SAM4S 800 mg
Table 45-2. Package Reference
JEDEC Drawing Reference MS-026
JESD97 Classification e3
Table 45-3. LQFP Package Characteristics
Moisture Sensitivity Level 3
1205
SAM4S Series [DATASHEET]
Atmel-11100K-ATARM-SAM4S-Datasheet_09-Jun-15
45.2 100-ball TFBGA Mechanical Characteristics
Figure 45-2. 100-ball TFBGA Package Drawing
Table 45-4. TFBGA Package Reference - Soldering Informatio n (Substrate Level)
Ball Land Diameter 450 µm
Soldering Mask Opening 350 µm
Table 45-5. Device and 100-ball TFBGA Package Maximum Weight
SAM4S 141 mg
Table 45-6. 100-ball TFBGA Package Cha racteristics
Moisture Sensitivity Level 3
Table 45-7. 100-ball TFBGA Package Reference
JEDEC Drawing Reference MO-275-DDAC-1
JESD97 Classification e8
SAM4S Series [DATASHEET]
Atmel-11100K-ATARM-SAM4S-Datasheet_09-Jun-15
1206
45.3 100-ball VFBGA Mechanical Characteristics
Figure 45-3. 100-ball VFBGA Pac kage Drawing
Table 45-8. VFBGA Package Dimens ions
Symbol Common Dimensions (mm)
Package: VFBGA
Body Size: X E 7.000 ± 0.100
Y D 7.000 ± 0.100
Ball Pitch: XeE 0.650
YeD 0.650
Total Thickness: A 1.000 max
Mold Thickness: M 0.450 ref.
Substrate Thickness: S 0.210 ref.
1207
SAM4S Series [DATASHEET]
Atmel-11100K-ATARM-SAM4S-Datasheet_09-Jun-15
Ball Diameter: 0.300
Stand Off: A1 0.160 ~ 0.260
Ball Width: b 0.270 ~ 0.370
Package Edge Tolerance: aaa 0.100
Mold Flatness: bbb 0.100
Coplanarity: ddd 0.080
Ball Offset (Package): eee 0.150
Ball Offset (Ball): fff 0.080
Ball Count: n 100
Edge Ball Center to Center: XE1 5.850
YD1 5.850
Corner Ball Center to Package Edge: X I 0.575
Y J 0.575
Table 45-9. VFBGA Package Reference - Soldering Information (Substrate Level)
Ball Land Diameter 0.27 mm
Soldering Mask Opening 275 µm
Table 45-10. Device and 100 -ball VFBGA Package Maximum Weight
SAM4S 75 mg
Table 45-11. 100-ball VFBGA Package Characteristics
Moisture Sensitivity Level 3
Table 45-12. 100-ball VFBGA Package Reference
JEDEC Drawing Reference MO-275-BBE-1
JESD97 Classification e8
Table 45-8. VFBGA Package Dimens ions (Continued)
Symbol Common Dimensions (mm)
SAM4S Series [DATASHEET]
Atmel-11100K-ATARM-SAM4S-Datasheet_09-Jun-15
1208
45.4 64-lead LQFP Mechanical Characteristics
Figure 45-4. 64-lead LQFP Package Drawing
Table 45-13. 64-lead LQFP Package Dimensio ns (in mm)
Symbol
Millimeter Inch
Min Nom Max Min Nom Max
A – –1.60– –0.063
A1 0.05 – 0.15 0.002 – 0.006
A2 1.35 1.40 1.45 0.053 0.055 0.057
D 12.00 BSC 0.472 BSC
D1 10.00 BSC 0.383 BSC
E 12.00 BSC 0.472 BSC
E1 10.00 BSC 0.383 BSC
R2 0.08 – 0.20 0.003 – 0.008
1209
SAM4S Series [DATASHEET]
Atmel-11100K-ATARM-SAM4S-Datasheet_09-Jun-15
R1 0.08 – – 0.003 – –
q 0°3.5°7° 0°3.5°7°
θ10° – – 0° – –
θ211° 12° 13° 11° 12° 13°
θ311° 12° 13° 11° 12° 13°
c 0.09 – 0.20 0.004 – 0.008
L 0.45 0.60 0.75 0.018 0.024 0.030
L1 1.00 REF 0.039 REF
S 0.20 – – 0.008 – –
b 0.17 0.20 0.27 0.007 0.008 0.011
e 0.50 BSC. 0.020 BSC.
D2 7.50 0.285
E2 7.50 0.285
Tolerances of Form and Position
aaa 0.20 0.008
bbb 0.20 0.008
ccc 0.08 0.003
ddd 0.08 0.003
Table 45-14. Device and LQFP Package Maximum Weight
SAM4S 750 mg
Table 45-15. LQFP Package Reference
JEDEC Drawing Reference MS-026
JESD97 Classification e3
Table 45-16. LQFP Package Characteristics
Moisture Sensitivity Level 3
Table 45-13. 64-lead LQFP Package Dimensio ns (in mm)
Symbol
Millimeter Inch
Min Nom Max Min Nom Max
SAM4S Series [DATASHEET]
Atmel-11100K-ATARM-SAM4S-Datasheet_09-Jun-15
1210
45.5 64-lead QFN Mechanical Characteristics
Figure 45-5. 64-lead QFN Package Drawing
Table 45-17. Device and QF N Package Maximum Weight (Pr eliminary)
SAM4S 280 mg
Table 45-18. QFN Package Refere nce
JEDEC Drawing Reference MO-220
JESD97 Classification e3
Table 45-19. QFN Package Cha racteristics
Moisture Sensitivity Level 3
1211
SAM4S Series [DATASHEET]
Atmel-11100K-ATARM-SAM4S-Datasheet_09-Jun-15
45.6 64-ball WLCSP Mechanical Characteristics
This package respects the recommendations of the NEMI User Group.
Figure 45-6. 64-ball WLCSP Package Mechanical Drawing (SAM4SD32/SAM4SD16)
SAM4S Series [DATASHEET]
Atmel-11100K-ATARM-SAM4S-Datasheet_09-Jun-15
1212
Figure 45-7. 64-ball WLCSP Package Mechanical Dr awing (SAM4S16/SAM4S8/SAM4S4/SAM4S2)
Table 45-20. 64-ball WLCSP Package Dimensions (in mm)
Symbol
Common Dimensions
MIN. NOM. MAX.
Total Th i ckn ess A 0.455 0.494 0.533
Stand Off A1 0.17 - 0.23
Wafer Thickness A2 0.254 ± 0.025
Body Size (4) D 4.423 BSC(1) / 4.424 BSC(2)/3.323 BSC(3)
E 4.723 BSC(1) / 3.420 BSC(2)/3.323 BSC (3)
Ball Diameter (Size) 0.25
Ball/Bump Width b 0.23 0.26 0.29
Ball/Bump Pitch eD 0.4
eE 0.4
Ball/Bump Count n 64
Edge Ball Center to Center D1 2.8 BSC
E1 2.8 BSC
1213
SAM4S Series [DATASHEET]
Atmel-11100K-ATARM-SAM4S-Datasheet_09-Jun-15
Notes: 1. For SAM4SD32/SAM4SD16
2. For SAM4S16/SAM4S8
3. For SAM4S4/SAM4S2
4. SAM4SD32/SD16/S8/S16 are pin-to-p in compatible.
Figure 45-8. UBM Pad Installation
Package Edge Tolerance aaa 0.03
Coplanarity (Whole Wafer) ccc 0.075
Ball/Bump Offset (Package) ddd 0.05
Ball/Bump Offset (Ball) eee 0.015
Table 45-21. WLCSP Package Referen ce - Soldering Information (Substrate Level)
UBM Pad (Under Bump Metallurgy) (E) 200 µm
PBO2 Opening (j) 240 µm
Table 45-22. Device and 64-ball WLCSP Package Maximum Weight
SAM4S TBD mg
Table 45-23. 64-ball WLCSP Package Characteristics
Moisture Sensitivity Level 1
Table 45-24. 64-ball WLCSP Package Refere nce
JEDEC Drawing Reference Not JEDEC
JESD97 Classification e1
Table 45-20. 64-ball WLCSP Package Dimensions (in mm) (Continued)
Symbol
Common Dimensions
MIN. NOM. MAX.
SAM4S Series [DATASHEET]
Atmel-11100K-ATARM-SAM4S-Datasheet_09-Jun-15
1214
45.7 48-lead LQFP Mechanical Characteristics
Figure 45-9. 48-lead LQFP Package Drawing
Table 45-25. Device and 48-lead LQFP Package Maximum Weight
SAM4S 190 mg
Table 45-26. 48-lead LQFP Package Characteristic s
Moisture Sensitivity Level 3
1
3
2
1
1.0
1.0
1.0
1215
SAM4S Series [DATASHEET]
Atmel-11100K-ATARM-SAM4S-Datasheet_09-Jun-15
Table 45-27. 48-lead LQFP Package Reference
JEDEC Drawing Reference
JESD97 Classification e3
SAM4S Series [DATASHEET]
Atmel-11100K-ATARM-SAM4S-Datasheet_09-Jun-15
1216
45.8 48-lead QFN Mechanical Characteristics
Figure 45-10. 48-lead QFN Package Drawing
Table 45-28. Device and 48-lead LQFP Package Maximum Weight
SAM4S 143 mg
Table 45-29. 48-lead QFN Package Characteristics
Moisture Sensitivity Level 3
Table 45-30. 48-lead QFN Package Reference
JEDEC Drawing Reference
JESD97 Classification e3
1217
SAM4S Series [DATASHEET]
Atmel-11100K-ATARM-SAM4S-Datasheet_09-Jun-15
45.9 Soldering Profile
Table 45-31 gives the recommended soldering profile from J-STD-020C.
Note: The package is certi fied to be backward compatible with Pb/Sn soldering profile.
A maximum of three reflow passes is allowed per component.
45.10 Packaging Resources
Land Pattern Definition.
Refer to the following IPC Standards:
IPC-7351A and IPC-782 (Generic Requirements for Surface Mount Design and Land Pattern Standards)
http://landpatterns.ipc.org/default.asp
Atmel Green and RoHS Policy and Package Material Declaration Datasheet available on www.atmel.com
Table 45-31. Soldering Profile
Profile Feature Green Package
Average Ramp-up Rate (217°C to Peak) 3°C/sec. max.
Preheat Temperature 175°C ± 25°C 180 sec. max.
Temperature Maintained Above 217°C 60 sec. to 150 sec.
Time within 5°C of Actual Peak Temperature 20 sec. to 40 sec.
Peak Temperature Range 260°C
Ramp-down Rate 6°C/sec. max.
Time 25°C to Peak Temperature 8 min. max.
SAM4S Series [DATASHEET]
Atmel-11100K-ATARM-SAM4S-Datasheet_09-Jun-15
1218
46. Marking
All devices are marked with the Atmel logo and the ordering code.
Additional marking is as follows:
where
“YY”: manufactory year
“WW”: manufactory week
“V”: revision
“XXXXXXXXX”: lot number
YYWW V
XXXXXXXXX ARM
1219
SAM4S Series [DATASHEET]
Atmel-11100K-ATARM-SAM4S-Datasheet_09-Jun-15
47. Ordering Information
Devices in TFBGA, VFBGA, LQFP and QFN packages can be ordered in trays or in tape and reel. Devices in a
WLCSP package are available in tape and reel only.
Table 47-1 provides ordering codes for tray packing. For tape and reel, append an ‘R’ to the tray ordering code;
e.g., ATSAM4SD32CA-CUR.
Table 47-1. Ordering Codes for SAM4S Devices
Ordering Code MRL Flash
(Kbytes) SRAM
(Kbytes) Package Carrier Type Operating
Temperatu re Range
ATSAM4SD32CA-CU A 2*1024 160 TFBGA100 Tray Industrial
(-40°C to +85°C)
ATSAM4SD32CB-CU B
ATSAM4SD32CA-CFU A 2*1024 160 VFBGA100 Tray Industrial
(-40°C to +85°C)
ATSAM4SD32CB-CFU B
ATSAM4SD32CA-AU A 2*1024 160 LQFP100 Tray Industrial
(-40°C to +85°C)
ATSAM4SD32CB-AU B
ATSAM4SD32CA-AN A 2*1024 160 LQFP100 Tray Industrial
(-40°C to +105°C)
ATSAM4SD32CB-AN B
ATSAM4SD32BA-MU A 2*1024 160 QFN64 Tray Industrial
(-40°C to +85°C)
ATSAM4SD32BB-MU B
ATSAM4SD32BA-AU A 2*1024 160 LQFP64 Tray Industrial
(-40°C to +85°C)
ATSAM4SD32BB-AU B
ATSAM4SD32BA-AN A 2*1024 160 LQFP64 Tray Industrial
(-40°C to +105°C)
ATSAM4SD32BB-AN B
ATSAM4SD32BA-UUR A 2*1024 160 WLCSP64 Tape and reel Industrial
(-40°C to +85°C)
ATSAM4SD32BB-UUR B
ATSAM4SD16CA-CU A 2*512 160 TFBGA100 Tray Industrial
(-40°C to +85°C)
ATSAM4SD16CB-CU B
ATSAM4SD16CA-CFU A 2*512 160 VFBGA100 Tray Industrial
(-40°C to +85°C)
ATSAM4SD16CB-CFU B
ATSAM4SD16CA-AU A 2*512 160 LQFP100 Tray Industrial
(-40°C to +85°C)
ATSAM4SD16CB-AU B
ATSAM4SD16CA-AN A 2*512 160 LQFP100 Tray Industrial
(-40°C to +105°C)
ATSAM4SD16CB-AN B
ATSAM4SD16BA-MU A 2*512 160 QFN64 Tray Industrial
(-40°C to +85°C)
ATSAM4SD16BB-MU B
ATSAM4SD16BA-AU A 2*512 160 LQFP64 Tray Industrial
(-40°C to +85°C)
ATSAM4SD16BB-AU B
ATSAM4SD16BA-AN A 2*512 160 LQFP64 Tray Industrial
(-40°C to +105°C)
ATSAM4SD16BB-AN B
SAM4S Series [DATASHEET]
Atmel-11100K-ATARM-SAM4S-Datasheet_09-Jun-15
1220
ATSAM4SD16BA-UUR A 2*512 160 WLCSP64 Tape and reel Industrial
(-40°C to +85°C)
ATSAM4SD16BB-UUR B
ATSAM4SA16CA-CU A 1024 160 TFBGA100 Tray Industrial
(-40°C to +85°C)
ATSAM4SA16CB-CU B
ATSAM4SA16CA-CFU A 1024 160 VFBGA100 Tray Industrial
(-40°C to +85°C)
ATSAM4SA16CB-CFU B
ATSAM4SA16CA-AU A 1024 160 LQFP100 Tray Industrial
(-40°C to +85°C)
ATSAM4SA16CB-AU B
ATSAM4SA16CA-AN A 1024 160 LQFP100 Tray Industrial
(-40°C to +105°C)
ATSAM4SA16CB-AN B
ATSAM4SA16BA-MU A 1024 160 QFN64 Tray Industrial
(-40°C to +85°C)
ATSAM4SA16BB-MU B
ATSAM4SA16BA-AU A 1024 160 LQFP64 Tray Industrial
(-40°C to +85°C)
ATSAM4SA16BB-AU B
ATSAM4SA16BA-AN A 1024 160 LQFP64 Tray Industrial
(-40°C to +105°C)
ATSAM4SA16BB-AN B
ATSAM4S16CA-CU A 1024 128 TFBGA100 Tray Industrial
(-40°C to +85°C)
ATSAM4S16CB-CU B
ATSAM4S16CA-CFU A 1024 128 VFBGA100 Tray Industrial
(-40°C to +85°C)
ATSAM4S16CB-CFU B
ATSAM4S16CA-AU A 1024 128 LQFP100 Tray Industrial
(-40°C to +85°C)
ATSAM4S16CB-AU B
ATSAM4S16CA-CFN A 1024 128 VFBGA100 Tray Industrial
(-40°C to +105°C)
ATSAM4S16CB-CFN B
ATSAM4S16CA-AN A 1024 128 LQFP100 Tray Industrial
(-40°C to +105°C)
ATSAM4S16CB-AN B
ATSAM4S16BA-MU A 1024 128 QFN64 Tray Industrial
(-40°C to +85°C)
ATSAM4S16BB-MU B
ATSAM4S16BA-AU A 1024 128 LQFP64 Tray Industrial
(-40°C to +85°C)
ATSAM4S16BB-AU B
ATSAM4S16BA-UUR A 1024 128 WLCSP64 Reel Industrial
(-40°C to +85°C)
ATSAM4S16BB-UUR B
ATSAM4S16BA-AN A 1024 128 LQFP64 Tray Industrial
(-40°C to +105°C)
ATSAM4S16BB-AN B
ATSAM4S8CA-CU A 512 128 TFBGA100 Tray Industrial
(-40°C to +85°C)
ATSAM4S8CB-CU B
Table 47-1. Ordering Codes for SAM4S Devices (Con tinued)
Ordering Code MRL Flash
(Kbytes) SRAM
(Kbytes) Package Carrier Type Operating
Temperatu re Range
1221
SAM4S Series [DATASHEET]
Atmel-11100K-ATARM-SAM4S-Datasheet_09-Jun-15
ATSAM4S8CA-CFU A 512 128 VFBGA100 Tray Industrial
(-40°C to +85°C)
ATSAM4S8CB-CFU B
ATSAM4S8CA-AU A 512 128 LQFP100 Tray Industrial
(-40°C to +85°C)
ATSAM4S8CB-AU B
ATSAM4S8CA-CFN A 512 128 VFBGA100 Tray Industrial
(-40°C to +105°C)
ATSAM4S8CB-CFN B
ATSAM4S8CA-AN A 512 128 LQFP100 Tray Industrial
(-40°C to +105°C)
ATSAM4S8CB-AN B
ATSAM4S8BA-MU A 512 128 QFN64 Tray Industrial
(-40°C to +85°C)
ATSAM4S8BB-MU B
ATSAM4S8BA-AU A 512 128 LQFP64 Tray Industrial
(-40°C to +85°C)
ATSAM4S8BB-AU B
ATSAM4S8BA-UUR A 512 128 WLCSP64 Reel Industrial
(-40°C to +85°C)
ATSAM4S8BB-UUR B
ATSAM4S8BA-AN A 512 128 LQFP64 Tray Industrial
(-40°C to +105°C)
ATSAM4S8BB-AN B
ATSAM4S4CA-CU A 256 64 TFBGA100 Tray Industrial
(-40°C to +85°C)
ATSAM4S4CB-CU B
ATSAM4S4CA-CFU A 256 64 VFBGA100 Tray Industrial
(-40°C to +85°C)
ATSAM4S4CB-CFU B
ATSAM4S4CA-AU A 256 64 LQFP100 Tray Industrial
(-40°C to +85°C)
ATSAM4S4CB-AU B
ATSAM4S4CA-AN A 256 64 LQFP100 Tray Industrial
(-40°C to +105°C)
ATSAM4S4CB-AN B
ATSAM4S4BA-MU A 256 64 QFN64 Tray Industrial
(-40°C to +85°C)
ATSAM4S4BB-MU B
ATSAM4S4BA-AU A 256 64 LQFP64 Tray Industrial
(-40°C to +85°C)
ATSAM4S4BB-AU B
ATSAM4S4BA-UUR A 256 64 WLCSP64 Reel Industrial
(-40°C to +85°C)
ATSAM4S4BB-UUR B
ATSAM4S4BA-AN A 256 64 LQFP64 Tray Industrial
(-40°C to +105°C)
ATSAM4S4BB-AN B
ATSAM4S4AA-MU A 256 64 QFN48 Tray Industrial
(-40°C to +85°C)
ATSAM4S4AB-MU B
ATSAM4S4AA-AU A 256 64 LQFP48 Tray Industrial
(-40°C to +85°C)
ATSAM4S4AB-AU B
Table 47-1. Ordering Codes for SAM4S Devices (Con tinued)
Ordering Code MRL Flash
(Kbytes) SRAM
(Kbytes) Package Carrier Type Operating
Temperatu re Range
SAM4S Series [DATASHEET]
Atmel-11100K-ATARM-SAM4S-Datasheet_09-Jun-15
1222
ATSAM4S4AA-AN A 256 64 LQFP48 Tray Industrial
(-40°C to +105°C)
ATSAM4S4AB-AN B
ATSAM4S2CA-CU A 128 64 TFBGA100 Tray Industrial
(-40°C to +85°C)
ATSAM4S2CB-CU B
ATSAM4S2CA-CFU A 128 64 VFBGA100 Tray Industrial
(-40°C to +85°C)
ATSAM4S2CB-CFU B
ATSAM4S2CA-AU A 128 64 LQFP100 Tray Industrial
(-40°C to +85°C)
ATSAM4S2CB-AU B
ATSAM4S2CA-AN A 128 64 LQFP100 Tray Industrial
(-40°C to +105°C)
ATSAM4S2CB-AN B
ATSAM4S2BA-MU A 128 64 QFN64 Tray Industrial
(-40°C to +85°C)
ATSAM4S2BB-MU B
ATSAM4S2BA-AU A 128 64 LQFP64 Tray Industrial
(-40°C to +85°C)
ATSAM4S2BB-AU B
ATSAM4S2BA-UUR A 128 64 WLCSP64 Reel Industrial
(-40°C to +85°C)
ATSAM4S2BB-UUR B
ATSAM4S2BA-AN A 128 64 LQFP64 Tray Industrial
(-40°C to +105°C)
ATSAM4S2BB-AN B
ATSAM4S2AA-MU A 128 64 QFN48 Tray Industrial
(-40°C to +85°C)
ATSAM4S2AB-MU B
ATSAM4S2AA-AU A 128 64 LQFP48 Tray Industrial
(-40°C to +85°C)
ATSAM4S2AB-AU B
ATSAM4S2AA-AN A 128 64 LQFP48 Tray Industrial
(-40°C to +105°C)
ATSAM4S2AB-AN B
Table 47-1. Ordering Codes for SAM4S Devices (Con tinued)
Ordering Code MRL Flash
(Kbytes) SRAM
(Kbytes) Package Carrier Type Operating
Temperatu re Range
1223
SAM4S Series [DATASHEET]
Atmel-11100K-ATARM-SAM4S-Datasheet_09-Jun-15
48. Errata
48.1 Errata SAM4SD32/SD16/SA16/S16/S8 Rev. A Parts
The errata are applicable to the devices in Table 48-1.
48.1.1 Flash Controller (EEFC)
Issue: Flash Buffer Not Cleared
The Write Buffer in the embedded Flash is not cleared after trying to write to a locked region. Therefore, the data
that was previously loaded into the Write Buf fer would remain in the buffer while the next page write com mand
(e.g., WP) is being executed.
Workaround: Do not do partial programming (Fill completely the Write Buffer). Note that this problem occurs
only if the software tries to write into a locked region.
Issue: Code Loop Optimization Cannot Be Disabled
The EFC does not work after the buffer for loop optimization is disabled; in Flash Mode Register (EEFC_FMR),
CLOE = 0.
Workaround: The CLOE bit must be kept at 1.
Issue: Erase Sector Command Cannot Be Performed If a Subsector Is Locked (ONLY in Flash
Sector0)
If one of subsector (Small Sector 0, Small Sector1 and Larger Sector) is locked, the Erase Sector Command (ES)
is not possible on non- locked subsect or s.
Workaround: All the lock bits of the sector0 must be cleared prior to issuing the ES command. After the ES
command has been issued, the first sector lock bits must be reverted to the state before clearing
them.
Table 48-1. Device List for Errata Described in Section 48.1
Device Name Revision Chip ID
SAM4SD32C A 0x29A7_0EE0
SAM4SD32B A 0x2997_0EE0
SAM4SD16C A 0x29A7_0CE0
SAM4SD16B A 0x2997_0CE0
SAM4SA16C A 0x28A7_0CE0
SAM4SA16B A 0x2897_0CE0
SAM4S16C A 0x28AC_0CE0
SAM4S16B A 0x289C_0CE0
SAM4S8C A 0x28AC_0AE0
SAM4S8B A 0x289C_0AE0
SAM4S Series [DATASHEET]
Atmel-11100K-ATARM-SAM4S-Datasheet_09-Jun-15
1224
48.1.2 Flash
Issue: Incorrect Flash Read May Occur Depending on VDDIO Voltage and Flash Wait State
Flash read issues leading to wrong instruction fetch o r incorrect data read may occur under the following operating
conditions:
VDDIO < 2.4V and Flash wait state(1) ≥ 1
If the core clock frequency does not require the use of the Flash wait state (2) (FWS = 0 in EEFC_FMR) or if only
data reads are performed on the Flash (e.g., if the code is running out of SRAM), there are no constraints on
VDDIO voltage. The usable voltage range for VDDIO is defined in Table 44-3 “DC Characteristics”.
Notes: 1. Defined by the FWS field in EEFC_FMR register.
2. See Section 44.12.9 “Embedded Fl ash Characteristics” for the maximum core clock frequency at zero (0) wait
state.
Workaround: Two workarounds are available:
1. Reduce the device speed to decrease the number of wait states to 0.
2. Copy the code from Flash to SRAM at 0 wait states and then run the code out of SRAM.
The issue will be corrected in the next device revision, Marketing Revision Level B (MRL B). Please contact your
local Sales Representative for further details.
Issue: Read Error after a GPNVM or Lock Bit Writing
The sequence below leads to a bad read value.
Fail sequence is:
Read Flash @ address XXX
Programming Flash: Write GPNVM or Lock Bit instructions
Read Flash @ address XXX
Workaround: A dummy read at another address needs to be included i n the sequence.
Sequence is:
Read Flash @ address XXX
Programming Flash: Write GPNVM or Lock Bit instructions
Read Flash @ address YYY (dummy read)
Read Flash @ address XXX
48.1.3 Watchdog
Issue: Watchdog Not Stopped in Wait Mode
When the Watchdog is enabled an d the bit WAITMODE = 1 is used to e nter wait mode, the wa tchdog is not h alted.
If the time spent in Wait Mode is longer than the Watchdog time-out, the device will be reset if Watchdog reset is
enabled.
Workaround: When entering wait mode, the Wait Fo r Event (W FE ) instructio n of the processor Co rtex-M4 mu st
be used with the SLEEPDEEP of the System Control Register (SCB_SCR) of the Cortex-M = 0.
1225
SAM4S Series [DATASHEET]
Atmel-11100K-ATARM-SAM4S-Datasheet_09-Jun-15
48.1.4 Brownout Detector
Issue: Unpredictable Behavior if BOD is Disabled, VDDCORE is Lost and VDDIO is Connected
In active mode or in wait mode, if the Brownout De tector is disabled (SUPC_MR.BODDIS = 1) and power is lost on
VDDCORE while VDDIO is powered, the device might not be properly reset and may behave unpredictably.
Workaround: When the Brownout Detector is disabled in active or in wait mode, VDDCORE always needs to be
powered.
48.1.5 Low-power Mode
Issue: Unpredictable Behavior Whe n Entering Sleep Mode
When entering Sleep mode, if an interrupt occurs during WFI or WFE (PMC_FSMR.LPM = 0) instruction
processing, the ARM core may read an incor rect data , thu s le ading to u npr ed ictabl e beha vio r of the so ftware. This
issue is not present in Wait mode.
Workaround: The following conditions must be met:
1. The interrupt vector table must be located in Flash.
2. The Matrix slave interface for the Flash must be set to 'No default master'. This is done by setting the field
DEFMSTR_TYPE to 0 in the register MATRIX_SCFG. The code example below can be used to program the
NO_DEFAULT_MASTER state:
MATRIX_SCFG[2] = MATRIX_SCFG_SLOT_CYCLE(0xFF) | MATRIX_SCFG_DEFMSTR_TYPE(0x0);
This must be done once in the software before entering Sleep mode.
48.1.6 PIO
Issue: PB4 Input Low-level Voltage Range
The undershoot is limited to -0.1V.
In normal operating conditions, the VIL minimum value on PB4 is limited to 0V.
Workaround: The voltage on PB4 with respect to ground must be in the range
-0.1V to + VDDIO + 0.4V instead of -0.3V to + VDDIO + 0.4V for all other input pins, as shown in
Table 44.1 “Absolute Maximum Ratings”.
The minimum VIL on PB4 must be 0V instead of -0.3V for all other input pins, as shown in Table
44.3 “DC Characteristics”.
SAM4S Series [DATASHEET]
Atmel-11100K-ATARM-SAM4S-Datasheet_09-Jun-15
1226
48.2 Errata SAM4SD32/SD16/SA16/S16/S8 Rev. B Parts
The errata are applicable to the devices in Table 48-1.
48.2.1 Flash Controller (EEFC)
Issue: Flash Buffer Not Cleared
The Write Buffer in the embedded Flash is not cleared after trying to write to a locked region. Therefore, the data
that was previously loaded into the Write Buf fer would remain in the buffer while the next page write com mand
(e.g., WP) is being executed.
Workaround: Do not do partial programming (Fill completely the Write Buffer). Note that this problem occurs
only if the software tries to write into a locked region.
Issue: Code Loop Optimization Cannot Be Disabled
The EFC does not work after the buffer for loop optimization is disabled, in Flash Mode Register (EEFC_FMR)
CLOE = 0.
Workaround: The CLOE bit must be kept at 1.
Issue: Erase Sector Command Cannot Be Performed If a Subsector Is Locked (ONLY in Flash
Sector0)
If one of subsector (Small Sector 0, Small Sector1 and Larger Sector) is locked, the Erase Sector Command (ES)
is not possible on non- locked subsect or s.
Workaround: All the lock bits of the sector0 must be cleared prior to issuing the ES command. After the ES
command has been issued, the first sector lock bits must be reverted to the state before clearing
them.
Table 48-2. Device List for Errata Described in Section 48.1
Device Name Revision Chip ID
SAM4SD32C B 0x29A7_0EE1
SAM4SD32B B 0x2997_0EE1
SAM4SD16C B 0x29A7_0CE1
SAM4SD16B B 0x2997_0CE1
SAM4SA16C B 0x28A7_0CE1
SAM4SA16B B 0x2897_0CE1
SAM4S16C B 0x28AC_0CE1
SAM4S16B B 0x289C_0CE1
SAM4S8C B 0x28AC_0AE1
SAM4S8B B 0x289C_0AE1
1227
SAM4S Series [DATASHEET]
Atmel-11100K-ATARM-SAM4S-Datasheet_09-Jun-15
48.2.2 Flash
Issue: Read Error after a GPNVM or Lock Bit Writing
The sequence below leads to a bad read value.
Fail sequence is:
Read Flash @ address XXX
Programming Flash: Write GPNVM or Lock Bit instructions
Read Flash @ address XXX
Workaround: A dummy read at another address needs to be included i n the sequence.
Sequence is:
Read Flash @ address XXX
Programming Flash: Write GPNVM or Lock Bit instructions
Read Flash @ address YYY (dummy read)
Read Flash @ address XXX
48.2.3 Watchdog
Issue: Watchdog Not Stopped in Wait Mode
When the Watchdog is enabled an d the bit WAITMODE = 1 is used to e nter wait mode, the wa tchdog is not h alted.
If the time spent in Wait Mode is longer than the Watchdog time-out, the device will be reset if Watchdog reset is
enabled.
Workaround: When entering wait mode, the Wait Fo r Event (W FE ) instructio n of the processor Co rtex-M4 mu st
be used with the SLEEPDEEP of the System Control Register (SCB_SCR) of the Cortex-M = 0.
48.2.4 Brownout Detector
Issue: Unpredictable Behavior if BOD is Disabled, VDDCORE is Lost and VDDIO is Connected
In active mode or in wait mode, if the Brownout De tector is disabled (SUPC_MR.BODDIS = 1) and power is lost on
VDDCORE while VDDIO is powered, the device might not be properly reset and may behave unpredictably.
Workaround: When the Brownout Detector is disabled in active or in wait mode, VDDCORE always needs to be
powered.
SAM4S Series [DATASHEET]
Atmel-11100K-ATARM-SAM4S-Datasheet_09-Jun-15
1228
48.2.5 PIO
Issue: PB4 Input Low-level Voltage Range
The undershoot is limited to -0.1V.
In normal operating conditions, the VIL minimum value on PB4 is limited to 0V.
Workaround: The voltage on PB4 with respect to ground must be in the range
-0.1V to + VDDIO + 0.4V instead of -0.3V to + VDDIO + 0.4V for all other input pins, as shown in
Table 44.1 “Absolute Maximum Ratings”.
The minimum VIL on PB4 must be 0V instead of -0.3V for all other input pins, as shown in Table
44.3 “DC Characteristics”.
1229
SAM4S Series [DATASHEET]
Atmel-11100K-ATARM-SAM4S-Datasheet_09-Jun-15
48.3 Errata SAM4S4/S2 Rev. A Parts
The errata are applicable to the devices in Table 48-3.
48.3.1 Flash Controller (EEFC)
Issue: Erase Sector (ES) Command Cannot Be Performed If a Subsector Is Locked (ONLY in Flash
sector 0)
If one of the subsectors
small sector 0
small sector 1
larger sector
is locked within the Flash sector 0, the erase sector (ES) command cannot be processed on non-locked
subsectors. Refer to the Flash overview in Section 8. “Memories”.
Workaround: All the lock bits of the sector 0 must be clea re d prio r to issuing the ES comm a nd . Afte r the ES
command has been issued, the lock bits must be reverted to the state before clearing them.
48.3.2 Flash
Issue: Incorrect Flash Read May Occur Depending on VDDIO Voltage and Flash Wait State
Flash read issues leading to wrong instruction fetch o r incorrect data read may occur under the following operating
conditions:
VDDIO < 2.4V and Flash wait state(1) ≥ 1
If the core clock frequency does not require the use of the Flash wait state(2) (FWS = 0 in EEFC_FMR) or if only
data reads are pe rformed on the Flash (e.g., if the co de is running out of SRAM), there ar e no constraints on
VDDIO voltage. The usable voltage range for VDDIO is defined in Table 44-3 “DC Characteristics”.
Notes: 1. Defined by the FWS field in EEFC_FMR.
2. See Section 44.12.9 “Embedded Fl ash Characteristics” for the maximum core clock frequency at zero (0) wait
state.
Workaround: Two workarounds are available:
1. Reduce the device speed to decrease the number of wait states to 0.
2. Copy the code from Flash to SRAM at 0 wait states and then run the code out of SRAM.
The issue will be corrected in the next device revision, Marketing Revision Level B (MRL B). Please contact your
local Sales Representative for further details.
Table 48-3. Device List for Errata Described in Section 48.3
Device Name Revision Chip ID
SAM4S4C A 0x28AB_09E0
SAM4S4B A 0x289B_09E0
SAM4S4A A 0x288B_09E0
SAM4S2C A 0x28AB_07E0
SAM4S2B A 0x289B_07E0
SAM4S2A A 0x288B_07E0
SAM4S Series [DATASHEET]
Atmel-11100K-ATARM-SAM4S-Datasheet_09-Jun-15
1230
48.3.3 Brownout Detector
Issue: Unpredictable Behavior if BOD is Disabled, VDDCORE is Lost and VDDIO is Connected
In active mode or in wait mode, if the Brownout De tector is disabled (SUPC_MR.BODDIS = 1) and power is lost on
VDDCORE while VDDIO is powered, the device might not be properly reset and may behave unpredictably.
Workaround: When the Brownout Detector is disabled in active or in wait mode, VDDCORE always needs to be
powered.
48.3.4 Low-power Mode
Issue: Unpredictable Behavior Whe n Entering Sleep Mode
When entering Sleep mode, if an interrupt occurs during WFI or WFE (PMC_FSMR.LPM = 0) instruction
processing, the ARM core may read an incor rect data , thu s le ading to u npr ed ictabl e beha vio r of the so ftware. This
issue is not present in Wait mode.
Workaround: The following conditions must be met:
1. The interrupt vector table must be located in Flash.
2. The Matrix slave interface for the Flash must be set to ‘No default master’. This is done by setting the field
DEFMSTR_TYPE to 0 in the register MATRIX_SCFG. The code example below can be used to program the
NO_DEFAULT_MASTER state:
MATRIX_SCFG[2] = MATRIX_SCFG_SLOT_CYCLE(0xFF) | MATRIX_SCFG_DEFMSTR_TYPE(0x0);
This must be done once in the software before entering Sleep mode.
48.3.5 PIO
Issue: PB4 Input Low-level Voltage Range
The undershoot is limited to -0.1V.
In normal operating conditions, the VIL minimum value on PB4 is limited to 0V.
Workaround: The voltage on PB4 with respect to ground must be in the range
-0.1V to + VDDIO + 0.4V instead of -0.3V to + VDDIO + 0.4V for all other input pins, as shown in
Table 44.1 “Absolute Maximum Ratings”.
The minimum VIL on PB4 must be 0V instead of -0.3V for all other input pins, as shown in Table
44.3 “DC Characteristics”.
1231
SAM4S Series [DATASHEET]
Atmel-11100K-ATARM-SAM4S-Datasheet_09-Jun-15
48.4 Errata SAM4S4/S2 Rev. B Parts
The errata are applicable to the devices in Table 48-4.
48.4.1 Flash Controller (EEFC)
Issue: Erase Sector (ES) Command Cannot Be Performed If a Subsector Is Locked (ONLY in Flash
sector 0)
If one of the subsectors
small sector 0
small sector 1
larger sector
is locked within the Flash sector 0, the erase sector (ES) command cannot be processed on non-locked
subsectors. Refer to the Flash overview in Section 8. “Memories”.
Workaround: All the lock bits of the sector 0 must be clea re d prio r to issuing the ES comm a nd . Afte r the ES
command has been issued, the lock bits must be reverted to the state before clearing them.
48.4.2 Brownout Detector
Issue: Unpredictable Behavior if BOD is Disabled, VDDCORE is Lost and VDDIO is Connected
In active mode or in wait mode, if the Brownout De tector is disabled (SUPC_MR.BODDIS = 1) and power is lost on
VDDCORE while VDDIO is powered, the device might not be properly reset and may behave unpredictably.
Workaround: When the Brownout Detector is disabled in active or in wait mode, VDDCORE always needs to be
powered.
Table 48-4. Device List for Errata Described in Section 48.4
Device Name Revision Chip ID
SAM4S4C B 0x28AB_09E1
SAM4S4B B 0x289B_09E1
SAM4S4A B 0x288B_09E1
SAM4S2C B 0x28AB_07E1
SAM4S2B B 0x289B_07E1
SAM4S2A B 0x288B_07E1
SAM4S Series [DATASHEET]
Atmel-11100K-ATARM-SAM4S-Datasheet_09-Jun-15
1232
48.4.3 PIO
Issue: PB4 Input Low-level Voltage Range
The undershoot is limited to -0.1V.
In normal operating conditions, the VIL minimum value on PB4 is limited to 0V.
Workaround: The voltage on PB4 with respect to ground must be in the range
-0.1V to + VDDIO + 0.4V instead of -0.3V to + VDDIO + 0.4V for all other input pins, as shown in
Table 44.1 “Absolute Maximum Ratings”.
The minimum VIL on PB4 must be 0V instead of -0.3V for all other input pins, as shown in Table
44.3 “DC Characteristics”.
1233
SAM4S Series [DATASHEET]
Atmel-11100K-ATARM-SAM4S-Datasheet_09-Jun-15
49. Revision History
In the tables that follow, the most recent version of the document appears first.
Table 49-1 . SAM4S Datasheet Rev. 11100K Revision History
Doc. Date Changes
09-Jun-15
“Features”: update d “Memories” section.
Added section “Safety Features Highlight”.
Section 8., “Memories”
Added Section 8.1.3.4 “Error Code Correction (ECC)”.
Section 44., “Electrical Characte ristics”
Added Table 44-24, “SAM4SD32/SA16/SD16 Typical Active Power Consumption with VDDCORE@ 1.2V running
from Flash Memory (AMP2) or SRAM”.
Table 49-2 . SAM4S Datasheet Rev. 11100J Revision History
Doc. Date Changes
28-May-15
“Features”: updated “System” and “Periph erals” sections
Section 2., “Block Diagram”
Updated Figures
Section 4., “Package and Pinout”
Modified AD13 and AD14 position in Table 4-2 “SAM4SD32/SD16/SA16/S16/S8/S4/S2 100-ball TFBGA Pinout” and
Table 4-3 “SAM4SD32/SD16/SA16/S16/S8/S4/S2 100-ball VFBGA Pinout”
Section 44., “Electrical Characte ristics”
Updated Table 44-41, “ADC Timing Characteristics”
Table 44-74, “AC Flash Characteristics”: added one “Endurance” value
Section 48., “Errata”
Section 48.1.5, “Low-power Mode” and Section 48.3.4, “Low-power Mode”: modified Workaround 2 (code example)
SAM4S Series [DATASHEET]
Atmel-11100K-ATARM-SAM4S-Datasheet_09-Jun-15
1234
Table 49-3 . SAM4S Datasheet Rev. 11100I Revision Histo ry
Doc. Date Changes
03-Apr-15
Introduction of four new devices: ATSAM4SD32BA-UUR, ATSAM4SD32BB-UUR, ATSAM4SD16BA-U UR and
ATSAM4SD16BB-UUR
Modified “Description”, Section 2. “Block Diagram”, and Section 6.5, “ERASE Pin”
Updated Table 9-1 "Real-time Event Mappin g List"
Added footnotes in Table 11-2 "Multiplexing on PIO Controller A (PIOA)", Table 11-3 "Multiplexing on PIO Controller B
(PIOB)" and Table 11-4 "Multiplexing on PIO Controller C (PIOC)"
Deleted reset value from individual register description sectio ns (reset values are found in “register mapping” sections)
Section 12., “ARM Cortex-M4 Processor”
Figure 12-1 “Typical Cortex-M4 Implementation”; replaced “Cortex-M4” with “Cortex-M4F”
Table 12-11 “Faults”: note 1 now ap plied to IACCVIOL.
Section 12.9.1.13 “Configurable Fault Status Register”: removed ‘MLSPERR’ bit
Table 12-34 ”System Timer (SYST) Register Mapping”: corrected SYST_CSR reset value
Section 13., “Debug and Test Features”
Modified Sectio n 13.5.2 “Debug Architecture”
Section 14., “Reset Controller (RSTC)”
Figure 14-3 “General Reset State”: corrected signal name to vddio_nreset
Section 14.4, “Functional Description ”: deleted subsection “Brownout Manager” and redundant subsection “Reset
Controller Status Register” (register is described in Section 14.5 .2, “Reset Controller Status Register”)
Updated Section 14.4.1 , “Reset Controller Overview”
Section 14.4.3, “Reset States”: organized subsections in order of reset state priority
Section 14.4.4, “Reset State Priorities”: reworded first paragraph
Section 14.5.2, “Reset Controller Status Register”: updated bit and field descriptions
Section 15., “Real-time Timer (RTT)”
Updated Figure 15-2 “RTT Counting” and Section 15.4 “Functional Description”
Section 15.5.1 “Real-time Timer Mode Register”: updated RTPRES field description
Modified ALMV description in Section 15.5.2 “Real-time Timer Alarm Register”
Section 15.5.2 “Real-time Timer Alarm Register”: added “(cleared on read)” to each bit description
Added notes in Section 15.5.3 “Real-time Timer Value Register”
Section 16., “Real-time Clock (RTC)”
Replaced “APB” with “System Bus” in Section 16.3, “Block Diagram”
Updated “Section 16.1, “Description” and Section 16.5 , “Functional Description” (removed references to the 20th
century)
Section 16.5.5, “RTC Internal Free Ru nning Counter Error Checking”: replaced “RTC status clear control register” with
“Status Clear Command Register”
Updated Section 16.5.7 , “RTC Accurate Clock Calibration” (added figures and descriptions)
Updated Section 16.6.2 , “RTC Mode Register” and Section 16.6.11, “RTC Inter r up t Ma sk Reg ist er”
Section 17., “Watchdog Timer (WDT)”
In Figure 17-2 “Watchdog Behavior”, “WDT_CR = WDRSTT” replaced with “WDT _ CR.WDRSTT=1”
Updated Section 17.5.3 “Watch dog Timer Status Register”
1235
SAM4S Series [DATASHEET]
Atmel-11100K-ATARM-SAM4S-Datasheet_09-Jun-15
03-Apr-15
Section 18., “Supply Controll er (S UPC) ”
Updated Figure 18-1 “Supply Controller Block Diagram”.
Section 18.4.2, “Slow Clock Genera tor”: modified last paragraph with information on entering Bypass mode.
Modfied Section 18.4.7.1, “Wake-up Inputs”, Section 18.5.5, “Supply Controller Mode Register”, Section 18.5.7, “Supply
Controller Wake-up In puts Register” and Section 18.5.8, “Supply Controller Status Register”
Section 18.4.7.2, “Low-p ower Tamper Detection and Anti-Tampering”: corrected ‘...LPDBCCLR bit must be set in
SUPC_MR’ to ‘...LPDBCCLR bit must be set in SUPC_WUMR’Updated Figure 18-4 “Wake-up Sources”
Section 18.5.2, “Supply Controlle r (SUPC) User Inte rface”: corrected reset value for SUPC_MR.
Section 19., “General Purpose Backup Registers (GPBR)”
Modified Secti on 19.1, “Description” and Section 19.2, “Embedded Characteristics”
Table 19-1 “Reg i ste r M ap p i ng ”: added reset value 0x00000000 for all registers SYS_GPBRx
Section 19.3.1, “General Purpose Backup Register x”: inserted sentence “These registers are reset at first power-up and
on each loss of VVDIO”
Section 20., “Enhanced Embedded Flash Contro ller (EEFC)”.
Updated Section 20.2, “Embedded Characteristics”
Added Figure 20-1 Flash Memory Areas
Section 20.3.2, “Interrupt Sources”: changed last sentence
Section 20.4.1, “Embedded Flash Organization”: corrected instance of command name “Get descriptor” to “Get Flash
Descriptor”
Figure 20-7 Command State Chart: replaced two instances of “MC_FSR” with “EEFC_FSR”
Modified Section 20.4.3.2, “Write Commands”, Section 20.4.3.3, “Erase Commands”, Section 20.4.3.8, “Unique Identifier
Area” and Section 20.4.3.9, “User Signature Area”
Section 20.5, “Enhanced Embedded F lash Controller (EEFC) User Interface”: deleted address offsets from individual
register descriptions (offsets are provided in Section 20-6, “Register Mapping”)
Modified Secti on 20.5.1, “EEFC Flash Mode Register”, Section 20 .5.2, “EEFC Flash Command Register” and Section
20.5.3, “EEFC Flash Status Registe r ”: add ed new field ‘ZERO’ (register bits 26:25)
Updated Section 20-6, “Register Mapping”
Section 21., “Fast Flash Programming Interface (F FPI)”
Section 21-1, “16-bit Parallel Programming Interface”: renamed figure
Section 22., “Cortex-M Cache Controller (CMCC)”
Section 22.4.3, “Cache Performance Monitoring”: corrected “MODE field of the CMCC_CF G register” to “MODE field of
the CMCC_MCFG register”
Table 22-1 "Re gi s t er Ma pp i ng": remove d CMCC_CTRL reset value for this write-only register; replaced “Cache ...” with
“Cache Controller ...” in “Register” colu mn contents
Updated Section 22.5.1, “Cache Controller Type Register”
Updated bi t descriptions i n Section 22.5.3, “Cache Controller Control Register”, Section 22.5.4, “Cache Controller Status
Register”, Section 22.5.5, “Cache Controller Maintenance Register 0”, Section 22.5.8, “Cache Controller Monitor Enable
Register” and Section 22.5.9, “Cache Controller Monitor Con tro l Register”.
Section 22.5.7, “Cache Controller Monitor Configuration Register”: changed access from Write-only to Read/Write.
Section 22.5.8, “Cache Controller Monitor Enable Register”: removed reset value from several write-only registers
(reset values are found in Table 22-1 "Register Mapping") and changed access fro m Write-only to Read/Write.
Table 49-3 . SAM4S Datasheet Rev. 11100I Revision Histo ry (Con tinued)
Doc. Date Changes
SAM4S Series [DATASHEET]
Atmel-11100K-ATARM-SAM4S-Datasheet_09-Jun-15
1236
03-Apr-15
Section 23., “Cyclic Redundancy Check Calculation Unit (CRCCU)”
Modified Secti on 23.1, “Description” and Section 23.2, “Embedded Characteristics”
Updated Figure 23-1, “Block Diagram”Section 23.5.2, “CRC Calculation Unit Operation”: reworded text describing how to
start the CRCCU
Table 23-3 “Reg i ste r M ap p i ng ”: deleted reset value 0x00000000 from all write-only registers
Section 23.6, “Transfer Contro l Registers Memory Mapping”: ad ded reset values to Table 23-2 “Transfer Control
Register Memory Mapping”
Section 23.7, “Cyclic Redundancy Check Calculation Unit (CRCCU) User Interface”:
Modified Secti on 23.7.10, “CRCCU Mode Register” and Section 23.7.11, “CRCCU Status Register”
Section 26., “Static Memory Controller (SMC)”
Added Latch Enables for NAND Flash in Table 26-1 “I/O Line Description”.
Updated Section 26.9.5, “Register Write Protection” and added information on write protection to Section 26.16.1, “SMC
Setup Register”, Section 26.16.2, “SMC Pulse Register”, Section 26.16 .3, “SMC Cycle Register” and Section 26.16.4,
“SMC MODE Register”.
Updated Section 26.16.8, “SMC Write Pro tection Mode Register”, Section 26.16.9, “SMC Write Protection Status
Register”and Section 26.10, “Scrambling/Unscrambling Function”.
Section 27., “Peripheral DMA Controller (PDC)”
Added Section 27.3, “Peripheral DMA Controller Connections”
Table 27-2 "Register Mapping": removed reset value from Transfer Control Register / PERIPH_PTCR (register access is
write-only)
Modified Secti on 27.6.10, “Transfer Status Register”
Section 28., “Clock Generator”
Section 28.2, “Embedded Characteristics” : removed bullet “Write Protected Registers”.
Section 28.4.2, “Slow Clock Crystal Oscillator”: deleted redundant content from end of section; appended “OSCBYPASS
bit of the Supply Controller Mode Register (SUPC_MR) needs to be set at 1” to read “OSCBYPASS bit of the Supply
Controller Mode Register (SUPC_MR) needs to be set at 1 prior to writing a 1 in bit XTALSEL”.
Added Section 28.5.5, “Bypassing the Main Crystal Oscillator”.
Updated Section 28.6.1 , “Divider and Phase Lock Loop Programming”.
Section 29., “Power Mana ge me nt Co ntro lle r (PMC) ”
Updated Section 29.2, “Embedded Characteristics” and Sectio n 29.7, “USB Clock Con troller”:
Modified Secti on 29.11, “Fast Startup”
Table 29-3 "Re gi s t er Ma pp i ng": changed PMC_SR reset value to 0x0003_0008 (was 0x0001_0008)
Modified Secti on 29.17.7, “PMC Clock Generator Main Oscillator Register”, Section 29.17.8, “PMC Clock Generator
Main Clock Frequency Register”, Section 29.17.9, “PMC Clock Generator PLLA Register” and Section 29.17.10, “PMC
Clock Generator PLLB Register”
Section 31., “Parallel Input/Output Controller (PIO)”
Replaced all instances of “PIO clock” and “PIO controller clock” with “peripheral clock”
Renamed “MCK” or “master clock” to “Peripheral clock” as needed
Section 31.2, “Embedded Characteristics”: repla ced bullet “Write Protect Registers” with “Register Write Protection”
Updated Figure 31-2, “I/O Line Control Logic” and Figure 31-5, “Input Debouncing Filter Timing”
Table 49-3 . SAM4S Datasheet Rev. 11100I Revision Histo ry (Con tinued)
Doc. Date Changes
1237
SAM4S Series [DATASHEET]
Atmel-11100K-ATARM-SAM4S-Datasheet_09-Jun-15
03-Apr-15
Updated Section 31.5.1 , “Pull-up and Pull-down Resistor Contro l” and Section 31.5 .3, “Peripheral A or B or C or D
Selection”
Section 31.5.10, “Input Edge/L evel Interrupt”: edited, reorganized and reformatted example of interrupt generation
(migrated configuration subsections into Table 31-3 "Configuration for Example Interrupt Generation")
Moved Section 31.5.14, “I/O Lines Programming Example” to appear before Section 31.5.15, “Register Write Protection”
Section 31.6.38, “PIO Additional Interrupt Modes Mask Register”: modified P0–P31 bit description
Replaced instances of “div_slclk” with “div_slck”; replaced instances of “slow_clock” with “slck”
Added bit configuration value s in Section 31.6.50, “PIO Parallel Capture Interrupt Enable Register”, Section 31.6.5 1 ,
“PIO Parallel Capture Interrupt Disable Register” and Section 31.6.52, “PIO Parallel Capture Interrupt Mask Register”
Section 32., “Synchronous Serial Controller (SSC)”
Renamed “Master Clock” or “MCK” to “peripheral clock”
Updated Figure 32-1 ”Block Diagram” and Figure 32-5 ”Time Slot Application Block Diagram”, Figure 32-15 ”Receive
Compare Modes”
Modified Secti on 32.9 “Synchronous Serial Controller (SSC) User Interface”, Section 32.9.17 “SSC Write Protec tion
Mode Register”, Section 32.9.18 “SSC Write Protection Status Register”, Section 32.9.6 “SSC Transmit Frame Mode
Register”
Replaced “16” with “256” in Section 32 .8.5.1 “Frame Sync Data”, Section 32.8.6.1 “Compare Functions” and
Table 32-4 ”Data Frame Registers”
Section 33., “Serial Peripheral Interface (SPI)”
Updated Section 33.3 “Block Dia gram”fModified Section 33.7.3.2, “Master Mode Flow Diagram”: replaced instance of
“Peripheral Data Controller” with “PDC”
Modified Secti on 33.7.3 “Master Mode Operations”, Section 33.8.1 “SPI Control Register”, Section 33.8.2 “SPI Mode
Register”, Section 33.8.5 “SPI Status Register”, Section 33.8.9 “SPI Chip Select Register” and Section “Transfer Size”
Section 33.7.1 “Modes of Operation”: updated text relating to Slave mode
Modified last paragraph in Section 33.7.3.5 “Peripheral Selection” and Section 33.7.3.8 “Peripheral Deselection without
PDC”
Section 34., “Two-wire Interface (TWI)”
Reformatted graphics for improved readabili ty
Updated Section 34.1, “Descriptio n”, Table 34-1 ”Atmel TWI Compatibility with I2C Standard”, Figure 34-1 Block
Diagram and Figure 34-9 Master Read with Multiple Data Bytes
Section 34.7.3.3, “Programming Master Mode”: added note to end of section “Data Transmit with the PDC” and “Data
Receive with the PDC”: updated step 2
Replaced instances of “shift register” with “internal shifter”
Section 34.8.5, “TWI Clock Waveform Generator Register”: replaced tmck with tperipheral clock in CLDIV and CHDIV
field descripti o n
Table 34-7 ”Register Mapping”: replaced TWI_THR reset value “0x00000000” with “–”
In register description sections: removed reset values from write-only registers
Moved section “Master Mode” into Section 34.2, “Embedded Characteristics”
Replaced Section 6. “Application Block Diagram” with updated Section 34.5, “I/O Lines Description”
Moved section “Slave Mode” into Section 34.7, “Functional Description”
Updated ”Clock Synchronization in Write Mode”
Section 34.7.3.3, “Programming Master Mode”: replaced all occurrences of "TWIHS_" with "T WI_".
Table 49-3 . SAM4S Datasheet Rev. 11100I Revision Histo ry (Con tinued)
Doc. Date Changes
SAM4S Series [DATASHEET]
Atmel-11100K-ATARM-SAM4S-Datasheet_09-Jun-15
1238
03-Apr-15
Section 34.8, “Two-wire Interface (TWI) User Interface”:
- removed line “Reset:” from above all register tables; redundant with T able 34-7 ”Register Mapping”.
- replaced instance of acronym “TWI2” with “TWI” in section title
Figure 34-4 Master Mode Typical Application Block Diagram: renamed lines from host with SDA and SCL; placed TW D
and TWCK in host block
Updated Section 34.7.3.4, “Master Transmitter Mode”, Section 34.7.3.5 “Master Receiver Mode”, Figure 34-23 Slave
Mode Typical Application Block Diagram:, Figure 34-24 Read Access Ordered by a Master, Figure 34-25 Write Access
Ordered by a Master, Figure 34-26 Master Performs a General Call, Figure 34-28 Clock Synchronization in Write Mode,
Figure 34-31 Read Write Flowchart in Slave Mode, Section 34.8.1, “TWI Con trol Register”, Section 34.8.5, “TWI Clock
Waveform Generator Register” and Section 34.8.6, “TWI Sta tus Register”
Section 35., “Universal Asynchronous Receiver Transmitter (UART)”
Figure 35-1 UART Block Diagram: changed ‘MCK’ to ‘peripheral clock’; added ‘bus clock’ to diagram.
In diagrams and equations: changed ‘MCK’ to ‘peripheral clock’
Figure 35-2 Baud Rate Generator: removed ‘(PMC)’ from figure.
Section 35.5.1, “Baud Rate Generator”: deleted equation for Baud Rate calculation. Now in Section 35.6.9, “UART Baud
Rate Generator Register”.
Section 35.5.2.4, “Receiver Overrun”: replaced “(or the Peripheral Data Controller or DMA Controller)” with “(or the
PDC)”
Section 35.5.4, “Peripheral DMA Controll er (PDC)”: repla ced “peripheral data controller” with “PDC”
Section 35.6.6, “UART Status Register”: replaced “Peripheral Data Controller” with “PDC” in ENDRX and ENDTX bit
descriptions
Section 35.6.9, “UART Baud Rate Generator Register”: added equation to CD bit description.
Section 36., “Universal Synchronous Asynchronous Receiver Transceiver (USART)”
Replaced all references to ‘MCK’ with ’peripheral clock’
Removed section “Application Block Diagram”
Modified Fi gure 36-1, “USART Block Diagram”, Figure 36-3, “Fractional Baud Rate Generator” and Figure 36-36,
“Example of RTS Drive with Timeguard”
Updated Section 36.2, “Embedded Characteristics”
Modified Ta ble 36-15 “Register Mapping”
Updated Table 36-7 “Possible Values for the Fi/Di Ratio”
Modified Secti on 36.5.3, “Interrupt Sources” and Section 36.6.1, “Baud Rate Generator”
Removed all references to bit RXIDLEV
Replaced bit ITERATION with bit ITER (US_CSR register)
Section 36.6.1.3, “Baud Rate in Synchronous Mode or SPI Mode”: replaced “CLK0” with “CLKO”
Modified Secti on 36.6.3.8 “Parity”, Section 36.6.3.3 “Asynchronous Receiver” Section 36.6.3.8 “Par it y” , ”Transmit
Character Repetition” and ”Disable Successive Receive NACK”
Modified Secti on 36.6.10, “Register Write Protection”, Section 36.7.1, “USART Control Register”, Section 36.7.3,
“USART Mode Register” , , Section 36.7.5, “USART Interrupt Enable Register”, Section 36.7.6, “USART Interrupt Enable
Register (SPI_MODE)”, Section 36.7.7, “USART Interrupt Disable Register”, Section 36.7.8, “USART Interrupt Disable
Register (SPI_MODE)”, Section 36.7.9, “USART Interrupt Mask Register”, Section 36.7.10, “USART Interrupt Mask
Register (SPI_MODE)”, Section 36.7.11, “USART Channel Status Register”, Section 36.7.12, “USART Cha nnel Status
Register (SPI_MODE)”, Section 36.7.15, “USART Baud Rate Generator Register”, Section 36.7.16, “USART Receiver
Time-out Register”, Section 36.7.17, “USART Transmitter Timeguard Register” and Section 36.7.21, “USART
Manchester Configuration Register”
Table 49-3 . SAM4S Datasheet Rev. 11100I Revision Histo ry (Con tinued)
Doc. Date Changes
1239
SAM4S Series [DATASHEET]
Atmel-11100K-ATARM-SAM4S-Datasheet_09-Jun-15
03-Apr-15
Section 37., “Timer Counter (TC)”
“Master clock” or “MCK” replaced with “peripheral clock”
Replaced all occurrences of ‘quadrature de coder logic’ with ‘quadrature decoder’ or ‘QDEC’
Modified Secti on 37.1, “Description”
Modified Secti on 37.2, “Embedded Characteristics”
Modified Secti on 37.5.2, “Power Management” and Section 37.5.3, “Interrupt Sources”
Section 37.6.14.2, “Input Pre-processing”: deleted sentence “Filters can be disabled using the FILTER bit in the
TC_BMR”
Updated Figure 37-16, “Input Stage”
Section 37.6.14, “Quadrature Decoder”: removed subsection “Mis sing Pulse Detection and Auto-correction”
Modified Secti on 37.6.14.4, “Position and Rotation Measurement” and Section 37.6.1 4.5, “Speed Measurement”
Updated Section 37.6.1 7, “Register Write Protection”
Section 37.7.2, “TC Ch annel Mode Register: Capture Mode”: in ‘Name’ line, replaced “(WAVE = 0)” with
“(CAPTURE_MODE)”
Section 37.7.3, “TC Ch annel Mode Register: Waveform Mode”: in ‘Name’ line, replaced “(WAVE = 1)” with
“(WAVEFORM_MODE)”
Updated Section 37.7.5 , “TC Counter Value Register”, Section 37.7.6 “TC Register A”, Section 37.7.7 “TC Register B” ,
Section 37.7.8 “TC Register C”, Section 37.7.9 “TC Statu s Regi st er” and , Section 37.7.14, “TC Block Mode
Register”Section 37.7.18, “TC QDEC Interrupt Status Registe r” and Section 37.7.20, “TC Write Protection Mode
Register”
Section 38., “High Speed Multimedia Card Interface (HSMCI)”
Section 38.1, “Description”: removed sentence “Only one slot can be selected at a time (slots are multiplexed)”
Added Section 38.14.19, “HSMCI FIFOx Memory Aperture”
Section 39., “Pulse Width Modulation Controller (PWM)”
Updated Section 39.2, “Embedded Characteristics”
Section 39.6.2.2, “Comparator”: Corrected the PWM waveform period formulas.
Updated Table 39-4 “Fault Inputs” and Figure 39-5. “Waveform Prope rties”.
Replaced “Master Clock (MCK)”, “MCK” or “master clock” with “peripheral clock”;
Updated Section 39.5.2 , “Power Management” and Section 39.5.3, “Interrupt Sources”
Corrected register name PWM_CPRx to PWM_CPRDx
Section 39.6.2.7, “Synchrono us Channels”: corre c ted paragraph beginning with‘If a channel x is defined as a
synchronous channel’.
Updated Table 39-6 “Register Mapping”
Updated Section 39.7.2 3, “PWM Fault Mode Register”, Section 39.7.24, “PWM Fault Status Register”, Section 39.7.25,
“PWM Fault Clear Register”, Section 39.7.27, “PWM Fault Pr otection Enable Register”
Section 39.7.30, “PWM Write Protection Control Register” and Section 39.7.31, “PWM Write Protection Status Register”:
removed reset values.
Changed CPRE bit description in Section 39.7.36, “PWM Channel Mode Register”.
Added Table 39-1 7 “Event Lin e Generation Waveform (Example)”
Section 40., “USB Device Port (UDP)”
Table 40-6, Register Mapping: modified footnote No. 1.
Section 40.7.4, “UDP In terrupt Enable Register”: modified WAKEUP bit description
“Using Endpoints With Ping-pong Attributes”: Replaced Bank 0 with Bank 1 in step 12
Table 49-3 . SAM4S Datasheet Rev. 11100I Revision Histo ry (Con tinued)
Doc. Date Changes
SAM4S Series [DATASHEET]
Atmel-11100K-ATARM-SAM4S-Datasheet_09-Jun-15
1240
03-Apr-15
Section 41., “Analog Comparator Controller (ACC)”
Added Table 41-1 "List of External Analog Data Inputs"
Changed all occurrences of ‘MCK’ to ‘peripheral clock’.
Updated Table 41-2 "ACC Pi n List"
Updated Figure 41-1, “Analog Comparator Controller Block Diagram”
Section 41.7.2, “ACC Mo de Register”: replaced two instances of “CF” with “C E” in SELFS bit description
Section 41.7.6, “ACC Interrupt Status Register”: added (cleared on read) to CE bit description
Section 42., “Analog-to-Digital Converter (ADC)”
Corrected ADC_SR to ADC_ISR in Section 42.6.5, “Conversion Results”.
Figure 42-1 “Analog-to-Digital Converter Block Diagram”: Added bus clock and added ADCClock output from Control
Logic block
Revised Secti on 42.6.1, “Analog-to-Digital Conversion”
Added Section 42.6.2, “ADC Clock”
Section 42.6.3, “ADC Reference Volta ge”: changed title (was “Conversion Reference”)
Modified Fi gure 42-4 “EOCx and DRDY Flag Behavior” and Figure 42-5 “EOCx, OVREx and GOVREx Flag Behavior”
Modified warning bel ow Figure 42-5 “EOCx, OVREx and GOVREx Flag Behavior”.
Section 42.6.8, “Compa rison Window”: Removed paragraph on LOWRES bit use.
Updated Section 42.6 .9, “Differential Inputs”
Modified Ta ble 42-5 “Gain of the Sample and Hold Unit” and Table 42-6 “Offset of the Sample and Hold Unit ”.
Section 42.6.10, “Input Gain and Offset”: all references to "OFFSET" bit changed to OFFx.
Added Figure 42-8 “Buffer Structure”.
Modified Section 42.7.2, “ADC Mode Register”, Section 42.7.6, “ADC Channel Disable Register”, Section 42.7.12, “ADC
Interrupt Status Register”, Section 42.7.14, “ADC Exten ded Mode Register”, Section 42.7.16, “ADC Channel Gain
Register”
Replaced references to vrefin by VADVREF in text and figures.
Section 42.6.12 “Automatic Calibration”: Removed sentence on ADC running mode.
Replaced instances of “ADCClock” with “ADC clock” or acronym “ADCCLK” th roughout
Section 43., “Digital-to-Analog Converter Controller (DACC)”
MCK replaced with Peripheral clock
Updated Section 43.2, “Embedded Characteristics”
Updated Figure 43-1 ”DACC Block Diagram”
Section 43.6.6, “DACC Timings”: replaced two instances of “DACC clock periods” with “peripheral clock periods”
Table 43-3 ”Register Mapping”:
- Removed reset value from write-only register DACC_CDR
- Displayed offset ranges 0x34–0x90 and 0x98–0xE0 as “Reserved”
Modified Secti on 43.7.2, “DACC Mode Register”
Removed references to Sleep mode and refresh period
Table 49-3 . SAM4S Datasheet Rev. 11100I Revision Histo ry (Con tinued)
Doc. Date Changes
1241
SAM4S Series [DATASHEET]
Atmel-11100K-ATARM-SAM4S-Datasheet_09-Jun-15
03-Apr-15
Section 44., “Electrical Characteristics”:
Updated Table 44-27, “4/8/12 MHz RC Oscillators Characteristics”
Updated parameter definition for Rpara(standby) and Cpara(standby) in Table 44-33, “XIN Clock Electrical Characteristic s (In
Bypass Mode)”
Updated SSC4 and SSC7 values and removed Note 1 in Table 44-66, “SSC Timings”
Removed footnotes from Table 44-31, “3 to 20 MHz Crystal Oscillator Characteristics”
Updated tTRACKTIM value in Table 44-41, “ADC Timing Characteristics”
Replaced tof symbol with tfo in Table 44-72, “T wo-wire Serial Bus Requirements”
Section 45., “Mechanical Characteristics”
Updated Section 45.6, “64-ball WLCSP Mechanical Characteristics”
Section 48., “Errata”
Added limitation on PB4 Input Voltage Range on Rev. A and Rev. B Parts (Section 48.1.6, “PIO”, Section 48.2.5, “PIO”,
Section 48.3.5, “PIO” and Section 48.4.3, “PIO”)
Table 49-3 . SAM4S Datasheet Rev. 11100I Revision Histo ry (Con tinued)
Doc. Date Changes
SAM4S Series [DATASHEET]
Atmel-11100K-ATARM-SAM4S-Datasheet_09-Jun-15
1242
Table 49-4 . SAM4S Datasheet Rev. 11100H Revision History
Doc. Date Changes
08-Jan-15
Section 30. “Chip Identifier (CHIPID)”
Table 30-1 ”SAM4S Chip ID Registers”: updated with Rev B values
Section 30.3.1 “Chip ID Register”:
- field ”EPROC: added new row with value 0, name SAMx7, description Cortex-M7
- field ”NVPSIZ: changed name and description for value 8
- field ”SRAMSIZ: changed name and description for value 2
Section 30.3.2 “Chip ID Extension Register”: in EXID field description , replaced "bit" with "field"
Section 44. “Electrical Characteristics”:
Updated and harmonized parameter symbols throughout
Table 44-3 ”DC Characteristics”: updated footnotes
Table 44-4 ”1.2V Voltage Regulator Characteristics”: replac ed tw o fo ot notes with single footnote fo r VDDIN conditions;
deleted “Cf. External Capacitor Requirements” from CDIN and CDOUT conditions
Table 44-5 ”Core Power Supply Brownout Detector Characteristics”: added parameter “Reset Period”
Table 44-8 ”Zero-Power-on Reset Char acteristics”: modified parameter name “Reset Time-out Period” to “R eset Period”
Section 44.4.2.1 “Sleep Mode”: deleted sentence “Table 44-14 shows the current consumption in typical conditions”;
corrected cross-reference link in title of Figure 44-6
Figure 44-9 ”Measurement Setup for Wait Mode”: replaced “3.3V” with “3.6V”
Table 44-21 ”SAM4S4/2 Active Power Consumption with VDDCORE @ 1.2V Running fro m Flash Memory or SRAM”:
added footnote “Flash Wait State (FWS) in EEFC_FMR adjusted versus core frequency”
Table 44-22 ”SAM4S16/S8 Active Power Consumption with VDDCORE @ 1.2V Running from Flash Memory or SRAM”:
added “AMP2” caption to SRAM column
Table 44-27 ”32.768 kHz Crystal Oscillator Characteristics”: added “Allowed Crystal Capacitance Load” parameter
Figure 44-13 ”32.768 kHz Crystal Oscillator Schematic”: added label “Ccrystal”
Added Section 44.5.5 “32.768 kHz XIN32 Clock Input Characteristics in Bypass Mode”
Table 44-30 ”3 to 20 MHz Crystal Oscillator Characteristics”: added “Allowed Crystal Capacitance Load”
parameter
Table 44-31 ”3 to 20 MHz Crystal Characteristics”: corrected ESR unit ‘W’ to ‘Ω’
Table 44-32 ”XIN Clock Electrical Characteristics (In Bypass Mode)”: for RPARASTANDBY, replaced “Impedance” with
“Resistance” in parameter description and corrected unit ‘W’ to ‘Ω’
Updated Figure 44-16 ”XIN Clock Timing”
Figure 44-21 ”Simplified Acquisition Path”: added caption “ADC Input”; replaced caption “12-bit ADC Core” with “12-bit
ADC”
1243
SAM4S Series [DATASHEET]
Atmel-11100K-ATARM-SAM4S-Datasheet_09-Jun-15
.
08-Jan-15
Added “Symbol” column to Table 44-57 ”Static Performance Characteristics”, Table 44-58 ”Dynamic Performance
Characteristics”, Table 44-59 ”Analog Outputs”, and Table 44-6 0 ”Analog Comparator Characteristics”
Section 44.11 “Temperature Sensor” : specified in stances of “27°C” as ambient temperature
Table 44-63 ”I/O Characteristics”: add ed parameter “Maximum I/O skew”
Section 44.12.3.1 “Maximum SPI Frequency”:
- under “Master Write Mode”, replaced “the maximum SPI frequency is the one from the pad” with “the maximum SPI
frequency is defined by the pin FreqMax value
- updated content under “Master Read Mode”
Table 44-65 ”SSC Timings”: in Min/Max values for SSC4 and SSC7, corrected links to footnote 2
Section 44.12.9 “Embedded Flash Characteristics”: in first paragraph, corrected “field FWS of the MC_FMR” to “field FWS
of the EEFC_FMR”
Section 45. “Mechanical Characteristics”
Inserted heading Section 45.1 “100-lead LQFP Mechanical Characteristics”
Inserted heading Section 45.2 “100-ball TFBGA Mechanical Characteristics”
Inserted heading Section 45.3 “100-ball VFBGA Mechanical Chara c teristics”
Inserted heading Section 45.4 “64-lead LQFP Mechan ical Characteristics”
Table 45-16 ”LQFP Package Characteristics”: corrected title (w as “LQFP and QFN Package Characteristics”)
Inserted heading Section 45.5 “64-lead QFN Mechanical Characteristics”
Inserted heading Section 45.6 “64-ball WLCSP Mechanical Characteristics”
Inserted heading Section 45.7 “48-lead LQFP Mechanical Characteristics” and added sentence “This package respects the
recommendations of the NEMI User Group.”
Inserted heading Section 45.8 “48-lead QFN Mechanical Characteristics” and added sentence “This package respects the
recommendations of the NEMI User Group.”
Table 45-29 ”48-lead QFN Package Characteristics” : corrected title (was “48-lead LQFP Package Characteristics”) and
changed Moisture Sensitivity Le vel from 1 to 3
Table 45-30 ”48-lead QFN Package Reference”: corrected title (was “48-le a d LQ FP Pa cka ge Refe rence”)
Added Section 46. “Mar king”
Section 47. “Ordering Information”:
Table 47-1 ”Ordering Codes for SAM4S Devices”: added ordering codes for MRL ‘B’
Section 48. “Errata”
Section 48.1 “Errata SAM4SD32/SD16/SA16/S16/S8 Rev. A Parts”: added Section 48.1.5 “Low-power Mo de”
Added Section 48.2 “Errata SAM4SD32/SD16/SA16/S16/S8 Rev. B Parts”
Section 48.3 “Errata SAM4S4/S2 Rev. A Parts”: added Se ction 48.3.4 “Low-power Mode”
Added Section 48.4 “Errata SAM4S4/S2 Rev. B Parts”
Table 49-4 . SAM4S Datasheet Rev. 11100H Revision His t ory (Continued)
Doc. Date Changes
SAM4S Series [DATASHEET]
Atmel-11100K-ATARM-SAM4S-Datasheet_09-Jun-15
1244
Table 49-5 . SAM4S Datasheet Rev. 11100G Revision Histor y
Doc. Date Changes
27-May-14
Table 3-1 ”Signal Description List”: WKUP[15:0] voltage reference type added.
In Figure 5-4 “Bac kup Battery”, modified ADC, DAC, Analog Comparator Supply from 2.0V to 2.4V
Modified Section 6.5 “ERASE Pin”.
Modified bullet list on use of erase commands depending on sector size in Section 8.1.3.1 “Flash Overview”
Modified Section 8.1.3.5 “Security Bit”, Section 8.1.3.11 “GPNVM Bits” and Section 8.1.4 “Boot Strategies”.
Section 24. “Boot Program”
Section 24.5.4 “In Applica tion Programming (IAP) Feature”: 5th sentence: added “...the EFC number...”
Section 29. “Power Management Controller (PMC)”
Section 29.17.9 “PMC Clock Generator PLLA Register”: Min value for bit MULA corre c ted to 4 from 7.
Section 29.17.10 “PMC Clo ck Generator PLLB Register”: Min value fo r bit MULB corrected to 4 from 1.
Section 44. “Electrical Characteristics”
Added Table 44-24 ”Typical Power Consumption on VDDCORE (VDDIO = 3.3V, TA = 25°C)”.
Table 44-73 ”AC Flash Characteristics”: Added parameter Erase Pin Assertion Time.
Section 48. “Errata”
Added Section Issue: and Section Issue: “Incorrect Flash Read May Occur Depending on VDDIO Voltage and
Flash Wait State”.
1245
SAM4S Series [DATASHEET]
Atmel-11100K-ATARM-SAM4S-Datasheet_09-Jun-15
Table 49-6 . SAM4S Datasheet Rev. 11100F 29-Jan-14 Revision History
Doc. Date Changes
29-Jan-14
Update to add SAM4S4 and SAM4S2 devices.
“Description”
48-pin package option added at end of section.
“Features”
”System”: Added bullet on tamper detection and anti-tampering feature
“Packages” : Modified dimens ions of 64-ball WLCSP package used for SAM4S16/S8. Added 48 -lead package
options.
Section 1. “Configuration Summary”
Table 1-2, “Configuration Summary for SAM4S8/S4/S2 Devices” added.
Section 2. “Block Diagram”
Figure 2-5, “SAM4S4/S2 100-pin Version Block Diagram”, Figure 2-6, “SAM4S4/S2 64-pin Version Block Diagra m”
and Figure 2-7, “SAM4S4/S2 48-pin Version Block Diagram” added.
Section 3. “Signal Description”
Added fault input number and added comment for “PWMFI0–2” (“PWM Fault Input” ) signal in Table 3-1 ”Signal
Description List”: Available on SAM4S4/S2 only.
Section 4. “Package and Pinout”
Added Table 4-6, “SAM4S4/S2 64-ball WLCSP Pinout”.
Added Section 4.3 “48-lead Packages and Pinouts”.
Section 5. “Power Considerations”
Figure 5-2, “Single Supply”: Modified note with restrictions after the figure.
Figure 5-3, “Core Externally Supplie d”: Changed voltage for ADC, DAC, Analog Comparator Supply. Modified note
with restrictions after the figure.
Removed redundant Figure 5-4. W ake-up Source.
Section 6. “Input/Output Lines”
Added Section 6.6 “Anti-tamper Pins/Low-power Tamper Detection”.
Section 8. “Memories”
Section 8.1.1 “Internal SRAM”, Section 8.1.3 “Embedded Flash”, Table 8-2, “Lock Bit Number”, Section 8.1.3.11
“GPNVM Bits” Added SAM4S4 and SAM4S2 devices.
Section 10. “System Controller”
Removed redundant Figure 10-1. System Controller Block Diagram.
Section 11. “Peripherals”
Table 11-2, “Multiplexing on PIO Controller A (PIOA)” updated with Peripheral D information and note on PWMFI
signals available for SAM4S4/S2 only.
SAM4S Series [DATASHEET]
Atmel-11100K-ATARM-SAM4S-Datasheet_09-Jun-15
1246
Section 12. “ARM Cortex-M4 Processor”
Section 12.5.3 “Power Management Programming Hints”: in 2nd instruction line, replaced “WFE(void)” with
“WFI(void)” to match ‘Wait For Interrupt’ and in 2nd instruction line, replaced “WFE(void)” with “WFI(void)” to match
‘Wait For Interrupt’
Section 12.9.1.2 “CPUID Base Register”: updated ‘Constant’ field description
Section 12.9.1.5 “Application Interrupt and Reset Control Register”: updated ‘VECTCLRACTIVE’ and ‘VECTRESET’
field descripti ons
Section 12.9.1.7 “Configuration and Con trol Register”: updated ‘USERSETMPEND’ field description
Section 12.9.1.16 “MemManage Fault Address Register”: updated ‘ADDRESS’ field description
Section 12.9.1.17 “Bus Fault Address Register”: updated ‘ADDRESS’ field description
Section 12.10.1.1 “SysTick Control and Status”: updated ‘TICKINT’ and ‘ENABLE’ field descriptions
Section 12.10.1.2 “SysTick Rel oad Value Registers”: updated ‘RELOAD’ field description
Section 12.10.1.3 “SysTick Current Value Register”: update d ‘CURRENT' field description
Section 12.10.1.4 “SysTick Calibration Value Register”: updated register reset value; updated ‘TENMS’ and ‘SKEW’
field descriptions.
Section 12.11.2.2 “MPU Control Register”: updated ‘ENABLE’ field description.
Section 12.11.2.3 “MPU Region Numbe r Re gister”: updated ‘REGION’ field description.
Updated Section 12.11.2.4 “MPU Region Base Address Register”.
Added Section 12.11.2.6 “MPU Region Base Address Register Alias 1”to Section 12.11.2.11 “MPU Region Attribute
and Size Register Alias 3”.
Corrected “Sterling Pound” symbol (£) to “less than or equal to” symbol (≤) in operation description in Section 12.6.7
“Saturating Instructions”.
Table 12-30 ”Mapping of Interrupts to the Interrupt Variables”: up dated count range in “Interru pts” column.
Section 14. “Reset Controller (RSTC)”
Figure 14-3 “General Reset State”: replaced “backup_nreset” with “vddbu_nreset”.
Section 14.4.2.2 “NRST External Reset Control”: replaced “ext_nreset” with “exter_nreset”.
Section 14.4.4.2 “Backup Reset”: replaced “core_backup_reset” with “vddcore_nreset”; reworded content to improve
comprehension.
RSTTYP information corrected in Section 14.4.6 “Reset Controller Status Register”.
Section 14.5.1 “Reset Controller Control Register”: updated EXTRST value 1 description (deleted phrase “and resets
the processor and the peripherals”).
Section 14.5.3 “Reset Controller Mode Register”: inserted sentence “This regi ster can only be writ ten if the WPEN bit
is cleared in the System Controller Write Protection Mode Register (SYSC_WPMR).”
Section 15. “Real-time Timer (RTT)”
Figure 15-1 “Real-time Timer”: replaced “16-bit Divider” with “16-bit Prescaler.
Revised Section 15.4 “Functional Description”.
Section 15.5.4 “Real-time Timer Status Register”: updated RTTINC bit description.
Table 49-6 . SAM4S Datasheet Rev. 11100F 29-Jan-14 Revision History (Continu ed)
Doc. Date Changes
1247
SAM4S Series [DATASHEET]
Atmel-11100K-ATARM-SAM4S-Datasheet_09-Jun-15
Section 16. “Real-time Clock (RTC)”
Section 16.1 “Description”: updated to explain need for accurate external 32.768 kHz clock
Section 16.2 “Embedded Characte ristics”: added feature “Write-Protected Registers”
Section 16.5.6 “Updating Time/Calen dar”: reworded second paragraph for clarity
Section 16.5.7 “RTC Accurate Clock Calibration”: replaced sentence “The period interval between 2 correction
events is programmable in order to cover the possible crystal oscillator clock variations” with “According to the
CORRECTION, NEGPPM and HIGHPPM values configu re d in the RTC Mode Register (RTC_MR), the period
interval between two correction events differs”
Section 16.6.1 “RTC Control Register”, Section 16.6.2 “RTC Mode Register”, Section 16.6.5 “RTC T ime Alarm
Register”, Section 16.6.6 “RTC Calendar Alarm Register”: added sentence “This register can only be written if the
WPEN bit is cleared in the System Controller Write Protection Mode Register (SYSC_WPMR) ” and updated
description of UPDCAL bit
Section 16.6.2 “RTC Mode Register”: corrected typo (THIGH value 2 description now reads “3.91 ms”)
Section 18. “Supply Contro ller (SUPC)”
Section 18.1 “Embedded Characte ristics”: adde d bullets on tamper detection and on anti-tampering.
Figure 18-1 “Supply Controller Block Diagram” modi fied.
Section 18.3.4 “Supply Monitor”: Supply Monitor sampling mode, power reduction factor: replaced incorrect values of
32, 256 or 2048 by the correct values of 2, 16 and 128.
Section 18.3.6.2 “Brownout Detector Reset”: Reworked 1st paragraph for clarity
Section 18.3.7.1 “Wake-up Inputs” : corrected WKUPPLx pins to WKUPTx pins. WKUP0, WKUP15 references
changed to WKUPx.
Figure 18-4 “Wake-up Sources”: Defined a section of the graphic as Low-p ower Tamper Detection Logic.
Section 18.3.7.2 “Low-power Tamper Detection and Anti-Tampe ring”: Changed all re ferences to RTCOUT1 and
RTCOUT 0 to RTCOUTx. Other minor modifications to improve clarity.
Figure 18-5 “Low-power Debouncer (Push-to-Make Switch, Pull-up Resistors)”, Figure 18-6 “Low-power Debouncer
(Push-to-Break Switch, Pull-down Resistors)”, Figure 18-7 “Using WKUP Pins Without RTCOUTx Pins”: Modified pin
names.
Added Section 18.3.8 “Register Write Protection”. In Section 18.4.9 “System Controller Write Protection Mode
Register”, updated re gister name and bit descriptions.
Added Section 18.3.9 “Register Bits in Backup Domain (VDDIO)”.
Section 18.4.3 “Supply Controller Control Registe r”: Added sentence on WPEN bit below register table and added
note to descriptions of bits VROFF and XTALSEL indi cating the bits are in the backup domain.
Section 18.4.5 “Supply Controller Mode Register”: Added sentence on WPEN bit below register table and added
note to all bit descriptions except bit KEY indicating the bits are in the backup domain
Section 18.4.4 “Supply Controller Supply Monitor Mode Register”, , Section 18.4.6 “Supply Controller Wake-up Mode
Register” and Section 18.4.7 “Supply Controller Wake-up Inputs Register”: Added sentence on WPEN bit below
register table and added a sentence below the register tables stating that the register is located in the backup domain
Section 18.4.7 “Supply Controller Wake-up Inputs Register”: corrected register name (was “System Controller Wake-
Up Inputs Register”)
Table 49-6 . SAM4S Datasheet Rev. 11100F 29-Jan-14 Revision History (Continu ed)
Doc. Date Changes
SAM4S Series [DATASHEET]
Atmel-11100K-ATARM-SAM4S-Datasheet_09-Jun-15
1248
Section 20. “Enhanced Embedded Flash Controller (EEFC)”
Corrected partial programming boundary from 32-bit to 64-bit and reworked Section 20.4.3.2 “Write Commands” and
all sub-sections with figures Figure 20-7 Full Page Programming to Figure 20-9 Programming Bytes in the Flash.
In Section 20.4.3.3 “Erase Commands”, modified paragraph on Erase pages (EPA) and Erase sector (ES)
commands, as well as Table 20-4 ”FARG Field for EPA Command”. Added “small sector” text as limitations in Table
20-4 ”FARG Field for EPA Command”.
Added notes when FARG exceeds limi ts in Section 20.4.3.4 “Lock Bit Prot ection”.
Re-worked Section 20.4.3.5 “GPNVM Bit” and added title in Section 20.4.3.6 “Calib ration Bit”.
In Section 20.5.2 “EEFC Flash Command Reg ister”, changed the description of FARG field ac cordingly.
Replaced NVIC by “interrupt controller” everywh ere in the document.
Section 23. “Cyclic Redundancy Check Calcula t ion Unit (CRCCU)”
Section 23.1 “Description”: added sentence with information on CRCCU and data integrity check.
Section 23.2 “Embedded Characteristics”: removed bullet ‘Single AHB Master Interface’. Inserted two new bullets on
data integrity check and background task. Added note.
Modified access type of Secti on 23.7.7 “CRCCU DMA Interrupt Mask Register”.
Section 23.6.2 “Transfer Control Register”: updated IEN bit description
Section 23.6.3 “Transfer Reference Register”: replaced “compared with that register” with “com pared with this field”
in REFCRC field description
Updated bit descriptions in Section 23.7.2 “CRCCU DMA Enable Register” to Section 23.7.6 “CRCCU DMA Interrupt
Disable Register”, in Section 23.7.8 “CRCC U DMA Interrupt Status Register”, in Section 23.7.9 “CRCCU Control
Register” and in Section 23.7.12 “CRCCU Interrupt Enable Register” to Section 23.7.15 “CRCCU Interrupt Status
Register”.
Section 27. “Peripheral DMA Con tro ller (PDC)”
Replaced “on- and/or off-chip” with “target” in Section 27.1 “Descri ption”and Section 27.4.2 “Memory Pointers”.
Added last paragraph to Section 27.4.1 “C on fi g u r at i on ” specifying that the peripheral clock must be enabled for a
PDC transfer.
Section 28. “Clock Generator”
Added Section 28.5.5 “Switch ing Main Clock between the Main RC Oscillator and Fast Crystal Oscillator”.
Section 29. “Power Ma nage me nt Contro lle r (PMC)”
Reworked Section 29.11 “Fast Startup” and added Section 29.12 “Start-up from Embedded Flash”
Reworked Section 29.13 “Main Clock Failure Detector”.
Enhanced Section 29.14 “Programming Sequence”
Enhanced Section 29.14 “Programming Sequence”
Section 29.16 “Register Write Protection”: Changed section title and re-wor ked content. In Section 29.17.21 “PMC
Write Protection Mode Register” and Section 29.17.25 “PMC Perip heral Clock Status Register 1”: Changed register
names and modified bit and field descriptio ns.
Section 30. “Chip Identifier (CHIPID)”
Section 30.3.1 “Chip ID Register”: Modified “ARCH: Architecture Identifier” bit description table to show only SAM4S.
Section 31. “Parallel Input/Output Controll er (PIO )”
Section 31.5.14 “Register Write Protection”: Changed section title and revise d content.
Section 31.7.46 “PIO Write Protection Mode Register”: Modified register name and aligned bit descriptions.
Replaced list of protectable registers with cross-reference to section “Register Write Protection”.
Section 31.7.47 “PIO Write Protection Status Register”: Modified register name and aligned bit descriptions.
Removed note .
Table 49-6 . SAM4S Datasheet Rev. 11100F 29-Jan-14 Revision History (Continu ed)
Doc. Date Changes
1249
SAM4S Series [DATASHEET]
Atmel-11100K-ATARM-SAM4S-Datasheet_09-Jun-15
Section 33. “Serial Peripheral Interface (SPI)”
‘MCK’ replaced with ‘periphera l clock’ throughout.
Updated Figure 33-1 “Block Diagram”, Figure 33-3 “SPI Transfer Forma t (NCPHA = 1, 8 bits per transfer)” and
Figure 33-4 “SPI Transfer Format (NCPHA = 0, 8 bits per transfer)”
Modified Sectio n 33.7.3 “Master Mode Operations”,
Modified Sectio n 33.7.5 “Register Write Protection”, Section 33.8.10 “SPI Write Protection Mode Register” and
Section 33.8.11 “SPI Write Protection Status Register”
MCK replaced with peripheral clock
Section 34. “Two-wire Interface (TWI)”
Section 34.2 “Embedded Characte ristics”; re moved bullet “Next Buffer Support”
Added details on master/slave mode configuration in Step 2 and fixed typos (‘TXDIS’ --> ‘TXTDIS’, ‘RXDIS’ -->
‘RXTDIS’), added commands 6-9 in Section 34.8.7.1 “Data Transmit with the PDC” on page 724 and and commands
4 and 12 in Section 34.8.7.2 “Data Receive with the PDC” on page 724.
Updated Figure 34-27 “Master Performs a General Call”.
Corrected TWI_THR to Write-only access in Table 34-7 ”Register Mapping” and Section 34.11.11 “TWI Transmit
Holding Register”
Added Section 34.10.6 “Using the Peripheral DMA Contro ller (PDC) in Slave Mode ”
Section 34.11.6 “TWI Status Register”, updated the description of “NACK: Not Acknowledged (clear on read)”, used
in master mode
Section 35. “U ni ve rsal Asynchronous Rec ei v er Tr ansmitter (UART)”
Corrected the offset for PDC registers in Section 35.6 “Unive rsal Asynchronous Receiver Transmitter (UART) User
Interface”.
Section 36. “Universal Synchronous Asynchronous Receiver Transceiver (USART)”
Table 36-2 ”I/O Line Description”: corrected RXD type from Input to I/O.
Added a paragraph on IRDA_FILTER programming criteria in Section 36.7.5.3 “IrDA Demodulator” and in the
corresponding bitfield description in Section 36.8.20 “USART IrDA FILTER Register”.
Corrected Figure 36-22 “Parity Error” for stop bit value.
Replaced 33400 baudrate with 38400 in Table 36-10, “Maximum Timeguard Length Depending on Baud Rate,” on
page 792, Table 36-11, “Maximum Time-out Period,” on page 793.
Section 36.7.10 “Register Write Protection”: Changed section title and re-worked content. Section 36.8.22 “USART
Write Protection Mode Register” and Section 36.8.23 “USART Write Prote c tion Status Register”: Cha nged register
names and modified bit and field descriptio ns.
In Section 36.7.3.4 “Manchester Decoder”, updated information on RXIDLEV bit in 4th paragraph.
Section 36.8.3 “USART Mode Register”: in table describing ‘PAR Parity Type’ field, ad ded value ‘5’ and description.
Section 36.8.18 “USART FI DI RATIO Register”: modified FI_DI_RATIO field from 16 bits to 11 bits.
In Section 36.8.21 “USART Manchester Configuration Register” added RXIDLEV as bit 31 and added bit description.
Section 37. “Timer Counter (TC)”
TIOA1 replaced with TIOB1 in Section 37.1 “Description”and added a note for ENETRG description in Section 37.7.3
“TC Channel Mode Register: Waveform Mode”.
Erroneous description of TCCLKS table, rows 0 to 4 reworked in Section 37.7.2 “TC Channel Mode Registe r:
Capture Mode” and Section 37.7.3 “TC Channel Mode Register: Waveform Mode”
Section 37.7.14 “TC Block Mode Register”: corrected TC2XC2S field configuration values: value 2 is TIOA0 (was
TIOA1); valu e 3 is TIOA1 (was TIOA2)
Section 37.6.2 “16-bit Counter”, Section 37.6.11.1 “WAVSEL = 00”, Figure 37-9 “WAVSEL = 10 without
Trigger”, Figure 37-10 “WAVSEL = 10 with Trigger”, Section 37.6.11.3 “WAVSEL = 01”, and Figure 37-1 4
“WAVSEL = 11 with Trigger”: replaced “0xFFFF” with “2n-1” in first paragraph (with “n” representing
counter size)
Table 49-6 . SAM4S Datasheet Rev. 11100F 29-Jan-14 Revision History (Continu ed)
Doc. Date Changes
SAM4S Series [DATASHEET]
Atmel-11100K-ATARM-SAM4S-Datasheet_09-Jun-15
1250
Section 38. “High Speed MultiMedia Card Interface (HSMCI)”
Changed PDCFBYTE to FBYTE in Section 9.6 “WRITE_SINGLE_BLOCK/WRITE_MULTIPLE_BLOCK Operation
using DMA Controller” and in Section 9.8 “READ_SINGLE_BLOCK/READ_MULTIPLE_BLOCK Operation using
DMA Controller”.
Section 38.13 “Register Write Protection”: changed title (was “Write Protection Registers”); revised content
In Section 38.14.2 “HSMCI Mode Register”, PDCMODE bit description, corrected reference to MCI Mode Register to
HSMCI Status Register.
In Section 38.14.7 “HSMCI Block Register”, BLKLEN bit description, removed sentence on its accessibility in HSMCI
Mode Register.
Section 38.14.17 “HSMCI Write Protection Mode Register”: modified register name (was HSMCI Write Protect Mode
Register); replaced list of protectable registers with cross-reference to section “Register Write Protection”
Section 38.14.18 “HSMCI Write Protection Status Register”: modified register name (was HSMCI Write Protect
Status Register) and updated description
Section 40. “USB Device Port (UDP)”
Section 40.2 “Embedded Characte ristics”: replaced bullet “Integrated Pull-up on DP” with “Integrated Pull-up on
DPP”, added bullet “Integrated Pull-down on DDM”
Section 40.6.3.6 “Entering in Suspend State”: replaced “must drain less than 500uA” with “must drain no more than
2.5 mA”
Section 40.6.3 “Controlling Device Sta te s”: replaced “may not consume more than 500 µA” with “must not consume
more than 2.5 mA”
Table 40-6 ”Register Ma pping”: corrected reset values for for UDP-FDR0..Y. Updated note (1).
Section 40.4.2 “Power Management”: added detail on fast RC.
Changed register names:
Section 40.7.10 old: UDP Endpoi nt Co nt rol an d Status Registe r (C on trol, Bulk Interrupt Endp oi n ts), new:
“UDP Endpoint Control and Status Register (CONTROL_BULK)”
Section 40.7.11 old: UDP Endpoint Control and S tatus Register (Isochronous Endpoints), new: “UDP
Endpoint Control and Status Register (ISOCHRONOUS)”.
Section 41. “Analog Compar ator Controller (ACC)”
Section 41.1 “Description” Upda ted section for clarity.
Figure 41-1 “Analog Comparator Controller Block Diagram”: Updated for clarity.
Section 41.6 “Functional Description”, Section 41.6.2 “Analog Settings” and Section 41.6.4 “Fault Mode ”: Updated
for clarity.
Replaced section “Write Protection System” with Section 41.6.5 “Register Write Protection”. Updated Section 41.7.8
“ACC Write Protection Mode Register” and Section 41.7.9 “ACC Write Protection Status Register”. Bit 0 name in
Section 41.7.9 “ACC Write Protection Statu s Register” changed from WPROTERR to WPVS.
Section 42. “Analog-to-Digital Converter (ADC)”
Section 42.1 “Description”: Added sentence: The last channel is internally connected by a temperature sensor.
Section 42.2 “Embedded Characte ristics”: upda ted section with new characteristics
Section 42.6.3 “Conversion Resolution”: Modified content to limit information on 12-bit resolution.
Section 42.6.14 “Register Write Protection”: Reworked content.
Section 42.7.3 “ADC Channel Sequence 1 Register” and Section 42.7 .4 “ADC Channel Sequence 2 Regi ster”:
modified max channel number to 15.
Section 42.7.12 “ADC Interrupt Status Register”: updated ‘ENDRX’ and ‘RXBUFF’ bit descriptions.
Section 42.7.15 “ADC Compare Window Registe r ”: upd ated ‘LOWTHRES’ and ‘HIGHTHRES’ field de scriptions.
Section 42.7.20 “ADC Write Protection Mode Register” and Section 42.7.21 “ADC Write Protection Status Register”:
Modified register names (from Write Protect to Write Protection). Reworked field descriptions.
Table 49-6 . SAM4S Datasheet Rev. 11100F 29-Jan-14 Revision History (Continu ed)
Doc. Date Changes
1251
SAM4S Series [DATASHEET]
Atmel-11100K-ATARM-SAM4S-Datasheet_09-Jun-15
Section 43. “Digital-to-Analo g Converter Controller (DACC)”
Section 43.7.7 “DACC Interrupt Enable Register”, Section 43.7.8 “DACC Interrupt Disable Register” and Section
43.7.9 “DACC Interrupt Mask Register”: mo dified bit descriptions.
Rework of all “refresh” related paragraphs, Section 43.7.3 “DACC Channel Enable Register” and Section 43.6.7
“DACC Timings”. Modified description for ”REFRESH: Automatic Refresh Period” field in Section 43.7.2 “DACC
Mode Register”.
Re-worked Section 43.6.8 “Register Write Protection” and associated registers and bit/fie ld descriptions in Section
43.7.12 “DACC Write Protection Mode Register” and Section 43.7.13 “DACC Write Protection Status Register”.
Section 44. “Electrical Characteristics”
Added Section 44.2 “Recommended Op erating Conditions”.
Section 44.4 “Power Consumption”: Added power consumpti on values for SAM4S4/SAM4S2. Updated Section
44.4.1 “Backup Mode Current Consumption”.
Removed Supply Ripple Voltage parameter from Table 44-30, “3 to 20 MHz Crystal Oscillator Characte ristics”
Table 44-32 ”XIN Clock Electrical Characteristics (In Bypass Mode)”: Added CPARASTANDBY AND RPARASTANDBY
parameters.
Updated and re-worked Section 44.8 “12-bit ADC Characte ristics”:
Updated Secti on 44.9 “12-bit DAC Characteristics”. Removed Max Vo ltage Ripple parameter from Table 44-55,
“Analog Power Supply Characteristics”. Added Refresh Time to Table 44-56, “Channel Conversion Time and DAC
Clock”.
In Section 44.12 “AC Characteristics” modified
Table 44-64, “SPI Timings”.
Table 44-65, “SSC Timi ngs”
Table 44-66, “SMC Read Signals - NRD Controlled (READ_MODE = 1)”
Table 44-68, “SMC Write Signals - NWE Controlled (WRITE_MODE = 1)”
Table 44-69, “SMC Write Signals - NCS Controlled (WRITE _MODE = 0)”
Table 44-70, “USART SPI Timings”
Table 44-71 ”Two-wire Serial Bus Requirements”: Added parameter tBUF
Section 44.12.9 “Embedded Flash Characteristics”: modified Table 44-72, “Embedded Flash Wait State at 105°C”.
Table 44-73, “AC Flash Characteristics”: Full Chip Erase: Added values for 256 Kbytes and 128 Kbytes. Added new
parameter Page Program Time.
Section 45. “Mechanical Cha ra c teristics”
Table 45-20 ”64-ball WLCSP Package Dimensions (in mm)” Added body size for SAM4S4 for WLCSP64 package.
Figure 45-8 ”48-lead LQFP Package Drawing” and corresponding characteristics added.
Figure 45-9 ”48-lead QFN Package Drawing” and corresponding characteristics added.
Section 48. “Errata”
Added Section 48.3 “Errata SAM4S4/S2 Rev. A Parts”.
Section 47. “Ordering Information”
Added information on carrier type availability.
Updated Table 47-1 ”Ordering Codes for SAM4S Devices”. Added new orderi ng codes for SAM4S4 and SAM4S2
devices.
Table 49-6 . SAM4S Datasheet Rev. 11100F 29-Jan-14 Revision History (Continu ed)
Doc. Date Changes
SAM4S Series [DATASHEET]
Atmel-11100K-ATARM-SAM4S-Datasheet_09-Jun-15
1252
Table 49-7 . SAM4S Datasheet Rev. 11100E 24-Jul-13 Revision History
Doc. Rev.
11100E Comments
Change
Request
Ref.
Introduction
Added WLCSP64 package in Section “Features” , Table 1-1, “Configuration Summary for
SAM4SD32/SD16/SA16/S16 Devices”, added Figure 4-6 and Table 4-5, “SAM4S16/S8 64-ball WLCSP
Pinout”.
Updated Section 5.6 “Low-power Mode s” . Added information on WFE.
Added 2nd paragraph in Section 6.1 “General Purpose I/O Lines”.
8620
9073
8992
RTC
Added new bullet “Safety/security features” in Section 16.2 “Embedded Characteristics”.
Last sentence added in Section 16.5.3 “Alarm”.
Added note in Section 16.5.3 “Alarm”, Section 16.6.5 “RTC Time Alarm Register” and Section 16.6.6 “RTC
Calendar Alarm Register”.
Replaced values for temperature range with a generic term in Section 16.5.7 “RTC Accurate Clock Calibration”.
Block diagram centered for readabili ty in Section 16.3 “Block Diagram”.
8544
8900
9027
9033
rfo
PMC
Section 28.4.2 “Slow Clock Crystal Oscillator”, replaced “...in MOSCSEL bit of CKGR_MOR,...” with “...in
XTALSEL bit of SUPC_CR,...” in the last phrase of the 3d paragraph.
Section 28.4.2 “Slow Clock Crystal Oscillator”, added references on the OSCSEL bit of PMC_SR in the 3d
paragraph.
Register name s in Clock Generator: Repla ced “PLL_MCKR” with “PMC_MCKR” and “PLL_SR” with “PMC_SR”
in Section 28.5.6 “Software Sequence to Detect the Presence of Fast Crystal”
In Section 28.6.1 “Divider and Phase Lock Loop Programming”, 3rd bullet, replaced PMC_IER with PMC_SR.
Deleted previous 4th bullet (was useless sentence “ Disable and then enable the PLL...”).
In Figure 28-3 and Section 28.5.3 “3 to 20 MHz Crystal or Ceramic Resonator-based Oscillator” paragraph 5,
replaced MOSCXTCNT with MOSCXTST.
Added code example in step 1. of Section 29.14 “Programming Sequence”.
Corrected reset value of CKGR_MOR register in Table 29-3, “Register Mapping”.
Corrected value of PLLA(B)COUNT field description in Section 29.17.9 “PMC Clock Generator PLLA Register”
and Section 29.17.10 “PMC Clock Generator PLLB Register ”.
Added a note in Section 29.17.8 “PMC Clock Generator Main Clock Frequency Register” an d reworked a
paragraph in Section 28.5.2 “Fast RC Oscillator Clock Frequency Adju stment”
9069
rfo
8970
8963
8447
8564
8853
Electrical Characteristics
Changed 85°C temperatures with 105°C in th e whole chapter. Added read/write characteristics temperature
information on Flash in Note (3), Table 44-3, “DC Characteristics” and Note (1), Table 44-73, “AC Flash
Characteristics”. Modified Section 44.4.1 “Backup Mode Current Consumption” and Table 44-9 to Table 44-23
with up-to-date current consumption values.
Updated Section 44.4.2 .1 “Sleep Mode”.
Added Section 44.4.3.1 “SAM4S4/2 Active Power Consumption”.
In Section 44.4.4 “Peripheral Power Consumption in Active Mode”, upd ated Table 44-24, “Typical Power
Consumption on VDDCORE (VDDIO = 3.3V, TA = 25°C)”
rfo
rfo
rfo
rfo
Mechanical Characteristics
Added Figure 45-6 and associated package dimensions and soldering tables for WLCSP64 package.
Soldering tables updated in Section 45. “Mechanical Characteristics”.8620
rfo
1253
SAM4S Series [DATASHEET]
Atmel-11100K-ATARM-SAM4S-Datasheet_09-Jun-15
Ordering Information
New ordering codes (105 °C, reel conditioning, WLCSP package) added in Table 47-1 , “Ordering Codes for
SAM4S Devices”.8620, rfo
Errata
Added Section Issue: “Watch dog Not Stopped in Wait Mode” and Section Issue: “Unpredictable Behavior if
BOD is Disabled, VDDCORE is Lost and VDDIO is Connected”.9075
Backpage
ARMConnected® logo and corresponding text deleted. rfo
Table 49-7 . SAM4S Datasheet Rev. 11100E 24-Jul-13 Revision History (Continued)
Doc. Rev.
11100E Comments
Change
Request
Ref.
Table 49-8 . SAM4S Datasheet Rev. 11100D 15-Apr-13 Revis ion Histo ry
Doc. Rev.
11100D Comments
Change
Request
Ref.
Introduction
Deleted sleep mode for fast start-up in Section 5.8 “Fast Start-up”.
Added 32 kHz trimming features in Sectio n “Features” .
Notes added in Section 8.1.3.1 “Flash Overview”, below Figure 8-3.
8763
rfo
Electrical Characteristics
In Table 43-26, added 2 lines describing CPARASTANDBY and RPARASTANDBY parameters.
In Table 43-62, Endurance line, deleted “Write/erase... @ 25°C” and 100k value.
In Table 43-62, added Write Page Mode values.
8614
8850
8860
Errata
Deleted former Chapter 45 “SAM4S Series Errata” (was only a cross-reference to Engineering Samples
Erratas), added a new detailed Section 48. “Errata”.8645
Backpage
ARMPowered® logo replaced with ARMConnected® logo, corresponding text updated. rfo
SAM4S Series [DATASHEET]
Atmel-11100K-ATARM-SAM4S-Datasheet_09-Jun-15
1254
Table 49-9 . SAM4S Datasheet Rev. 11100C 09-Jan-13 Revision History
Doc. Rev.
11100C Comments
Change
Request
Ref.
Introduction
In Section 2. “Block Diagram”, USB linked to Peripheral Bridge instead of AHB Bus Matrix in Figure 2-3, Figure
2-4, Figure 3. and Figure 2-2.
Reference to the LPM bit removed in the whole datasheet.
Flash rails mentioned in Section 5.1 “Power Supplies”.
Section 9. “Real Time Event Management” created.
WKUP[15:0] pins added on each block diagram in Section 2. “Block Diagram” and in Table 3-1, “Signal
Description List”.
All diagrams updated with Real Time Events in Section 2. “Block Diagram”.
JTAG and PA7 pins details added in Section 6.2.1 “Serial Wire JTAG Debug Port (SWJ-DP) Pins”.
8386
8392
8406
8439
8459
8484
8547
CORTEX
Section 12.8.3 “Nested Vectored Interrupt Controller (NVIC) User Interface”, offset information for NVIC register
mapping updated in Table 12-31 ”Nested Vectored Interrupt Controller (NVIC) Register Mapping”.
Section 12.9.1 “System Control Block (SCB) User Interface”, deleted lines with MMFSR, BFSR, UFSR and
updated the note in Table 12-32, “System Control Block (SCB) Register Mappi ng”.
Table 12-34 ”System Timer (SYST) Register Mapping”: table name updated (SysTick changed to SYST).
Harmonized instructions code fonts in Section 12.6 “Cortex -M4 Instruction Set”. Fixed various typos.
8211
8343
RTT
RTC 1Hz calibrated clock feature added in Section 15.1 “Description”, Section 15.4 “Functi onal Description”
and in RTT_MR register, see Section 15.5.1 “Real-time Timer Mode Register” .
RTC
New bullet “Safety/security features” added in Section 16.2 “Embedded Ch aracteristics”. 8544
WDT
Note added in Section 17.5.3 “Watchdog Timer Status Register”. 8128
SUPC
Offsets updated and SYSC_WPMR in Table 18-1 ”System Controller Regi sters”. Sectio n 18.4.9 “System
Controller Write Protection Mode Register” added.
Force Wake Up Pi n removed from Section 18.1 “Embedded Characteristics”.
In Section 18.3.3 “Core Voltage Regulator Control/Backup Low-power Mode”, removed informations related to
WFE and WFI, deleted reference to 1.8V for voltage regulator.
Figure 18-1 Block Diagram updated.
8253
8263
8363, 8407
8515
EEFC
In Section 20.5.2 “EEFC Flash Command Register”, table added in FCMD bitfield, details added in table in
FARG bitfield.
Note concerning bit number limitation added in Section 20.4.3.5 “GPNVM Bit”.
8352
8390
1255
SAM4S Series [DATASHEET]
Atmel-11100K-ATARM-SAM4S-Datasheet_09-Jun-15
CMCC
Updated access condition from Write-only to Read-only in Section 22.5.4 “Cache Controller Status Register”
and Section 22.5.10 “Cache Controller Monitor Status Register”. Index bitfield size increased from 4 to 5 bits in
Section 22.5.6 “Cache Controller Maintenance Register 1”, bitfield description complete d.
“0xXX - 0xFC” offset replaced with “0x38 - 0xFC” in the last row in Table 22-1 ”Register Mapping”. In Figure 22-
1, replaced “Cortex MPPB” with “APB Interface” in Block Diagram.
8373
rfo
CRCCU
TRWIDTH bitfield description table completed in Section 23. 6. 2 “Tra n sfer Control Regist er” .
Updated Section 23.1 “Description” and Section 23.5.2 “CRC Calculation Unit Operation”.8303
rfo
PDC
Offset data for Register Mapping updated in Table 27-1 ”Register Mapping”.
“ABP bridge” changed to “APB bridge” in Section 27.1 “Description”.7976
rfo
PMC
Section 28.5.6 “Software Sequence to Detect the Presence of Fast Crystal” adde d.
Updated CKGR_MOR register reset value to 0x0000_ 0008 in Section 29.17 “Power Management Controller
(PMC) User Interface”.
8371
8448
CHIPID
Section 30.3.1 “Chip ID Register”, in ARCH bitfield description table, rows sharing SAM3/SAM4 names
reconfigured with standalone rows for each name.
Section 30.3.1 “Chip ID Register”, in ARCH bitfield description table, various devices adde d or removed.
Section 30.3.1 “Chip ID Register”, in SRAMSIZ bitfield description table, replaced 1K/1Kbyte with
192K/192Kbyte for value1.
In Section 30.2 “Embedded Charac teristics”, updated T able 30-1 ”SAM4S Chip ID Registers”.
7730
7977,
8034, 8383
8036
rfo
PIO
DSIZE bit description updated in Section 31.7.49 “PIO Parallel Capture Mode Register”.
Section 31.4.2 “External Interrupt Lines” added. Section 31.4.4 “Interrupt Generation” updated. 7705
rfo
SSC
Removed Table 30-4 in Section 32.7.1.1 “Clock Divider”.
Last line (PDC register) updated in Table 32-5 ”Register Mapping”.
Reworked tables and bitfield descriptions in Section 32.9.3 “SSC Receive Clock Mode Register”, Section
32.9.4 “SSC Receive Frame Mode Registe r ”, Section 32.9.5 “SSC Transmit Clock Mode Register”, Section
32.9.6 “SSC Transmit Frame Mode Register”.
7303
7971
8466
SPI
In Section 33.2 “Embedded Charac teristics”, added the 2 first bul l ets, deleted the pr evi ous last bullet. 8544
Table 49-9 . SAM4S Datasheet Rev. 11100C 09-Jan-13 Revision History (Continu ed)
Doc. Rev.
11100C Comments
Change
Request
Ref.
SAM4S Series [DATASHEET]
Atmel-11100K-ATARM-SAM4S-Datasheet_09-Jun-15
1256
TWI
NVIC and AIC changed to Interrupt Controller. Section 33.10.4.5 “PDC” removed. “This bit is only used in
Master mode” removed from bitfields ENDRX, ENDTX, RXBUFF, and TXBUFE in Section 34.11.6 “TWI Status
Register”.
Figure 34-23 updated: SVREAD = 1 and first occurrence of RXRDY = 1.
Removed “20” at the end of the 1st paragraph in Section 34.1 “Description”.
Table 34-7 ”Register Mapping”, replaced “0x100 - 0x124” with “0x100 - 0x128” and “Reserved for the PDC” with
“Reserved for PDC registers” in the PDC line.
Section 34.10.6 “Using the Peripheral DMA Controller (PDC) in Slave Mode” reworked.
7844
7884
7921
7973
rfo
UART
Table 35-3 ”Register Mapping”, PDC registers info for register mapping updated. 7967
USART
Section 36.7.1 “Baud Rate Generator”, replaced “or 6” with “or 6 times lower” in the last phrase. rfo
HSMCI
Phrase “not only for Write operations now” removed from NOTBUSY bitfield descriptionI in Section 38.14.12
“HSMCI Status Register”.
replaced BCNT bitfield table with the corresponding description and updated Warning note in BCNT bitfield
description in Section 38.14.7 “HSMCI Block Regi ster”.
In Section 38.6.3 “Interrupt”, replaced references to NVIC/AIC with “interrupt co ntroller”.
8394
8431
rfo
PWM
Typo corrected in line Timer0 in Table 39-4 ”Fault Inputs”.
Replaced ‘Main OSC’ with ‘Ma in OSC (PMC)’ in Table 39-4 ”Fault Inputs”.8438
rfo
UDP
Pull-up’ and ‘pull-down’ spelling harmonized in the whole chapter.
Added UDP_CSRx (ISOENDPT) alternate register in Section 40.7.11 “UDP Endpoint Control and Status
Register (ISOCHRONOUS)”.
7867
8414
ADC
Removed “...and EOC bit corresponding to the last converted channel” from the last phrase of the third
paragraph in Section 42.6.4 “Conversion Results” .
TRANSFER value set to 2 in TRANSFER bitfield description in Section 42.7 .2 “AD C Mode Register”.
Text amended in Section 42.1 “Descriptio n”.
SLEEP and FWUP bitfield description texts in tables updated in Section 42.7.2 “ADC Mode Register” .
8357
8462
rfo
Electrical Characteristics
Whole chapter reworked to add SAM4SD32/SD16/SA16 data, various values added or updated.
Clext values changed in Table 44-30.
Configurations A and B updated in Section 44.4.1 “Backup Mode Curren t Con s umption”.
rfo, 8435
8391
8422
Mechanical Characteristics
QFN64 package drawing and table updated in Figure 45-5. 8529
Table 49-9 . SAM4S Datasheet Rev. 11100C 09-Jan-13 Revision History (Continu ed)
Doc. Rev.
11100C Comments
Change
Request
Ref.
1257
SAM4S Series [DATASHEET]
Atmel-11100K-ATARM-SAM4S-Datasheet_09-Jun-15
.
Table 49-1 0. SAM4S Datasheet Rev. 1 1100B 31-Jul-12 Revision History
Doc. Rev.
11100B Comments
Change
Request
Ref.
Introduction
48 pins packages (SAM4S16A and SAM4S8A devices) removed.
Write Protected Registers added in “Description” on page 1.
Note related to EWP and EWPL comma nds added in Section 8.1.3.1 “Flash Overview” on page 38 .
References to WFE instructions replaced by relevant bits precise descriptions.
Dual bank and cache memory mentioned in “Description” on page 1 and “Configuration Summary” on page 4.
Flash and SRAM memory sizes updated in “Description” on page 1 and “Configuration Summary” on page 4.
1 µA instead of 3 in “Description” on page 1, Section 5.3 on page 27 and Section 5.6.1 on page 30.
Table titles and sub-section titles updated with new devices.
New block diagram added in Figure 2-2 on page 6.
VFBGA100 package added: Figure 4-3 on page 17 and Table 4-3 on page 20 added.
Reference to CortexM3 deleted and VDDIO value added in Section 5.6.1 “Backup Mode” on pa ge 30.
Entering W ait Mode process updated and current changed from 15 to 32 µA in Section 5.6.2 on page 30.
Added paragraph detailing mode selection with FLPM value in Section 5.6.3 on page 31.
Values added and notes updated in Table 5-1 on page 32.
Third paragraph frequency values updated in Section 6.1 on page 34.
SRAM upper address chang ed to 0x20400000, an d EFC1 added in Figu re 7-1 on page 37.
Note added in Section 8.1.3.1 “Flash Overview” on page 38.
New devices features added in Section 8.1.1 “Internal SRAM” on page 38, Section 8.1.3.1 “Flash Overview” on
page 38, Section 8.1.3.4 “Lock Regions” on page 42, Section 8.1.3.5 “Security Bit” on page 42, Section
8.1.3.11 “GPNVM Bits” on page 43.
EEFC replaced by EEFC0 and EEFC1 in Table 11-1 on page 48.
‘Cortex M-4’ changed for ‘Cortex-M4’ in block diagrams: Figure 2-3 on page 7 and Figu re 2- 4 on page 8.
Section 5.6.4 “Low-power Mode Summary Table”, updated the list of potential wake up sources for Sleep Mode
in Table 5-1 on page 32.
Added references to S16 in the flash size description in Section 8.1.3.1 “Fla sh Overview”.
Section 2. “Block Diagram”, replaced “Time Coun ter B” by “Time Counter A” in Fi gure 2-3 on page 7.
Fixed the section structure for Section 5.6.3 “Sleep Mode”.
8100
8213
8225
8275
rfo
rfo
rfo
rfo
rfo
rfo
CORTEX
FPU related instructions deleted in Table 12-13 on page 87.
Fonts style corrected for instructions code in the whole chapter.
Updated Figure 12-9 on page 97.
8252
rfo
rfo
RSTC
Updated for dual core.
EXTRST field descripti on updated in Section 14.5.1 “Reset Controller Control Register” on page 283.8306
8340
SAM4S Series [DATASHEET]
Atmel-11100K-ATARM-SAM4S-Datasheet_09-Jun-15
1258
RTC
In Section 16.6.2 “RTC Mode Register” on page 303, formulas associated with conditions HIGHPPM = 1 and
HIGHPPM = 0 have been swapped, text has been clarifie d.
In Section 16.5.7 “RTC Accurate Clock Calibration” on page 299, paragraph describing RTC clock calibration
circuitry correction updated with mention of crystal drift.
7950
7952
SUPC
References to WFE instructions deleted in Section 18.3.3 “Core Voltage Regulator Control/Backup Low-power
Mode” on page 328.
Supply monitor threshold values modified in Section 18.3.4 “Sup ply Monitor” on page 328.
SMTH bit table replaced by a cross-reference to Electrical characteristics in Section 18.4.4 “Supply Controller
Supply Monitor Mode Reg ister” on page 338.
Typo in Section 18.4.8 “Supply Controller Status Register” on page 343 is now fixed.
“half” replaced with “first half” in Section 18.4.6 “Supply Controller Wake-up Mode Register” on page 340 and in
Section 18.4.7.2 “Low Power Debouncer Inputs” on page 295.
Figure 18-4 on page 331 modified.
Push-to-Break figure example Figure 18-6 on page 333 added, title of Figure 18-5 on page 333 modified.
“square waveform ..” changed to “duty cycle ..” in Section 18.4.7.2 “Low Power De bouncer Inputs” on page
295.
Switching time of slow crystal oscillator updated in Section 18.3.2 “Slow Clock Generator” on page 328 .
rfo
8024
8067
8064, 8082
8082
8226
8266
EEFC
Added GPNVM command line in Section • “FARG: Flash Command Argument” on page 368.
Unique identifier address changed in Section 20.4.3.8 “Unique Iden tifier” on page 363.
User Signature address changed in Section 20.4.3.9 “User Signature” on page 363.
Changed the System Controller base address from 0x400E0800 to 0x400E0A00 in Section 20.5 “Enhanced
Embedded Flash Controller (EEFC) User Interface” on page 365.
8076
8274
rfo
FFPI
All references, tables, figures related to 48-bit devices cleared in this whole chapter. rfo
CMCC
New chapter.
CRCCU
Typos: CCIT802 corrected to CCITT8 02, CCIT16 corrected to CCITT16 in Section 23.5.1 “CRC Calculation
Unit” on page 399 and Section 23.7.10 “CRCCU Mode Register” on page 414. TRC_RC corrected to TR_CRC
in Section 23.7.10 “CRCCU Mode Register” on page 414.
7803
SMC
“turned out” changed to “switched to output mode” in Section 26.8.4 “Write Mode ” on pa ge 45 0.
Removed DBW which is not required for 8-bit only in Section 26.15.4 “SMC MOD E Re gi ste r” on pa g e 47 6 .7925
8307
Table 49-1 0. SAM4S Datasheet Rev. 11100B 31-Jul-12 Revision History (Continued)
Doc. Rev.
11100B Comments
Change
Request
Ref.
1259
SAM4S Series [DATASHEET]
Atmel-11100K-ATARM-SAM4S-Datasheet_09-Jun-15
PMC
Added a note in Section 29.17.7 “PMC Clock Genera to r Main Oscillator Register” on page 528.
Max MULA/MULB value changed from 2047 to 62 in Section 29.17.9 “PMC Clock Generator PLLA Register” on
page 531 and Section 29.17.10 “PMC Clock Generator PLLB Register” on page 532.
Step 5 in Secti on 28.2.13 “Programming Sequence” on page 463: Master Clock option added in CSS field.
Third paragraph added in Section 28.2.12 “Main Crystal Clock Failure Detector” on page 46 2. WA IT MODE bit
added in Section 29.17.7 “PMC Clock Generator Mai n Oscillator Register” on page 528.
7848
8064
8170
8208
CHIPID
Table 30-1 on page 552 modified. rfo
TC
Changed TIOA1 in TIOB1 in Section 37.6.14.1 “Description” on page 860 and Section 37.6.14.4 “Position and
Rotation Measurement” on page 865.8101
PWM
Font size enlarged in Figure 39-14 on page 964.
“CMPS” replaced with “CMPM” in whole document. 7910
8021
ADC
EOCAL pin and description added in Secti on 42.7.12 “ADC Interrupt Status Register” on page 1106.
PDC register row added in Section 42.7 “Analog-to-Digital Converter (ADC) User Interface” on page 1092.
Added comment in Section 42.7.15 “ADC Compare Window Register” on page 1109.
Features added in Section 42.2 “Embedded Characteristics” on page 1077.
Comments added, and removed “offset” in Secti on 42.6.11 “Automatic Calibration” on page 1090.
rfo
7969
8045
8088
8133
Electrical Characteristics
Whole chapter updated. In tables, values updated, and missing values added.
Comment for fla s h erasing added in Section 44.12.9 “Embedded Flash Cha ra c teristics” on page 1199.
Updated conditions for VLINE-TR and VLOAD-TR in Table 44-4 on page 1143.
Removed the “ADVREF Current” row from Table 43-30 on page 1059.
Updated the “Offset Error” parameter description in Table 43-32 on page 1061.
Updated the TACCURACY parameter description in Table 44-6 on page 1144 .
Updated the temperature sensor description in Section 44.11 “Temperature Sensor” on page 1180 and the
slope accuracy parameter data in Table 44-60 on page 1180.
8085, 8245
8223
rfo
rfo
rfo
Mechanical Characteristics
48 pins packages (SAM4S16A and SAM4S8A devices) removed.
100-ball VFBGA package drawing added in Figure 45-3 on pag e 1203.8100
rfo
Ordering Information
Table 47-1 on page 1216 completed with new devices and reordered. rfo
Errata
Removed the Flash Memory section.
Removed the Errata section and added references for two separate errata documents in Section 47. “Ordering
Information” on page 1216.
rfo
rfo
Specified the preliminary status of the datasheet. rfo
Table 49-1 0. SAM4S Datasheet Rev. 11100B 31-Jul-12 Revision History (Continued)
Doc. Rev.
11100B Comments
Change
Request
Ref.
SAM4S Series [DATASHEET]
Atmel-11100K-ATARM-SAM4S-Datasheet_09-Jun-15
1260
Table 49-11. SAM4S Datasheet Rev. 1110 0A 28-Oct-11 Revision History
Doc. Rev.
11100A Comments
Change
Request
Ref.
First issue.
1261
SAM4S Series [DATASHEET]
Atmel-11100K-ATARM-SAM4S-Datasheet_09-Jun-15
Table of Contents
Description. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 1
Features . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 2
Safety Features Highlight . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 4
1. Configuration Summary . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 5
2. Block Diagram . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 6
3. Signal Description . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 13
4. Package and Pinout . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 17
4.1 100-l ead Packages and Pinouts . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 17
4.2 64-lead Packages and Pinouts . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 22
4.3 48-lead Packages and Pinouts . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 25
5. Power Considerations . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 27
5.1 Power Supplies . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 27
5.2 Power-up Considerations . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 27
5.3 Voltage Regulator . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 28
5.4 Typical Powering Schematics . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 29
5.5 Active Mode. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 30
5.6 Low-power Modes. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 30
5.7 Wake-up Sources . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 33
5.8 Fast Start-up . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 33
6. Input/Output Lines . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 35
6.1 General Purpose I/O Lines . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 35
6.2 System I/O Lines. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 36
6.3 Test Pin. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 37
6.4 NRST Pin . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 37
6.5 ERASE Pin . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 37
6.6 Ant i-tamper Pins/Low-pow er Tamper Detection . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 37
7. Product Mapping . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 38
8. Memories . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 39
8.1 Embedded Memories . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 39
8.2 External Memories . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 45
9. Real Time Event Management . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 46
9.1 Embedded Characteristics . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 46
9.2 Real Time Event Mapping List . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 47
10. System Controller . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 49
10.1 System Controller and Peripheral Mapping. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 49
10.2 Power-on-Reset, Brownout and Supply Mo nitor. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 49
11. Peripherals . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 50
11.1 Peripheral Identifiers . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 50
11.2 Peripheral Signal Multiplexing on I/O Lines. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 51
SAM4S Series [DATASHEET]
Atmel-11100K-ATARM-SAM4S-Datasheet_09-Jun-15
1262
12. ARM Cortex-M4 Processor . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 55
12.1 Description . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 55
12.2 Embedded Characteristics . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 56
12.3 Block Diagram. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 56
12.4 Cortex-M4 Models. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 57
12.5 Power Management . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 86
12.6 Cortex-M4 Instruction Set . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 88
12.7 Cortex-M4 Core Peripherals . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 195
12.8 Nested Vectored Interrupt Controller (NVIC). . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 196
12.9 System Control Block (SCB). . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 207
12.10 System Timer (SysTick) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 233
12.11 Memory Protection Unit (MPU) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 239
12.12 Glossary . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 262
13. Debug and Test Features . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 267
13.1 Description . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 267
13.2 Embedded Characteristics . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 267
13.3 Application Examples . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 268
13.4 Debug and Test Pin Description . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 269
13.5 Functional Description. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 270
14. Reset Controller (RSTC) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 275
14.1 Description . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 275
14.2 Embedded Characteristics . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 275
14.3 Block Diagram. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 275
14.4 Functional Description. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 276
14.5 Reset Controller (RSTC) User Interface . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 281
15. Real-time Timer (RTT) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 285
15.1 Description . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 285
15.2 Embedded Characteristics . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 285
15.3 Block Diagram. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 285
15.4 Functional Description. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 286
15.5 Real-time Timer (RTT) User Interface. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 288
16. Real-time Clock (RTC) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 293
16.1 Description . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 293
16.2 Embedded Characteristics . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 293
16.3 Block Diagram. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 294
16.4 Product Dependencies . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 294
16.5 Functional Description. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 294
16.6 Real-time Clock (RTC) User Interface . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 302
17. Watchdog Timer (WDT) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 319
17.1 Description . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 319
17.2 Embedded Characteristics . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 319
17.3 Block Diagram. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 320
17.4 Functional Description. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 321
17.5 Watchdog Timer (WDT) User Interface. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 323
18. Supply Controller (SUPC) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 328
18.1 Description . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 328
1263
SAM4S Series [DATASHEET]
Atmel-11100K-ATARM-SAM4S-Datasheet_09-Jun-15
18.2 Embedded Characteristics . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 328
18.3 Block Diagram. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 329
18.4 Functional Description. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 330
18.5 Supply Controller (SUPC) User Interface . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 339
19. General Purpose Backup Registers (GPBR) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 349
19.1 Description . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 349
19.2 Embedded Characteristics . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 349
19.3 General Purpose Backup Registers (GPBR) User Interface. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 350
20. Enhanced Embedded Flash Controller (EEFC) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 352
20.1 Description. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 352
20.2 Embedded Characteristics. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 352
20.3 Product Dependencies . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 352
20.4 Functional Description. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 353
20.5 Enhanced Embedded Flash Controller (EEFC) User Interface. . . . . . . . . . . . . . . . . . . . . . . . . . . . 370
21. Fast Flash Programming Interface (FFPI) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 376
21.1 Description . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 376
21.2 Embedded Characteristics. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 376
21.3 Parallel Fast Flash Programming . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 377
22. Cortex-M Cache Controller (CMCC) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 385
22.1 Description . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 385
22.2 Embedded Characteristics . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 385
22.3 Block Diagram. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 386
22.4 Functional Description. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 386
22.5 Cortex-M Cache Controller (CMCC) User Interface . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 388
23. Cyclic Redundancy Check Calculation Unit (CRCCU) . . . . . . . . . . . . . . . . . . . . . . . . . . . 400
23.1 Description . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 400
23.2 Embedded Characteristics . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 400
23.3 CRCCU Block Diagram. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 401
23.4 Product Dependencies . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 402
23.5 CRCCU Functional Description. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 403
23.6 Transfer Control Registers Memory Mapping . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 404
23.7 Cyclic Redundancy Check Calculation Unit (CRCCU) User Interface . . . . . . . . . . . . . . . . . . . . . . 408
24. Boot Program . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 424
24.1 Description . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 424
24.2 Hardware and Software Constraints . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 424
24.3 Flow Diagram . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 424
24.4 Device Initialization . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 425
24.5 SAM-BA Monitor . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 426
25. Bus Matrix (MATRIX) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 430
25.1 Description . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 430
25.2 Master/Slave Management . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 430
25.3 Memory Mapping. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 431
25.4 Special Bus Granting Techniques. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 431
25.5 Arbitration . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 432
25.6 System I/O Configuration . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 433
SAM4S Series [DATASHEET]
Atmel-11100K-ATARM-SAM4S-Datasheet_09-Jun-15
1264
25.7 Register Write Protection . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 434
25.8 Bus Matrix (MATRIX) (MATRIX) User Interface . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 435
26. Static Memory Controller (SMC) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 443
26.1 Description . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 443
26.2 Embedded Characteristics. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 443
26.3 I/O Lines Description. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 444
26.4 Product Dependencies . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 444
26.5 Multiplexed Signals. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 445
26.6 External Memory Mapping . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 446
26.7 Connection to External Devices . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 446
26.8 Application Example . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 448
26.9 Standard Read and Write Protocols . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 450
26.10 Scrambling/Unscrambling Function. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 459
26.11 Automatic Wait States. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 459
26.12 Data Float Wait States . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 464
26.13 External Wait. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 468
26.14 Slow Clock Mode. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 474
26.15 Asynchronous Page Mode . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 476
26.16 Static Memory Controller (SMC) User Interface . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 479
27. Peripheral DMA Controller (PDC) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 490
27.1 Description . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 490
27.2 Embedded Characteristics . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 490
27.3 Peripheral DMA Controller Connections . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 491
27.4 Block Diagram. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 492
27.5 Functional Description. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 493
27.6 Peripheral DMA Controller (PDC) User Interface . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 495
28. Clock Generator . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 506
28.1 Description . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 506
28.2 Embedded Characteristics . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 506
28.3 Block Diagram. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 507
28.4 Slow Clock. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 508
28.5 Main Clock. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 509
28.6 Divider and PLL Block. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 513
29. Power Management Controller (PMC) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 515
29.1 Description . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 515
29.2 Embedded Characteristics . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 515
29.3 Block Diagram. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 516
29.4 Master Clock Controller. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 516
29.5 Processor Clock Controller . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 517
29.6 SysTick Clock . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 517
29.7 USB Clock Controller . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 517
29.8 Peripheral Clock Controller . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 518
29.9 Free-Running Processor Clock. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 518
29.10 Programmable Clock Output Controller . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 518
29.11 Fast Startup. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 518
29.12 Startup from Embedded Flash . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 520
29.13 Main Clock Failure Detector . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 520
29.14 Programming Sequence . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 522
1265
SAM4S Series [DATASHEET]
Atmel-11100K-ATARM-SAM4S-Datasheet_09-Jun-15
29.15 Clock Switching Details. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 525
29.16 Register Write Protection . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 528
29.17 Power Management Controller (PMC) User Interface. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 529
30. Chip Identifier (CHIPID) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 560
30.1 Description . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 560
30.2 Embedded Characteristics . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 561
30.3 Chip Identifier (CHIPID) User Interface . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 562
31. Parallel Input/Output Controller (PIO) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 567
31.1 Description . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 567
31.2 Embedded Characteristics . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 568
31.3 Block Diagram. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 569
31.4 Product Dependencies . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 570
31.5 Functional Description. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 571
31.6 Parallel Input/Output Controller (PIO) User Interface . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 585
32. Synchronous Serial Controller (SSC) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 642
32.1 Description . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 642
32.2 Embedded Characteristics. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 643
32.3 Block Diagram. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 643
32.4 Application Block Diagram . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 643
32.5 SSC Application Examples . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 644
32.6 Pin Name List . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 645
32.7 Product Dependencies . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 645
32.8 Functional Description. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 647
32.9 Synchronous Serial Controller (SSC) User Interface . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 659
33. Serial Peripheral Interface (SPI) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 686
33.1 Description . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 686
33.2 Embedded Characteristics . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 687
33.3 Block Diagram. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 688
33.4 Application Block Diagram . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 688
33.5 Signal Description . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 689
33.6 Product Dependencies . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 689
33.7 Functional Description. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 691
33.8 Serial Peripheral Interface (SPI) User Interface . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 704
34. Two-wire Interface (TWI) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 719
34.1 Description . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 719
34.2 Embedded Characteristics . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 719
34.3 List of Abbreviations . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 720
34.4 Block Diagram. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 720
34.5 I/O Lines Description. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 720
34.6 Product Dependencies . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 721
34.7 Functional Description. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 721
34.8 Two-wire Interface (TWI) User Interface. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 746
35. Universal Asynchronous Receiver Transmitter (UART) . . . . . . . . . . . . . . . . . . . . . . . . . 761
35.1 Description . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 761
35.2 Embedded Characteristics . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 761
35.3 Block Diagram. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 761
SAM4S Series [DATASHEET]
Atmel-11100K-ATARM-SAM4S-Datasheet_09-Jun-15
1266
35.4 Product Dependencies . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 762
35.5 Functional Description. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 762
35.6 Universal Asynchronous Receiver Transmitter (UART) User Interface . . . . . . . . . . . . . . . . . . . . . 768
36. Universal Synchronous Asynchronous Receiver Transceiver (USART) . . . . . . . . . 779
36.1 Description . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 779
36.2 Embedded Characteristics . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 779
36.3 Block Diagram. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 781
36.4 I/O Lines Description. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 781
36.5 Product Dependencies . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 782
36.6 Functional Description. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 783
36.7 Universal Synchronous Asynchronous Receiver Transmitter (USART) User Interface . . . . . . . . . 814
37. Timer Counter (TC) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 851
37.1 Description . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 851
37.2 Embedded Characteristics . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 851
37.3 Block Diagram. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 852
37.4 Pin List . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 853
37.5 Product Dependencies . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 853
37.6 Functional Description. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 854
37.7 Timer Counter (T C) User Interface . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 875
38. High Speed Multimedia Card Interface (HSMCI) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 905
38.1 Description . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 905
38.2 Embedded Characteristics . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 905
38.3 Block Diagram. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 906
38.4 Application Block Diagram . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 907
38.5 Pin Name List . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 907
38.6 Product Dependencies . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 908
38.7 Bus Topology . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 908
38.8 High Speed MultiMedia Card Operations . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 91 1
38.9 SD/SDIO Card Operation . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 918
38.10 CE-ATA Operation . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 919
38.11 HSMCI Boot Operation Mode . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 920
38.12 HSMCI Transfer Done Timings. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 921
38.13 Register Write Protection . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 923
38.14 High Speed MultiMedia Card Interface (HSMCI) User Interface. . . . . . . . . . . . . . . . . . . . . . . . . . . 924
39. Pulse Width Modulation Controller (PWM) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 952
39.1 Description . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 952
39.2 Embedded Characteristics . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 953
39.3 Block Diagram. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 954
39.4 I/O Lines Description. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 954
39.5 Product Dependencies . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 954
39.6 Functional Description. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 957
39.7 Pulse Width Modulation Controller (PWM ) User Interface . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 980
40. USB Device Port (UDP) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 1028
40.1 Description . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 1028
40.2 Embedded Characteristics . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 1028
40.3 Block Diagram. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 1029
40.4 Product Dependencies . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 1030
1267
SAM4S Series [DATASHEET]
Atmel-11100K-ATARM-SAM4S-Datasheet_09-Jun-15
40.5 Typical Connection . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 1030
40.6 Functional Description. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 1032
40.7 USB Device Port (UDP) User Interface. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 1045
41. Analog Comparator Controller (ACC) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 1069
41.1 Description . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 1069
41.2 Embedded Characteristics . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 1069
41.3 Block Diagram. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 1069
41.4 Pin Name List . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 1070
41.5 Product Dependencies . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 1070
41.6 Functional Description. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 1071
41.7 Analog Comparator Controller (ACC) User Interface . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 1072
42. Analog-to-Digital Converter (ADC) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 1083
42.1 Description . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 1083
42.2 Embedded Characteristics . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 1084
42.3 Block Diagram. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 1085
42.4 Signal Description . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 1085
42.5 Product Dependencies . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 1086
42.6 Functional Description. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 1087
42.7 Analog-to-Digital (ADC) User Interface. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 1097
43. Digital-to-Analog Converter Controller (DACC) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 1121
43.1 Description . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 1121
43.2 Embedded Characteristics . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 1121
43.3 Block Diagram. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 1122
43.4 Signal Description . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 1122
43.5 Product Dependencies . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 1122
43.6 Functional Description. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 1124
43.7 Digital-to-Analog Converter Controller (DACC) User Interface. . . . . . . . . . . . . . . . . . . . . . . . . . . 1126
44. Electrical Characteristics . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 1142
44.1 Absolute Maximum Ratings. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 1142
44.2 Recommended Operating Conditions. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 1142
44.3 DC Characteristics . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 1143
44.4 Power Consumption . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 1149
44.5 Oscillator Characteristics. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 1163
44.6 PLLA, PLLB Characteristics . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 1169
44.7 USB Transceiver Characteristics . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 1170
44.8 12-bit ADC Characteristics . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 1172
44.9 12-bit DAC Characteristics . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 1181
44.10 Analog Comparator Characteristics . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 1183
44.11 Temperature Sensor . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 1183
44.12 AC Characteristics. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 1184
45. Mechanical Characteristics . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 1204
45.1 100-lead LQFP Mechanical Characteristics . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 1204
45.2 100-ball TFBGA Mechanical Characteristics. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 1205
45.3 100-ball VFBGA Mechanical Characteristics . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 1206
45.4 64-lead LQFP Mechanical Characteristics . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 1208
45.5 64-lead QFN Mechanical Characteristics . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 1210
45.6 64-ball WLCSP Mechanical Characteristics . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 1211
SAM4S Series [DATASHEET]
Atmel-11100K-ATARM-SAM4S-Datasheet_09-Jun-15
1268
45.7 48-lead LQFP Mechanical Characteristics . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 1214
45.8 48-lead QFN Mechanical Characteristics . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 1216
45.9 Soldering Profile . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 1217
45.10 Packaging Resources . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 1217
46. Marking . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 1218
47. Ordering Information . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 1219
48. Errata . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 1223
48.1 Errata SAM4SD32/SD16/SA16/S16/S8 Rev. A Parts. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 1223
48.2 Errata SAM4SD32/SD16/SA16/S16/S8 Rev. B Parts. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 1226
48.3 Errata SAM4S4/S2 Rev. A Parts. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 1229
48.4 Errata SAM4S4/S2 Rev. B Parts. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 1231
49. Revision History . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 1233
Table of Contents . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 1261
X
XXX
XX
ARM Connected Logo
Atmel Corporation 1600 Technology Drive, San Jose, CA 95110 USA T: (+1)(408) 441.0311 F: (+1)(408) 436.4200 | www.atmel.com
© 2015 Atmel Corporation. / Rev.: Atmel-11100K-ATARM-SAM4S-Datashe et_09-Jun-15.
Atmel®, Atmel logo and combinati ons thereof, Enabling Unlimited Possibilities®, and others are registered trademarks or trademarks of Atmel Corporation in U.S. and
other countries. ARM®, ARM Connected® logo, and others are the registered trademarks or trademarks of ARM Ltd. Windows® is a register ed trademark of
Microsoft Corporation in U.S. and/or other countries. Other terms and product names may be trademarks of others.
DISCLAIMER: The information in this document is provided in c onnec tion with Atmel products. No lic ense, ex press or implied, by estoppel or otherwise, to any intellectual property right
is granted by this document or in connection with the sale of Atmel products. EXCEPT AS SET FORTH IN THE ATMEL TERMS AND CONDITIONS OF SALES LOCATED ON THE
ATMEL WEBSITE, ATMEL ASSUMES NO LIABILITY WHATSOEVER AND DISCLAIMS ANY EXPRESS, IMPLIED OR STATUTORY WARRANTY RELATING TO ITS PRODUCTS
INCLUDING, BUT NOT LIMITED TO, THE IMPLIED WARRANTY OF MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE, OR NON-INFRINGEMENT. IN NO EVENT
SHALL ATMEL BE LIABLE FOR ANY DIRECT, INDIRECT, CONSEQUENTIAL, PUNITIVE, SPECIAL OR INCIDENTAL DAMAGES (INCLUDING, WITHOUT LIMITATION, DAMAGES
FOR LOSS AND PROFITS, BUSINESS INTE RRUPTION, OR LOSS OF INFO RMATION) ARISING OUT OF THE USE OR INABILIT Y TO USE THIS DOCU MENT, EVEN IF ATMEL HAS
BEEN ADVISED OF THE POSSIBILITY OF SUCH DAMAGES. Atmel makes no representations or warranties with respect to the accuracy or completeness of the contents of this
document and reserves the right to make changes to s pecifications and products descriptions at any time without notice. Atmel does not make any commitment to update the information
contained herein. Unless specifically provided otherwise, Atmel products are not suitable for, and shall not be used in, automotive applications. Atmel products are not intended,
authorized, or warranted for use as components in applications intended to support o r sustain life.
SAFETY-CRITICAL, MILITARY, AND AUTOMOTIVE APPLICATIONS DISCLAIMER: Atmel products are not designed for and will not be used in con nection with any applications where
the failure of such products would reasonably be expected to result in significant personal injury or death (“Safety-Critical Applications”) without an Atmel officer's specific written
consent. Safety-Critical Applications include, without limitation, life support devices and systems, equipment or systems for the operation of nuclear facilities and weapons systems.
Atmel products are not designed nor intended for use in military or aerospace applications or environments unless spec ifically designated by Atmel as military-grade. Atmel products are
not designed nor intended for use in automotive applications unless specifically designated by Atmel as automotive -grade.