APL531712BI-TRG - Anpec Electronics Corp.

Rev. A.4 - Mar., 2009

APL5317

www.anpec.com.tw1

ANPEC reserves the right to make changes to improve reliability or manufacturability without notice, and

advise customers to obtain the latest version of relevant information to verify before placing orders.

Selectable Adjustable/Fixed Low Dropout 300mA Linear Regulator

Features

•Wide Operating Voltage: 2.8~6V

•Low Dropout Voltage:

230mV(Typical) @ 300mA

•Guaranteed 300mA Output Current

•Two Modes for Setting Output Voltage

- Fixed Output Voltage: 1~5V

- Adjustable Output Voltage: 0.8~5.5V

•Current-Limit Protection with Foldback Current

•Internal Soft-Start

•Over-Temperature Protection

•Stable with Low ESR Ceramic Capacitor

•SOT-23-5 Package

•Lead Free and Green Devices Available

(RoHS Compliant)

General Description

The APL5317 is a low dropout linear regulator which only

needs a single input voltage supply from 2.8 to 6V, and it

can deliver current up to 300mA to a set output voltage. It

can work with low ESR ceramic capacitors that make it

ideal for using in the battery-powered applications, such

as notebook computers and cellular phones. Its typical

dropout voltage is only 230mV at 300mA loading. The

APL5317 provides two output voltage operation modes,

the fixed output voltage mode and the adjustable output

voltage, controlled by the SET pin for setting the output

voltage. The fixed output voltage mode sets the output to

a preset voltage (only 1.2V available now) in the chip by

connecting SET pin to the ground, and the adjustable

output voltage mode needs two resistors as a voltage

divider connected to SET pin to define the output. The

current-limit with current foldback and thermal shutdown

functions protect the device against current over-loads

and over temperature. The APL5317 is available in a SOT-

23-5 package.

Simplified Application Circuit

Applications

•Cellular Phones

•Portable and Battery-Powered Equipment

•Notebook and Personal Computers

1. Fixed Output Voltage Mode 2. Adjustable Output Voltage Mode

VIN

SHDN

GND

VOUT

SET

CIN 3

1 5

APL5317 VOUT

VIN

COUT

Pin Configuration

SHDN 3 4 SET

VIN 1

GND 2 5 VOUT

SOT-23-5

VIN

SHDN

GND

VOUT

SET

CIN 3

1 5

APL5317 VOUT

COUT

VIN

Rev. A.4 - Mar., 2009

APL5317

www.anpec.com.tw2

Symbol Parameter Rating Unit

VIN VIN Supply Voltage (VIN to GND) -0.3 ~ 6.5 V

VSHDN SHDN Input Voltage (SHDN to GND) -0.3 ~ 6.5 V

PD Power Dissipation Internally Limited W

TJ Junction Temperature -40 ~ 150 oC

TSTG Storage Temperature -65 ~ 150 oC

TSDR Maximum Lead Soldering Temperature, 10 Seconds 260 oC

Absolute Maximum Ratings (Note 3)

Thermal Characteristics

Symbol Parameter Typical Value Unit

θJA Thermal Resistance-Junction to Ambient (Note 4)

SOT-23-5

240 oC/W

θJC Thermal Resistance-Junction to Case SOT-23-5

130 oC/W

Note 4 : θJA is measured with the component mounted on a high effective thermal conductivity test board in free air.

Recommended Operating Conditions

Symbol Parameter Range Unit

VIN VIN Supply Voltage 2.8 ~ 6 V

VOUT Output Voltage 0.8 ~ 5.5 V

IOUT VOUT Output Current 0 ~ 300 mA

Ordering and Marking Information

Note : ANPEC lead-free products contain molding compounds/die attach materials and 100% matte tin plate termination finish; which

are fully compliant with RoHS. ANPEC lead-free products meet or exceed the lead-free requirements of IPC/JEDEC J-STD-020C for

MSL classification at lead-free peak reflow temperature. ANPEC defines “Green” to mean lead-free (RoHS compliant) and halogen

free (Br or Cl does not exceed 900ppm by weight in homogeneous material and total of Br and Cl does not exceed 1500ppm by

weight).

Note 1: For other voltage versions, please contact ANPEC for details.

Note 2: Because APL5317 and APL5317-12 are identical, the marking of APL5317 is same as APL5317-12.

Note 3: Absolute Maximum Ratings are those values beyond which the life of a device may be impaired. Exposure to absolute

maximum rating conditions for extended periods may affect device reliability.

Temperature Range

Package Code

Voltage Code

APL5317

Handling Code

Package Code

B : SOT-23-5

Operating Junction Temperature Range

I : -40 to 85 oC

Handling Code

TR : Tape & Reel

Voltage Code (Note 1)

12 : 1.2V

Assembly Material

G: Halogen and Lead Free Device

APL5317 B: 375X X - Date code

Assembly Material

APL5317-12 B: 375X X - Date code

Rev. A.4 - Mar., 2009

APL5317

www.anpec.com.tw3

Symbol Parameter Range Unit

CIN Input Capacitor 0.22 ~ 100 µF

OUT Output Capacitor 1.5 ~ 33 µF

TJ Junction Temperature -40 ~ 125 oC

Electrical Characteristics

Unless otherwise specified, these specifications apply over VIN = VOUT+1V (min VIN=2.8V), IOUT=0~300mA, CIN = 1µF, COUT = 2.2µF, TA

= -40 to 85oC. Typical values are at TA = 25oC.

Recommended Operating Conditions (Cont.)

APL5317

Symbol Parameter Test Conditions Min.

Typ.

Max.

Unit

VIN Input Voltage 2.8 - 6 V

VOUT Output Voltage Range 0.8 - 5.5 V

IQ Quiescent Current IOUT =10mA ~300mA - 135

160

µA

REF Reference Voltage Measured on SET,

VIN=VOUT+1V(min VIN=2.8V),

IOUT=10mA - 0.8 - V

Output Voltage Accuracy TA=25°C,

VIN=VOUT+1V(min VIN=2.8V),

IOUT=10mA -1 - +1 %

Output Voltage Accuracy TA=-40°C ~ 85°C,

VIN=VOUT+1V(min VIN=2.8V),

IOUT=0~300mA -2 - +2 %

VOUT = 2.5V, IOUT = 300mA - 230

360

VDROP Dropout Voltage VOUT = 3.3V, IOUT = 300mA - 170

300

PSRR Power Supply Ripple Rejection

Ratio f = 10kHz, IOUT = 300mA - 45 - dB

Noise f = 80Hz to 100kHz, IOUT = 300mA

- 160

- µVRMS

ILIMIT Current-Limit 450

600

- mA

ISHORT Foldback Current VOUT = 0V - 80 - mA

SHDN Input Voltage High 1.6 - -

SHDN Input Voltage Low - - 0.4 V

Shutdown VIN Supply Current SHDN = Low, VIN = 6V - 0.1 1 µA

SHDN Pull Low Resistance - 3 - MΩ

VOUT Discharge MOSFET RDS(ON) SHDN = Low - 60 - Ω

Over Temperature Threshold - 160

- °

Over Temperature Hysteresis - 40 - °C

SET Input Threshold for

Fixed/Adjustable Output Voltage

Mode - 100

- mV

SET Input Bias Current VSET=0.8V -100

- 100

TSS Soft-Start Interval - 60 - µs

Rev. A.4 - Mar., 2009

APL5317

www.anpec.com.tw4

Typical Operating Characteristics

Quiescent Current vs. Supply VoltageQuiescent Current vs. Junction Temperature

Quiescent Current vs. Output CurrentPSRR vs. Frequency

Dropout Voltage vs. Output CurrentDropout Voltage vs. Output Current

1000 10000 100000 1000000

PSRR (dB)

Frequency (Hz)

-60

-50

-40

-30

-20

-10

0VIN=3.3V, VOUT=1.2V

CIN=1µF, COUT=2.2µF

IOUT=300mA

Dropout Voltage, VDROP (mV)

Output Current, IOUT (mA)

VOUT=3.3V

0100 200 300

100

150

200

250

TJ=-50°C

TJ=0°C

TJ=25°C

TJ=125°C

TJ=75°C

Supply Voltage, VIN (V)

Quiescent Current, IQ (µA)

100

120

140

160

0 1 2 3 4 5 6 7

IOUT= 0mV

100

120

140

160

180

050 100 150 200 250 300

Output Current, IOUT (mA)

Quiescent Current, IQ (µA)

VIN=5.5V

VIN=4.5V

Output Current, IOUT (mA)

Dropout Voltage, VDROP (mV)

100

150

200

250

300

0100 200 300

VOUT=2.5V

TJ=-50°C

TJ=75°C

TJ=25°C

TJ=0°C

TJ=125°C

Junction Temperature, TJ (°C)

Quiescent Current, IQ (µA)

126

128

130

132

134

136

138

-50 -25 0 25 50 75 100 125

Rev. A.4 - Mar., 2009

APL5317

www.anpec.com.tw5

Typical Operating Characteristics (Cont.)

Loop Gain vs. Frequency Phase vs. Frequency

Current Limit vs. Junction Temperature

Loop Gain (dB)

Frequency (Hz)

IOUT=100mA

IOUT=300mA

VIN=3.3V, VOUT=1.2V, CIN=1µF, COUT=2.2µF

-40

-30

-20

-10

1000 10000 100000 1000000 1000 10000 100000 1000000

Frequency (Hz)

Phase (degree)

IOUT=100mA

IOUT=300mA

VIN=3.3V, VOUT=1.2V, CIN=1µF, COUT=2.2µF

100

120

140

160

Junction Temperature, TJ (°C)

Current Limit, ILIMIT (mA)

VIN=5V

450

500

550

600

650

-50 -25 025 50 75 100 125

Rev. A.4 - Mar., 2009

APL5317

www.anpec.com.tw6

Operating Waveforms

Load TransientLine Transient

CH1 : VOUT, 50mV/div, AC

CH2 : IOUT, 100mA/div, DC

Time : 100µs/div

CH1 : VIN, 1V/div, DC

CH2 : VOUT, 20mV/div, AC

Time : 100µs/div

EnableShutdown

CH1 : VOUT, 500mV/div

CH2 : VSHDN, 5V/div

CH3 : IOUT, 200mA/div

Time : 50µs/div

CH1 : VOUT, 500mV/Div

CH2 : VSHDN, 5V/Div

CH3 : IOUT, 200mA/Div DC

Time : 10µs/Div

VOUT

OUT

VIN=3.3V, CIN=1µF, COUT=2.2µF, TR=1µsCIN=1µF, COUT=2.2µF, TR=10µs, IOUT=10mA

VIN

OUT

VOUT

VSHDN

I OUT

VOUT

VSHDN

I OUT

Rev. A.4 - Mar., 2009

APL5317

www.anpec.com.tw7

Operating Waveforms (Cont.)

Power on Power off

CH1 : VIN, 2V/div

CH2 : VOUT, 500mV/div

CH3 : IOUT, 100mA/div

Time : 200µs/Div

CH1 : VIN, 2V/div

CH2 : VOUT,, 500mV/div,

CH3 : IOUT, 100mA/div

Time : 50ms/Div

Pin Description

NO. NAME FUNCTION

1 VIN Voltage supply input pin

2 GND Ground pin

3 SHDN Shutdown control pin, logic high: enable; logic low: shutdown

4 SET Connect this pin to the ground for fixed output voltage operation. Connect this pin to an external resi

stor

divider for adjustable output voltage mode operation.

5 VOUT Regulator output pin

VIN

VOUT

OUT

VIN

VOUT

OUT

Rev. A.4 - Mar., 2009

APL5317

www.anpec.com.tw8

Block Diagram

Typical Application Circuits

1. Fixed Output Voltage Mode

2.2µF/GRM155R60J225M Murata

VIN

SHDN

GND

VOUT

SET

CIN 3

1 5

APL5317 VOUT

VIN

2.2µF

1µF

Enable

Shutdown

COUT

Thermal

Shutdown

GND

SHDN

VOUT

SET

VIN

Shutdown

Logic Foldback

Current

Limit

100mV0.8V

3MΩLow

High

Rev. A.4 - Mar., 2009

APL5317

www.anpec.com.tw9

Typical Application Circuits (Cont.)

2. Adjustable Output Voltage Mode











+⋅=R2

10.8 VOUT

VIN

SHDN

GND

VOUT

SET

CIN 3

1 5

APL5317 VOUT

COUT

VIN

2.2µF

1µF

Enable

Shutdown

Rev. A.4 - Mar., 2009

APL5317

www.anpec.com.tw10

Function Description











+⋅=R2

10.8 VOUT

Where R1 is connected from VOUT to SET with Kelvin

sensing and R2 is connected from SET to GND. The rec-

ommended value of R2 is in the range of 100 to 100kΩ.

An error amplifier works with a temperature compensated

0.8V reference and an output PMOS regulates the output

to the presetting voltage. The error amplifier is designed

with high bandwidth and DC gain provides very fast tran-

sient response and less load regulation. It compares the

reference with the feedback voltage and amplifies the dif-

ference to drive the output PMOS which provides load

current from VIN to VOUT.

Internal Soft-Start

An internal soft-start function controls rising rate of the

output voltage to limit the surge current at start-up. The

typical soft-start interval is about 80µs.

Output Voltage Regulation

The APL5317 can work in either fixed or adjustable mode

by connecting the SET to GND or a resistor-divider which

receives the feedback voltage of the regulator. The output

voltage set by the resistor-divider is determined by:

Thermal Shutdown

A thermal shutdown circuit limits the junction tempera-

ture of APL5317. When the junction temperature exceeds

+160οC, a thermal sensor turns off the output PMOS, al-

lowing the device to cool down. The regulator regulates

the output again through initiation of a new soft-start cycle

after the junction temperature is cooled by 40οC.The ther-

mal shutdown is designed with a 40οC hysteresis to lower

the average junction temperature during continuous ther-

mal overload conditions, extending lifetime of the device.

For normal operation, device power dissipation should

be externally limited, so that junction temperature will not

exceed 125οC.

Under-Voltage Lock Out (UVLO)

The APL5317 monitors the input voltage to prevent wrong

logic control. The UVLO function initiates a soft-start pro-

cess after input voltage exceeds its rising UVLO thresh-

old during power on. The UVLO function also shuts off

the output when the input voltage falls below its falling

threshold. Typical UVLO hysteresis voltage is 0.8V.

Shutdown Control

The APL5317 has an active-low shutdown function. Force

SHDN high (>1.6V) enables the VOUT; force SHDN low

(<0.4V) disables the VOUT. SHDN is internally pulled low

by a resistor (3MΩ typical). If SHDN is not used, it will

connect to VIN for normal operation.

Rev. A.4 - Mar., 2009

APL5317

www.anpec.com.tw11

Application Information

Input Capacitor

The APL5317 needs a proper output capacitor to main-

tain circuit stability and improve transient response over

temperature and current. In order to insure the circuit

stability, the proper output capacitor value should be larger

than 2.2µF. With X5R and X7R dielectrics, 2.2µF is suffi-

cient at all operating temperatures. Large output capaci-

tor value can reduce noise and improve load-transient

response and PSRR, however, it also affects power on

issue. Equation (1) shows the relationship between the

maximum COUT value and VOUT.

Where the unit of COUT is µF and VOUT is V, Figure 1 shows

the curve of maximum output capacitor over the output

voltage. The output voltage range is from 0.8 to 5.5V and

the output capacitor value should be under the line. Out-

put capacitors must be placed at the load and the ground

pin as close as possible and the impedance of the layout

must be minimized.

The APL5317 maximum power dissipation depends on

the thermal resistance and temperature difference be-

tween the die junction and ambient air. The power dissi-

pation PD across the device is:

PD = (TJ - TA) / θJA

where (TJ-TA) is the temperature difference between the

junction and ambient air. θJA is the thermal resistance

between junction and ambient air. Assuming the TA=25oC

and maximum TJ=160oC (typical thermal limit threshold),

the maximum power dissipation is calculated as:

PD(max)=(160-25)/240

= 0.56(W)

For normal operation, do not exceed the maximum junc-

tion temperature rating of TJ = 125 oC. The calculated

power dissipation should less than:

PD =(125-25)/240

= 0.41(W)

The GND provides an electrical connection to ground and

channels heat away. Connect the GND to the ground by

using a large pad or a ground plane.

Figure 2 illustrates the layout. Below is a checklist for

your layout:

1. Please place the input capacitors close to the VIN.

2. Ceramic capacitors for load must be placed near

the load as close as possible.

3. To place APL5317 and output capacitors near the

load is good for performance.

4. Large current paths, the bold lines in figure 2,

must have wide tracks.

5. Divider resistor R1 and R2 must be placed near

the SET as close as possible.

The APL5317 requires proper input capacitors to supply

surge current during stepping load transients to prevent

the input rail from dropping. Because the parasitic induc-

tor from the voltage sources or other bulk capacitors to

the VIN limit the slew rate of the surge current, place the

Input capacitors near VIN as close as possible. Input ca-

pacitors should be larger than 1µF and a minimum ce-

ramic capacitor of 1µF is necessary.

)1.(..............................

-31COUT

OUT(max) =

Output Capacitor (µF)

Output voltage (V)

Figure 1

0 1 2 3 4 5 6

Output Capacitor

Operation Region and Power Dissipation

Layout Consideration

Rev. A.4 - Mar., 2009

APL5317

www.anpec.com.tw12

Application Information (Cont.)

PCB Layout Consideration (Cont.)

Figure 2

VIN

GND

VOUT

APL5317

VOUT

COUT

SET

LOAD

CIN

VIN

Recommended Minimum Footprint

0.05

0.02

0.1

0.038

0.076

Unit : Inch

SOT-23-5

Rev. A.4 - Mar., 2009

APL5317

www.anpec.com.tw13

Package Information

SOT-23-5

MAX.

0.057

0.051

0.024

0.006

0.009

0.0200.012

L0.30

0.08

0.30

0.60 0.012

0.95 BSC

1.90 BSC

0.22

0.50

0.037 BSC

0.075 BSC

0.003

MIN.

MILLIMETERS

0.00

0.90

SOT-23-5

MAX.

1.45

0.15

1.30

MIN.

0.000

0.035

INCHES

VIEW A

0.25

GAUGE PLANE

SEATING PLANE

A2A1

SEE

VIEW A

1.40

2.60

1.80

3.00

2.70 3.10 0.122

0.071

0.1180.102

0.055

0.016

Note : 1. Follow JEDEC TO-178 AA.

2. Dimension D and E1 do not include mold flash, protrusions or gate

burrs. Mold flash, protrusion or gate burrs shall not exceed 10 mil

per side.

Rev. A.4 - Mar., 2009

APL5317

www.anpec.com.tw14

Carrier Tape & Reel Dimensions

Application

A H T1 C d D W E1 F

178.0±2.00

50 MIN.

8.4+2.00

-0.00

13.0+0.50

-0.20

1.5 MIN.

20.2 MIN.

8.0±0.30

1.75±0.10

3.5±0.05

P0 P1 P2 D0 D1 T A0 B0 K0 SOT-23-5

4.0±0.10

2.0±0.05

1.5+0.10

-0.00

1.0 MIN.

0.6+0.00

-0.40

3.20±0.20

3.10±0.20

1.50±0.20

(mm)

Devices Per Unit

Package Type Unit Quantity

SOT-23-5 Tape & Reel 3000

OD0

BA0

SECTION B-B

SECTION A-A

OD1

Rev. A.4 - Mar., 2009

APL5317

www.anpec.com.tw15

Taping Direction Information

Classification Profile

SOT-23-5

USER DIRECTION OF FEED

Rev. A.4 - Mar., 2009

APL5317

www.anpec.com.tw16

Classification Reflow Profiles

Profile Feature Sn-Pb Eutectic Assembly Pb-Free Assembly

Preheat & Soak

Temperature min (Tsmin)

Temperature max (Tsmax)

Time (Tsmin to Tsmax) (ts)

100 °C

150 °C

60-120 seconds

150 °C

200 °C

60-120 seconds

Average ramp-up rate

(Tsmax to TP) 3 °C/second max. 3°C/second max.

Liquidous temperature (TL)

Time at liquidous (tL) 183 °C

60-150 seconds 217 °C

60-150 seconds

Peak package body Temperature

(Tp)* See Classification Temp in table 1 See Classification Temp in table 2

Time (tP)** within 5°C of the specified

classification temperature (Tc) 20** seconds 30** seconds

Average ramp-down rate (Tp to Tsmax)

6 °C/second max. 6 °C/second max.

Time 25°C to peak temperature 6 minutes max. 8 minutes max.

* Tolerance for peak profile Temperature (Tp) is defined as a supplier minimum and a user maximum.

** Tolerance for time at peak profile temperature (tp) is defined as a supplier minimum and a user maximum.

Table 2. Pb-free Process – Classification Temperatures (Tc)

Package

Thickness Volume mm3

<350 Volume mm3

350-2000 Volume mm3

>2000

<1.6 mm 260 °C 260 °C 260 °C

1.6 mm – 2.5 mm 260 °C 250 °C 245 °C

≥2.5 mm 250 °C 245 °C 245 °C

Table 1. SnPb Eutectic Process – Classification Temperatures (Tc)

Package

Thickness Volume mm3

<350 Volume mm3

≥350

<2.5 mm 235 °C 220 °C

≥2.5 mm 220 °C 220 °C

Reliability Test Program

Test item Method Description

SOLDERABILITY JESD-22, B102 5 Sec, 245°C

HOLT JESD-22, A108 1000 Hrs, Bias @ 125°C

PCT JESD-22, A102 168 Hrs, 100%RH, 2atm, 121°C

TCT JESD-22, A104 500 Cycles, -65°C~150°C

ESD MIL-STD-883-3015.7 VHBM≧2KV, VMM≧200V

Latch-Up JESD 78 10ms, 1tr≧100mA

Rev. A.4 - Mar., 2009

APL5317

www.anpec.com.tw17

Customer Service

Anpec Electronics Corp.

Head Office :

No.6, Dusing 1st Road, SBIP,

Hsin-Chu, Taiwan, R.O.C.

Tel : 886-3-5642000

Fax : 886-3-5642050

Taipei Branch :

2F, No. 11, Lane 218, Sec 2 Jhongsing Rd.,

Sindian City, Taipei County 23146, Taiwan

Tel : 886-2-2910-3838

Fax : 886-2-2917-3838