Rev. 1.1 January 2011 www.aosmd.com Page 1 of 10
AOZ8001K
Ultra-Low Capacitance TVS Diode Array
Not recommended for new designs.
General Description
The AOZ8001K is a transient voltage suppressor array
designed to protect high speed data lines from ESD and
lightning.
This device incorporates four surge rated, low capacitance
steering diodes and a TVS in a single package. During
transient conditions, the steering diodes direct the
transient to either the positive side of the power supply
line or to ground. They may be used to meet the ESD
immunity requirements of IEC 61000-4-2, Level 4.
The TVS diodes provide effective suppression of ESD
voltages: ±15kV (air discharge) and ±8kV (contact
discharge).
The AOZ8001K comes in a RoHS compliant SC-89
package and is rated over a -40°C to +85°C ambient
temperature range. It is compatible with both lead free
and SnPb assembly techniques.
The very small 1.7 x 1.7 x 0.6mm SC-89 package makes
it ideal for applications where PCB space is a premium.
The SC-89 has a flow through package design for an
optimal and user friendly PCB layout design. The small
size, low capacitance and high ESD protection makes
it ideal for protecting high speed video and data
communication interfaces.
Features
ESD protection for high-speed data lines:
IEC 61000-4-2, level 4 (ESD) immunity test
±15kV (air discharge) and ±8kV (contact discharge)
IEC 61000-4-5 (Lightning) 5A (8/20µs)
Human Body Model (HBM) ±15kV
Small package saves board space
Low insertion loss
Protects four I/O lines
Low capacitance from IO to Ground: 1.0pF
Low clamping voltage
Low operating voltage: 5.0V
Pb-free device
Green product
Applications
USB 2.0 power and data line protection
Video graphics cards
Monitors and flat panel displays
Digital Video Interface (DVI)
10/100/1000 Ethernet
Notebook computers
Typical Application
Figure 1. USB 2.0 High Speed Port
USB Controller
+5V
D+
D-
GND
+5V
USB Controlle
r
+5V
D+
D-
GND
AOZ8001K
Not recommended for new designs.
Rev. 1.1 January 2011 www.aosmd.com Page 2 of 10
AOZ8001K
Ordering Information
All AOS Products are offering in packaging with Pb-free plating and compliant to RoHS standards.
Please visit www.aosmd.com/web/quality/rohs_compliant.jsp for additional information.
Pin Configuration
Absolute Maximum Ratings
Exceeding the Absolute Maximum ratings may damage the device.
Notes:
1. IEC 61000-4-2 discharge with CDischarge = 150pF, RDischarge = 330.
2. Human Body Discharge per MIL-STD-883, Method 3015 CDischarge = 100pF, RDischarge = 1.5k.
Maximum Operating Ratings
Part Number Ambient Temperature Range Package Environmental
AOZ8001KI
-40°C to +85°C SC-89
RoHS Compliant
AOZ8001KIL RoHS Compliant
Green Product
1
2
3
6
5
4
CH1
VN
NC
NC
VP
CH2
SC-89
(Top View)
Parameter Rating
VP – VN 6V
Peak Pulse Current (IPP), tP = 8/20µs 5A
Storage Temperature (TS) -65°C to +150°C
ESD Rating per IEC61000-4-2, Contact(1) ±8kV
ESD Rating per IEC61000-4-2, Air(1) ±15kV
ESD Rating per Human Body Model(2) ±15kV
Parameter Rating
Junction Temperature (TJ) -40°C to +125°C
Rev. 1.1 January 2011 www.aosmd.com Page 3 of 10
AOZ8001K
Electrical Characteristics
TA = 25°C unless otherwise specified. Specifications in BOLD indicate a temperature range of -40°C to +85°C.
Notes:
3. The working peak reverse voltage, VRWM, should be equal to or greater than the DC or continuous peak operating voltage level.
4. VBR is measured at the pulse test current IT.
5. Measurements performed with no external capacitor on VP (pin 5 floating).
6. Measurements performed with VP biased to 3.3 Volts (pin 5 @ 3.3V).
7. Measurements performed using a 100ns Transmission Line Pulse (TLP) system.
Symbol Parameter Conditions Min. Typ. Max. Units
VRWM Reverse Working Voltage Between pin 5 and 2(3) 5.5 V
VBR Reverse Breakdown Volt-
age
IT = 1mA, between pins 5 and 2(4) 6.6 V
IRReverse Leakage Current VRWM = 5V, between pins 5 and 2 1.0 µA
VFDiode Forward Voltage IF = 15mA 0.70 0.85 1 V
VCL Channel Clamp Voltage
Positive Transients
Negative Transient
IPP = 1A, tp = 100ns, any I/O pin to Ground(5)(7)
10.00
-2.00
V
V
Channel Clamp Voltage
Positive Transients
Negative Transient
IPP = 5A, tp = 100ns, any I/O pin to Ground(5)(7)
11.00
-5.00
V
V
Channel Clamp Voltage
Positive Transients
Negative Transient
IPP = 12A, tp = 100ns, any I/O pin to Ground(5)(7)
14.50
-10.50
V
V
CjJunction Capacitance VR = 0V, f = 1MHz, between I/O pins(6) 0.1 0.12 pF
VR = 0V, f = 1MHz, any I/O pin to Ground(6) 1.0 1.17 pF
ΔCjChannel Input Capacitance
Matching
VR = 0V, f = 1MHz, between I/O pins(5) 0.03 pF
Rev. 1.1 January 2011 www.aosmd.com Page 4 of 10
AOZ8001K
Typical Performance Characteristics
Typical Variation of CIN vs VR
(f = 1MHz, T = 25C)
1.5
1.25
1.0
0.75
0.50
0.25
0
0
Vp = 3.3V
Input Voltage (V)
Clamping Voltage vs. Peak Pulse Current
(tperiod = 100ns, tr = 1ns)
15
14
13
12
11
10
9
Peak Pulse Current, IPP (A)
Clamping Voltage, VCL (V)
Forward Voltage vs. Forward Current
(tperiod = 100ns, tr = 1ns)
12
10
8
6
4
2
0
Forward Current (A)
F
orwar
d
V
o
l
tage
(V)
I/O – Gnd Insertion Loss (S21) vs. Frequency
(Vp = 3.3V)
1
0
-1
-2
-3
-4
-5
-6
-7
-8
-9
-10
Frequency (MHz)
Insertion Loss (dB)
1 10 100 1000
10010 1000
Analog Crosstalk (I/O–I/O) vs. Frequency
20
0
-20
-40
-60
-80
Frequency (MHz)
Insertion Loss (dB)
ESD Response (8kV Contact per IEC61000-4-2)
12345
0 2 4 6 8 10 12
0 2 4 6 8 10 12
Rev. 1.1 January 2011 www.aosmd.com Page 5 of 10
AOZ8001K
Connector
D+
D-
D+
D-
Protected IC
Flow Through Layout
Application Information
The AOZ8001K TVS is design to protect two data lines
from fast damaging transient over-voltage by clamping it
to a reference. When the transient on a protected data
line exceed the reference voltage the steering diode is
forward bias thus, conducting the harmful ESD transient
away from the sensitive circuitry under protection.
PCB Layout Guidelines
Printed circuit board layout is the key to achieving the
highest level of surge immunity on power and data lines.
The location of the protection devices on the PCB is the
simplest and most important design rule to follow. The
AOZ8001K devices should be located as close as possi-
ble to the noise source. The placement of the AOZ8001K
devices should be used on all data and power lines that
enter or exit the PCB at the I/O connector. In most
systems, surge pulses occur on data and power lines
that enter the PCB through the I/O connector. Placing
the AOZ8001K devices as close as possible to the noise
source ensures that a surge voltage will be clamped
before the pulse can be coupled into adjacent PCB
traces. In addition, the PCB should use the shortest
possible traces. A short trace length equates to low
impedance, which ensures that the surge energy will be
dissipated by the AOZ8001K device. Long signal traces
will act as antennas to receive energy from fields that are
produced by the ESD pulse. By keeping line lengths as
short as possible, the efficiency of the line to act as an
antenna for ESD related fields is reduced. Minimize inter-
connecting line lengths by placing devices with the most
interconnect as close together as possible. The protec-
tion circuits should shunt the surge voltage to either the
reference or chassis ground. Shunting the surge voltage
directly to the IC’s signal ground can cause ground
bounce. The clamping performance of TVS diodes on a
single ground PCB can be improved by minimizing the
impedance with relatively short and wide ground traces.
The PCB layout and IC package parasitic inductances
can cause significant overshoot to the TVS’s clamping
voltage. The inductance of the PCB can be reduced by
using short trace lengths and multiple layers with
separate ground and power planes. One effective
method to minimize loop problems is to incorporate a
ground plane in the PCB design. The AOZ8001K
ultra-low capacitance TVS is designed to protect four
high speed data transmission lines from transient
over-voltages by clamping them to a fixed reference.
The low inductance and construction minimizes voltage
overshoot during high current surges. When the voltage
on the protected line exceeds the reference voltage the
internal steering diodes are forward biased, conducting
the transient current away from the sensitive circuitry.
Good circuit board layout is critical for the suppression
of ESD induced transients. The following guidelines are
recommended:
1. Place the TVS near the IO terminals or connectors to
restrict transient coupling.
2. Fill unused portions of the PCB with ground plane.
3. Minimize the path length between the TVS and the
protected line.
4. Minimize all conductive loops including power and
ground loops.
5. The ESD transient return path to ground should be
kept as short as possible.
6. Never run critical signals near board edges.
7. Use ground planes whenever possible.
8. Avoid running critical signal traces (clocks, resets,
etc.) near PCB edges.
9. Separate chassis ground traces from components
and signal traces by at least 4mm.
10. Keep the chassis ground trace length-to-width ratio
<5:1 to minimize inductance.
11. Protect all external connections with TVS diodes.
Rev. 1.1 January 2011 www.aosmd.com Page 6 of 10
AOZ8001K
SIM Card Port Connection
IEEE1394 Port Connection
SIM
AOZ8001K
AOZ8001K
VCC
Reset
Clock
I/O
GND
IEEE 1394
PHY
IEEE 1394
Connector
TPBIASx
TPAx+
TPAx-
TPBx+
TPBx-
GND
AOZ8001K
AOZ8001K
Rev. 1.1 January 2011 www.aosmd.com Page 7 of 10
AOZ8001K
10/100 Ethernet Port Connection
Ethernet
Controller
RJ45
Connector
TRD0+
TRD0-
TRD1+
TRD1-
TRD2+
TRD2-
TRD3-
TRD3+
AOZ8001K
AOZ8001K
AOZ8001K
AOZ8001K
Rev. 1.1 January 2011 www.aosmd.com Page 8 of 10
AOZ8001K
Package Dimensions, SC-89
Notes:
1. All dimensions are in millimeters.
2. Dimension are inclusive of plating.
3. Package body sizes exclude mold flash and gate burrs. Mold flash at the non-lead sides should be less than 3 mils each.
4. Controlling dimension is millimeter, converted inch dimensions are not necessarily exact.
Symbols
A
A3
b
D
E1
e
E
L1
L2
L3
L4
b1
e1
θ
Dimensions in millimeters
RECOMMENDED LAND PATTERN
Min.
0.53
0.13
0.17
1.50
1.50
1.10
0.11
0.10
0.05
0.20
8°
UNIT: mm
Nom.
0.57
0.17
1.66
1.65
0.50 BSC
1.20
0.19
0.23
0.10
0.83 REF
0.27
10°
Max.
0.60
0.18
0.25
1.70
1.70
1.30
0.26
0.30
0.34
12°
Symbols
A
A3
b
D
E1
e
E
L1
L2
L3
L4
b1
e1
θ
Dimensions in inches
Min.
0.021
0.005
0.007
0.060
0.060
0.043
0.004
0.004
0.002
0.008
8°
Nom.
0.022
0.007
0.065
0.065
0.020 BSC
0.047
0.007
0.009
0.004
0.033 REF
0.011
10°
Max.
0.024
0.007
0.010
0.067
0.067
0.051
0.010
0.012
0.013
12°
D
E
L2
A
L1
L3
L4
A3
Pin 1
θ (4x) e1
b
b1
e
0.52
0.18
1.24
8
8
0.30
0.50
Rev. 1.1 January 2011 www.aosmd.com Page 9 of 10
AOZ8001K
Tape and Reel Dimensions, SC-89
Carrier Tape
Reel
Tape Size
8mm
Reel Size
ø180
M
ø180.00
±0.50
Package
SC-89, 6L
(8mm)
A0
1.78
±0.05
B0
1.78
±0.05
K0
0.89
±0.05
D0
0.50
±0.05
D1
1.50
±0.10
E
8.00
+0.30/-0.10
E1
1.75
±0.10
E2
3.50
±0.05
P0
4.00
±0.10
P1
4.00
±0.10
P2
2.00
±0.05
T
0.25
±0.05
N
ø60.50
UNIT: mm
G
M
W1
S
K
H
N
W
V
R
Trailer Tape
300mm min. or
75 empty pockets
Components Tape
Orientation in Pocket
Leader Tape
500mm min. or
125 empty pockets
Feeding Direction
D1
P1
P2
A0
D0
P0
E2 E
E1
T
K0
B0
W
9.00
±0.30
W1
11.40
±1.00
H
ø13.00
+0.50/-0.20
K
10.60
S
2.00
±0.50
G
ø9.00
R
5.00
V
18.00
Leader/Trailer and Orientation
Rev. 1.1 January 2011 www.aosmd.com Page 10 of 10
AOZ8001K
Part Marking
AOZ8001KIL
(SC-89)
LWB
Assembly Lot and
Location Code
Part Number Code,
Underscore Denotes Green Code
Week & Year Code
AOZ8001KI
(SC-89)
LWB
Assembly Lot and
Location Code
Part Number Code
Week & Year Code
As used herein:
1. Life support devices or systems are devices or
systems which, (a) are intended for surgical implant into
the body or (b) support or sustain life, and (c) whose
failure to perform when properly used in accordance
with instructions for use provided in the labeling, can be
reasonably expected to result in a significant injury of
the user.
2. A critical component in any component of a life
support, device, or system whose failure to perform can
be reasonably expected to cause the failure of the life
support device or system, or to affect its safety or
effectiveness.
Alpha & Omega Semiconductor reserves the right to make changes at any time without notice.
LIFE SUPPORT POLICY
ALPHA & OMEGA SEMICONDUCTOR PRODUCTS ARE NOT AUTHORIZED FOR USE AS CRITICAL
COMPONENTS IN LIFE SUPPORT DEVICES OR SYSTEMS.