General Description
The MAX5522–MAX5525 are dual, 10-bit, ultra-low-
power, voltage-output, digital-to-analog converters
(DACs) offering rail-to-rail buffered voltage outputs. The
DACs operate from a 1.8V to 5.5V supply and consume
less than 5µA, making the devices suitable for low-
power and low-voltage applications. A shutdown mode
reduces overall current, including the reference input
current, to just 0.18µA. The MAX5522–MAX5525 use a
3-wire serial interface that is compatible with SPI™,
QSPI™, and MICROWIRE™.
Upon power-up, the MAX5522–MAX5525 outputs are
driven to zero scale, providing additional safety for
applications that drive valves or for other transducers
that need to be off during power-up. The zero-scale
outputs enable glitch-free power-up.
The MAX5522 accepts an external reference input and
provides unity-gain outputs. The MAX5523 contains a
precision internal reference and provides a buffered
external reference output with unity-gain DAC outputs.
The MAX5524 accepts an external reference input and
provides force-sense outputs. The MAX5525 contains a
precision internal reference and provides a buffered
external reference output with force-sense DAC outputs.
The MAX5524/MAX5525 are available in a 4mm x 4mm
x 0.8mm, 12-pin, thin QFN package. The MAX5522/
MAX5523 are available in an 8-pin µMAX package. All
devices are guaranteed over the extended -40°C to
+85°C temperature range.
For 12-bit compatible devices, refer to the MAX5532–
MAX5535 data sheet. For 8-bit compatible devices,
refer to the MAX5512–MAX5515 data sheet.
Applications
Portable Battery-Powered Devices
Instrumentation
Automatic Trimming and Calibration in Factory
or Field
Programmable Voltage and Current Sources
Industrial Process Control and Remote
Industrial Devices
Remote Data Conversion and Monitoring
Chemical Sensor Cell Bias for Gas Monitors
Programmable LCD Bias
Features
♦Ultra-Low 5µA Supply Current
♦Shutdown Mode Reduces Supply Current to
0.18µA (max)
♦Single +1.8V to +5.5V Supply
♦Small 4mm x 4mm x 0.8mm Thin QFN Package
♦Internal Reference Sources 8mA of Current
(MAX5523/MAX5525)
♦Flexible Force-Sense-Configured Rail-to-Rail
Output Buffers
♦Fast 16MHz, 3-Wire, SPI-/QSPI-/MICROWIRE-
Compatible Serial Interface
♦TTL- and CMOS-Compatible Digital Inputs with
Hysteresis
♦Glitch-Free Outputs During Power-Up
MAX5522–MAX5525
Dual, Ultra-Low-Power,
10-Bit, Voltage-Output DACs
________________________________________________________________ Maxim Integrated Products 1
Ordering Information
19-3064; Rev 1; 12/04
For pricing, delivery, and ordering information, please contact Maxim/Dallas Direct! at
1-888-629-4642, or visit Maxim’s website at www.maxim-ic.com.
*EP = Exposed paddle (internally connected to GND).
PART TEMP RANGE PIN-PACKAGE
MAX5522EUA -40°C to +85°C 8 µMAX
MAX5523EUA -40°C to +85°C 8 µMAX
MAX5524ETC -40°C to +85°C 12 Thin QFN-EP*
MAX5525ETC -40°C to +85°C 12 Thin QFN-EP*
SPI and QSPI are trademarks of Motorola, Inc.
MICROWIRE is a trademark of National Semiconductor Corp.
Selector Guide
PART OUTPUTS REFERENCE TOP MARK
MAX5522EUA Unity gain External —
MAX5523EUA Unity gain Internal —
MAX5524ETC Force sense External AACK
MAX5525ETC Force sense Internal AACL
1
2
3
4
8
7
6
5
OUTA
GND
VDD
OUTBREFIN(MAX5522)
REFOUT(MAX5523)
DIN
SCLK
CS
MAX5522
MAX5523
µMAX
TOP VIEW
Pin Configurations
Pin Configurations continued at end of data sheet.
MAX5522–MAX5525
Dual, Ultra-Low-Power,
10-Bit, Voltage-Output DACs
2 _______________________________________________________________________________________
ABSOLUTE MAXIMUM RATINGS
ELECTRICAL CHARACTERISTICS
(VDD = +1.8V to +5.5V, OUT_ unloaded, TA= TMIN to TMAX, unless otherwise noted. Typical values are at TA= +25°C.)
Stresses beyond those listed under “Absolute Maximum Ratings” may cause permanent damage to the device. These are stress ratings only, and functional
operation of the device at these or any other conditions beyond those indicated in the operational sections of the specifications is not implied. Exposure to
absolute maximum rating conditions for extended periods may affect device reliability.
VDD to GND..............................................................-0.3V to +6V
OUTA, OUTB to GND.................................-0.3V to (VDD + 0.3V)
FBA, FBB to GND.......................................-0.3V to (VDD + 0.3V)
SCLK, DIN, CS to GND ..............................-0.3V to (VDD + 0.3V)
REFIN, REFOUT to GND ............................-0.3V to (VDD + 0.3V)
Continuous Power Dissipation (TA= +70°C)
12-Pin Thin QFN (derate 16.9mW/°C above +70°C).....1349mW
8-Pin µMAX (derate 5.9mW/°C above +70°C) .............471mW
Operating Temperature Range ...........................-40°C to +85°C
Storage Temperature Range .............................-65°C to +150°C
Junction Temperature......................................................+150°C
Lead Temperature (soldering, 10s) .................................+300°C
PARAMETER SYMBOL CONDITIONS MIN TYP MAX UNITS
STATIC ACCURACY (MAX5522/MAX5524 EXTERNAL REFERENCE)
Resolution N 10 Bits
VDD = 5V, VREF = 4.096V ±1±4
Integral Nonlinearity (Note 1) INL VDD = 1.8V, VREF = 1.024V ±1±4LSB
Guaranteed monotonic, VDD = 5V,
VREF = 4.096V ±0.2 ±1
Differential Nonlinearity (Note 1) DNL Guaranteed monotonic, VDD = 1.8V,
VREF = 1.024V ±0.2 ±1
LSB
VDD = 5V, VREF = 4.096V ±1±20
Offset Error (Note 2) VOS VDD = 1.8V, VREF = 1.024V ±1±20 mV
Offset-Error Temperature Drift ±2 µV/°C
VDD = 5V, VREF = 4.096V ±0.5 ±2
Gain Error (Note 3) GE VDD = 1.8V, VREF = 1.024V ±0.5 ±2LSB
Gain-Error Temperature
Coefficient ±4 ppm/°C
Power-Supply Rejection Ratio PSRR 1.8V ≤ VDD ≤ 5.5V 85 dB
STATIC ACCURACY (MAX5523/MAX5525 INTERNAL REFERENCE)
Resolution N 10 Bits
VDD = 5V, VREF = 3.9V ±1±4
Integral Nonlinearity (Note 1) INL VDD = 1.8V, VREF = 1.2V ±1±4LSB
Guaranteed monotonic, VDD = 5V,
VREF = 3.9V ±0.2 ±1
Differential Nonlinearity (Note 1) DNL Guaranteed monotonic, VDD = 1.8V,
VREF = 1.2V ±0.2 ±1
LSB
VDD = 5V, VREF = 3.9V ±1±20
Offset Error (Note 2) VOS VDD = 1.8V, VREF = 1.2V ±1±20 mV
Offset-Error Temperature Drift ±2 µV/°C
VDD = 5V, VREF = 3.9V ±0.5 ±2
Gain Error (Note 3) GE VDD = 1.8V, VREF = 1.2V ±0.5 ±2LSB
Gain-Error Temperature
Coefficient ±4 ppm/°C
MAX5522–MAX5525
Dual, Ultra-Low-Power,
10-Bit, Voltage-Output DACs
_______________________________________________________________________________________ 3
ELECTRICAL CHARACTERISTICS (continued)
(VDD = +1.8V to +5.5V, OUT_ unloaded, TA= TMIN to TMAX, unless otherwise noted. Typical values are at TA= +25°C.)
PARAMETER SYMBOL CONDITIONS MIN TYP MAX UNITS
Power-Supply Rejection Ratio PSRR 1.8V ≤ VDD ≤ 5.5V 85 dB
REFERENCE INPUT (MAX5522/MAX5524)
Reference-Input Voltage Range VREFIN 0V
DD V
Normal operation 4.1 MΩ
Reference-Input Impedance RREFIN In shutdown 2.5 GΩ
REFERENCE OUTPUT (MAX5523/MAX5525)
No external load, VDD = 1.8V 1.197 1.214 1.231
No external load, VDD = 2.5V 1.913 1.940 1.967
No external load, VDD = 3V 2.391 2.425 2.459
Initial Accuracy VREFOUT
No external load, VDD = 5V 3.828 3.885 3.941
V
Output-Voltage Temperature
Coefficient VTEMPCO TA = -40°C to +85°C (Note 4) 12 30 ppm/°C
Line Regulation VREFOUT < VDD - 200mV (Note 5) 2 200 µV/V
0 ≤ IREFOUT ≤ 1mA, sourcing, VDD = 1.8V,
VREF = 1.2V 0.3 2
0 ≤ IREFOUT ≤ 8mA, sourcing, VDD = 5V,
VREF = 3.9V 0.3 2
Load Regulation
-150µA ≤ IREFOUT ≤ 0, sinking 0.2
µV/µA
0.1Hz to 10Hz, VREF = 3.9V 150
10Hz to 10kHz, VREF = 3.9V 600
0.1Hz to 10Hz, VREF = 1.2V 50
Output Noise Voltage
10Hz to 10kHz, VREF = 1.2V 450
µVP-P
VDD = 5V 30
Short-Circuit Current (Note 6) VDD = 1.8V 14 mA
Capacitive Load Stability Range (Note 7) 0 to 10 nF
Thermal Hysteresis (Note 8) 200 ppm
REFOUT unloaded, VDD = 5V 5.4
Reference Power-Up Time
(from Shutdown) REFOUT unloaded, VDD = 1.8V 4.4 ms
Long-Term Stability 200 ppm/
1khrs
DAC OUTPUTS (OUTA, OUTB)
Capacitive Driving Capability CL1000 pF
VDD = 5V, VOUT set to full scale, OUT
shorted to GND, source current 65
VDD = 5V VOUT set to 0V, OUT shorted to
VDD, sink current 65
VDD = 1.8V, VOUT set to full scale OUT
shorted to GND, source current 14
Short-Circuit Current (Note 6)
VDD = 1.8V, VOUT set to 0V, OUT shorted to
VDD, sink current 14
mA
MAX5522–MAX5525
Dual, Ultra-Low-Power,
10-Bit, Voltage-Output DACs
4 _______________________________________________________________________________________
ELECTRICAL CHARACTERISTICS (continued)
(VDD = +1.8V to +5.5V, OUT_ unloaded, TA= TMIN to TMAX, unless otherwise noted. Typical values are at TA= +25°C.)
PARAMETER SYMBOL CONDITIONS MIN TYP MAX UNITS
VDD = 5V 3
Coming out of shutdown
(MAX5522/MAX5524) VDD = 1.8V 3.8
DAC Power-Up Time
Coming out of standby
(MAX5523/MAX5525)
VDD = 1.8V to
5.5V 0.4
µs
Output Power-Up Glitch CL = 100pF 10 mV
FB_ Input Current 10 pA
DIGITAL INPUTS (SCLK, DIN, CS)
4.5V ≤ VDD ≤ 5.5V 2.4
2.7V < VDD ≤ 3.6V 2.0
Input High Voltage VIH
1.8V ≤ VDD ≤ 2.7V 0.7 x VDD
V
4.5V ≤ VDD ≤ 5.5V 0.8
2.7V < VDD ≤ 3.6V 0.6Input Low Voltage VIL
1.8V ≤ VDD ≤ 2.7V 0.3 x VDD
V
Input Leakage Current IIN (Note 9) ±0.05 ±0.5 µA
Input Capacitance CIN 10 pF
DYNAMIC PERFORMANCE
Voltage-Output Slew Rate SR Positive and negative (Note 10) 10 V/ms
Voltage-Output Settling Time 0.1 to 0.9 of full scale to within 0.5 LSB
(Note 10) 660 µs
VDD = 5V 80
0.1Hz to 10Hz VDD = 1.8V 55
VDD = 5V 620
Output Noise Voltage
10Hz to 10kHz VDD = 1.8V 476
µVP-P
POWER REQUIREMENTS
Supply Voltage Range VDD 1.8 5.5 V
VDD = 5V 7.0 8.0
VDD = 3V 6.4 8.0MAX5523/MAX5525
VDD = 1.8V 7.0 8.0
VDD = 5V 3.8 5.0
VDD = 3V 3.8 5.0
Supply Current (Note 9) IDD
MAX5522/MAX5524
VDD = 1.8V 4.7 6.0
µA
VDD = 5V 3.3 4.5
VDD = 3V 2.8 4.0
Standby Supply Current IDDSD MAX5523/MAX5525
(Note 9) VDD = 1.8V 2.4 3.5
µA
Shutdown Supply Current IDDPD (Note 9) 0.05 0.25 µA
MAX5522–MAX5525
Dual, Ultra-Low-Power,
10-Bit, Voltage-Output DACs
_______________________________________________________________________________________ 5
Note 1: Linearity is tested within codes 24 to 1020.
Note 2: Offset is tested at code 24.
Note 3: Gain is tested at code 1023. For the MAX5524/MAX5525, FB_ is connected to its respective OUT_.
Note 4: Guaranteed by design. Not production testsed
Note 5: VDD must be a minimum of 1.8V.
Note 6: Outputs can be shorted to VDD or GND indefinitely, provided that package power dissipation is not exceeded.
Note 7: Optimal noise performance is at 2nF load capacitance.
Note 8: Thermal hysteresis is defined as the change in the initial +25°C output voltage after cycling the device from TMAX to TMIN.
Note 9: All digital inputs at VDD or GND.
Note 10: Load = 10kΩin parallel with 100pF, VDD = 5V, VREF = 4.096V (MAX5522/MAX5524) or VREF = 3.9V (MAX5523/MAX5525).
TIMING CHARACTERISTICS
(VDD = +4.5V to +5.5V, TA= TMIN to TMAX, unless otherwise noted. Typical values are at TA= +25°C.)
PARAMETER SYMBOL CONDITIONS MIN TYP MAX UNITS
TIMING CHARACTERISTICS (VDD = 4.5V to 5.5V )
Serial Clock Frequency fSCLK 0 16.7 MHz
DIN to SCLK Rise Setup Time tDS 15 ns
DIN to SCLK Rise Hold Time tDH 0ns
SCLK Pulse-Width High tCH 24 ns
SCLK Pulse-Width Low tCL 24 ns
CS Pulse-Width High tCSW 100 ns
SCLK Rise to CS Rise Hold Time tCSH 0ns
CS Fall to SCLK Rise Setup Time tCSS 20 ns
SCLK Fall to CS Fall Setup tCSO 0ns
CS Rise to SCK Rise Hold Time tCS1 20 ns
TIMING CHARACTERISTICS
(VDD = +1.8V to +5.5V, TA= TMIN to TMAX, unless otherwise noted. Typical values are at TA= +25°C.)
PARAMETER SYMBOL CONDITIONS MIN TYP MAX UNITS
TIMING CHARACTERISTICS (VDD = 1.8V to 5.5V )
Serial Clock Frequency fSCLK 0 10 MHz
DIN to SCLK Rise Setup Time tDS 24 ns
DIN to SCLK Rise Hold Time tDH 0ns
SCLK Pulse-Width High tCH 40 ns
SCLK Pulse-Width Low tCL 40 ns
CS Pulse-Width High tCSW 150 ns
SCLK Rise to CS Rise Hold Time tCSH 0ns
CS Fall to SCLK Rise Setup Time tCSS 30 ns
SCLK Fall to CS Fall Setup tCSO 0ns
CS Rise to SCK Rise Hold Time tCS1 30 ns
MAX5522–MAX5525
Dual, Ultra-Low-Power,
10-Bit, Voltage-Output DACs
6 _______________________________________________________________________________________
Typical Operating Characteristics
(VDD = 5.0V, VREF = 4.096V (MAX5522/MAX5524), VREF = 3.9V (MAX5523/MAX54525), TA = +25°C, unless otherwise noted.)
SUPPLY CURRENT vs. SUPPLY VOLTAGE
(MAX5522/MAX5524)
MAX5522 toc01
SUPPLY VOLTAGE (V)
SUPPLY CURRENT (µA)
5.55.04.0 4.52.5 3.0 3.52.0
0.5
1.0
1.5
2.0
2.5
3.0
3.5
4.0
4.5
5.0
0
1.5 6.0
SUPPLY CURRENT vs. TEMPERATURE
(MAX5522/MAX5524)
MAX5522 toc02
TEMPERATURE (°C)
SUPPLY CURRENT (µA)
603510-15
0.5
1.0
1.5
2.0
2.5
3.0
3.5
4.0
4.5
5.0
0
-40 85
SUPPLY CURRENT vs. SUPPLY VOLTAGE
(MAX5523/MAX5525)
MAX5522 toc03
SUPPLY VOLTAGE (V)
SUPPLY CURRENT (µA)
5.55.04.0 4.52.5 3.0 3.52.0
1
2
3
4
5
6
7
8
9
10
0
1.5 6.0
SUPPLY CURRENT vs. TEMPERATURE
(MAX5523/MAX5525)
MAX5522 toc04
TEMPERATURE (°C)
SUPPLY CURRENT (µA)
603510-15
1
2
3
4
5
6
7
8
9
10
0
-40 85
SHUTDOWN SUPPLY CURRENT
vs. TEMPERATURE (MAX5522/MAX5524)
MAX5522 toc05
TEMPERATURE (°C)
SHUTDOWN SUPPLY CURRENT (nA)
603510-15
1
10
100
1000
0.1
-40 85
SHUTDOWN SUPPLY CURRENT
vs. TEMPERATURE (MAX5523/MAX5525)
MAX5522 toc06
TEMPERATURE (°C)
SHUTDOWN SUPPLY CURRENT (nA)
603510-15
1
10
100
1000
0.1
-40 85
STANDBY SUPPLY CURRENT
vs. TEMPERATURE (MAX5523/MAX5525)
MAX5522 toc07
TEMPERATURE (°C)
STANDBY SUPPLY CURRENT (µA)
603510-15
0.5
1.0
1.5
2.0
2.5
3.0
3.5
4.0
4.5
5.0
0
-40 85
VREF = 3.9V
VREF = 2.4V
VREF = 1.9V VREF = 1.2V
SUPPLY CURRENT
vs. CLOCK FREQUENCY
MAX5522 toc08
FREQUENCY (kHz)
SUPPLY CURRENT (µA)
1000010001001010.1
10
100
1000
1
0.01 100000
CS = LOGIC LOW
CODE = 0
VDD = 5V
VDD = 1.8V
SUPPLY CURRENT
vs. LOGIC INPUT VOLTAGE
MAX5522 toc09
LOGIC INPUT VOLTAGE (V)
SUPPLY CURRENT (mA)
4.54.03.0 3.51.0 1.5 2.0 2.50.5
0.5
1.0
1.5
2.0
2.5
3.0
3.5
4.0
4.5
5.0
0
0 5.0
VDD = 5V
ALL DIGITAL INPUTS
SHORTED TOGETHER
MAX5522–MAX5525
Dual, Ultra-Low-Power,
10-Bit, Voltage-Output DACs
_______________________________________________________________________________________ 7
INL vs. INPUT CODE
(VDD = VREF = 1.8V)
MAX5522 toc10
DIGITAL INPUT CODE
INL (LSB)
1000800200 400 600
-1.0
-0.8
-0.6
-0.4
-0.2
0
0.2
0.4
-1.2
0 1200
INL vs. INPUT CODE
(VDD = VREF = 5V)
MAX5522 toc11
DIGITAL INPUT CODE
INL (LSB)
1000800200 400 600
-1.0
-0.8
-0.6
-0.4
-0.2
0
0.2
0.4
-1.2
0 1200
DNL vs. INPUT CODE
(VDD = VREF = 1.8V)
MAX5522 toc12
DIGITAL INPUT CODE
DNL (LSB)
1000800600400200
-0.02
-0.01
0
0.01
0.02
0.03
0.04
0.05
0.06
-0.03
0 1200
DNL vs. INPUT CODE
(VDD = VREF = 5V)
MAX5522 toc13
DIGITAL INPUT CODE
DNL (LSB)
1000800600400200
-0.02
-0.01
0
0.01
0.02
0.03
0.04
-0.03
01200
OFFSET VOLTAGE
vs. TEMPERATURE
MAX5522 toc14
TEMPERATURE (°C)
OFFSET VOLTAGE (mV)
603510-15
0.2
0.4
0.6
0.8
1.0
-1.0
-0.2
0
-40 85
-0.4
-0.6
-0.8
VDD = 5V
VREF = 3.9V
GAIN ERROR CHANGE
vs. TEMPERATURE
MAX5522 toc15
TEMPERATURE (°C)
GAIN ERROR CHANGE (LSB)
603510-15
-0.08
-0.06
-0.04
-0.02
0
0.02
0.04
0.06
0.08
0.10
-0.10
-40 85
VDD = 5V
VREF = 3.9V
DIGITAL FEEDTHROUGH RESPONSE
MAX5522 toc16
20µs/div
CS
5V/div
SCLK
5V/div
DIN
5V/div
OUT
50mV/div
ZERO SCALE
DAC OUTPUT LOAD REGULATION
vs. OUTPUT CURRENT
MAX5522 toc17
DAC OUTPUT CURRENT
(µ
A
)
DAC OUTPUT VOLTAGE (V)
8006004002000-200-400-600-800
0.6042
0.6044
0.6046
0.6048
0.6050
0.6040
-1000 1000
VDD = 1.8V
DAC CODE = MIDSCALE
VREF = 1.2V
DAC OUTPUT LOAD REGULATION
vs. OUTPUT CURRENT
MAX5522 toc18
DAC OUTPUT CURRENT (mA)
DAC OUTPUT VOLTAGE (V)
86-8 -6 -4 0 2-2 4
1.9405
1.9410
1.9415
1.9420
1.9425
1.9430
1.9435
1.9440
1.9400
-10 10
VDD = 5.0V
DAC CODE = MIDSCALE
VREF = 3.9V
Typical Operating Characteristics (continued)
(VDD = 5.0V, VREF = 4.096V (MAX5522/MAX5524), VREF = 3.9V (MAX5523/MAX54525), TA = +25°C, unless otherwise noted.)
MAX5522–MAX5525
Dual, Ultra-Low-Power,
10-Bit, Voltage-Output DACs
8 _______________________________________________________________________________________
Typical Operating Characteristics (continued)
(VDD = 5.0V, VREF = 4.096V (MAX5522/MAX5524), VREF = 3.9V (MAX5523/MAX54525), TA = +25°C, unless otherwise noted.)
DAC OUTPUT VOLTAGE
vs. OUTPUT SOURCE CURRENT
MAX5522 toc19
OUTPUT SOURCE CURRENT (mA)
OUTPUT VOLTAGE (V)
1010.1000.010
1
2
3
4
5
0
0.001 100
VREF = VDD
CODE = MIDSCALE
VDD = 5V
VDD = 3V
VDD = 1.8V
DAC OUTPUT VOLTAGE
vs. OUTPUT SINK CURRENT
MAX5522 toc20
OUTPUT SINK CURRENT (mA)
DAC OUTPUT VOLTAGE (V)
1010.10.01
0.5
1.0
1.5
2.0
2.5
3.0
3.5
4.0
4.5
5.0
0
0.001 100
VREF = VDD
CODE = MIDSCALE
VDD = 5V
VDD = 3V
VDD = 1.8V
OUTPUT LARGE-SIGNAL STEP RESPONSE
(VDD = 1.8V, VREF = 1.2V)
MAX5522 toc21
100µs/div
VOUT
200mV/div
OUTPUT LARGE-SIGNAL STEP RESPONSE
(VDD = 5V, VREF = 3.9V)
MAX5522 toc22
200µs/div
VOUT
500mV/div
POWER-UP OUTPUT VOLTAGE GLITCH
MAX5522 toc24
20ms/div
VOUT
10mV/div
VDD
2V/div
MAJOR CARRY OUTPUT VOLTAGE GLITCH
(CODE 7FFh TO 800h)
(VDD = 5V, VREF = 3.9V)
MAX5522 toc25
100µs/div
VOUT
AC-COUPLED
5mV/div
REFERENCE OUTPUT VOLTAGE
vs. TEMPERATURE
MAX5522 toc26
TEMPERATURE (°C)
REFERENCE OUTPUT VOLTAGE (V)
6035-15 10
3.905
3.910
3.915
3.920
3.925
3.930
3.935
3.940
3.900
-40 85
VDD = 5V
REFERENCE OUTPUT VOLTAGE
vs. REFERENCE OUTPUT CURRENT
MAX5522 toc27
REFERENCE OUTPUT CURRENT (µA)
REFERENCE OUTPUT VOLTAGE (V)
7500550035001500
1.215
1.216
1.217
1.218
1.219
1.220
1.214
-500
VDD = 1.8V
MAX5522–MAX5525
Dual, Ultra-Low-Power,
10-Bit, Voltage-Output DACs
_______________________________________________________________________________________ 9
Typical Operating Characteristics (continued)
(VDD = 5.0V, VREF = 4.096V (MAX5522/MAX5524), VREF = 3.9V (MAX5523/MAX54525), TA = +25°C, unless otherwise noted.)
REFERENCE OUTPUT VOLTAGE
vs. REFERENCE OUTPUT CURRENT
MAX5522 toc28
REFERENCE OUTPUT CURRENT (µA)
REFERENCE OUTPUT VOLTAGE (V)
14,50012,0009500700045002000
3.89
3.90
3.91
3.92
3.88
-500
VDD = 5V
REFERENCE OUTPUT VOLTAGE
vs. SUPPLY VOLTAGE
MAX5522 toc29
SUPPLY VOLTAGE (V)
REFERENCE OUTPUT VOLTAGE (mV)
5.55.04.0 4.52.5 3.0 3.52.0
1.21732
1.21734
1.21736
1.21738
1.21740
1.21742
1.21744
1.21746
1.21748
1.21750
1.21730
1.5 6.0
REFERENCE LINE-TRANSIENT RESPONSE
(VREF = 1.2V)
MAX5522 toc30
100µs/div
2.8V
VDD
1.8V
VREF
500mV/div
REFERENCE LINE-TRANSIENT RESPONSE
(VREF = 3.9V)
MAX5522 toc31
100µs/div
5.5V
VDD
4.5V
VREF
500mV/div
3.9V
REFERENCE LOAD TRANSIENT
(VDD = 1.8V)
MAX5522 toc32
200µs/div
REFOUT
SOURCE
CURRENT
0.5mA/div
VREF
500mV/div
REFERENCE LOAD TRANSIENT
(VDD = 5V)
MAX5522 toc33
200µs/div
REFOUT
SOURCE
CURRENT
0.5mA/div
VREF
500mV/div
3.9V
REFERENCE LOAD TRANSIENT
(VDD = 1.8V)
MAX5522 toc34
200µs/div
REFOUT
SINK
CURRENT
50µA/div
VREF
500mV/div
MAX5522–MAX5525
Dual, Ultra-Low-Power,
10-Bit, Voltage-Output DACs
10 ______________________________________________________________________________________
Typical Operating Characteristics (continued)
(VDD = 5.0V, VREF = 4.096V (MAX5522/MAX5524), VREF = 3.9V (MAX5523/MAX54525), TA = +25°C, unless otherwise noted.)
REFERENCE PSRR vs. FREQUENCY
MAX5522 toc37
FREQUENCY (kHz)
POWER-SUPPLY REJECTION RATIO (dB)
100100.1 1
10
20
30
40
50
60
70
80
0
0.01 1000
VDD = 5V
REFERENCE OUTPUT NOISE
(0.1Hz TO 10Hz) (VDD = 1.8V, VREF = 1.2V)
MAX5522 toc38
1s/div
100µV/div
REFERENCE OUTPUT NOISE
(0.1Hz TO 10Hz) (VDD = 5V, VREF = 3.9V)
MAX5522 toc39
1s/div
100µV/div
DAC-TO-DAC CROSSTALK
MAX5522 toc40
400µs/div
OUTB
AC-COUPLED
10mV/div
OUTA
1V/div
OUTB AT FULL SCALE
REFERENCE PSRR vs. FREQUENCY
MAX5522 toc36
FREQUENCY (kHz)
POWER-SUPPLY REJECTION RATIO (dB)
100100.1 1
10
20
30
40
50
60
70
80
0
0.01 1000
VDD = 1.8V
REFERENCE LOAD TRANSIENT
(VDD = 5V)
MAX5522 toc35
200µs/div
REFOUT
SINK
CURRENT
100µA/div
VREF
500mV/div
3.9V
MAX5522–MAX5525
Dual, Ultra-Low-Power,
10-Bit, Voltage-Output DACs
______________________________________________________________________________________ 11
Pin Description
PIN
MAX5522
MAX5523 MAX5524 MAX5525
NAME FUNCTION
1111 CS Active-Low Digital Chip-Select Input
2222 SCLK Serial-Interface Clock Input
3333 DINSerial-Interface Data Input
4 — 4 — REFIN Reference Input
— 4 — 4 REFOUT Reference Output
— — 5, 11 5, 11 N.C. No Connection. Leave N.C. inputs unconnected
(floating) or connected to GND.
— — 6 6 FBB Channel B Feedback Input
5577 OUTBChannel B Analog Voltage Output
6688 V
DD Power Input. Connect VDD to a 1.8V to 5.5V power
supply. Bypass VDD to GND with a 0.1µF capacitor.
7799 GNDGround
8 8 10 10 OUTA Channel A Analog Voltage Output
— — 12 12 FBA Channel A Feedback Input
— — EP EP
Exposed Paddle
Exposed Paddle. Connect EP to GND.
10-BIT DAC
DAC
REGISTER
OUTA
REFIN
GND
MAX5522
INPUT
REGISTER
POWER-
DOWN
CONTROL
CONTROL
LOGIC
AND
SHIFT
REGISTER
10-BIT DAC
DAC
REGISTER
OUTB
SCLK
VDD
DIN
CS
INPUT
REGISTER
Functional Diagrams
MAX5522–MAX5525
Dual, Ultra-Low-Power,
10-Bit, Voltage-Output DACs
12 ______________________________________________________________________________________
Functional Diagrams (continued)
10-BIT DAC
2-BIT
PROGRAMMABLE
REFERENCE
DAC
REGISTER
OUTA
REF
BUF
GND
MAX5523
REFOUT
INPUT
REGISTER
POWER-
DOWN
CONTROL
CONTROL
LOGIC
AND
SHIFT
REGISTER
10-BIT DAC
DAC
REGISTER
OUTB
SCLK
VDD
DIN
CS
INPUT
REGISTER
10-BIT DAC
DAC
REGISTER
OUTA
REFIN
GND
MAX5524
INPUT
REGISTER
POWER-
DOWN
CONTROL
CONTROL
LOGIC
AND
SHIFT
REGISTER
10-BIT DAC
DAC
REGISTER
OUTB
FBA
FBB
SCLK
VDD
DIN
CS
INPUT
REGISTER
Detailed Description
The MAX5522–MAX5525 dual, 10-bit, ultra-low-power,
voltage-output DACs offer rail-to-rail buffered voltage
outputs. The DACs operate from a 1.8V to 5.5V supply
and require only 5µA (max) supply current. These
devices feature a shutdown mode that reduces overall
current, including the reference input current, to just
0.18µA (max) The MAX5523/MAX5525 include an inter-
nal reference that saves additional board space and
can source up to 8mA, making it functional as a system
reference. The 16MHz, 3-wire serial interface is com-
patible with SPI, QSPI, and MICROWIRE protocols.
When VDD is applied, all DAC outputs are driven to
zero scale with virtually no output glitch. The MAX5522/
MAX5523 output buffers are configured in unity gain
and come in µMAX packages. The MAX5524/MAX5525
output buffers are configured in force sense allowing
users to externally set voltage gains on the output (an
output-amplifier inverting input is available). The
MAX5524/MAX5525 come in 4mm x 4mm thin QFN
packages.
Digital Interface
The MAX5522–MAX5525 use a 3-wire serial interface
that is compatible with SPI/QSPI/MICROWIRE protocols
(Figures 1 and 2).
The MAX5522–MAX5525 include a single, 16-bit, input
shift register. Data loads into the shift register through
the serial interface. CS must remain low until all 16 bits
are clocked in. The 16 bits consist of 4 control bits
(C3–C0), 10 data bits (D9–D0) (Table 1), and 2 sub-bits
(S1 and S0). D9–D0 are the DAC data bits and S1 and
S0 are the sub-bits. The sub-bits must be set to zero for
proper operation. Following the control bits, data loads
MSB first, D9–D0. The control bits C3–C0 control the
MAX5522–MAX5525, as outlined in Table 2.
Each DAC channel includes two registers: an input reg-
ister and a DAC register. The input register holds input
data. The DAC register contains the data updated to
the DAC output.
The double-buffered register configuration allows any
of the following:
•Loading the input registers without updating the DAC
registers
•Updating the DAC registers from the input registers
•Updating all the input and DAC registers simultaneously
MAX5522–MAX5525
Dual, Ultra-Low-Power,
10-Bit, Voltage-Output DACs
______________________________________________________________________________________ 13
Functional Diagrams (continued)
10-BIT DAC
2-BIT
PROGRAMMABLE
REFERENCE
DAC
REGISTER
OUTA
REF
BUF
GND
MAX5525
REFOUT
INPUT
REGISTER
POWER-
DOWN
CONTROL
CONTROL
LOGIC
AND
SHIFT
REGISTER
10-BIT DAC
DAC
REGISTER
OUTB
FBA
FBB
SCLK
VDD
DIN
CS
INPUT
REGISTER
MAX5522–MAX5525
Dual, Ultra-Low-Power,
10-Bit, Voltage-Output DACs
14 ______________________________________________________________________________________
tCSW
tCSS
tCS0 tDH
tCL
tCS1
tCSH
tCH
tDS
SCLK
DIN
CS
C2 C1 S0
C3
Figure 1. Timing Diagram
16151413121110987654321SCLK
C3 C2 C1 C0 D9 D8 D7 D6 D5 D4 D3 D2 D1 D0 S1 S0DIN
CONTROL BITS DATA BITS SUB-BITS
COMMAND
EXECUTED
CS
Figure 2. Register Loading Diagram
Table 1. Serial Write Data Format
Sub-bits S1 to S0 must be set to zero for proper operation.
CONTROL DATA BITS
MSB LSB
C3 C2 C1 C0 D9 D8 D7 D6 D5 D4 D3 D2 D1 D0 S1 S0
MAX5522–MAX5525
Dual, Ultra-Low-Power,
10-Bit, Voltage-Output DACs
______________________________________________________________________________________ 15
Table 2. Serial-Interface Programming Commands
CONTROL BITS
INPUT DATA
SUB-BITS
C3
C2 C1 C0
D9–D0
S1 AND S0
FUNCTION
0000
XXXXXXXXXX
00 No operation; command is ignored.
0 0 0 1 10-bit data 00 Load input register A from shift register; DAC registers unchanged;
DAC outputs unchanged.
0 0 1 0 10-bit data 00 Load input register B from shift register; DAC registers unchanged;
DAC outputs unchanged.
0 0 1 1 — — Command reserved. Do not use.
0 1 0 0 — — Command reserved. Do not use.
0 1 0 1 — — Command reserved. Do not use.
0 1 1 0 — — Command reserved. Do not use.
0 1 1 1 — — Command reserved. Do not use.
1 0 0 0 10-bit data 00
Load DAC registers A and B from respective input registers; DAC
outputs A and B updated; MAX5523/MAX5525 enter normal
operation if in standby or shutdown; MAX5522/MAX5524 enter
normal operation if in shutdown.
1 0 0 1 10-bit data 00
Load input register A and DAC register A from shift register; DAC
output A updated; Load DAC register B from input register B; DAC
output B updated; MAX5523/MAX5525 enter normal operation if in
standby or shutdown; MAX5522/MAX5524 enter normal operation
if in shutdown.
1 0 1 0 10-bit data 00
Load input register B and DAC register B from shift register; DAC
output B updated; Load DAC register A from input register A; DAC
output A updated; MAX5523/MAX5525 enter normal operation if in
standby or shutdown; MAX5522/MAX5524 enter normal operation
if in shutdown.
1 0 1 1 — — Command reserved. Do not use.
1100 D9, D8,
XXXXXXXX 00
MAX5523/MAX5525 enter standby*, MAX5522/MAX5524 enter
shutdown. For the MAX5523/MAX5525, D9 and D8 configure the
internal reference voltage (Table 3).
1101 D9, D8,
XXXXXXXX 00
MAX5522–MAX5525 enter normal operation; DAC outputs reflect
existing contents of DAC registers. For the MAX5523/MAX5525,
D9 and D8 configure the internal reference voltage (Table 3).
1110 D9, D8,
XXXXXXXX 00
MAX5522–MAX5525 enter shutdown; DAC outputs set to high
impedance. For the MAX5523/MAX5525, D9 and D8 configure the
internal reference voltage (Table 3).
1 1 1 1 10-bit data 00
Load input registers A and B and DAC registers A and B from shift
register; DAC outputs A and B updated; MAX5523/MAX5525 enter
normal operation if in standby or shutdown; MAX5522/MAX5524
enter normal operation if in shutdown.
X = Don’t care.
*Standby mode can be entered from normal operation only. It is not possible to enter standby mode from shutdown.
Power Modes
The MAX5522–MAX5525 feature two power modes to
conserve power during idle periods. In normal opera-
tion, the device is fully operational. In shutdown mode,
the device is completely powered down, including the
internal voltage reference in the MAX5523/MAX5525.
The MAX5523/MAX5525 also offer a standby mode in
which all circuitry is powered down except the internal
voltage reference. Standby mode keeps the reference
powered up while the remaining circuitry is shut down,
allowing it to be used as a system reference. It also
helps reduce the wake-up delay by not requiring the ref-
erence to power up when returning to normal operation.
Shutdown Mode
The MAX5522–MAX5525 feature a software-program-
mable shutdown mode that reduces the supply current
and the interface input-current to 0.18µA (max). Writing
an input control word with control bits C[3:0] = 1110
(Table 2) places the device in shutdown mode. In shut-
down, the MAX5522/MAX5524 reference input and DAC
output buffers go high impedance. Placing the MAX5523/
MAX5525 into shutdown turns off the internal reference
and the DAC output buffers go high impedance. The seri-
al interface still remains active for all devices.
Table 2 shows several commands that bring the
MAX5522–MAX5525 back to normal operation. The
power-up time from shutdown is required before the
DAC outputs are valid.
Note: For the MAX5523/MAX5525, standby mode can-
not be entered directly from shutdown mode. The
device must be brought into normal operation first
before entering standby mode.
Standby Mode (MAX5523/MAX5525 Only)
The MAX5523/MAX5525 feature a software-program-
mable standby mode that reduces the typical supply
current to 3µA (max). Standby mode powers down all
circuitry except the internal voltage reference. Place
the device in standby mode by writing an input control
word with control bits C[3:0] = 1100 (Table 2). The
internal reference and serial interface remain active
while the DAC output buffers go high impedance.
For the MAX5523/MAX5525, standby mode cannot be
entered directly from shutdown mode. The device must
be brought into normal operation first before entering
standby mode. To enter standby from shutdown, issue
the command to return to normal operation followed
immediately by the command to go into standby.
Table 2 shows several commands that bring the
MAX5523/MAX5525 back to normal operation. When
transitioning from standby mode to normal operation,
only the DAC power-up time is required before the DAC
outputs are valid.
Reference Input
The MAX5522/MAX5524 accept a reference with a volt-
age range extending from 0 to VDD. The output voltage
(VOUT) is represented by a digitally programmable volt-
age source as:
VOUT = (VREF x N / 256) x gain
where N is the numeric value of the DAC’s binary input
code (0 to 1023), VREF is the reference voltage, gain is
the externally set voltage gain for the MAX5524, and
gain is one for the MAX5522.
In shutdown mode, the reference input enters a high-
impedance state with an input impedance of 2.5GΩ(typ).
Reference Output
The MAX5523/MAX5525 internal voltage reference is
software configurable to one of four voltages. Upon
power-up, the default reference voltage is 1.214V.
Configure the reference voltage using D8 and D9 data
bits (Table 3) when the control bits are as follows C[3:0]
= 1100, 1101, or 1110 (Table 2). VDD must be kept at a
minimum of 200mV above VREF for proper operation.
MAX5522–MAX5525
Dual, Ultra-Low-Power,
10-Bit, Voltage-Output DACs
16 ______________________________________________________________________________________
Table 3. Reference Output Voltage
Programming
D9 D8 REFERENCE VOLTAGE (V)
0 0 1.214
0 1 1.940
1 0 2.425
1 1 3.885
MAX5522–MAX5525
Dual, Ultra-Low-Power,
10-Bit, Voltage-Output DACs
______________________________________________________________________________________ 17
Applications Information
1-Cell and 2-Cell Circuits
See Figure 3 for an illustration of how to power the
MAX5522–MAX5525 with either one lithium-ion battery
or two alkaline batteries. The low current consumption
of the devices make the MAX5522–MAX5525 ideal for
battery-powered applications.
Programmable Current Source
See the circuit in Figure 4 for an illustration of how to
configure the MAX5524/MAX5525 as a programmable
current source for driving an LED. The MAX5524/
MAX5525 drive a standard NPN transistor to program
the current source. The current source (ILED) is defined
in the equation in Figure 4.
REFIN
MAX5524
MAX6006
(1µA, 1.25V
SHUNT
REFERENCE) GND
+1.25V
0.01µF
536kΩ
VDD
DAC
VOUT
NDAC IS THE NUMERIC VALUE
OF THE DAC INPUT CODE.
VOUT (1.22mV / LSB)
1.8V ≤ VALKALINE ≤ 3.3V
2.2V ≤ VLITHIUM ≤ 3.3V
VOUT = VREFIN × NDAC
1024
0.1µF
Figure 3. Portable Application Using Two Alkaline Cells or One Lithium Coin Cell
R
2N3904
NDAC IS THE NUMERIC VALUE
OF THE DAC INPUT CODE.
ILED
REFIN
LED
1/2 MAX5524
V+
DAC
VOUT
ILED = VREFIN × NDAC
1024 × R
FB
Figure 4. Programmable Current Source Driving an LED
R
FB
NDAC IS THE NUMERIC VALUE
OF THE DAC INPUT CODE.
IT
REFIN
1/2 MAX5524
DAC
VOUT
VOUT = VBIAS + (IT × R)
VOUT
VBIAS
TRANSDUCER
VBIAS = VREFIN × NDAC
1024
Figure 5. Transimpedance Configuration for a Voltage-Biased
Current-Output Transducer
MAX5522–MAX5525
Voltage Biasing a
Current-Output Transducer
See the circuit in Figure 5 for an illustration of how to
configure the MAX5524/MAX5525 to bias a current-out-
put transducer. In Figure 5, the output voltage of the
MAX5524/MAX5525 is a function of the voltage drop
across the transducer added to the voltage drop
across the feedback resistor R.
Unipolar Output
Figure 6 shows the MAX5524 in a unipolar output con-
figuration with unity gain. Table 4 lists the unipolar out-
put codes.
Bipolar Output
The MAX5524 output can be configured for bipolar
operation as shown in Figure 7. The output voltage is
given by the following equation:
VOUT_ = VREFIN x [(NA- 512) / 512]
where NArepresents the decimal value of the DAC’s
binary input code. Table 5 shows the digital codes (off-
set binary) and the corresponding output voltage for
the circuit in Figure 7.
Configurable Output Gain
The MAX5524/MAX5525 have force-sense outputs,
which provide a connection directly to the inverting ter-
minal of the output op amp, yielding the most flexibility.
The advantage of the force-sense output is that specific
gains can be set externally for a given application. The
gain error for the MAX5524/MAX5525 is specified in a
unity-gain configuration (op-amp output and inverting ter-
minals connected), and additional gain error results from
external resistor tolerances. Another advantage of the
force-sense DAC is that it allows many useful circuits to
be created with only a few simple external components.
An example of a custom fixed gain using the MAX5524/
MAX5525 force-sense output is shown in Figure 8. In
this example, R1 and R2 set the gain for VOUTA.
VOUTA = [(VREFIN x NA) / 1024] x [1 + (R2 / R1)]
where NArepresents the numeric value of the DAC
input code.
Self-Biased Two-Electrode
Potentiostat Application
See the circuit in Figure 10 for an illustration of how to
use the MAX5525 to bias a two-electrode potentiostat
on the input of an ADC.
Power Supply and
Bypassing Considerations
Bypass the power supply with a 4.7µF capacitor in parallel
with a 0.1µF capacitor to GND. Minimize lengths to reduce
lead inductance. If noise becomes an issue, use shielding
and/or ferrite beads to increase isolation. For the thin QFN
package, connect the exposed pad to ground.
Dual, Ultra-Low-Power,
10-Bit, Voltage-Output DACs
18 ______________________________________________________________________________________
Table 4. Unipolar Code Table (Gain = +1)
DAC CONTENTS
MSB LSB ANALOG OUTPUT
1111 1111 1100 +VREF (1023/1024)
1000 0000 0100 +VREF (513/1024)
1000 0000 0000 +VREF (512/1024) = +VREF/2
0111 1111 1100 +VREF (511/1024)
0000 0000 0100 +VREF (1/1024)
0000 0000 0000 0V
Table 5. Bipolar Code Table (Gain = +1)
DAC CONTENTS
MSB LSB ANALOG OUTPUT
1111 1111 1100 +VREF (511/512)
1000 0000 0100 +VREF (1/512)
1000 0000 0000 0V
0111 1111 1100 -VREF (1/512)
0000 0000 0100 -VREF (511/512)
0000 0000 0000 -VREF (512/512) = -VREF
NA IS THE DAC INPUT CODE
(0 TO 1023 DECIMAL).
REFIN
MAX5524
OUT_
FB_
VOUT = VREFIN × NA
1024
DAC
Figure 6. Unipolar Output Circuit
Layout Considerations
Digital and AC transient signals coupling to GND can
create noise at the output. Use proper grounding tech-
niques, such as a multilayer board with a low-inductance
ground plane. Wire-wrapped boards and sockets are not
recommended. For optimum system performance, use
printed circuit (PC) boards. Good PC board ground lay-
out minimizes crosstalk between DAC outputs, reference
inputs, and digital inputs. Reduce crosstalk by keeping
analog lines away from digital lines.
MAX5522–MAX5525
Dual, Ultra-Low-Power,
10-Bit, Voltage-Output DACs
______________________________________________________________________________________ 19
REFIN
1/2 MAX5524
OUT_
VOUT
FB_
V+
10kΩ10kΩ
V-
DAC
Figure 7. Bipolar Output Circuit
NDACA IS THE NUMERIC VALUE
OF THE DAC A INPUT CODE.
REFIN DAC
VOUT1
VOUT1 = VREFIN × NDACA
1024
(
1 + R2
)
R1
NDACB IS THE NUMERIC VALUE
OF THE DAC B INPUT CODE.
VOUT2 = VREFIN × NDACB
1024
VOUTA
1/2 MAX5524
FBA
DAC
VOUT2
VOUTB
FBB
R2
R1
Figure 8. Separate Force-Sense Outputs Create Unity and
Greater-than-Unity DAC Gains Using the Same Reference
H
L
FB W
NDAC IS THE NUMERIC VALUE OF THE DAC INPUT CODE.
NPOT IS THE NUMERIC VALUE OF THE POT INPUT CODE.
REFIN
1/2 MAX5524
MAX5401
SOT-POT
100kΩ
DAC VOUT
5PPM/°C
RATIOMETRIC
TEMPCO
1.8V ≤ VDD ≤ 5.5V
VOUT
VOUT = VREFIN × NDAC
1024
(
1 + 255 - NPOT
)
255
SCLK
DIN
CS2
CS1
Figure 9. Software-Configurable Output Gain
DAC
BAND
GAP
TO ADC
OUT
REFOUT
REF
1/2 MAX5525
TO ADC
TO ADC
FB
WE
SENSOR
CE
IFRF
CL
Figure 10. Self-Biased Two-Electrode Potentiostat Application
MAX5522–MAX5525
Dual, Ultra-Low-Power,
10-Bit, Voltage-Output DACs
20 ______________________________________________________________________________________
Chip Information
TRANSISTOR COUNT: 10,688
PROCESS: BiCMOS
DAC
BAND
GAP
TO ADC
OUTA
REFOUT
MAX5525
TO ADC
REF
FBA
WE
SENSOR
CE
IFRF
CL
DAC OUTB
REF
FBB
Figure 11. Driven Two-Electrode Potentiostat Application
12
FBA
11
N.C.
10
OUTA
45
N.C.
6
FBB
1
2SCLK
3
9
8
7DIN
GND
VDD
OUTB
MAX5524
MAX5525
CS
REFIN(MAX5524)
REFOUT(MAX5525)
THIN QFN
TOP VIEW
Pin Configurations (continued)
MAX5522–MAX5525
Dual, Ultra-Low-Power,
10-Bit, Voltage-Output DACs
______________________________________________________________________________________ 21
24L QFN THIN.EPS
C1
2
21-0139
PACKAGE OUTLINE
12, 16, 20, 24L THIN QFN, 4x4x0.8mm
Package Information
(The package drawing(s) in this data sheet may not reflect the most current specifications. For the latest package outline information,
go to www.maxim-ic.com/packages.)
MAX5522–MAX5525
Dual, Ultra-Low-Power,
10-Bit, Voltage-Output DACs
22 ______________________________________________________________________________________
Package Information (continued)
(The package drawing(s) in this data sheet may not reflect the most current specifications. For the latest package outline information,
go to www.maxim-ic.com/packages.)
C
2
2
21-0139
PACKAGE OUTLINE
12, 16, 20, 24L THIN QFN, 4x4x0.8mm
MAX5522–MAX5525
Dual, Ultra-Low-Power,
10-Bit, Voltage-Output DACs
Maxim cannot assume responsibility for use of any circuitry other than circuitry entirely embodied in a Maxim product. No circuit patent licenses are
implied. Maxim reserves the right to change the circuitry and specifications without notice at any time.
Maxim Integrated Products, 120 San Gabriel Drive, Sunnyvale, CA 94086 408-737-7600 ____________________ 23
© 2004 Maxim Integrated Products Printed USA is a registered trademark of Maxim Integrated Products.
Package Information (continued)
(The package drawing(s) in this data sheet may not reflect the most current specifications. For the latest package outline information,
go to www.maxim-ic.com/packages.)
8LUMAXD.EPS
PACKAGE OUTLINE, 8L uMAX/uSOP
1
1
21-0036 J
REV.DOCUMENT CONTROL NO.APPROVAL
PROPRIETARY INFORMATION
TITLE:
MAX
0.043
0.006
0.014
0.120
0.120
0.198
0.026
0.007
0.037
0.0207 BSC
0.0256 BSC
A2 A1
c
eb
A
L
FRONT VIEW SIDE VIEW
E H
0.6±0.1
0.6±0.1
ÿ 0.50±0.1
1
TOP VIEW
D
8
A2 0.030
BOTTOM VIEW
16∞
S
b
L
H
E
D
e
c
0∞
0.010
0.116
0.116
0.188
0.016
0.005
8
4X S
INCHES
-
A1
A
MIN
0.002
0.950.75
0.5250 BSC
0.25 0.36
2.95 3.05
2.95 3.05
4.78
0.41
0.65 BSC
5.03
0.66
6∞0∞
0.13 0.18
MAX
MIN
MILLIMETERS
-1.10
0.05 0.15
α
α
DIM