© Semiconductor Components Industries, LLC, 2012
February, 2012 − Rev. 2
1Publication Order Number:
EVBUM2072/D
NB4N121KMNGEVB
NB4N121KMNGEVB
Evaluation Board User's
Manual
Board Name: NB4N121KMNGEVB
Device Name: NB4N121KMN
Description
The NB4N121K Evaluation Board was designed to
provide a flexible and convenient platform to quickly
evaluate, characterize and verify the performance and
operation of the device under test NB4N121K.
The NB4N121K is a Clock differential input fanout
distribution device with 1 to 21 HCSL level differential
outputs, optimized for ultra low propagation delay variation.
The NB4N121K is designed with HCSL clock distribution
for FBDIMM applications in mind. Inputs can accept
differential LVPECL, CML, or LVDS levels. Single−ended
LVPECL, CML, LVCMOS or LVTTL levels are accepted
with the proper VREFAC supply. Clock input pins
incorporate an internal 50 W on die termination resistors.
Output drive current at IREF (Pin 1) for 1X load is selected
by connecting a 0 kW to 1 kW external resistor to GND. To
drive a 2X load, connect the IREF Pin 1 through 20 kW to 50
kW external resistors. The NB4N121K specifically
guarantees low output–to–output skews. Optimal design,
layout, and processing minimize skew within a device and
from device to device. System designers can take advantage
of the NB4N121K’s performance to distribute low skew
clocks across the backplane or the motherboard. The device
is packaged in a low profile 8 x 8 mm 52−pin QFN package.
This user’s manual provides detailed information on the
board’s contents, layout and use. The manual should be used
in conjunction with the NB4N121K data sheet which
contains full technical details on device specifications and
operation.
Board Features
•Fully assembled evaluation board with Device−Under−
Test (DUT) soldered mounted. The device may be
demounted and replaced by a test fixture socket
(ANTARES Test Technology, P/N FP0052QN0805C,
3350 Scott Blvd., Bldg 58, Santa Clara, CA 95054,
Phone: (408) 988−6800, www.antares−att.com,) for
manual insertion of different sample device units.
•Accommodates the electrical characterization of the
NB4N121K in the QFN52 package
•Equal length input and output data lines to minimize
skew measurement calibration.
•Default 1X output drive (50 W load) with optional 2X
load capability (25 W load) selectable by installing
pulldown resistors and adjusting board RREF setting on
IREF (pin1). Adjustable RREF resistor potentiometer for
fine tuning output drive current (amplitude) levels.
•Single + 3.3 V Operation for direct LOW Impedance
probe connection (50 W to GND).
Appendix 1: Device Information
Appendix 2: Schematics
Appendix 3: IREF Pin Load Plot
Appendix 4: Bill of Materials, Board Stackup
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EVAL BOARD USER’S MANUAL
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Board Map
Figure 1. Front Figure 2. Back
Not Used
VCC and GND Supply Connections C2 and C3 Power Supply Caps
RREF Trimpot
0 to 50 kW
Front Notes:
1. VCCO and VCC contacts must be ganged and
connected together to the positive 3.3 V supply.
2. CLKSEL is not used (no SMA).
Back Notes:
1. C2 and C3 are power supply caps
2. RREF trimpot is connected from IREF to GND to
select output drive for 1X (0 to 1 kW; Short to
GND) or 2X loading (20 K to 50 kW; Open or
Short to VCC). See Appendix 3: Device IREF pin 1
load plot of RREF vs. IREF current
3. Back D.U.T. area detail: (See Figure 3) Odd
numbered resistors R17 to R81 are populated for 1X
load. Even numbered resistors are not populated.
The even numbered resistors may be repopulated
with 50 W (to GND) components to convert the
board to 2X load use with 50 W scope input
impedance loading (presents a 25 W parallel load to
the device outputs). Even numbered “series shorting”
resistors R17 to R81 are populated zero ohm value.
These may be repopulated with a series resistor
value to improve signal integrity. Components C1,
C4, C5, C6, and C7 are 0.01 mF bypass caps.
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Figure 3. Back D.U.T. Area Detail
Test and Measurements Setup Details:
Step 1: Basic Equipment
•Signal Generator
•Oscilloscope
•Power Supply
•Voltmeter
•Matched High−Speed Coax Cables with SMA
Connectors
Step 2: Board Test Connections Setup: (1X Load configuration, IREF pin shorted to GND)
Figure 4. NB4N121KMNGEVB Evaluation Board Connector Configuration
OscilloscopeNB4L121KSignal
Generator
VCC, VCCO (Note 1)
OUT
OUT
IN
IN
CLK
CLK
VTCLK
VTCLK
Qx
Qx
Trigger
50 W Coax
50 W Coax
50 W Coax
50 W Coax
IREF
GND
Table 1. Power Supply Connections
Positive and GND supplies must be connected to anvil clips for proper operation. Bridge VCC and VCCO board connection
together.
Board Connector Pin Supply Value Device Pin
VCC, VCCO (Note 1) VCC 3.0 to 3.6 V 7, 26, 39, 52
GND GND 0 V 2
IREF (Note 2) RREF to GND For 1x loading: 0 to 50 kW
For 2x loading: 20 K to 50 kW
1
EXPOSED PAD Vias GND Thermal Conduit Exposed Pad
1. Short together and connect to VCC supply. See Appendix 4: Board Lamination Stackup
2. See Appendix 3: Device IREF pin 1 Load Plot of RREF vs. IREF Current
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Table 1. Input/Output Board to Device Pin Connections
Board Connector Device Pin Name Device Pin
VTCLK VTCLK 3
CLK CLK 4
CLK CLK 5
VTCLK VTCLK 6
Q20 Q20 8
Q20 Q20 9
Q19 Q19 10
Q19 Q19 11
Q18 Q18 12
Q19 Q19 13
Q17 Q17 14
Q17 Q17 15
Q16 Q16 16
Q16 Q16 17
Q15 Q15 18
Q15 Q15 19
Q14 Q14 20
Q14 Q14 21
Q13 Q13 22
Q13 Q13 23
Q12 Q12 24
Q12 Q12 25
Q11 Q11 27
Q11 Q11 28
Q10 Q10 29
Q10 Q10 30
Q9 Q9 31
Q9 Q9 32
Q8 Q8 33
Q8 Q8 34
Q7 Q7 35
Q7 Q7 36
Q6 Q6 37
Q6 Q6 38
Q5 Q5 40
Q5 Q5 41
Q4 Q4 42
Q4 Q4 43
Q3 Q3 44
Q3 Q3 45
Q2 Q2 46
Q2 Q2 47
Q1 Q1 48
Q1 Q1 49
Q0 Q0 50
Q0 Q0 51
Input Pins and Signals
CLK and CLK pins require differential LVPECL levels
swinging around an acceptable common mode voltage per
datasheet. Internal impedance matching resistor of 50 W is
provided for driver termination from input pin to the
respective VTx pin. Typically the VTx pins are connected to
a VTT of VCC−2.0 V. The differential inputs can be driven
single ended per the datasheet.
Output Pins and Signals
Output pairs in use must always be balance in each pins
loading and termination even if only one side of an output
pair is delivered to receiver or scope. Do not unbalance an
output pair by loading or probing only one line. Unused
outputs should be left floating open. The Rs resistors values
are zero W, but may be changed to value such as 6 to 12ĂW
to improve signal integrity.
For 1X loading, set RREF potentiometer between 0 and
1kW to GND for 1X loading (see Appendix 1: Device IREF
pin 1 load plot of RREF vs. IREF current).
For 50 W (Low Impedance) probes with High Bandwidth
(>1 GHz): The odd numbered Serial Resistors R17 to R81
positions are populated with zero W resistors. The even
numbered Parallel Loading resistors R18 to R82 should not
be populated (open). Scope module inputs will provide
proper termination 50 W to GND. Un−probed outputs will
need to be externally loaded with 50 W to GND for proper
balanced operation.
For High Impedance Probes, low input capacitance probe
with High Bandwidth (>1 GHz), odd numbered Series
Resistors positions R17 to R81 are populated with 0 W value
components. The even numbered Parallel Loading resistors
R18 to R82 should also all be populated with 50 W (to GND)
components for proper termination.
For 2X loading, set the RREF between 20 K and 50 kW to
GND or tie IREF directly to VCC.
For 50 W (Low Impedance) probes with High Bandwidth
(>1 GHz), the odd numbered Serial Resistors R17 to R81
positions should be populated with zero W value
components. All even numbered Parallel Loading resistors
R18 to R82 should have 50 W value components installed.
A typical scope (probe) 50 W impedance in parallel with the
installed even numbered Parallel Loading 50 W resistors
R18 to R82 will present a 25 W (2X) load to the device.
Un−probed outputs will need to be externally loaded with
50ĂW to GND to present the proper 25 W load to the device.
For High Impedance Probes, low input capacitance probe
with High Bandwidth (>1 GHz), odd numbered Series
Resistors positions R17 to R81 are populated with 0 W value
components. The even numbered Parallel Loading resistors
R18 to R82 should also all be populated with 25 W (to GND)
components for proper termination.
Low Impedance Probes:
Use 50 W (Low Impedance) probes with High Bandwidth
(>1 GHz). The odd numbered Resistors R18 to R82
positions should be populated with 50 W value components.
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A typical scope (probe) 50 W impedance in parallel with the
installed odd numbered 50 W Resistor value will present a
25ĂW load to the device. Un−probed outputs will need to be
externally loaded with 25 W to GND for proper operation.
High Impedance Probes:
Use a high impedance, low input capacitance probe with
High Bandwidth (>1 GHz) and repopulate odd numbered
Resistors R18 to R82 (25 W value).
Step 3: Electrical Measurements
Device will meet the specifications after thermal
equilibrium has been established when mounted in a test
socket or printed circuit board with maintained transverse
airflow greater than 500 lfpm. Electrical parameters are
guaranteed only over the declared operating temperature
range. Functional operation of the device exceeding these
conditions is not implied. Device specification limit values
are applied individually under normal operating conditions
and not valid simultaneously.
APPENDIXES
Appendix 1: Device Information
Figure 5. Package Case Identification
152
QFN−52
CASE 485M
MN SUFFIX
Figure 6. Device Marking Diagram
XXXXXXXXX = Device Code
A = Assembly Site
WL = Wafer Lot
YY = Year
WW = Work Week
G = Pb−Free Package
xxxxxxxxx
xxxxxxxxx
AWLYYWWG
1
52
MARKING DIAGRAM
Figure 7. Device Function Diagram Figure 8. Output Loading Diagram
Device Under Test: NB4N121K
Package Case Identification,
Device Marking Diagram,
Device Function Diagram,
Output Loading Diagram,
Pinout Diagram,
Pin Description
HCSL
Driver
Z0 = 50 W
Z0 = 50 W
Qx
Qx
RREFA
RS1C
RS2C
1X Load
RL2B
50
RL1B
50
CL1D
2 pF
VCC
GND
CLK
CLK
RREF
IREF Q20
Q20
Q19
Q19
Q1
Q1
Q0
Q0
RS1C = 0 W,
RREFA = 0−1 kW for 1X Load, 20 K−50 K for 2X Load
RLxB may be open for 1X load (supplied by scope input
module, may be 50 W for 2X load to present a 25 W load with
scope 50 W input module impedance.
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Figure 9. Pinout Diagram
Exposed Pad (EP)
Q11
Q11
Q10
Q10
Q9
Q9
Q8
Q8
Q7
Q7
Q6
Q6
VCC
NB4N121K
IREF
GND
VTCLK
CLK
CLK
VTCLK
VCC
Q20
Q20
Q19
Q19
Q18
Q18 13
12
11
10
9
8
7
6
5
4
3
2
139
38
37
36
35
34
33
32
31
30
29
28
27
VCC
Q12
Q12
Q13
Q13
Q14
Q14
Q15
Q15
Q16
Q16
Q17
Q17
14 26
15 16 17 18 19 20 21 22 23 24 25
51 50 49 48 47 46 45 44 43 42 41
52 40
VCC
Q0
Q0
Q1
Q1
Q2
Q2
Q3
Q3
Q4
Q4
Q5
Q5
Table 2. PIN DESCRIPTION
Pin Name I/O Description
1 IREF Output Output current programming pin to select 1X or 2X load. Connect a
selected resistor from IREF pin to GND (See Appendix 3: Device IREF
pin 1 load plot of RREF vs. IREF current.
2 GND −Supply Ground. GND pin must be externally connected to power sup-
ply to guarantee proper operation.
3, 6 VTCLK,
VTCLK
−Internal 50 W Termination Resistor connection Pins. In the differential
configuration when the input termination pins are connected to the
common termination voltage, and if no signal is applied then the device
may be susceptible to self−oscillation.
4 CLK LVPECL
Input
CLOCK Input (TRUE)
5 CLK LVPECL
Input
CLOCK Input (INVERT)
7, 26, 39, 52 VCC −Positive Supply pins. VCC pins must be externally connected to a
power supply to guarantee proper operation.
8, 10, 12, 14, 16, 18, 20, 22,
24, 27, 29, 31, 33, 35, 37, 40,
42, 44, 46, 48, 50
Q[20−0] HCSL
Output
Output (INVERT)
9, 11, 13, 15, 17, 19, 21, 23,
25, 28, 30, 32, 34, 36, 38, 41,
43, 45, 47, 49, 51
Q[20−0] HCSL
Output
Output (TRUE)
Exposed Pad EP GND Exposed Pad. The thermally exposed pad (EP) on package bottom
(see case drawing) must be attached to a sufficient heat−sinking con-
duit for proper thermal operation. (Note 1)
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Appendix 2: Schematics
Figure 10. Pins 1 to 13
VTCLK
VCC
Q20
Q20
Q19
Q19
Q18
Q18
IREF
GND
VTCLK
CLK
CLK
1
2
VCC VCCO
0.1 mF
C5
3
12
POTBOU3269W0−50 K
2345
1
J3 CON_SMA_ST
2345
1
J4 CON_SMA_ST
2345
1
J7 CON_SMA_ST
2345
1
J8 CON_SMA_ST
2345
1
J37 CON_SMA_ST
2345
1
J38 CON_SMA_ST
2345
1
J10 CON_SMA_ST
2345
1
J11 CON_SMA_ST
2345
1
J41 CON_SMA_ST
2345
1
J42 CON_SMA_ST 1
2
12
12
R46
R48
DNI
DNI 1
2
R42
DNI
1
2
0
0
12
0
12
0
1
2
R44
DNI
R50
R52
DNI
DNI
1
2
1
2
12
12
0
0
R45
R47
R49
R51 3
4
5
6
7
8
9
10
11
12
13
R41
R43
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Figure 11. Pins 14 to 26
Q15
Q14
Q14
Q13
Q13
Q12
Q12
VCCO
Q17
Q17
Q16
Q16
Q15
14
15
2345
1
CON_SMA_ST
1
2
12
12
R78
R80
DNI
DNI 1
2
R66
DNI
1
2
0
0
12
0
12
0
1
2
R76
DNI
R84
R82
DNI
DNI
1
2
1
2
12
12
0
0
R77
R79
R83
R81
16
17
18
19
20
21
22
23
24
25
26
2345
1
CON_SMA_ST
2345
1
CON_SMA_ST
2345
1
CON_SMA_ST
2345
1
CON_SMA_ST
2345
1
CON_SMA_ST
2345
1
CON_SMA_ST
2345
1
CON_SMA_ST
2345
1
CON_SMA_ST
2345
1
CON_SMA_ST
2345
1
CON_SMA_ST
2345
1
J21 CON_SMA_ST
12
0
1
2
R72
DNI
2
1
R74
DNI
12
012
0
12
0
R68
DNI 1
2
R62
DNI
1
2
12
0
12
0
1
2
R64
DNI
2
1
R70
DNI
J20
J19
J16
J29
J30
J15
J14
J13
J12
J35
J36
R75
R73
R71
R69
R63
R61
R67
R65
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Figure 12. Pins 27 to 39
Q8
Q8
Q9
Q9
Q10
Q10
Q11
Q11
VCC
Q6
Q6
Q7
Q7
39
38
2345
1
J1
CON_SMA_ST
2345
1
J2
CON_SMA_ST
2345
1
J32
CON_SMA_ST
2345
1
J33
CON_SMA_ST
2345
1
J22
CON_SMA_ST
2345
1
J25
CON_SMA_ST
2345
1
J26
CON_SMA_ST
2345
1
J27
CON_SMA_ST
2345
1
J28
CON_SMA_ST
2345
1
J31
CON_SMA_ST
1
2
12
12
R54
R56
DNI
DNI
1
2
R16
DNI
1
2
0
0
12
0
12
0
1
2R14
DNI
12
12
0
0
R53
R55
R11
R9
37
36
35
34
33
32
31
30
29
28
27
2345
1
J5
CON_SMA_ST
2345
1
J6
CON_SMA_ST
R12
DNI
1
2
R15
R13
1
2R10
DNI
R4
DNI
1
2
12
12
0
0
R3
R1 R2
DNI
2
1
2
1R8
DNI
12
12
0
0
R7
R5 R6
DNI
2
1
2
1R20
DNI
12
12
0
0
R19
R17 R18
DNI
2
1
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Figure 13. Pins 40 to 52
Q3
Q2
Q2
Q1
Q1
Q0
Q0
VCC
Q5
Q5
Q4
Q4
Q3
40
41
2345
1
CON_SMA_ST
1
2
12
12
R38
R40
DNI
DNI 1
2
R26
DNI
1
2
0
0
12
0
12
0
1
2
R36
DNI
R60
R58
DNI
DNI
1
2
1
2
12
12
0
0
R37
R39
R59
R57
42
43
44
45
46
47
48
49
50
51
52
2345
1
CON_SMA_ST
2345
1
CON_SMA_ST
2345
1
CON_SMA_ST
2345
1
CON_SMA_ST
2345
1
CON_SMA_ST
2345
1
CON_SMA_ST
2345
1
CON_SMA_ST
2345
1
CON_SMA_ST
2345
1
CON_SMA_ST
2345
1
CON_SMA_ST
2345
1
J52 CON_SMA_ST
12
0
1
2
R32
DNI
2
1
R34
DNI
12
012
0
12
0
R28
DNI 1
2
R22
DNI
1
2
12
0
12
0
1
2
R24
DNI
2
1
R30
DNI
J51
J50
J49
J17
J18
J34
J39
J40
J48
J23
J24
R35
R33
R31
R29
R23
R21
R27
R25
VCCO
VCC
Figure 14. Schematic Bypass and Supply Connector Details
C7 C6 C1
VCCO
C2
+C4
VCC
C3
+
GND
VCCO
VCC
TP2
KEYSTONE 5016
TP1
KEYSTONE 5016
TP3
KEYSTONE 5016
J43
1
1
CON DSUB09−RAMP−788796
1
6
2
7
3
8
4
9
5
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Appendix 3: Device IREF Pin 1 Load Plot of RREF vs. IREF Current
Figure 15. Device IREF pin 1 Load Plot of RREF vs. IREF Current
RREF (K)
50403020100
32
30
28
26
24
22
20
18
16
14
IREF
Ityp @ 50 kW: 29.3 mA
Ityp @ 1 kW: 15.4 mA
3.0 V
+20°C
+85°C
+130°C
14.54 mA/27.15 mA
14.92 mA/27.42 mA
15.05 mA/26.93 mA
3.3 V
15.06 mA/28.66 mA
15.42 mA/29.33 mA
14.60 mA/29.25 mA
3.6 V
15.65 mA/29.97 mA
15.86 mA/30.60 mA
16.03 mA/30.80 mA
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Appendix 4: Bill of Materials, Board Lamination Stackup, and Fabrication Notes
Bill of Materials Table
Top Bot Description Value Source Source P/N Reference Designators
0 5 Cap, Chip, 0.1 mF,
0603, 50 V, 10%
X7R
0.1 mFC1, C4, C5, C6, C7
0 2 Cap, Chip, 10 mF,
Tant “C”, 25 V, 10%
10 mFC2, C3
1 0 ANTARES 52 QFN
Socket
FP0052QN0805C Alternative construction option:
ANTARES Test Technology 3350 Scott Blvd.,
Bldg 58, Santa Clara, CA 95054, Phone:
(408) 988−6800, www.antares-att.com
4 2−56 Pem Nuts DUT1
3TP1, TP2, TP3 KEYSTONE 5016 (or similar)
46 0 Connector, SMA,
Straight
Johnson 142−0701−201 J1, J2, J3, J4, J5, J6, J7, J8, J10, J11, J12,
J13, J14J15, J16, J17, J18, J19, J20, J21,
J22, J23, J24, J25, J26, J27, J28, J29, J30,
J31, J32, J33, J34, J35, J36, J37, J38, J39,
J40, J41, J42, J48, J49, J50, J51, J52
1 J43 CON DSUB09−
RAMP−788796
J43 (Optional − Not Supplied)
0 42 Res, Chip, 0 W,
0603, 1/16 W, 5%
0R1, R3, R5, R7, R9, R11, R13, R15, R17,
R19, R21, R23, R25, R27, R29, R31, R33,
R35, R37, R39, R41, R43, R45, R47, R49,
R51, R53, R55, R57, R59, R61, R63, R65,
R67, R69, R71, R73, R75, R77, R79, R81,
R83
0 1 0−50 K
POTENTIOMETER,
TOP ADJUST
0−50 kWBOURNS 3269W−1−503 R85
Board Lamination Stackup:
Dielectric is FR4 (interlayer between 1−2, 2−3, 3−4, 4−5, 5−6).
Layers #1 (Topside) and #6 (Bottomside) are signal path copper (trace width 0.014″).
ÉÉÉÉÉÉÉÉÉÉÉÉÉÉÉÉÉÉÉ
ÉÉÉÉÉÉÉÉÉÉÉÉÉÉÉÉÉÉÉ
ÉÉÉÉÉÉÉÉÉÉÉÉÉÉÉÉÉÉÉ
ÉÉÉÉÉÉÉÉÉÉÉÉÉÉÉÉÉÉÉ
ÉÉÉÉÉÉÉÉÉÉÉÉÉÉÉÉÉÉÉ
ÉÉÉÉÉÉÉÉÉÉÉÉÉÉÉÉÉÉÉ
ÉÉÉÉÉÉÉÉÉÉÉÉÉÉÉÉÉÉÉ
Trace
Width
Layer
Material
Dielectric
Thickness
Copper
Thickness
Layer
Name
Layer
Number
LAMINATION DIAGRAM
0.0141/2 OZ.TOP1
N/A1 OZ.GND2
N/A1 OZ.PWR13
N/A1 OZ.PWR24
N/A1 OZ.GND5
0.0141/2 OZ.BTN6
FINISHED PCB THICKNESS TO BE: 0.100 ±10%
0.008
0.005
Adjust
0.005
0.008
See Note 1
See Note 1
See Note 1
See Note 1
See Note 1
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Board Fabrication Notes:
(Unless otherwise specified)
1. ARTWORK:
Fabricate using ADC artwork No. AZ10035 Rev A.
Drill locations determined by ADC file
AZ10035NC.DRL
2. MATERIAL:
High temp FR4 − 170°C Tg
3. BOARD THICKNESS:
Refer to stacking diagram for finished board
thickness.
4. TWIST AND WARP:
Board twist shall not exceed 0.5% (0.005 in.) per
linear inch.
5. PLATING:
Copper thickness for internal and external layers is
specified in the stacking diagram.
Finished PCB to be electrodeposited hard gold
plate, type 1 (99.7% min gold), grade C (knoop
hardness 130−200), class X, 3−10 micro inches
thick, over entire board surface.
Selective plating is not required.
Hole Plating:
0.011 minimum barrel avg. / 0.009 absolute
minimum. Absolute maximum to be determined
by PCB vendor based on the required finished hole
diameter. Hole diameters are after plating unless
otherwise specified.
5.1 − Surface pads in this area to be free from any
irregularities or defects that might hinder proper
performance of the pad.
6. ANNULAR RING:
Annular ring to be 0.005 minimum with top to
bottom registration to be within 0.003.
7. SOLDERMASK:
Apply soldermask, color: green, type: LP1, per
artwork provided. If VIA plugs are required, plug
pattern will be supplied with artwork.
8. SILKSCREEN:
To be white, non−conductive ink per artwork. No
ink is to be on plated thru hole or surface mount
pads. Silkscreen lines and text width are to be
0.006 minimum.
9. SOLDERABILITY:
Plated holes shall not be rough or irregular so as to
prevent proper solder wicking.
10. DRILL CHART:
Hole sizes specified are finished hole sizes, unless
otherwise specified:
Standard plated hole tolerance is ±0.003
Standard non−plated hole tolerance is ±0.002
11. IMPEDANCE:
Impedance controlled layers: 1, 6.
12. APPROVAL:
100% continuity and isolation test required for
each fabricated PCB. Final test data must be cross
referenced to the IPC−D−356 file provided. A
verification stamp is required on each PCB.
A TDR report shall be provided for each
impedance controlled layer at the time of
shipment. Final acceptance shall be determined by
these layers having a characteristic impedance of
50 ohms ±10%. Vendor can make line width
adjustments on impedance controlled conductor
widths of 0.0005. All other artwork deviations
must have prior approval from R&D ADC.
ON Semiconductor and are registered trademarks of Semiconductor Components Industries, LLC (SCILLC). SCILLC reserves the right to make changes without further notice
to any products herein. SCILLC makes no warranty, representation or guarantee regarding the suitability of its products for any particular purpose, nor does SCILLC assume any liability
arising out of the application or use of any product or circuit, and specifically disclaims any and all liability, including without limitation special, consequential or incidental damages.
“Typical” parameters which may be provided in SCILLC data sheets and/or specifications can and do vary in different applications and actual performance may vary over time. All
operating parameters, including “Typicals” must be validated for each customer application by customer’s technical experts. SCILLC does not convey any license under its patent rights
nor the rights of others. SCILLC products are not designed, intended, or authorized for use as components in systems intended for surgical implant into the body, or other applications
intended to support or sustain life, or for any other application in which the failure of the SCILLC product could create a situation where personal injury or death may occur. Should
Buyer purchase or use SCILLC products for any such unintended or unauthorized application, Buyer shall indemnify and hold SCILLC and its officers, employees, subsidiaries, affiliates,
and distributors harmless against all claims, costs, damages, and expenses, and reasonable attorney fees arising out of, directly or indirectly, any claim of personal injury or death
associated with such unintended or unauthorized use, even if such claim alleges that SCILLC was negligent regarding the design or manufacture of the part. SCILLC is an Equal
Opportunity/Affirmative Action Employer. This literature is subject to all applicable copyright laws and is not for resale in any manner.
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