K6R1016C1D CMOS SRAM
Revision 0.3
- 1 - December 2001
PRELIMINARY
Preliminary
Document Title
64Kx16 Bit High-Speed CMOS Static RAM(5.0V Operating).
Operated at Commercial and Industrial Temperature Ranges.
Revision History
The attached data sheets are prepared and approved by SAMSUNG Electronics. SAMSUNG Electronics CO., LTD. reserve the right to change the
specifications. SAMSUNG Electronics will evaluate and reply to your requests and questions on the parameters of this device. If you have any questions,
please contact the SAMSUNG branch office near your office, call or contact Headquarters.
Rev. No.
Rev. 0.0
Rev. 0.1
Rev. 0.2
Rev. 0.3
Remark
Preliminary
Preliminary
Preliminary
Preliminary
History
Initial release with Preliminary.
Page 4, DC operation condition modify
Current modify
1. Delete 15ns speed bin.
2. Change Icc for Industrial mode.
Item Previous Current
ICC(Industrial) 10ns 85mA 75mA
12ns 75mA 65mA
Draft Data
June. 8. 2001
June. 16. 2001
September. 9. 2001
December. 18.2001
K6R1016C1D CMOS SRAM
Revision 0.3
- 2 - December 2001
PRELIMINARY
Preliminary
1Mb Async. Fast SRAM Ordering Information
Org. Part Number VDD(V) Speed ( ns ) PKG Temp. & Power
256K x4 K6R1004C1D-JC(I) 10/12 510/12 J : 32-SOJ C : Commercial Temperature
,Normal Power Range
I : Industrial Temperature
,Normal Power Range
K6R1004V1D-JC(I) 08/10 3.3 8/10
128K x8 K6R1008C1D-J(T)C(I) 10/12 510/12 J : 32-SOJ
T : 32-TSOP2
K6R1008V1D-J(T)C(I) 08/10 3.3 8/10
64K x16 K6R1016C1D-J(T,E)C(I) 10/12 510/12 J : 44-SOJ
T : 44-TSOP2
E : 48-TBGA
K6R1016V1D-J(T,E)C(I) 08/10 3.3 8/10
K6R1016C1D CMOS SRAM
Revision 0.3
- 3 - December 2001
PRELIMINARY
Preliminary
64K x 16 Bit High-Speed CMOS Static RAM
The K6R1016C1D is a 1,048,576-bit high-speed Static Random
Access Memory organized as 65,536 words by 16 bits. The
K6R1016C1D uses 16 common input and output lines and has
at output enable pin which operates faster than address access
time at read cycle. Also it allows that lower and upper byte
access by data byte control (UB, LB). The device is fabricated
using SAMSUNG′s advanced CMOS process and designed for
high-speed circuit technology. It is particularly well suited for
use in high-density high-speed system applications. The
K6R1016C1D is packaged in a 400mil 44-pin plastic SOJ or
TSOP2 forward or 48-TBGA.
GENERAL DESCRIPTIONFEATURES
• Fast Access Time 10,12(Max.)
• Power Dissipation
Standby (TTL) : 20mA(Max.)
(CMOS) : 5mA(Max.)
Operating K6R1016C1D-10 : 65mA(Max.)
K6R1016C1D-12 : 55mA(Max.)
• Single 5.0V±10% Power Supply
• TTL Compatible Inputs and Outputs
• I/O Compatible with 3.3V Device
• Fully Static Operation
- No Clock or Refresh required
• Three State Outputs
• Center Power/Ground Pin Configuration
• Data Byte Control: LB: I/O1~ I/O8, UB: I/O9~ I/O16
• Standard Pin Configuration:
K6R1016C1D-J : 44-SOJ-400
K6R1016C1D-T: 44-TSOP2-400BF
K6R1016C1D-E: 48-TBGA ( 6.0mm X 7.0mm )
with 0.75 ball pitch
• Operating in Commercial and Industrial Temperature range.
Clk Gen.
I/O1~I/O8
OE
UB
CS
FUNCTIONAL BLOCK DIAGRAM
Row Select
Data
Cont. Column Select
A10 A11 A12 A13 A14 A15
CLK
Gen.
Pre-Charge Circuit
Memory Array
512 Rows
128x16 Columns
I/O Circuit &
A0
I/O9~I/O16 Data
Cont.
WE
LB
A1
A2
A3
A4
A5
A6
A7
A9
A8PIN FUNCTION
Pin Name Pin Function
A0 - A15 Address Inputs
WE Write Enable
CS Chip Select
OE Output Enable
LB Lower-byte Control(I/O1~I/O8)
UB Upper-byte Control(I/O9~I/O16)
I/O1 ~ I/O16 Data Inputs/Outputs
VCC Power(+5.0V)
VSS Ground
N.C No Connection
K6R1016C1D CMOS SRAM
Revision 0.3
- 4 - December 2001
PRELIMINARY
Preliminary
ABSOLUTE MAXIMUM RATINGS*
* Stresses greater than those listed under "Absolute Maximum Ratings" may cause permanent damage to the device. This is a stress rating only and
functional operation of the device at these or any other conditions above those indicated in the operating sections of this specification is not implied.
Exposure to absolute maximum rating conditions for extended periods may affect reliability.
Parameter Symbol Rating Unit
Voltage on Any Pin Relative to VSS VIN, VOUT -0.5 to VCC+0.5 V
Voltage on VCC Supply Relative to VSS VCC -0.5 to 7.0 V
Power Dissipation Pd1W
Storage Temperature TSTG -65 to 150 °C
Operating Temperature Commercial TA0 to 70 °C
Industrial TA-40 to 85 °C
RECOMMENDED DC OPERATING CONDITIONS*(TA= to 70°C)
* The above parameters are also guaranteed at industrial temperature range.
** VIL(Min) = -2.0V a.c(Pulse Width ≤ 8ns) for I ≤ 20mA.
*** VIH(Max) = VCC + 2.0V a.c(Pulse Width ≤ 8ns) for I ≤ 20mA.
Parameter Symbol Min Typ Max Unit
Supply Voltage VCC 4.5 5.0 5.5 V
Ground VSS 0 0 0 V
Input High Voltage VIH 2.2 -VCC+0.5*** V
Input Low Voltage VIL -0.5** -0.8 V
LB OE A0 A1 A2 N.C
I/O1 UB A3 A4 CS I/O9
I/O2 I/O3 A5 A6 I/O11 I/O10
Vss I/O4 N.C A7 I/O12 Vcc
Vcc I/O5 N.C N.C I/O13 Vss
I/O7 I/O6 A14 A15 I/O14 I/O15
I/O8 N.C A12 A13 WE I/O16
N.C A8 A9 A10 A11 N.C
1 23456
A
B
C
D
E
F
G
H
48-TBGA ( Top View )
PIN CONFIGURATION(TOP VIEW)
SOJ/
TSOP2
1
2
3
4
5
6
7
8
9
10
11
12
13
14
15
16
17
18
19
20
21
22
A15
A14
A13
OE
UB
LB
I/O16
I/O15
I/O14
I/O13
Vss
Vcc
I/O12
I/O11
I/O10
I/O9
N.C
A12
A11
A10
A9
N.C
A0
A1
A2
A3
A4
CS
I/O1
I/O2
I/O3
I/O4
Vcc
Vss
I/O5
I/O6
I/O7
I/O8
WE
A5
A6
A7
A8
N.C
44
43
42
41
40
39
38
37
36
35
34
33
32
31
30
29
28
27
26
25
24
23
K6R1016C1D CMOS SRAM
Revision 0.3
- 5 - December 2001
PRELIMINARY
Preliminary
TEST CONDITIONS*
* The above test conditions are also applied at industrial temperature range.
Parameter Value
Input Pulse Levels 0V to 3V
Input Rise and Fall Times 3ns
Input and Output timing Reference Levels 1.5V
Output Loads See below
AC CHARACTERISTICS(TA=0 to 70°C, VCC=5.0V±10%, unless otherwise noted.)
Output Loads(B)
DOUT
5pF*
480Ω
255Ω
for tHZ, tLZ, tWHZ, tOW, tOLZ & tOHZ
+5.0V
* Including Scope and Jig Capacitance
Output Loads(A)
DOUT RL = 50Ω
ZO = 50Ω
VL = 1.5V
30pF*
* Capacitive Load consists of all components of the
test environment.
CAPACITANCE*(TA=25°C, f=1.0MHz)
* Capacitance is sampled and not 100% tested.
Item Symbol Test Conditions MIN Max Unit
Input/Output Capacitance CI/O VI/O=0V -8pF
Input Capacitance CIN VIN=0V -6pF
DC AND OPERATING CHARACTERISTICS*(TA=0 to 70°C, Vcc=5.0V±10%, unless otherwise specified)
* The above parameters are also guaranteed at industrial temperature range.
Parameter Symbol Test Conditions Min Max Unit
Input Leakage Current ILI VIN=VSS to VCC -2 2µA
Output Leakage Current ILO CS=VIH or OE=VIH or WE=VIL
VOUT=VSS to VCC -2 2µA
Operating Current ICC Min. Cycle, 100% Duty
CS=VIL, VIN=VIH or VIL, IOUT=0mA Com. 10ns -65 mA
12ns -55
Ind. 10ns -75
12ns -65
Standby Current ISB Min. Cycle, CS=VIH -20 mA
ISB1 f=0MHz, CS≥VCC-0.2V,
VIN≥VCC-0.2V or VIN≤0.2V -5
Output Low Voltage Level VOL IOL=8mA -0.4 V
Output High Voltage Level VOH IOH=-4mA 2.4 -V
K6R1016C1D CMOS SRAM
Revision 0.3
- 6 - December 2001
PRELIMINARY
Preliminary
Address
Data Out Previous Valid Data Valid Data
TIMING DIAGRAMS
TIMING WAVEFORM OF READ CYCLE(1) (Address Controlled, CS=OE=VIL, WE=VIH, UB, LB=VIL
tAA
tRC
tOH
READ CYCLE*
* The above parameters are also guaranteed at industrial temperature range.
Parameter Symbol K6R1016C1D-10 K6R1016C1D-12 Unit
Min Max Min Max
Read Cycle Time tRC 10 -12 -ns
Address Access Time tAA -10 -12 ns
Chip Select to Output tCO -10 -12 ns
Output Enable to Valid Output tOE -5-6ns
UB, LB Access Time tBA -5-6ns
Chip Enable to Low-Z Output tLZ 3-3-ns
Output Enable to Low-Z Output tOLZ 0-0-ns
UB, LB Enable to Low-Z Output tBLZ 0-0-ns
Chip Disable to High-Z Output tHZ 0506ns
Output Disable to High-Z Output tOHZ 0506ns
UB, LB Disable to High-Z Output tBHZ 0506ns
Output Hold from Address Change tOH 3-3-ns
Chip Selection to Power Up Time tPU 0-0-ns
Chip Selection to Power DownTime tPD -10 -12 ns
WRITE CYCLE*
* The above parameters are also guaranteed at industrial temperature range.
Parameter Symbol K6R1016C1D-10 K6R1016C1D-12 Unit
Min Max Min Max
Write Cycle Time tWC 10 -12 -ns
Chip Select to End of Write tCW 7-8-ns
Address Set-up Time tAS 0-0-ns
Address Valid to End of Write tAW 7-8-ns
Write Pulse Width(OE High) tWP 7-8-ns
Write Pulse Width(OE Low) tWP1 10 -12 -ns
UB, LB Valid to End of Write tBW 7-8-ns
Write Recovery Time tWR 0-0-ns
Write to Output High-Z tWHZ 0 5 0 6 ns
Data to Write Time Overlap tDW 5-6-ns
Data Hold from Write Time tDH 0-0-ns
End of Write to Output Low-Z tOW 3-3-ns
K6R1016C1D CMOS SRAM
Revision 0.3
- 7 - December 2001
PRELIMINARY
Preliminary
NOTES(READ CYCLE)
1. WE is high for read cycle.
2. All read cycle timing is referenced from the last valid address to the first transition address.
3. tHZ and tOHZ are defined as the time at which the outputs achieve the open circuit condition and are not referenced to VOH or
VOL levels.
4. At any given temperature and voltage condition, tHZ(Max.) is less than tLZ(Min.) both for a given device and from device to
device.
5. Transition is measured ±200mV from steady state voltage with Load(B). This parameter is sampled and not 100% tested.
6. Device is continuously selected with CS=VIL.
7. For common I/O applications, minimization or elimination of bus contention conditions is necessary during read and write cycle.
TIMING WAVEFORM OF WRITE CYCLE(1) (OE =Clock)
Address
CS
UB, LB
WE
Data in
Data out
tWC
tCW(3)
tBW
tWP(2)
tAS(4)
tDH
tDW
tOHZ(6)
High-Z High-Z
Valid Data
OE
tAW tWR(5)
Valid Data
High-Z
tRC
CS
Address
UB, LB
OE
Data out
tHZ(3,4,5)tAA
tCO
tBA
tOE
tOLZ
tLZ(4,5)
tOHZ
tBHZ(3,4,5)
tBLZ(4,5)
tPU tPD
50%
50%
VCC
Current
ICC
ISB
TIMING WAVEFORM OF READ CYCLE(2) (WE=VIH)
K6R1016C1D CMOS SRAM
Revision 0.3
- 8 - December 2001
PRELIMINARY
Preliminary
TIMING WAVEFORM OF WRITE CYCLE(3) (CS=Controlled)
Address
CS
tAW
tDW tDH
Valid Data
WE
Data in
Data out High-Z High-Z(8)
UB, LB
tCW(3)
tWP(2)
tAS(4)
tWC
tWR(5)
High-Z
High-Z
tLZ tWHZ(6)
tBW
TIMING WAVEFORM OF WRITE CYCLE(2) (OE =Low fixed)
Address
CS
UB, LB
WE
Data in
Data out
tWC
tCW(3)
tBW
tWP1(2)
tDH
tDW
tWR(5)
tAS(4)
tOW
tWHZ(6) (10) (9)
High-Z
Valid Data
tAW
High-Z
K6R1016C1D CMOS SRAM
Revision 0.3
- 9 - December 2001
PRELIMINARY
Preliminary
FUNCTIONAL DESCRIPTION
* X means Don′t Care.
CS WE OE LB UB Mode I/O Pin Supply Current
I/O1~I/O8I/O9~I/O16
HXX* X X Not Select High-Z High-Z ISB, ISB1
LHHX X Output Disable High-Z High-Z ICC
LXXH H
LHL L HRead DOUT High-Z ICC
HLHigh-Z DOUT
L L DOUT DOUT
L L XLHWrite DIN High-Z ICC
HLHigh-Z DIN
L L DIN DIN
NOTES(WRITE CYCLE)
1. All write cycle timing is referenced from the last valid address to the first transition address.
2. A write occurs during the overlap of a low CS, WE, LB and UB. A write begins at the latest transition CS going low and WE
going low; A write ends at the earliest transition CS going high or WE going high. tWP is measured from the beginning of write
to the end of write.
3. tCW is measured from the later of CS going low to end of write.
4. tAS is measured from the address valid to the beginning of write.
5. tWR is measured from the end of write to the address change. tWR applied in case a write ends as CS or WE going high.
6. If OE, CS and WE are in the Read Mode during this period, the I/O pins are in the output low-Z state. Inputs of opposite phase
of the output must not be applied because bus contention can occur.
7. For common I/O applications, minimization or elimination of bus contention conditions is necessary during read and write cycle.
8. If CS goes low simultaneously with WE going or after WE going low, the outputs remain high impedance state.
9. Dout is the read data of the new address.
10. When CS is low: I/O pins are in the output state. The input signals in the opposite phase leading to the output should not be
applied.
Address
CS
Valid Data
UB, LB
WE
Data in
Data out
TIMING WAVEFORM OF WRITE CYCLE(4) (UB, LB Controlled)
tWC
tCW(3)
tBW
tWP(2)
tDH
tDW
tWR(5)
tAW
tAS(4)
High-Z High-Z(8)
tBLZ tWHZ(6)
High-Z
K6R1016C1D CMOS SRAM
Revision 0.3
- 10 December 2001
PRELIMINARY
Preliminary
#1
44-SOJ-400
#44
25.58 ±0.12
1.125 ±0.005
MAX
28.98
1.141
MAX
0.148
3.76
1.19
( )
0.047
1.27
( )
0.050
0.95
( )
0.0375
+0.10
0.43 -0.05
+0.004
0.017 -0.002
+0.10
0.71 -0.05
+0.004
0.028 -0.002
1.27
0.050
10.16
0.400
+0.10
0.20 -0.05
+0.004
0.008 -0.002
9.40 ±0.25
0.370 ±0.010
MIN
0.69
0.027
#22
#23
0.004
0.10 MAX
11.18 ±0.12
0.440 ±0.005
PACKAGE DIMENSIONS Units:millimeters/Inches
1.00 ±0.10
0.039 ±0.004
44-TSOP2-400BF
0.002
#1
0.05
#22
#23
0.30
0.012 0.80
0.0315 MIN
0.047
1.20 MAX
0.741
18.81MAX
18.41 ±0.10
0.725 ±0.004
11.76 ±0.20
0.463 ±0.008
+ 0.075
- 0.035
0.50
+ 0.003
- 0.001
0.125
0.005
0.020
10.16
0.400
0.10
0.004
0~8°
0.45 ~0.75
0.018 ~ 0.030
( )
0.805
0.032
( ) MAX
Units:millimeters/Inches
#44
0.25
0.010TYP
+0.10
−0.05
+0.004
−0.002
K6R1016C1D CMOS SRAM
Revision 0.3
- 11 December 2001
PRELIMINARY
Preliminary
C1/2
PACKAGE DIMENSION
6 5 4 3 2 1
A
B
C
D
E
F
G
H
C
B/2
B
C1
B
C
Bottom ViewTop View
D
E2
E1
E
C
Side View
0.55/Typ.
0.35/Typ.
A
Y
Detail A
Min Typ Max
A-0.75 -
B5.90 6.00 6.10
B1 -3.75 -
C6.90 7.00 7.10
C1 -5.25 -
D0.40 0.45 0.50
E0.80 0.90 1.00
E1 -0.55 -
E2 0.30 0.35 0.40
Y- - 0.08
B1
#A1
Notes.
1. Bump counts: 48(8 row x 6 column)
2. Bump pitch: (x,y)=(0.75 x 0.75)(typ.)
3. All tolerence are +/-0.050 unless
otherwise specified.
4. Typ: Typical
5. Y is coplanarity: 0.08(Max)
48 TAPE BALL GRID ARRAY(0.75mm ball pitch)
Unit: millimeters
