1
2
3
4
5
6
7
8
16
15
14
13
12
11
10
9
Top View
IN1IN2
D1D2
S1S2
V– V+
GND VL
S4S3
D4D3
IN4IN3
Dual-In-Line and SOIC
Top View
S1S2
V– V+
NC NC
GND VL
S4S3
LCC
NC IN3D3
D4IN4
NC IN2D2
D1IN1
Key
910111213
4
5
6
7
8
1231920
14
15
16
17
18
DG411 DG411
DG411/412/413
Siliconix
S-52883—Rev. C, 28-Apr-97 1
Precision Monolithic Quad SPST CMOS Analog Switches
Features Benefits Applications
44-V Supply Max Rating
15-V Analog Signal Range
On-Resistance—rDS(on): 25
Fast Switching—tON: 110 ns
Ultra Low Power—PD: 0.35 W
TTL, CMOS Compatible
Single Supply Capability
Widest Dynamic Range
Low Signal Errors and Distortion
Break-Before-Make Switching
Action
Simple Interfacing
Precision Automatic Test Equipment
Precision Data Acquisition
Communication Systems
Battery Powered Systems
Computer Peripherals
Description
The DG411 series of monolithic quad analog switches was
designed to provide high speed, low error switching of
precision analog signals. Combining low power (0.35 W)
with high speed (tON: 110 ns), the DG411 family is ideally
suited for portable and battery powered industrial and
military applications.
To achieve high-voltage ratings and superior switching
performance, the DG41 1 series was built on Siliconix’ s high
voltage silicon gate process. An epitaxial layer prevents
latchup.
Each switch conducts equally well in both directions when
on, and blocks input voltages up to the supply levels
when off.
The DG41 1 and DG412 respond to opposite control logic as
shown in the Truth Table. The DG413 has two normally
open and two normally closed switches.
Functional Block Diagram and Pin Configuration
Truth Table
Logic DG411 DG412
0 ON OFF
1 OFF ON
Lo
g
ic “0” 0.8 V
Logic
0
0
.
8
V
Logic
“
1
”
2.4 V
Logic
“1”
2
.
4
V
Updates to this data sheet may be obtained via facsimile by calling Siliconix FaxBack, 1-408-970-5600. Please request FaxBack document #70050.
Top View
S1S2
V– V+
NC NC
GND VL
S4S3
LCC
NC IN3D3
D4IN4
NC IN2D2
D1IN1
Key
910111213
4
5
6
7
8
1231920
14
15
16
17
18
1
2
3
4
5
6
7
8
16
15
14
13
12
11
10
9
Top View
IN1IN2
D1D2
S1S2
V– V+
GND VL
S4S3
D4D3
IN4IN3
Dual-In-Line and SOIC
DG413 DG413
DG411/412/413
2 Siliconix
S-52883—Rev. C, 28-Apr-97
Functional Block Diagram and Pin Configuration
Truth Table
Logic SW1,
SW4SW2,
SW3
0 OFF ON
1 ON OFF
Logic
“
0
”
0.8 V
Logic
0
0
.
8
V
Logic
“
1
”
24V
L
og
i
c
“1”
2
.
4
V
Ordering Information
Temp Range Package Part Number
DG411/412
–40 to 85_C
16
-
Pin Plastic DIP
DG411DJ
16
-
Pi
n
Pl
as
ti
c
DIP
DG412DJ
–40 to 85_C
16
-
Pin Narrow SOIC
DG411DY
16
-
Pi
n
N
arrow
SOIC
DG412DY
16
-
Pin CerDIP
DG411AK, DG411AK/883, 5962-9073101MEA
–
55 to 125
_
C
16
-
Pi
n
C
er
DIP
DG412AK, DG412AK/883, 5962-9073102MEA
–
55
t
o
125_C
LCC
-
20
DG411AZ/883, 5962-9073101M2A
LCC
-
20
5962-9073102M2A
DG413
Temp Range Package Part Number
–
40to 85
_
C
16-Pin Plastic DIP DG413DJ
–
40
t
o
85_C
16-Pin Narrow SOIC DG413DY
–
55 to 125
_
C
16-Pin CerDIP DG413AK, DG413AK/883, 5962-9073103MEA
–
55
t
o
125_C
LCC-20 5962-9073103M2A
Absolute Maximum Ratings
V+ to V– 44 V. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
GND to V– 25 V. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
VL(GND –0.3 V) to (V+) +0.3 V. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
Digital Inputsa, VS, VD(V–) –2 V to (V+) +2 V. . . . . . . . . . . . . . . . . . .
or 30 mA, whichever occurs first
Continuous Current (Any Terminal) 30 mA. . . . . . . . . . . . . . . . . . . . . .
Peak Current, S or D (Pulsed 1 ms, 10% Duty Cycle) 100 mA. . . . . . . .
Storage Temperature (AK, AZ Suffix) –65 to 150_C. . . . . . . . . .
(DJ, DY Suffix) –65 to 125_C. . . . . . . . . . .
Power Dissipation (Package)b
16-Pin Plastic DIPc470 mW. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
16-Pin Narrow SOICd600 mW. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
16-Pin CerDIPe900 mW. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
LCC-20e900 mW. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
Notes:
a. Signals on SX, DX, or INX exceeding V+ or V– will be clamped by
internal diodes. Limit forward diode current to maximum current
ratings.
b. All leads welded or soldered to PC Board.
c. Derate 6 mW/_C above 25_C
d. Derate 7.6 mW/_C above 75_C
e. Derate 12 mW/_C above 75_C
DG411/412/413
Siliconix
S-52883—Rev. C, 28-Apr-97 3
Specificationsa
Test Conditions
Unless Otherwise Specified A Suffix
–55 to 125_CD Suffix
–40 to 85_C
Parameter Symbol V+ = 15 V, V– = –15 V
VL = 5 V, VIN = 2.4 V, 0.8 VfTempbTypcMindMaxdMindMaxdUnit
Analog Switch
Analog Signal RangeeVANALOG Full –15 15 –15 15 V
Drain-Source
On-Resistance rDS(on) V+ = 13.5 V, V– = –13.5 V
IS = –10 mA, VD = 8.5 V Room
Full 25 35
45 35
45 W
Switch Off
Lk C
IS(off) V+ = 16.5, V– = –16.5 V
V155VV155V
Room
Full 0.1 –0.25
–20 0.25
20 –0.25
–5 0.25
5
Leakage Current ID(off)
,
VD = 15.5 V, VS = 15.5 V Room
Full 0.1 –0.25
–20 0.25
20 –0.25
–5 0.25
5nA
Channel On
Leakage Current ID(on) V+ = 16.5 V, V– = –16.5 V
VS = VD = 15.5 V Room
Full 0.1 –0.4
–40 0.4
40 –0.4
–10 0.4
10
Digital Control
Input Current, VIN Low IIL VIN Under Test = 0.8 V Full 0.005 –0.5 0.5 –0.5 0.5
mA
Input Current, VIN High IIH VIN Under Test = 2.4 V Full 0.005 –0.5 0.5 –0.5 0.5 m
A
Dynamic Characteristics
Turn-On Time tON RL = 300 W, CL = 35 pF
V 10VS Fi 2
Room
Full 110 175
240 175
220
Turn-Off Time tOFF
L,Lp
VS = 10 V See Figure 2 Room
Full 100 145
160 145
160 ns
Break-Before-Make
Time Delay tDDG413 Only, VS = 10 V
RL = 300 W, CL = 35 pF Room 25
Charge Injection Q Vg = 0 V, Rg = 0 W, CL = 10 nF Room 5 pC
Off IsolationeOIRR
RL=50WC
L=5pF
Room 68
Channel-to-Channel Cross-
talkeXTALK
R
L =
50
W
,
C
L =
5
p
F
,
f = 1 MHz Room 85 dB
Source Off CapacitanceeCS(off) Room 9
Drain Off CapacitanceeCD(off) f = 1 MHz Room 9 pF
Channel On CapacitanceeCD(on) Room 35
Power Supplies
Positive Supply Current I+ Room
Full 0.0001 1
51
5
Negative Supply Current I– V+ = 16.5, V– = –16.5 V
V05V
Room
Full –0.0001 –1
–5 –1
–5
mA
Logic Supply Current ILVIN = 0 or 5 V Room
Full 0.0001 1
51
5
mA
Ground Current IGND Room
Full –0.0001 –1
–5 –1
–5
DG411/412/413
4 Siliconix
S-52883—Rev. C, 28-Apr-97
Specificationsa for Unipolar Supplies
Test Conditions
Unless Otherwise Specified A Suffix
–55 to 125_CD Suffix
–40 to 85_C
Parameter Symbol V+ = 12 V, V– = 0 V
VL = 5 V, VIN = 2.4 V, 0.8 VfTempbTypcMindMaxdMindMaxdUnit
Analog Switch
Analog Signal RangeeVANALOG Full 12 12 V
Drain-Source
On-Resistance rDS(on) V+ = 10.8 V, IS = –10 mA
VD = 3 V, 8 V Room
Full 40 80
100 80
100 W
Dynamic Characteristics
Turn-On Time tON RL = 300 W, CL = 35 pF
V 8 V S Fi 2
Room
Hot 175 250
400 250
315
Turn-Off Time tOFF
L,Lp
VS = 8 V, See Figure 2 Room
Hot 95 125
140 125
140 ns
Break-Before-Make
Time Delay tDDG413 Only, VS = 8 V,
RL = 300 W, CL = 35 pF Room 25
Charge Injection Q Vg = 6 V, Rg = 0 W, CL = 10 nF Room 25 pC
Power Supplies
Positive Supply Current I+ Room
Hot 0.0001 1
51
5
Negative Supply Current I–
V+=135 V
IN =0or5V
Room
Hot –0.0001 –1
–5 –1
–5
mA
Logic Supply Current IL
V
+ =
13
.
5
,
V
IN =
0
or
5
V
Room
Hot 0.0001 1
51
5
m
A
Ground Current IGND Room
Hot –0.0001 –1
–5 –1
–5
Notes:
a. Refer to PROCESS OPTION FLOWCHART.
b. Room = 25_C, Full = as determined by the operating temperature suffix.
c. Typical values are for DESIGN AID ONLY, not guaranteed nor subject to production testing.
d. The algebraic convention whereby the most negative value is a minimum and the most positive a maximum, is used in this data sheet.
e. Guaranteed by design, not subject to production test.
f. VIN = input voltage to perform proper function.
Typical Characteristics
On-Resistance vs. VD and Power Supply Voltage
VD – Drain Voltage (V)
–20 –15 –10 –5 0 5 10 15 20
45
40
35
30
25
20
15
10
5
0
TA = 25_C
50
5 V
8 V
10 V
12 V
15 V
20 V
rDS(on) – Drain-Source On-Resistance (
0 2 4 6 8 101214161820
0
50
100
150
200
250
300
( )
DS(on)
V
VL = 5 V
On-Resistance vs. VD and Unipolar Supply Voltage
V+ = 3 V
VL = 3 V
8 V
V+ = 5 V
12 V 15 V 20 V
VD – Drain Voltage (V)
W
W
DG411/412/413
Siliconix
S-52883—Rev. C, 28-Apr-97 5
Typical Characteristics (Cont’d)
Leakage Current vs. Analog Voltage
Charge Injection vs. Analog VoltageCharge Injection vs. Analog Voltage
Input Switching Threshold vs. Supply Voltage
(pA)
I, I
SD
Q (pC)
VD or VS — Drain or Source Voltage (V)
VD – Drain Voltage (V)VS – Source Voltage (V)
Q (pC)
(V)
IN
V
100
80
60
40
20
0
–20
–40
–60–15 –10 –5 0 5 10 15
100
80
60
40
20
0
–20
–40
–60–15 –10 –5 0 5 10 15
120
140
40
30
10
–40
–60 –15 –10 –5 0 5 10 15
20
0
–50
–30
–10
–20
V+ = 15 V
V– = –15 V
VL = 5 V
TA = 25_CID(off)
IS(off)
V+ = 15 V
V– = –15 V
VL = 5 V
V+ = 15 V
V– = –15 V
VL = 5 V CL = 10 nF
CL = 1 nFCL = 10 nF
CL = 1 nF
ID(on)
3.5
3.0
5 10152025303540
2.5
2.0
1.5
1.0
0.5
0
–5 –10 –15 –10 –5 0 0 0
(V+)
(V–)
6.5 V
5.5 V
VL = 7.5 V
4.5 V
Switching Time vs. Temperature
Temperature (_C)
(ns)tON,t
OFF
240
180
120
60
0–55 –35 –15 5 25 45 65 85 105 125
210
150
90
30
V+ = 15 V
V– = –15 V
VL = 5 V
VS = 10 V
tOFF
tON
–15 –10 –5 0 5 10 15
5
10
15
20
25
30
35 V+ = 15 V
V– = –15 V
VL = 5 V
ID, IS Leakages vs. Temperature
125_C
85_C
25_C
–55_C
rDS(on) – Drain-Source On-Resistance (
VD – Drain Voltage (V)
DG411/412/413
6 Siliconix
S-52883—Rev. C, 28-Apr-97
Typical Characteristics (Cont’d)
Operating Voltage Range
V+ (V)
V– – Negative Supply (V)
ÉÉÉÉÉÉÉÉ
ÉÉÉÉÉÉÉÉ
ÉÉÉÉÉÉÉÉ
ÉÉÉÉÉÉÉÉ
ÉÉÉÉÉÉÉÉ
ÉÉÉÉÉÉÉÉ
ÉÉÉÉÉÉÉÉ
ÉÉÉÉÉÉÉÉ
ÉÉÉÉÉÉÉÉ
50
40
30
00
20
10
–10 –20 –30 –40
2
42
CMOS
Compatible
V–
V+
DX
SX
VL
GND
TTL Compatible
VIN = 0.8 V, 2.4 V
VL = 5 V CMOS
Compatible
CMOS
VL 3 V + V+
10
Supply Current vs. Input Switching Frequency
f – Frequency (Hz)
ISUPPLY
100 mA
10 mA
1 mA
100
mA
10 mA
1 mA
100 nA
10 nA
100 1 k 10 k 100 k 1 M 10 M
I+, I–
IL
V+ = 15 V
V– = –15 V
VL = 5 V
= 1 SW
= 4 SW
10
Schematic Diagram (Typical Channel)
Figure 1.
Level
Shift/
Drive
VIN
VL
S
V+
GND
V-
D
V-
V+
Test Circuits
Figure 2. Switching Time
0 V
Logic
Input
Switch
Input*
Switch
Output
3 V 50%
0 V
Switch
Input*
VS
tr <20 ns
tf <20 ns
90%
–VS
tON
tON
VO90%
VO
*VS = 10 V for tON, VS = –10 V for tOFF
Note: Logic input waveform is inverted for switches that
have the opposite logic sense control
CL (includes fixture and stray capacitance)
V+
IN
RL
RL + rDS(on)
VO = VS
S D
–15 V
VO
GND
10 V
VL
CL
35 pF
V–
RL
300
+15 V+5 V
DG411/412/413
Siliconix
S-52883—Rev. C, 28-Apr-97 7
Test Circuits (Cont’d)
Figure 3. Break-Before-Make (DG413)
0 V
Logic
Input
Switch
Switch
Output
3 V
50%
0 V
Output
0 V
90%
VO2
VO1
90%
VS1
VS2
tDtD
Figure 4. Charge Injection
VO2
CL (includes fixture and stray capacitance)
V+
S2
V–
S1
VL
VS2
IN2
D2
VS1
RL2
300 W
D1VO1
CL2
35 pF
–15 V
GND
+5 V +15 V
CL
10 nF
D
RgVO
V+
S
V–
3 V IN
VL
Vg
–15 V
GND
+15 V+5 V
RL1
300 WCL1
35 pF
OFFONOFF
OFFONOFF
VO
DVO
INX
INX
Q = DVO x CL
INX dependent on switch configuration Input polarity determined
by sense of switch.
IN1
Figure 5. Crosstalk
0V, 2.4 V
S1
XTALK Isolation = 20 log VS
VO
D2
C = RF bypass
RL
D1
S2
VS
0V, 2.4 V
IN150 W
VO
IN2
Rg = 50 W
VLV+
–15 V
GND V–
NC
C
+15 V
C+5 V C
DG411/412/413
8 Siliconix
S-52883—Rev. C, 28-Apr-97
Test Circuits (Cont’d)
Figure 6. Off Isolation Figure 7. Source/Drain Capacitances
RL
50
D
0V, 2.4 V
V+
Rg = 50
–15 V
GND V– C
VS
Off Isolation = 20 log VS
VO
IN
VLVO
+5 V
C
+15 V
S
C
D
IN
S
VLV+
–15 V
GND V– C
0 V, 2.4 V
Meter
HP4192A
Impedance
Analyzer
or Equivalent
+5 V
C
+15 V
C
C = RF Bypass
Applications
Single Supply Operation:
The DG41 1/412/413 can be operated with unipolar supplies
from 5 V to 44 V. These devices are characterized and tested
for unipolar supply operation at 12 V to facilitate the
majority of applications. In single supply operation, V+ is
tied to VL and V– is tied to 0 V. See Input Switching
Threshold vs. Supply Voltage curve for VL versus input
threshold requirments.
Summing Amplifier
When driving a high impedance, high capacitance load such
as shown in Figure 8, where the inputs to the summing
amplifier have some noise filtering, it is necessary to have
shunt switches for rapid discharge of the filter capacitor,
thus preventing offsets from occurring at the output.
+
–
DG413
R1R2
C1
R3R4
C2
R6
R5
VIN 1
VIN 2VOUT
Figure 8. Summing Amplifier
