September 2003
This document specifies SPANSION memory products that are now off ered b y both Adv anced Micro De vices and
Fujitsu. Although the document is marked with the name of the company that originally de v eloped the specification,
these products will be offered to customers of both AMD and Fujitsu.
Continuity of Specifications
There is no change to this datasheet as a result of offering the device as a SPANSION product. Future routine
revisions will occur when appropriate, and changes will be noted in a revision summary.
Continuity of Ordering Part Numbers
AMD and Fujitsu continue to support existing part numbers beginning with "Am" and "MBM". To order these
products, please use only the Ordering Part Numbers listed in this document.
For More Information
Please contact your local AMD or Fujitsu sales office for additional information about SPANSION memory
solutions.
TM
TM
TM
SPANSION Flash Memory
Data Sheet
TM
DS05-20867-5E
FUJITSU SEMICONDUCTOR
DATA SHEET
FLASH MEMORY
CMOS
2M (256K × 8/128K × 16) BIT
MBM29F200TC-55/-70/-90/MBM29F200BC-55/-70/-90
■
■■
■GENERAL DESCRIPTION
The MBM29F200TC/BC is a 2M-bit, 5.0 V-only Flash memory organized as 256K bytes of 8 bits each or 128K
words of 16 bits each. The MBM29F200TC/BC is offered in a 48-pin TSOP (1) and 44-pin SOP packages . This
device is designed to be programmed in-system with the standard system 5.0 V VCC supply. 12.0 V VPP is not
required for write or erase operations. The de vices can also be reprogrammed in standard EPROM programmers.
The standard MBM29F200TC/BC offers access times 55 ns and 90 ns allowing operation of high-speed
microprocessors without wait states . To eliminate bus contention the de vice has separate chip enable (CE), write
enable (WE), and output enable (OE) controls.
(Continued)
■
■■
■PRODUCT LINE-UP
■
■■
■PACKAGES
Part No. MBM29F200TC/MBM29F200BC
Ordering Part No. VCC = 5.0 V ± 5% -55 — —
VCC = 5.0 V ± 10% — -70 -90
Max Address Access Time (ns) 55 70 90
Max CE Access Time (ns) 55 70 90
Max OE Access Time (ns) 30 30 35
48-pin plastic TSOP (1) 48-pin plastic TSOP (1) 44-pin plastic SOP
(FPT-48P-M19) (FPT-48P-M20) (FPT-44P-M16)
Marking Side
Marking Side
Marking Side
MBM29F200TC-55/70/90/MBM29F200BC-55/70/90
2
(Continued)
The MBM29F200TC/BC is pin and command set compatible with JEDEC standard. Commands are written to
the command register using standard microprocessor write timings. Register contents serve as input to an
internal state-machine which controls the erase and programming circuitry. Write cycles also internally latch
addresses and data needed for the programming and erase operations. Reading data out of the devices is similar
to reading from12.0 V Flash or EPROM devices.
The MBM29F200TC/BC is programmed by executing the program command sequence. This will invoke the
Embedded Progra m Algorithm which is an internal algorithm that automatically times the program pulse widths
and verifies proper cell margin. Typically, each sector can be programmed and verified in less than 0.5 seconds.
Erase is accomplished by executing the erase command sequence. This will invoke the Embedded Erase
Algorithm which is an internal algorithm that automatically preprograms the arra y if it is not already programmed
bef ore executing the er ase oper ation. During erase, the device automatically times the erase pulse widths and
verifies proper cell margin.
A sector is typically erased and verified in 1.0 second (if already completely preprogrammed.).
The devices also features a sector erase architecture. The sector mode allows each sector to be erased and
reprogrammed without affecting other sectors. The MBM29F200TC/BC is erased when shipped from the factory.
The de vices features single 5.0 V power supply operation f or both read and write functions. Internally generated
and regulated voltages are provided for the program and erase operations. A low VCC detector automatically
inhibits write operations on the loss of power. The end of program or erase is detected by Data Polling of DQ7,
by the Toggle Bit feature on DQ6, or the RY/BY output pin. Once the end of a program or erase cycle has been
completed, the device internally resets to the read mode.
Fujitsu’s Flash technology combines years of EPROM and E2PROM experience to produce the highest levels
of quality, reliability, and cost effectiveness. The MBM29F200TC/BC memory electr ically erase the entire chip
or all bits within a sector simultaneously via Fowler-Nordhiem tunneling. The bytes/w ords are progr ammed one
byte/word at a time using the EPROM programming mechanism of hot electron injection.
MBM29F200TC-55/70/90/MBM29F200BC-55/70/90
3
■
■■
■FEATURES
• Single 5.0 V read, write, and erase
Minimizes system level power requirements
• Compatible with JEDEC-standard commands
Uses same software commands as E2PROMs
• Compatible with JEDEC-standard w o rld-wide pinouts
48-pin TSOP (1) (Package suffix: PFTN – Normal Bend Type, PFTR – Reversed Bend Type)
44-pin SOP (Package suffix: PF)
• Minim um 100,000 write/erase cycles
• High perf ormance
55 ns maximum access time
• Sector erase architecture
One 16K byte, two 8K bytes, one 32K byte, and three 64K bytes.
Any combination of sectors can be concurrently erased. Also supports full chip erase.
• Boot Code Sector Architecture
T = Top sector
B = Bottom sector
• Embedded EraseTM* Algorithms
Automatically pre-programs and erases the chip or any sector
• Embedded ProgramTM* Algorithms
Automatically writes and verifies data at specified address
•Data
Polling and Toggle Bit feature for detection of program or erase cycle completion
• Ready/Busy output (RY/BY)
Hardware method for detection of program or erase cycle completion
• Low Vcc write inhibit ≤ 3.2 V
• Erase Suspend/Resume
Suspends the erase operation to allow a read in another sector within the same device
• Hardware RESET pin
Resets internal state machine to the read mode
• Sector protection
Hardware method disables any combination of sectors from write or erase operations
• Temporary sector unprotection
Hardware method temporarily enables any combination of sectors from write on erase operations.
* : Embedded EraseTM and Embedded ProgramTM are trademarks of Advanced Micro Devices, Inc.
MBM29F200TC-55/70/90/MBM29F200BC-55/70/90
4
■
■■
■PIN ASSIGNMENTS
Pin name Function
A16 to A0, A-1 Address Inputs
DQ15 to DQ0Data Inputs/Outputs
CE Chip Enable
OE Output Enable
WE Write Enable
RY/BY Ready-Busy Output
RESET Hardware Reset Pin/Temporary Sector Unprotection
BYTE Selects 8-bit or 16-bit mode
N.C. No Internal Connection
VSS Device Ground
RY/BY
A
15
A
14
A
13
A
12
A
11
A
10
A
9
A
8
N.C.
N.C.
WE
RESET
N.C.
N.C.
RY/BY
N.C.
N.C.
A
7
A
6
A
5
A
4
A
3
A
2
A
1
1
2
3
4
5
6
7
8
9
10
11
12
13
14
15
16
17
18
19
20
21
22
23
24
48
47
46
45
44
43
42
41
40
39
38
37
36
35
34
33
32
31
30
29
28
27
26
25
MBM29F200TC/MBM29F200BC
Normal Bend
MBM29F200TC/MBM29F200BC
Reverse Bend
TSOP (1)
1
2
3
4
5
6
7
8
9
10
11
12
13
14
15
16
17
18
19
20
21
22
44
43
42
41
40
39
38
37
36
35
34
33
32
31
30
29
28
27
26
25
24
23
N.C.
RY/BY
A
7
A
6
A
5
A
4
A
3
A
2
A
1
A
0
CE
V
SS
OE
DQ
0
DQ
8
DQ
1
DQ
9
DQ
2
DQ
10
DQ
3
DQ
11
RESET
WE
A
8
A
9
A
10
A
11
A
12
A
13
A
14
A
15
A
16
BYTE
V
SS
DQ
15
/A
-1
DQ
7
DQ
14
DQ
6
DQ
13
DQ
5
DQ
12
DQ
4
V
CC
SOP
(Top View)
A
16
BYTE
V
SS
DQ
15
/A
-1
DQ
7
DQ
14
DQ
6
DQ
13
DQ
5
DQ
12
DQ
4
V
CC
DQ
11
DQ
3
DQ
10
DQ
2
DQ
9
DQ
1
DQ
8
DQ
0
OE
V
SS
CE
A
0
A
0
CE
V
SS
OE
DQ
0
DQ
8
DQ
1
DQ
9
DQ
2
DQ
10
DQ
3
DQ
11
V
CC
DQ
4
DQ
12
DQ
5
DQ
13
DQ
6
DQ
14
DQ
7
DQ
15
/A
-1
V
SS
BYTE
A
16
24
23
22
21
20
19
18
17
16
15
14
13
12
11
10
9
8
7
6
5
4
3
2
1
25
26
27
28
29
30
31
32
33
34
35
36
37
38
39
40
41
42
43
44
45
46
47
48
A
1
A
2
A
3
A
4
A
5
A
6
A
7
N.C.
N.C.
N.C.
RESET
WE
N.C.
N.C.
A
8
A
9
A
10
A
11
A
12
A
13
A
14
A
15
(Marking Side)
(FPT-48P-M19)
(FPT-48P-M20)
(FPT-44P-M16)
(Marking Side)
N.C.
N.C.
MBM29F200TC-55/70/90/MBM29F200BC-55/70/90
5
■
■■
■BLOCK DIAGRAM
■
■■
■LOGIC SYMBOL
VSS
VCC
WE
CE
A16 to A0
OE
Erase Voltage
Generator
DQ15 to DQ0
State
Control
Command
Register Program Voltage
Generator
Low VCC Detector Address
Latch X-Decoder
Y-Decoder
Cell Matrix
Y-Gating
Chip Enable
Output Enable
Logic Data Latch
Input/Output
Buffers
STB
STB
Timer for
A-1
BYTE
RESET
RY/BY
Buffer RY/BY
Program/Erase
17 A16 to A0
WE RY/BY
OE
CE
A-1
DQ15 to DQ0
16 or 8
RESET
BYTE
MBM29F200TC-55/70/90/MBM29F200BC-55/70/90
6
■
■■
■FLEXIBLE SECTOR-ERASE ARCHITECTURE
MBM29F200TC/BC User Bus Operation Table (BYTE = VIH)
Legend: L = VIL, H = VIH, X = VIL or VIH, = Pulse input. See DC Characteristics for vo ltage levels.
*1 : Manufacturer and device codes may also be accessed via a command register write sequence. Refer to
“MBM29F200TC/BC Command Definitions Table” in “■ FLEXIBLE SECTOR-ERASE ARCHITECTURE”.
*2 : Refer to the section on Sector Protection.
*3 : WE can be VIL if OE is VIL, OE at VIH initiates the write operations.
MBM29F200TC/BC User Bus Operation Table (BYTE = VIL)
Legend: L = VIL, H = VIH, X = VIL or VIH, = Pulse input. See DC Characteristics for vo ltage levels.
*1 : Manufacturer and device codes may also be accessed via a command register write sequence. Refer to
“MBM29F200TC/BC Command Definitions Table” in “■ FLEXIBLE SECTOR-ERASE ARCHITECTURE”.
*2 : Refer to the section on Sector Protection.
*3 : WE can be VIL if OE is VIL, OE at VIH initiates the wr ite operations.
Operation CE OE WE A0A1A6A9DQ15 to
DQ0RESET
Auto-Select Manufacturer Code *1LLHLLLVID Code H
Auto-Select Device Code *1LLHHLLVID Code H
Read *3LLHA0A1A6A9DOUT H
Standby HXXXXXXHigh-Z H
Output Disable LHHXXXXHigh-Z H
Write L H L A0A1A6A9DIN H
Enable Sector Protection *2LVID LHLVID XH
Verify Sector Protection *2LLHLHLVID Code H
Temporary Sector Unprotection XXXXXXX X V
ID
Reset (Hardware)/Standby XXXXXXXHigh-Z L
Operation CE OE WE DQ15
/A-1 A0A1A6A9DQ7 to DQ0RESET
Auto-Select Manufacturer Code *1LLHLLLLVID Code H
Auto-Select Device Code *1LLHLHLLVID Code H
Read *3LLHA-1 A0A1A6A9DOUT H
Standby H XXXXXXX High-Z H
Output Disable L HHXXXXX High-Z H
Write L H L A-1 A0A1A6A9DIN H
Enable Sector Protection *2LVID LLHLVID XH
Verify Sector Protection *2LLHLLHLVID Code H
Temporary Sector Unprotection XXXXXXXX X V
ID
Reset (Hardware)/Standby XXXXXXXX High-Z L
MBM29F200TC-55/70/90/MBM29F200BC-55/70/90
7
MBM29F200TC/BC Command Definitions Table
*1 : Either of the two reset command will reset the device.
*2 : The fourth bus cycle is only for read.
Notes : • Address bits A16 to A11 = X = “H” or “L” for all address commands except or Program Address (PA) and
Sector Address (SA).
• Bus operations are defined in “MBM29F200TC/BC User Bus Operation Table (BYTE = VIH) ” and
“MBM29F200TC/BC User Bus Operation Table (BYTE = VIL) ” in “■ FLEXIBLE SECTOR-ERASE
ARCHITECTURE”.
• RA = Address of the memory location to be read.
IA = Autoselect read address that set A6, A1, A0, (A−1) .
PA = Address of the memory location to be programmed. Addresses are latched on the falling edge of
the WE pulse.
SA = Address of the sector to be erased. The combination of A16, A15, A14, A13, and A12 will
uniquely select any sector.
• RD = Data read from location RA during read operation.
ID = Device code/manufacture code for the address located by IA.
PD = Data to be programmed at location PA. Data is latched on the falling edge of WE.
• The system should generate the following address patterns:
Word Mode: 555h or 2AAh to addresses A10 to A0
Byte Mode: AAAh or 555h to addresses A10 to A-1
• Both Read/Reset commands are functionally equivalent, resetting the device to the read mode.
• The command conbinations not described in “MBM29F200TC/BC Command Definitions Table” in
“■ FLEXIBLE SECTOR-ERASE ARCHITECTURE” are illegal.
Command
Sequence
Bus
Write
Cycles
Req'd
First Bus
Write Cycle Second
Bus
Write Cycle Third Bus
Write Cycle Fourth Bus
Read/Write
Cycle Fifth Bus
Write Cycle Sixth Bus
Write Cycle
Addr Data Addr Data Addr Data Addr Data Addr Data Addr Data
Read/Reset*1Word 1XXXhF0h——————————
Byte
Read/Reset*1Word 3555h AAh 2AAh 55h 555h F0h RA*2RD*2————
Byte AAAh 555h AAAh
Autoselect Word 3555h AAh 2AAh 55h 555h 90h IA*2ID*2————
Byte AAAh 555h AAAh
Program Word 4555h AAh 2AAh 55h 555h A0h PA PD — — — —
Byte AAAh 555h AAAh
Chip Erase Word 6555h AAh 2AAh 55h 555h 80h 555h AAh 2AAh 55h 555h 10h
Byte AAAh 555h AAAh AAAh 555h AAAh
Sector Erase Word 6555h AAh 2AAh 55h 555h 80h 555h AAh 2AAh 55h SA 30h
Byte AAAh 555h AAAh AAAh 555h
Sector Erase Suspend Erase can be suspended during sector erase with Addr (“H” or “L”). Data (B0h)
Sector Erase Resume Erase can be resumed after suspend with Addr (“H” or “L”). Data (30h)
MBM29F200TC-55/70/90/MBM29F200BC-55/70/90
8
MBM29F200TC/BC Sector Protection Verify Autoselect Codes Table
*1 : A-1 is for Byte mode.
*2 : Outputs 01h at protected sector addresses and outputs 00h at unprotected sector addresses.
Extended Autoselect Code Table
(B): Byte mode
(W): Word mode
Type A16 to A12 A6A1A0A-1*1Code
(HEX)
Manufacturer’s Code X VIL VIL VIL VIL 04h
Device Code
MBM29F200TC Byte XV
IL VIL VIH VIL 51h
Word X 2251h
MBM29F200BC Byte XV
IL VIL VIH VIL 57h
Word X 2257h
Sector Protection Sector
Addresses VIL VIH VIL VIL 01h*2
Type Code DQ15 DQ14 DQ13 DQ12 DQ11 DQ10 DQ9DQ8DQ7DQ6DQ5DQ4DQ3DQ2DQ1DQ0
Manufacturer’s Code 04h A-1/0 000000000000100
Device
Code
MBM29F200TC (B) 51h A-1 HI-Z HI-Z HI-Z HI-Z HI-Z HI-Z HI-Z 0 1 0 1 0 0 0 1
(W) 2251h 0 010001001010001
MBM29F200BC (B) 57h A-1 HI-Z HI-Z HI-Z HI-Z HI-Z HI-Z HI-Z 0 1 0 1 0 1 1 1
(W) 2257h 0 010001001010111
Sector Protection 01h A-1/0 000000000000001
MBM29F200TC-55/70/90/MBM29F200BC-55/70/90
9
Sector Address Table (MBM29F200TC)
Sector Address Table (MBM29F200BC)
Sector Architecture
• One 16K byte, two 8K bytes, one 32K byte, and three 64K bytes
• Individual-sector, multiple-sector, or bulk-erase capability
• Individual or multiple-sector protection is user definable.
Sector
Address A16 A15 A14 A13 A12 Address Range
SA0 0 0 X X X 00000h to 0FFFFh
SA1 0 1 X X X 10000h to 1FFFFh
SA2 1 0 X X X 20000h to 2FFFFh
SA3 1 1 0 X X 30000h to 37FFFh
SA411100 38000h to 39FFFh
SA511101 3A000h to 3BFFFh
SA61111X 3C000h to 3FFFFh
Sector
Address A16 A15 A14 A13 A12 Address Range
SA00000X 00000h to 03FFFh
SA100010 04000h to 05FFFh
SA200011 06000h to 07FFFh
SA3 0 0 1 X X 08000h to 0FFFFh
SA4 0 1 X X X 10000h to 1FFFFh
SA5 1 0 X X X 20000h to 2FFFFh
SA6 1 1 X X X 30000h to 3FFFFh
3FFFFh
3BFFFh
39FFFh
37FFFh
2FFFFh
1FFFFh
0FFFFh
00000h
16K byte
8K byte
8K byte
32K byte
64K byte
64K byte
64K byte
MBM29F200TC Sector Architecture
3FFFFh
2FFFFh
1FFFFh
0FFFFh
07FFFh
05FFFh
03FFFh
00000h
64K byte
64K byte
64K byte
32K byte
8K byte
8K byte
16K byte
MBM29F200BC Sector Architecture
(×8) 1FFFFh
1DFFFh
1CFFFh
1BFFFh
17FFFh
0FFFFh
07FFFh
00000h
(×16) 1FFFFh
17FFFh
0FFFFh
07FFFh
03FFFh
02FFFh
01FFFh
00000h
(×16)(×8)
MBM29F200TC-55/70/90/MBM29F200BC-55/70/90
10
■
■■
■FUNCTIONAL DESCRIPTION
Read Mode
The MBM29F200TC/BC has two control functions which must be satisfied in order to obtain data at the outputs .
CE is the pow er control and should be used f or a de vice selection. OE is the output control and should be used
to gate data to the output pins if a device is selected.
Address access time (tACC) is equal to the delay from stable addresses to valid output data. The chip enable
access time (tCE) is the delay from stable addresses and stable CE to valid data at the output pins. The output
enable access time is the delay from the falling edge of OE to valid data at the output pins (Assuming the
addresses have been stable for at least tACC - tCE time).
Standby Mode
There are two w ays to implement the standb y mode on the MBM29F200TC/BC de vices, one using both the CE
and RESET pins; the other via the RESET pin only.
When using both pins, a CMOS standb y mode is achie v ed with CE and RESET inputs both held at VCC ± 0.3 V.
Under this condition the current consumed is less than 5 µA max. A TTL standby mode is achie v ed with CE and
RESET pins held at VIH. Under this condition the current is reduced to approximately 1mA. During Embedded
Algorithm operation, VCC Active current (ICC2) is required even CE = VIH. The device can be read with standard
access time (tCE) from either of these standby modes.
When using the RESET pin only, a CMOS standby mode is achieved with RESET input held at VSS ± 0.3 V
(CE = “H” or “L”). Under this condition the current is consumed is less than 5 µA max. A TTL standby mode is
achieved with RESET pin held at VIL, (CE= “H” or “L”). Under this condition the current required is reduced to
appro ximately 1mA. Once the RESET pin is taken high, the device requires tRH of wake up time before outputs
are valid for read access.
In the standby mode the outputs are in the high impedance state, independent of the OE input.
Output Disable
With the OE input at a logic high level (VIH), output from the device is disabled. This will cause the output pins
to be in a high impedance state.
Autoselect
The autoselect mode allows the reading out of a binary code from the device and will identify its manufacturer
and type. This mode is intended for use by progr amming equipment for the purpose of automatically matching
the de vices to be progr ammed with its corresponding progr amming algorithm. This mode is functional ov er the
entire temperature range of the device.
To activate this mode, the programming equipment must force VID (11.5 V to 12.5 V) on address pin A9. Two
identifier bytes may then be sequenced from the devices outputs by toggling address A0 from VIL to VIH. All
addresses are don't cares except A0, A1 and A6 ( A-1) (See “MBM29F200TC/BC Sector Protection Verify
Autoselect Code Table” in “■ FLEXIBLE SECTOR-ERASE ARCHITECTURE”).
The manufacturer and device codes may also be read via the command register, for instances when the
MBM29F200TC/BC is erased or programmed in a system without access to high voltage on the A9 pin. The
command sequence is illustrated in “MBM29F200TC/BC Command Definitions Table” in “■ FLEXIBLE SECTOR-
ERASE ARCHITECTURE” (refer to Autoselect Command section).
A0 = VIL represents the manufacturer’s code (Fujitsu = 04h) and A0 = VIH the device identifier code
(MBM29F200TC =51h and MBM29F200BC = 57h for ×8 mode; MBM29F200TC = 2251h and MBM29F200
BC = 2257h for ×16 mode). These two bytes/words are given in the “MBM29F200TC/BC Sector Protection V erify
Autoselect Code Table” and “Extended Autoselect Code Table” in “■ FLEXIBLE SECTOR-ERASE
ARCHITECTURE”. All identifiers for manufacturer and device will exhibit odd parity with DQ7 defined as the
parity bit. In order to read the proper device codes when executing the autoselect, A1 must be VIL (See
“MBM29F200TC/BC Sector Protection Verify Autoselect Code Table” and “Extended A utoselect Code Table” in
“■ FLEXIBLE SECTOR-ERASE ARCHITECTURE”).
MBM29F200TC-55/70/90/MBM29F200BC-55/70/90
11
Write
Device erasure and programming are accomplished via the command register. The contents of the register serve
as inputs to the internal state machine. The state machine outputs dictate the function of the device.
The command register itself does not occup y any addressab le memory location. The register is a latch used to
store the commands, along with the address and data information needed to execute the command. The
command register is written by bringing WE to VIL, while CE is at VIL and OE is at VIH. Addresses are latched on
the falling edge of WE or CE, whichever happens later; while data is latched on the rising edge of WE or CE,
whichever happens first. Standard microprocessor write timings are used.
Refer to AC Write Characteristics and the Erase/Programming Waveforms for specific timing parameters.
Sector Protection
The MBM29F200TC/BC f eatures hardw are sector protection. This feature will disable both progr am and erase
operations in an y number of sectors (0 through 6). The sector protection f eature is enabled using prog ramming
equipment at the user’s site. The device is shipped with all sectors unprotected.
To activate this mode, the programming equipment must force VID on address pin A9 and control pin OE, (suggest
VID = 11.5V), CE = VIL, and A6 = VIL. The sector addresses (A16, A15, A14, A13, and A12) should be set to the sector
to be protected. “Sector Address Table (MBM29F200TC) ” and “Sector Address Table (MBM29F200BC) ” in “■
FLEXIBLE SECTOR-ERASE ARCHITECTURE” define the sector address for each of the seven (7) individual
sectors. Programming of the protection circuitry begins on the falling edge of the WE pulse and is terminated
with the rising edge of the same. Sector addresses must be held constant during the WE pulse. Refer to “AC
Wav eforms for Sector Protection Timing Diag r am” in “■ TIMING DIA GRAM” and “Sector Protection Algorithm”
in “■ FLOW CHART” for sector protection waveforms and algorithm.
To v erify programming of the protection circuitry, the progr amming equipment must force VID on address pin A9
with CE and OE at VIL and WE at VIH. Scanning the sector addresses ( A16, A15, A14, A13, and A12) while (A6, A1,
A0) = (0, 1, 0) will produce a logical “1” code at de vice output DQ0 f or a protected sector. Otherwise the devices
will produce 00h for unprotected sector. In this mode, the lower order addresses, except for A0, A1, and A6 are
don't care. Address locations with A1 = VIL are reserved for Autoselect manufacturer and device codes. A-1
requires to apply to VIL on byte mode.
It is also possible to determine if a sector is protected in the system by writing an Autoselect command. Performing
a read operation at the address location XX02h, where the higher order addresses ( A16, A15, A14, A13, and A12)
are the desired sector address will produce a logical “1” at DQ0 f or a protected sector . See “MBM29F200TC/BC
Sector Protection Verify Autoselect Code Table” and “Extended Autoselect Code Table” in “■ FLEXIBLE
SECTOR-ERASE ARCHITECTURE” for Autoselect codes.
Temporary Sector Unprotection
This f eature allows tempor ary unprotection of pre viously protected sectors of the MBM29F200TC/BC de vice in
order to change data. The Sector Unprotection mode is activated by setting the RESET pin to high voltage
(12 V). During this mode, formerly protected sectors can be programmed or erased by selecting the sector
addresses. Once the 12 V is taken away from the RESET pin, all the previously protected sectors will be protected
again. Refer to “Temporary Sector Unprotection Timing Diagram” in “■ TIMING DIAGRAM” and “Temporary
Sector Unprotection Algorithm” in “■ FLOW CHART”.
Command Definitions
Device operations are selected by writing specific address and data sequences into the command register.
Writing incorrect address and data values or writing them in the improper sequence will reset the de vice to the
read mode. “MBM29F200TC/BC Command Definitions Table” in “■ FLEXIBLE SECTOR-ERASE
ARCHITECTURE” defines the valid register command sequences. Note that the Erase Suspend (B0h) and
Erase Resume (30h) commands are valid only while the Sector Erase oper ation is in prog ress. Moreover both
Read/Reset commands are functionally equivalent, resetting the device to the read mode. Please note that
commands are always written at DQ7 to DQ0 and DQ15 to DQ8 bits are ignored.
MBM29F200TC-55/70/90/MBM29F200BC-55/70/90
12
Read/Reset Command
The read or eset operation is initiated b y writing the read/reset command sequence into the command register .
Microprocessor read cycles retriev e array data from the memory. The de vices remain enabled f or reads until the
command register contents are altered.
The device will automatically power-up in the read/reset state. In this case, a command sequence is not required
to read data. Standard microprocessor read cycles will retrieve array data. This default value ensures that no
spurious alteration of the memory content occurs during the power transition. Refer to the AC Read
Characteristics and Waveforms for the specific timing parameters.
Autoselect Command
Flash memories are intended for use in applications where the local CPU alters memory contents. As such,
manufacture and device codes must be accessible while the devices reside in the target system. PROM
programmers typically access the signature codes by raising A9 to a high voltage. Ho wever, multiplexing high
voltage onto the address lines is not generally desired system design practice.
The device contains an autoselect command operation to supplement traditional PROM programming
methodology. The operation is initiated by writing the autoselect command sequence into the command register .
F ollowing the command write, a read cycle from address XX00h retrie v es the manuf acture code of 04h. A read
cycle from address XX01h for ×16 (XX02h for ×8) returns the device code (MBM29F200TC = 51h and
MBM29F200BC = 57h for ×8 mode; MBM29F200TC = 2251h and MBM29F200BC = 2257h for ×16 mode). (See
“MBM29F200TC/BC Sector Protection Verify Autoselect Code Table” and “Extended A utoselect Code Table” in
“■ FLEXIBLE SECTOR-ERASE ARCHITECTURE”.)
All manufacturer and device codes will exhibit odd parity with DQ7 defined as the parity bit.
Scanning the sector addresses ( A16, A15, A14, A13, and A12) while (A6, A1, A0) = (0, 1, 0) will produce a logical “1”
at device output DQ0 for a protected sector. The programming verification should be perform margin mode on
the protected sector (See “MBM29F200TC/BC User Bus Operation Table (BYTE = VIH) ” and “MBM29F200TC/
BC User Bus Operation Table (BYTE = VIL) ” in “■ FLEXIBLE SECTOR-ERASE ARCHITECTURE”).
To terminate the operation, it is necessary to write the read/reset command sequence into the register and also
to write the autoselect command during the operation, execute it after writing read/reset command sequence.
Byte/Word Programming
The device is programmed on a byte-by-byte (or word-by-word) basis. Programming is a four bus cycle operation.
There are two “unloc k” write cycles. These are f ollowed b y the program set-up command and data write cycles .
Addresses are latched on the f alling edge of CE or WE, whiche v er happens later and the data is latched on the
rising edge of CE or WE, whichever happens first. The rising edge of CE or WE (whichever happens first) begins
programming. Upon executing the Embedded ProgramTM Algorithm command sequence the system is not
required to provide further controls or timings. The device will automatically provide adequate internally generated
program pulses and verify the programmed cell margin.
The automatic programming operation is completed when the data on DQ7 is equiva lent to data written to this
bit at which time the devices return to the read mode and addresses are no longer latched (see “Hardware
Sequence Flags Table” in “■ FUNCTIONAL DESCRIPTION”, Hardware Sequence Flags) Therefore, the devices
require that a v alid address to the de vices be supplied by the system at this particular instance of time. Hence ,
Data Polling must be performed at the memory location which is being programmed.
Any commands written to the chip during this period will be ignored. If hardware reset occurs during the
programming operation, it is impossible to guarantee the data are being written.
Programming is allowed in any sequence and across sector boundaries. Beware that a data “0” cannot be
programmed bac k to a “1”. Attempting to do so may either hang up the de vice or result in an apparent success
according to the data polling algorithm but a read from read/reset mode will show that the data is still “0”. Only
erase operations can convert “0”s to “1”s.
“Data Polling algorithm” in “■ FLOW CHART” illustrates the Embedded Programming Algorithm using typical
command strings and bus operations.
MBM29F200TC-55/70/90/MBM29F200BC-55/70/90
13
Chip Erase
Chip erase is a six bus cycle operation. There are two “unlock” write cycles. These are followed by writing the
“set-up” command. Two more “unlock” write cycles are then followed by the chip erase command.
Chip erase does not require the user to program the device prior to erase. Upon executing the Embedded EraseTM
Algorithm command sequence the device will automatically prog ram and verify the entire memory f or an all zero
data pattern prior to electrical erase. The system is not required to provide an y controls or timings during these
operations.
The automatic erase begins on the rising edge of the last WE pulse in the command sequence and terminates
when the data on DQ7 is “1” (see Write Operation Status section) at which time the device returns to read the
mode.
“Toggle Bit algorithm” in “■ FLOW CHART” illustrates the Embedded Erase Algorithm using typical command
strings and bus operations.
Sector Erase
Sector erase is a six b us cycle operation. There are two “unloc k” write cycles. These are f ollow ed by writing the
“set-up” command. Two more “unloc k” write cycles are then follo wed b y the sector erase command. The sector
address (any address location within the desired sector) is latched on the falling edge of WE, while the command
(Data = 30h) is latched on the rising edge of WE. After time-out of 50 µs from the rising edge of the last sector
erase command, the sector erase operation will begin.
Multiple sectors may be erased concurrently by writing the six bus cycle operations on “MBM29F200TC/BC
Command Definitions Table” in “ ■ FLEXIBLE SECTOR-ERASE ARCHITECTURE”. This sequence is follo w ed
with writes of the Sector Erase command to addresses in other sectors desired to be concurrently erased. The
time between writes must be less than 50 µs otherwise that command will not be accepted and erasure will start.
It is recommended that processor interrupts be disabled during this time to guarantee this condition. The
interrupts can be re-enabled after the last Sector Erase command is written. A time-out of 50 µs from the rising
edge of the last WE will initiate the e xecution of the Sector Er ase command(s). If another fa lling edge of the WE
occurs within the 50 µs time-out window the timer is reset. (Monitor DQ3 to determine if the sector erase timer
window is still open, see section DQ3, Sector Erase Timer.) Any commands other than Sector Erase or Erase
Suspend during this time-out period will reset the devices to the read mode, ignoring the previous command
string. Resetting the device once execution has begun will corrupt the data in that sector. In that case, restart
the erase on those sectors and allo w them to complete. (Refer to the Write Operation Status section for Sector
Erase Timer operation.) Loading the sector er ase b uff er ma y be done in an y sequence and with any n umber of
sectors (0 to 6).
Sector erase does not require the user to program the devices prior to erase. The device automatically programs
all memory locations in the sector(s) to be erased prior to electrical er ase. When erasing a sector or sectors the
remaining unselected sectors are not affected. The system is not required to provide any controls or timings
during these operations.
The automatic sector erase begins after the 50 µs time out from the rising edge of the WE pulse for the last
sector erase command pulse and terminates when the data on DQ7 is “1” (see Write Operation Status section)
at which time the de vice returns to the read mode. Data polling must be perf ormed at an address within any of
the sectors being erased.
“Toggle Bit algorithm” in “■ FLOW CHART” illustrates the Embedded Erase Algorithm using typical command
strings and bus operations.
Erase Suspend
The Erase Suspend command allows the user to interrupt a Sector Erase operation and then perform data reads
from or programs to a sector not being erased. This command is applicable ONLY during the Sector Erase
operation which includes the time-out period for sector erase. The Erase Suspend command will be ignored if
written during the Chip Erase operation or Embedded Program Algorithm. Writting the Erase Suspend command
MBM29F200TC-55/70/90/MBM29F200BC-55/70/90
14
during the Sector Erase time-out results in immediate termination of the time-out period and suspension of the
erase operation.
Writing the Erase Resume command resumes the erase operation. The addresses are “don’t cares” when writing
the Erase Suspend or Erase Resume command.
When the Erase Suspend command is written during the Sector Erase operation, the device will take a maximum
of 20 µs to suspend the erase operation. When the device has entered the erase-suspended mode, the RY/BY
output pin and the DQ7 bit will be at logic “1”, and DQ6 will stop toggling. The user must use the address of the
erasing sector f or reading DQ6 and DQ7 to determine if the erase operation has been suspended. Further writes
of the Erase Suspend command are ignored.
When the erase operation has been suspended, the de vice def aults to the erase-suspend-read mode . Reading
data in this mode is the same as reading from the standard read mode e xcept that the data m ust be read from
sectors that hav e not been erase-suspended. Successiv ely reading from the erase-suspended sector while the
device is in the erase-suspend-read mode will cause DQ2 to toggle. (See the section on DQ2).
After entering the erase-suspend-read mode, the user can program the device by writing the appropriate
command sequence for Program. This program mode is known as the erase-suspend-program mode. Again,
programming in this mode is the same as prog ramming in the regular Progr am mode e xcept that the data must
be programmed to sectors that are not erase-suspended. Successively reading from the erase-suspended sector
while the device is in the erase-suspend-program mode will cause DQ2 to toggle. The end of the erase-suspended
program oper ation is detected by the RY/BY output pin, Data polling of DQ7, or by the Toggle Bit I (DQ6) which
is the same as the regular Program oper ation. Note that DQ7 must be read from the program address while DQ6
can be read from any address.
To resume the operation of Sector Erase , the Resume command (30h) should be written. Any further writes of
the Resume command at this point will be ignored. Another Erase Suspend command can be written after the
chip has resumed erasing.
Write Operation Status Hardware Sequence Flags Table
*1 : Performing successive read operations from any address will cause DQ6 to toggle.
*2 : Reading the byte address being programmed while in the erase-suspend program mode will indicate
logic “1” at the DQ2 bit. However, successive reads from the erase-suspended sector will cause DQ2 to
toggle.
Notes : • DQ0 and DQ1 are reserve pins for future use. DQ4 is Fujitsu internal use only.
• DQ15 to DQ8 are “DON’T CARES” because there is for × 16 mode.
Status DQ7DQ6DQ5DQ3DQ2
In
Progress
Embedded Progr am Algorithm DQ7Toggle 0 0 1
Embedded Erase Algorithm 0 Toggle 0 1 Toggle
Erase
Suspended
Mode
Erase Suspend Read
(Erase Suspended Sector) 1100Toggle
Erase Suspend Read
(Non-Erase Suspended Sector) Data Data Data Data Data
Erase Suspend Program
(Non-Erase Suspended Sector) DQ7Toggle*1001*2
Exceeded
Time
Limits
Embedded Progr am Algorithm DQ7Toggle 1 0 1
Embedded Erase Algorithm 0 Toggle 1 1 N/A
Erase
Suspended
Mode Erase Suspend Program
(Non-Erase Suspended Sector) DQ7Toggle 1 0 N/A
MBM29F200TC-55/70/90/MBM29F200BC-55/70/90
15
DQ7
Data Polling
The MBM29F200TC/BC device feature Data Polling as a method to indicate to the host that the Embedded
Algorithms are in progress or completed. During the Embedded Program Algorithm an attempt to read the device
will produce the complement of the data last written to DQ7. Upon completion of the Embedded Program
Algorithm, an attempt to read the device will produce the true data last written to DQ7. During the Embedded
Erase Algorithm, an attempt to read the device will produce a “0” at the DQ7 output. Upon completion of the
Embedded Erase Algorithm an attempt to read the device will produce a “1” at the DQ7 output. The flowchart
for Data Polling (DQ7) is shown in “Sector Protection Algorithm” in “■ FLOW CHART”.
For Programing, the Data P olling is valid after the rising edge of fourth write pulse in the four write pulse sequence.
F or chip erase and sector erase , the Data Polling is valid after the rising edge of the sixth write pulse in the six
write pulse sequence. Data P olling m ust be perf ormed at sector address within any of the sectors being erased
and not a protected sector. Otherwise, the status ma y not be v alid. Once the Embedded Algorithm operation is
close to being completed, the MBM29F200TC/BC data pins (DQ7) may change asynchronously while the output
enable (OE) is asserted low. This means that the device is driving status information on DQ7 at one instant of
time and then that byte’s valid data at the ne xt instant of time. Depending on when the system samples the DQ7
output, it may read the status or valid data. Even if the device has completed the Embedded Algorithm operation
and DQ7 has a v alid data, the data outputs on DQ6 to DQ0 ma y be still inv alid. The v alid data on DQ7 to DQ0 will
be read on the successive read attempts.
The Data Polling feature is only active during the Embedded Programming Algorithm, Embedded Erase Algorithm
or sector erase time-out (See “Hardware Sequence Flags Table” in “■ FUNCTIONAL DESCRIPTION”).
See “AC Waveforms for Data P olling during Embedded Algorithm Operations” in “■ TIMING DIA GRAM” f or the
Data Polling timing specifications and diagrams.
DQ6
Toggle Bit I
The MBM29F200TC/BC also feature the “Toggle Bit I” as a method to indicate to the host system that the
Embedded Algorithms are in progress or completed.
During an Embedded Program or Erase Algorithm cycle, successive attempts to read (OE toggling) data from
the device will result in DQ6 toggling between one and z ero. Once the Embedded Progr am or Er ase Algorithm
cycle is completed, DQ6 will stop toggling and valid data will be read on the next successive attempts. During
programming, the Toggle Bit I is valid after the rising edge of the fourth write pulse in the four write pulse sequence.
For chip erase and sector erase, the Toggle Bit I is valid after the rising edge of the sixth write pulse in the six
write pulse sequence. The Toggle Bit I is active during the sector time out.
In programming, if the sector being written to is protected, the toggle bit l will toggle f or about 2 µs and then stop
toggling without the data having changed. In er ase , the device will erase all the selected sectors e xcept for the
ones that are protected. If all selected sectors are protected, the chip will toggle the toggle bit f or about 100 µs
and then drop back into read mode, having changed none of the data.
Either CE or OE toggling will cause the DQ6 to toggle. In addition, an Erase Suspend/Resume command will
cause DQ6 to toggle.
See “AC Wavef o rms f or Toggle Bit I during Embedded Algorithm Operations” in “■ TIMING DIAGRAM” for the
Toggle Bit I timing specifications and diagrams.
DQ5
Exceeded Timing Limits
DQ5 will indicate if the program or erase time has ex ceeded the specified limits (internal pulse count). Under
these conditions DQ5 will produce a “1”. This is a failure condition which indicates that the program or erase
MBM29F200TC-55/70/90/MBM29F200BC-55/70/90
16
cycle was not successfully completed. Data Polling is the only operating function of the devices under this
condition. The CE circuit will partially power down the device under these conditions (to approximately 2 mA).
The OE and WE pins will control the output disable functions as described in “MBM29F200TC/BC User Bus
Operation Table (BYTE = VIH) ” and “MBM29F200TC/BC User Bus Operation Table (BYTE = VIL) ” in “■ FLEXIBLE
SECTOR-ERASE ARCHITECTURE”.
The DQ5 f ailure condition may also appear if a user tries to progr am a non blank location without erasing. In this
case the device locks out and never complete the Embedded Algorithm operation. Hence, the system never
reads a valid data on DQ7 bit and DQ6 never stops toggling. Once the device has exceeded timing limits, the
DQ5 bit will indicate a “1”. Please note that this is not a de vice f ailure condition since the de vice w as incorrectly
used.
DQ3
Sector Erase Timer
After the completion of the initial sector erase command sequence the sector erase time-out will begin. DQ 3 will
remain low until the time-out is complete. Data Polling and Toggle Bit are valid after the initial sector erase
command sequence.
If Data Polling or the Toggle Bit I indicates the device has been written with a valid erase command, DQ3 may
be used to determine if the sector erase timer window is still open. If DQ3 is high (“1”) the internally controlled
erase cycle has begun; attempts to write subsequent commands to the device will be ignored until the erase
operation is completed as indicated by Data Polling or Toggle Bit I. If DQ3 is low (“0”), the device will accept
additional sector erase commands. To insure the command has been accepted, the system software should
check the status of DQ3 prior to and f ollowing each subsequent sector erase command. If DQ3 w ere high on the
second status check, the command may not have been accepted.
Refer to “Hardware Sequence Flags Table” in “■ FUNCTIONAL DESCRIPTION”: Hardware Sequence Flags.
DQ2
Toggle Bit II
This toggle bit II, along with DQ6, can be used to determine whether the device is in the Embedded Erase
Algorithm or in Erase Suspend.
Successive reads from the erasing sector will cause DQ2 to toggle during the Embedded Erase Algorithm. If the
device is in the erase-suspended-read mode, successive reads from the erase-suspended sector will cause DQ2
to toggle. When the device is in the erase-suspended-program mode , successive reads from the byte address
of the non-erase suspended sector will indicate a logic “1” at the DQ2 bit.
DQ6 is different from DQ2 in that DQ6 toggles only when the standard program or Erase, or Erase Suspend
Program oper ation is in prog ress . The behavior of these two status bits, along with that of DQ7, is summarized
as follows:
*1 : These status flags apply when outputs are read from a sector that has been erase-suspended.
*2 : These status flags apply when outputs are read from the byte address of the non-erase suspended sector.
Mode DQ7DQ6DQ2
Program DQ7Toggle 1
Erase 0 Toggle Toggle
Erase Suspend Read
(Erase-Suspended Sector) *111Toggle
Erase Suspend Program DQ7*2Toggle 1*2
MBM29F200TC-55/70/90/MBM29F200BC-55/70/90
17
For example, DQ2 and DQ6 can be used together to determine the erase-suspend-read mode (DQ2 toggles while
DQ6 does not). See also “Hardware Sequence Flags Table” in “■ FUNCTIONAL DESCRIPTION” and “Temporary
Sector Unprotection Algorithm” in “■ FLOW CHART”.
Furthermore, DQ2 can also be used to determine which sector is being erased. When the de vice is in the erase
mode, DQ2 toggles if this bit is read from the erasing sector.
RY/BY
Ready/Busy
The MBM29F200TC/BC provides a RY/BY open-drain output pin as a way to indicate to the host system that
the EmbeddedTM Algorithms are either in progress or completed. If the output is low, the device is busy with
either a program or erase operation. If the output is high, the device is ready to accept any read/write or erase
operation. When the RY/BY pin is low, the de vice will not accept any additional prog ram or er ase commands. If
the MBM29F200TC/BC is placed in an Erase Suspend mode , the RY/BY output will be high. Also, since this is
an open drain output, many RY/BY pins can be tied together in parallel with a pull up resistor to VCC.
During programming, the R Y/BY pin is driv en low after the rising edge of the fourth write pulse. During an erase
operation, the RY/BY pin is driven lo w after the rising edge of the sixth write pulse. The RY/BY pin will indicate
a busy condition during the RESET pulse. Refer to “RY/BY Timing Diagram during Program/Er ase Operations”
and “RESET/RY/BY Timing Diagram” in “■ TIMING DIAGRAM” for a detailed timing diagram.
Since this is an open-drain output, several RY/BY pins can be tied together in parallel with a pull-up resistor to VCC.
RESET
Hardware Reset
The MBM29F200TC/BC device may be reset by driving the RESET pin to VIL. The RESET pin has a pulse
requirement and has to be kept lo w (VIL) f or at least 500 ns in order to properly reset the internal state machine.
Any operation in the process of being executed will be terminated and the internal state machine will be reset
to the read mode 20 µs after the RESET pin is driven low. Furthermore, once the RESET pin goes high, the
de vice requires time of tRH before it will allow read access. When the RESET pin is lo w, the device will be in the
standby mode for the duration of the pulse and all the data output pins will be tri-stated. If a hardware reset
occurs during a program or erase operation, the data at that particular location will be corrupted. Please note
that the RY/BY output signal should be ignored during the RESET pulse. Refer to “RESET/RY/BY Timing
Diagram” in “■ TIMING DIAGRAM” for the timing diagram. Refer to Temporary Sector Unprotection for additional
functionality.
If hardware reset occurs during Embedded Erase Algorithm, there is a possibility that the erasing sector(s)
cannot be used.
Byte/Word Configuration
The BYTE pin selects the byte (8-bit) mode or w ord (16-bit) mode for the MBM29F200TC/BC de vice. When this
pin is driven high, the device operates in the word (16-bit) mode. The data is read and prog rammed at DQ15 to
DQ0. When this pin is driven low, the device operates in byte (8-bit) mode. Under this mode, the DQ15/A-1 pin
becomes the low est address bit and DQ14 to DQ8 bits are tri-stated. Howe v er , the command bu s cycle is alwa ys
an 8-bit operation and hence commands are written at DQ7 to DQ0 and the DQ15 to DQ8 bits are ignored. Ref er
to “Timing Diagram for Byte Mode Configuration”, “BYTE Timing Diagram for Write Operations” and “AC
Waveforms for Sector Protection Timing Diagram” in “■ TIMING DIAGRAM” for the timing diagram.
Data Protection
The MBM29F200TC/BC are designed to off er protection against accidental erasure or programming caused b y
spurious system lev el signals that ma y e xist during pow er transitions. During powe r up the device automatically
resets the internal state machine in the read mode. Also, with its control register architecture, alteration of the
memory contents only occurs after successful completion of specific multi-bus cycle command sequences.
The device also incorporate several f eatures to prevent inadvertent write cycles resulting form VCC power-up and
power-down transitions or system noise.
MBM29F200TC-55/70/90/MBM29F200BC-55/70/90
18
Low VCC Write Inhibit
To avoid initiation of a write cycle during VCC power-up and po w er-do wn, a write cycle is lock ed out for VCC less
than 3.2 V (typically 3.7 V). If VCC < VLKO, the command register is disabled and all internal program/erase circuits
are disabled. Under this condition the de vice will reset to the read mode. Subsequent writes will be ignored until
the VCC le vel is g reater than VLKO. It is the users responsibility to ensure that the control pins are logically correct
to prevent unintentional writes when VCC is above 3.2 V.
If Embedded Erase Algorithm is interrupted, there is possibility that the erasing sector(s) cannot be used.
Write Pulse “Glitch” Protection
Noise pulses of less than 5 ns (typical) on OE, CE, or WE will not initiate a write cycle.
Logical Inhibit
Writing is inhibited by holding any one of OE = VIL, CE = VIH, or WE = VIH. To initiate a write cycle CE and WE
must be a logical zero while OE is a logical one.
Power-Up Write Inhibit
Power-up of the device with WE = CE = VIL and OE = VIH will not accept commands on the rising edge of WE.
The internal state machine is automatically reset to the read mode on power-up.
MBM29F200TC-55/70/90/MBM29F200BC-55/70/90
19
■
■■
■ABSOLUTE MAXIMUM RATINGS
*1 : Voltage is defined on the basis of VSS = GND = 0 V.
*2 : Minimum DC v oltage on input or I/O pins is –0.5 V. During voltage tr ansitions, input or I/O pins ma y undershoot
VSS to –2.0 V for periods of up to 20 ns. Maximum DC voltage on output and I/O pins is VCC +0.5 V. During voltage
transitions, input or I/O pins may overshoot to VCC +2.0 V for periods of up to 20 ns.
*3 : Minimum DC input voltage on A9, OE, and RESET pins is –0.5 V. During voltage transitions, A9, OE, and RESET
pins may undershoot VSS to –2.0 V for periods of up to 20 ns. Maximum DC input voltage on A9,OE, and RESET
pins is +13.0 V which ma y ov ershoot to 13.5 V f or periods of up to 20 ns. Voltage diff erence between input and
supply voltage (VIN - VCC) does not exceed +9.0 V.
WARNING: Semiconductor devices can be permanently damaged by application of stress (voltage, current,
temperature, etc.) in excess of absolute maximum ratings. Do not exceed these ratings.
■
■■
■RECOMMENDED OPERATING CONDITIONS
* : Voltage is defined on the basis of VSS = GND = 0 V.
Note : Operating ranges define those limits between which the functionality of the devices are guaranteed.
WARNING: The recommended operating conditions are required in order to ensure the normal operating ranges
for the semiconductor device. All of the device’s electrical characteristics are warranted whent the
device is operated within these ranges.
Always use semiconductor devices within their recommended operating condition ranges.
Operation outside these ranges may adversely affect reliability and could result in device failure.
No warr anty is made with respect to uses, operating conditions, or combinations not represented
on the data sheet. Users considering application outside the listed conditions are advised to contact
their FUJITSU representatives beforehand.
Parameter Symbol Rating Unit
Min Max
Storage Temperature Tstg –55 +125 °
°°
°C
Ambient Temperature with Power Applied TA–40 +85 °C
Voltage with respect to Ground All pins except
A9, OE, and RESET *1, *2VIN, VOUT –2.0 +7.0 V
Power Supply Voltage *1VCC –2.0 +7.0 V
A9, OE, RESET *2, *3VIN –2.0 +13.5 V
Parameter Symbol Value Unit
Min Max
Ambient Temperatue MBM29F200TC/BC-55 TA–20 +70 °C
MBM29F200TC/BC-70/-90 –40 +85
Power Supply Voltage* MBM29F200TC/BC-55 VCC +4.75 +5.25 V
MBM29F200TC/BC-70/-90 +4.50 +5.50 V
MBM29F200TC-55/70/90/MBM29F200BC-55/70/90
20
■
■■
■MAXIMUM OVERSHOOT/MAXIMUM UNDERSHOOT
1. Maximum Unders hoot Waveform
2. Maximum Overshoot Waveform
3. Maximum Overshoot Waveform
+0.8 V
–0.5 V
20 ns
–2.0 V 20 ns
20 ns
+2.0 V
VCC+0.5 V
20 ns
VCC+2.0 V 20 ns
20 ns
VCC+0.5 V
+13.0 V
20 ns
+14.0 V 20 ns
20 ns
Note : This waveform is applied for A9, OE and RESET.
MBM29F200TC-55/70/90/MBM29F200BC-55/70/90
21
■
■■
■DC CHARACTERISTICS
*1 : The ICC current listed includes both the DC operating current and the frequency dependent component
(at 6 MHz). The frequency component typically is 2 mA/MHz, with OE at VIH.
*2 : ICC active while Embedded Algorithm (program or erase) is in progress.
*3 : Applicable to sector protection function.
*4 : (VID - VCC) do not exceed 9 V.
Description Symbol Test Conditions Min Max Unit
Input Leakage Current ILI VIN = VSS to VCC, VCC = VCC Max –1.0 +1.0 µA
Output Leakage Current ILO VOUT = VSS to VCC, VCC = VCC Max –1.0 +1.0 µA
A9, OE, RESET Inputs Leakage
Current ILIT VCC = VCC Max,
A9, OE, RESET = 12.5 V —50µA
VCC Active Current *1ICC1 CE = VIL, OE = VIH Byte —35 mA
Word 40
VCC Active Current *2ICC2 CE = VIL, OE = VIH —50mA
VCC Current (Standby) ICC3
VCC = VCC Max, CE = VIH,
RESET = VIH —1mA
VCC = VCC Max, CE = VCC ± 0.3 V,
RESET = VCC ± 0.3 V —5µA
VCC Current (Standby, Reset) ICC4
VCC = VCC Max,
RESET = VIL —1mA
VCC = VCC Max,
RESET = VSS ± 0.3 V —5µA
Input Low Level VIL — –0.5 0.8 V
Input High Level VIH —2.0VCC + 0.5 V
Voltage for Autoselect and
Sector Protection
(A9, OE, RESET) *3,*4VID — 11.5 12.5 V
Output Low Voltage Level VOL IOL = 5.8 mA, VCC = VCC Min — 0.45 V
Output High Voltage Level VOH1 IOH = –2.5 mA, VCC = VCC Min 2.4 — V
VOH2 IOH = –100 µA VCC – 0.4 — V
Low VCC Lock-Out Voltage VLKO —3.24.2V
MBM29F200TC-55/70/90/MBM29F200BC-55/70/90
22
■
■■
■AC CHARACTERISTICS
• Read Only Operations Characteristics
Description Symbol Test
Setup -55 *1-70 *2-90 *2Unit
JEDEC Standard Min Max Min Max Min Max
Read Cycle Time tAVAV tRC — 55 — 70 — 90 — ns
Address to Output Delay tAVQV tACC CE = VIL
OE = VIL —55—70—90ns
Chip Enable to Output Delay tELQV tCE OE = VIL —55—70—90ns
Output Enable to Output Delay tGLQV tOE — — 30 — 30 — 35 ns
Chip Enable to Output High-Z tEHQZ tDF — — 15 — 20 — 20 ns
Output Enable to Output High-Z tGHQZ tDF — — 15 — 20 — 20 ns
Output Hold Time From Addresses,
CE or OE, Whichever Occurs First tAXQX tOH —0—0—0—ns
RESET Pin Low to Read Mode — tREADY ——20—20—20µs
CE to BYTE Switching Low or High — tELFL
tELFH ——5—5—5ns
*1 : Test Conditions:
Output Load: 1 TTL gate and 30 pF
Input rise and fall times: 5 ns
Input pulse levels: 0.0 V/3.0 V
Timing measurement reference level
Input : 1.5 V
Output : 1.5 V
*2 : Test Conditions:
Output Load: 1 TTL gate and 100 pF
Input rise and fall times: 5 ns
Input pulse levels: 0.45 V/2.4 V
Timing measurement reference level
Input : 0.8 V and 2.0 V
Output : 0.8 V and 2.0 V
Test Conditions
CL
5.0 V
Diode = 1N3064
or Equivalent
2.7 kΩ
Device
Under
Test
Diode = 1N3064
or Equivalent
6.2 kΩ
Notes : • CL = 30 pF including jig capacitance
• CL = 100 pF including jig capacitance
MBM29F200TC-55/70/90/MBM29F200BC-55/70/90
23
• Write/Erase/Program Operations
(Continued)
Description
Symbol MBM29F200TC/BC
Unit
JEDEC Standard -55 -70 -90
Min Typ Max Min Typ Max Min Typ Max
Write Cycle Time tAVAV tWC 55 — — 70 — — 90 — — ns
Address Setup Time tAVWL tAS 0——0——0——ns
Address Hold Time tWLAX tAH 40 — — 45 — — 45 — — ns
Data Setup Time tDVWH tDS 25 — — 30 — — 45 — — ns
Data Hold Time tWHDX tDH 0——0——0——ns
Output Enable Setup Time — tOES 0——0——0——ns
Output
Enable
Hold Time
Read —t
OEH 0——0——0——ns
Toggle and Data Polling 10 — — 10 — — 10 — — ns
Read Recover Time Before Write tGHWL tGHWL 0——0——0——ns
Read Recover Time Before Write tGHEL tGHEL 0——0——0——ns
CE Setup Time tELWL tCS 0——0——0——ns
WE Setup Time tWLEL tWS 0——0——0——ns
CE Hold Time tWHEH tCH 0——0——0——ns
WE Hold Time tEHWH tWH 0——0——0——ns
Write Pulse Width tWLWH tWP 30 — — 35 — — 45 — — ns
CE Pulse Width tELEH tCP 30 — — 35 — — 45 — — ns
Write Pulse Width High tWHWL tWPH 20 — — 20 — — 20 — — ns
CE Pulse Width High tEHEL tCPH 20 — — 20 — — 20 — — ns
Byte Programming Operation tWHWH1 tWHWH1 —8——8——8—µs
Sector Erase Operation *1tWHWH2 tWHWH2 —1——1——1—s
—— 8——8 —— 8 s
VCC Setup Time — tVCS 50 — — 50 — — 50 — — µs
RiseTime to VID —tVIDR 500 — — 500 — — 500 — — ns
Voltage Transition Time *2—tVLHT 4——4——4——µs
Write Pulse Width *2—tWPP 100 — — 100 — — 100 — — µs
OE Setup Time to WE Active *2—tOESP 4——4——4——µs
CE Setup Time to WE Active *2—tCSP 4——4——4——µs
Recover Time from RY/BY —tRB 0——0——0——ns
MBM29F200TC-55/70/90/MBM29F200BC-55/70/90
24
(Continued)
*1 : This does not include the preprogramming time.
*2 : These timing is for Sector Protection operation.
Description
Symbol MBM29F200TC/BC
Unit
JEDEC Standard -55 -70 -90
Min Typ Max Min Typ Max Min Typ Max
RESET Pulse Width — tRP 500 — — 500 — — 500 — — ns
RESET Hold Time Before Read — tRH 50 — — 50 — — 50 — — ns
BYTE Switching Low to Output High-Z — tFLQZ — — 30 — — 30 — — 35 ns
BYTE Switching High to Output Active — tFHQV — — 55 — — 70 — — 90 ns
Progra m/Erase Valid to RY/BY Delay — tBUSY — — 55 — — 70 — — 90 ns
Delay Time from Embedded Output
Enable —t
EOE — — 55 — — 70 — — 90 ns
MBM29F200TC-55/70/90/MBM29F200BC-55/70/90
25
■
■■
■ERASE AND PROGRAMMING PERFORMANCE
■TSOP (1) PIN CAPACITANCE
Note : Test conditions TA = +25°C, f = 1.0 MHz
■SOP PIN CAPACITANCE
Note : Test conditions TA = +25°C, f = 1.0 MHz
Parameter Limits Unit Comment
Min Typ Max
Sector Erase Time — 1 8 s Excludes 00h programming
prior to erasure
Word Progra mming Time — 16 200 µs Excludes system-level
overhead
Byte Programming Time — 8 150 µs
Chip Programming Time — 2.1 5.0 s Excludes system-level
overhead
Erase/Program Cycle 100,000 — — cycle
Parameter
Symbol Parameter Description Test Setup Typ Max Unit
CIN Input Capacitance VIN = 0 8 9 pF
COUT Output Capacitance VOUT = 0 8 10 pF
CIN2 Control Pin Capacitance VIN = 0 8.5 11.5 pF
Parameter
Symbol Parameter Description Test Setup Typ Max Unit
CIN Input Capacitance VIN = 0 7.5 9 pF
COUT Output Capacitance VOUT = 0 8 10 pF
CIN2 Control Pin Capacitance VIN = 0 8.5 11 pF
MBM29F200TC-55/70/90/MBM29F200BC-55/70/90
26
■
■■
■TIMING DIAGRAM
• Key to Switching Waveforms
(1) AC Waveforms for Read Operations
WAVEFORM INPUTS OUTPUTS
Must Be
Steady
May
Change
from H to L
May
Change
from L to H
“H” or “L”
Any Change
Permitted
Does Not
Apply
Will Be
Steady
Will Be
Changing
from H to L
Will Be
Changing
from L to H
Changing
State
Unknown
Center Line is
High-
Impedance
“Off” State
WE
OE
CE
tACC
tDF
tOH
tCE
tOE
Outputs
tRC
Address Address Stable
High-Z Output Valid High-Z
tOEH
MBM29F200TC-55/70/90/MBM29F200BC-55/70/90
27
(2) AC Waveforms for Hardware Reset/Read Operations
(3) Alternate WE Controlled Program Operation Timings
RESET
tACC
tOH
Outputs
tRC
Address Address Stable
High-Z Output Valid
tRH
tGHWL tWP
tDS
tWHWH1
tWC tAH
CE
OE
tRC
Address
Data
tAS
tOE
tWPH
tCS
tDH
DQ7
PDA0h DOUT
tCE
WE
555h PA PA
tOH
Data Polling3rd Bus Cycle
tCH
DOUT
Notes : • PA is address of the memory location to be programmed
• PD is data to be programmed at byte address.
• DQ7 is the output of the complement of the data written to the device.
• DOUT is the output of the data written to the device.
• Figure indicates last two bus cycles out of four bus cycle sequence.
• These waveforms are for the × 16 mode.
MBM29F200TC-55/70/90/MBM29F200BC-55/70/90
28
(4) Alternate CE Controlled Program Operation Timings
tCP
tDS
tWHWH1
tWC tAH
WE
OE
Address
Data
tAS
tCPH
tDH
DQ7
A0h DOUT
CE
555h PA PA
Data Polling3rd Bus Cycle
tWS tWH
tGHEL
PD
Notes : • PA is address of the memory location to be programmed.
• PD is data to be programmed at byte address.
• DQ7 is the output of the complement of the data written to the device.
• DOUT is the output of the data written to the device.
• Figure indicates last two bus cycles out of four bus cycle sequence.
• These waveforms are for the × 16 mode.
MBM29F200TC-55/70/90/MBM29F200BC-55/70/90
29
(5) AC Waveforms Chip/Sector Erase Operations
VCC
CE
OE
Address
Data
WE
555h 2AAh 555h
555h 2AAh SA
tDS
tCH
tAS tAH
tCS
tWPH
tDH
tVCS
tWC
tWP
AAh 55h 80h AAh 55h 10h/
tGHWL
30h
10h for Chip Erase
Notes : • SA is the sector address for Sector Erase. Addresses = 555h (Word), AAAh (Byte) for
Chip Erase.
• These waveforms are for the × 16 mode. The addresses differ from × 8 mode.
MBM29F200TC-55/70/90/MBM29F200BC-55/70/90
30
(6) AC Waveforms for Data Polling during Embedded Algorithm Operations
(7) AC Waveforms for Toggle Bit I during Embedded Algorithm Operations
tOEH
tOE
tWHWH1 or 2
CE
OE
WE
tDF
tCH
tCE
High-Z
DQ7 =
Valid Data
DQ6 to DQ0 = Output Flag DQ6 to DQ0
Valid Data
DQ7
*
High-Z
Data
DQ6 to DQ0
DQ7
Data
tEOE
* : DQ7 = Valid Data (The device has completed the Embedded operation).
tOEH
CE
WE
OE
Data DQ6 = Toggle
*
tOES
tOE
(DQ7 to DQ0)DQ6 =
Stop Toggling DQ7 to DQ0
Valid
DQ6 = Toggle
DQ6
* : DQ6 stops toggling (The device has completed the Embedded operation).
MBM29F200TC-55/70/90/MBM29F200BC-55/70/90
31
(8) RY/BY Timing Diagram during Program/Erase Operations
(9) RESET/RY/BY Timing Diagram
(10) Timing Diagram for Word Mode Configuration
Rising edge of the last WE signal
CE
RY/BY
WE
tBUSY
Entire programming
or erase operations
tRP
RESET
tREADY
RY/BY
WE
tRB
CE
BYTE
tELFH tFHQV
A-1
Data Output
(DQ7 to DQ0)
DQ15
DQ15/A-1
DQ14 to DQ0(DQ14 to DQ0)
Data Output
MBM29F200TC-55/70/90/MBM29F200BC-55/70/90
32
(11) Timing Diagram for Byte Mode Configuration
(12) BYTE Timing Diagram for Write Operations
CE
BYTE
DQ15/A-1
DQ14 to DQ0tELFL
DQ15 A-1
tFLQZ
Data Output
(DQ7 to DQ0)
(DQ14 to DQ0)
Data Output
Falling edge of the last write pulse
tHOLD
CE or WE
(tAH)
tSET
(tAS)
Input
Valid
BYTE
MBM29F200TC-55/70/90/MBM29F200BC-55/70/90
33
(13) AC Waveforms Sector Protection Timing Diagram
tVLHT
SAX SAY
A0
A6
A9
VID
5 V
OE
VID
5 V
tVLHT
tOESP tWPP
tCSP
WE
CE
tOE
01h
Data
A1
A16, A15
tVLHT
A14, A13, A12
tVLHT
tVLHT
VCC
SAX = Sector Address for initial sector
SAY = Sector Address for next sector
Note : A-1 is VIL on byte mode.
MBM29F200TC-55/70/90/MBM29F200BC-55/70/90
34
(14) Temporary Sector Unprotection
(15) DQ2 vs. DQ6
VID
5 V
RESET
CE
WE
RY/BY tVCS Program or Erase Command Sequence
5 V
tVLHT
tVIDR
VCC tVCS
DQ2*
DQ6
WE Erase
Erase
Suspend
Enter
Embedded
Erasing
Erase Suspend
Read
Enter Erase
Suspend Program
Erase
Suspend
Program
Erase Suspend
Read
Erase
Resume
Erase Erase
Complete
Toggle
DQ2 and DQ6
with OE or CE
* : DQ2 is read from the erase-suspended sector.
MBM29F200TC-55/70/90/MBM29F200BC-55/70/90
35
■
■■
■FLOW CHART
(1) Embedded Programming Algorithm
No
Yes
Start
Program Command Sequence* (Address/Command):
555h/AAh
2AAh/55h
555h/A0h
Write Program Command
Sequence
(See Below)
Data Polling Device
Increment Address Last Address
?
Programming Completed
Program Address/Program Data
EMBEDDED ALGORITHMS
* : The sequence is applied for × 16 mode.
The addresses differ from × 8 mode.
MBM29F200TC-55/70/90/MBM29F200BC-55/70/90
36
(2) Embedded Erase Algorithm
Start
555h/AAh
2AAh/55h
555h/AAh
555h/80h
555h/10h
2AAh/55h
555h/AAh
2AAh/55h
555h/AAh
555h/80h
2AAh/55h
Additional sector
erase commands
are optional.
Write Erase Command
Sequence
(See Below)
Data Polling or Toggle Bit
Successfully Completed
Erasure Completed
Chip Erase Command Sequence*
(Address/Command):
Individual Sector/Multiple Sector*
Erase Command Sequence
(Address/Command):
Sector Address/30h
Sector Address/30h
Sector Address/30h
EMBEDDED ALGORITHMS
* : The sequence is applied for × 16 mode.
The addresses differ from × 8 mode.
MBM29F200TC-55/70/90/MBM29F200BC-55/70/90
37
(3) Data Polling Algorithm
Fail
DQ7 = Data?
No
No
DQ7 = Data?
DQ5 = 1?
Pass
Yes
Yes
No
Start
Read Byte
(DQ7 to DQ0)
Addr. = VA
Read Byte
(DQ7 to DQ0)
Addr. = VA
Yes
Note : DQ7 is rechecked even if DQ5 = “1” because DQ7 may change simultaneously with DQ5.
VA = Byte address for programming
= Any of the sector addresses
within the sector being erased
during sector erase operation
= Any of the sector addresses
within the sector not being
protected during chip erase
operation
MBM29F200TC-55/70/90/MBM29F200BC-55/70/90
38
(4) Toggle Bit Algorithm
Fail
DQ6 = Toggle
?
Yes
Pass
No
No
DQ6 = Toggle
DQ5 = 1?
Yes
Yes
Start
Read
?
(DQ7 to DQ0)
Addr. = “H” or “L”
No
Read
(DQ7 to DQ0)
Addr. = “H” or “L”
Read
(DQ7 to DQ0)
Addr. = “H” or “L”
*1
*1,*2
Read
(DQ7 to DQ0)
Addr. = “H” or “L”
*1,*2
*1 : Read toggle bit twice to determine whether it is toggling.
*2 : DQ6 is rechecked even if DQ5 = “1” because DQ6 may stop toggling at the same time as
DQ5 changing to “1”.
*1
MBM29F200TC-55/70/90/MBM29F200BC-55/70/90
39
(5) Sector Protection Algorithm
Setup Sector Addr.
Activate WE Pulse
WE = VIH, CE = OE = VIL
(A9 should remain VID)
Yes
Yes
No
No
PLSCNT = 1
Time out 100 µs
Read from Sector
Increment PLSCNT
No
Yes
Protect Another Sector?
Start
Sector Protection
Data = 01h?PLSCNT = 25?
Device Failed
Remove VID from A9
Completed
Remove VID from A9
Write Reset Command
(Addr. = SA, A1 = 1,
OE = VID, A9 = VID,
A6 = CE = VIL, RESET = VIH
(A16, A15, A14, A13, A12)
Write Reset Command
A0 = VIL, A1 = VIH
A0 = V6 = 0)*
* : A-1 is VIL on byte mode.
MBM29F200TC-55/70/90/MBM29F200BC-55/70/90
40
(6) Temporary Sector Unprotection Algorithm
RESET = VID*1
Perform Erase or
Program Operations
RESET = VIH
Start
Temporary Sector
Unprotection Completed*2
*1 : All protected sectors unprotected.
*2 : All previously protected sectors are protected once again.
MBM29F200TC-55/70/90/MBM29F200BC-55/70/90
41
■
■■
■ORDERING INFORMATION
Part No. Package Access Time (ns) Remark
MBM29F200TC-55PF
MBM29F200TC-70PF
MBM29F200TC-90PF
44-pin plastic SOP
(FPT-44P-M16)
55
70
90
Top sector
MBM29F200TC-55PFTN
MBM29F200TC-70PFTN
MBM29F200TC-90PFTN
48-pin plastic TSOP (1)
(FPT-48P-M19)
Normal Bend
55
70
90
MBM29F200TC-55PFTR
MBM29F200TC-70PFTR
MBM29F200TC-90PFTR
48-pin plastic TSOP (1)
(FPT-48P-M20)
Reverse Bend
55
70
90
MBM29F200BC-55PF
MBM29F200BC-70PF
MBM29F200BC-90PF
44-pin plastic SOP
(FPT-44P-M16)
55
70
90
Bottom sector
MBM29F200BC-55PFTN
MBM29F200BC-70PFTN
MBM29F200BC-90PFTN
48-pin plastic TSOP (1)
(FPT-48P-M19)
Normal Bend
55
70
90
MBM29F200BC-55PFTR
MBM29F200BC-70PFTR
MBM29F200BC-90PFTR
48-pin plastic TSOP (1)
(FPT-48P-M20)
Reverse Bend
55
70
90
MBM29F200 T C -55 PFTN
DEVICE NUMBER/DESCRIPTION
MBM29F200
2Mega-bit (256K × 8-Bit or 128K × 16-Bit) CMOS Flash Memory
5.0 V-only Read, Write, and Erase
PACKAGE TYPE
PFTN = 48-Pin Thin Small Outline Package
(TSOP (1)) Normal Bend
PFTR = 48-Pin Thin Small Outline Package
(TSOP (1)) Reverse Bend
PF = 44-Pin Small Outline Package
SPEED OPTION
See Product Selector Guide
C = Device Revision
BOOT CODE SECTOR ARCHITECTURE
T = Top sector
B = Bottom sector
MBM29F200TC-55/70/90/MBM29F200BC-55/70/90
42
■
■■
■PACKAGE DIMENSIONS
48-pin plastic TSOP (1)
(FPT-48P-M19)
Note 1) * : Values do not include resin protrusion.
Resin protrusion and gate protrusion are +0.15 (.006) Max (each side) .
Note 2) Pins width and pins thickness include plating thickness.
Note 3) Pins width do not include tie bar cutting remainder.
Dimensions in mm (inches) .
Note : The values in parentheses are reference values.
–.003
+.001
–0.08
+0.03
.007
0.17
"A" (Stand off height)
0.10(.004)
(Mounting
height)
(.472±.008)
12.00±0.20
LEAD No.
48
2524
1
(.004±.002)
0.10(.004) M
1.10 +0.10
–0.05
+.004
–.002.043
0.10±0.05
(.009±.002)
0.22±0.05
(.787±.008)
20.00±0.20
(.724±.008)
18.40±0.20
INDEX
2003 FUJITSU LIMITED F48029S-c-6-7
C
0~8˚
0.25(.010)
0.50(.020)
0.60±0.15
(.024±.006)
Details of "A" part
*
*
MBM29F200TC-55/70/90/MBM29F200BC-55/70/90
43
(Continued)
48-pin plastic TSOP (1)
(FPT-48P-M20)
Note 1) * : Values do not include resin protrusion.
Resin protrusion and gate protrusion are +0.15 (.006) Max (each side) .
Note 2) Pins width and pins thickness include plating thickness.
Note 3) Pins width do not include tie bar cutting remainder.
Dimensions in mm (inches) .
Note : The values in parentheses are reference values.
–.003
+.001
.007
–0.08
+0.03
0.17
"A"
(Stand off height)
(.004±.002)
0.10±0.05
0.10(.004)
(Mounting height)
12.00±0.20(.472±.008)
LEAD No.
48
2524
1
0.10(.004) M
1.10 +0.10
–0.05
+.004
–.002
.043
(.009±.002)
0.22±0.05
(.787±.008)
20.00±0.20
(.724±.008)
18.40±0.20
INDEX
2003 FUJITSU LIMITED F48030S-c-6-7
C
0~8˚
0.25(.010)
0.60±0.15
(.024±.006)
Details of "A" part
*
*
0.50(.020)
MBM29F200TC-55/70/90/MBM29F200BC-55/70/90
44
(Continued)
44-pin plastic SOP
(FPT-44P-M16)
Note 1) *1 : These dimensions include resin protrusion.
Note 2) *2 : These dimensions do not include resin protrusion.
Note 3) Pins width and pins thickness include plating thickness.
Note 4) Pins width do not include tie bar cutting remainder.
Dimensions in mm (inches) .
Note : The values in parentheses are reference values.
C
2002 FUJITSU LIMITED F44023S-c-6-6
M
0.13(.005)
1.27(.050)
13.00±0.10
16.00±0.20
(.512±.004)
(.630±.008)
1
1.120 –.008
+.010
–0.20
+0.25
28.45
0.10(.004)
22
2344
–0.07
+0.08
0.42
.017 +.0031
–.0028
INDEX
0~8˚
0.25(.010)
(Mounting height)
Details of "A" part
2.35±0.15
(.093±.006)
–0.15
+0.10
0.20
.008 +.004
–.006
(Stand off)
0.80±0.20
(.031±.008)
0.88±0.15
(.035±.006)
–0.04
+0.03
0.17
.007 +.001
–.002
"A"
*1
*2
MBM29F200TC-55/70/90/MBM29F200BC-55/70/90
FUJITSU LIMITED
All Rights Reserved.
The contents of this document are subject to change without notice.
Customers are advised to consult with FUJITSU sales
representatives before ordering.
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circuit examples, in this document are presented solely for the
purpose of reference to show examples of operations and uses of
Fujitsu semiconductor device; Fujitsu does not warrant proper
operation of the device with respect to use based on such
information. When you develop equipment incorporating the
device based on such information, you must assume any
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assumes no liability for any damages whatsoever arising out of
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function and schematic diagrams, shall not be construed as license
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Fujitsu assumes no liability for any infringement of the intellectual
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The products described in this document are designed, developed
and manufactured as contemplated for general use, including
without limitation, ordinary industrial use, general office use,
personal use, and household use, but are not designed, developed
and manufactured as contemplated (1) for use accompanying fatal
risks or dangers that, unless extremely high safety is secured, could
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reaction control in nuclear facility, aircraft flight control, air traffic
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Please note that Fujitsu will not be liable against you and/or any
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Any semiconductor devices have an inherent chance of failure. You
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over-current levels and other abnormal operating conditions.
If any products described in this document represent goods or
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F0404
FUJITSU LIMITED Printed in Japan
