DM74ALS125N_NL - Fairchild Semiconductor

November 1989

Revised February 2000

DM74ALS125 Quad 3-STATE Buffer

DM74ALS125

Quad 3-STATE Buffer

General Descript ion

This device contains four independent gates each of which

performs a non-inverti ng buffer fun ction. The o utputs have

the 3-STATE feature. The 3-STATE circuitry c ontai ns a fea-

ture that maintains the buffer outputs in 3-STATE (high

impedance state) during power supply ramp-up or ramp-

down. This eliminates bus glitching problems that arise

during power-up and power-down. To minimize the possi-

bility that two out puts will att empt t o ta ke a co mm on bus to

opposite logic levels, the disable time is shorter than the

enable time of the outputs.

Features

■Advanced low power oxide-isolated ion-implanted

Schottky TTL process

■Functional and pin compatible with the 74LS counterpart

■Switching response specified into 500Ω and 50 pF load

■Switching response specifications guaranteed over full

temperature and VCC supply range

■PNP input design reduces input loading

■Low level drive current: 74ALS = 24 mA

Ordering Code:

Devices also available in Ta pe and Reel. Spe ci fy by append ing the suffix let t er “X” to the o rdering c ode.

Connection Diagram

Functional Table

Y = A

H = HIGH Logic Level

L = LOW Logic Le v el

X = Either LO W or HIGH Logic Lev el

Hi-Z = 3-STATE (Outpu ts are disabled)

Logic Diagram

Order Number Package Number Package Description

DM74ALS125M M14A 14-Lead Small Outline Integrated Circuit (SOIC), JEDEC MS-012, 0.150 Narrow

DM74ALS125N N14A 14-Lead Plastic Dual-In-Line Package (PDIP), JEDEC MS-001, 0.300 Wide

Input Output

AC Y

LL L

HL H

X H Hi-Z

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DM74ALS125

Absolute Maximum Ratings(Note 1)

Note 1: The Absolute Maximum Ratings are those values beyond which

the saf ety of the device cannot be guarante ed. The device s hould not be

operated at these limits. The parametric values defined in the Electrical

Characteristics tables are not gua rant eed at the absolute maximum rati n gs.

The “Re comme nded Operat ing Co ndition s” table will define the cond itions

for actu al device operation.

Recommended Operating Conditions

Electrical Characteristics

over recommended operating free air temperature (unless otherwise specified)

Supply Voltage, VCC 7V

Input Voltage 7V

Voltage Applied to Disabled Output 5.5V

Operating Free Air Temperature Range 0 to +70°C

Storage Temperature Range −65°C to +150°C

Typical θJA

N Package 78.0°C/W

M Package 111.0°C/W

Symbol Parameter Min Typ Max Units

VCC Supply Voltage 4.5 5 5.5 V

VIH HIGH Level Input Voltage 2 V

VIL LOW Level Input Voltage 0.8 V

IOH HIGH Level Output Current −15 mA

IOL LOW Level Output Current 24 mA

TAOperating Free-Air Temperature 0 70 °C

Symbol Parameter Conditions Min Typ Max Units

VIK Input Clamp Voltage VCC = 4.5V, II = −18 mA −1.5 V

VOH HIGH Level VCC = 4.5V to 5.5V IOH = −0.4 mA VCC − 2V

Output Voltage VCC = 4.5V IOH = −3 mA 2.4 V

IOH = Max 2 V

VOL LOW Level VCC = 4.5V IOL = 12 mA 0.25 0.4 V

Output Voltage IOL = 24 mA 0.35 0.5 V

IIInput Current at Max VCC = 5.5V, VI = 7V 0.1 mA

Input Voltage

IIH HIGH Level VCC = 5.5V, VI = 2.7V 20 µA

Input Current

IIL LOW Level VCC = 5.5V, VIL = 0.4V −0.1 mA

Input Current

IOOutput Drive VCC = 5.5V, VO = 2.25V −30 −112 mA

Current

IOZH HIGH Level 3-STATE VCC = 5.5V, VO = 2.7V 20 µA

Output Current

IOZL LOW Level 3-STAT E VCC = 5.5V, VO = 0.4V −20 µA

Output Current

ICC Supply Curre nt VCC = 5.5V Outputs HIGH 7 10 mA

Outputs LOW 10 14 mA

3-STATE 13.5 18 mA

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DM74ALS125

Switching Characteristics

Symbol Parameter From To Conditions Min Max Units

(Input) (Output)

tPLH Propagation Delay Time AY VCC = 4.5V to 5.5V, 310ns

LOW-to-HIGH Level Output CL = 50 pF,

tPHL Propagation Delay Time AY R1 = 500Ω,210ns

HIGH-to-LOW Level Output R2 = 500Ω,

tPZH Output Enable Time CY TA = Min to Max 213ns

to HIGH Level Output

tPZL Output Enable Time CY 212ns

to LOW Level Output

tPHZ Output Disable Time CY 18ns

from HIGH Level Output

tPLZ Output Disable Time CY 213ns

from LOW Level Output

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DM74ALS125

Physical Dimensions inches (millimeters) unless otherwise noted

14-Lead Small Outline Integrated Circuit (SOIC), JEDEC MS-012, 0.150 Narrow

Package Number M14A

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DM74ALS125 Quad 3-STATE Buffer

Physical Dimensions inches (millimeters) unless otherwise noted (Continued)

14-Lead Plastic Dual-In-Line Package (PDIP), JEDEC MS-001, 0.300 Wide

Packag e Num be r N14A

Fairchild does not assume any responsibility for use of any circu itry described, no circuit patent licenses are implied and

Fairchild reserves the right at any time without notice to change said circuitry and specifications.

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