PD - 96339A IRLHS6342PbF VDS 30 V VGS 12 V RDS(on) max 15.5 m (@VGS = 4.5V) Qg (typical) ID 11 (@TC (Bottom) = 25C) 12 nC i A HEXFET(R) Power MOSFET TOP VIEW 6 D D 1 D 2 D S G 3 D D D 5 D 4 S D D G S S 2mm x 2mm PQFN Applications * Charge and discharge switch for battery application * System/Load Switch Features and Benefits Features Low RDSon ( 15.5m) Low Thermal Resistance to PCB ( 13C/W) Low Profile ( 1.0 mm) Compatible with Existing Surface Mount Techniques RoHS Compliant Containing no Lead, no Bromide and no Halogen MSL1, Consumer Qualification Orderable part number Package Type IRLHS6342TRPBF IRLHS6342TR2PBF PQFN 2mm x 2mm PQFN 2mm x 2mm Resulting Benefits Lower Conduction Losses Enable better thermal dissipation results in Increased Power Density Easier Manufacturing Environmentally Friendlier Increased Reliability Standard Pack Form Quantity Tape and Reel 4000 400 Tape and Reel Note Absolute Maximum Ratings Parameter Max. VDS Drain-to-Source Voltage 30 VGS 12 ID @ TA = 25C Gate-to-Source Voltage Continuous Drain Current, VGS @ 10V ID @ TA = 70C Continuous Drain Current, VGS @ 10V ID @ TC(Bottom) = 25C Continuous Drain Current, VGS @ 10V 6.9 19 ID @ TC(Bottom)= 70C Continuous Drain Current, VGS @ 10V 15 ID @ TC(Bottom) = 25C IDM Continuous Drain Current, VGS @ 10V (Wirebond Limited) Pulsed Drain Current PD @TA = 25C Power Dissipation c PD @TA = 70C g Power Dissipation g TJ Linear Derating Factor Operating Junction and TSTG Storage Temperature Range V 8.7 hi hi 12i A 76 2.1 g Units 1.3 0.02 -55 to + 150 W W/C C Notes through are on page 2 www.irf.com 1 02/25/11 IRLHS6342PbF Static @ TJ = 25C (unless otherwise specified) Min. Typ. Drain-to-Source Breakdown Voltage Parameter 30 --- --- Breakdown Voltage Temp. Coefficient Static Drain-to-Source On-Resistance --- --- 22 12.0 --- 15.5 VGS(th) VGS(th) Gate Threshold Voltage Gate Threshold Voltage Coefficient --- 0.5 --- 15.0 --- -4.2 19.5 1.1 --- IDSS Drain-to-Source Leakage Current --- --- --- --- 1.0 150 A VDS = 24V, VGS = 0V VDS = 24V, VGS = 0V, TJ = 125C IGSS Gate-to-Source Forward Leakage Gate-to-Source Reverse Leakage --- --- --- --- 100 -100 nA VGS = 12V VGS = -12V gfs Qg Forward Transconductance Total Gate Charge Gate-to-Source Charge 39 --- --- --- 11 0.5 --- --- --- Gate-to-Drain Charge --- 4.6 --- Gate Resistance Turn-On Delay Time Rise Time --- --- --- 2.1 4.9 13 --- --- --- Turn-Off Delay Time Fall Time Input Capacitance --- --- --- 19 13 1019 --- --- --- Output Capacitance Reverse Transfer Capacitance --- --- 97 70 --- --- BVDSS VDSS/TJ RDS(on) Qgs Qgd RG td(on) tr td(off) tf Ciss Coss Crss Max. Units V Conditions VGS = 0V, ID = 250A mV/C Reference to 25C, ID = 1mA VGS = 4.5V, ID = 8.5A m VGS = 2.5V, ID = 8.5A V VDS = VGS, ID = 10A mV/C e e S VDS = 10V, ID = 8.5A VDS = 15V nC VGS = 4.5V ID = 8.5A (See Fig. 6 & 17) ns pF VDD = 15V, VGS = 4.5V ID = 8.5A RG=1.8 See Fig.18 VGS = 0V VDS = 25V = 1.0MHz Avalanche Characteristics EAS IAR Parameter Single Pulse Avalanche Energy Avalanche Current c d Typ. --- Max. 14 Units mJ --- 8.5 A Diode Characteristics Parameter Min. IS Continuous Source Current ISM (Body Diode) Pulsed Source Current VSD trr Qrr --- c (Body Diode) Diode Forward Voltage Reverse Recovery Time Reverse Recovery Charge Forward Turn-On Time ton Typ. --- Max. Units i 12 --- --- 76 --- --- --- 11 1.2 17 Conditions MOSFET symbol D A showing the integral reverse V ns p-n junction diode. TJ = 25C, IS = 8.5A, VGS = 0V TJ = 25C, IF = 8.5A, VDD = 15V di/dt = 300 A/s --- 13 20 nC Time is dominated by parasitic Inductance G e S e Thermal Resistance RJC (Bottom) RJC (Top) RJA RJA Parameter Junction-to-Case Junction-to-Case Junction-to-Ambient Junction-to-Ambient (<10s) g g f f Typ. --- --- --- --- Max. 13 90 60 42 Units C/W Notes: Repetitive rating; pulse width limited by max. junction temperature. Starting TJ = 25C, L = 0.39mH, RG = 50, IAS = 8.5A. Pulse width 400s; duty cycle 2%. R is measured at TJ of approximately 90C. When mounted on 1 inch square 2 oz copper pad on 1.5x1.5 in. board of FR-4 material. Calculated continuous current based on maximum allowable junction temperature. Package is limited to 12A by die-source to lead-frame bonding technology 2 www.irf.com IRLHS6342PbF 100 100 10 BOTTOM TOP ID, Drain-to-Source Current (A) ID, Drain-to-Source Current (A) TOP VGS 10V 4.5V 3.0V 2.5V 2.0V 1.8V 1.5V 1.4V 1 1.4V BOTTOM 10 1.4V 60s PULSE WIDTH 60s PULSE WIDTH Tj = 150C Tj = 25C 1 0.1 0.1 1 10 0.1 100 10 100 Fig 2. Typical Output Characteristics Fig 1. Typical Output Characteristics 100 2.0 RDS(on) , Drain-to-Source On Resistance (Normalized) ID, Drain-to-Source Current (A) 1 V DS, Drain-to-Source Voltage (V) V DS, Drain-to-Source Voltage (V) TJ = 150C TJ = 25C 10 VDS = 15V 60s PULSE WIDTH 1.0 ID = 8.5A VGS = 4.5V 1.8 1.6 1.4 1.2 1.0 0.8 0.6 1.0 1.5 2.0 2.5 3.0 3.5 -60 -40 -20 0 Fig 4. Normalized On-Resistance vs. Temperature Fig 3. Typical Transfer Characteristics 10000 14.0 VGS = 0V, f = 1 MHZ C iss = C gs + C gd, C ds SHORTED C rss = C gd VGS, Gate-to-Source Voltage (V) ID= 8.5A C oss = C ds + C gd Ciss 1000 Coss Crss 100 20 40 60 80 100 120 140 160 T J , Junction Temperature (C) VGS, Gate-to-Source Voltage (V) C, Capacitance (pF) VGS 10V 4.5V 3.0V 2.5V 2.0V 1.8V 1.5V 1.4V 10 12.0 VDS= 24V VDS= 15V VDS= 6.0V 10.0 8.0 6.0 4.0 2.0 0.0 1 10 100 VDS, Drain-to-Source Voltage (V) Fig 5. Typical Capacitance vs.Drain-to-Source Voltage www.irf.com 0 5 10 15 20 25 30 QG, Total Gate Charge (nC) Fig 6. Typical Gate Charge vs.Gate-to-Source Voltage 3 IRLHS6342PbF 1000 ID, Drain-to-Source Current (A) ISD, Reverse Drain Current (A) 100 T J = 150C T J = 25C 10 OPERATION IN THIS AREA LIMITED BY R DS(on) 100 100sec 1msec 10 Limited by Wire Bond 1 0.1 0.4 0.5 0.6 0.7 0.8 0.9 1.0 1.1 0 1 VSD, Source-to-Drain Voltage (V) 10 100 VDS, Drain-to-Source Voltage (V) Fig 7. Typical Source-Drain Diode Forward Voltage Fig 8. Maximum Safe Operating Area 20 VGS(th) , Gate threshold Voltage (V) 1.6 18 Limited By Package 16 ID, Drain Current (A) DC Tc = 25C Tj = 150C Single Pulse VGS = 0V 1.0 10msec 14 12 10 8 6 4 2 0 1.4 1.2 1.0 0.8 ID = 10A ID = 25A 0.6 ID = 250A 0.4 ID = 1.0mA 0.2 ID = 1.0A 0.0 25 50 75 100 125 150 -75 -50 -25 T C , Case Temperature (C) 0 25 50 75 100 125 150 T J , Temperature ( C ) Fig 9. Maximum Drain Current vs. Case (Bottom) Temperature Fig 10. Threshold Voltage vs. Temperature Thermal Response ( Z thJC ) C/W 100 10 D = 0.50 0.20 0.10 0.05 1 0.02 0.01 0.1 Notes: 1. Duty Factor D = t1/t2 2. Peak Tj = P dm x Zthjc + Tc SINGLE PULSE ( THERMAL RESPONSE ) 0.01 1E-006 1E-005 0.0001 0.001 0.01 0.1 1 t1 , Rectangular Pulse Duration (sec) Fig 11. Maximum Effective Transient Thermal Impedance, Junction-to-Case (Bottom) 4 www.irf.com 30 RDS(on), Drain-to -Source On Resistance ( m) RDS(on) , Drain-to -Source On Resistance (m) IRLHS6342PbF ID = 8.5A 25 20 T J = 125C 15 10 T J = 25C 5 0 2 4 6 8 10 12 28 26 24 22 20 Vgs = 2.5V 18 16 14 Vgs = 4.5V 12 10 14 5 15 25 35 45 55 65 75 ID, Drain Current (A) VGS, Gate -to -Source Voltage (V) Fig 13. Typical On-Resistance vs. Drain Current Fig 12. On-Resistance vs. Gate Voltage 600 60 ID TOP 1.9A 3.4A BOTTOM 8.5A 50 500 Single Pulse Power (W) EAS , Single Pulse Avalanche Energy (mJ) 30 40 30 20 400 300 200 100 10 0 1E-5 0 25 50 75 100 125 150 1E-4 Starting T J , Junction Temperature (C) Driver Gate Drive - - P.W. + * dv/dt controlled by RG * Driver same type as D.U.T. * I SD controlled by Duty Factor "D" * D.U.T. - Device Under Test P.W. Period D.U.T. ISD Waveform Reverse Recovery Current V DD D= Period * RG 1E+0 VGS=10V Circuit Layout Considerations * Low Stray Inductance * Ground Plane * Low Leakage Inductance Current Transformer - 1E-1 Fig 15. Typical Power vs. Time + + 1E-2 Time (sec) Fig 14. Maximum Avalanche Energy vs. Drain Current D.U.T 1E-3 + - Body Diode Forward Current di/dt D.U.T. VDS Waveform Diode Recovery dv/dt Re-Applied Voltage Body Diode VDD Forward Drop Inductor Curent Ripple 5% ISD * VGS = 5V for Logic Level Devices Fig 16. Peak Diode Recovery dv/dt Test Circuit for N-Channel HEXFET(R) Power MOSFETs www.irf.com 5 IRLHS6342PbF Id Vds Vgs L VCC DUT 0 1K Vgs(th) S Qgs1 Qgs2 Qgd Qgodr Fig 17b. Gate Charge Waveform Fig 17a. Gate Charge Test Circuit V(BR)DSS 15V DRIVER L VDS D.U.T RG + V - DD IAS 20V tp A I AS 0.01 tp Fig 18a. Unclamped Inductive Test Circuit V DS V GS RG RD VDS 90% D.U.T. + -V DD V10V GS Pulse Width 1 s Duty Factor 0.1 Fig 19a. Switching Time Test Circuit 6 Fig 18b. Unclamped Inductive Waveforms 10% VGS td(on) tr td(off) tf Fig 19b. Switching Time Waveforms www.irf.com IRLHS6342PbF PQFN 2x2 Outline Package Details For footprint and stencil design recommendations, please refer to application note AN-1154 at http://www.irf.com/technical-info/appnotes/an-1154.pdf PQFN 2x2 Outline Part Marking Note: For the most current drawing please refer to IR website at: http://www.irf.com/package/ www.irf.com 7 IRLHS6342PbF PQFN 2x2 Outline Tape and Reel 8 www.irf.com IRLHS6342PbF Qualification information Qualification level Moisture Sensitivity Level RoHS compliant Cons umer (per JE DE C JE S D47F PQFN 2mm x 2mm guidelines ) MS L1 (per JE DE C J-S T D-020D Yes ) Qualification standards can be found at International Rectifier's web site http://www.irf.com/product-info/reliability Higher qualification ratings may be available should the user have such requirements. Please contact your International Rectifier sales representative for further information: http://www.irf.com/whoto-call/salesrep/ Applicable version of JEDEC standard at the time of product release. Data and specifications subject to change without notice. IR WORLD HEADQUARTERS: 233 Kansas St., El Segundo, California 90245, USA Tel: (310) 252-7105 TAC Fax: (310) 252-7903 Visit us at www.irf.com for sales contact information.02/2011 www.irf.com 9