LF155/LF156/LF157 Series Monolithic JFET Input Operational Amplifiers General Description These are the first monolithic JFET input operational amplifiers to incorporate well matched, high voltage JFETs on the same chip with standard bipolar transistors (BI-FETTM Technology). These amplifiers feature low input bias and offset currents/low offset voltage and offset voltage drift, coupled with offset adjust which does not degrade drift or commonmode rejection. The devices are also designed for high slew rate, wide bandwidth, extremely fast settling time, low voltage and current noise and a low 1/f noise corner. Advantages Y Y Y Y Y Y Replace expensive hybrid and module FET op amps Rugged JFETs allow blow-out free handling compared with MOSFET input devices Excellent for low noise applications using either high or low source impedancevery low 1/f corner Offset adjust does not degrade drift or common-mode rejection as in most monolithic amplifiers New output stage allows use of large capacitive loads (5,000 pF) without stability problems Internal compensation and large differential input voltage capability Y Y Common Features (LF155A, LF156A, LF157A) Y Low input bias current Y Low Input Offset Current Y High input impedance Y Low input offset voltage Y Low input offset voltage temp. drift Y Low input noise current Y High common-mode rejection ratio Y Large dc voltage gain Y Y Y Y Precision high speed integrators Fast D/A and A/D converters High impedance buffers Wideband, low noise, low drift amplifiers Logarithmic amplifiers 30 pA 3 pA 1012X 1 mV 3 mV/ C 0.01 pA/0Hz 100 dB 106 dB Uncommon Features 4 1.5 LF157A (AV e 5) 1.5 5 12 50 V/ms 2.5 5 20 MHz 20 12 12 nV/0Hz LF155A LF156A Y Extremely fast settling time to 0.01% Y Fast slew rate Y Wide gain bandwidth Y Low input noise voltage Applications Y Photocell amplifiers Sample and Hold circuits Units ms Simplified Schematic *3 pF in LF157 series. TL/H/5646 - 1 BI-FETTM , BI-FET IITM are trademarks of National Semiconductor Corporation. C1995 National Semiconductor Corporation TL/H/5646 RRD-B30M115/Printed in U. S. A. LF155/LF156/LF157 Series Monolithic JFET Input Operational Amplifiers December 1994 Absolute Maximum Ratings If Military/Aerospace specified devices are required, contact the National Semiconductor Sales Office/Distributors for availability and specifications. (Note 8) LF355B/6B/7B LF355/6/7 LF155A/6A/7A LF155/6/7 LF255/6/7 LF355A/6A/7A g 22V g 22V g 22V g 18V Supply Voltage g 40V g 40V g 40V g 30V Differential Input Voltage g 20V g 20V g 20V g 16V Input Voltage Range (Note 2) Output Short Circuit Duration Continuous Continuous Continuous Continuous TjMAX H-Package 150 C 150 C 115 C 115 C N-Package 100 C 100 C M-Package 100 C 100 C Power Dissipation at TA e 25 C (Notes 1 and 9) H-Package (Still Air) 560 mW 560 mW 400 mW 400 mW H-Package (400 LF/Min Air Flow) 1200 mW 1200 mW 1000 mW 1000 mW N-Package 670 mW 670 mW M-Package 380 mW 380 mW Thermal Resistance (Typical) iJA H-Package (Still Air) 160 C/W 160 C/W 160 C/W 160 C/W H-Package (400 LF/Min Air Flow) 65 C/W 65 C/W 65 C/W 65 C/W N-Package 130 C/W 130 C/W M-Package 195 C/W 195 C/W (Typical) iJC H-Package 23 C/W 23 C/W 23 C/W 23 C/W b 65 C to a 150 C b 65 C to a 150 C b 65 C to a 150 C b 65 C to a 150 C Storage Temperature Range Soldering Information (Lead Temp.) Metal Can Package Soldering (10 sec.) 300 C 300 C 300 C 300 C Dual-In-Line Package Soldering (10 sec.) 260 C 260 C 260 C Small Outline Package Vapor Phase (60 sec.) 215 C 215 C Infrared (15 sec.) 220 C 220 C See AN-450 ``Surface Mounting Methods and Their Effect on Product Reliability'' for other methods of soldering surface mount devices. ESD tolerance (100 pF discharged through 1.5 kX) 1000V 1000V 1000V 1000V DC Electrical Characteristics (Note 3) TA e Tj e 25 C Symbol Parameter LF155A/6A/7A Conditions Min LF355A/6A/7A Typ Max 1 3 Min Units Typ Max 2 2.5 1 2 2.3 mV mV 5 3 5 mV/ C VOS Input Offset Voltage RS e 50X, TA e 25 C Over Temperature DVOS/DT Average TC of Input Offset Voltage RS e 50X DTC/DVOS Change in Average TC with VOS Adjust RS e 50X, (Note 4) IOS Input Offset Current Tj e 25 C, (Notes 3, 5) TjsTHIGH 3 10 10 3 10 1 pA nA IB Input Bias Current Tj e 25 C, (Notes 3, 5) TjsTHIGH 30 50 25 30 50 5 pA nA RIN Input Resistance Tj e 25 C AVOL Large Signal Voltage Gain VS e g 15V, TA e 25 C VO e g 10V, RL e 2k Over Temperature 50 Output Voltage Swing VS e g 15V, RL e 10k VS e g 15V, RL e 2k g 12 g 10 VO 0.5 1012 2 200 25 50 1012 X 200 V/mV 25 g 13 g 12 mV/ C per mV 0.5 g 12 g 10 V/mV g 13 g 12 V V DC Electrical Characteristics (Note 3) TA e Tj e 25 C (Continued) Symbol Parameter LF155A/6A/7A Conditions VCM Input Common-Mode Voltage Range CMRR Common-Mode Rejection Ratio PSRR Supply Voltage Rejection Ratio VS e g 15V Min Typ g 11 (Note 6) LF355A/6A/7A Max Max Units Min Typ a 15.1 b 12 g 11 a 15.1 b 12 V V 85 100 85 100 dB 85 100 85 100 dB AC Electrical Characteristics TA e Tj e 25 C, VS e g 15V Symbol SR Parameter Slew Rate Conditions LF155A/6A; AV e 1, LF157A; AV e 5 LF155A/355A Min Typ 3 5 LF156A/356A Max Min Typ 10 12 LF157A/357A Max Max Units Min Typ 40 50 V/ms V/ms 15 20 MHz GBW Gain Bandwidth Product ts Settling Time to 0.01% (Note 7) 4 1.5 1.5 ms en Equivalent Input Noise Voltage RS e 100X f e 100 Hz f e 1000 Hz 25 20 15 12 15 12 nV/0Hz nV/0Hz in Equivalent Input Noise Current f e 100 Hz f e 1000 Hz 0.01 0.01 0.01 0.01 0.01 0.01 pA/0Hz pA/0Hz CIN Input Capacitance 3 3 3 pF 2.5 4 4.5 DC Electrical Characteristics (Note 3) Symbol Parameter Min VOS Input Offset Voltage RS e 50X, TA e 25 C Over Temperature DVOS/DT Average TC of Input Offset Voltage RS e 50X LF255/6/7 LF355B/6B/7B LF155/6/7 Conditions Typ 3 DTC/DVOS Change in Average TC RS e 50X, (Note 4) with VOS Adjust Max Min 5 7 Typ Max 3 5 6.5 LF355/6/7 Min Units Typ Max 3 10 13 mV mV 5 5 5 mV/ C 0.5 0.5 0.5 mV/ C per mV IOS Input Offset Current Tj e 25 C, (Notes 3, 5) TjsTHIGH 3 20 20 3 20 1 3 50 2 pA nA IB Input Bias Current Tj e 25 C, (Notes 3, 5) TjsTHIGH 30 100 50 30 100 5 30 200 8 pA nA RIN Input Resistance Tj e 25 C AVOL Large Signal Voltage Gain VS e g 15V, TA e 25 C VO e g 10V, RL e 2k Over Temperature 25 VO Output Voltage Swing VS e g 15V, RL e 10k VS e g 15V, RL e 2k VCM Input Common-Mode Voltage Range VS e g 15V 1012 50 1012 200 50 g 12 g 10 g 13 g 12 g 12 g 10 g 11 a 15.1 b 12 g 11 1012 X 200 V/mV 200 25 g 13 g 12 g 12 g 10 g 13 g 12 V V a 10 a 15.1 b 12 V V 25 15 g 15.1 b 12 V/mV CMRR Common-Mode Rejection Ratio 85 100 85 100 80 100 dB PSRR Supply Voltage Rejec- (Note 6) tion Ratio 85 100 85 100 80 100 dB 3 DC Electrical Characteristics TA e Tj e 25 C, VS e g 15V Parameter LF155A/155, LF255, LF355A/355B LF355 LF156A/156, LF256/356B LF356A/356 LF157A/157 LF257/357B LF357A/357 Typ Max Typ Max Typ Max Typ Max Typ Max Typ Max 2 4 2 4 5 7 5 10 5 7 5 10 Supply Current Units mA AC Electrical Characteristics TA e Tj e 25 C, VS e g 15V Symbol SR Parameter Slew Rate Conditions LF155/6: AV e 1, LF157: AV e 5 GBW Gain Bandwidth Product ts en LF155/255/ LF156/256, LF156/256/ LF157/257, LF157/257/ 355/355B LF356B 356/356B LF357B 357/357B Typ Min Typ 5 7.5 12 Units Min Typ 30 50 V/ms V/ms 2.5 5 20 MHz Settling Time to 0.01% (Note 7) 4 1.5 1.5 ms Equivalent Input Noise RS e 100X Voltage f e 100 Hz f e 1000 Hz 25 20 15 12 15 12 nV/0Hz nV/0Hz 0.01 0.01 0.01 0.01 0.01 0.01 pA/0Hz pA/0Hz 3 3 3 pF in Equivalent Input Current Noise CIN Input Capacitance f e 100 Hz f e 1000 Hz Notes for Electrical Characteristics Note 1: The maximum power dissipation for these devices must be derated at elevated temperatures and is dictated by TjMAX, ijA, and the ambient temperature, TA. The maximum available power dissipation at any temperature is Pd e (TjMAX b TA)/ijA or the 25 C PdMAX, whichever is less. Note 2: Unless otherwise specified the absolute maximum negative input voltage is equal to the negative power supply voltage. Note 3: Unless otherwise stated, these test conditions apply: LF155A/6A/7A LF155//6/7 Supply Voltage, VS TA THIGH LF255//6/7 g 15V s VS s g 20V g 15V s VS s g 20V b 55 C s TA s a 125 C a 125 C b 25 C s TA s a 85 C a 85 C LF355A/6A/7A LF355B/6B/7B LF355//6/7 g 15V s VS s g 18V 0 CsTAs a 70 C a 70 C g 15V s VS g 20V 0 CsTAs a 70 C a 70 C VS e g 15V 0 CsTAs a 70 C a 70 C and VOS, IB and IOS are measured at VCM e 0. Note 4: The Temperature Coefficient of the adjusted input offset voltage changes only a small amount (0.5mV/ C typically) for each mV of adjustment from its original unadjusted value. Common-mode rejection and open loop voltage gain are also unaffected by offset adjustment. Note 5: The input bias currents are junction leakage currents which approximately double for every 10 C increase in the junction temperature, TJ. Due to limited production test time, the input bias currents measured are correlated to junction temperature. In normal operation the junction temperature rises above the ambient temperature as a result of internal power dissipation, Pd. Tj e TA a ijA Pd where ijA is the thermal resistance from junction to ambient. Use of a heat sink is recommended if input bias current is to be kept to a minimum. Note 6: Supply Voltage Rejection is measured for both supply magnitudes increasing or decreasing simultaneously, in accordance with common practice. Note 7: Settling time is defined here, for a unity gain inverter connection using 2 kX resistors for the LF155/6. It is the time required for the error voltage (the voltage at the inverting input pin on the amplifier) to settle to within 0.01% of its final value from the time a 10V step input is applied to the inverter. For the LF157, AV eb 5, the feedback resistor from output to input is 2 kX and the output step is 10V (See Settling Time Test Circuit). Note 8: Refer to RETS155AX for LF155A, RETS155X for LF155, RETS156AX for LF156A, RETS156X for LF156, RETS157A for LF157A and RETS157X for LF157 military specifications. Note 9: Max. Power Dissipation is defined by the package characteristics. Operating the part near the Max. Power Dissipation may cause the part to operate outside guaranteed limits. 4 Typical DC Performance Characteristics Curves are for LF155, LF156 and LF157 unless otherwise specified. Input Bias Current Input Bias Current Input Bias Current Voltage Swing Supply Current Supply Current Negative Current Limit Positive Current Limit Positive Common-Mode Input Voltage Limit TL/H/5646 - 2 Negative Common-Mode Input Voltage Limit Open Loop Voltage Gain Output Voltage Swing TL/H/5646 - 3 5 Typical AC Performance Characteristics Gain Bandwidth Gain Bandwidth Normalized Slew Rate TL/H/5646 - 4 Output Impedance Output Impedance Output Impedance TL/H/5646 - 12 LF155 Small Signal Pulse Response, AV e a 1 LF156 Small Signal Pulse Response, AV e a 1 TL/H/5646 - 6 TL/H/5646-5 LF155 Large Signal Pulse Response, AV e a 1 LF156 Large Signal Pulse Response, AV e a 1 TL/H/5646-8 TL/H/5646 - 9 6 Small Signal Pulse Response, AV e a 5 TL/H/5646 - 7 LF157 Large Signal Pulse Response, AV e a 5 TL/H/5646 - 10 Typical AC Performance Characteristics (Continued) Inverter Settling Time Inverter Settling Time Open Loop Frequency Response Bode Plot Bode Plot Bode Plot Common-Mode Rejection Ratio Power Supply Rejection Ratio Power Supply Rejection Ratio Undistorted Output Voltage Swing Equivalent Input Noise Voltage Equivalent Input Noise Voltage (Expanded Scale) TL/H/5646 - 11 7 Detailed Schematic *C e 3 pF in LF157 series. TL/H/5646 - 13 Connection Diagrams (Top Views) Dual-In-Line Package (M and N) Metal Can Package (H) TL/H/5646-14 Order Number LF156AH, LF155H, LF156H, LF255H, LF256H, LF257H, LF355AH, LF356AH, LF357AH, LF356BH, LF355H, LF356H, LF357H, LM155AH/883, LM155H/883, LM156AH/883, LM156H/883, LM157AH/883 or LM157H/883* See NS Package Number H08C TL/H/5646 - 29 Order Number LF355M, LF356M, LF357M, LF355BM, LF356BM, LF355BN, LF356BN, LF357BN, LF355N, LF356N or LF357N See NS Package Number M08A or N08E *Available per JM38510/11401 or JM38510/11402 8 Application Hints Precautions should be taken to ensure that the power supply for the integrated circuit never becomes reversed in polarity or that the unit is not inadvertently installed backwards in a socket as an unlimited current surge through the resulting forward diode within the IC could cause fusing of the internal conductors and result in a destroyed unit. All of the bias currents in these amplifiers are set by FET current sources. The drain currents for the amplifiers are therefore essentially independent of supply voltage. As with most amplifiers, care should be taken with lead dress, component placement and supply decoupling in order to ensure stability. For example, resistors from the output to an input should be placed with the body close to the input to minimize ``pickup'' and maximize the frequency of the feedback pole by minimizing the capacitance from the input to ground. A feedback pole is created when the feedback around any amplifier is resistive. The parallel resistance and capacitance from the input of the device (usually the inverting input) to ac ground set the frequency of the pole. In many instances the frequency of this pole is much greater than the expected 3 dB frequency of the closed loop gain and consequently there is negligible effect on stability margin. However, if the feedback pole is less than approximately six times the expected 3 dB frequency a lead capacitor should be placed from the output to the input of the op amp. The value of the added capacitor should be such that the RC time constant of this capacitor and the resistance it parallels is greater than or equal to the original feedback pole time constant. The LF155/6/7 series are op amps with JFET input devices. These JFETs have large reverse breakdown voltages from gate to source and drain eliminating the need for clamps across the inputs. Therefore large differential input voltages can easily be accomodated without a large increase in input current. The maximum differential input voltage is independent of the supply voltages. However, neither of the input voltages should be allowed to exceed the negative supply as this will cause large currents to flow which can result in a destroyed unit. Exceeding the negative common-mode limit on either input will force the output to a high state, potentially causing a reversal of phase to the output. Exceeding the negative common-mode limit on both inputs will force the amplifier output to a high state. In neither case does a latch occur since raising the input back within the common-mode range again puts the input stage and thus the amplifier in a normal operating mode. Exceeding the positive common-mode limit on a single input will not change the phase of the output however, if both inputs exceed the limit, the output of the amplifier will be forced to a high state. These amplifiers will operate with the common-mode input voltage equal to the positive supply. In fact, the commonmode voltage can exceed the positive supply by approximately 100 mV independent of supply voltage and over the full operating temperature range. The positive supply can therefore be used as a reference on an input as, for example, in a supply current monitor and/or limiter. Typical Circuit Connections VOS Adjustment Driving Capacitive Loads # VOS is adjusted with a 25k potentiometer # The potentiometer wiper is con- TL/H/5646 - 15 *LF155/6 R e 5k LF157 For distortion s 1% and a 20 Vp-p VOUT swing, power bandwidth is: 500 kHz. R e 1.25k nected to V a # For potentiometers with temperature coefficient of 100 ppm/ C or less the additional drift with adjust is & 0.5 mV/ C/mV of adjustment # Typical overall drift: 5 mV/ C g (0.5 mV/ C/mV of adj.) LF157. A Large Power BW Amplifier Due to a unique output stage design, these amplifiers have the ability to drive large capacitive loads and still maintain stability. CL(MAX) j 0.01 mF. Overshoot s 20% Settling time (ts) j 5 ms 9 Typical Applications Settling Time Test Circuit # Settling time is tested with the LF155/6 connected as unity gain inverter and LF157 connected for AV e b 5 # FET used to isolate the probe capacitance # Output e 10V step # AV e b 5 for LF157 TL/H/5646 - 16 Large Signal inverter Output, VOUT (from Settling Time Circuit) LF356 LF355 TL/H/5646-17 LF357 TL/H/5646 - 18 Low Drift Adjustable Voltage Reference # # # # # D VOUT/DT e g 0.002%/ C All resistors and potentiometers should be wire-wound P1: drift adjust P2: VOUT adjust Use LF155 for X Low IB X Low drift X Low supply current TL/H/5646-20 10 TL/H/5646 - 19 Typical Applications (Continued) Fast Logarithmic Converter # Dynamic range: 100 mA ades), l VO l e 1V/decade # # # # s Ii s 1 mA (5 dec- Transient response: 3 ms for DIi e 1 decade C1, C2, R2, R3: added dynamic compensation VOS adjust the LF156 to minimize quiescent error RT: Tel Labs type Q81 a 0.3%/ C TL/H/5646 - 21 lVOUTl e ( R2 kT Rr 1a ln Vi RT q VREF Ri ( 1 e log Vi R2 e 15.7k, RT e 1k, 0.3%/ C (for temperature compensation) RiIr Precision Current Monitor # VO e 5 R1/R2 (V/mA of IS) # R1, R2, R3: 0.1% resistors # Use LF155 for X Common-mode range to supply range X Low IB X Low VOS X Low Supply Current TL/H/5646 - 31 8-Bit D/A Converter with Symmetrical Offset Binary Operation TL/H/5646 - 32 # R1, R2 should be matched within # Full-scale response time: 3ms EO a 9.920 a 0.040 b 0.040 b 9.920 g 0.05% B1 B2 B3 B4 B5 B6 B7 B8 1 1 0 0 1 0 1 0 1 0 1 0 1 0 1 0 1 0 1 0 11 1 0 1 0 1 0 1 0 1 0 1 0 Comments Positive Full-Scale ( a ) Zero-Scale (b) Zero-Scale Negative Full-Scale Typical Applications (Continued) Wide BW Low Noise, Low Drift Amplifier Isolating Large Capacitive Loads TL/H/5646 - 22 # Overshoot 6% # ts 10 ms # When driving large CL, the VOUT slew rate determined by CL and Sr j 191 kHz 2 q VP # Parasitic input capacitance C1 j (3 pF for LF155, LF156 and LF157 plus any additional layout capacitance) interacts with feedback elements and creates undesirable high frequency pole. To compensate add C2 such that: R2 C2 j R1 C1. # Power BW: fMAX e IOUT(MAX): DVOUT 0.02 I e OUT j V/ms e 0.04 V/ms (with CL shown) DT CL 0.5 Low Drift Peak Detector Boosting the LF156 with a Current Amplifier TL/H/5646 # By adding D1 and Rf, VD1 e 0 during hold mode. Leakage of D2 provided by feedback path through Rf. # IOUT(MAX) j 150 mA (will drive RL 0.15 # DVOUT e DT 10b2 # Leakage of circuit is essentially Ib (LF155, LF156) plus capacitor leakage t 100X) of Cp. V/ms (with CL shown) # Diode D3 clamps VOUT (A1) to VIN b VD3 to improve speed and to limit reverse bias of D2. # No additional phase shift added by the current amplifier # Maximum input frequency should be kk (/2qRfCD2 where CD2 is the shunt capacitance of D2. 3 Decades VCO Non-Inverting Unity Gain Operation for LF157 R1C t R1 e 1 (2q) (5 MHz) R2 a RS 4 AV(DC) e 1 fb3 dB & 5 MHz Inverting Unity Gain for LF157 R1C t R1 e TL/H/5646-24 fe 1 (2q) (5 MHz) R2 4 AV(DC) e b 1 VC (R8 a R7) , 0 s VC s 30V, 10 Hz s f s 10 kHz (8 VPU R8 R1) C fb3 dB & 5 MHz TL/H/5646 - 25 R1, R4 matched. Linearity 0.1% over 2 decades. 12 Typical Applications (Continued) High Impedance, Low Drift Instrumentation Amplifier TL/H/5646 - 26 # VOUT e ( R3 2R2 a 1 DV, Vb a 2V s VIN common-mode s V a R R1 # System VOS adjusted via A2 VOS adjust # Trim R3 to boost up CMRR to 120 dB. Instrumentation amplifier resistor array recommended for best accuracy and lowest drift 13 Typical Applications (Continued) Fast Sample and Hold TL/H/5646 - 33 # Both amplifiers (A1, A2) have feedback loops individually closed with stable responses (overshoot negligible) # Acquisition time TA, estimated by: TA j 2RON, VIN, Ch (/2 provided that: Sr ( VIN k 2qSr RON Ch and TA l VIN Ch , RON is of SW1 IOUT(MAX) VIN Ch If inequality not satisfied: TA j 20 mA # LF156 develops full Sr output capability for VIN t 1V # Addition of SW2 improves accuracy by putting the voltage drop across SW1 inside the feedback loop # Overall accuracy of system determined by the accuracy of both amplifiers, A1 and A2 High Accuracy Sample and Hold TL/H/5646 - 27 # By closing the loop through A2, the VOUT accuracy will be determined uniquely by A1. No VOS adjust required for A2. # TA can be estimated by same considerations as previously but, because of the added propagation delay in the feedback loop (A2) the overshoot is not negligible. # Overall system slower than fast sample and hold # R1, CC: additional compensation # Use LF156 for X Fast settling time X Low VOS 14 Typical Applications (Continued) High Q Band Pass Filter # By adding positive feedback (R2) Q increases to 40 # fBP e 100 kHz VOUT e 100Q VIN # Clean layout recommended # Response to a 1 Vp-p tone burst: 300 ms TL/H/5646 - 28 High Q Notch Filter # 2R1 e R e 10 MX 2C e C1 e 300 pF # Capacitors should be matched to obtain high Q # fNOTCH e 120 Hz, notch e b 55 dB, Q l 100 # Use LF155 for X Low IB X Low supply current TL/H/5646 - 34 15 16 Physical Dimensions inches (millimeters) Metal Can Package (H) Order Number LF156AH, LF155H, LF156H, LF255H, LF256H, LF257H, LF355AH, LF356AH, LF357AH, LF356BH, LF355H, LF356H or LF357H NS Package Number H08C Small Outline Package (M) Order Number LF355M, LF356M, LF357M, LF355BM or LF356BM NS Package Number M08A 17 LF155/LF156/LF157 Series Monolithic JFET Input Operational Amplifiers Physical Dimensions inches (millimeters) (Continued) Molded Dual-In-Line Package (N) Order Number LF355N, LF356N, LF357N, LF355BN, LF356BN, LF357BN NS Package Number N08E LIFE SUPPORT POLICY NATIONAL'S PRODUCTS ARE NOT AUTHORIZED FOR USE AS CRITICAL COMPONENTS IN LIFE SUPPORT DEVICES OR SYSTEMS WITHOUT THE EXPRESS WRITTEN APPROVAL OF THE PRESIDENT OF NATIONAL SEMICONDUCTOR CORPORATION. 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