LNBH221 Dual LNB supply and control IC with step-up converter and IC interface Features All the features are the same for both section Complete and independent interface between LNBS and relevant IC bus Built-in DC-DC controller for single 12 V supply operation and high efficiency (typ. 93 % @ 500 mA) LNB output current guaranteed up to 500 mA Both compliant with EUTELSAT and direct output voltage specification accurate built-in 22 kHz tone oscillator suits widely accepted standards Fast oscillator start-up facilitates DiSEqCTM encoding Built-in 22 kHz tone detector supports bidirectional DiSEqCTM 2.0 Semi low-drop post regulator and high efficiency step-up PWM for low power loss: Typ. 0.56 W @ 125 mA Two output pins suitable to by-pass the output R-L filter and avoid any tone distortion (R-L filter as per DiSEqC 2.0 specs, see Figure 4 on page 8) Overload and over-temperature internal protections Overload and over-temperature IC diagnostic bits LNB short circuit SOA protection with IC diagnostic bit PowerSO-36 ) s t( c u d o r P e et assembled in PowerSO-36, specifically designed to provide the power 13/18 V, and the 22 kHz tone signalling for two independent LNB down converters or to a multiswitch box that could be independently powered and set. In this application field, it offers a complete solution with extremely low component count, low power dissipation together with simple design and IC standard interfacing. l o bs O ) s ( t c u d o r eP t e ol s b O +/- 4 kV ESD tolerant on input/output power pins Description Intended for analog and digital dual satellite STB receivers/sat-TV, sets/PC cards, the LNBH221 is a voltage regulator and interface IC, April 2009 Doc ID 9913 Rev 6 1/27 www.st.com 27 Contents LNBH221 Contents 1 Diagram . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 3 2 Maximum ratings . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 4 3 Pin configuration . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 5 4 Typical application circuits for each section: A and B . . . . . . . . . . . . . 7 5 Application information . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 9 IC bus interface (one for each section) . . . . . . . . . . . . . . . . . . . . . . . . . . 10 5.2 Data validity . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 10 5.3 Start and stop conditions . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 10 5.4 Byte format . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 11 5.5 Acknowledge . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 11 ) s t( c u d o r P e t section) . . . . . . . . . . . 13 LNBH221 software description (same for lboth e o s b O ) s ( t c u d o r P e t oleElectrical characteristics . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 16 6 7 5.1 s b O 5.6 Transmission without acknowledgement . . . . . . . . . . . . . . . . . . . . . . . . . 11 6.1 Interface protocol . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 13 6.2 System register (SR, 1 byte) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 13 6.3 Transmitted data (IC bus write mode) . . . . . . . . . . . . . . . . . . . . . . . . . . . 13 6.4 Received data (IC bus read mode) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 14 6.5 Power-on IC interface reset . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 15 6.6 Address pin . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 15 6.7 DiSEqCTM implementation . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 15 8 Thermal design notes . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 18 9 Typical performance characteristics (of each section) . . . . . . . . . . . . 19 10 Package mechanical data . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 23 11 Revision history . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 26 2/27 Doc ID 9913 Rev 6 LNBH221 Diagram 1 Diagram Figure 1. Block diagram Gate LNBH221- section A Sense Step-up Controller VoTX Vup Vcc Byp SDA SCL VoRX Preregul.+ U.V.lockout +P.ON res. Linear Post-reg +Modulator +Protections V Select IC Diagn. Enable ADDR TEN 22KHz Oscill. DSQIN Tone Detector DSQOUT Step-up Controller SDA SCL Linear Post-reg +Modulator +Protections l o bs V Select IC TEN ) s t( c du EXTM Diagn. Enable ADDR DSQIN P e et VoRX Preregul.+ U.V.lockout +P.ON res. ) s t( c u d o r VoTX Vup Byp DETIN LNBH221- section B Gate Sense Vcc EXTM -O 22KHz Oscill. Tone Detector DETIN DSQOUT o r eP t e ol s b O Doc ID 9913 Rev 6 3/27 Maximum ratings LNBH221 2 Maximum ratings Table 1. Absolute maximum ratings Symbol Parameter Value Unit VCC DC input voltage -0.3 to 16 V VUP DC input voltage -0.3 to 25 V DC output pin voltage -0.3 to 25 V Internally limited mA VOTX/RX IO Output current VI Logic input voltage (SDA, SCL, DSQIN) -0.3 to 7 V Detector input signal amplitude -0.3 to 2 VPP VOH Logic high output voltage (DSQOUT) -0.3 to 7 V IGATE Gate current 400 mA Current sense voltage -0.3 to 1 Address pin voltage -0.3 to 7 VDETIN VSENSE VADDRESS TSTG TJ Storage temperature range -40 to 150 ) s t( Operating junction temperature range -40 to 125 C V c u d o r V C P e et Note: Absolute maximum ratings are those values beyond which damage to the device may occur. Functional operation under these conditions is not implied. Table 2. Thermal data Symbol RthJC -O Parameter ) s t( c du Thermal resistance junction-case l o bs o r eP t e ol s b O 4/27 Doc ID 9913 Rev 6 Value Unit 2 C/W LNBH221 Pin configuration 3 Pin configuration Figure 2. Pin configurations (top view) ) s t( c u d o r Table 3. Pin description Symbol VCC l o bs Name P e et Function A B 8 V to 15 V supply. A 220 F bypass capacitor to GND with a 470 nF (ceramic) in parallel is recommended. 8 26 External MOS switch gate connection of the step-up converter. 7 25 ) s t( c du Supply input -O Pin number Sect: GATE External switch gate SENSE Current sense (input) Current Sense comparator input. Connected to current sensing resistor. 6 24 Step-up voltage Input of the linear post-regulator. The voltage on this pin is monitored by the internal step-up controller to keep a minimum dropout across the linear pass transistor. 9 27 Output port during 22 RX Output to the LNB in DiSEqC 2.0 application. See truth table kHz Tone RX for voltage selections and description on page 4. 28 10 SDA Serial data Bidirectional data from/to IC bus. 2 20 SCL Serial clock Clock from IC bus. 3 21 DSQIN DiSEqC input When the TEN bit of the system register is LOW, this pin will accept the DiSEqC code from the main controller. Each section of the LNBH221 will use this code to modulate the internally generated 22 kHz carrier. Set to GND this pin if not used. 4 22 DETIN Detector in 22 kHz tone detector input. Must be AC coupled to the DiSEqC bus. 35 17 VUP o r eP t e ol VORX s b O Doc ID 9913 Rev 6 5/27 Pin configuration Table 3. LNBH221 Pin description Symbol Name Pin number Sect: Function A B Open drain output of the tone detector to the main microcontroller for DiSEqC data decoding. It is LOW when tone is detected on the DETIN. 5 23 External modulation External modulation input. Needs DC decoupling to the AC source. If not used, can be left open. 31 13 GND Ground 1, 14, 1, 14, 18, 18, Circuit ground. It is internally connected to the die frame for heat 19, 19, dissipation. 32, 32, 36 36 BYP Bypass capacitor pin Needed for internal pre regulator filtering. VOTX Output port during 22 Output of the linear post regulator/modulator to the LNB. See kHz tone TX truth table for voltage selections. GND Ground To be connected to ground. Address setting Four IC bus addresses available by setting the address pin level voltage. DSQOUT DiSEqC output EXTM ADDR l o bs O ) s ( t c u d o r eP t e ol s b O 6/27 Doc ID 9913 Rev 6 34 ) s t( 30 c u d o r P e et 16 12 29 11 33 15 LNBH221 Typical application circuits for each section: A and B 4 Typical application circuits for each section: A and B Figure 3. Application circuit for DiSEqC 1.x and output current up to 500 mA D1 1N4001 Axial Ferrite Bead Filter F1 suggested part number: MURATA BL01RN1-A62 Panasonic EXCELS A35 IC1 F1 Vup C9 220F C2 220F IC2 STS4DNFS30L VoRX C3 470nF Ceramic Set TTX=1 to LNB Gate VoTX LNBH221 Sense L1=22H Rsc 0.1 C5 10nF Section A and B C4 470nF Ceramic c u d o r Byp C5 470nF C1 220F P e et SDA EXTM SCL Address DSQIN DSQOUT Tone Enable ) s t( (**) DETIN Vcc Vin 12V D2 BAT43 l o bs GND 0<VADDR<VBYP O ) s ( t c u d o r eP t e ol s b O Doc ID 9913 Rev 6 7/27 Typical application circuits for each section: A and B Figure 4. LNBH221 Application circuit for bi-directional DiSEqC 2.0 and output current up to 500 mA F1 suggested part number: MURATA BL01RN1-A62 Panasonic EXCELS A35 D2 1N4001 Axial Ferrite Bead Filter IC1 F1 Vup C9 220F IC2 C3(***) 470nF Ceramic C2 220F VoTX D4(***) BAT43 C8(***) 100nF STS4DNFS30L 270H Gate LNBH221 Sense L1=22H to LNB VoRX C7(***) 100nF D3(***) BAT43 15 ohm (*) see note (**) DETIN Rsc 0.1 C6 10nF Section A and B Byp C1 220F Vin 12V C4(***) 470nF Ceramic ) s t( C5 470nF Vcc SDA EXTM SCL ADDRESS DSQIN (**) 22KHz Tone Enable c u d o r 0<VADDR<VBYP DSQOUT GND l o bs P e et C8, D3 and D4 are needed to protect the output pins from any negative voltage spikes during high speed voltage transitions. (*) R-L filter to be used according to EUTELSAT recommendation to implement the DiSEqCTM 2.0, (see DiSEqCTM implementation on page 8). If bidirectional DiSEqCTM 2.0 is not implemented it can be removed both with C8 and D4. O ) (**) Do not leave these pins floating if not used. s ( t c u d (***) To be soldered as close as possible to relative pins. o r eP t e ol s b O 8/27 Doc ID 9913 Rev 6 LNBH221 5 Application information Application information Basically, the LNBH221 includes two circuits that are completely independent. Each circuit can be separately controlled and must have its independent external components. All the below specification must be considered equal for each section. This IC has a built in DC-DC step-up controller that, from a single supply source ranging from 8 to 15 V, generates the voltages (VUP) that let the linear post-regulator to work at a minimum dissipated power of 1 W typ. @ 500 mA load (the linear regulator drop voltage is internally kept at: VUP - VOUT = 2 V typ.). An under voltage lockout circuit will disable the whole circuit when the supplied VCC drops below a fixed threshold (6.7 V typically). The internal 22 kHz tone generator is factory trimmed in accordance to the standards, and can be controlled either by the IC interface or by a dedicated pin (DSQIN) that allows immediate DiSEqCTM data encoding Note 1. When the TEN (Tone ENable) IC bit it is set to HIGH, a continuous 22 kHz tone is generated on the output regardless of the DSQIN pin logic status. The TEN bit must be set LOW when the DSQIN pin is used for DiSEqCTM encoding. The fully bi-directional DiSEqCTM 2.0 interfacing is completed by the built-in 22 kHz tone detector. Its input pin (DETIN) must be AC coupled to the DiSEqCTM bus, and the extracted PWK data are available on the DSQOUT pin Note 1. To comply to the bi-directional DiSEqCTM 2.0 bus hardware requirements an output R-L filter is needed. The LNBH221 is provided with two output pins: the VOTX to be used during the tone transmission and the VORX to be used when the tone is received. This allows the 22 kHz Tone to pass without any losses due to the R-L filter impedance (see DiSeqC 2.0 application circuit on page 4). In DiSeqC 2.0 applications during the 22 kHz transmission activated by DSQIN pin (or TEN IC bit), the VOTX pin must be preventively set ON by the TTX IC bit and, both the 13/18 V power supply and the 22 kHz tone, are provided by mean of VOTX output. As soon as the tone transmission is expired, the VOTX must be set to OFF by setting the TTX IC bit to zero and the 13/18 V power supply is provided to the LNB by the VORX pin through the R-L filter. When the LNBH221 is used in DiSeqC 1.x applications the R-L filter is not required (see DiSeqC 1.x Figure 4 on page 8), the TTX IC bit must be kept always to HIGH so that, the VOTX output pin can provide both the 13/18 V power supply and the 22 kHz tone, enabled by DSQIN pin or by TEN IC bit. All the functions of this IC are controlled via IC bus by writing 6 bits on the system register (SR, 8 bits). The same register can be read back, and two bits will report the diagnostic status. When the IC is put in stand-by (EN bit LOW), the power blocks are disabled. ) s t( c u d o r l o bs P e et O ) s ( t c u d o r eP When the regulator blocks are active (EN bit HIGH), the output can be logic controlled to be 13 or 18 V by mean of the VSEL bit (Voltage SELect) for remote controlling of non-DiSEqC LNBs. Additionally, the LNBH221 is provided with the LLC IC bit that increase the selected voltage value (+1 V when VSEL = 0 and +1.5 V when VSEL = 1) to compensate for the excess voltage drop along the coaxial cable (LLC bit HIGH). By mean of the LLC bit, the LNBH221 is also compliant to the American LNB power supply standards that require the higher output voltage level to 19.5 V (typ.) (instead of 18 V), by simply setting the LLC=1 when VSEL = 1. In order to improve design flexibility and to allow implementation of new coming LNB remote control standards, an analogic modulation input pin is available (EXTM). s b O t e ol An appropriate DC blocking capacitor must be used to couple the modulating signal source to the EXTM pin. Also in this case, the VOTX output must be set ON during the tone transmission by setting the TTX bit high. When external modulation is not used, the relevant pin can be left open. The current limitation block is SOA type: if the output port is shorted to ground, the SOA current limitation block limits the short circuit current (ISC) at typically 300 mA or 200 mA respectively for VOUT 13 V or 18 V, to reduce the power dissipation. Doc ID 9913 Rev 6 9/27 Application information LNBH221 Moreover, it is possible to set the short circuit current protection either statically (simple current clamp) or dynamically by the PCL bit of the IC SR; when the PCL (pulsed current limiting) bit is set to LOW, the overcurrent protection circuit works dynamically, as soon as an overload is detected, the output is shut-down for a time TOFF, typically 900 ms. Simultaneously the OLF bit of the system register is set to HIGH. After this time has elapsed, the output is resumed for a time TON = 1/10 TOFF (typ.). At the end of TON, if the overload is still detected, the protection circuit will cycle again through TOFF and TON. At the end of a full TON in which no overload is detected, normal operation is resumed and the OLF bit is reset to LOW. Typical TON + TOFF time is 990 ms and it is determined by an internal timer. This dynamic operation can greatly reduce the power dissipation in short circuit condition, still ensuring excellent power-on start up in most conditions. However, there could be some cases in which an highly capacitive load on the output may cause a difficult startup when the dynamic protection is chosen. This can be solved by initiating any power startup in static mode (PCL = HIGH) and then switching to the dynamic mode (PCL = LOW) after a chosen amount of time. When in static mode, the OLF bit goes HIGH when the current clamp limit is reached and returns LOW when the overload condition is cleared. This IC is also protected against overheating: when the junction temperature exceeds 150 C (typ.), the step-up converter and the linear regulator are shut off, and the OTF SR bit is set to HIGH. Normal operation is resumed and the OTF bit is reset to LOW when the junction is cooled down to 140 C (typ.). Note: ) s t( c u d o r 1 External components are needed to comply to bi-directional DiSEqCTM bus hardware requirements. Full compliance of the whole application to DiSEqCTM specifications is not implied by the use of this IC. 2 NOTICE: DiSEqC is a trademark of EUTELSAT. IC is a trademark of Philips Semiconductors. l o bs 5.1 P e et IC bus interface (one for each section) O ) Data transmission from main micropower to the LNBH221 and viceversa takes place through the 2 wires IC bus interface, consisting of the two lines SDA and SCL (pull-up resistors to positive supply voltage must be externally connected). 5.2 s ( t c Data validity u d o r P e t ole As shown in Figure 5, the data on the SDA line must be stable during the high period of the clock. The HIGH and LOW state of the data line can only change when the clock signal on the SCL line is LOW. s b O 5.3 Start and stop conditions As shown in Figure 6 a start condition is a HIGH to LOW transition of the SDA line while SCL is HIGH. The stop condition is a LOW to HIGH transition of the SDA line while SCL is HIGH. A STOP conditions must be sent before each START condition. 10/27 Doc ID 9913 Rev 6 LNBH221 5.4 Application information Byte format Every byte transferred to the SDA line must contain 8 bits. Each byte must be followed by an acknowledge bit. The MSB is transferred first. 5.5 Acknowledge The master (micropower) puts a resistive HIGH level on the SDA line during the acknowledge clock pulse (see Figure 7). The peripheral (LNBH221) that acknowledges has to pull-down (LOW) the SDA line during the acknowledge clock pulse, so that the SDA line is stable LOW during this clock pulse. The peripheral which has been addressed has to generate an acknowledge after the reception of each byte, otherwise the SDA line remains at the HIGH level during the ninth clock pulse time. In this case the master transmitter can generate the STOP information in order to abort the transfer. The LNBH221 won't generate the acknowledge if the VCC supply is below the under voltage lockout threshold (6.7 V typ.). 5.6 ) s t( Transmission without acknowledgement c u d o r Avoiding to detect the acknowledge of the LNBH221, the micropower can use a simpler transmission: simply it waits one clock without checking the slave acknowledging, and sends the new data. This approach of course is less protected from misworking and decreases the noise immunity. Figure 5. l o bs Data validity on the IC bus P e et O ) s ( t c u d o r eP t e ol s b O Doc ID 9913 Rev 6 11/27 Application information Figure 6. Figure 7. LNBH221 Timing diagram on IC bus ) s t( c u d o r Acknowledge on IC bus l o bs O ) s ( t c u d o r eP t e ol s b O 12/27 Doc ID 9913 Rev 6 P e et LNBH221 LNBH221 software description (same for both section) 6 LNBH221 software description (same for both section) 6.1 Interface protocol The interface protocol comprises: - A start condition (S) - A chip address byte = hex 10 / 11 (the LSB bit determines read(=1)/write(=0) transmission) - A sequence of data (1 byte + acknowledge) - A stop condition (P) Chip address MSB 0 0 S 0 1 0 Data 0 0 LSB R/W ACK MSB LSB t c u d ro ACK= Acknowledge S= Start P= Stop R/W= Read/Write 6.2 System register (SR, 1 byte) MSB R, W PCL R, W TTX R, W TEN R,W= read and write bit c u d R= Read-only bit All bits reset to 0 at power-on 6.3 R, W LLC ) s t( ) s ( ACK l o bs P P e et -O R, W VSEL LSB R, W EN R OTF R OLF o r eP Transmitted data (IC bus write mode) s b O t e ol When the R/W bit in the chip address is set to 0, the main micropower can write on the system register (SR) of the LNBH221 via IC bus. Only 6 bits out of the 8 available can be written by the micropower, since the remaining 2 are left to the diagnostic flags, and are read-only. Doc ID 9913 Rev 6 13/27 LNBH221 software description (same for both section) Table 4. PCL LNBH221 Truth table TTX TEN LLC VSEL EN OTF OLF 0 0 1 X X VOUT=13.25V, VUP=15.25V 0 1 1 X X VOUT=18V, VUP=20V 1 0 1 X X VOUT=14.25V, VUP=16.25V 1 1 1 X X VOUT=19.5V, VUP=21.5V 0 1 X X 22 kHz tone is controlled by DSQIN pin 1 1 X X 22 kHz tone is ON, DSQIN pin disabled 1 X X VORX output is ON, output voltage controlled by VSEL and LLC 1 X X VOTX output is ON, 22 kHz controlled by DSQIN or TEN, output voltage level controlled by VSEL and LLC 0 1 X X Pulsed (dynamic) current limiting is selected 1 1 X X Static current limiting is selected 0 X X Power blocks disabled 0 1 X X X X X X Function c u d o r X= don't care. Values are typical unless otherwise specified. l o bs 6.4 Received data (IC bus read mode) ) s t( P e et The LNBH221 can provide to the master a copy of the system register information via IC bus in read mode. The read mode is master activated by sending the chip address with R/W bit set to 1. O ) s ( t c u d At the following master generated clocks bits, the LNBH221 issues a byte on the SDA data bus line (MSB transmitted first). At the ninth clock bit the MCU master can: o r eP - acknowledge the reception, starting in this way the transmission of another byte from the LNBH221; - no acknowledge, stopping the read mode communication. t e ol s b O While the whole register is read back by the micropower, only the two read-only bits OLF and OTF convey diagnostic informations about the LNBH221. Table 5. PCL ISEL Register TEN LLC VSEL EN These bits are read exactly the same as they were left after last write operation OTF OLF Function 0 TJ<140C, normal operation 1 TJ>150C, power block disabled 0 IOUT<IOMAX, normal operation 1 IOUT>IOMAX, overload protection triggered Values are typical unless otherwise specified. 14/27 Doc ID 9913 Rev 6 LNBH221 6.5 LNBH221 software description (same for both section) Power-on IC interface reset The IC interface built in the LNBH221 is automatically reset at power on. As long as the VCC stays below the under voltage lockout threshold (6.7 V typ.), the interface will not respond to any IC command and the system register (SR) is initialized to all zeroes, thus keeping the power blocks disabled. Once the VCC rises above 7.3 V typ, the IC interface becomes operative and the SR can be configured by the main micropower. This is due to 500 mV of hysteresis provided in the UVL threshold to avoid false retriggering of the poweron reset circuit. 6.6 Address pin Connecting this pin to GND the chip IC interface address is 0001000, but, it is possible to choice among 4 different addresses simply setting this pin at 4 fixed voltage levels (see Table 9 on page 17). 6.7 ) s t( DiSEqCTM implementation c u d o r The LNBH221 helps the system designer to implement the bi-directional DiSEqC 2.0 protocol by allowing an easy PWK modulation/demodulation of the 22 kHz carrier. The PWK data are exchanged between the LNBH221 and the main micropower using logic levels that are compatible with both 3.3 and 5 V microcontrollers. This data exchange is made through two dedicated pins, DSQIN and DSQOUT, in order to maintain the timing relationships between the PWK data and the PWK modulation as accurate as possible. These two pins should be directly connected to two I/O pins of the micropower, thus leaving to the resident firmware the task of encoding and decoding the PWK data in accordance to the DiSEqC protocol. Full compliance of the system to the specification is thus not implied by the bare use of the LNBH221. The system designer should also take in consideration the bus hardware requirements; that can be simply accomplished by the R-L termination connected on the VOUT pins of the LNBH221, as shown in the Figure 4 on page 8. To avoid any losses due to the R-L impedance during the tone transmission, the LNBH221 has dedicated output (VOTX) that, in a DiSEqC 2.0 application, is connected after the filter and must be enabled by setting the TTX SR bit HIGH only during the tone transmission (see DiSEqC 2.0 Application information on page 9). Unidirectional (1.x) DiSEqC and non-DiSEqC systems normally don't need this termination, and the VOTX pin can be directly connected to the LNB supply port of the tuner (see Figure 3: Application circuit for DiSEqC 1.x and output current up to 500 mA on page 7). There is also no need of tone decoding, thus DETIN and DSQOUT pins can be left unconnected and the tone is provided by the VOTX. l o bs P e et O ) s ( t c u d o r eP t e ol s b O Doc ID 9913 Rev 6 15/27 Electrical characteristics 7 LNBH221 Electrical characteristics TJ = 0 to 85 C, EN = 1, TTX = 0/1, LLC=VSEL=TEN=PCL=0, DSQIN=LOW, VIN = 12 V, IOUT = 50 mA, unless otherwise specified. See software description section for IC access to the system register. Table 6. Electrical characteristics of each section (A and B) Symbol Parameter VIN Supply voltage IIN Supply current VOUT Output voltage VOUT Line regulation VOUT Load regulation Min. IOUT = 500 mA TEN=VSEL=LLC=1 Output voltage VOUT IMAX Parameter Typ. 8 Max. Unit 15 V EN=TEN=VSEL=LLC=1, No Load 20 EN=0 3.5 7 40 mA IOUT = 500 mA VSEL=1 LLC=0 17.3 18 18.7 LLC=1 18.7 19.5 20.3 IO = 500 mA VSEL=0 LLC=0 12.75 13.25 13.75 LLC=1 13.75 14.25 14.75 V c u d o r VSEL=0 VIN =8 to 15V VSEL=1 P e et 5 40 5 60 VSEL = 0 or 1 IOUT = 50 to 500mA l o bs Output current limiting VSEL = 0 ) s t( 500 V mV 200 mV 750 mA 300 -O ISC Output short circuit current tOFF Dynamic overload protection OFF time PCL=0, output shorted 900 ms tON Dynamic overload protection ON time PCL=0, output shorted tOFF/1 0 ms fTONE Tone frequency TEN=1 20 22 24 kHz ATONE DTONE VSEL = 1 c u d ) s t( mA 200 o r eP Tone amplitude TEN=1 0.55 0.72 0.9 VPP Tone duty cycle TEN=1 40 50 60 % Tone rise and fall time TEN=1 5 8 15 s GEXTM External modulation gain VOUT/VEXTM, f = 10Hz to 50kHz, TTX=1 VEXTM External modulation input voltage AC Coupling, TTX=1 400 mVPP ZEXTM External modulation impedance f = 10Hz to 50kHz 260 W fSW DC-DC converter switch frequency 220 kHz fDETIN Tone detector frequency capture range t e ol tr, tf s b O 16/27 0.4VPP sinewave Doc ID 9913 Rev 6 6 18 24 kHz LNBH221 Table 6. Electrical characteristics Electrical characteristics of each section (A and B) (continued) Symbol Parameter Parameter VDETIN Tone detector input amplitude ZDETIN Tone detector input impedance Min. fIN=22 kHz sinewave Typ. 0.2 Max. Unit 1.5 VPP 150 VOL DSQOUT pin logic LOW Tone present, IOL=2mA IOZ DSQOUT pin leakage current Tone absent, VOH = 6V VIL DSQIN input pin logic LOW VIH DSQIN input pin logic HIGH IIH DSQIN pin input current VIH = 5V 15 IOBK Output backward current EN=0, VOBK = 18V -6 0.3 k 0.5 V 10 A 0.8 V 2 V A -15 mA TSHDN Thermal shutdown threshold 150 C TSHDN Thermal shutdown hysteresis 15 C Table 7. Gate and sense electrical characteristics (TJ = 0 to 85 C, VIN = 12 V) Symbol Parameter Parameter RDSON-L Gate LOW RDSON IGATE=-100mA RDSON-H Gate LOW RDSON IGATE=100mA VSENSE Current limit sense voltage Table 8. Min. c u d o r eP let o s b ) s t( Typ. Max. Unit 4.5 4.5 200 mV IC electrical characteristics (TJ = 0 to 85 C, VIN = 12 V) Symbol O ) Parameter VIL LOW level input voltage VIH HIGH level input voltage IIN Input current c u d o r eP Parameter t(s Min. Typ. SDA, SCL SDA, SCL Max. Unit 0.8 V 2 SDA, SCL, VIN= 0.4 to 4.5V VOL Low level output voltage SDA (open drain), IOL = 6mA fMAX Maximum clock frequency SCL V -10 10 A 0.6 V 500 kHz t e ol bs Table 9. O Symbol Address pin characteristics (TJ = 0 to 85 C, VIN = 12 V) Parameter Parameter Min. Typ. Max. Unit VADDR-1 "0001000" addr pin voltage 0 0.7 V VADDR-2 "0001001" addr pin voltage 1.3 1.7 V VADDR-3 "0001010" addr pin voltage 2.3 2.7 V VADDR-4 "0001011" addr pin voltage 3.3 5 V VADDR-1 "0001000" addr pin voltage 0 0.7 V Doc ID 9913 Rev 6 17/27 Thermal design notes 8 LNBH221 Thermal design notes During normal operation, the LNBH221 device dissipates some power. At rated output current of 500 mA on each section output, the voltage drop on both linear regulators lead to a total dissipated power that is typically 2 W. The heat generated requires a suitable heatsink to keep the junction temperature below the over-temperature protection threshold. Assuming a 45 C temperature inside the set-top-box case, the total RthJC has to be less than 40 C/W. While this can be easily achieved using a through-hole power package that can be attached to a small heatsink or to the metallic frame of the receiver, a surface mount power package must rely on PCB solutions whose thermal efficiency is often limited. The simplest solution is to use a large, continuous copper area of the GND layer to dissipate the heat coming from the IC body. Given for the PSO-36 package an RthJC equal to 2 C/W, a maximum of 38 C/W are left to the PCB heatsink. This area can be the inner GND layer of a multi-layer PCB, or, in a dual layer PCB, an unbroken GND area even on the opposite side where the IC is placed. In figure 8, it is shown a suggested layout for the PSO-36 package with a dual layer PCB, where the IC exposed pad connected to GND and the square dissipating area are thermally connected through 32 vias holes, filled by solder. This arrangement, when L = 40 mm, achieves an RthJA of about 28 C/W. ) s t( c u d o r Different layouts are possible, too. Basic principles, however, suggest to keep the IC and its ground exposed pad approximately in the middle of the dissipating area; to provide as many vias as possible; to design a dissipating area having a shape as square as possible and not interrupted by other copper traces. Figure 8. l o bs PowerSO-36 suggested PCB heatsink layout O ) s ( t c u d o r eP t e ol s b O 18/27 Doc ID 9913 Rev 6 P e et LNBH221 9 Typical performance characteristics (of each section) Typical performance characteristics (of each section) TJ = 25 C, unless otherwise specification. Figure 9. Output voltage vs. temperature Figure 10. Output voltage vs. temperature ) s t( Figure 11. Output voltage vs. temperature c u d o r Figure 12. Load regulation vs. temperature l o bs P e et O ) s ( t c u d o r eP Figure 13. Load regulation vs. temperature t e ol Figure 14. Supply current vs. temperature s b O Doc ID 9913 Rev 6 19/27 Typical performance characteristics (of each section) LNBH221 Figure 15. Supply current vs. temperature Figure 16. Supply current vs. temperature Figure 17. Dynamic overload protection ON time vs. temperature Figure 18. Dynamic overload protection OFF time vs. temperature ) s t( c u d o r l o bs P e et O ) s ( t c u d Figure 19. Output current limiting vs. temperature Figure 20. Tone frequency vs. temperature o r eP t e ol s b O 20/27 Doc ID 9913 Rev 6 LNBH221 Typical performance characteristics (of each section) Figure 21. Tone amplitude vs. temperature Figure 22. Tone duty cycle vs. temperature Figure 23. Tone rise time vs. temperature Figure 24. Tone fall time vs. temperature ) s t( c u d o r l o bs P e et O ) s ( t c u d Figure 25. Under voltage lockout threshold vs. Figure 26. Output backward current vs. temperature temperature o r eP t e ol s b O Doc ID 9913 Rev 6 21/27 Typical performance characteristics (of each section) LNBH221 Figure 27. DC-DC converter efficiency vs. temperature Figure 28. Current limit sense voltage vs. temperature Figure 29. 22 kHz tone waveform Figure 30. DSQIN tone enable transient response ) s t( c u d o r l o bs P e et O ) s ( t c u d VCC = 12 V, IO = 50 mA, EN = TEN = 1 VCC = 12 V, IO = 50 mA, EN=1, Tone enabled by DSQIN pin Figure 31. DSQIN tone enable transient response Figure 32. DSQIN tone disable transient response o r eP t e ol s b O VCC = 12 V, IO = 50 mA, EN=1, Tone enabled by DSQIN pin 22/27 VCC = 12 V, IO = 50 mA, EN=1, Tone enabled by DSQIN pin Doc ID 9913 Rev 6 LNBH221 10 Package mechanical data Package mechanical data In order to meet environmental requirements, ST offers these devices in different grades of ECOPACK(R) packages, depending on their level of environmental compliance. ECOPACK(R) specifications, grade definitions and product status are available at: www.st.com. ECOPACK(R) is an ST trademark. ) s t( c u d o r l o bs P e et O ) s ( t c u d o r eP t e ol s b O Doc ID 9913 Rev 6 23/27 Package mechanical data LNBH221 PowerSO-36 mechanical data mm. Dim. A a1 a2 a3 b c D (1) D1 E E1 (1) E2 E3 e e3 G H h L N S Min. inch. Typ. Max. Min. 3.60 0.30 3.30 0.10 0.38 0.32 16.00 9.80 14.50 11.10 2.90 6.2 0.10 0 0.22 0.23 15.80 9.40 13.90 10.90 5.8 Typ. Max. 0.1417 0.0118 0.1299 0.0039 0.0150 0.0126 0.6299 0.3858 0.5709 0.4370 0.1142 0.2441 0.0039 0 0.0087 0.0091 0.6220 0.3701 0.5472 0.4291 0.2283 0.65 11.05 ) s t( 0.0256 0.4350 0 15.50 0.10 15.90 1.10 1.10 10 8 0.80 0 c u d o r 0.0000 0.6102 P e et 0.0315 0.0039 0.6260 0.0433 0.0433 10 8 0 l o bs (1) "D and E1" do not include mold flash or protusions - Mold flash or protusions shall not exceed 0.15 mm (0.006") O ) s ( t c u d o r eP t e ol s b O 0096119/B 24/27 Doc ID 9913 Rev 6 LNBH221 Package mechanical data Tape and reel PowerSO-36 mechanical data mm. inch. Dim. Min. Typ. Max. A Min. Typ. 330 12.992 C 12.8 13.2 D 20.2 0.795 N 60 2.362 T Max. 0.504 30.4 0.519 1.197 Ao 15.1 15.3 0.594 0.602 Bo 16.5 16.7 0.650 0.658 Ko 3.8 4.0 0.149 0.157 Po 3.9 4.1 0.153 0.161 P 23.9 24.1 0.941 W 23.7 24.3 0.933 l o bs ) s t( c u d o r 0.949 0.957 P e et O ) s ( t c u d o r eP t e ol s b O Doc ID 9913 Rev 6 25/27 Revision history LNBH221 11 Revision history Table 10. Document revision history Date Revision Changes 08-Apr-2005 4 Maturity changed. 01-Mar-2006 5 The Figure 3 and Figure 4 updated. 17-Apr-2009 6 Updated statement ECOPACK(R). ) s t( c u d o r l o bs O ) s ( t c u d o r eP t e ol s b O 26/27 Doc ID 9913 Rev 6 P e et LNBH221 Please Read Carefully: Information in this document is provided solely in connection with ST products. STMicroelectronics NV and its subsidiaries ("ST") reserve the right to make changes, corrections, modifications or improvements, to this document, and the products and services described herein at any time, without notice. ) s t( All ST products are sold pursuant to ST's terms and conditions of sale. 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