April 2009 Doc ID 9913 Rev 6 1/27
27
LNBH221
Dual LNB supply and control IC with
step-up converter and I²C interface
Features
■All the features are the same for both section
■Complete and independent interface between
LNBS and relevant I²C bus
■Built-in DC-DC controller for single 12 V supply
operation and high efficiency (typ. 93 % @ 500
mA)
■LNB output current guaranteed up to 500 mA
■Both compliant with EUTELSAT and direct
output voltage specification accurate built-in 22
kHz tone oscillator suits widely accepted
standards
■Fast oscillator start-up facilitates DiSEqC™
encoding
■Built-in 22 kHz tone detector supports bi-
directional DiSEqC™ 2.0
■Semi low-drop post regulator and high
efficiency step-up PWM for low power loss:
Typ. 0.56 W @ 125 mA
■Two output pins suitable to by-pass the output
R-L filter and avoid any tone distortion (R-L
filter as per DiSEqC 2.0 specs, see Figure 4 on
page 8)
■Overload and over-temperature internal
protections
■Overload and over-temperature I²C diagnostic
bits
■LNB short circuit SOA protection with I²C
diagnostic bit
■+/- 4 kV ESD tolerant on input/output power
pins
Description
Intended for analog and digital dual satellite STB
receivers/sat-TV, sets/PC cards, the LNBH221 is
a voltage regulator and interface IC,
assembled in PowerSO-36, specifically designed
to provide the power 13/18 V, and the 22 kHz tone
signalling for two independent LNB down
converters or to a multiswitch box that could be
independently powered and set. In this
application field, it offers a complete solution with
extremely low component count, low power
dissipation together with simple design and I²C
standard interfacing.
PowerSO-36
www.st.com
Obsolete Product(s) - Obsolete Product(s)
Obsolete Product(s) - Obsolete Product(s)
Contents LNBH221
2/27 Doc ID 9913 Rev 6
Contents
1 Diagram . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 3
2 Maximum ratings . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 4
3 Pin configuration . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 5
4 Typical application circuits for each section: A and B . . . . . . . . . . . . . 7
5 Application information . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 9
5.1 I²C bus interface (one for each section) . . . . . . . . . . . . . . . . . . . . . . . . . . 10
5.2 Data validity . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 10
5.3 Start and stop conditions . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 10
5.4 Byte format . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 11
5.5 Acknowledge . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 11
5.6 Transmission without acknowledgement . . . . . . . . . . . . . . . . . . . . . . . . . 11
6 LNBH221 software description (same for both section) . . . . . . . . . . . 13
6.1 Interface protocol . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 13
6.2 System register (SR, 1 byte) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 13
6.3 Transmitted data (I²C bus write mode) . . . . . . . . . . . . . . . . . . . . . . . . . . . 13
6.4 Received data (I²C bus read mode) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 14
6.5 Power-on I²C interface reset . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 15
6.6 Address pin . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 15
6.7 DiSEqC™ implementation . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 15
7 Electrical characteristics . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 16
8 Thermal design notes . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 18
9 Typical performance characteristics (of each section) . . . . . . . . . . . . 19
10 Package mechanical data . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 23
11 Revision history . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 26
Obsolete Product(s) - Obsolete Product(s)
LNBH221 Diagram
Doc ID 9913 Rev 6 3/27
1 Diagram
Figure 1. Block diagram
LNBH221- section A
LNBH221- section B
DSQIN
Vup VoRX
SDA
SCL
Vcc
DSQOUT
VoTX
DETIN
Byp
Gate
Sense
EXTM
ADDR
Enable
Preregul.+
U.V.lockout
+P.ON res.
V Select
Linear Post-reg
+Modulator
+Protections
Diagn.
I²C
Tone
Detector
22KHz
Oscill.
TEN
Step-up
Controller
DSQIN
Vup VoRX
SDA
SCL
Vcc
DSQOUT
VoTX
DETIN
Byp
Gate
Sense
EXTM
ADDR
Enable
Preregul.+
U.V.lockout
+P.ON res.
V Select
Linear Post-reg
+Modulator
+Protections
Diagn.
I²C
Tone
Detector
22KHz
Oscill.
TEN
Step-up
Controller
LNBH221- section A
LNBH221- section B
DSQIN
Vup VoRX
SDA
SCL
Vcc
DSQOUT
VoTX
DETIN
Byp
Gate
Sense
EXTM
ADDR
Enable
Preregul.+
U.V.lockout
+P.ON res.
V Select
Linear Post-reg
+Modulator
+Protections
Diagn.
I²C
Tone
Detector
22KHz
Oscill.
TEN
Step-up
Controller
Enable
Preregul.+
U.V.lockout
+P.ON res.
V Select
Linear Post-reg
+Modulator
+Protections
Diagn.
I²C
Tone
Detector
22KHz
Oscill.
TEN
Step-up
Controller
DSQIN
Vup VoRX
SDA
SCL
Vcc
DSQOUT
VoTX
DETIN
Byp
Gate
Sense
EXTM
ADDR
Enable
Preregul.+
U.V.lockout
+P.ON res.
V Select
Linear Post-reg
+Modulator
+Protections
Diagn.
I²C
Tone
Detector
22KHz
Oscill.
TEN
Step-up
Controller
Enable
Preregul.+
U.V.lockout
+P.ON res.
V Select
Linear Post-reg
+Modulator
+Protections
Diagn.
I²C
Tone
Detector
22KHz
Oscill.
TEN
Step-up
Controller
Obsolete Product(s) - Obsolete Product(s)
Maximum ratings LNBH221
4/27 Doc ID 9913 Rev 6
2 Maximum ratings
Note: Absolute maximum ratings are those values beyond which damage to the device may occur.
Functional operation under these conditions is not implied.
Table 1. Absolute maximum ratings
Symbol Parameter Value Unit
VCC DC input voltage -0.3 to 16 V
VUP DC input voltage -0.3 to 25 V
VOTX/RX DC output pin voltage -0.3 to 25 V
IOOutput current Internally limited mA
VILogic input voltage (SDA, SCL, DSQIN) -0.3 to 7 V
VDETIN Detector input signal amplitude -0.3 to 2 VPP
VOH Logic high output voltage (DSQOUT) -0.3 to 7 V
IGATE Gate current ± 400 mA
VSENSE Current sense voltage -0.3 to 1 V
VADDRESS Address pin voltage -0.3 to 7 V
TSTG Storage temperature range -40 to 150 °C
TJOperating junction temperature range -40 to 125 °C
Table 2. Thermal data
Symbol Parameter Value Unit
RthJC Thermal resistance junction-case 2 °C/W
Obsolete Product(s) - Obsolete Product(s)
LNBH221 Pin configuration
Doc ID 9913 Rev 6 5/27
3 Pin configuration
Figure 2. Pin configurations (top view)
Table 3. Pin description
Symbol Name Function
Pin number
Sect:
AB
VCC Supply input 8 V to 15 V supply. A 220 µF bypass capacitor to GND with a 470
nF (ceramic) in parallel is recommended. 826
GATE External switch gate External MOS switch gate connection of the step-up converter. 7 25
SENSE Current sense (input) Current Sense comparator input. Connected to current sensing
resistor. 624
VUP Step-up voltage
Input of the linear post-regulator. The voltage on this pin is
monitored by the internal step-up controller to keep a minimum
dropout across the linear pass transistor.
927
VORX Output port during 22
kHz Tone RX
RX Output to the LNB in DiSEqC 2.0 application. See truth table
for voltage selections and description on page 4. 28 10
SDA Serial data Bidirectional data from/to I²C bus. 2 20
SCL Serial clock Clock from I²C bus. 3 21
DSQIN DiSEqC input
When the TEN bit of the system register is LOW, this pin will
accept the DiSEqC code from the main μcontroller. Each section
of the LNBH221 will use this code to modulate the internally
generated 22 kHz carrier. Set to GND this pin if not used.
422
DETIN Detector in 22 kHz tone detector input. Must be AC coupled to the DiSEqC
bus. 35 17
Obsolete Product(s) - Obsolete Product(s)
Pin configuration LNBH221
6/27 Doc ID 9913 Rev 6
DSQOUT DiSEqC output
Open drain output of the tone detector to the main
microcontroller for DiSEqC data decoding. It is LOW when tone is
detected on the DETIN.
523
EXTM External modulation External modulation input. Needs DC decoupling to the AC
source. If not used, can be left open. 31 13
GND Ground Circuit ground. It is internally connected to the die frame for heat
dissipation.
1, 14,
18,
19,
32,
36
1, 14,
18,
19,
32,
36
BYP Bypass capacitor pin Needed for internal pre regulator filtering. 34 16
VOTX Output port during 22
kHz tone TX
Output of the linear post regulator/modulator to the LNB. See
truth table for voltage selections. 30 12
GND Ground To be connected to ground. 29 11
ADDR Address setting Four I²C bus addresses available by setting the address pin level
voltage. 33 15
Table 3. Pin description
Symbol Name Function
Pin number
Sect:
AB
Obsolete Product(s) - Obsolete Product(s)
LNBH221 Typical application circuits for each section: A and B
Doc ID 9913 Rev 6 7/27
4 Typical application circuits for each section: A and B
Figure 3. Application circuit for DiSEqC 1.x and output current up to 500 mA
LNBH221
Vup
Gate
Vin
12V
L1=22µH Sense
Vcc
C5
10nF
VoTX
SDA
SCL
DSQIN
Address
C5
470nF
GND
0<VADDR
<VBYP
Rsc
0.1 Ω
C3
470nF
Ceramic
D1 1N4001
C1
220µF
C4
470nF
Ceramic
D2
BAT43
IC1
STS4DNFS30L
IC2
C9
220µF C2
220µF
Axial Ferrite Bead Filter
F1
F1 suggested part number:
MURATA BL01RN1-A62
Panasonic EXCELS A35
EXTM
DSQOUT
(**) DETIN
VoRX
to LNB
Byp
Tone Enable
Set TTX=1
Section A and B
LNBH221
Vup
Gate
Vin
12V
L1=22µH Sense
Vcc
C5
10nF
VoTX
SDA
SCL
DSQIN
Address
C5
470nF
GND
0<VADDR
<VBYP
Rsc
0.1 Ω
C3
470nF
Ceramic
D1 1N4001
C1
220µF
C4
470nF
Ceramic
D2
BAT43
IC1
STS4DNFS30L
IC2
STS4DNFS30L
IC2
C9
220µF
C9
220µF C2
220µF
Axial Ferrite Bead Filter
F1
F1 suggested part number:
MURATA BL01RN1-A62
Panasonic EXCELS A35
EXTM
DSQOUT
(**) DETIN
VoRX
to LNB
Byp
Tone Enable
Set TTX=1
Section A and B
Obsolete Product(s) - Obsolete Product(s)
Typical application circuits for each section: A and B LNBH221
8/27 Doc ID 9913 Rev 6
C8, D3 and D4 are needed to protect the output pins from any negative voltage spikes during high speed
voltage transitions.
(*) R-L filter to be used according to EUTELSAT recommendation to implement the DiSEqC™ 2.0, (see
DiSEqC™ implementation on page 8). If bidirectional DiSEqC™ 2.0 is not implemented it can be removed
both with C8 and D4.
(**) Do not leave these pins floating if not used.
(***) To be soldered as close as possible to relative pins.
Figure 4. Application circuit for bi-directional DiSEqC 2.0 and output current up to 500 mA
22KHz Tone Enable
270µH
15 ohm
(*) see note
LNBH221
Vup
Gate
Vin
12V
L1=22µH Sense
Vcc
VoRX
VoTX
(**) DETIN
C7(***)
100nF
to LNB
SDA
SCL
DSQOUT
DSQIN (**)
ADDRESS
Byp
C5
470nF
GND
0<VADDR<VBYP
EXTM
C6
10nF
Rsc
0.1 Ω
C3(***)
470nF
Ceramic
D2 1N4001
C1
220µF
C4(***)
470nF
Ceramic
D3(***)
BAT43
IC1
D4(***)
BAT43
C8(***)
100nF
C9
220µF C2
220µF
F1
Axial Ferrite Bead Filter
F1 suggested part number:
MURATA BL01RN1-A62
Panasonic EXCELS A35
Section A and B
STS4DNFS30L
IC2
22KHz Tone Enable
270µH
15 ohm
(*) see note
LNBH221
Vup
Gate
Vin
12V
L1=22µH Sense
Vcc
VoRX
VoTX
(**) DETIN
C7(***)
100nF
to LNB
SDA
SCL
DSQOUT
DSQIN (**)
ADDRESS
Byp
C5
470nF
GND
0<VADDR<VBYP
0<VADDR<VBYP
EXTM
C6
10nF
Rsc
0.1 Ω
C3(***)
470nF
Ceramic
D2 1N4001
C1
220µF
C4(***)
470nF
Ceramic
D3(***)
BAT43
IC1
D4(***)
BAT43
C8(***)
100nF
C9
220µF
C9
220µF C2
220µF
F1
Axial Ferrite Bead Filter
F1 suggested part number:
MURATA BL01RN1-A62
Panasonic EXCELS A35
Axial Ferrite Bead Filter
F1 suggested part number:
MURATA BL01RN1-A62
Panasonic EXCELS A35
Section A and B
STS4DNFS30L
IC2
STS4DNFS30L
IC2
Obsolete Product(s) - Obsolete Product(s)
LNBH221 Application information
Doc ID 9913 Rev 6 9/27
5 Application information
Basically, the LNBH221 includes two circuits that are completely independent. Each circuit
can be separately controlled and must have its independent external components. All the
below specification must be considered equal for each section.
This IC has a built in DC-DC step-up controller that, from a single supply source ranging
from 8 to 15 V, generates the voltages (VUP) that let the linear post-regulator to work at a
minimum dissipated power of 1 W typ. @ 500 mA load (the linear regulator drop voltage is
internally kept at: VUP - VOUT = 2 V typ.). An under voltage lockout circuit will disable the
whole circuit when the supplied VCC drops below a fixed threshold (6.7 V typically). The
internal 22 kHz tone generator is factory trimmed in accordance to the standards, and can
be controlled either by the I²C interface or by a dedicated pin (DSQIN) that allows immediate
DiSEqC™ data encoding Note 1. When the TEN (Tone ENable) I²C bit it is set to HIGH, a
continuous 22 kHz tone is generated on the output regardless of the DSQIN pin logic status.
The TEN bit must be set LOW when the DSQIN pin is used for DiSEqC™ encoding. The
fully bi-directional DiSEqC™ 2.0 interfacing is completed by the built-in 22 kHz tone
detector. Its input pin (DETIN) must be AC coupled to the DiSEqC™ bus, and the extracted
PWK data are available on the DSQOUT pin Note 1. To comply to the bi-directional
DiSEqC™ 2.0 bus hardware requirements an output R-L filter is needed. The LNBH221 is
provided with two output pins: the VOTX to be used during the tone transmission and the
VORX to be used when the tone is received. This allows the 22 kHz Tone to pass without
any losses due to the R-L filter impedance (see DiSeqC 2.0 application circuit on page 4). In
DiSeqC 2.0 applications during the 22 kHz transmission activated by DSQIN pin (or TEN I²C
bit), the VOTX pin must be preventively set ON by the TTX I²C bit and, both the 13/18 V
power supply and the 22 kHz tone, are provided by mean of VOTX output. As soon as the
tone transmission is expired, the VOTX must be set to OFF by setting the TTX I²C bit to zero
and the 13/18 V power supply is provided to the LNB by the VORX pin through the R-L filter.
When the LNBH221 is used in DiSeqC 1.x applications the R-L filter is not required (see
DiSeqC 1.x Figure 4 on page 8), the TTX I²C bit must be kept always to HIGH so that, the
VOTX output pin can provide both the 13/18 V power supply and the 22 kHz tone, enabled
by DSQIN pin or by TEN I²C bit. All the functions of this IC are controlled via I²C bus by
writing 6 bits on the system register (SR, 8 bits). The same register can be read back, and
two bits will report the diagnostic status. When the IC is put in stand-by (EN bit LOW), the
power blocks are disabled.
When the regulator blocks are active (EN bit HIGH), the output can be logic controlled to be
13 or 18 V by mean of the VSEL bit (Voltage SELect) for remote controlling of non-DiSEqC
LNBs. Additionally, the LNBH221 is provided with the LLC I²C bit that increase the selected
voltage value (+1 V when VSEL = 0 and +1.5 V when VSEL = 1) to compensate for the
excess voltage drop along the coaxial cable (LLC bit HIGH). By mean of the LLC bit, the
LNBH221 is also compliant to the American LNB power supply standards that require the
higher output voltage level to 19.5 V (typ.) (instead of 18 V), by simply setting the LLC=1
when VSEL = 1. In order to improve design flexibility and to allow implementation of new
coming LNB remote control standards, an analogic modulation input pin is available
(EXTM).
An appropriate DC blocking capacitor must be used to couple the modulating signal source
to the EXTM pin. Also in this case, the VOTX output must be set ON during the tone
transmission by setting the TTX bit high. When external modulation is not used, the relevant
pin can be left open. The current limitation block is SOA type: if the output port is shorted to
ground, the SOA current limitation block limits the short circuit current (ISC) at typically 300
mA or 200 mA respectively for VOUT 13 V or 18 V, to reduce the power dissipation.
Obsolete Product(s) - Obsolete Product(s)
Application information LNBH221
10/27 Doc ID 9913 Rev 6
Moreover, it is possible to set the short circuit current protection either statically (simple
current clamp) or dynamically by the PCL bit of the I²C SR; when the PCL (pulsed current
limiting) bit is set to LOW, the overcurrent protection circuit works dynamically, as soon as an
overload is detected, the output is shut-down for a time TOFF
, typically 900 ms.
Simultaneously the OLF bit of the system register is set to HIGH. After this time has
elapsed, the output is resumed for a time TON = 1/10 TOFF (typ.). At the end of TON, if the
overload is still detected, the protection circuit will cycle again through TOFF and TON. At the
end of a full TON in which no overload is detected, normal operation is resumed and the OLF
bit is reset to LOW. Typical TON + TOFF time is 990 ms and it is determined by an internal
timer. This dynamic operation can greatly reduce the power dissipation in short circuit
condition, still ensuring excellent power-on start up in most conditions. However, there could
be some cases in which an highly capacitive load on the output may cause a difficult start-
up when the dynamic protection is chosen. This can be solved by initiating any power start-
up in static mode (PCL = HIGH) and then switching to the dynamic mode (PCL = LOW) after
a chosen amount of time. When in static mode, the OLF bit goes HIGH when the current
clamp limit is reached and returns LOW when the overload condition is cleared. This IC is
also protected against overheating: when the junction temperature exceeds 150 °C (typ.),
the step-up converter and the linear regulator are shut off, and the OTF SR bit is set to
HIGH. Normal operation is resumed and the OTF bit is reset to LOW when the junction is
cooled down to 140 °C (typ.).
Note: 1 External components are needed to comply to bi-directional DiSEqC™ bus hardware
requirements. Full compliance of the whole application to DiSEqC™ specifications is not
implied by the use of this IC.
2 NOTICE: DiSEqC is a trademark of EUTELSAT. I²C is a trademark of Philips
Semiconductors.
5.1 I²C bus interface (one for each section)
Data transmission from main micropower to the LNBH221 and viceversa takes place
through the 2 wires I²C bus interface, consisting of the two lines SDA and SCL (pull-up
resistors to positive supply voltage must be externally connected).
5.2 Data validity
As shown in Figure 5, the data on the SDA line must be stable during the high period of the
clock. The HIGH and LOW state of the data line can only change when the clock signal on
the SCL line is LOW.
5.3 Start and stop conditions
As shown in Figure 6 a start condition is a HIGH to LOW transition of the SDA line while
SCL is HIGH.
The stop condition is a LOW to HIGH transition of the SDA line while SCL is HIGH. A STOP
conditions must be sent before each START condition.
Obsolete Product(s) - Obsolete Product(s)
LNBH221 Application information
Doc ID 9913 Rev 6 11/27
5.4 Byte format
Every byte transferred to the SDA line must contain 8 bits. Each byte must be followed by an
acknowledge bit. The MSB is transferred first.
5.5 Acknowledge
The master (micropower) puts a resistive HIGH level on the SDA line during the
acknowledge clock pulse (see Figure 7). The peripheral (LNBH221) that acknowledges has
to pull-down (LOW) the SDA line during the acknowledge clock pulse, so that the SDA line is
stable LOW during this clock pulse. The peripheral which has been addressed has to
generate an acknowledge after the reception of each byte, otherwise the SDA line remains
at the HIGH level during the ninth clock pulse time. In this case the master transmitter can
generate the STOP information in order to abort the transfer. The LNBH221 won't generate
the acknowledge if the VCC supply is below the under voltage lockout threshold (6.7 V typ.).
5.6 Transmission without acknowledgement
Avoiding to detect the acknowledge of the LNBH221, the micropower can use a simpler
transmission: simply it waits one clock without checking the slave acknowledging, and sends
the new data.
This approach of course is less protected from misworking and decreases the noise
immunity.
Figure 5. Data validity on the I²C bus
Obsolete Product(s) - Obsolete Product(s)
Application information LNBH221
12/27 Doc ID 9913 Rev 6
Figure 6. Timing diagram on I²C bus
Figure 7. Acknowledge on I²C bus
Obsolete Product(s) - Obsolete Product(s)
LNBH221 LNBH221 software description (same for both section)
Doc ID 9913 Rev 6 13/27
6 LNBH221 software description (same for both
section)
6.1 Interface protocol
The interface protocol comprises:
- A start condition (S)
- A chip address byte = hex 10 / 11 (the LSB bit determines read(=1)/write(=0) transmission)
- A sequence of data (1 byte + acknowledge)
- A stop condition (P)
ACK= Acknowledge
S= Start
P= Stop
R/W= Read/Write
6.2 System register (SR, 1 byte)
R,W= read and write bit
R= Read-only bit
All bits reset to 0 at power-on
6.3 Transmitted data (I²C bus write mode)
When the R/W bit in the chip address is set to 0, the main micropower can write on the
system register (SR) of the LNBH221 via I²C bus. Only 6 bits out of the 8 available can be
written by the micropower, since the remaining 2 are left to the diagnostic flags, and are
read-only.
Chip address Data
MSB LSB MSB LSB
S0001000R/WACK ACKP
MSB LSB
R, W R, W R, W R, W R, W R, W R R
PCL TTX TEN LLC VSEL EN OTF OLF
Obsolete Product(s) - Obsolete Product(s)
LNBH221 software description (same for both section) LNBH221
14/27 Doc ID 9913 Rev 6
X= don't care.
Values are typical unless otherwise specified.
6.4 Received data (I²C bus read mode)
The LNBH221 can provide to the master a copy of the system register information via I²C
bus in read mode. The read mode is master activated by sending the chip address with R/W
bit set to 1.
At the following master generated clocks bits, the LNBH221 issues a byte on the SDA data
bus line (MSB transmitted first).
At the ninth clock bit the MCU master can:
- acknowledge the reception, starting in this way the transmission of another byte from the
LNBH221;
- no acknowledge, stopping the read mode communication.
While the whole register is read back by the micropower, only the two read-only bits OLF
and OTF convey diagnostic informations about the LNBH221.
Values are typical unless otherwise specified.
Table 4. Truth table
PCL TTX TEN LLC VSEL EN OTF OLF Function
001XXV
OUT=13.25V, VUP=15.25V
011XXV
OUT=18V, VUP=20V
101XXV
OUT=14.25V, VUP=16.25V
111XXV
OUT=19.5V, VUP=21.5V
0 1 X X 22 kHz tone is controlled by DSQIN pin
1 1 X X 22 kHz tone is ON, DSQIN pin disabled
01XX
VORX output is ON, output voltage controlled by VSEL
and LLC
1X 1XX
VOTX output is ON, 22 kHz controlled by DSQIN or TEN,
output voltage level controlled by VSEL and LLC
0 1 X X Pulsed (dynamic) current limiting is selected
1 1 X X Static current limiting is selected
X X X X X 0 X X Power blocks disabled
Table 5. Register
PCL ISEL TEN LLC VSEL EN OTF OLF Function
These bits are read exactly the same as
they were left after last write operation
0T
J<140°C, normal operation
1T
J>150°C, power block disabled
0I
OUT<IOMAX, normal operation
1I
OUT>IOMAX, overload protection triggered
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LNBH221 LNBH221 software description (same for both section)
Doc ID 9913 Rev 6 15/27
6.5 Power-on I²C interface reset
The I²C interface built in the LNBH221 is automatically reset at power on. As long as the
VCC stays below the under voltage lockout threshold (6.7 V typ.), the interface will not
respond to any I²C command and the system register (SR) is initialized to all zeroes, thus
keeping the power blocks disabled. Once the VCC rises above 7.3 V typ, the I²C interface
becomes operative and the SR can be configured by the main micropower. This is due to
500 mV of hysteresis provided in the UVL threshold to avoid false retriggering of the power-
on reset circuit.
6.6 Address pin
Connecting this pin to GND the chip I²C interface address is 0001000, but, it is possible to
choice among 4 different addresses simply setting this pin at 4 fixed voltage levels (see
Table 9 on page 17).
6.7 DiSEqC™ implementation
The LNBH221 helps the system designer to implement the bi-directional DiSEqC 2.0
protocol by allowing an easy PWK modulation/demodulation of the 22 kHz carrier. The PWK
data are exchanged between the LNBH221 and the main micropower using logic levels that
are compatible with both 3.3 and 5 V microcontrollers. This data exchange is made through
two dedicated pins, DSQIN and DSQOUT, in order to maintain the timing relationships
between the PWK data and the PWK modulation as accurate as possible. These two pins
should be directly connected to two I/O pins of the micropower, thus leaving to the resident
firmware the task of encoding and decoding the PWK data in accordance to the DiSEqC
protocol. Full compliance of the system to the specification is thus not implied by the bare
use of the LNBH221. The system designer should also take in consideration the bus
hardware requirements; that can be simply accomplished by the R-L termination connected
on the VOUT pins of the LNBH221, as shown in the Figure 4 on page 8. To avoid any losses
due to the R-L impedance during the tone transmission, the LNBH221 has dedicated output
(VOTX) that, in a DiSEqC 2.0 application, is connected after the filter and must be enabled
by setting the TTX SR bit HIGH only during the tone transmission (see DiSEqC 2.0
Application information on page 9). Unidirectional (1.x) DiSEqC and non-DiSEqC systems
normally don't need this termination, and the VOTX pin can be directly connected to the LNB
supply port of the tuner (see Figure 3: Application circuit for DiSEqC 1.x and output current
up to 500 mA on page 7). There is also no need of tone decoding, thus DETIN and
DSQOUT pins can be left unconnected and the tone is provided by the VOTX.
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Electrical characteristics LNBH221
16/27 Doc ID 9913 Rev 6
7 Electrical characteristics
TJ = 0 to 85 °C, EN = 1, TTX = 0/1, LLC=VSEL=TEN=PCL=0, DSQIN=LOW, VIN = 12 V,
IOUT = 50 mA, unless otherwise specified. See software description section for I²C access to
the system register.
Table 6. Electrical characteristics of each section (A and B)
Symbol Parameter Parameter Min. Typ. Max. Unit
VIN Supply voltage IOUT = 500 mA
TEN=VSEL=LLC=1 815V
IIN Supply current
EN=TEN=VSEL=LLC=1, No
Load 20 40 mA
EN=0 3.5 7
VOUT Output voltage IOUT = 500 mA
VSEL=1
LLC=0 17.3 18 18.7 V
LLC=1 18.7 19.5 20.3
VOUT Output voltage IO = 500 mA
VSEL=0
LLC=0 12.75 13.25 13.75 V
LLC=1 13.75 14.25 14.75
ΔVOUT Line regulation VIN =8 to 15V VSEL=0 5 40 mV
VSEL=1 5 60
ΔVOUT Load regulation VSEL = 0 or 1 IOUT = 50 to
500mA 200 mV
IMAX Output current limiting 500 750 mA
ISC Output short circuit current VSEL = 0 300 mA
VSEL = 1 200
tOFF
Dynamic overload protection
OFF time PCL=0, output shorted 900 ms
tON
Dynamic overload protection
ON time PCL=0, output shorted tOFF/1
0ms
fTONE Tone frequency TEN=1 20 22 24 kHz
ATONE Tone amplitude TEN=1 0.55 0.72 0.9 VPP
DTONE Tone duty cycle TEN=1 40 50 60 %
tr, tfTone rise and fall time TEN=1 5 8 15 µs
GEXTM External modulation gain ΔVOUT/ΔVEXTM, f = 10Hz to
50kHz, TTX=1 6
VEXTM
External modulation input
voltage AC Coupling, TTX=1 400 mVPP
ZEXTM External modulation impedance f = 10Hz to 50kHz 260 W
fSW
DC-DC converter switch
frequency 220 kHz
fDETIN
Tone detector frequency
capture range 0.4VPP sinewave 18 24 kHz
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LNBH221 Electrical characteristics
Doc ID 9913 Rev 6 17/27
VDETIN Tone detector input amplitude fIN=22 kHz sinewave 0.2 1.5 VPP
ZDETIN Tone detector input impedance 150 kΩ
VOL DSQOUT pin logic LOW Tone present, IOL=2mA 0.3 0.5 V
IOZ DSQOUT pin leakage current Tone absent, VOH = 6V 10 µA
VIL DSQIN input pin logic LOW 0.8 V
VIH DSQIN input pin logic HIGH 2 V
IIH DSQIN pin input current VIH = 5V 15 µA
IOBK Output backward current EN=0, VOBK = 18V -6 -15 mA
TSHDN Thermal shutdown threshold 150 °C
ΔTSHDN Thermal shutdown hysteresis 15 °C
Table 6. Electrical characteristics of each section (A and B) (continued)
Symbol Parameter Parameter Min. Typ. Max. Unit
Table 7. Gate and sense electrical characteristics (TJ = 0 to 85 °C, VIN = 12 V)
Symbol Parameter Parameter Min. Typ. Max. Unit
RDSON-L Gate LOW RDSON IGATE=-100mA 4.5 Ω
RDSON-H Gate LOW RDSON IGATE=100mA 4.5 Ω
VSENSE Current limit sense voltage 200 mV
Table 8. I²C electrical characteristics (TJ = 0 to 85 °C, VIN = 12 V)
Symbol Parameter Parameter Min. Typ. Max. Unit
VIL LOW level input voltage SDA, SCL 0.8 V
VIH HIGH level input voltage SDA, SCL 2 V
IIN Input current SDA, SCL, VIN= 0.4 to 4.5V -10 10 µA
VOL Low level output voltage SDA (open drain), IOL = 6mA 0.6 V
fMAX Maximum clock frequency SCL 500 kHz
Table 9. Address pin characteristics (TJ = 0 to 85 °C, VIN = 12 V)
Symbol Parameter Parameter Min. Typ. Max. Unit
VADDR-1 "0001000" addr pin voltage 0 0.7 V
VADDR-2 "0001001" addr pin voltage 1.3 1.7 V
VADDR-3 "0001010" addr pin voltage 2.3 2.7 V
VADDR-4 "0001011" addr pin voltage 3.3 5 V
VADDR-1 "0001000" addr pin voltage 0 0.7 V
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Thermal design notes LNBH221
18/27 Doc ID 9913 Rev 6
8 Thermal design notes
During normal operation, the LNBH221 device dissipates some power. At rated output
current of 500 mA on each section output, the voltage drop on both linear regulators lead to
a total dissipated power that is typically 2 W. The heat generated requires a suitable
heatsink to keep the junction temperature below the over-temperature protection threshold.
Assuming a 45 °C temperature inside the set-top-box case, the total RthJC has to be less
than 40 °C/W.
While this can be easily achieved using a through-hole power package that can be attached
to a small heatsink or to the metallic frame of the receiver, a surface mount power package
must rely on PCB solutions whose thermal efficiency is often limited. The simplest solution
is to use a large, continuous copper area of the GND layer to dissipate the heat coming from
the IC body.
Given for the PSO-36 package an RthJC equal to 2 °C/W, a maximum of 38 °C/W are left to
the PCB heatsink. This area can be the inner GND layer of a multi-layer PCB, or, in a dual
layer PCB, an unbroken GND area even on the opposite side where the IC is placed. In
figure 8, it is shown a suggested layout for the PSO-36 package with a dual layer PCB,
where the IC exposed pad connected to GND and the square dissipating area are thermally
connected through 32 vias holes, filled by solder. This arrangement, when L = 40 mm,
achieves an RthJA of about 28 °C/W.
Different layouts are possible, too. Basic principles, however, suggest to keep the IC and its
ground exposed pad approximately in the middle of the dissipating area; to provide as many
vias as possible; to design a dissipating area having a shape as square as possible and not
interrupted by other copper traces.
Figure 8. PowerSO-36 suggested PCB heatsink layout
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LNBH221 Typical performance characteristics (of each section)
Doc ID 9913 Rev 6 19/27
9 Typical performance characteristics (of each section)
TJ = 25 °C, unless otherwise specification.
Figure 9. Output voltage vs. temperature Figure 10. Output voltage vs. temperature
Figure 11. Output voltage vs. temperature Figure 12. Load regulation vs. temperature
Figure 13. Load regulation vs. temperature Figure 14. Supply current vs. temperature
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Typical performance characteristics (of each section) LNBH221
20/27 Doc ID 9913 Rev 6
Figure 15. Supply current vs. temperature Figure 16. Supply current vs. temperature
Figure 17. Dynamic overload protection ON
time vs. temperature
Figure 18. Dynamic overload protection OFF
time vs. temperature
Figure 19. Output current limiting vs.
temperature
Figure 20. Tone frequency vs. temperature
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LNBH221 Typical performance characteristics (of each section)
Doc ID 9913 Rev 6 21/27
Figure 21. Tone amplitude vs. temperature Figure 22. Tone duty cycle vs. temperature
Figure 23. Tone rise time vs. temperature Figure 24. Tone fall time vs. temperature
Figure 25. Under voltage lockout threshold vs.
temperature
Figure 26. Output backward current vs.
temperature
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Typical performance characteristics (of each section) LNBH221
22/27 Doc ID 9913 Rev 6
Figure 27. DC-DC converter efficiency vs.
temperature
Figure 28. Current limit sense voltage vs.
temperature
Figure 29. 22 kHz tone waveform Figure 30. DSQIN tone enable transient
response
VCC = 12 V, IO = 50 mA, EN = TEN = 1
VCC = 12 V, IO = 50 mA, EN=1, Tone enabled by DSQIN pin
Figure 31. DSQIN tone enable transient
response
Figure 32. DSQIN tone disable transient
response
VCC = 12 V, IO = 50 mA, EN=1, Tone enabled by DSQIN pin
VCC = 12 V, IO = 50 mA, EN=1, Tone enabled by DSQIN pin
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LNBH221 Package mechanical data
Doc ID 9913 Rev 6 23/27
10 Package mechanical data
In order to meet environmental requirements, ST offers these devices in different grades of
ECOPACK® packages, depending on their level of environmental compliance. ECOPACK®
specifications, grade definitions and product status are available at: www.st.com.
ECOPACK® is an ST trademark.
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Package mechanical data LNBH221
24/27 Doc ID 9913 Rev 6
Dim. mm. inch.
Min. Typ. Max. Min. Typ. Max.
A3.60 0.1417
a1 0.10 0.30 0.0039 0.0118
a23.30 0.1299
a3 0 0.10 0 0.0039
b0.22 0.38 0.0087 0.0150
c0.230.32 0.0091 0.0126
D (1) 15.80 16.00 0.6220 0.6299
D1 9.40 9.80 0.3701 0.3858
E13.90 14.50 0.5472 0.5709
E1 (1) 10.90 11.10 0.4291 0.4370
E2 2.90 0.1142
E35.86.2 0.2283 0.2441
e 0.65 0.0256
e311.05 0.4350
G 0 0.10 0.0000 0.0039
H 15.50 15.90 0.6102 0.6260
h 1.10 0.0433
L0.80 1.10 0.0315 0.0433
N 10° 10°
S0° 8°0° 8°
PowerSO-36 mechanical data
0096119/B
(1) “D and E1” do not include mold flash or protusions - Mold flash or protusions shall not exceed 0.15 mm (0.006”)
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LNBH221 Package mechanical data
Doc ID 9913 Rev 6 25/27
Dim.
mm. inch.
Min. Typ. Max. Min. Typ. Max.
A330 12.992
C 12.813.2 0.504 0.519
D 20.2 0.795
N60 2.362
T30.4 1.197
Ao 15.1 15.30.594 0.602
Bo 16.5 16.7 0.650 0.658
Ko 3.84.0 0.1490.157
Po 3.94.1 0.1530.161
P23.924.1 0.941 0.949
W23.7 24.30.933 0.957
Tape and reel PowerSO-36 mechanical data
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Revision history LNBH221
26/27 Doc ID 9913 Rev 6
11 Revision history
Table 10. Document revision history
Date Revision Changes
08-Apr-2005 4 Maturity changed.
01-Mar-2006 5 The Figure 3 and Figure 4 updated.
17-Apr-2009 6 Updated statement ECOPACK®.
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LNBH221
Doc ID 9913 Rev 6 27/27
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