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FAN6100Q Secondary-Side Constant Voltage and Constant Current Controller Compatible with Qualcomm(R) Quick Charge 2.0 Features Description Supports Qualcomm Quick Charge 2.0 Specification Secondary-Side Constant Voltage (CV) and Constant Current (CC) Regulation Built-in Charge-Pump Circuit for Low Output Voltage Operation Internal, Accurate, Adaptive CV/CC Reference Voltage Low-Value Current Sensing Resistor for High Efficiency Programmable Cable Voltage Drop Compensation Two Operational Transconductance Amplifiers with Open-Drain Type for Dual-Loop CV/CC Control Compatible with Fairchild's FAN501A Output Under-Voltage Protection Wide VIN Supply Voltage Range (R) Adaptive Secondary-Side Output Over-Voltage Protection through Photo-Coupler Low Quiescent Current Consumption in Green Mode < 850 A Available in 20-Pin 3 x 4 mm MLP Package The controller consists of two operational amplifiers for voltage and current loop regulation with adjustable reference voltage. The CC control loop also incorporates a current sense amplifier with gain of 10. Outputs of the CV and CC amplifiers are tied together in open drain configuration. The FAN6100Q enables power adaptor's output voltage adjustment if it detects a protocol capable powered device. It can be capable of outputting 5.0 V at the beginning, and then 9 V or 12 V to meet requirement of High-Voltage Dedicated Charging Port (HVDCP) power supply. If a non compliant powered device is detected, the controller disables output voltage adjustment to ensure safe operation with smart phone and tablets that support only 5 V. FAN6100Q also incorporates an internal charge pump circuit to maintain CC regulation down to power supply's output voltage, VBUS of 2 V without an external voltage supply to the IC. Programmable cable voltage drop compensation allows precise CV regulation at the end of a USB cable via adjusting one external resistor. The device is available in the 20-pin MLP 3 x 4 package. Applications The FAN6100Q is a integrated secondary side power (R) adaptor controller that is compatible with Qualcomm TM Quick Charge 2.0 Class A technology. It is designed for use in application that requires Constant Voltage (CV) and Constant Current (CC) regulation. Battery Chargers for quick charge application AC/DC Adapters for Portable Devices that Require CV/CC Control All trademarks are the property of their respective owners. Ordering Information Part Number Operating Temperature Range Package Packing Method FAN6100QMPX -40C to +125C 20-Lead, MLP, QUAD, JEDEC MO-220, 3 mm x 4 mm, 0.5 mm Pitch, Single DAP Tape & Reel (c) 2014 Fairchild Semiconductor Corporation FAN6100Q * Rev. 1.2 www.fairchildsemi.com FAN6100Q -- Secondary-Side CV/CC Controller Compatible with Qualcomm(R) Quick Charge 2.0 March 2015 VO D+ D- AC IN GND 8 7 U1 FAN501A 6 4 5 10 1 9 2 11 10 9 2 1 3 3 12 18 13 U2 FAN6100Q 19 15 17 14 16 6 5 4 8 20 7 Figure 1. Typical Application Internal Block Diagram OVP VIN CP CN VDD Voltage Magement with Charge Pump Mode Condition VIN-OVP 3.65/3.25V 6.4/6.2V Mode Condition Internal Bias 0.495V/0.37V VIN-UVP SFB VREF Cable Voltage Drop Compensation COMR Mode Condition VCVR IREF CSN AVCCR CSP VIN UVP Protection Multiplier Mode Condition BLD VCCR PGND Mode Communication Constant Current Mode Selection SGND QP QN DP DN Figure 2. Function Block Diagram (c) 2014 Fairchild Semiconductor Corporation FAN6100Q * Rev. 1.2 www.fairchildsemi.com 2 FAN6100Q -- Secondary-Side CV/CC Controller Compatible with Qualcomm(R) Quick Charge 2.0 Application Diagram FAN6100Q -- Secondary-Side CV/CC Controller Compatible with Qualcomm(R) Quick Charge 2.0 Marking Information F- Fairchild Logo Z: Assembly Plant Code X: Year Code Y: Week Code TT: Die Run Code T: Package Type (MP=MLP) M: Manufacture Flow Code ZXYTT 6100Q TM Figure 3.Top Mark Pin Configuration NC CN CP VDD 20 19 18 17 VIN 1 16 PGND BLD 2 15 QP OVP 3 14 QN IREF 4 13 DN SFB 5 12 DP VREF 6 11 SGND FAN6100Q 7 8 9 10 SGND COMR CSP CSN Figure 4. Pin Assignments (c) 2014 Fairchild Semiconductor Corporation FAN6100Q * Rev. 1.2 www.fairchildsemi.com 3 Pin # Name Description 1 VIN Input Voltage Detection. This pin is tied to output terminal of the power adaptor to monitor output voltage and supply internal charge pump circuit. 2 BLD Output Bleeder Current Setting. This pin connects to output terminal of the power adaptor via an external resistor to form an output discharging path when mode changes from high-output voltage to low-output voltage. 3 OVP Output Over-Voltage-Protection. This pin is used for adaptive output over-voltage-protection. Typically an opto-coupler is connected to this pin to generate pull-low protection signal. 4 IREF Reference Output Current Sensing Voltage. The voltage is the amplifying output current sensing voltage. This pin is tied to the internal CC loop amplifier positive terminal. 5 SFB Secondary-Side Feedback Signal. Common output terminal of the dual operational transconductance amplifiers with open drain operation. Typically an opto-coupler is connected to this pin to provide feedback signal to the primary-side PWM controller. 6 VREF Reference Output Voltage Sensing Voltage. This pin is used to sense the output voltage for CV regulation via resistor divider. It is tied to the internal CV loop amplifier positive terminal. 7 SGND Signal Ground. 8 COMR Programmable Cable-Drop Voltage Compensation. An external resistor is connected to this pin to adjust output voltage compensation weighting. 9 CSP Positive Terminal of Output Current Sensing Amplifier. This pin connects directly to the positive voltage terminal of the current sense resistor. CSP need to be tied to ground of power adaptor via short PCB trace. 10 CSN Negative Terminal of Output Current Sensing Amplifier. This pin connects directly to the negative voltage terminal of the current sense resistor. CSN need to be tied to negative terminal of output capacitor via short PCB trace. 11 SGND 12 DP Positive Terminal of Communication Interface. This pin is tied to the USB D+ data line input. 13 DN Negative Terminal of Communication Interface. This pin is tied to the USB D- data line input. 14 QN LSB Switch for Mode Selection of Output Current. 15 QP MSB Switch for Mode Selection of Output Current. 16 PGND 17 VDD 18 CP Positive Voltage Terminal of Charge Pump. 19 CN Negative Voltage Terminal of Charge Pump. An external capacitor is necessary to be connected between CP pin and CN pin. 20 NC No Connect Signal Ground. Power Ground. Power Supply. IC operating current is supplied through this pin. This pin is typically connected to an external VDD capacitor. (c) 2014 Fairchild Semiconductor Corporation FAN6100Q * Rev. 1.2 www.fairchildsemi.com 4 FAN6100Q -- Secondary-Side CV/CC Controller Compatible with Qualcomm(R) Quick Charge 2.0 Pin Definitions Stresses exceeding the absolute maximum ratings may damage the device. The device may not function or be operable above the recommended operating conditions and stressing the parts to these levels is not recommended. In addition, extended exposure to stresses above the recommended operating conditions may affect device reliability. The absolute maximum ratings are stress ratings only. Symbol Parameter Min. Max. Unit VVIN VIN Pin Input Voltage 20 V VBLD BLD Pin Input Voltage 20 V VOVP OVP Pin Input Voltage 20 V VSFB SFB Pin Input Voltage -0.3 20 V VIREF IREF Pin Input Voltage -0.3 6.0 V VVREF VREF Pin Input Voltage -0.3 6.0 V VCOMR COMR Pin Input Voltage -0.3 6.0 V VCSP CSP Pin Input Voltage -0.3 6.0 V VCSN CSN Pin Input Voltage -0.3 6.0 V VDP DP Pin Input Voltage -0.3 6.0 V VDN DN Pin Input Voltage -0.3 6.0 V VQN QN Pin Input Voltage -0.3 6.0 V VQP QP Pin Input Voltage -0.3 6.0 V VDD VDD Pin Input Voltage -0.3 6.0 V VCP CP Pin Input Voltage -0.3 6.0 V VCN CN Pin Input Voltage -0.3 6.0 V PD Power Dissipation (TA=25C) 0.88 W JA Thermal Resistance (Junction-to-Air) 110 C/W TJ Junction Temperature -40 +150 C Storage Temperature Range -40 +150 C +260 C TSTG TL ESD Lead Temperature, (Wave soldering or IR, 10 Seconds) Electrostatic Discharge Capability Human Body Model, JEDEC:JESD22_A114 2.0 Charged Device Model, JEDEC:JESD22_C101 2.0 kV Note: 1. All voltage values, except differential voltages, are given with respect to GND pin. Recommended Operating Conditions The Recommended Operating Conditions table defines the conditions for actual device operation. Recommended operating conditions are specified to ensure optimal performance. Fairchild does not recommend exceeding them or designing to Absolute Maximum Ratings. Symbol Parameter Min. Max. Unit Junction Temperature -40 +125 C VDD-OP VDD Operating Voltage 3.12 6.00 V VIN-OP VIN Operating Voltage 16 V TJ (c) 2014 Fairchild Semiconductor Corporation FAN6100Q * Rev. 1.2 www.fairchildsemi.com 5 FAN6100Q -- Secondary-Side CV/CC Controller Compatible with Qualcomm(R) Quick Charge 2.0 Absolute Maximum Ratings VIN=5 V or 9 V or 12 V at TJ = -40C to 125C unless noted. Symbol Parameter Conditions Min. Typ. Max. Unit VIN Section VIN-OP IIN-OP-5V IIN-OP-9V,12V IIN-Green IIN-ST Continuous Operating Voltage 16 V Operating Supply Current at 5 V VIN=5 V, VCSP=100 mV, VCSN=0V 2.4 3.2 mA Operating Supply Current Over 5 V (9 V, 12 V) VIN=12 V, VCSP=100 mV, VCSN=0 V 1.2 2.0 mA Green Mode Operating Supply Current VIN=5 V, VCSP=VCSN=0 V 850 1050 A Startup Current VIN=1 V, VCSP=100 mV, VCSN=0 V 15 A VIN-UVP-L-5V VIN Under-Voltage-Protection Enable Voltage at 5 V 2.35 2.50 2.65 V VIN-UVP-H-5V VIN Under-Voltage-Protection Disable Voltage at 5 V 2.85 3.00 3.15 V VIN-UVP-L-9V VIN Under-Voltage-Protection Enable Voltage at 9 V 6.50 6.75 7.00 V VIN-UVP-H-9V VIN Under-Voltage-Protection Disable Voltage at 9 V 7.40 7.65 7.90 V VIN-UVP-L-12V VIN Under-Voltage-Protection Enable Voltage at 12 V 8.70 9.00 9.30 V VIN-UVP-H-12V VIN Under-Voltage-Protection Disable Voltage at 12 V 9.85 10.20 10.55 V tD-VIN-UVP VIN Under-Voltage-Protection Debounce Time 10 15 20 ms VIN-EN-L Charge-Pump Enable Threshold Voltage 1.5 2.0 2.5 V VIN-CP Charge Pump Disable Threshold Voltage 6.20 6.40 6.60 V VIN-CP-Hys Hysteresis Voltage for Charge Pump Disable Threshold Voltage VIN-OVP-5V VIN Over-Voltage-Protection Voltage at 5 V 5.80 VIN-OVP-9V VIN Over-Voltage-Protection Voltage at 9 V 10.50 10.80 11.10 V VIN-OVP-12V VIN Over-Voltage-Protection Voltage at 12 V 14.00 14.40 14.80 V tD-VIN-OVP VIN Over-Voltage-Protection Debounce Time 0.20 6.00 V 6.20 V 16 28 40 s 3.50 3.65 3.80 V 3.12 3.25 3.38 V 120 125 130 kHz VDD Section VDD-ON Turn-on Threshold Voltage VDD-OFF Turn-off Threshold Voltage fS-CP (2) Charge Pump Switching Frequency CC Mode Selection Section QP/QN-VR QP/QN-FIX1.5A QP/QN-FIX2.0A QP/QN-CLPM tD_Mode QP/QN State for Variable CC Mode QP=0 and QN=0 QP/QN State for Fixative 1.5 A CC Mode QP=0 and QN=1 QP/QN State for Fixative 2.0 A CC Mode QP=1 and QN=0 QP/QN State for Current Limit Protection Mode QP=1 and QN=1 CC Mode Selection De-bounce Time 3.5 4.0 4.5 ms Continued on the following page... (c) 2014 Fairchild Semiconductor Corporation FAN6100Q * Rev. 1.2 www.fairchildsemi.com 6 FAN6100Q -- Secondary-Side CV/CC Controller Compatible with Qualcomm(R) Quick Charge 2.0 Electrical Characteristics VIN=5 V or 9 V or 12 V at TJ = -40C to 125C unless noted. Symbol Parameter Conditions Min. Typ. Max. Unit 9.7 10.0 10.3 Constant Current Sensing Section AV-CCR (3) Output Current Sensing Amplifier Gain V/V VCCR-VR-5V Reference Voltage for Constant Current Regulation at Variable CC 5 V Mode 1.155 1.200 1.245 V VCCR-VR-9V Reference Voltage for Constant Current Regulation at Variable CC 9 V Mode 0.920 0.960 1.000 V VCCR-VR-12V Reference Voltage for Constant Current Regulation at Variable CC 12 V Mode 0.685 0.715 0.745 V VCCR-FIX-1.5A Reference Voltage for Constant Current Regulation at Fixative 1.5 A CC Mode 0.835 0.870 0.905 V VCCR-FIX-1.5A-12V Reference Voltage for Constant Current Regulation at Fixative 1.5 A CC 12 V Mode 0.635 0.660 0.685 V VCCR-FIX-2.0A Reference Voltage for Constant Current Regulation at Fixative 2.0 A CC Mode 1.155 1.200 1.245 V VCCR-FIX-2.0A-12V Reference Voltage for Constant Current Regulation at Fixative 2.0 A CC 12 V Mode 0.865 0.900 0.935 V AV-CCR-Protection Constant Current Attenuator for Protection Mode AV-CCR-UVP Constant Current Attenuator for VIN Under-Voltage Protection 0.125 V/V 0.125 V/V VGreen-H Green Mode Disable Threshold Voltage 0.400 0.495 0.590 0.34 VGreen-L Green Mode Enable Threshold Voltage tGreen-BLANK Green Mode Blanking Time at Startup ZCSP,ZCSN Current Sensing Input Impedance (3) 0.37 0.40 40 V V ms M 4 Constant Voltage Sensing Section VCVR-5V Reference Voltage for Constant Voltage Regulation at 5 V 0.980 1.000 1.020 V VCVR-9V Reference Voltage for Constant Voltage Regulation at 9 V 1.765 1.800 1.835 V VCVR-12V Reference Voltage for Constant Voltage Regulation at 12 V 2.355 2.400 2.445 V Cable Drop Compensation Section KCOMR-CDC Design Parameter for Cable-Drop Voltage Compensation 0.90 1.00 1.10 A/V Constant Current Amplifier Section Gm-CC fP-CC RCC-IN-CC CC Amplifier Transconductance (3) (3) CC Amplifier Dominate Pole (3) CC Amplifier Input Resistor 8.50 3.5 S 10 kHz 13.75 19.00 k Constant Voltage Amplifier Section Gm-CV fP-CV IBias-IN-CV CV Amplifier Transconductance (3) 3.5 (3) CV Amplifier Dominate Pole CV Amplifier Input Bias Current S 10 (3) kHz 30 nA Continued on the following page... (c) 2014 Fairchild Semiconductor Corporation FAN6100Q * Rev. 1.2 www.fairchildsemi.com 7 FAN6100Q -- Secondary-Side CV/CC Controller Compatible with Qualcomm(R) Quick Charge 2.0 Electrical Characteristics VIN=5 V or 9 V or 12 V at TJ = -40C to 125C unless noted. Symbol Parameter Conditions Min. Typ. Max. Unit 700 mA 350 ms Output Bleeder Section (3) IBLD Output Bleeder Current tBLD Output Bleeder Current Discharging Time 100 290 320 Secondary-Side Feedback Section ISFB-Sink-MAX Maximum SFB Pin Sink Current (3) 2 mA 2 mA OVP Section IOVP-Sink-MAX Maximum OVP Pin Sink Current Qualcomm Protocol Section VDPL DP Low Level Threshold Voltage VDPH DP High Level Threshold Voltage VDNL DN Low Level Threshold Voltage VDNH DN High Level Threshold Voltage VSEL_REF BC1.2 Detection 0.23 0.25 0.27 V 1.94 2.00 2.06 V 0.30 0.35 0.40 V 1.94 2.00 2.06 V Output Voltage Selection Reference 1.8 2.0 2.2 V tBC1.2 DP and DN High Debounce Time 1.0 tDP_UNPLUG Unplug DP Low Debounce Time 20 tTOGGLE DN Low Debounce Time after BC1.2 Detection is Complete tV_CHANGE Mode Change Signal Detection Debounce Time tV_REQUEST Blanking Time after Mode Change Signal Detection is Complete RDP DP Resistance RDN DN Pull-Low Resistance BC1.2 Detection 20 40 40 1.5 S 60 ms 1 ms 60 ms 200 ms 300 500 700 k 14.25 19.53 24.80 k Notes: 2. Guaranteed for temperature range -5C ~85C. 3. Guaranteed by design. (c) 2014 Fairchild Semiconductor Corporation FAN6100Q * Rev. 1.2 www.fairchildsemi.com 8 FAN6100Q -- Secondary-Side CV/CC Controller Compatible with Qualcomm(R) Quick Charge 2.0 Electrical Characteristics Figure 5. VDD Turn-On Threshold Voltage (VDD-ON) vs. Temperature Figure 6. VDD Turn-Off Threshold Voltage (VDD-OFF) vs. Temperature Figure 7. Operating Current Under 5 V (IIN-OP-5V) vs. Temperature Figure 8. Operating Current Over 5 V (IIN-OP-9V,12V) vs. Temperature Figure 9. Reference Voltage for CC Regulation at Variable CC 5 V Mode (VCCR-VR-5V) vs. Temperature (c) 2014 Fairchild Semiconductor Corporation FAN6100Q * Rev. 1.2 Figure 10. Reference Voltage for CC Regulation at Variable CC 9 V Mode (VCCR-VR-9V) vs. Temperature www.fairchildsemi.com 9 FAN6100Q -- Secondary-Side CV/CC Controller Compatible with Qualcomm(R) Quick Charge 2.0 Typical Performance Characteristics Figure 11. Reference Voltage for CC Regulation at Figure 12. Reference Voltage for CC Regulation at Variable CC 12 V Mode (VCCR-VR-12V) vs. Temperature Fixative 1.5 A CC Mode (VCCR-FIX-1.5A) vs. Temperature Figure 13. Reference Voltage for CC regulation at Fixative 1.5 A CC 12 V Mode (VCCR-FIX-1.5A-12V) vs. Temperature Figure 14. Reference Voltage for CC Regulation at Fixative 2.0 A CC Mode (VCCR-FIX-2.0A) vs. Temperature Figure 15. Reference Voltage for CC Regulation at Fixative 2.0 A CC 12 V Mode (VCCR-FIX-2.0A-12V) vs. Temperature Figure 16. Reference Voltage for CV Regulation at 5.0 V (VCVR-5V) vs. Temperature (c) 2014 Fairchild Semiconductor Corporation FAN6100Q * Rev. 1.2 www.fairchildsemi.com 10 FAN6100Q -- Secondary-Side CV/CC Controller Compatible with Qualcomm(R) Quick Charge 2.0 Typical Performance Characteristics Figure 17.Reference Voltage for CV Regulation at 9 V (VCVR-9V) vs. Temperature Figure 18. Reference Voltage for CV Regulation at 12 V (VCVR-12V) vs. Temperature Figure 19. VIN OVP Voltage Under 5 V (VIN-OVP-5V) vs. Temperature Figure 20. VIN OVP Voltage at 9 V (VIN-OVP-9V) vs. Temperature Figure 21. VIN OVP Voltage at 12 V (VIN-OVP-12V) vs. Temperature Figure 22. VIN UVP Enable Voltage Under 5 V (VIN-UVP-L-5V) vs. Temperature (c) 2014 Fairchild Semiconductor Corporation FAN6100Q * Rev. 1.2 www.fairchildsemi.com 11 FAN6100Q -- Secondary-Side CV/CC Controller Compatible with Qualcomm(R) Quick Charge 2.0 Typical Performance Characteristics Figure 23. VIN UVP Disable Voltage Under 5 V (VIN-UVP-H-5V) vs. Temperature Figure 24. VIN UVP Enable Voltage at 9 V (VIN-UVP-L-9V) vs. Temperature Figure 25. VIN UVP Disable Voltage at 9 V (VIN-UVP-H-9V) vs. Temperature Figure 26. VIN UVP Enable Voltage at 12 V (VIN-UVP-L-12V) vs. Temperature Figure 27. VIN UVP Disable Voltage at 12 V (VIN-UVP-H-12V) Figure 28. Charge Pump Disable Threshold Voltage vs. Temperature (VIN-CP) vs. Temperature (c) 2014 Fairchild Semiconductor Corporation FAN6100Q * Rev. 1.2 www.fairchildsemi.com 12 FAN6100Q -- Secondary-Side CV/CC Controller Compatible with Qualcomm(R) Quick Charge 2.0 Typical Performance Characteristics Figure 29.DP Low Level Threshold Voltage (VDPL) vs. Temperature Figure 30.DN Low Level Threshold Voltage (VDNL) vs. Temperature Figure 31.DP High Level Threshold Voltage (VDPH) vs. Temperature Figure 32. DN High Level Threshold Voltage (VDNH) vs. Temperature Figure 33.Output Voltage Selection Reference (VSEL_REF) vs. Temperature (c) 2014 Fairchild Semiconductor Corporation FAN6100Q * Rev. 1.2 www.fairchildsemi.com 13 FAN6100Q -- Secondary-Side CV/CC Controller Compatible with Qualcomm(R) Quick Charge 2.0 Typical Performance Characteristics The integrated secondary-side power adaptor controller FAN6100Q which is compatible with Qualcomm(R) Quick TM Charge 2.0 Class A technology for quick charger application. The FAN6100Q enables power supply's output voltage adjustment if it detects a protocol capable mobile and tablet. When a compliant powered is detected, FAN6100Q will produce BC1.2 procedure then will permit receiving output voltage change signal from portable device by DP and DN pin signal. For TM Qualcomm(R) Quick Charge 2.0 Class A technology application, it can be capable of outputting 5.0 V at the beginning, and then 9 V or 12 V to meet class A requirement of HVDCP power supplies. These voltages are based on the capabilities of the downstream device. The downstream device requests an output voltage for the HVDCP power supply. If a non compliant powered device is detected, the controller disables adaptive output voltage to ensure safe operation with smart phone and tablets that support only 5 V. amplifiers for constant voltage (CV) and constant current (CC) regulation with adjustable voltage references. The constant voltage (CV) regulation is implemented in the same way as the conventional isolated power supply. The output voltage is sensed on the VREF pin via the resistor divider, RF1 and RF2 and compared with the internal reference voltage for constant voltage regulation (VCVR) to generate a CV compensation signal (COMV) on the SFB pin. The compensation signal is transferred to the primary-side using an opto-coupler and applied to the PWM comparator through attenuator Av to determine the duty cycle. The output voltage can be derived by setting R F1 and RF2, calculated by: VO VCVR The controller consists of two operational amplifiers for Constant Voltage (CV) and Constant Current (CC) regulation with adjustable references voltage. The CC control loop also incorporates a current sense amplifier with gain of 10. Outputs of the CV and CC amplifiers are tied together in open drain configuration. FAN6100Q also incorporates an internal charge pump circuit to maintain CC regulation down to the power supply's output voltage, VBUS of 2 V without an external voltage supply to the IC. Programmable cable voltage drop compensation allows precise CV regulation at the end of USB cable via adjusting one external resistor. RF 1 RF 2 RF 2 (1) Constant-Current Regulation Operation The constant current (CC) regulation is implemented with sensing the output current. The output current is sensed via current-sense resistor (RCS) connected between the CSP and CSN pins and placed on the output ground return path. The sensed signal is amplified by internal current sensing amplifier AV-CCR before the amplified current feedback signal is fed into the positive terminal of the internal operational amplifier and compared with the internal reference voltage for constant current regulation (VCCR) to generate a CC compensation signal (COMI) on the SFB pin. The compensation signal is transferred to the primary-side using an opto-coupler to the primary-side PWM controller. The constant current point (IO_CC) can be set by selecting the current sensing resistor as: Furthermore, protection functions of the FAN6100Q include adaptive VIN Over-Voltage Protection (VIN OVP) and adaptive VIN Under-Voltage Protection (VIN UVP). Constant-Voltage Regulation Operation I O _ CC Figure 34 shows the primary-side internal PWM control circuit of FAN501A and secondary side regulator circuit of FAN6100Q which consists of two operational 1 AV CCR VCCR RCS (2) Np:Ns Lm CO1 + VO - RL IREF CFC1 RFC1 VREF CFV1 CO2 RCS_SEC Gate S Q OSC R Q CSN RLED CLED Drv CSP RF1 IDS AV-CCR CS RCS_PRI SFB RFB COMV RFV1 - + - Av VCCR Rbias + 1/3 - Slope Compensation + COMI VSAW VEA.V VCVR FB RF2 CFB COPT Figure 34. Internal PWM Control Circuit (c) 2014 Fairchild Semiconductor Corporation FAN6100Q * Rev. 1.2 www.fairchildsemi.com 14 FAN6100Q -- Secondary-Side CV/CC Controller Compatible with Qualcomm(R) Quick Charge 2.0 Functional Description VSAW Table 2. Variable CC Mode Specifications Gate Output Voltage Rated Current COMI 5V 2.0 A COMV 9V 1.67 A OSC CLK 12 V 1.25 A CV Regulation CC Regulation For fixative 1.5 A CC Mode setting, it is fixative CC output 1.5 A except for 12 V mode. The QP should be connected to ground as a low-level signal and QN can be open to generate a high-level signal. The specifications are as follows: Figure 35. PWM Operation for CV and CC VEA is compared with an internal sawtooth waveform (VSAW ) by PWM comparators to determine the duty cycle. As seen in Figure 34, outputs of comparators is used as a reset signal of flip-flop to determine the MOSFET turn-off instant. The lower signal, either COMV or COMI, is transferred to the primary-side to determine the duty cycle, as shown in Figure 35. During CV regulation, COMV is transferred to the primary-side to determine the duty cycle while COMI is saturated to HIGH. During CC regulation, COMI is transferred to the primary-side to determine the duty cycle while COMV is saturated to HIGH. Table 3. Fixative 1.5A CC Mode Specifications Output Voltage 5V 9V 12 V Rated Current 1.5 A 1.1 A For fixative 2.0 A CC Mode setting, it is fixative CC output 2.0 A except for 12 V mode. The specifications are as follows: Green Mode Operation FAN6100Q has Green Mode operation with low quiescent current consumption (<850 A). During the Green Mode, the charge pump function is disabled to reduce power consumption. The FAN6100Q enters green mode when the amplified output current sensed signal is smaller than 0.37 V. If the amplified output current sensed signal increases to larger than 0.495 V, FAN6100Q leaves green mode and the charge pump function is enabled. Table 4. Fixative 2.0A CC Mode Specifications Output Voltage 5V 9V 12 V Rated Current 2.0 A 1.56 A Once protection mode has occurred, the output current is adjusted and modified by AV-CCR-Protection. The output current can be calculated as: Once FAN6100Q enters Green Mode, the operating current is also reduced from 2.4 mA to 850 A to minimize power consumption. It provides low power consumption by the green mode operation at no load. I O _ CC _ protection Constant Current Mode Selection V 1 CCR FIX 1.5 A AV CCR protection A V CCR RCS (3) FAN6100Q provides flexible output CC choice for a variety of power rating designs. The control signal is a logic level signal for constant current mode determined by QP and QN pins setting. The output constant current mode selection specifications are as follows: Table 1. Mode Descriptions and Settings Mode Description Mode Setting Variable CC Mode QP=0 and QN=0 Fixative 1.5 A CC Mode QP=0 and QN=1 Fixative 2.0 A CC Mode QP=1 and QN =0 (c) 2014 Fairchild Semiconductor Corporation FAN6100Q * Rev. 1.2 www.fairchildsemi.com 15 FAN6100Q -- Secondary-Side CV/CC Controller Compatible with Qualcomm(R) Quick Charge 2.0 For variable CC mode setting, it is variable output CC for each mode. The QP and QN should be connected to ground as low level signal. The variable output CC for each mode specifications are as follows: VEA FAN6100Q incorporates programmable cable voltage drop compensation function via adjusting one external resistor to maintain constant voltage regulation at end of the USB cable. During startup, the charge-pump circuit is enabled when VIN voltage is larger than 2 V and disabled after 40 ms from the VDD voltage reaches VDD-ON (3.65 V). The charge-pump circuit is used to boost the VDD voltage to maintain normal operation for the controller when output voltage is low. The charge-pump stage includes a Low Dropout (LDO) pre-regulator and a charge-pump circuit. The LDO pre-regulator regulates the VCLAMP voltage to 2.7 V and then boosts up the VDD voltage when VIN is lower than VIN-CP (6.4 V) and out of Green Mode. When VIN is greater than the value 6.2 V which subtract VIN-CP from VIN-CP-Hys or lower than VIN-CP (6.4 V) in Green Mode, the charge-pump circuit is disabled and the VIN voltage is fed directly to VDD. Figure 36 shows the internal block of the cable voltage drop compensation function. Output current information is obtained from the amplified current sensing voltage. Depending on the weighting of the external resistor, the current signal is modulated to offset the CV loop reference voltage, VCVR. Thus, output voltage is increased by this offset voltage on the CV loop reference to compensate for cable voltage drop. The external compensation resistor, RCOMR, can be calculated by: RCOMR R RF 2 1 1 Cable RF 1 RF 2 RCS AV CCR K COMRCDC The charge-pump circuit needs an external capacitor, CCP, typically 220 nF~1 F, as the energy storage element. To stabilize the operation of the clamping LDO stage, it is typical to use 1 F capacitor to keep the LDO loop stable. (4) where: RF1 and RF2 = output feedback resistor divider derived from Eq. (1); RCable = cable resistance; RCS = current sensing resistor derived from Eq. (2); KCOMR-CDC = cable compensation design parameter of the controller, which is 1.0 A/V; and AV-CCR When charge-pump circuit is disabled, the output capacitor supplies charging current to charge the holdup capacitor CVDD. The VDD voltage is clamped at 5.4 V by internal Zener diode when the charge-pump circuit is disabled. The CVDD typically 220 nF~1 F, as the energy storage element. VO CO1 RCS = derived from Eq. (2), 10 V/V. CN RCable CO1 VO_End RCS CSP CP VIN Voltage Magement with Charge Pump IO CVDD XAVCCR CSN VDD CCP Internal Bias 3.65V / 3.25V 0.495V/0.37V 6.4V / 6.2V AVCCR COMR Cable Voltage Drop Compensation RF1 RCOMR Figure 37. Supply Voltage Block VREF Output Bleeder Section RF2 VCVR For HVDCP power supply application, a discharge path on the output of the HVDCP power supply is necessary to ensure that a high output voltage level can transfer to a low output voltage level quickly during mode changes. This is especially critical under no-load condition where the natural decay rate of the output voltage is low. To enable output bleeder function when the mode changes from high output voltage to low output voltage can ensure short voltage transition time. Mode Condition Figure 36. Cable Voltage Drop Compensation Block Supply Voltage and Charge Pump Operation Figure 37 shows the supply voltage circuit, including VDD and the charge-pump circuit. FAN6100Q can withstand up to 20 V on the VIN pin and enable this pin to be connected directly to the output terminal of a power supply. It is typical to use about 100 resistor between the VIN pin and the output terminal of a power supply (c) 2014 Fairchild Semiconductor Corporation FAN6100Q * Rev. 1.2 Figure 38 shows the internal block of bleeder function. The FAN6100Q implements the output bleeder function to discharge the output voltage rapidly during mode changes. The BLD pin is connected to the output www.fairchildsemi.com 16 FAN6100Q -- Secondary-Side CV/CC Controller Compatible with Qualcomm(R) Quick Charge 2.0 and then connect 470 nF capacitor on the VIN pin if ESD immunity needs to be enhanced. Cable Voltage Drop Compensation VIN Under-Voltage-Protection Figure 40 shows the VIN under-voltage-protection (VIN UVP) block. The output current is reduced to protect the system at 5 V, 9 V and 12 V conditions when VIN UVP function is triggered. Once output voltage drops below VIN-UVP-L, the CC reference voltage VCCR is adjusted and modified by AV-CCR-UVP. The output current can be calculated as: I O _ CC The first step bleeder current is determined by internal constant current design, the type value is 240 mA. The second step Bleeder Discharging Current (IBLD) can be adjusted by external Bleeder Series Resistor (RBLD), it can be calculated as: I BLD VO RBLD 1 AV CCR VCCR AV CCRUVP RCS (6) CO1 VO_End RCS IO (5) IREF CSN CSP VIN XAVCCR where RBLD is bleeder resistor connected between the output side and the BLD pin. SFB IBLD Mode Condition VO Multiplier 5.1V ZD RBLD VCCR VIN-UVP VIN UVP Protection Mode Condition BLD Figure 40. VIN Under-Voltage Protection Block Mode ChangE Signal from high output voltage to low output voltage Protocol Communication FAN6100Q is compatible with Qualcom(R) Quick TM Charge 2.0 Class A technology which is capable of outputting 5 V at the beginning, and then 9 V or 12 V. FAN6100Q can compatible with USB BC1.2 specification and permit receiving output voltage change signal form portable device by DP and DN pin signal. Figure 38. Output Bleeder Function VIN Over-Voltage-Protection (OVP) Figure 39 shows the VIN OVP block, which is adaptive operated according to mode condition. Output voltage is sensed through VIN pin for OVP detection. Once output voltage rises to VIN-OVP by each mode and then VIN OVP is triggered, where VIN OVP occurs, the OVP pin is pulled down to ground through an internal switch until VDD-OFF (3.25 V) is reached. If portable device has detected as a HVDCP, FAN6100Q will allow to progress USB BC1.2 procedure. After complete BC1.2 procedure, the output voltage is determined by both DP & DN voltage. The voltage on DP & DN is show in Table 5. The detection voltage specifications are as follows: Table 5. DP & DN Voltage CO1 VO_End Detection Voltage RCS VIN OVP OVP Mode Condition VIN-OVP HVDCP Power Supply DP DN Output Voltage 0.6 V 0.6 V 12 V 3.3 V 0.6 V 9V 0.6 V 3.3 V Reserved 3.3 V 3.3 V Reserved 0.6 V GND 5V FAN6100Q complies with Qualcomm QC2.0 compliance guidance and meets all specification. UL Figure 39. VIN Over-Voltage-Protection Block (c) 2014 Fairchild Semiconductor Corporation FAN6100Q * Rev. 1.2 www.fairchildsemi.com 17 FAN6100Q -- Secondary-Side CV/CC Controller Compatible with Qualcomm(R) Quick Charge 2.0 voltage terminal as the discharging path. When the high-output voltage to low-output voltage mode change signal is initiated, an internal switch is turned on to discharge the output voltage. The switch stays on until tBLD-MAX is reached. The BLD pin can withstand up to 20 V and enable this pin to be connected directly to the output terminal of a HVDCP power supply, but the output voltage shall be not lower than 4.1 V at output voltage transition and short transition time consideration, it recommends adding 2-step bleeder circuit, which is one 5.1 V Zener diode and one resistance (RBLD), to avoid output voltage drop deeply. AC IN (c) 2014 Fairchild Semiconductor Corporation FAN6100Q * Rev. 1.2 U3 FOD817B C1,22mF/400V L2 10mH C2,22mF/400V 4 6 7 5 8 U1 FAN501A 10 18 D4 MMSZ5244B R25 10K Q2 MMBT2222A D1 MMSD3070 R11 8.25k R14/1.6, R15/1.6 C23 10mF 5 2 6 CY,100pF U3 FOD817B R29 1k D7, TSP20U60S C8 1nF R8 47k C9 3.3nF 16 17 19 18 3 C17 1nF R35 C19 470nF 7.5k R22 1k 5 9 2 4 8 20 U2 FAN6100Q 11 10 R21 1k R19/100m, R20/100m D2 1N4148WS C20,1nF C13 47nF R30 1k C10,1mF C11,1mF ZD1,6.2V C16,330mF C7 20pF Q1 FCU900N60Z D6 FFM107 C3, 1nF/1kV R16 100 R9 62K R13 47 R3 0 R2 300k 7 R18 18 7 1 6 14 15 13 12 C14 470nF R24,51k C4 22mF 3 2 9 1 R7,49.9k R1,49.9k 1 EPC1716 TX1 C15,330mF R27 15k TH1 SCK053 F1 2A/250V BR1 MDB10SV L1 330mH ZD2,5.1V R31,91k C6, 470pF R32 30.1k R33 7.32k C18 6.8nF GND D+ D- VO FAN6100Q -- Secondary-Side CV/CC Controller Compatible with Qualcomm(R) Quick Charge 2.0 Typical Application Circuit Figure 41. Schematic of Typical Application Circuit www.fairchildsemi.com Core: EPC-1716 Bobbin: EPC-1716 1 3 S 1/2 Primary Winding ( 0.2x1) E Shielding ( 0.025x1) GND 5 6 7 S GND 5 4 GND 5 S1 S2 3 Drain 2 E Secondary Winding ( 0.7x1) E1 E2 Auxiliary Winding + Shielding ( 0.15) Primary Winding ( 0.2x1) S BOBBIN Figure 42. Transformer Diagram Terminal Isolation Layer Winding Wire Turns Start Pin End Pin Turns NP-2 3 1 0.2 mmx1 26 2 Copper Shielding 5 Open Copper Foil 0.025 mm 1 2 Ns 7 6 0.7 mmx1 6 2 Na 4 5 0.15 mmx1 11 2 Na-Shield 5 Open 0.15 mmx1 11 2 NP-1 2 3 0.2 mmx1 34 2 Bobbin - EPC1716 Inductance 1-2 600 H 5% 100 kHz Effective Leakage 1-2 <30 H Maximum Short Other Pin (c) 2014 Fairchild Semiconductor Corporation FAN6100Q * Rev. 1.2 www.fairchildsemi.com 19 FAN6100Q -- Secondary-Side CV/CC Controller Compatible with Qualcomm(R) Quick Charge 2.0 Transformer Specification 3.00 0.10 C A 20 B 2X 3.50 1.80 17 0.60(20X) 16 1 4.50 4.00 2.80 3.90 6 0.10 C TOP VIEW 2X 11 (0.25)4X 0.50 7 10 0.30(20X) RECOMMENDED LAND PATTERN 0.10 C 0.08 C SIDE VIEW C NOTES: 7 (0.60) 4X 10 6 11 16 1 (0.60) 4X PIN#1 IDENT 0.50 20 BOTTOM VIEW 17 0.10 0.05 C A B C A. DOES NOT FULLY CONFORMS TO JEDEC REGISTRATION MO-220. B. DIMENSIONS ARE IN MILLIMETERS. C. DIMENSIONS AND TOLERANCES PER ASME Y14.5M, 2009. D. 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