THS4502
THS4503
SLOS352D − APRIL 2002 − REVISED JANUARY 2004
WIDEBAND, LOW-DISTORTION FULLY DIFFERENTIAL AMPLIFIERS
DGK−8DGN−8 D−8
FEATURES
DFully Differential Architecture
DBandwidth: 370 MHz
DSlew Rate: 2800 V/µs
DIMD3: −95 dBc at 30 MHz
DOIP3: 51 dBm at 30 MHz
DOutput Common-Mode Control
DWide Power Supply Voltage Range: 5 V, ±5 V,
12 V, 15 V
DCentered Input Common-Mode Range
DPower-Down Capability (THS4502)
DEvaluation Module Available
DESCRIPTION
The THS4502 and THS4503 are high-performance fully
differential amplifiers from Texas Instruments. The
THS4502, featuring power-down capability, and the
THS4503, without power-down capability, set new
performance standards for fully differential amplifiers
with unsurpassed linearity, supporting 14-bit operation
through 40 MHz. Package options include the 8-pin
SOIC and the 8-pin MSOP with PowerPAD for a
smaller footprint, enhanced ac performance, and
improved thermal dissipation capability.
APPLICATIONS
DHigh Linearity Analog-to-Digital Converter
Preamplifier
DWireless Communication Receiver Chains
DSingle-Ended to Differential Conversion
DDifferential Line Driver
DActive Filtering of Differential Signals
1
2
3
4
8
7
6
5
VIN− VIN+
VOCM
VS+
VOUT+
PD
VS−
VOUT−
RELATED DEVICES
DEVICE(1) DESCRIPTION
THS4500/1 370 MHz, 2800 V/µs, VICR Includes VS−
THS4502/3 370 MHz, 2800 V/µs, Centered VICR
THS4120/1 3.3 V, 100 MHz, 43 V/µs, 3.7 nV√Hz
THS4130/1 ±15 V, 150 MHz, 51 V/µs, 1.3 nV√Hz
THS4140/1 ±15 V, 160 MHz, 450 V/µs, 6.5 nV√Hz
THS4150/1 ±15 V, 150 MHz, 650 V/µs, 7.6 nV√Hz
(1) Even numbered devices feature power-down capability
APPLICATION CIRCUIT DIAGRAM
f − Frequency − MHz
−80
−92
0204060
− Third-Order Intermodulation Distortion − dBc
−74
THIRD-ORDER INTERMODULATION
DISTORTION
−62
80 100
−68
−86
−98
12
10
14
16
IMD3
Bits
VS
392 Ω
+
−
−
+800 Ω
5 V
−5 V
VOUT
392 Ω
402 Ω
56.2 Ω
50 Ω374 Ω
VOCM
2.5 V
−
+−
+
VOCM 14 Bit/80 MSps
IN
IN
5 V
Vref
5 V
−5 V
VS
0.1 µF 10 µF
0.1 µF 10 µF
THS4502
392 Ω
10 pF
1 µF
56.2 ΩADC
374 Ω
50 Ω
402 Ω
392 Ω
10 pF
24.9 Ω
24.9 Ω
PowerPAD is a trademark of Texas Instruments.
UNLESS OTHERWISE NOTED this document contains PRODUCTION DATA
information current as of publication date. Products conform to specifications per
the terms of Texas Instruments standard warranty. Production processing does
not necessarily include testing of all parameters.
Please b e aware that an important notice concerning availability, standard warranty , and use in critical applications of Texas Instruments
semiconductor products and disclaimers thereto appears at the end of this data sheet.
www.ti.com
Copyright 2002−2004, Texas Instruments Incorporated
THS4502
THS4503
SLOS352D − APRIL 2002 − REVISED JANUARY 2004
www.ti.com
2
ABSOLUTE MAXIMUM RATINGS
over o p e r a t i n g f ree-air temperature range unless otherwise noted(1)
UNIT
Supply voltage, VS16.5 V
Input voltage, VI±VS
Output current, IO (2) 150 mA
Differential input voltage, VID 4 V
Continuous power dissipation See Dissipation Rating Table
Maximum junction temperature, TJ (3) 150°C
Maximum junction temperature, continuous
operation, long term reliability TJ (4) 125°C
Operating free-air C suffix 0°C to 70°C
Operating free-air
temperature range, TAI suffix −40°C to 85°C
Storage temperature range, Tstg −65°C to 150°C
Lead temperature
1,6 mm (1/16 inch) from case for 10
seconds 300°C
HBM 4000 V
ESD ratings: CDM 1000 V
ESD ratings: MM 100 V
(1) Stresses above these ratings may cause permanent damage.
Exposure to absolute maximum conditions for extended periods
may degrade device reliability. These are stress ratings only, and
functional operation of the device at these or any other conditions
beyond those specified is not implied.
(2) The THS450x may incorporate a PowerPAD on the underside of
the chip. This acts as a heatsink and must be connected to a
thermally dissipative plane for proper power dissipation. Failure
to do so may result in exceeding the maximum junction
temperature which could permanently damage the device. See TI
technical brief SLMA002 for more information about utilizing the
PowerPAD thermally enhanced package.
(3) The absolute maximum temperature under any condition is
limited by the constraints of the silicon process.
(4) The maximum junction temperature for continuous operation is
limited by package constraints. Operation above this temperature
may result in reduced reliability and/or lifetime of the device.
This integrated circuit can be damaged by ESD. Texas
Instruments recommends that all integrated circuits be
handled with appropriate precautions. Failure to observe
proper handling and installation procedures can cause damage.
ESD damage can range from subtle performance degradation to
complete device failure. Precision integrated circuits may be more
susceptible to damage because very small parametric changes could
cause the device not to meet its published specifications.
PACKAGE DISSIPATION RATINGS
θ θ (1) POWER RATING(2)
PACKAGE
θ
JC
(°C/W)
θ
JA
(°C/W) TA ≤ 25°C TA = 85°C
D (8 pin) 38.3 97.5 1.02 W 410 mW
DGN (8 pin) 4.7 58.4 1.71 W 685 mW
DGK (8 pin) 54.2 260 385 mW 154 mW
(1) This data was taken using the JEDEC standard High-K test PCB.
(2) Power rating is determined with a junction temperature of 125°C.
This is the point where distortion starts to substantially increase.
Thermal management of the final PCB should strive to keep the
junction temperature at or below 125°C for best performance and
long term reliability.
RECOMMENDED OPERATING CONDITIONS
MIN NOM MAX UNIT
Dual supply ±5±7.5
Supply voltage Single supply 4.5 5 15 V
Operating free- C suf fix 0 70
°
air temperature,
TAI suffix −40 85 °C
PACKAGE/ORDERING INFORMATION ORDERABLE PACKAGE AND NUMBER
TEMPERATURE PLASTIC
SMALL OUTLINE
PLASTIC MSOP(1)
PowerPAD PLASTIC MSOP(1)
SMALL OUTLINE
(D) (DGN) SYMBOL (DGK) SYMBOL
° °
THS4502CD THS4502CDGN BCG THS4502CDGK ATX
0°C to 70°CTHS4503CD THS4503CDGN BCK THS4503CDGK ATY
° °
THS4502ID THS4502IDGN BCI THS4502IDGK ASX
−40°C to 85°CTHS4503ID THS4503IDGN BCL THS4503IDGK ASY
(1) All packages are available taped and reeled. The R suffix standard quantity is 2500. The T suffix standard quantity is 250 (e.g., THS4502DT).
THS4502
THS4503
SLOS352D − APRIL 2002 − REVISED JANUARY 2004
www.ti.com
3
PIN ASSIGNMENTS
THS4503
(TOP VIEW)
VIN−1
2
3
4
8
7
6
5
VOCM
VS+
VOUT+
VIN+
VS−
VOUT−
PD
D, DGN, DGK
THS4502
(TOP VIEW) D, DGN, DGK
VIN−1
2
3
4
8
7
6
5
VOCM
VS+
VOUT+
VIN+
VS−
VOUT−
NC
ELECTRICAL CHARACTERISTICS VS = ±5 V
Rf = Rg = 499 Ω, RL = 800 Ω, G = +1, Single-ended input unless otherwise noted.
THS4502 AND THS4503
TYP OVER T E M P E R ATURE MIN/
PARAMETER TEST CONDITIONS
25°C 25°C0°C to
70°C−40°C to
85°CUNITS
MIN/
TYP/
MAX
AC PERFORMANCE G = +1, PIN= −20 dBm, Rf = 392 Ω370 MHz Typ
G = +2, PIN= −30 dBm, Rf = 1 kΩ175 MHz Typ
Small-signal bandwidth G = +5, PIN= −30 dBm, Rf = 1.3 kΩ70 MHz Typ
G = +10, PIN = −30 dBm, Rf = 1.3 kΩ30 MHz Typ
Gain-bandwidth product G > +10 300 MHz Typ
Bandwidth for 0.1dB flatness PIN = −20 dBm 150 MHz Typ
Large-signal bandwidth VP = 2 V 220 MHz Typ
Slew rate 4 VPP Step 2800 V/µsTyp
Rise time 2 VPP Step 0.8 ns Typ
Fall time 2 VPP Step 0.6 ns Typ
Settling time to 0.01% VO = 4 VPP 8.3 ns Typ
0.1% VO = 4 VPP 6.3 ns Typ
Harmonic distortion G = +1, VO = 2 VPP Typ
f = 8 MHz −83 dBc Typ
2nd harmonic f = 30 MHz −74 dBc Typ
f = 8 MHz −97 dBc Typ
3rd harmonic f = 30 MHz −78 dBc Typ
Third-order intermodulation
distortion VO = 2VPP, fc = 30 MHz,
Rf = 392 Ω, 200 kHz tone spacing −94 dBc Typ
Third-order output intercept point fc = 30 MHz, Rf = 392 Ω,
Referenced to 50 Ω52 dBm Typ
Input voltage noise f > 1 MHz 6.8 nV/√Hz Typ
Input current noise f > 100 kHz 1.7 pA/√Hz Typ
Overdrive recovery time Overdrive = 5.5 V 75 ns Typ
DC PERFORMANCE
Open-loop voltage gain 55 52 50 50 dB Min
Input of fset voltage −1−4 / +2 −5 / +3 −6 / +4 mV Max
Average offset voltage drift ±10 ±10 µV/°CTyp
Input bias current 4 4.6 5 5.2 µA Max
Average bias current drift ±10 ±10 nA/°CTyp
Input of fset current 0.5 1 2 2 µA Max
THS4502
THS4503
SLOS352D − APRIL 2002 − REVISED JANUARY 2004
www.ti.com
4
ELECTRICAL CHARACTERISTICS VS = ±5 V (continued)
Rf = Rg = 499 Ω, RL = 800 Ω, G = +1, Single-ended input unless otherwise noted.
PARAMETER
THS4502 AND THS4503
TEST CONDITIONSPARAMETER MIN/
TYP/
MAX
OVER T E M P E R ATURETYP
TEST CONDITIONSPARAMETER MIN/
TYP/
MAX
UNITS
−40°C to
85°C
0°C to
70°C
25°C25°C
TEST CONDITIONS
Average offset current drift ±40 ±40 nA/°CTyp
INPUT
Common-mode input range ±4.0 ±3.7 ±3.4 ±3.4 V Min
Common-mode rejection ratio 80 74 70 70 dB Min
Input impedance 107 || 1 Ω || pF Typ
OUTPUT
Differential output voltage swing RL = 1 kΩ ±8±7.6 ±7.4 ±7.4 V Min
Differential output current drive RL = 20 Ω120 110 100 100 mA Min
Output balance error PIN = −20 dBm, f = 100 kHz −58 dB Typ
Closed-loop output impedance
(single-ended) f = 1 MHz 0.1 ΩTyp
OUTPUT COMMON-MODE VOLTAGE CONTROL
Small-signal bandwidth RL = 400 Ω180 MHz Typ
Slew rate 2 VPP step 87 V/µsTyp
Minimum gain 1 0.98 0.98 0.98 V/V Min
Maximum gain 1 1.02 1.02 1.02 V/V Max
Common-mode of fset voltage +2 −1.6/+6.8 −3.6/+8.8 −4.6/+9.8 mV Max
Input bias current VOCM = 2.5 V 100 150 170 170 µA Max
Input voltage range ±4±3.7 ±3.4 ±3.4 V Min
Input impedance 25 || 1 kΩ || pF Typ
Maximum default voltage VOCM left floating 0 0.05 0.10 0.10 V Max
Minimum default voltage VOCM left floating 0−0.05 −0.10 −0.10 V Min
POWER SUPPLY
Specified operating voltage ±5±8.25 ±8.25 ±8.25 V Max
Maximum quiescent current 23 28 32 34 mA Max
Minimum quiescent current 23 18 14 12 mA Min
Power supply rejection (±PSRR) 80 76 73 70 dB Min
POWER DOWN (THS4502 ONLY)
Enable voltage threshold Device enabled ON above –2.9 V −2.9 V Min
Disable voltage threshold Device disabled OFF below –4.3 V −4.3 V Max
Power-down quiescent current 800 1000 1200 1200 µA Max
Input bias current 200 240 260 260 µA Max
Input impedance 50 || 1 kΩ || pF Typ
Turnon time delay 1000 ns Typ
Turnoff time delay 800 ns Typ
THS4502
THS4503
SLOS352D − APRIL 2002 − REVISED JANUARY 2004
www.ti.com
5
ELECTRICAL CHARACTERISTICS VS = 5 V
Rf = Rg = 499 Ω, RL = 800 Ω, G = +1, Single-ended input unless otherwise noted.
THS4502 AND THS4503
TYP OVER T E M P E R ATURE MIN/
PARAMETER TEST CONDITIONS
25°C 25°C0°C to
70°C−40°C to
85°CUNITS
MIN/
TYP/
MAX
AC PERFORMANCE G = +1, PIN = −20 dBm, Rf = 392 Ω320 MHz Typ
G = +2, PIN = −30 dBm, Rf = 1 kΩ160 MHz Typ
Small-signal bandwidth G = +5, PIN = −30 dBm, Rf = 1.3 kΩ60 MHz Typ
G = +10, PIN = −30 dBm, Rf = 1.3 kΩ30 MHz Typ
Gain-bandwidth product G > +10 300 MHz Typ
Bandwidth for 0.1 dB flatness PIN = −20 dBm 180 MHz Typ
Large-signal bandwidth VP = 1 V 200 MHz Typ
Slew rate 2 VPP Step 1300 V/µsTyp
Rise time 2 VPP Step 0.6 ns Typ
Fall time 2 VPP Step 0.8 ns Typ
Settling time to 0.01% VO = 2 V Step 13.1 ns Typ
0.1% VO = 2 V Step 8.3 ns Typ
Harmonic distortion VO = 2 VPP Typ
f = 8 MHz, −81 dBc Typ
2nd harmonic f = 30 MHz −60 dBc Typ
f = 8 MHz −74 dBc Typ
3rd harmonic f = 30 MHz −62 dBc Typ
Input voltage noise f > 1 MHz 6.8 nV/√Hz Typ
Input current noise f > 100 kHz 1.6 pA/√Hz Typ
Overdrive recovery time Overdrive = 5.5 V 75 ns Typ
DC PERFORMANCE
Open-loop voltage gain 54 51 49 49 dB Min
Input of fset voltage −0.6 −3.6/+2.4 −4.6/+3.4 −5.6/+4.4 mV Max
Average offset voltage drift ±10 ±10 µV/°CTyp
Input bias current 4 4.6 5 5.2 µA Max
Average bias current drift ±10 ±10 nA/°CTyp
Input of fset current 0.5 0.7 1.2 1.2 µA Max
Average offset current drift ±20 ±20 nA/°CTyp
INPUT
Common-mode input range 1 / 4 1.3 / 3.7 1.6 / 3.4 1.6 / 3.4 V Min
Common-mode rejection ratio 80 74 70 70 dB Min
Input Impedance 107 || 1 Ω || pF Typ
OUTPUT
Differential output voltage swing RL = 1 kΩ, Referenced to 2.5 V ±3.3 ±2.8 ±2.6 ±2.6 V Min
Output current drive RL = 20 Ω100 90 80 80 mA Min
Output balance error PIN = −20 dBm, f = 100 kHz −58 dB Typ
Closed-loop output impedance
(single-ended) f = 1 MHz 0.1 ΩTyp
THS4502
THS4503
SLOS352D − APRIL 2002 − REVISED JANUARY 2004
www.ti.com
6
ELECTRICAL CHARACTERISTICS VS = 5 V
Rf = Rg = 499 Ω, RL = 800 Ω, G = +1, Single-ended input unless otherwise noted.
THS4502 AND THS4503
TYP OVER T E M P E R ATURE
PARAMETER TEST CONDITIONS
25°C 25°C0°C to
70°C−40°C to
85°CUNITS MIN/
MAX
OUTPUT COMMON-MODE VOLTAGE CONTROL
Small-signal bandwidth RL = 400 Ω180 MHz Typ
Slew rate 2 VPP Step 80 V/µsTyp
Minimum gain 1 0.98 0.98 0.98 V/V Min
Maximum gain 1 1.02 1.02 1.02 V/V Max
Common-mode of fset voltage 2−2.2/6.2 −4.2/8.2 −5.2/9.2 mV Max
Input bias current VOCM = 2.5 V 1 2 3 3 µA Max
Input voltage range 1/4 1.2/3.8 1.3/3.7 1.3/3.7 V Min
Input impedance 25 || 1 kΩ || pF Typ
Maximum default voltage VOCM left floating 2.5 2.55 2.6 2.6 V Max
Minimum default voltage VOCM left floating 2.5 2.45 2.4 2.4 V Min
POWER SUPPLY
Specified operating voltage 5 16.5 16.5 16.5 V Max
Maximum quiescent current 20 25 29 31 mA Max
Minimum quiescent current 20 16 12 10 mA Min
Power supply rejection (+PSRR) 75 72 69 66 dB Min
POWER DOWN (THS4502 ONLY)
Enable voltage threshold Device enabled ON above 2.1 V 2.1 V Min
Disable voltage threshold Device disabled OFF below 0.7 V 0.7 V Max
Power-down quiescent current 600 800 1200 1200 µA Max
Input bias current 100 125 140 140 µA Max
Input impedance 50 || 1 kΩ || pF Typ
Turnon time delay 1000 ns Typ
Turnoff time delay 800 ns Typ
THS4502
THS4503
SLOS352D − APRIL 2002 − REVISED JANUARY 2004
www.ti.com
7
TYPICAL CHARACTERISTICS
Table of Graphs (±5 V)
FIGURE
Small signal unity gain frequency response 1
Small signal frequency response 2
0.1 dB gain flatness frequency response 3
Harmonic distortion (single-ended input to differential output) vs Frequency 4, 6, 12, 14
Harmonic distortion (differential input to differential output) vs Frequency 5, 7, 13, 15
Harmonic distortion (single-ended input to differential output) vs Output voltage swing 8, 10, 16, 18
Harmonic distortion (differential input to differential output) vs Output voltage swing 9, 11, 17, 19
Harmonic distortion (single-ended input to differential output) vs Load resistance 20
Harmonic distortion (differential input to differential output) vs Load resistance 21
Third order intermodulation distortion (single-ended input to differential output) vs Frequency 22
Third order output intercept point vs Frequency 23
Slew rate vs Differential output voltage step 24
Settling time 25, 26
Large-signal transient response 27
Small-signal transient response 28
Overdrive recovery 29, 30
Voltage and current noise vs Frequency 31
Rejection ratios vs Frequency 32
Rejection ratios vs Case temperature 33
Output balance error vs Frequency 34
Open-loop gain and phase vs Frequency 35
Open-loop gain vs Case temperature 36
Input bias and of fset current vs Case temperature 37
Quiescent current vs Supply voltage 38
Input of fset voltage vs Case temperature 39
Common-mode rejection ratio vs Input common-mode range 40
Differential output current drive vs Case temperature 41
Harmonic distortion (single-ended and differential input to differential output) vs Output common-mode voltage 42
Small signal frequency response at VOCM 43
Output offset voltage at V OCM vs Output common-mode voltage 44
Quiescent current vs Power-down voltage 45
Turnon and turnoff delay times 46
Single-ended output impedance in power down vs Frequency 47
Power-down quiescent current vs Case temperature 48
Power-down quiescent current vs Supply voltage 49
THS4502
THS4503
SLOS352D − APRIL 2002 − REVISED JANUARY 2004
www.ti.com
8
TYPICAL CHARACTERISTICS
Table of Graphs (5 V)
FIGURE
Small signal unity gain frequency response 50
Small signal frequency response 51
0.1 dB gain flatness frequency response 52
Harmonic distortion (single-ended input to differential output) vs Frequency 53, 54, 61, 63
Harmonic distortion (differential input to differential output) vs Frequency 55, 56, 62, 64
Harmonic distortion (single-ended input to differential output) vs Output voltage swing 57, 58, 65, 67
Harmonic distortion (differential input to differential output) vs Output voltage swing 59, 60, 66, 68
Harmonic distortion (single-ended input to differential output) vs Load resistance 69
Harmonic distortion (differential input to differential output) vs Load resistance 70
Slew rate vs Differential output voltage step 71
Large-signal transient response 72
Small-signal transient response 73
Voltage and current noise vs Frequency 74
Rejection ratios vs Frequency 75
Rejection ratios vs Case temperature 76
Output balance error vs Frequency 77
Open-loop gain and phase vs Frequency 78
Open-loop gain vs Case temperature 79
Input bias and of fset current vs Case temperature 80
Quiescent current vs Supply voltage 81
Input of fset voltage vs Case temperature 82
Common-mode rejection ratio vs Input common-mode range 83
Output drive vs Case temperature 84
Harmonic distortion (single-ended and differential input) vs Output common-mode range 85
Small signal frequency response at VOCM 86
Output offset voltage vs Output common-mode voltage 87
Quiescent current vs Power-down voltage 88
Turnon and turnoff delay times 89
Single-ended output impedance in power down vs Frequency 90
Power-down quiescent current vs Case temperature 91
Power-down quiescent current vs Supply voltage 92
THS4502
THS4503
SLOS352D − APRIL 2002 − REVISED JANUARY 2004
www.ti.com
9
TYPICAL CHARACTERISTICS (±5 V Graphs)
Figure 1
−4
−3.5
−3
−2.5
−2
−1.5
−1
−0.5
0
0.5
1
0.1 1 10 100 1000
f − Frequency − MHz
Small Signal Unity Gain − dB
SMALL SIGNAL UNITY GAIN
FREQUENCY RESPONSE
Gain = 1
RL = 800 Ω
Rf = 392 Ω
PIN = −20 dBm
VS = ±5 V
Figure 2
−2
0
2
4
6
8
10
12
14
16
18
20
22
0.1 1 10 100 1000
f − Frequency − MHz
Small Signal Gain − dB
SMALL SIGNAL FREQUENCY RESPONSE
Gain = 10, Rf = 1.3 kΩ
Gain = 5, Rf = 1.3 kΩ
Gain = 2, Rf = 1 kΩ
RL = 800 Ω
PIN = −30 dBm
VS = ±5 V
Figure 3
−0.5
−0.4
−0.3
−0.2
−0.1
0
0.1
110 100 1000
Rf = 392 Ω
Rf = 499 Ω
Gain = 1
RL = 800 Ω
PIN = −20 dBm
VS = ±5 V
f − Frequency − MHz
0.1 dB Gain Flatness − dB
0.1 dB GAIN FLATNESS
FREQUENCY RESPONSE
Figure 4
−100
−90
−80
−70
−60
−50
−40
−30
−20
−10
0
0.1 1 10 100
HD2
HD3
Harmonic Distortion − dBc
HARMONIC DIST ORTION
vs
FREQUENCY
f − Frequency − MHz
Single-Ended Input to
Differential Output
Gain = 1
RL = 800 Ω
Rf = 499 Ω
VO = 1 VPP
VS = ±5 V
Figure 5
−100
−90
−80
−70
−60
−50
−40
−30
−20
−10
0
0.1 1 10 100
HD2
HD3
Harmonic Distortion − dBc
HARMONIC DISTORTION
vs
FREQUENCY
f − Frequency − MHz
Differential Input to
Differential Output
Gain = 1
RL = 800 Ω
Rf = 499 Ω
VO = 1 VPP
VS = ±5 V
Figure 6
−100
−90
−80
−70
−60
−50
−40
−30
−20
−10
0
0.1 1 10 100
HD2
HD3
Harmonic Distortion − dBc
HARMONIC DISTORTION
vs
FREQUENCY
f − Frequency − MHz
Single-Ended Input to
Differential Output
Gain = 1
RL = 800 Ω
Rf = 499 Ω
VO = 2 VPP
VS = ±5 V
Figure 7
−100
−90
−80
−70
−60
−50
−40
−30
−20
−10
0
0.1 1 10 100
HD2
HD3
Harmonic Distortion − dBc
HARMONIC DISTORTION
vs
FREQUENCY
f − Frequency − MHz
Differential Input to
Differential Output
Gain = 1
RL = 800 Ω
Rf = 499 Ω
VO = 2 VPP
VS = ±5 V
Figure 8
−100
−90
−80
−70
−60
−50
−40
−30
−20
−10
0
0 0.5 1 1.5 2 2.5 3 3.5 4 4.5 5 5.5 6
HD2
HD3
Harmonic Distortion − dBc
HARMONIC DISTORTION
vs
OUTPUT VOLTAGE SWING
VO − Output Voltage Swing − V
Single-Ended Input to
Differential Output
Gain = 1
RL = 800 Ω
Rf = 499 Ω
f= 8 MHz
VS = ±5 V
Figure 9
−100
−90
−80
−70
−60
−50
−40
−30
−20
−10
0
0 0.5 1 1.5 2 2.5 3 3.5 4 4.5 5 5.5 6
HD2
HD3
Harmonic Distortion − dBc
HARMONIC DISTORTION
vs
OUTPUT VOLTAGE SWING
VO − Output Voltage Swing − V
Differential Input to
Differential Output
Gain = 1
RL = 800 Ω
Rf = 499 Ω
f= 8 MHz
VS = ±5 V
THS4502
THS4503
SLOS352D − APRIL 2002 − REVISED JANUARY 2004
www.ti.com
10
TYPICAL CHARACTERISTICS (±5 V Graphs)
Figure 10
−100
−90
−80
−70
−60
−50
−40
−30
−20
−10
0
0123456
HD2
HD3
Harmonic Distortion − dBc
HARMONIC DISTORTION
vs
OUTPUT VOLTAGE SWING
VO − Output Voltage Swing − V
Single-Ended Input to
Differential Output
Gain = 1
RL = 800 Ω
Rf = 499 Ω
f= 30 MHz
VS = ±5 V
Figure 11
−100
−90
−80
−70
−60
−50
−40
−30
−20
−10
0
0123456
HD2
HD3
Harmonic Distortion − dBc
HARMONIC DISTORTION
vs
OUTPUT VOLTAGE SWING
Differential Input to
Differential Output
Gain = 1
RL = 800 Ω
Rf = 499 Ω
VO = 30 VPP
VS = ±5 V
VO − Output Voltage Swing − V
Figure 12
−100
−90
−80
−70
−60
−50
−40
−30
−20
−10
0
0.1 1 10 100
HD2
HD3
Harmonic Distortion − dBc
HARMONIC DISTORTION
vs
FREQUENCY
f − Frequency − MHz
Single-Ended Input to
Differential Output
Gain = 2
RL = 800 Ω
Rf = 499 Ω
VO = 1 VPP
VS = ±5 V
Figure 13
−100
−90
−80
−70
−60
−50
−40
−30
−20
−10
0.1 1 10 100
0
HD2
HD3
Harmonic Distortion − dBc
HARMONIC DISTORTION
vs
FREQUENCY
f − Frequency − MHz
Differential Input to
Differential Output
Gain = 1
RL = 800 Ω
Rf = 499 Ω
VO = 1 VPP
VS = ±5 V
Figure 14
−100
−90
−80
−70
−60
−50
−40
−30
−20
−10
0
0.1 1 10 100
HD2
HD3
Harmonic Distortion − dBc
HARMONIC DISTORTION
vs
FREQUENCY
f − Frequency − MHz
Single-Ended Input to
Differential Output
Gain = 2
RL = 800 Ω
Rf = 499 Ω
VO = 2 VPP
VS = ±5 V
Figure 15
−100
−90
−80
−70
−60
−50
−40
−30
−20
−10
0
0.1 1 10 100
HD2
HD3
Harmonic Distortion − dBc
HARMONIC DISTORTION
vs
FREQUENCY
f − Frequency − MHz
Differential Input to
Differential Output
Gain = 2
RL = 800 Ω
Rf = 499 Ω
VO = 2 VPP
VS = ±5 V
Figure 16
−100
−90
−80
−70
−60
−50
−40
−30
−20
−10
0
012345678910
HD2
HD3
Harmonic Distortion − dBc
HARMONIC DISTORTION
vs
OUTPUT VOLTAGE SWING
VO − Output Voltage Swing − V
Single-Ended Input to
Differential Output
Gain = 2
RL = 800 Ω
Rf = 1.3 kΩ
f= 8 MHz
VS = ±5 V
Figure 17
−100
−90
−80
−70
−60
−50
−40
−30
−20
−10
0
012345678910
HD2
HD3
Harmonic Distortion − dBc
HARMONIC DISTORTION
vs
OUTPUT VOLTAGE SWING
VO − Output Voltage Swing − V
Differential Input to
Differential Output
Gain = 2
RL = 800 Ω
Rf = 1.3 kΩ
f= 8 MHz
VS = ±5 V
Figure 18
−100
−90
−80
−70
−60
−50
−40
−30
−20
−10
0
012345678910
HD2
HD3
Harmonic Distortion − dBc
HARMONIC DISTORTION
vs
OUTPUT VOLTAGE SWING
VO − Output Voltage Swing − V
Single-Ended Input to
Differential Output
Gain = 2
RL = 800 Ω
Rf = 1.3 kΩ
f= 30 MHz
VS = ±5 V
THS4502
THS4503
SLOS352D − APRIL 2002 − REVISED JANUARY 2004
www.ti.com
11
TYPICAL CHARACTERISTICS (±5 V Graphs)
Figure 19
−100
−90
−80
−70
−60
−50
−40
−30
−20
−10
0
012345678910
HD2
HD3
Harmonic Distortion − dBc
HARMONIC DISTORTION
vs
OUTPUT VOLTAGE SWING
VO − Output Voltage Swing − V
Differential Input to
Differential Output
Gain = 2
RL = 800 Ω
Rf = 1.3 kΩ
f= 8 MHz
VS = ±5 V
Figure 20
−100
−90
−80
−70
−60
−50
−40
−30
−20
−10
0
0 400 800 1200 1600
HD2
HD3
Harmonic Distortion − dBc
HARMONIC DISTORTION
vs
LOAD RESISTANCE
RL − Load Resistance − Ω
Single-Ended Input to
Differential Output
Gain = 1
VO = 2 VPP
Rf = 499 Ω
f= 30 MHz
VS = ±5 V
Figure 21
−100
−90
−80
−70
−60
−50
−40
−30
−20
−10
0
0 400 800 1200 1600
HD2
HD3
Harmonic Distortion − dBc
HARMONIC DISTORTION
vs
LOAD RESISTANCE
RL − Load Resistance − Ω
Differential Input to
Differential Output
Gain = 1
VO = 2 VPP
Rf = 499 Ω
f= 30 MHz
VS = ±5 V
Figure 22
−100
−90
−80
−70
−60
−50
10 100
Third-Order Intermodulation Distortion − dBc
THIRD-ORDER INTERMODULATION
DISTORTION
vs
FREQUENCY
f − Frequency − MHz
Single-Ended Input to
Differential Output
Gain = 1
VO = 2 VPP
Rf = 392 Ω
VS = ±5 V
Tone Spacing = 200 kHz
Figure 23
40
30
20
15 0 102030405060
Third-Order Output Intersept Point − dBm
50
55
f − Frequency − MHz
THIRD-ORDER OUTPUT INTERCEPT
POINT
vs
FREQUENCY
60
70 80 90 100
45
35
25
Normalized to 200 Ω
Gain = 1
Rf = 392 Ω
VS = ± 5 V
Tone Spacing = 200 kHz
OIP3 RL= 800 Ω
Normalized to 50 Ω
Figure 24
0
500
1000
1500
2000
2500
3000
0 0.5 1 1.5 2 2.5 3 3.5 4
VO − Differential Output Voltage Step − V
SR − Slew Rate −
SLEW RATE
vs
DIFFERENTIAL OUTPUT VOLTAGE STEP
sµ
V/
Gain = 1
RL = 800 Ω
Rf = 499 Ω
f= 8 MHz
VS = ±5 V
Figure 25
−1.5
−1
−0.5
0
0.5
1
1.5
0 5 10 15 20
t − Time − ns
− Output Voltage − V
SETTLING TIME
VO
Gain = 1
RL = 800 Ω
Rf = 499 Ω
f= 1 MHz
VS = ±5 V
Rising Edge
Falling Edge
Figure 26
−2.5
−2
−1.5
−1
−0.5
0
0.5
1
1.5
2
2.5
0510 15 20
t − Time − ns
− Output Voltage − V
SETTLING TIME
VO
Gain = 1
RL = 800 Ω
Rf = 499 Ω
f= 1 MHz
VS = ±5 V
Rising Edge
Falling Edge
Figure 27
−3
−2
−1
0
1
2
3
−100 0 100 200 300 400 500
t − Time − ns
− Output Voltage − V
LARGE-SIGNAL TRANSIENT RESPONSE
VO
Gain = 1
RL = 800 Ω
Rf = 499 Ω
tr/tf = 300 ps
VS = ±5 V
THS4502
THS4503
SLOS352D − APRIL 2002 − REVISED JANUARY 2004
www.ti.com
12
TYPICAL CHARACTERISTICS (±5 V Graphs)
Figure 28
−0.4
−0.3
−0.2
−0.1
0
0.1
0.2
0.3
0.4
−100 0 100 200 300 400 500
t − Time − ns
− Output Voltage − V
SMALL-SIGNAL TRANSIENT RESPONSE
VO
Gain = 1
RL = 800 Ω
Rf = 499 Ω
tr/tf = 300 ps
VS = ±5 V
Figure 29
t − Time − µs
0
−1
−4
0 0.1 0.2 0.3 0.4 0.5 0.6
Single-Ended Output Voltage − V
1
2
OVERDRIVE RECOVERY
4
0.7 0.8 0.9 1
3
−3
−5
−2
5
0
−0.5
−2
0.5
1
2
1.5
−1.5
−2.5
−1
2.5
Gain = 4
RL = 800 Ω
Rf = 499 Ω
Overdrive = 4.5 V
VS = ±5 V
Figure 30
−6
−4
−2
0
2
4
6
0 0.1 0.2 0.3 0.4 0.5 0.6 0.7 0.8 0.9 1−3
−2
−1
0
1
2
3
t − Time − µs
Single-Ended Output Voltage − V
OVERDRIVE RECOVERY
− Input Voltage − VVI
Gain = 4
RL = 800 Ω
Rf = 499 Ω
Overdrive = 5.5 V
VS = ±5 V
Figure 31
1
10
100
0.01 0.1 1 10 100
Vn
In
f − Frequency − kHz
− Voltage Noise −
VOLTAGE AND CURRENT NOISE
vs
FREQUENCY
nV/ Hz
Vn
− Current Noise −pA/ Hz
In
1000 10 k
Figure 32
−10
0
10
20
30
40
50
60
70
80
90
0.1 1 10 100
Rejection Ratios − dB
REJECTION RATIOS
vs
FREQUENCY
f − Frequency − MHz
PSRR+
PSRR−CMMR
RL = 800 Ω
VS = ±5 V
Figure 33
0
10
20
30
40
50
60
70
80
90
100
−40−30−20−100 102030405060708090
Rejection Ratios − dB
REJECTION RATIOS
vs
CASE TEMPERATURE
Case Temperature − °C
PSRR+
PSRR−
CMMR
RL = 800 Ω
VS = ±5 V
Figure 34
−70
−60
−50
−40
−30
−20
−10
0
0.1 1 10 100
Output Balance Error − dB
OUTPUT BALANCE ERROR
vs
FREQUENCY
f − Frequency − MHz
PIN = −20 dBm
RL = 800 Ω
Rf = 499 Ω
VS = ±5 V
Figure 35
0
10
20
30
40
50
60
0.01 0.1 1 10 100 1000
−150
−120
−90
−60
−30
0
30
Open-Loop Gain − dB
OPEN-LOOP GAIN AND PHASE
vs
FREQUENCY
f − Frequency − MHz
PIN = −30 dBm
RL = 800 Ω
Rf = 100 kΩ
VS = ±5 V
Phase −
Gain
Phase
°
Figure 36
48
49
50
51
52
53
54
55
56
57
−40−30−20−100 102030405060708090
Open-Loop Gain − dB
OPEN-LOOP GAIN
vs
CASE TEMPERATURE
Case Temperature − °C
RL = 800 Ω
VS = ±5 V
THS4502
THS4503
SLOS352D − APRIL 2002 − REVISED JANUARY 2004
www.ti.com
13
TYPICAL CHARACTERISTICS (±5 V Graphs)
Figure 37
0
0.25
0.5
0.75
1
1.25
1.5
1.75
2
2.25
−40−30−20−100 102030405060708090
0.05
0.06
0.07
0.08
0.09
0.1
0.11
0.12
0.13
0.14
− Input Bias Current −
INPUT BIAS AND OFFSET CURRENT
vs
CASE TEMPERATURE
Case Temperature − °C
VS = ±5 V
− Input Offset Current −
IIB−
IIB Aµ
IOS Aµ
IIB+
IOS
Figure 38
0
5
10
15
20
25
30
35
0 0.5 1 1.5 2 2.5 3 3.5 4 4.5 5
VS − Supply Voltage − ±V
Quiescent Current − mA
QUIESCENT CURRENT
vs
SUPPLY VOLTAGE
TA = 85°C
TA = 25°C
TA = −40°C
Figure 39
0
0.5
1
1.5
2
2.5
−40−30−20−100 102030405060708090
Case Temperature − °C
− Input Offset Voltage − mV
INPUT OFFSET VOLTAGE
vs
CASE TEMPERATURE
VOS
VS = ±5 V
Figure 40
−10
0
10
20
30
40
50
60
70
80
90
100
110
−6−4−20246
Input Common-Mode Voltage Range − V
CMRR − Common-Mode Rejection Ratio − dB
COMMON-MODE REJECTION RATIO
vs
INPUT COMMON-MODE RANGE
VS = ±5 V
Figure 41
−150
−100
−50
0
50
100
150
200
−40−30−20−100 102030405060708090
Differential Output Current Drive − mA
DIFFERENTIAL OUTPUT CURRENT DRIVE
vs
CASE TEMPERATURE
Case Temperature − °C
VS = ±5 V Source
Sink
−100
−90
−80
−70
−60
−50
−40
−30
−20
−10
0
−3.5 −2.5 −1.5 −0.5 0.5 1.5 2.5 3.5
VOC − Output Common-Mode Voltage − V
Harmonic Distortion − dBc
HARMONIC DISTORTION
vs
OUTPUT COMMON-MODE VOLTAGE
HD2-SE
HD3-SE and Diff
Single-Ended and Differential
Input to Differential Output
Gain = 1, VO = 2 VPP
f= 8 MHz, Rf = 499 Ω
VS = ±5 V
HD2-Diff
Figure 42
Figure 43
−3
−2
−1
0
1
2
3
1 10 100 1000
SMALL SIGNAL FREQUENCY RESPONSE
AT VOCM
f − Frequency − MHz
Gain = 1
RL = 800 Ω
Rf = 499 Ω
PIN= −20 dBm
VS = ±5 V
Small Signal Frequency Response at VOCM − dB
Figure 44
−600
−400
−200
0
200
400
600
−5−4−3−2−1012345
VOC − Output Common-Mode Voltage − V
− Output Offset Voltage at
OUTPUT OFFSET VOLTAGE AT VOCM
vs
OUTPUT COMMON-MODE VOLTAGE
VOS VOCM− mV
Figure 45
−5
0
5
10
15
20
25
30
−5−4.5 −4−3.5 −3−2.5 −2−1.5 −1−0.5 0
Power-Down Voltage − V
Quiescent Current − mA
QUIESCENT CURRENT
vs
POWER-DOWN VOLTAGE
THS4502
THS4503
SLOS352D − APRIL 2002 − REVISED JANUARY 2004
www.ti.com
14
TYPICAL CHARACTERISTICS (±5 V Graphs)
Figure 46
−1
−2
−5
0 0.5 1 2
0
100.5101 102 103
−3
−6
−4
0
0.01
0.03
0.02
t − Time − ms
Powerdown Voltage Signal − V
TURNON AND TURNOFF DELAY TIMES
Quiescent Current − mA
1.5 2.5 3
Current
Figure 47
0
100
200
300
400
500
600
700
800
900
1000
1100
0.1 1 10 100 1000
− Single-Ended Output Impedance
SINGLE-ENDED OUTPUT IMPEDANCE
IN POWER DOWN
vs
FREQUENCY
ZO
f − Frequency − MHz
Gain = 1
RL = 800 Ω
Rf = 392 Ω
PIN = −1 dBm
VS = ±5 V
in Power Down −Ω
Figure 48
0
0.2
0.4
0.6
0.8
1
1.2
1.4
−40−30−20−100 102030405060708090
Power-Down Quiescent Current − mA
POWER-DOWN QUIESCENT CURRENT
vs
CASE TEMPERATURE
Case Temperature − °C
RL = 800 Ω
VS = ±5 V
Figure 49
0
100
200
300
400
500
600
700
800
900
1000
0 0.5 1 1.5 2 2.5 3 3.5 4 4.5 5
VS − Supply Voltage − ±V
Power-Down Quiescent Current −
POWER-DOWN QUIESCENT CURRENT
vs
SUPPLY VOLTAGE
Aµ
RL = 800 Ω
THS4502
THS4503
SLOS352D − APRIL 2002 − REVISED JANUARY 2004
www.ti.com
15
TYPICAL CHARACTERISTICS (5 V Graphs)
Figure 50
−4
−3
−2
−1
0
1
0.1 1 10 100 1000
f − Frequency − MHz
Small Signal Unity Gain − dB
SMALL SIGNAL UNITY GAIN
FREQUENCY RESPONSE
Gain = 1
RL = 800 Ω
Rf = 392 Ω
PIN = −20 dBm
VS = 5 V
Figure 51
−2
0
2
4
6
8
10
12
14
16
18
20
22
0.1 1 10 100 1000
f − Frequency − MHz
Small Signal Gain − dB
SMALL SIGNAL FREQUENCY RESPONSE
Gain = 10, Rf = 1.3 kΩ
Gain = 5, Rf = 1.3 kΩ
Gain = 2, Rf = 1 kΩ
RL = 800 Ω
PIN = −30 dBm
VS = 5 V
Figure 52
−0.5
−0.4
−0.3
−0.2
−0.1
0
0.2
110 100 1000
Rf = 392 Ω
Rf = 499 Ω
f − Frequency − MHz
0.1 dB Gain Flatness − dB
0.1 dB GAIN FLATNESS
FREQUENCY RESPONSE
Gain = 1
RL = 800 Ω
PIN = −20 dBm
VS = 5 V
0.1
Figure 53
−100
−90
−80
−70
−60
−50
−40
−30
−20
−10
0
0.1 1 10 100
HD2
HD3
Harmonic Distortion − dBc
HARMONIC DISTORTION
vs
FREQUENCY
f − Frequency − MHz
Single-Ended Input to
Differential Output
Gain = 1
RL = 800 Ω
Rf = 499 Ω
VO = 1 VPP
VS = 5 V
Figure 54
−100
−90
−80
−70
−60
−50
−40
−30
−20
−10
0
0.1 1 10 100
HD2
HD3
Harmonic Distortion − dBc
HARMONIC DISTORTION
vs
FREQUENCY
f − Frequency − MHz
Single-Ended Input to
Differential Output
Gain = 1
RL = 800 Ω
Rf = 499 Ω
VO = 2 VPP
VS = 5 V
Figure 55
−100
−90
−80
−70
−60
−50
−40
−30
−20
−10
0
0.1 1 10 100
HD2
HD3
Harmonic Distortion − dBc
HARMONIC DISTORTION
vs
FREQUENCY
f − Frequency − MHz
Differential Input to
Differential Output
Gain = 1
RL = 800 Ω
Rf = 499 Ω
VO = 1 VPP
VS = 5 V
Figure 56
−100
−90
−80
−70
−60
−50
−40
−30
−20
−10
0
0.1 1 10 100
HD2
HD3
Harmonic Distortion − dBc
HARMONIC DISTORTION
vs
FREQUENCY
f − Frequency − MHz
Differential Input to
Differential Output
Gain = 1
RL = 800 Ω
Rf = 499 Ω
VO = 2 VPP
VS = 5 V
Figure 57
−100
−90
−80
−70
−60
−50
−40
−30
−20
−10
0
0 0.5 1 1.5 2 2.5 3 3.5 4 4.5 5
HD2
HD3
Harmonic Distortion − dBc
HARMONIC DISTORTION
vs
OUTPUT VOLTAGE SWING
VO − Output Voltage Swing − V
Single-Ended Input to
Differential Output
Gain = 1
RL = 800 Ω
Rf = 499 Ω
f= 8 MHz
VS = ±5 V
Figure 58
−100
−90
−80
−70
−60
−50
−40
−30
−20
−10
0
0 0.5 1 1.5 2 2.5 3 3.5 4 4.5 5
HD2
HD3
Harmonic Distortion − dBc
HARMONIC DISTORTION
vs
OUTPUT VOLTAGE SWING
VO − Output Voltage Swing − V
Single-Ended Input to
Differential Output
Gain = 1
RL = 800 Ω
Rf = 499 Ω
f= 30 MHz
VS = 5 V
THS4502
THS4503
SLOS352D − APRIL 2002 − REVISED JANUARY 2004
www.ti.com
16
TYPICAL CHARACTERISTICS (5 V Graphs)
Figure 59
−100
−90
−80
−70
−60
−50
−40
−30
−20
−10
0
0 0.5 1 1.5 2 2.5 3 3.5 4 4.5 5
HD2
HD3
Harmonic Distortion − dBc
HARMONIC DISTORTION
vs
OUTPUT VOLTAGE SWING
VO − Output Voltage Swing − V
Differential Input to
Differential Output
Gain = 1
RL = 800 Ω
Rf = 499 Ω
f= 8 MHz
VS = 5 V
Figure 60
−100
−90
−80
−70
−60
−50
−40
−30
−20
−10
0
0 0.5 1 1.5 2 2.5 3 3.5 4 4.5 5
HD2
HD3
Harmonic Distortion − dBc
HARMONIC DISTORTION
vs
OUTPUT VOLTAGE SWING
VO − Output Voltage Swing − V
Differential Input to
Differential Output
Gain = 1
RL = 800 Ω
Rf = 499 Ω
f= 30 MHz
VS = 5 V
Figure 61
−100
−90
−80
−70
−60
−50
−40
−30
−20
−10
0
0.1 1 10 100
HD2
HD3
Harmonic Distortion − dBc
HARMONIC DISTORTION
vs
FREQUENCY
f − Frequency − MHz
Single-Ended Input to
Differential Output
Gain = 2
RL = 800 Ω
Rf = 499 Ω
VO = 1 VPP
VS = 5 V
Figure 62
−100
−90
−80
−70
−60
−50
−40
−30
−20
−10
0.1 1 10 100
0
HD2
HD3
Harmonic Distortion − dBc
HARMONIC DISTORTION
vs
FREQUENCY
f − Frequency − MHz
Differential Input to
Differential Output
Gain = 2
RL = 800 Ω
Rf = 499 Ω
VO = 1 VPP
VS = 5 V
Figure 63
−100
−90
−80
−70
−60
−50
−40
−30
−20
−10
0
0.1 1 10 100
HD2
HD3
Harmonic Distortion − dBc
HARMONIC DISTORTION
vs
FREQUENCY
f − Frequency − MHz
Single-Ended Input to
Differential Output
Gain = 2
RL = 800 Ω
Rf = 499 Ω
VO = 2 VPP
VS = 5 V
Figure 64
−100
−90
−80
−70
−60
−50
−40
−30
−20
−10
0.1 1 10 100
0
HD2
HD3
Harmonic Distortion − dBc
HARMONIC DISTORTION
vs
FREQUENCY
f − Frequency − MHz
Differential Input to
Differential Output
Gain = 2
RL = 800 Ω
Rf = 499 Ω
VO = 2 VPP
VS = 5 V
Figure 65
−100
−90
−80
−70
−60
−50
−40
−30
−20
−10
0
0 0.5 1 1.5 2 2.5 3 3.5 4 4.5 5
HD2
HD3
Harmonic Distortion − dBc
HARMONIC DISTORTION
vs
OUTPUT VOLTAGE SWING
VO − Output Voltage Swing − V
Single-Ended Input to
Differential Output
Gain = 2
RL = 800 Ω
Rf = 1.3 kΩ
f= 8 MHz
VS = 5 V
Figure 66
−100
−90
−80
−70
−60
−50
−40
−30
−20
−10
0
0 0.5 1 1.5 2 2.5 3 3.5 4 4.5 5
HD2
HD3
Harmonic Distortion − dBc
HARMONIC DISTORTION
vs
OUTPUT VOLTAGE SWING
VO − Output Voltage Swing − V
Differential Input to
Differential Output
Gain = 2
RL = 800 Ω
Rf = 1.3 kΩ
f= 8 MHz
VS = 5 V
Figure 67
−100
−90
−80
−70
−60
−50
−40
−30
−20
−10
0
0 0.5 1 1.5 2 2.5 3 3.5 4 4.5 5
HD2
HD3
Harmonic Distortion − dBc
HARMONIC DISTORTION
vs
OUTPUT VOLTAGE SWING
VO − Output Voltage Swing − V
Single-Ended Input to
Differential Output
Gain = 2
RL = 800 Ω
Rf = 1.3 kΩ
f= 30 MHz
VS = 5 V
THS4502
THS4503
SLOS352D − APRIL 2002 − REVISED JANUARY 2004
www.ti.com
17
TYPICAL CHARACTERISTICS (5 V Graphs)
Figure 68
−100
−90
−80
−70
−60
−50
−40
−30
−20
−10
0
0 0.5 1 1.5 2 2.5 3 3.5 4 4.5 5
HD2
HD3
Harmonic Distortion − dBc
HARMONIC DISTORTION
vs
OUTPUT VOLTAGE SWING
VO − Output Voltage Swing − V
Differential Input to
Differential Output
Gain = 2
RL = 800 Ω
Rf = 1.3 kΩ
f= 8 MHz
VS = 5 V
Figure 69
−100
−90
−80
−70
−60
−50
−40
−30
−20
−10
0
0 400 800 1200 1600
HD2
HD3
Harmonic Distortion − dBc
HARMONIC DISTORTION
vs
LOAD RESISTANCE
RL − Load Resistance − Ω
Single-Ended Input to
Differential Output
Gain = 1
VO = 2 VPP
Rf = 499 Ω
f= 30 MHz
VS = 5 V
Figure 70
−100
−90
−80
−70
−60
−50
−40
−30
−20
−10
0
0 400 800 1200 1600
HD2
HD3
Harmonic Distortion − dBc
HARMONIC DISTORTION
vs
LOAD RESISTANCE
RL − Load Resistance − Ω
Differential Input to
Differential Output
Gain = 1
VO = 2 VPP
Rf = 499 Ω
f= 30 MHz
VS = 5 V
Figure 71
0
200
400
600
800
1000
1600
0 0.5 1 1.5 2 2.5 3 3.5 4
VO − Differential Output Voltage Step − V
SR − Slew Rate −
SLEW RATE
vs
DIFFERENTIAL OUTPUT VOLTAGE STEP
sµ
V/
1200
1400 Gain = 1
RL = 800 Ω
Rf = 499 Ω
VS = 5 V
Figure 72
−100 0 100 200 300 400 500
t − Time − ns
− Output Voltage − V
LARGE-SIGNAL TRANSIENT RESPONSE
VO
−2
−1.5
−1
−0.5
0
0.5
1
1.5
2
Gain = 1
RL = 800 Ω
Rf = 499 Ω
tr/tf = 300 ps
VS = 5 V
Figure 73
−0.4
−0.3
−0.2
−0.1
0
0.1
0.2
0.3
0.4
−100 0 100 200 300 400 500
t − Time − ns
− Output Voltage − V
SMALL-SIGNAL TRANSIENT RESPONSE
VO
Gain = 1
RL = 800 Ω
Rf = 499 Ω
tr/tf = 300 ps
VS = 5 V
Figure 74
1
10
100
0.01 0.1 1 10 100
Vn
In
f − Frequency − kHz
− Voltage Noise −
VOLTAGE AND CURRENT NOISE
vs
FREQUENCY
nV/ Hz
Vn
− Current Noise −pA/ Hz
In
1000 10 k
Figure 75
−10
0
10
20
30
40
50
60
70
80
90
0.1 1 10 100
Rejection Ratios − dB
REJECTION RATIOS
vs
FREQUENCY
f − Frequency − MHz
PSRR+
PSRR−CMMR
RL = 800 Ω
VS = 5 V
Figure 76
−40−30−20−100 102030405060708090
Rejection Ratios − dB
REJECTION RATIOS
vs
CASE TEMPERATURE
Case Temperature − °C
PSRR+
PSRR−
CMMR
RL = 800 Ω
VS = 5 V
0
20
40
60
80
100
120
THS4502
THS4503
SLOS352D − APRIL 2002 − REVISED JANUARY 2004
www.ti.com
18
TYPICAL CHARACTERISTICS (5 V Graphs)
Figure 77
−70
−60
−50
−40
−30
−20
−10
0
0.1 1 10 100
Output Balance Error − dB
OUTPUT BALANCE ERROR
vs
FREQUENCY
f − Frequency − MHz
PIN = −20 dBm
RL = 800 Ω
Rf = 499 Ω
VS = 5 V
Figure 78
0
10
20
30
40
50
60
0.01 0.1 1 10 100 1000
−150
−120
−90
−60
−30
0
30
Open-Loop Gain − dB
OPEN-LOOP GAIN AND PHASE
vs
FREQUENCY
f − Frequency − MHz
PIN = −30 dBm
RL = 800 Ω
Rf = 100 kΩ
VS = 5 V
Phase −
Gain
Phase
°
Figure 79
−40−30−20−100 102030405060708090
Open-Loop Gain − dB
OPEN-LOOP GAIN
vs
CASE TEMPERATURE
Case Temperature − °C
RL = 800 Ω
VS = 5 V
46
47
48
49
50
51
52
53
54
55
56
57
Figure 80
0
0.25
0.5
0.75
1
1.25
1.5
1.75
2
2.25
−40−30−20−100 102030405060708090
0.05
0.06
0.07
0.08
0.09
0.1
0.11
0.12
0.13
0.14
− Input Bias Current −
INPUT BIAS AND OFFSET CURRENT
vs
CASE TEMPERATURE
Case Temperature − °C
VS = ±5 V
− Input Offset Current −
IIB−
IIB Aµ
IOS Aµ
IIB+
IOS
Figure 81
0
5
10
15
20
25
30
35
0 0.5 1 1.5 2 2.5 3 3.5 4 4.5 5
VS − Supply Voltage − ±V
Quiescent Current − mA
QUIESCENT CURRENT
vs
SUPPLY VOLTAGE
TA = 85°C
TA = 25°C
TA = −40°C
Figure 82
0
0.5
1
1.5
2
2.5
−40−30−20−100 102030405060708090
Case Temperature − °C
− Input Offset Voltage − mV
INPUT OFFSET VOLTAGE
vs
CASE TEMPERATURE
VOS
VS = 5 V
Figure 83
0
10
20
30
40
50
60
70
80
90
0 0.5 1 1.5 2 2.5 3 3.5 4 4.5 5
Input Common-Mode Voltage Range − V
CMRR − Common-Mode Rejection Ratio − dB
COMMON-MODE REJECTION RATIO
vs
INPUT COMMON-MODE RANGE
VS = 5 V
Figure 84
−150
−100
−50
0
50
100
150
−40−30−20−100 102030405060708090
Output Drive − mA
OUTPUT DRIVE
vs
CASE TEMPERATURE
Case Temperature − °C
VS = 5 V Source
Sink
Figure 85
−100
−90
−80
−70
−60
−50
−40
−30
−20
−10
0
Harmonic Distortion − dBc
HARMONIC DISTORTION
vs
OUTPUT COMMON-MODE VOLTAGE
VOCM − Output Common-Mode Voltage − V
Single-Ended and
Differential Input
Gain = 1
VO = 2 VPP
Rf = 499 Ω
f= 8 MHz
VS = 5 V
1.5 1.75 2 2.25 2.5 2.75 3 3.25 3.5
HD3-SE
HD3-Diff
HD2-DiffHD2-SE
THS4502
THS4503
SLOS352D − APRIL 2002 − REVISED JANUARY 2004
www.ti.com
19
TYPICAL CHARACTERISTICS
Figure 86
−3
−2
−1
0
1
2
3
1 10 100 1000
SMALL SIGNAL FREQUENCY RESPONSE
at VOCM
f − Frequency − MHz
Gain = 1
RL = 800 Ω
Rf = 499 Ω
PIN= −20 dBm
VS = 5 V
Small Signal Frequency Response at VOCM − dB
Figure 87
−800
−600
−400
−200
0
200
400
600
800
0 0.5 1 1.5 2 2.5 3 3.5 4 4.5 5
VOC − Output Common-Mode Voltage − V
− Output Offset Voltage − mV
OUTPUT OFFSET VOLTAGE
vs
OUTPUT COMMON-MODE VOLTAGE
VOS
Figure 88
0
5
10
15
20
25
0 0.25 0.5 0.75 1 1.25 1.5 1.75 2 2.25 2.5
Power-down Voltage − V
Quiescent Current − mA
QUIESCENT CURRENT
vs
POWER-DOWN VOLTAGE
Figure 89
−1
−2
−5
0 0.5 1 2
0
100.5101 102 103
−3
−6
−4
0
0.01
0.03
0.02
t − Time − ms
Powerdown Voltage Signal − V
TURNON AND TURNOFF DELAY TIMES
Quiescent Current − mA
1.5 2.5 3
Current
Figure 90
0
100
200
300
400
500
600
700
800
900
1000
1100
0.1 1 10 100 1000
− Single-Ended Output Impedance
SINGLE-ENDED OUTPUT IMPEDANCE
IN POWER DOWN
vs
FREQUENCY
ZOin Power Down −
f − Frequency − MHz
Gain = 1
RL = 400 Ω
Rf = 392 Ω
PIN = −1 dBm
VS = 5 V
Ω
Figure 91
−40−30−20−100 102030405060708090
POWER-DOWN QUIESCENT CURRENT
vs
CASE TEMPERATURE
Case Temperature − °C
RL = 800 Ω
VS = 5 V
0
0.1
0.2
0.3
0.4
0.5
0.6
0.7
0.8
0.9
1
Power-Down Quiescent Current − mA
Figure 92
0
100
200
300
400
500
600
700
800
900
1000
0 0.5 1 1.5 2 2.5 3 3.5 4 4.5 5
VS − Supply Voltage − V
POWER-DOWN QUIESCENT CURRENT
vs
SUPPLY VOLTAGE
Power-Down Quiescent Current −Aµ
THS4502
THS4503
SLOS352D − APRIL 2002 − REVISED JANUARY 2004
www.ti.com
20
APPLICATION INFORMATION
FULLY DIFFERENTIAL AMPLIFIERS
Differential signaling offers a number of performance
advantages in high-speed analog signal processing
systems, including immunity to external common-mode
noise, suppression of even-order nonlinearities, and
increased dynamic range. Fully differential amplifiers not
only serve as the primary means of providing gain to a
differential signal chain, but also provide a monolithic
solution for converting single-ended signals into
differential signals for easier, higher performance
processing. The THS4500 family of amplifiers contains
products in Texas Instruments’ expanding line of
high-performance fully differential amplifiers. Information
on fully differential amplifier fundamentals, as well as
implementation specific information, is presented in the
applications section of this data sheet to provide a better
understanding of the operation of the THS4500 family of
devices, and to simplify the design process for designs
using these amplifiers.
Applications Section
DFully Differential Amplifier Terminal Functions
DInput Common-Mode Voltage Range and the
THS4500 Family
DChoosing the Proper Value for the Feedback and
Gain Resistors
DApplication Circuits Using Fully Differential
Amplifiers
DKey Design Considerations for Interfacing to an
Analog-to-Digital Converter
DSetting the Output Common-Mode Voltage With the
VOCM Input
DSaving Power With Power-Down Functionality
DLinearity: Definitions, Terminology, Circuit
Techniques, and Design Tradeoffs
DAn Abbreviated Analysis of Noise in Fully
Differential Amplifiers
DPrinted-Circuit Board Layout Techniques for Optimal
Performance
DPower Dissipation and Thermal Considerations
DPower Supply Decoupling Techniques and
Recommendations
DEvaluation Fixtures, Spice Models, and Applications
Support
DAdditional Reference Material
FULLY DIFFERENTIAL AMPLIFIER
TERMINAL FUNCTIONS
Fully differential amplifiers are typically packaged in
eight-pin packages as shown in the diagram. The device
pins include two inputs (VIN+, VIN−), two outputs (VOUT−,
VOUT+), two power supplies (VS+, VS−), an output
common-mode control pin (VOCM), and an optional
power-down pin (PD).
VIN−1
2
3
4
8
7
6
5
VOCM
VS+
VOUT+
VIN+
VS−
VOUT−
PD
Fully Differential Amplifier Pin Diagram
A standard configuration for the device is shown in the
figure. The functionality of a fully differential amplifier can
be imagined as two inverting amplifiers that share a
common noninverting terminal (though the voltage is not
necessarily fixed). For more information on the basic
theory of operation for fully differential amplifiers, refer to
the Texas Instruments application note titled Fully
Differential Amplifiers, literature number SLOA054.
INPUT COMMON-MODE VOLTAGE RANGE
AND THE THS4500 FAMILY
The key difference between the THS4500/1 and the
THS4502/3 is the input common-mode range for the two
devices. The THS4502 and THS4503 have an input
common-mode range that is centered around midrail, and
the THS4500 and THS4501 have an input common-mode
range that is shifted to include the negative power supply
rail. Selection of one or the other is determined by the
nature of the application. Specifically, the THS4500 and
THS4501 are designed for use in single-supply
applications where the input signal is ground-referenced,
as depicted in Figure 93. The THS4502 and THS4503 are
designed for use in single-supply or split-supply
applications where the input signal is centered between
the power supply voltages, as depicted in Figure 94.
Figure 93
VOCM
+VS
VS
RSRg1
Rg2
Rf1
Rf2
+
−
RT
−
+
Application Circuit for the THS4500 and THS4501,
Featuring Single-Supply Operation With a
Ground-Referenced Input Signal
THS4502
THS4503
SLOS352D − APRIL 2002 − REVISED JANUARY 2004
www.ti.com
21
Figure 94
VOCM
+VS
VS
RSRg1
Rg2
Rf1
Rf2
+
−
RT
−
+
−VS
Application Circuit for the THS4500 and THS4501,
Featuring Split-Supply Operation With an Input
Signal Referenced at the Midrail
Equations 1−5 allow for calculation of the required input
common-mode range for a given set of input conditions.
The equations allow calculation of the input common-
mode range requirements given information about the
input signal, the output voltage swing, the gain, and the
output common-mode voltage. Calculating the maximum
and minimum voltage required for VN and VP (the
amplifier’s input nodes) determines whether or not the
input common-mode range is violated or not. Four
equations are required. Two calculate the output voltages
and two calculate the node voltages at VN and VP (note
that only one of these needs calculation, as the amplifier
forces a virtual short between the two nodes).
VOUT)+VIN)(1–β)–VIN–(1–β))2VOCMβ
2β
VOUT–+–VIN)(1–β))VIN–(1–β))2VOCMβ
2
β
(1)
(2)
VN+VIN–(1–β))VOUT)β
Where: β+RG
RF)RG
VP+VIN)(1–β))VOUT–β
(3)
(4)
(5)
NOTE:
The equations denote the device inputs as VN and
VP, and the circuit inputs as VIN+ and VIN−.
Figure 95
VOCM
Rg
Rg
Rf
Rf
+
−
−
+
Vp
Vn
VOUT−
VOUT+
VIN+
VIN−
Diagram For Input Common-Mode Range Equations
The two tables below depict the input common-mode
range requirements for two different input scenarios, an
input referenced around the negative rail and an input
referenced around midrail. The tables highlight the
differing requirements o n input common-mode range, and
illustrate reasoning for choosing either the THS4500/1 or
the THS4502/3. For signals referenced around the
negative power supply, the THS4500/1 should be chosen
since its input common-mode range includes the negative
supply rail. For all other situations, the THS4502/3 offers
slightly improved distortion and noise performance for
applications with input signals centered between the
power supply rails.
Table 1. Negative-Rail Referenced
Gain
(V/V) VIN+ (V) VIN−
(V) VIN
(VPP)VOCM
(V) VOD
(VPP)VNMIN
(V) VNMAX
(V)
1−2.0 to
2.0 0 4 2.5 4 0.75 1.75
2−1.0 to
1.0 0 2 2.5 4 0.5 1.167
4−0.5 to
0.5 0 1 2.5 4 0.3 0.7
8−0.25 to
0.25 0 0.5 2.5 4 0.167 0.389
NOTE:This table assumes a negative-rail referenced, single-ended
input signal on a single 5-V supply as shown in Figure 93.
VNMIN = VPMIN and VNMAX = VPMAX.
Table 2. Midrail Referenced
Gain
(V/V) VIN+ (V) VIN−
(V) VIN
(VPP)VOCM
(V) VOD
(VPP)VNMIN
(V) VNMAX
(V)
10.5 to
4.5 2.5 4 2.5 4 2 3
21.5 to
3.5 2.5 2 2.5 4 2.16 2.83
42.0 to
3.0 2.5 1 2.5 4 2.3 2.7
82.25 to
2.75 2.5 0.5 2.5 4 2.389 2.61
NOTE:This table assumes a midrail referenced, single-ended input
signal on a single 5-V supply.
VNMIN = VPMIN and VNMAX = VPMAX.
THS4502
THS4503
SLOS352D − APRIL 2002 − REVISED JANUARY 2004
www.ti.com
22
CHOOSING THE PROPER VALUE FOR THE
FEEDBACK AND GAIN RESISTORS
The selection of feedback and gain resistors impacts
circuit performance in a number of ways. The values in this
section provide the optimum high frequency performance
(lowest distortion, flat frequency response). Since the
THS4500 family of amplifiers is developed with a voltage
feedback architecture, the choice of resistor values does
not have a dominant ef fect on bandwidth, unlike a current
feedback amplifier. However, resistor choices do have
second-order effects. For optimal performance, the
following feedback resistor values are recommended. In
higher gain configurations (gain greater than two), the
feedback resistor values have much less ef fect on the high
frequency performance. Example feedback and gain
resistor values are given in the section on basic design
considerations (Table 3).
Amplifier loading, noise, and the flatness of the frequency
response are three design parameters that should be
considered when selecting feedback resistors. Larger
resistor values contribute more noise and can induce
peaking i n the ac response in low gain configurations, and
smaller resistor values can load the amplifier more heavily,
resulting in a reduction in distortion performance. In
addition, feedback resistor values, coupled with gain
requirements, determine the value of the gain resistors,
directly impacting the input impedance of the entire circuit.
While there are no strict rules about resistor selection,
these trends can provide qualitative design guidance.
APPLICATION CIRCUITS USING FULLY
DIFFERENTIAL AMPLIFIERS
Fully differential amplifiers provide designers with a great
deal of flexibility in a wide variety of applications. This
section provides an overview of some common circuit
configurations and gives some design guidelines.
Designing the interface to an ADC, driving lines
differentially, and filtering with fully differential amplifiers
are a few of the circuits that are covered.
BASIC DESIGN CONSIDERATIONS
The circuits in Figures 96 through 100 are used to highlight
basic design considerations for fully differential amplifier
circuit designs.
Table 3. Resistor Values for Balanced Operation
in Various Gain Configurations
Gain ǒVOD
VIN ǓR2 & R4 (Ω)R1 (Ω)R3 (Ω) RT (Ω)
1 392 412 383 54.9
1 499 523 487 53.6
2 392 215 187 60.4
2 1.3k 665 634 52.3
5 1.3k 274 249 56.2
5 3.32k 681 649 52.3
10 1.3k 147 118 64.9
10 6.81k 698 681 52.3
NOTE:Values i n the table above assume a 50 Ω source impedance.
VOCM
Vn
VS
RS
R1
RT
R2
R4
−
++
−
Vout+
Vout−
R3
VP
Figure 96
Equations for calculating fully dif ferential amplifier resistor
values in order to obtain balanced operation in the
presence of a 50-Ω source impedance are given in
equations 6 through 9.
RT+1
1
RS–1–K
2(1)K)
R3
K+R2
R1 R2 +R4
R3 +R1 *ǒRs|| RTǓ
(6)
β1+R1
R1 )R2 β2+R3 )RT|| RS
R3 )RT|| RS)R4
VOD
VS+2ǒ1–β2
β1)β2Ǔǒ RT
RT)RSǓ
VOD
VIN +2ǒ1–β2
β1)β2Ǔ
(7)
(8)
(9)
For more detailed information about balance in fully
differential amplifiers, see Fully Differential Amplifiers,
referenced at the end of this data sheet.
THS4502
THS4503
SLOS352D − APRIL 2002 − REVISED JANUARY 2004
www.ti.com
23
INTERFACING TO AN ANALOG-TO-DIGITAL
CONVERTER
The THS4500 family of amplifiers are designed
specifically to interface to today’s highest-performance
analog-to-digital converters. This section highlights the
key concerns when interfacing to an ADC and provides
example ADC/fully differential amplifier interface circuits.
Key design concerns when interfacing to an
analog-to-digital converter:
DTerminate the input source properly. In high-frequency
receiver chains, the source feeding the fully
differential amplifier requires a specific load
impedance (e.g., 50 Ω).
DDesign a symmetric printed-circuit board layout.
Even-order distortion products are heavily influenced
by layout, and careful attention to a symmetric layout
will minimize these distortion products.
DMinimize inductance in power supply decoupling
traces and components. Poor power supply
decoupling can have a dramatic effect on circuit
performance. Since the outputs are differential,
differential currents exist in the power supply pins.
Thus, decoupling capacitors should be placed in a
manner that minimizes the impedance of the current
loop.
DUse separate analog and digital power supplies and
grounds. Noise (bounce) in the power supplies
(created by digital switching currents) can couple
directly into the signal path, and power supply noise
can create higher distortion products as well.
DUse care when filtering. While an RC low-pass filter
may be desirable on the output of the amplifier to filter
broadband noise, the excess loading can negatively
impact the amplifier linearity. Filtering in the feedback
path does not have this effect.
DAC-coupling allows easier circuit design. If
dc-coupling i s required, be aware of the excess power
dissipation that can occur due to level-shifting the
output through the output common-mode voltage
control.
DDo not terminate the output unless required. Many
open-loop, class-A amplifiers require 50-Ω
termination for proper operation, but closed-loop fully
differential amplifiers drive a specific output voltage
regardless of the load impedance present.
Terminating the output of a fully differential amplifier
with a heavy load adversely effects the amplifier’s
linearity.
DComprehend the VOCM input drive requirements.
Determine i f t h e A D C ’s voltage reference can provide
the required amount of current to move VOCM to the
desired value. A buffer may be needed.
DDecouple the VOCM pin to eliminate the antenna
ef fect. V OCM is a high-impedance node that can act as
an antenna. A large decoupling capacitor on this node
eliminates this problem.
DBe cognizant of the input common-mode range. If the
input signal is referenced around the negative power
supply rail (e.g., around ground on a single 5 V
supply), then the THS4500/1 accommodates the
input signal. If the input signal is referenced around
midrail, choose the THS4502/3 for the best operation.
DPackaging makes a difference at higher frequencies.
If possible, choose the smaller, thermally enhanced
MSOP package for the best performance. As a rule,
lower junction temperatures provide better
performance. If possible, use a thermally enhanced
package, even if the power dissipation is relatively
small compared to the maximum power dissipation
rating to achieve the best results.
DComprehend the ef fect of the load impedance seen by
the fully differential amplifier when performing
system-level intercept point calculations. Lighter
loads (such as those presented by an ADC) allow
smaller intercept points to support the same level of
intermodulation distortion performance.
EXAMPLE ANALOG-TO-DIGITAL
CONVERTER DRIVER CIRCUITS
The THS4500 family of devices is designed to drive
high-performance ADCs with extremely high linearity,
allowing for the maximum effective number of bits at the
output of the data converter. Two representative circuits
shown below highlight single-supply operation and split
supply operation. Specific feedback resistor, gain resistor,
and feedback capacitor values are not specified, as their
values depend on the frequency of interest. Information on
calculating these values can be found in the applications
material above.
Figure 97
+
−+
−
VOCM 12 Bit/80 MSps
IN
IN
5 V
CM
5 V
−5 V
VS
10 µF 0.1 µF
10 µF 0.1 µF
THS4503
Rf
Rf
CF
CF
1 µF
Rg
Rg0.1 µF
RT
RS
ADS5410
Using the THS4503 With the ADS5410
Riso
Riso
THS4502
THS4503
SLOS352D − APRIL 2002 − REVISED JANUARY 2004
www.ti.com
24
Figure 98
+
−+
−
VOCM 14 Bit/40 MSps
IN
IN
5 V
CM
5 V
VS
10 µF 0.1 µF
THS4501
Rf
Rf
CF
CF
1 µF
Rg
Rg
RT
RS
ADS5421
0.1 µF
Using the THS4501 With the ADS5421
Riso
Riso
FULLY DIFFERENTIAL LINE DRIVERS
The THS4500 family of amplifiers can be used as
high-frequency, high-swing differential line drivers. Their
high power supply voltage rating (16.5 V absolute
maximum) allows operation on a single 12-V or a single
15-V supply. The high supply voltage, coupled with the
ability to provide differential outputs enables the ability to
drive 26 VPP into reasonably heavy loads (250 Ω or
greater). The circuit in Figure 99 illustrates the THS4500
family of devices used as high speed line drivers. For line
driver applications, close attention must be paid to thermal
design constraints due to the typically high level of power
dissipation.
Figure 99
VOCM
15 V
VS
RSRgRf
Rf
+
−
RT
−
+
Rg
CG
0.1 µF
CG
THS4500/2 VDD
CS
CS
RL
VOD = 26 VPP
Riso
Riso
Fully Differential Line Driver With High Output Swing
FILTERING WITH FULLY DIFFERENTIAL
AMPLIFIERS
Similar to their single-ended counterparts, fully dif ferential
amplifiers have the ability to couple filtering functionality
with voltage gain. Numerous filter topologies can be based
on fully dif ferential amplifiers. Several of these are outlined
in A Differential Circuit Collection, (literature number
SLOA064) referenced at the end of this data sheet. The
circuit below depicts a simple two-pole low-pass filter
applicable to many different types of systems. The first
pole is set by the resistors and capacitors in the feedback
paths, and the second pole is set by the isolation resistors
and the capacitor across the outputs of the isolation
resistors.
Figure 100
VS
RSRg1 Rf1
Rf2
+
−
RT
−
+VO
Riso
C
CF2
CF1
Rg2 Riso
A Two-Pole, Low-Pass Filter Design Using a Fully
Differential Amplifier With Poles Located at:
P1 = (2πRfCF)−1 in Hz and P2 = (4πRisoC)−1 in Hz
Often times, filters like these are used to eliminate
broadband noise and out-of-band distortion products in
signal acquisition systems. It should be noted that the
increased load placed on the output of the amplifier by the
second low-pass filter has a detrimental effect on the
distortion performance. The preferred method of filtering
is using the feedback network, as the typically smaller
capacitances required at these points in the circuit do not
load the amplifier nearly as heavily in the pass-band.
SETTING THE OUTPUT COMMON-MODE
VOLTAGE WITH THE VOCM INPUT
The output common-mode voltage pin provides a critical
function t o the fully dif ferential amplifier; it accepts an input
voltage and reproduces that input voltage as the output
common-mode voltage. In other words, the VOCM input
provides the ability to level-shift the outputs to any voltage
inside the output voltage swing of the amplifier.
A description of the input circuitry of the VOCM pin is shown
below to facilitate an easier understanding of the VOCM
interface requirements. The VOCM pin has two 50-kΩ
resistors between the power supply rails to set the default
output common-mode voltage to midrail. A voltage
applied to the VOCM pin alters the output common-mode
voltage as long as the source has the ability to provide
enough current to overdrive the two 50-kΩ resistors. This
phenomenon is depicted in the VOCM equivalent circuit
diagram. The table contains some representative
examples to aid in determining the current drive
requirement for the VOCM voltage source. This parameter
is especially important when using the reference voltage
THS4502
THS4503
SLOS352D − APRIL 2002 − REVISED JANUARY 2004
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25
of an analog-to-digital converter to drive VOCM. Output
current drive capabilities differ from part to part, so a
voltage buffer may be necessary in some applications.
Figure 101
R = 50 kΩ
R = 50 kΩ
VS+
VS−
VOCM
IIN
IIN = 2 VOCM − VS+ − VS−
R
Equivalent Input Circuit for VOCM
By design, the input signal applied to the VOCM pin
propagates to the outputs as a common-mode signal. As
shown in the equivalent circuit diagram, the VOCM input
has a high impedance associated with it, dictated by the
two 50-kΩ resistors. While the high impedance allows for
relaxed drive requirements, it also allows the pin and any
associated printed-circuit board traces to act as an
antenna. For this reason, a decoupling capacitor is
recommended on this node for the sole purpose of filtering
any high frequency noise that could couple into the signal
path through the VOCM circuitry. A 0.1-µF or 1-µF
capacitance is a reasonable value for eliminating a great
deal of broadband interference, but additional, tuned
decoupling capacitors should be considered if a specific
source of electromagnetic or radio frequency interference
is present elsewhere in the system. Information on the ac
performance (bandwidth, slew rate) of the VOCM circuitry
is included in the specification table and graph section.
Since the VOCM pin provides the ability to set an output
common-mode voltage, the ability for increased power
dissipation e x i s t s . W h i l e t h i s does not pose a performance
problem for the amplifier, it can cause additional power
dissipation o f which the system designer should be aware.
The circuit shown in Figure 102 demonstrates an
example of this phenomenon. For a device operating on
a single 5-V supply with an input signal referenced around
ground and an output common-mode voltage of 2.5 V, a
dc potential exists between the outputs and the inputs of
the device. The amplifier sources current into the
feedback network in order to provide the circuit with the
proper operating point. While there are no serious effects
on the circuit performance, the extra power dissipation
may need to be included in the system’s power budget.
Figure 102
VOCM = 2.5 V
5 V
VS
RSRg1
Rg2
Rf1
Rf2
+
−
RT
−
+RL
2.5-V DC
2.5-V DC
DC Current Path to Ground
DC Current Path to Ground
I2 = VOCM
Rf2 + Rg2
Depiction of DC Power Dissipation Caused By
Output Level-Shifting in a DC-Coupled Circuit
I1 = VOCM
Rf1+ Rg1 + RS || RT
SAVING POWER WITH POWER-DOWN
FUNCTIONALITY
The THS4500 family of fully differential amplifiers contains
devices that come with and without the power-down
option. Even-numbered devices have power-down
capability, which is described in detail here.
The power-down pin of the amplifiers defaults to the
positive supply voltage in the absence of an applied
voltage (i.e. an internal pullup resistor is present), putting
the amplifier in the power-on mode of operation. To turn off
the amplifier in an effort to conserve power, the
power-down pin can be driven towards the negative rail.
The threshold voltages for power-on and power-down are
relative to the supply rails and given in the specification
tables. Above the enable threshold voltage, the device is
on. Below the disable threshold voltage, the device is off.
Behavior in between these threshold voltages is not
specified.
Note that this power-down functionality is just that; the
amplifier consumes less power in power-down mode. The
power-down mode is not intended to provide a
high-impedance output. In other words, the power-down
functionality is not intended to allow use as a 3-state bus
driver. When in power-down mode, the impedance looking
back into the output of the amplifier is dominated by the
feedback and gain setting resistors.
The time delays associated with turning the device on and
off are specified as the time it takes for the amplifier to
reach 50% of the nominal quiescent current. The time
delays are on the order of microseconds because the
amplifier moves in and out of the linear mode of operation
in these transitions.
THS4502
THS4503
SLOS352D − APRIL 2002 − REVISED JANUARY 2004
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26
LINEARITY: DEFINITIONS, TERMINOLOGY,
CIRCUIT TECHNIQUES, AND DESIGN
TRADEOFFS
The THS4500 family of devices features unprecedented
distortion performance for monolithic fully differential
amplifiers. This section focuses on the fundamentals of
distortion, circuit techniques for reducing nonlinearity,
and methods for equating distortion of fully differential
amplifiers t o desired linearity specifications in RF receiver
chains.
Amplifiers are generally thought of as linear devices. In
other words, the output of an amplifier is a linearly scaled
version o f the input signal applied to it. In reality, however,
amplifier transfer functions are nonlinear. Minimizing
amplifier nonlinearity is a primary design goal in many
applications.
Intercept points are specifications that have long been
used as key design criteria in the RF communications
world as a metric for the intermodulation distortion
performance of a device in the signal chain (e.g.,
amplifiers, mixers, etc.). Use of the intercept point, rather
than strictly the intermodulation distortion, allows for
simpler system-level calculations. Intercept points, like
noise figures, can be easily cascaded back and forth
through a signal chain to determine the overall receiver
chain’s intermodulation distortion performance. The
relationship between intermodulation distortion and
intercept point is depicted in Figure 103 and Figure 104.
Figure 103
IMD3 = PS − PO
PS
PO
PO
∆fc = fc − f1
∆fc = f2 − fc
PS
fc − 3∆ff1f
cf2 fc + 3∆f
Power
f − Frequency − MHz
Figure 104
IMD3
OIP3
IIP3
3X
PIN
(dBm)
1X
POUT
(dBm)
PO
PS
Due to the intercept point’s ease of use in system level
calculations for receiver chains, it has become the
specification o f choice for guiding distortion-related design
decisions. Traditionally, these systems use primarily
class-A, single-ended RF amplifiers as gain blocks. These
RF amplifiers are typically designed to operate in a 50-Ω
environment, just like the rest of the receiver chain. Since
intercept points are given in dBm, this implies an
associated impedance (50 Ω).
However, with a fully differential amplifier, the output does
not require termination as an RF amplifier would. Because
closed-loop amplifiers deliver signals to their outputs
regardless of the impedance present, it is important to
comprehend this when evaluating the intercept point of a
fully differential amplifier. The THS4500 series of devices
yields optimum distortion performance when loaded with
200 Ω to 1 kΩ, very similar to the input impedance of an
analog-to-digital converter over its input frequency band.
As a result, terminating the input of the ADC to 50 Ω can
actually be detrimental to system performance.
This discontinuity between open-loop, class-A amplifiers
and closed-loop, class-AB amplifiers becomes apparent
when comparing the intercept points of the two types of
devices. Equation 10 gives the definition of an intercept
point, relative to the intermodulation distortion.
OIP3+PO)ǒŤIMD3Ť
2Ǔwhere
PO+10 logǒV2
Pdiff
2RL 0.001Ǔ
(10)
(11)
NOTE:Po is the output power of a single tone, RL is the dif ferential load
resistance, and VP(diff) is the differential peak voltage for a
single tone.
THS4502
THS4503
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27
As can be seen in the equation, when a higher impedance
is used, the same level of intermodulation distortion
performance results in a lower intercept point. Therefore,
it is important to comprehend the impedance seen by the
output of the fully differential amplifier when selecting a
minimum intercept point. The graphic below shows the
relationship between the strict definition of an intercept
point with a normalized, or equivalent, intercept point for
the THS4502.
Figure 105
40
30
20
15 0 102030405060
50
55
f − Frequency − MHz
THIRD-ORDER OUTPUT INTERCEPT POINT
vs
FREQUENCY
60
70 80 90 100
45
35
25
Normalized to 200 Ω
Gain = 1
Rf = 392 Ω
VS = ± 5 V
Tone Spacing = 200 kHz
OIP3 RL= 800 Ω
Normalized to 50 Ω
− Third-Order Output Intercept Point − dBm
OIP3
Comparing specifications between different device types
becomes easier when a common impedance level is
assumed. For this reason, the intercept points on the
THS4500 family of devices are reported normalized to a
50-Ω load impedance.
AN ANALYSIS OF NOISE IN FULLY
DIFFERENTIAL AMPLIFIERS
Noise analysis in fully differential amplifiers is analogous
to noise analysis in single-ended amplifiers. The same
concepts apply. Below, a generic circuit diagram
consisting of a voltage source, a termination resistor, two
gain setting resistors, two feedback resistors, and a fully
differential amplifier is shown, including all the relevant
noise sources. From this circuit, the noise factor (F) and
noise figure (NF) are calculated. The figures indicate the
appropriate scaling factor for each of the noise sources in
two dif ferent cases. The first case includes the termination
resistor, and the second, simplified case assumes that the
voltage source is properly terminated by the gain-setting
resistors. With these scaling factors, the amplifier’s input
noise power (NA) can be calculated by summing each
individual noise source with its scaling factor. The noise
delivered t o the amplifier by the source (NI) and input noise
power are used to calculate the noise factor and noise
figure as shown in equations 23 through 27.
Figure 106. Noise Sources in a Fully
Differential Amplifier Circuit
NiNARgRf
egef
es
Rs
enNo
ini
iii
Rt
et
Ni
Si
No
So
+
−
fully-diff
amp
RgRf
egef
ȧ
ȡ
Ȣ
Rg
Rf)
Rg
Rg)RsRt
2ǒRs)RtǓȧ
ȣ
Ȥ
2
(eni)2
(ini)2
(iii)2
4kTRtȧ
ȡ
Ȣ
2RsRG
Rs)2Rg
Rt)2RsRg
Rs)2Rgȧ
ȣ
Ȥ
2
4kTRf2 ǒRg
RfǓ2
4kTRg2
ȧ
ȧ
ȡ
Ȣ
Rg
Rg)RsRt
2ǒRs)RtǓȧ
ȧ
ȣ
Ȥ
2
NA: Fully Differential Amplifier
Noise
Source Scale Factor
(12)
(13)
(14)
(15)
(16)
(17)
Rg2
Rg2
Figure 107. Scaling Factors for Individual Noise
Sources Assuming a Finite Value Termination
Resistor
THS4502
THS4503
SLOS352D − APRIL 2002 − REVISED JANUARY 2004
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28
ȧ
ȡ
Ȣ
Rg
Rf)Rg
Rg)Rs
2ȧ
ȣ
Ȥ
2
(eni)2
(ini)2
(iii)2
2 ǒRg
RfǓ2
4kTRg2
ȧ
ȡ
Ȣ
Rg
Rg)Rs
2ȧ
ȣ
Ȥ
2
NA: Fully Differential Amplifier; termination = 2Rg
Noise
Source Scale Factor
4kTRf
(18)
(19)
(20)
(21)
(22)
Rg2
Rg2
Figure 108. Scaling Factors for Individual Noise
Sources Assuming No termination Resistance is
Used (e.g., RT is open)
Ni+4kTRsȧ
ȧ
ȧ
ȧ
ȡ
Ȣ
2RtRg
Rt)2Rg
Rs)2RtRg
Rt)2Rg
ȧ
ȧ
ȧ
ȧ
ȣ
Ȥ
2
(23)
Figure 109. Input Noise With a Termination
Resistor
Ni+4kTRsǒ2Rg
Rs)2RgǓ2(24)
Figure 110. Input Noise Assuming No
Termination Resistor
Noise Factor and Noise Figure Calculations
NA+SǒNoise Source Scale FactorǓ
F+1)NA
NI
NF +10 log (F)
(25)
(26)
(27)
PRINTED-CIRCUIT BOARD LAYOUT
TECHNIQUES FOR OPTIMAL
PERFORMANCE
Achieving optimum performance with high frequency
amplifier-like devices in the THS4500 family requires
careful attention to board layout parasitic and external
component types.
Recommendations that optimize performance include:
DMinimize parasitic capacitance to any ac ground for all
of the signal I/O pins. Parasitic capacitance on the
output and input pins can cause instability. To reduce
unwanted capacitance, a window around the signal
I/O pins should be opened in all of the ground and
power planes around those pins. Otherwise, ground
and power planes should be unbroken elsewhere on
the board.
DMinimize the distance (< 0.25”) from the power supply
pins to high frequency 0.1-µF decoupling capacitors.
At the device pins, the ground and power plane layout
should not be in close proximity to the signal I/O pins.
Avoid narrow power and ground traces to minimize
inductance between the pins and the decoupling
capacitors. The power supply connections should
always be decoupled with these capacitors. Larger
(6.8 µF or more) tantalum decoupling capacitors,
effective at lower frequency, should also be used on
the main supply pins. These may be placed somewhat
farther from the device and may be shared among
several devices in the same area of the PC board. The
primary goal is to minimize the impedance seen in the
dif ferential-current return paths.
DCareful selection and placement of external
components preserve the high frequency
performance of the THS4500 family. Resistors should
be a very low reactance type. Surface-mount resistors
work best and allow a tighter overall layout. Metal-film
and carbon composition, axially-leaded resistors can
also provide good high frequency performance.
Again, keep their leads and PC board trace length as
short a s p o s s i ble. Never use wirewound type resistors
in a high frequency application. Since the output pin
and inverting input pins are the most sensitive to
parasitic capacitance, always position the feedback
and series output resistors, if any, as close as possible
to the inverting input pins and output pins. Other
network components, such as input termination
resistors, should be placed close to the gain-setting
resistors. Even with a low parasitic capacitance
shunting the external resistors, excessively high
resistor values can create significant time constants
that can degrade performance. Good axial metal-film
or surface-mount resistors have approximately 0.2 pF
in shunt with the resistor. For resistor values > 2. 0 kΩ,
this parasitic capacitance can add a pole and/or a zero
below 400 MHz that can ef fect circuit operation. Keep
resistor values as low as possible, consistent with
load driving considerations.
DConnections to other wideband devices on the board
may be made with short direct traces or through
onboard transmission lines. For short connections,
consider the trace and the input to the next device a s
a lumped capacitive load. Relatively wide traces
THS4502
THS4503
SLOS352D − APRIL 2002 − REVISED JANUARY 2004
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29
(50 mils to 100 mils) should be used, preferably with
ground and power planes opened up around them.
Estimate the total capacitive load and determine if
isolation resistors on the outputs are necessary. Low
parasitic capacitive loads (< 4 pF) may not need an RS
since the THS4500 family is nominally compensated
to operate with a 2-pF parasitic load. Higher parasitic
capacitive loads without an RS are allowed as the
signal gain increases (increasing the unloaded phase
margin). I f a long trace is required, and the 6-dB signal
loss intrinsic to a doubly-terminated transmission line
is acceptable, implement a matched impedance
transmission line using microstrip or stripline
techniques (consult an ECL design handbook for
microstrip and stripline layout techniques).
A 50-Ω environment is normally not necessary
onboard, and in fact, a higher impedance environment
improves distortion as shown in the distortion versus
load plots. With a characteristic board trace
impedance defined based on board material and trace
dimensions, a matching series resistor into the trace
from the output of the THS4500 family is used as well
as a terminating shunt resistor at the input of the
destination device.
Remember also that the terminating impedance is th e
parallel combination of the shunt resistor and the input
impedance of the destination device: this total
ef fective impedance should be set to match the trace
impedance. If the 6-dB attenuation of a doubly
terminated transmission line is unacceptable, a long
trace can be series-terminated at the source end only.
Treat the trace as a capacitive load in this case. This
does not preserve signal integrity as well as a
doubly-terminated line. If the input impedance of the
destination device is low, there is some signal
attenuation due to the voltage divider formed by the
series output into the terminating impedance.
DSocketing a high speed part like the THS4500 family
is not recommended. The additional lead length and
pin-to-pin capacitance introduced by the socket can
create an extremely troublesome parasitic network
which can make it almost impossible to achieve a
smooth, stable frequency response. Best results are
obtained by soldering the THS4500 family parts
directly onto the board.
PowerPAD DESIGN CONSIDERATIONS
The THS4500 family is available in a thermally-enhanced
PowerPAD family of packages. These packages are
constructed using a downset leadframe upon which the die
is mounted [see Figure 111(a) and Figure 111(b)]. This
arrangement results in the lead frame being exposed as a
thermal pad on the underside of the package [see
Figure 111(c)]. Because this thermal pad has direct
thermal contact with the die, excellent thermal
performance can be achieved by providing a good thermal
path away from the thermal pad.
The PowerPAD package allows for both assembly and
thermal management in one manufacturing operation.
During the surface-mount solder operation (when the
leads are being soldered), the thermal pad can also be
soldered to a copper area underneath the package.
Through the use of thermal paths within this copper area,
heat can be conducted away from the package into either
a ground plane or other heat dissipating device.
The PowerPAD package represents a breakthrough in
combining the small area and ease of assembly of surface
mount with the, heretofore, awkward mechanical methods
of heatsinking.
DIE
Side V iew (a)
DIE
End V iew (b)
Thermal
Pad
Bottom V iew (c)
Figure 111. Views of Thermally Enhanced
Package
Although there are many ways to properly heatsink the
PowerPAD package, the following steps illustrate the
recommended approach.
0.060
0.040
0.075 0.025
0.205
0.010
vias
Pin 1
Top View
0.017
0.035
0.094
0.030
0.013
Figure 112. PowerPAD PCB Etch and Via Pattern
PowerPAD PCB LAYOUT CONSIDERATIONS
1. Prepare the PCB with a top side etch pattern as shown
in Figure 112. There should be etch for the leads as
well as etch for the thermal pad.
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SLOS352D − APRIL 2002 − REVISED JANUARY 2004
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30
2. Place five holes in the area of the thermal pad. These
holes should be 13 mils in diameter. Keep them small
so that solder wicking through the holes is not a
problem during reflow.
3. Additional vias may be placed anywhere along the
thermal plane outside of the thermal pad area. This
helps dissipate the heat generated by the THS4500
family IC. These additional vias may be larger than the
13-mil diameter vias directly under the thermal pad.
They can be larger because they are not in the thermal
pad area to be soldered so that wicking is not a
problem.
4. Connect all holes to the internal ground plane.
5. When connecting these holes to the ground plane, do
not use the typical web or spoke via connection
methodology. Web connections have a high thermal
resistance connection that is useful for slowing the
heat transfer during soldering operations. This makes
the soldering of vias that have plane connections
easier. In this application, however, low thermal
resistance is desired for the most efficient heat
transfer. Therefore, the holes under the THS4500
family PowerPAD package should make their
connection to the internal ground plane with a
complete connection around the entire circumference
of the plated-through hole.
6. The top-side solder mask should leave the terminals
of the package and the thermal pad area with its five
holes exposed. The bottom-side solder mask should
cover the five holes of the thermal pad area. This
prevents solder from being pulled away from the
thermal pad area during the reflow process.
7. Apply solder paste to the exposed thermal pad area
and all of the IC terminals.
8. With these preparatory steps in place, the IC is simply
placed in position and run through the solder reflow
operation as any standard surface-mount
component. This results in a part that is properly
installed.
POWER DISSIPATION AND THERMAL
CONSIDERATIONS
The THS4500 family of devices does not incorporate
automatic thermal shutof f protection, so the designer must
take care to ensure that the design does not violate the
absolute maximum junction temperature of the device.
Failure may result if the absolute maximum junction
temperature of 1 5 0 °C is exceeded. For best performance,
design for a maximum junction temperature of 125°C.
Between 125°C and 150°C, damage does not occur, but
the performance of the amplifier begins to degrade.
The thermal characteristics of the device are dictated by
the package and the PC board. Maximum power
dissipation for a given package can be calculated using the
following formula.
PDmax +Tmax–TA
qJA
Where:
PDmax is the maximum power dissipation in the amplifier (W).
Tmax is the absolute maximum junction temperature (°C).
TA is the ambient temperature (°C).
θJA = θJC + θCA
θJC is the thermal coefficient from the silicon junctions to the
case (°C/W).
θCA is the thermal coefficient from the case to ambient air
(°C/W).
(28)
For systems where heat dissipation is more critical, the
THS4500 family of devices is offered in an 8-pin MSOP
with PowerPAD. The thermal coefficient for the MSOP
PowerPAD package is substantially improved over the
traditional SOIC. Maximum power dissipation levels are
depicted in the graph for the two packages. The data for
the DGN package assumes a board layout that follows the
PowerPAD layout guidelines referenced above and
detailed in the PowerPAD application notes in the
Additional Reference Material section at the end of the
data sheet.
2
1.5
1
0
−40 −20 0 20
− Maximum Power Dissipation − W
2.5
3
3.5
40 60 80
TA − Ambient Temperature − °C
PD
8-Pin DGN Package
θJA = 170°C/W for 8-Pin SOIC (D)
θJA = 58.4°C/W for 8-Pin MSOP (DGN)
ΤJ = 150°C, No Airflow
Figure 113. Maximum Power Dissipation vs
Ambient Temperature
0.5
8-Pin D Package
When determining whether or not the device satisfies the
maximum power dissipation requirement, it is important to
not only consider quiescent power dissipation, but also
dynamic power dissipation. Often times, this is difficult to
quantify because the signal pattern is inconsistent, but an
estimate of the RMS power dissipation can provide
visibility into a possible problem.
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31
DRIVING CAPACITIVE LOADS
High-speed amplifiers are typically not well-suited for
driving large capacitive loads. If necessary, however, t he
load capacitance should be isolated by two isolation
resistors in series with the output. The requisite isolation
resistor size depends on the value of the capacitance, but
10 to 25 Ω is a good place to begin the optimization
process. Larger isolation resistors decrease the amount of
peaking in the frequency response induced by the
capacitive load, but this comes at the expense of larger
voltage drop across the resistors, increasing the output
swing requirements of the system.
Figure 114
VS
RSRg
Rf
Rf
+
−
RT−
+
Riso
CL
Rg
Riso = 10 − 25 Ω
VS
−VS
Riso
Use of Isolation Resistors With a Capacitive Load.
POWER SUPPLY DECOUPLING
TECHNIQUES AND RECOMMENDATIONS
Power supply decoupling is a critical aspect of any
high-performance amplifier design process. Careful
decoupling provides higher quality ac performance (most
notably improved distortion performance). The following
guidelines ensure the highest level of performance.
1. Place decoupling capacitors as close to the power
supply inputs as possible, with the goal of minimizing
the inductance of the path from ground to the power
supply.
2. Placement priority should be as follows: smaller
capacitors should be closer to the device.
3. Use of solid power and ground planes is
recommended to reduce the inductance along power
supply return current paths.
4. Recommended values for power supply decoupling
include 1 0 - µF and 0.1-µF capacitors for each supply.
A 1000-pF capacitor can be used across the supplies
as well for extremely high frequency return currents,
but often is not required.
EVALUATION FIXTURES, SPICE MODELS,
AND APPLICATIONS SUPPORT
Texas Instruments is committed to providing its customers
with the highest quality of applications support. To support
this goal, an evaluation board has been developed for the
THS4500 family of fully differential amplifiers. The
evaluation board can be obtained by ordering through the
Texas Instruments web site, www.ti.com, or through your
local Texas Instruments sales representative. Schematic
for the evaluation board is shown below with their default
component values. Unpopulated footprints are shown to
provide insight into design flexibility.
Figure 115
_
+
4
5
37
26
VOCM−VS
PwrPad
VSPD
1
8
R0805 R4
C4 C0805
R5 R0805
C3
C0805
R6
R7
R0805
R0805
C5
C6
C0805
C0805
C7
C0805
J2
J3
J2
J3
R2
R0805
R3
R0805
C1
C0805C2
C0805
R1 R1206
J1
3
1
4
5
6
R11
R1206
R9
R0805
R8
R9
R0805
R0805
J2
J3
J4
T1
U1
THS450X
Simplified Schematic of the Evaluation Board. Power
Supply Decoupling, VOCM, and Power Down Circuitry
Not Shown
Computer simulation of circuit performance using SPICE
is often useful when analyzing the performance of analog
circuits and systems. This is particularly true for video and
RF amplifier circuits where parasitic capacitance and
inductance c a n h a v e a m a j o r e ffect on circuit performance.
A SPICE model for the THS4500 family of devices is
available through the Texas Instruments web site
(www.ti.com). The PIC is also available for design
assistance and detailed product information. These
models do a good job of predicting small-signal ac and
transient performance under a wide variety of operating
conditions. They are not intended to model the distortion
characteristics of the amplifier, nor do they attempt to
distinguish between the package types in their
small-signal ac performance. Detailed information about
what is and is not modeled is contained in the model file
itself.
THS4502
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SLOS352D − APRIL 2002 − REVISED JANUARY 2004
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32
ADDITIONAL REFERENCE MATERIAL
DPowerPAD Made Easy, application brief, Texas Instruments Literature Number SLMA004.
DPowerPAD Thermally Enhanced Package, technical brief, Texas Instruments Literature Number SLMA002.
DKarki, James. Fully Differential Amplifiers. application report, Texas Instruments Literature Number SLOA054D.
DKarki, James. Fully Differential Amplifiers Applications: Line Termination, Driving High−Speed ADCs, and Differential
Transmission Lines. Texas Instruments Analog Applications Journal, February 2001.
DCarter, Bruce. A Differential Op-Amp Circuit Collection. application report, Texas Instruments Literature Number
SLOA064.
DCarter, Bruce. Differential Op-Amp Single-Supply Design Technique, application report, Texas Instruments Literature
Number SLOA072.
DKarki, James. Designing for Low Distortion with High-Speed Op Amps. Texas Instruments Analog Applications
Journal, July 2001.
www.ti.com
PowerPAD i s a trademark of Texas In struments
DGN (S-PDSO-G8)
THERMAL INFORMATION
THERMAL PAD MECHANICAL DATA
PPTD041
Exposed Thermal Pad
5
4
8
1
1,78
MAX
1,73
MAX
This PowerPAD™ pack age i ncorporat es an expos ed thermal pad that is designed to be attached directly to an
external heatsink. When t he t herm al pad i s soldered directly to the printed circuit board (PCB), the PCB can be
used as a heatsink. In addi t i on, through t he us e of thermal vias, the thermal pad can be attached directly to a
ground plane or special heatsi nk st ruc ture des i gned i nt o the PCB. This design optimizes the heat transfer from
the integrated circuit (IC).
The exposed thermal pad dimensions for thi s package are shown in the following illustra tion.
For additional inf orm at i on on t he P owerPA D pac k age and how to take advantage of its heat dissipating abilities,
refer to Technical Brief, P owerP AD Th e rmal ly En hanced Package, Texas Instr u ments L iterature No. SLMA002
and Application Brief, PowerPAD Made Easy, Texas Instr u ments L itera ture No . SLMA004. Both documents are
available at www.ti.com.
Exposed Therma l Pad Dimens ions
NOTE: All linear dimensions are in millimeters
Top View
PACKAGING INFORMATION
Orderable Device Status (1) Package
Type Package
Drawing Pins Package
Qty Eco Plan (2) Lead/Ball Finish MSL Peak Temp (3)
THS4502CD ACTIVE SOIC D 8 75 Green (RoHS &
no Sb/Br) CU NIPDAU Level-1-260C-UNLIM
THS4502CDGK ACTIVE MSOP DGK 8 100 Green (RoHS &
no Sb/Br) CU NIPDAU Level-1-260C-UNLIM
THS4502CDGKG4 ACTIVE MSOP DGK 8 100 Green (RoHS &
no Sb/Br) CU NIPDAU Level-1-260C-UNLIM
THS4502CDGKR ACTIVE MSOP DGK 8 2500 Green (RoHS &
no Sb/Br) CU NIPDAU Level-1-260C-UNLIM
THS4502CDGKRG4 ACTIVE MSOP DGK 8 2500 Green (RoHS &
no Sb/Br) CU NIPDAU Level-1-260C-UNLIM
THS4502CDGN ACTIVE MSOP-
Power
PAD
DGN 8 80 Green (RoHS &
no Sb/Br) CU NIPDAU Level-1-260C-UNLIM
THS4502CDGNR ACTIVE MSOP-
Power
PAD
DGN 8 2500 Green (RoHS &
no Sb/Br) CU NIPDAU Level-1-260C-UNLIM
THS4502CDGNRG4 ACTIVE MSOP-
Power
PAD
DGN 8 2500 Green (RoHS &
no Sb/Br) CU NIPDAU Level-1-260C-UNLIM
THS4502CDR ACTIVE SOIC D 8 2500 Green (RoHS &
no Sb/Br) CU NIPDAU Level-1-260C-UNLIM
THS4502CDRG4 ACTIVE SOIC D 8 2500 Green (RoHS &
no Sb/Br) CU NIPDAU Level-1-260C-UNLIM
THS4502ID ACTIVE SOIC D 8 75 Green (RoHS &
no Sb/Br) CU NIPDAU Level-1-260C-UNLIM
THS4502IDG4 ACTIVE SOIC D 8 75 Green (RoHS &
no Sb/Br) CU NIPDAU Level-1-260C-UNLIM
THS4502IDGK ACTIVE MSOP DGK 8 100 Green (RoHS &
no Sb/Br) CU NIPDAU Level-1-260C-UNLIM
THS4502IDGKR ACTIVE MSOP DGK 8 2500 Green (RoHS &
no Sb/Br) CU NIPDAU Level-1-260C-UNLIM
THS4502IDGKRG4 ACTIVE MSOP DGK 8 2500 Green (RoHS &
no Sb/Br) CU NIPDAU Level-1-260C-UNLIM
THS4502IDGN ACTIVE MSOP-
Power
PAD
DGN 8 80 Green (RoHS &
no Sb/Br) CU NIPDAU Level-1-260C-UNLIM
THS4502IDGNG4 ACTIVE MSOP-
Power
PAD
DGN 8 80 Green (RoHS &
no Sb/Br) CU NIPDAU Level-1-260C-UNLIM
THS4502IDGNR ACTIVE MSOP-
Power
PAD
DGN 8 2500 Green (RoHS &
no Sb/Br) CU NIPDAU Level-1-260C-UNLIM
THS4502IDGNRG4 ACTIVE MSOP-
Power
PAD
DGN 8 2500 Green (RoHS &
no Sb/Br) CU NIPDAU Level-1-260C-UNLIM
THS4502IDR ACTIVE SOIC D 8 2500 Green (RoHS &
no Sb/Br) CU NIPDAU Level-1-260C-UNLIM
THS4503CD ACTIVE SOIC D 8 75 Green (RoHS &
no Sb/Br) CU NIPDAU Level-1-260C-UNLIM
THS4503CDGK ACTIVE MSOP DGK 8 100 Green (RoHS &
no Sb/Br) CU NIPDAU Level-1-260C-UNLIM
PACKAGE OPTION ADDENDUM
www.ti.com 13-Sep-2005
Addendum-Page 1
Orderable Device Status (1) Package
Type Package
Drawing Pins Package
Qty Eco Plan (2) Lead/Ball Finish MSL Peak Temp (3)
THS4503CDGKG4 ACTIVE MSOP DGK 8 100 Green (RoHS &
no Sb/Br) CU NIPDAU Level-1-260C-UNLIM
THS4503CDGKR ACTIVE MSOP DGK 8 2500 Green (RoHS &
no Sb/Br) CU NIPDAU Level-1-260C-UNLIM
THS4503CDGKRG4 ACTIVE MSOP DGK 8 2500 Green (RoHS &
no Sb/Br) CU NIPDAU Level-1-260C-UNLIM
THS4503CDGN ACTIVE MSOP-
Power
PAD
DGN 8 80 Green (RoHS &
no Sb/Br) CU NIPDAU Level-1-260C-UNLIM
THS4503CDGNR ACTIVE MSOP-
Power
PAD
DGN 8 2500 Green (RoHS &
no Sb/Br) CU NIPDAU Level-1-260C-UNLIM
THS4503CDGNRG4 ACTIVE MSOP-
Power
PAD
DGN 8 2500 Green (RoHS &
no Sb/Br) CU NIPDAU Level-1-260C-UNLIM
THS4503CDR ACTIVE SOIC D 8 2500 Green (RoHS &
no Sb/Br) CU NIPDAU Level-1-260C-UNLIM
THS4503CDRG4 ACTIVE SOIC D 8 2500 Green (RoHS &
no Sb/Br) CU NIPDAU Level-1-260C-UNLIM
THS4503ID ACTIVE SOIC D 8 75 Green (RoHS &
no Sb/Br) CU NIPDAU Level-1-260C-UNLIM
THS4503IDGK ACTIVE MSOP DGK 8 80 Green (RoHS &
no Sb/Br) CU NIPDAU Level-1-260C-UNLIM
THS4503IDGKR ACTIVE MSOP DGK 8 2500 Green (RoHS &
no Sb/Br) CU NIPDAU Level-1-260C-UNLIM
THS4503IDGKRG4 ACTIVE MSOP DGK 8 2500 Green (RoHS &
no Sb/Br) CU NIPDAU Level-1-260C-UNLIM
THS4503IDGN ACTIVE MSOP-
Power
PAD
DGN 8 80 Green (RoHS &
no Sb/Br) CU NIPDAU Level-1-260C-UNLIM
THS4503IDGNG4 ACTIVE MSOP-
Power
PAD
DGN 8 80 Green (RoHS &
no Sb/Br) CU NIPDAU Level-1-260C-UNLIM
THS4503IDGNR ACTIVE MSOP-
Power
PAD
DGN 8 2500 Green (RoHS &
no Sb/Br) CU NIPDAU Level-1-260C-UNLIM
THS4503IDGNRG4 ACTIVE MSOP-
Power
PAD
DGN 8 2500 Green (RoHS &
no Sb/Br) CU NIPDAU Level-1-260C-UNLIM
THS4503IDR ACTIVE SOIC D 8 2500 Green (RoHS &
no Sb/Br) CU NIPDAU Level-1-260C-UNLIM
THS4503IDRG4 ACTIVE SOIC D 8 2500 Green (RoHS &
no Sb/Br) CU NIPDAU Level-1-260C-UNLIM
(1) The marketing status values are defined as follows:
ACTIVE: Product device recommended for new designs.
LIFEBUY: TI has announced that the device will be discontinued, and a lifetime-buy period is in effect.
NRND: Not recommended for new designs. Device is in production to support existing customers, but TI does not recommend using this part in
a new design.
PREVIEW: Device has been announced but is not in production. Samples may or may not be available.
OBSOLETE: TI has discontinued the production of the device.
(2) Eco Plan - The planned eco-friendly classification: Pb-Free (RoHS) or Green (RoHS & no Sb/Br) - please check
http://www.ti.com/productcontent for the latest availability information and additional product content details.
PACKAGE OPTION ADDENDUM
www.ti.com 13-Sep-2005
Addendum-Page 2
TBD: The Pb-Free/Green conversion plan has not been defined.
Pb-Free (RoHS): TI's terms "Lead-Free" or "Pb-Free" mean semiconductor products that are compatible with the current RoHS requirements
for all 6 substances, including the requirement that lead not exceed 0.1% by weight in homogeneous materials. Where designed to be soldered
at high temperatures, TI Pb-Free products are suitable for use in specified lead-free processes.
Green (RoHS & no Sb/Br): TI defines "Green" to mean Pb-Free (RoHS compatible), and free of Bromine (Br) and Antimony (Sb) based flame
retardants (Br or Sb do not exceed 0.1% by weight in homogeneous material)
(3) MSL, Peak Temp. -- The Moisture Sensitivity Level rating according to the JEDEC industry standard classifications, and peak solder
temperature.
Important Information and Disclaimer:The information provided on this page represents TI's knowledge and belief as of the date that it is
provided. TI bases its knowledge and belief on information provided by third parties, and makes no representation or warranty as to the
accuracy of such information. Efforts are underway to better integrate information from third parties. TI has taken and continues to take
reasonable steps to provide representative and accurate information but may not have conducted destructive testing or chemical analysis on
incoming materials and chemicals. TI and TI suppliers consider certain information to be proprietary, and thus CAS numbers and other limited
information may not be available for release.
In no event shall TI's liability arising out of such information exceed the total purchase price of the TI part(s) at issue in this document sold by TI
to Customer on an annual basis.
PACKAGE OPTION ADDENDUM
www.ti.com 13-Sep-2005
Addendum-Page 3
IMPORTANT NOTICE
Texas Instruments Incorporated and its subsidiaries (TI) reserve the right to make corrections, modifications,
enhancements, improvements, and other changes to its products and services at any time and to discontinue
any product or service without notice. Customers should obtain the latest relevant information before placing
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TI warrants performance of its hardware products to the specifications applicable at the time of sale in
accordance with TI’s standard warranty. Testing and other quality control techniques are used to the extent TI
deems necessary to support this warranty. Except where mandated by government requirements, testing of all
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TI assumes no liability for applications assistance or customer product design. Customers are responsible for
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