SBVS028B − DECEMBER 2000 − REVISED DECEMBER 2007
FEATURES
DUL1950 Recognized
DDIP-18 and SO-10 Packages
D55 W/in3 (3.3 W/cm3) Power Density
DDevice-to-Device Synchronization
DThermal Protection
D1000 Vrms Isolation
D400 kHz Switching
D125 FITS at 55°C
DShort-Circuit Protection
D12−V, 24−V Inputs
D5−V Outputs
APPLICATIONS
DPoint-of-Use Power Conversion
DDigital Interface Power
DGround Loop Elimination
DPower-Supply Noise Reduction
DESCRIPTION
The DCR02 family is a series of high-efficiency,
input-isolated, output-regulated DC/DC converters. In
addition to 2−W nominal, galvanically-isolated output
power capability, this range of converters offers very low
output noise and high accuracy.
The DCR02 family is implemented in standard molded
device packaging, providing standard JEDEC outlines
suitable for high-volume assembly.
The DCR is manufactured using the same technology as
standard device packages, thereby achieving very high
reliability.
Input
Controller LDO
Regulator
ENABLE
VRECSYNC
VSERROR
VOUT
0VIN 0VOUT
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Please be aware that an important notice concerning availability, standard warranty, and use in critical applications of Texas Instruments
semiconductor products and disclaimers thereto appears at the end of this data sheet.
All trademarks are the property of their respective owners.
! "# $ " %&$ ' !$
$"# %$"$ % ( # " ) # *+'
!$ %$, $+ $ , " %#'
SBVS028B − DECEMBER 2000 − REVISED DECEMBER 2007
www.ti.com
2
This integrated circuit can be damaged by ESD. Texas Instruments recommends that all integrated circuits be handled with appropriate
precautions. Failure to observe proper handling and installation procedures can cause damage.
ESD damage can range from subtle performance degradation to complete device failure. Precision integrated circuits may be more susceptible to
damage because very small parametric changes could cause the device not to meet its published specifications.
ORDERING INFORMATION(1)
PRODUCT PACKAGE-LEAD PACKAGE
DESIGNATOR
SPECIFIED
TEMPERATURE
RANGE
PACKAGE
MARKING ORDERING
NUMBER TRANSPORT MEDIA,
QUANTITY
DIP−18 NVE −40°C to +70°C DCR021205P DCR021205P Rail, 20
DCR021205 SO−10(2) DVS −40°C to +70°C DCR021205P−U DCR021205P−U Rail, 20
DCR021205
SO−10(2) DVS −40°C to +70°C DCR021205P−U DCR021205P−U/700 Tape and Reel, 700
DIP−18 NVE −40°C to +70°C DCR022405P DCR022405P Rail, 20
DCR022405 SO−10(2) DVS −40°C to +70°C DCR022405P−U DCR022405P−U Rail, 20
DCR022405
SO−10(2) DVS −40°C to +70°C DCR022405P−U DCR022405P−U/700 Tape and Reel, 700
(1) For the most current package and ordering information, refer to our web site at www.ti.com.
(2) SO−10 packages have 18 pins, but only 10 pins are active.
SUPPLEMENTAL ORDERING INFORMATION
Basic Model Number: 2−W Product
Voltage Input:
12V In
Voltage Output:
5V Out
Package Code:
P = 18-Pin Plastic DIP
P-U = SO-10
DCR02 12 05 (P)
PIN ASSIGNMENTS
NVE and DVS
PACKAGES
(TOP VIEW)
DCR02
1
2
7
8
9
18
17
12
11
10
VS
NC
VREC
0VOUT
VO
SYNC
0VIN
ERROR
ENABLE
DNC
ABSOLUTE MAXIMUM RATINGS
over o p e rating free-air temperature range unless otherwise noted(1)
DCR02
SERIES UNIT
Input Voltage
DCR0212 15 V
Input Voltage
DCR0224 29 V
Storage Temperature −60 to +125 °C
Lead Temperature (wave soldering, 10s) + 260 °C
(1) Stresses above these ratings may cause permanent damage.
Exposure to absolute maximum conditions for extended periods
may degrade device reliability. These are stress ratings only, an d
functional operation of the device at these or any other conditions
beyond those specified is not implied.
Terminal Functions
TERMINAL
NAME NO. I/O DESCRIPTION
VS1 I Voltage input
NC 2 No connection
VREC 7 O Rectified output
0VOUT 8 O Output ground
VO9 O Voltage output
DNC 10 Do not connect
ENABLE 11 OOutput voltage enable
ERROR 12 O Error flag active low
0VIN 17 I Input ground
SYNC 18 I Synchronization input
NOTE:I = input and O = output.
SBVS028B − DECEMBER 2000 − REVISED DECEMBER 2007
www.ti.com
3
ELECTRICAL CHARACTERISTICS
At TA = +25°C, VS = nominal, IOUT = 10mA, COUT = 0.1µF ceramic, and CIN = 2.2µF ceramic, unless otherwise noted(1).
DCR02 SERIES
PARAMETER TEST CONDITIONS MIN TYP MAX UNITS
OUTPUT
Setpoint
DCR021205 5 V
Setpoint
DCR022405 5 V
Setpoint accuracy 0.5% 2.0%
Maximum output
current
DCR021205 400 mA
Maximum output
current DCR022405 400 mA
Output short-circuit protected Duration Infinite
Line regulation
DCR021205 1 mV/V
Line regulation
DCR022405 1 mV/V
Over line and load 10mA to 400mA load, over input voltage range 1.0% 2.5%
Versus temperature −40°C to +70°C 1.0%
DCR0212 ripple 20−MHz bandwidth, 50% load(1) 18 mVPP
Ripple and noise
DCR0212 noise 100−MHz bandwidth, 50% load(1) 20 mVPP
Ripple and noise
DCR0224 ripple 20−MHz bandwidth, 50% load(1) 18 mVPP
DCR0224 noise 100−MHz bandwidth, 50% load(1) 25 mVPP
INPUT
Nominal voltage, VS
DCR021205 12 V
Nominal voltage, V
SDCR022405 24 V
Voltage range −10% +10%
IO = 0 mA 15 mA
DCR021205 IO = 10 mA 23 mA
Supply current
DCR021205
IO = 400 mA 250 mA
Supply current
IO = 0 mA 15 mA
DCR022405 IO = 10 mA 17 mA
DCR022405
IO = 400 mA 129 mA
Reflected ripple current 20−M Hz bandwidth, 100% load(1) 8 mAPP
ISOLATION
Voltage
1−s flash test 1 kVrms
Voltage
60−s test, UL1950(2) 1 kVrms
Input/output capacitance 25 pF
OUTPUT ENABLE CONTROL
Logic high input voltage 2.0 VREC V
Logic high input current 2.0 < VENABLE < VREC 100 nA
Logic low input voltage −0.2 0.5 V
Logic low input current 0 < VENABLE < 0.5 100 nA
ERROR FLAG
Logic high open collector leakage VERROR = 5 V 10 µA
Logic low output voltage Sinking 2 mA 0.4 V
THERMAL SHUTDOWN
Junction temperature
Temp activated +150 °C
Junction temperature
Temp deactivated +130 °C
(1) Ceramic capacitors, CIN = 2.2 µF, CFILTER = 1 µF, and COUT = 0.1 µF.
(2) During UL1950 recognition test only.
SBVS028B − DECEMBER 2000 − REVISED DECEMBER 2007
www.ti.com
4
ELECTRICAL CHARACTERISTICS (continued)
At TA = +25°C, VS = nominal, IOUT = 10mA, COUT = 0.1µF ceramic, and CIN = 2.2µF ceramic, unless otherwise noted(1).
DCR02 SERIES
PARAMETER UNITSMAXTYPMINTEST CONDITIONS
Synchronization Pin
Max external capacitance on SYNC pin 3 pF
Internal oscillator frequency 720 800 880 kHz
External synchronization frequency 720 880 kHz
External synchronization signal high 2.5 2.5 5.0 V
External synchronization signal low 0 0.4 V
Temperature Range
Operating −40 +70 °C
(1) Ceramic capacitors, CIN = 2.2 µF, CFILTER = 1 µF, and COUT = 0.1 µF.
(2) During UL1950 recognition test only.
TYPICAL CHARACTERISTICS
Figure 1
0 40030025015050
30
0
10
100
20
40
90
VI (V)
21.5
22.5
23.0
24.0
25.0
26.0
70
50
60
80
100 200 350
26.0 V
25.0 V 24.0 V
26.0 V
25.0 V
23.0 V
η − Efficiency − %
IO − Output Current − mA
EFFICIENCY
vs
OUTPUT CURRENT
DCR022405
Figure 2
100
40
90
70
50
60
80
0 40030025015050 100 200 350
13.2 V
12.8 V
12.3 V
10.8 V
11.3 V
11.8 V
VI (V)
10.8
11.3
11.8
12.3
12.8
13.2
IO − Output Current − mA
η − Efficiency − %
DCR021205
EFFICIENCY
vs
OUTPUT CURRENT
SBVS028B − DECEMBER 2000 − REVISED DECEMBER 2007
www.ti.com
5
FUNCTIONAL DESCRIPTION
OVERVIEW
The DCR02 series offers isolation from an unregulated
power supply operating from a choice of input voltages.
This series provides a variety of regulated output voltages
at a nominal output power of 2 W.
POWER STAGE
The input supply is chopped at a frequency of 400 kHz
(internal oscillator divided by 2), which is used to drive the
center-tapped toroidal transformer.
RECTIFICATION
The transformer output is full wave rectified and smoothed
by the external capacitor connected to VREC.
REGULATOR
The internal low-dropout regulator provides a
well-regulated output voltage throughout the operating
range of the device.
OSCILLATOR AND WATCHDOG
The DCR02 uses an internal saw-tooth generator to
provide the 800−kHz onboard oscillator that is used to
drive the power switching circuit. The operation of the
oscillator is monitored by the watchdog, which three-states
the output driver circuit if the oscillator fails or if the SYNC
pin is taken low (shutdown mode). When the SYNC pin is
returned high, normal operation resumes.
SYNCHRONIZATION
If more than one DCR02 is being used, beat frequencies
and other electrical interference can be generated. This
interference is due to the small variations in switching
frequencies between the converters. The DCR02
overcomes this by allowing devices to be synchronized to
one another. Up to eight devices can be synchronized by
connecting the SYNC pins together, with care being taken
to minimize the capacitance of tracking.
Significant stray capacitance on the SYNC pin reduces the
frequency of the internal oscillator. If this reduction is large,
the DCR02 may be taken out with its optimized operating
parameters, and saturation of the magnetics may result,
damaging the device.
If devices are synchronized, it should be noted that all
devices draws maximum current simultaneously at start
up. This can cause the input voltage to dip. Should it fall
below the minimum input voltage, the devices may not
start up. A low equivalent series resistance (ESR) 2.2−µF
ceramic capacitor should be connected as close to the
device input pins as possible.
If more than eight devices are required to be synchronized,
it is recommended that external synchronization be used.
Details of this procedure are contained in application
report SBAA035, External Synchronization of the
DCP01/02 Series of DC/DC Converters, available for
download at www.ti.com.
CONSTRUCTION
The DCR02 is manufactured using the same technology
as standard IC packages. There is no substrate within the
package. The DCR02 is constructed using a driver IC,
low-dropout voltage regulator, rectifier diodes, and a
wound magnetic toroid, all mounted on a leadframe. The
DCR02 requires no special printed circuit board (PCB)
assembly processing, since there is no solder within the
package. The result is an isolated DC/DC converter with
inherently high reliability.
SBVS028B − DECEMBER 2000 − REVISED DECEMBER 2007
www.ti.com
6
ADDITIONAL FUNCTIONS
DISABLE/ENABLE
The DCR02 can be disabled or enabled by driving the
SYNC pin using an open drain CMOS gate. If the SYNC
pin is pulled low, the DCR02 is disabled. The disable time
depends upon the external loading. The internal disable
function is implemented in 2 µs. Removal of the pull down
enables the DCR02.
Capacitance loading on the SYNC pin should be
minimized in order to prevent a reduction in the internal
oscillator frequency. See application report SBAA035 for
information on how to nullify the effects of additional
capacitance on the SYNC pin. The oscillator frequency
can be measured at VREC, as this is the fundamental
frequency of the ripple component.
OUTPUT ENABLE/DISABLE
The regulated output of the DCR02 can be disabled by
pulling the ENABLE pin low (by connecting ENABLE to
0VOUT). Holding the ENABLE pin high (connect ENABLE
to VREC) enables the regulated output voltage, thus
allowing the output to be controlled from the isolated side,
as shown in Figure 3.
ERROR FLAG
The DCR02 has an ERROR pin which provides a power
good flag, as long as the internal regulator is in regulation.
DECOUPLING
Ripple Reduction
Due to the very low forward resistance of the DMOS
switching transistors, high-current demands are placed
upon the input supply for a short time. By placing a good
quality low ESR 2.2−µF ceramic capacitor close to the IC
supply input pins, the effects on the power supply can be
minimized.
The high switching frequency of 400 kHz allows relatively
small values of capacitors to be used for filtering the
rectified output voltage. A good quality, low ESR 1µF
ceramic capacitor placed close to the VREC pin and output
ground reduces the ripple.
It is not recommended that the DCR02 be fitted using an
IC socket because this degrades performance.
The output at VREC is full wave rectified and produces a
ripple of 800 kHz.
It is recommended that a 0.1−µF, low ESR ceramic
capacitor be connected close to the output pin and ground
to reduce noise on the output. The capacitor values listed
are minimum values. If lower ripple is required, the ceramic
filter capacitor should be increased in value to 2.2µF.
NOTE: As with all switching power supplies, the best
performance is only obtained with low ESR ceramic
capacitors connected close to the respective buses. If low
ESR ceramic capacitors a re n ot used, the ESR generates a
voltage drop w hen t he c apacitor i s s upplying the load p ower.
Often a larger capaci tor is chosen for this purpose when a
low ESR smal ler capacitance performs just as well .
DCR 02
VOUT
VIN
CIN(1) COUT
0.1µF
RERR
10kΩ
REN
10kΩ
CFILTER
1µF
VO1
0VOUT
0V
ENABLE
VREC
ERROR
VS
U1
0V
SYNC
ERROR
SW1
(see text)
NOTE: (1) Required 2.2µF low ESR ceramic capacitor.
Figure 3. DCR02 with a Single Output
SBVS028B − DECEMBER 2000 − REVISED DECEMBER 2007
www.ti.com
7
APPLICATION NOTES
DCR02 SINGLE VOLTAGE OUTPUT
The DCR02 can be used to provide a single voltage output
by connecting the circuit as shown in Figure 3. The
ERROR output signal is pulled up to the value of VOUT for
the particular DCR02 being used. The value of RERR
depends on the loading on the ERROR line; however, the
total load on the ERROR line must not exceed the value
given in the specification.
The output can be permanently enabled by connecting the
ENABLE pin to the VREC pin. The DCR02 can be enabled
remotely by connecting the ENABLE pin to VREC via a
pull-up resistor (REN); the value of this resistor is not critical
for the DCR02 since only a small current flows. Switch
SW1 can be used to pull the ENABLE pin low, thus
disabling the output. The switching devices can be a
bipolar transistor, FET, or a mechanical device; the main
load that it senses is REN.
GENERATING TWO POSITIVE OUTPUT
VOLTAGES
Two DCR02s can be used to create two +5−V output
voltages, as shown in Figure 4. The two DCR02s are
connected in self-synchronization, thus locking the
oscillators of both devices to a single frequency.
The ERROR and ENABLE facilities can be used in a
similar configuration for a single DCR02. The filter
capacitors connected to the VREC pins (CFILTER) should be
kept separate from each other and connected in close
proximity to the respective DCR02. If similar output
voltages are being used, it is not recommended that a
single filter capacitor (with an increased capacitance) be
used with both VREC pins connected together, since this
could result in the overloading of one of the devices.
DCR 02
VOUT
VIN
COUT
0.1µF
RERR
10kΩ
CFILTER
1µF
CFILTER
1µF
VO1
0V
ENABLE
VREC
ERROR
VS
U1
0V
SYNC
ERROR
DCR 02
VOUT
VIN
COUT
0.1µF
RERR
10kΩ
VO2
0V
ENABLE
VREC
ERROR
VS
U2
0V
SYNC
0VOUT
ERROR
CIN(1)
CIN(1)
NOTE: (1) Required 2.2µF low ESR ceramic capacitor.
Figure 4. Generating Two Positive Voltages from Self-Synchronized DCR02s
SBVS028B − DECEMBER 2000 − REVISED DECEMBER 2007
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8
GENERATION OF DUAL POLARITY
VOLTAGES FROM TWO
SELF-SYNCHRONIZED DCR02s
Two DCR02s can be configured to produce a dual polarity
supply (that is, ±5 V); the circuit must be connected as
shown in Figure 5.
It should be observed that both DCR02s are positive
voltage regulators; therefore the ERROR, ENABLE, and
VREC pins are relative to their respective devices, 0 V, and
must not be connected together.
PCB LAYOUT
RIPPLE AND NOISE
Careful consideration should be given to the layout of the
PCB in order for the best results to be obtained.
The DCR02 is a switching power supply and as such can
place high peak current demands on the input supply. In
order to avoid the supply falling momentarily during the
fast switching pulses, ground and power planes should be
used to track the power to the input of DCR02; this also
serves to reduce noise on the circuit. If this is not possible,
the supplies must be connected in a star formation, with
the tracks made as wide as possible.
If the SYNC pin is being used, the tracking between device
SYNC pins should be short, to avoid stray capacitance. If
the SYNC pin is not being used, it is advisable to place a
guard ring (connected to input ground) around this pin to
avoid any noise pickup.
The output should be taken from the device using ground
and power planes. This ensures minimum losses.
A good quality, low ESR ceramic capacitor placed as close
as practical across the input reduces reflected ripple and
ensure a smooth startup.
Additionally, a good quality, low ESR ceramic capacitor
placed as close as practical across the rectifier output
terminal and output ground also gives the best ripple and
noise performance.
THERMAL MANAGEMENT
Due to the high power density of this device, it is advisable
to provide a ground plane on the output. The output
regulator is mounted on a copper leadframe, and a ground
plane serves as an efficient heatsink.
DCR 02
VOUT
VIN
COUT
0.1µF
CFILTER
1µF
VPOS O/P
VNEG O/P
0V
ENABLE
VREC
ERROR
VS
U1
0V
SYNC
DCR 02
VOUT
VIN
COUT
0.1µF
CFILTER
1µF
0V
ENABLE
VREC
ERROR
VS
U2
0V
SYNC
0V
CIN(1)
CIN(1)
NOTE: (1) Required 2.2µF low ESR ceramic capacitor.
Figure 5. Dual Polarity Voltage Generation from Two Self-Synchronized DCR02s
PACKAGING INFORMATION
Orderable Device Status (1) Package
Type Package
Drawing Pins Package
Qty Eco Plan (2) Lead/Ball Finish MSL Peak Temp (3)
DCR021205P ACTIVE PDIP NVE 10 20 Pb-Free
(RoHS) CU NIPDAU N / A for Pkg Type
DCR021205P-U ACTIVE SOP DVS 10 20 Pb-Free
(RoHS) CU NIPDAU Level-3-260C-168 HR
DCR022405P ACTIVE PDIP NVE 10 20 Pb-Free
(RoHS) CU NIPDAU N / A for Pkg Type
DCR022405P-U ACTIVE SOP DVS 10 20 Pb-Free
(RoHS) CU NIPDAU Level-3-260C-168 HR
DCR022405P-U/700 ACTIVE SOP DVS 10 700 Pb-Free
(RoHS) CU NIPDAU Level-3-260C-168 HR
(1) The marketing status values are defined as follows:
ACTIVE: Product device recommended for new designs.
LIFEBUY: TI has announced that the device will be discontinued, and a lifetime-buy period is in effect.
NRND: Not recommended for new designs. Device is in production to support existing customers, but TI does not recommend using this part in
a new design.
PREVIEW: Device has been announced but is not in production. Samples may or may not be available.
OBSOLETE: TI has discontinued the production of the device.
(2) Eco Plan - The planned eco-friendly classification: Pb-Free (RoHS), Pb-Free (RoHS Exempt), or Green (RoHS & no Sb/Br) - please check
http://www.ti.com/productcontent for the latest availability information and additional product content details.
TBD: The Pb-Free/Green conversion plan has not been defined.
Pb-Free (RoHS): TI's terms "Lead-Free" or "Pb-Free" mean semiconductor products that are compatible with the current RoHS requirements
for all 6 substances, including the requirement that lead not exceed 0.1% by weight in homogeneous materials. Where designed to be soldered
at high temperatures, TI Pb-Free products are suitable for use in specified lead-free processes.
Pb-Free (RoHS Exempt): This component has a RoHS exemption for either 1) lead-based flip-chip solder bumps used between the die and
package, or 2) lead-based die adhesive used between the die and leadframe. The component is otherwise considered Pb-Free (RoHS
compatible) as defined above.
Green (RoHS & no Sb/Br): TI defines "Green" to mean Pb-Free (RoHS compatible), and free of Bromine (Br) and Antimony (Sb) based flame
retardants (Br or Sb do not exceed 0.1% by weight in homogeneous material)
(3) MSL, Peak Temp. -- The Moisture Sensitivity Level rating according to the JEDEC industry standard classifications, and peak solder
temperature.
Important Information and Disclaimer:The information provided on this page represents TI's knowledge and belief as of the date that it is
provided. TI bases its knowledge and belief on information provided by third parties, and makes no representation or warranty as to the
accuracy of such information. Efforts are underway to better integrate information from third parties. TI has taken and continues to take
reasonable steps to provide representative and accurate information but may not have conducted destructive testing or chemical analysis on
incoming materials and chemicals. TI and TI suppliers consider certain information to be proprietary, and thus CAS numbers and other limited
information may not be available for release.
In no event shall TI's liability arising out of such information exceed the total purchase price of the TI part(s) at issue in this document sold by TI
to Customer on an annual basis.
PACKAGE OPTION ADDENDUM
www.ti.com 16-Apr-2009
Addendum-Page 1
TAPE AND REEL INFORMATION
*All dimensions are nominal
Device Package
Type Package
Drawing Pins SPQ Reel
Diameter
(mm)
Reel
Width
W1 (mm)
A0 (mm) B0 (mm) K0 (mm) P1
(mm) W
(mm) Pin1
Quadrant
DCR022405P-U/700 SOP DVS 10 700 330.0 32.4 11.0 20.0 5.7 16.0 32.0 Q1
PACKAGE MATERIALS INFORMATION
www.ti.com 11-Mar-2008
Pack Materials-Page 1
*All dimensions are nominal
Device Package Type Package Drawing Pins SPQ Length (mm) Width (mm) Height (mm)
DCR022405P-U/700 SOP DVS 10 700 406.0 348.0 63.0
PACKAGE MATERIALS INFORMATION
www.ti.com 11-Mar-2008
Pack Materials-Page 2
MECHANICAL DATA
MPDS113 – OCTOBER 2001
1
POST OFFICE BOX 655303 • DALLAS, TEXAS 75265
DVS (R-PDSO-G10/18) PLASTIC SMALL-OUTLINE PACKAGE
C
C
C
4203553/B 09/01
0.920 (23,37)
0.880 (22,35)
0.240 (6,10)
0.280 (7,11)
0.070 (1,78)
0.045 (1,14) 0.210 (5,33)
0.115 (2,92)
0.195 (4,95)
MAX
Full Lead
MIN 4 PL
0.005 (0,13)
Plane
Seating
0.300 (7,62)
0.325 (8.26)
0.420 (10,70)
0.045 (1,15)
0.057 (1,45)
Index
Area
0.015 (0,38)
MIN
Plane
Base
0.022 (0,56)
0.014 (0,36)
19
1018
C
L
0.100 (2,54)
0.405 (10,30)
0.025 (0,65)
0.043 (1,10) 0.008 (0,20)
0.014 (0,36)
0°± 5°
D
NOTES: A. All linear dimensions are in inches (millimeters).
B. This drawing is subject to change without notice.
C. Dimensions do not include mold flash or protrusions.
Mold flash or protrusions shall not exceed 0.010 (0,25).
D. Maximum dimension does not include dambar
protrusions. Dambar protrusions shall not exceed 0.010 (0,25)
E. Distance between leads including dambar protrusions
to be 0.005 (0,13) minimum.
F. A visual index feature must be located within the
cross–hatched area.
G. For automatic insertion, any raised irregularity on the top
surface (step, mesa, etc.) shall be symmetrical about
the lateral and longitudinal package centerlines.
MECHANICAL DATA
MPDI055 – APRIL 2001
1
POST OFFICE BOX 655303 • DALLAS, TEXAS 75265
NVE (R-PDIP-T10/18) PLASTIC DUAL-IN-LINE
0.300 (7,63)
4202497/A 03/01
0.014 (0,36)
0.008 (0,20)
0.060 (1,52)
0.300 (7,62)
0.325 (8,26)
MIN 4 PL
Full Lead
0.115 (2,92)
0.150 (3,81)
0.115 (2,92)
0.195 (4,95)0.070 (1,78)
0.045 (1,14)
0.014 (0,36)
0.022 (0,56)
Area
1
18
9
10
0.280 (7,11)
0.240 (6,10)
0.920 (23,37)
0.880 (22,35)
Index
–C–
0.010 (0,25) C
0.100 (2,54)
0.430 (10,92)
MAX
Seating
Plane
Plane
Base
0.005 (0,13)
0.015 (0,38)
MIN
0.210 (5,33)
MAX
0.000 (0,00)
M
D
E
F
F
D
E
D
NOTES: A. All linear dimensions are in inches (millimeters).
B. This drawing is subject to change without notice.
C. Falls within JEDEC MS-001-AC with the exception
of lead count.
D. Dimensions do not include mold flash or protrusions.
Mold flash or protrusions shall not exceed 0.010 (0,25).
E. Dimensions measured with the leads constrained to be
perpendicular to Datum C.
F. Dimensions are measured at the lead tips with the
leads unconstrained.
G. A visual index feature must be located within the
cross-hatched area.
IMPORTANT NOTICE
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