MT4LC16M4G3TG-6S - Micron - Datasheet.Directory

16 Meg x 4 EDO DRAM Micron Technology, Inc., reserves the right to change products or specifications without notice.

16 MEG x 4

EDO DRAM

16 MEG x 4 EDO DRAM PART NUMBERS

REFRESH

PART NUMBER ADDRESSING PACKAGE REFRESH

MT4LC16M4H9DJ-x 4K SOJ Standard

MT4LC16M4H9DJ-x S 4K SOJ Self

MT4LC16M4H9TG-x 4K TSOP Standard

MT4LC16M4H9TG-x S 4K TSOP Self

MT4LC16M4G3DJ-x 8K SOJ Standard

MT4LC16M4G3DJ-x S 8K SOJ Self

MT4LC16M4G3TG-x 8K TSOP Standard

MT4LC16M4G3TG-x S 8K TSOP Self

x = speed

FEATURES

• Single +3.3V ±0.3V power supply

• Industry-standard x4 pinout, timing, functions,

and packages

• 12 row, 12 column addresses (H9) or

13 row, 11 column addresses (G3)

• High-performance CMOS silicon-gate process

• All inputs, outputs and clocks are LVTTL-compat-

ible

• Extended Data-Out (EDO) PAGE MODE access

• Optional self refresh (S) for low-power data

retention

• 4,096-cycle CAS#-BEFORE-RAS# (CBR) REFRESH

distributed across 64ms

OPTIONS MARKING

• Refresh Addressing

4,096 (4K) rows H9

8,192 (8K) rows G3

• Plastic Packages

32-pin SOJ (400 mil) DJ

32-pin TSOP (400 mil) TG

• Timing

50ns access -5

60ns access -6

• Refresh Rates

Standard Refresh None

Self Refresh (128ms period) S*

NOTE: 1. The 16 Meg x 4 EDO DRAM base number

differentiates the offerings in one place—

MT4LC16M4H9. The fifth field distinguishes the

address offerings: H9 designates 4K addresses and

G3 designates 8K addresses.

2. The “#” symbol indicates signal is active LOW.

*Contact factory for availability

Part Number Example:

MT4LC16M4H9DJ-6

PIN ASSIGNMENT (Top View)

DRAM MT4LC16M4G3, MT4LC16M4H9

For the latest data sheet, please refer to the Micron Web

site: www.micronsemi.com/mti/msp/html/datasheet.html

32-Pin SOJ 32-Pin TSOP

DQ0

DQ1

WE#

RAS#

Vss

DQ3

DQ2

CAS#

OE#

NC/A12**

A11

A10

Vss

DQ0

DQ1

WE#

RAS#

Vss

DQ3

DQ2

CAS#

OE#

NC/A12**

A11

A10

Vss

KEY TIMING PARAMETERS

SPEED tRC tRAC tPC tAA tCAC tCAS

-5 84ns 50ns 20ns 25ns 13ns 8ns

-6 104ns 60ns 25ns 30ns 15ns 10ns

**NC on H9 version, A12 on G3 version

GENERAL DESCRIPTION

The 16 Meg x 4 DRAM is a high-speed CMOS,

dynamic random-access memory device containing

67,108,864 bits and designed to operate from 3V to

3.6V. The MT4LC16M4H9 and MT4LC16M4G3 are

functionally organized as 16,777,216 locations con-

taining 4 bits each. The 16,777,216 memory locations

are arranged in 4,096 rows by 4,096 columns on the H9

version and 8,192 rows by 2,048 columns on the G3

version. During READ or WRITE cycles, each location is

16 Meg x 4 EDO DRAM Micron Technology, Inc., reserves the right to change products or specifications without notice.

16 MEG x 4

EDO DRAM

FUNCTIONAL BLOCK DIAGRAM

MT4LC16M4G3 (13 row addresses)

A10

A11

A12

RAS#

NO. 2 CLOCK

GENERATOR

REFRESH

CONTROLLER

NO. 1 CLOCK

GENERATOR V

WE#

CAS#

CONTROL

LOGIC

COLUMN-

ADDRESS

BUFFER(11)

ROW-

ADDRESS

BUFFERS (13) 8,192

2,048

COLUMN

DECODER

OE#

DQ0

DQ1

DQ2

DQ3

REFRESH

COUNTER

ROW SELECT

ROW

DECODER

2,048

SENSE AMPLIFIERS

I/O GATING

DATA-OUT

BUFFER

DATA-IN

BUFFER

8,192 x 2,048 x 4

MEMORY

ARRAY

COMPLEMENT

SELECT

8,192

FUNCTIONAL BLOCK DIAGRAM

MT4LC16M4H9 (12 row addresses)

A10

A11

RAS#

NO. 2 CLOCK

GENERATOR

REFRESH

CONTROLLER

NO. 1 CLOCK

GENERATOR VDD

VSS

WE#

CAS#

CONTROL

LOGIC

COLUMN-

ADDRESS

BUFFER(12)

ROW-

ADDRESS

BUFFERS (12) 4,096

4,096

COLUMN

DECODER

OE#

DQ0

DQ1

DQ2

DQ3

REFRESH

COUNTER

ROW SELECT

ROW

DECODER

4,096

SENSE AMPLIFIERS

I/O GATING

DATA-OUT

BUFFER

DATA-IN

BUFFER

4,096 x 4,096 x 4

MEMORY

ARRAY

COMPLEMENT

SELECT

4,096

16 Meg x 4 EDO DRAM Micron Technology, Inc., reserves the right to change products or specifications without notice.

16 MEG x 4

EDO DRAM

uniquely addressed via the address bits. First, the row

address is latched by the RAS# signal, then the column

address is latched by CAS#. The device provides EDO-

PAGE-MODE operation, allowing for fast successive

data operations (READ, WRITE, or READ-MODIFY-

WRITE) within a given row.

The 16 Meg x 4 DRAM must be refreshed periodically

in order to retain stored data.

DRAM ACCESS

Each location in the DRAM is uniquely addressable,

as mentioned in the General Description. The data for

each location is accessed via the four I/O pins (DQ0-

DQ3). A logic HIGH on WE# dictates read mode, while

a logic LOW on WE# dictates write mode. During a

WRITE cycle, data-in (D) is latched by the falling edge

of WE# or CAS#, whichever occurs last. An EARLY

WRITE occurs when WE# is taken LOW prior to CAS#

falling. A LATE WRITE or READ-MODIFY-WRITE occurs

when WE# falls after CAS# is taken LOW. During

EARLY WRITE cycles, the data outputs (Q) will remain

High-Z, regardless of the state of OE#. During LATE

WRITE or READ-MODIFY-WRITE cycles, OE# must be

taken HIGH to disable the data outputs prior to apply-

ing input data. If a LATE WRITE or READ-MODIFY-

WRITE is attempted while keeping OE# LOW, no WRITE

will occur, and the data outputs will drive read data

from the accessed location.

EDO PAGE MODE

DRAM READ cycles have traditionally turned the

output buffers off (High-Z) with the rising edge of

CAS#. If CAS# went HIGH and OE# was LOW (active),

the output buffers would be disabled. The 16 Meg x 4

DRAM offers an accelerated page mode cycle by elimi-

nating output disable from CAS# HIGH. This option is

called EDO and it allows CAS# precharge time (tCP) to

occur without the output data going invalid (see READ

and EDO-PAGE-MODE READ waveforms).

EDO operates like any DRAM READ or FAST-PAGE-

MODE READ, except data is held valid after CAS# goes

HIGH, as long as RAS# and OE# are held LOW and WE#

is held HIGH. OE# can be brought LOW or HIGH while

CAS# and RAS# are LOW, and the DQs will transition

between valid data and High-Z. Using OE#, there are

two methods to disable the outputs and keep them

disabled during the CAS# HIGH time. The first method

is to have OE# HIGH when CAS# transitions HIGH and

keep OE# HIGH for tOEHC thereafter. This will disable

the DQs, and they will remain disabled (regardless of

the state of OE# after that point) until CAS# falls again.

The second method is to have OE# LOW when CAS#

transitions HIGH and then bring OE# HIGH for a

minimum of tOEP anytime during the CAS# HIGH

period. This will disable the DQs, and they will remain

disabled (regardless of the state of OE# after that point)

until CAS# falls again. (Please refer to Figure 1.) During

other cycles, the outputs are disabled at tOFF time after

RAS# and CAS# are HIGH or at tWHZ after WE# transi-

tions LOW. The tOFF time is referenced from the rising

edge of RAS# or CAS#, whichever occurs last. WE# can

also perform the function of disabling the output

drivers under certain conditions, as shown in Figure 2.

EDO-PAGE-MODE operations are always initiated

with a row address strobed in by the RAS# signal,

followed by a column address strobed in by CAS#, just

like for single location accesses. However, subsequent

column locations within the row may then be accessed

at the page mode cycle time. This is accomplished by

cycling CAS# while holding RAS# LOW and entering

new column addresses with each CAS# cycle. Returning

RAS# HIGH terminates the EDO-PAGE-MODE opera-

tion.

DRAM REFRESH

The supply voltage must be maintained at the speci-

fied levels, and the refresh requirements must be met in

order to retain stored data in the DRAM. The refresh

requirements are met by refreshing all 8,192 rows (G3)

or all 4,096 rows (H9) in the DRAM array at least once

every 64ms. The recommended procedure is to execute

4,096 CBR REFRESH cycles, either uniformly spaced or

grouped in bursts, every 64ms. The MT4LC16M4G3

internally refreshes two rows for every CBR cycle,

whereas the MT4LC16M4H9 refreshes one row for

every CBR cycle. So with either device, executing 4,096

CBR cycles covers all rows. The CBR refresh will invoke

the internal refresh counter for automatic RAS# ad-

dressing. Alternatively, RAS#-ONLY REFRESH capabil-

ity is inherently provided. However, with this method,

some compatibility issues may become apparent. For

example, both G3 and H9 versions require 4,096 CBR

REFRESH cycles, yet each requires a different number of

RAS#-ONLY REFRESH cycles (G3 = 8,192 and H9 =

4,096). JEDEC strongly recommends the use of CBR

REFRESH for this device.

An optional self refresh mode is also available on the

“S” version. The self refresh feature is initiated by

performing a CBR REFRESH cycle and holding RAS#

LOW for the specified tRASS. The “S” option allows for

an extended refresh period of 128ms, or 31.25µs per

row for a 4K refresh and 15.625µs per row for an 8K

refresh, when using a distributed CBR REFRESH. This

refresh rate can be applied during normal operation, as

well as during a standby or battery backup mode.

GENERAL DESCRIPTION (Continued)

16 Meg x 4 EDO DRAM Micron Technology, Inc., reserves the right to change products or specifications without notice.

16 MEG x 4

EDO DRAM

VIH

CAS#

VIH

RAS#

VIH

ADDR ROW COLUMN (A)

DON’T CARE

UNDEFINED

VIH

WE#

VIOH

IOL OPEN

tWPZ

The DQs go to High-Z if WE# falls and, if

WPZ is met,

will remain High-Z until CAS# goes LOW with

WE# HIGH (i.e., until a READ cycle is initiated).

VIH

OE#

VALID DATA (B)

tWHZ

WE# may be used to disable the DQs to prepare

for input data in an EARLY WRITE cycle. The DQs

will remain High-Z until CAS# goes LOW with

WE# HIGH (i.e., until a READ cycle is initiated).

tWHZ

COLUMN (D)

VALID DATA (A)

COLUMN (B) COLUMN (C)

INPUT DATA (C)

Figure 2

WE# Control of DQs

VIH

CAS#

VIH

RAS#

VIH

ADDR ROW COLUMN (A) COLUMN (B)

VIH

OE#

VIOH

IOL OPEN

tOD

VALID DATA (B)

VALID DATA (A)

COLUMN (C)

VALID DATA (A)

tOE

VALID DATA (C)

COLUMN (D)

VALID DATA (D)

tOD

tOEHC

tOD

tOEP

tOES

The DQs go back to

Low-Z if tOES is met.

The DQs remain High-Z

until the next CAS# cycle

if tOEHC is met.

The DQs remain High-Z

until the next CAS# cycle

if tOEP is met.

Figure 1

OE# Control of DQs

The self refresh mode is terminated by driving RAS#

HIGH for a minimum time of tRPS. This delay allows for

the completion of any internal refresh cycles that may

be in process at the time of the RAS# LOW-to-HIGH

transition. If the DRAM controller uses a distributed

CBR refresh sequence, a burst refresh is not required

upon exiting self refresh. However, if the DRAM con-

troller uses RAS#-ONLY or burst CBR refresh, all rows

must be refreshed with a refresh rate of tRC minimum

prior to resuming normal operation.

STANDBY

Returning RAS# and CAS# HIGH terminates a

memory cycle and decreases chip current to a reduced

standby level. The chip is preconditioned for the next

cycle during the RAS# HIGH time.

DRAM REFRESH (Continued)

16 Meg x 4 EDO DRAM Micron Technology, Inc., reserves the right to change products or specifications without notice.

16 MEG x 4

EDO DRAM

ABSOLUTE MAXIMUM RATINGS*

Voltage on VCC Relative to VSS ................ -1V to +4.6V

Voltage on NC, Inputs or I/O Pins

Relative to VSS ....................................... -1V to +4.6V

Operating Temperature, TA (ambient) ... 0°C to +70°C

Storage Temperature (plastic) ............ -55°C to +150°C

Power Dissipation ................................................... 1W

*Stresses greater than those listed under “Absolute

Maximum Ratings” may cause permanent damage to

the device. This is a stress rating only, and functional

operation of the device at these or any other conditions

above those indicated in the operational sections of

this specification is not implied. Exposure to absolute

maximum rating conditions for extended periods may

affect reliability.

DC ELECTRICAL CHARACTERISTICS AND OPERATING CONDITIONS

(Note: 1) (VCC = +3.3V ±0.3V)

PARAMETER/CONDITION SYMBOL MIN MAX UNITS NOTES

SUPPLY VOLTAGE VCC 3 3.6 V

INPUT HIGH VOLTAGE:

Valid Logic 1; All inputs, I/Os and any NC VIH 2VCC + 0.3 V 26

INPUT LOW VOLTAGE:

Valid Logic 0; All inputs, I/Os and any NC VIL -0.3 0.8 V 26

INPUT LEAKAGE CURRENT:

Any input at VIN (0V £ VIN £ VCC + 0.3V);II-2 2 µA 27

All other pins not under test = 0V

OUTPUT HIGH VOLTAGE:

IOUT = -2mA VOH 2.4 –V

OUTPUT LOW VOLTAGE:

IOUT = 2mA VOL –0.4 V

OUTPUT LEAKAGE CURRENT:

Any output at VOUT (0V £ VOUT £ VCC + 0.3V); IOZ -5 5 µA

DQ is disabled and in High-Z state

16 Meg x 4 EDO DRAM Micron Technology, Inc., reserves the right to change products or specifications without notice.

16 MEG x 4

EDO DRAM

ICC OPERATING CONDITIONS AND MAXIMUM LIMITS

(Notes: 1, 2, 3, 5, 6) (VCC = +3.3V ±0.3V)

4K 8K

PARAMETER/CONDITION SYMBOL SPEED REFRESH REFRESH UNITS NOTES

STANDBY CURRENT: TTL I

ALL 1 1 mA

(RAS# = CAS# = V

)

STANDBY CURRENT: CMOS

(RAS# = CAS# ž V

- 0.2V; DQs may be left open; I

ALL 500 500 µA

Other inputs: V

• V

- 0.2V or V

£ 0.2V)

OPERATING CURRENT: Random READ/WRITE I

-5 170 130 mA 25

Average power supply current -6 160 120

(RAS#, CAS#, address cycling:

RC =

RC [MIN])

OPERATING CURRENT: EDO PAGE MODE I

-5 150 150 mA 25

Average power supply current -6 120 120

(RAS# = V

, CAS#, address cycling:

PC =

PC [MIN])

REFRESH CURRENT: RAS#-ONLY I

-5 170 130 mA 22

Average power supply current -6 160 120

(RAS# cycling, CAS# = V

RC =

RC [MIN])

REFRESH CURRENT: CBR I

-5 160 160 mA 4, 7

Average power supply current -6 150 150

(RAS#, CAS#, address cycling:

RC =

RC [MIN])

REFRESH CURRENT: Extended (“S” version only)

Average power supply current: CAS# = 0.2V or CBR cycling; I

ALL 400 400 µA 4, 7

RAS# =

RAS (MIN); WE# = V

- 0.2V; A0-A11, OE# and

= V

- 0.2V or 0.2V (D

may be left open)

REFRESH CURRENT: Self (“S” version only)

Average power supply current: CBR with

RAS# •

RASS (MIN) and CAS# held LOW; I

ALL 400 400 µA 4, 7

WE# = V

- 0.2V; A0-A11, OE# and D

= V

- 0.2V or 0.2V

may be left open)

16 Meg x 4 EDO DRAM Micron Technology, Inc., reserves the right to change products or specifications without notice.

16 MEG x 4

EDO DRAM

CAPACITANCE

(Note: 2)

PARAMETER SYMBOL MAX UNITS

Input Capacitance: Address pins CI15pF

Input Capacitance: RAS#, CAS#, WE#, OE# CI27pF

Input/Output Capacitance: DQ CIO 7pF

AC ELECTRICAL CHARACTERISTICS

(Notes: 5, 6, 7, 8, 9, 10, 11, 12) (VCC = +3.3V ±0.3V)

AC CHARACTERISTICS -5 -6

PARAMETER SYMBOL MIN MAX MIN MAX UNITS NOTES

Access time from column address tAA 25 30 ns

Column-address setup to CAS# precharge tACH 12 15 ns

Column-address hold time (referenced to RAS#) tAR 38 45 ns

Column-address setup time tASC 0 0 ns

Row-address setup time tASR 0 0 ns

Column address to WE# delay time tAWD 42 49 ns 18

Access time from CAS# tCAC 13 15 ns

Column-address hold time tCAH 8 10 ns

CAS# pulse width tCAS 8 10,000 10 10,000 ns

CAS# LOW to “Don’t Care” during Self Refresh tCHD 15 15 ns

CAS# hold time (CBR Refresh) tCHR 8 10 ns 4

CAS# to output in Low-Z tCLZ 0 0 ns

Data output hold after CAS# LOW tCOH 3 3 ns

CAS# precharge time tCP 8 10 ns 13

Access time from CAS# precharge tCPA 28 35 ns

CAS# to RAS# precharge time tCRP 5 5 ns

CAS# hold time tCSH 38 45 ns

CAS# setup time (CBR Refresh) tCSR 5 5 ns 4

CAS# to WE# delay time tCWD 28 35 ns 18

WRITE command to CAS# lead time tCWL 8 10 ns

Data-in hold time tDH 8 10 ns 19

Data-in setup time tDS 0 0 ns 19

Output disable tOD 0 12 0 15 ns 23, 24

Output enable time tOE 12 15 ns 20

OE# hold time from WE# during tOEH 8 10 ns 24

READ-MODIFY-WRITE cycle

OE# HIGH hold time from CAS# HIGH tOEHC 5 10 ns

OE# HIGH pulse width tOEP 5 5 ns

OE# LOW to CAS# HIGH setup time tOES 4 5 ns

Output buffer turn-off delay tOFF 0 12 0 15 ns 17, 23

16 Meg x 4 EDO DRAM Micron Technology, Inc., reserves the right to change products or specifications without notice.

16 MEG x 4

EDO DRAM

AC ELECTRICAL CHARACTERISTICS

(Notes: 5, 6, 7, 8, 9, 10, 11, 12) (VCC = +3.3V ±0.3V)

AC CHARACTERISTICS -5 -6

PARAMETER SYMBOL MIN MAX MIN MAX UNITS NOTES

OE# setup prior to RAS# during tORD 0 0 ns

HIDDEN REFRESH cycle

EDO-PAGE-MODE READ or WRITE cycle time tPC 20 25 ns

EDO-PAGE-MODE READ-WRITE cycle time tPRWC 47 56 ns

Access time from RAS# tRAC 50 60 ns 23

RAS# to column-address delay time tRAD 9 12 ns 15

Row-address hold time tRAH 9 10 ns

RAS# pulse width tRAS 50 10,000 60 10,000 ns

RAS# pulse width (EDO PAGE MODE) tRASP 50 125,000 60 125,000 ns

RAS# pulse width during Self Refresh tRASS 100 100 µs

Random READ or WRITE cycle time tRC 84 104 ns

RAS# to CAS# delay time tRCD 11 14 ns 14

READ command hold time (referenced to CAS#) tRCH 0 0 ns 16

READ command setup time tRCS 0 0 ns

Refresh period tREF 64 64 ms 22

Refresh period (4,096 cycles) “S” version tREF 128 128 ms 4

RAS# precharge time tRP 30 40 ns

RAS# to CAS# precharge time tRPC 5 5 ns

RAS# precharge time exiting Self Refresh tRPS 90 105 ns

READ command hold time (referenced to RAS#) tRRH 0 0 ns 16

RAS# hold time tRSH 13 15 ns

READ-WRITE cycle time tRWC 116 140 ns

RAS# to WE# delay time tRWD 67 79 ns 18

WRITE command to RAS# lead time tRWL 13 15 ns

Transition time (rise or fall) tT250250ns

WRITE command hold time tWCH 8 10 ns

WRITE command hold time (referenced to RAS#) tWCR 38 45 ns

WE# command setup time tWCS 0 0 ns 18

WE# to outputs in High-Z tWHZ 0 12 0 15 ns

WRITE command pulse width tWP 5 5 ns

WE# pulse width to disable outputs tWPZ 10 10 ns

WE# hold time (CBR Refresh) tWRH 8 10 ns 4, 23

WE# setup time (CBR Refresh) tWRP 8 10 ns 4, 23

16 Meg x 4 EDO DRAM Micron Technology, Inc., reserves the right to change products or specifications without notice.

16 MEG x 4

EDO DRAM

NOTES

1. All voltages referenced to VSS.

2. This parameter is sampled. VCC = +3.3V; f = 1

MHz; TA = 25°C.

3. ICC is dependent on output loading and cycle

rates. Specified values are obtained with mini-

mum cycle time and the outputs open.

4. Enables on-chip refresh and address counters.

5. The minimum specifications are used only to

indicate cycle time at which proper operation

over the full temperature range is ensured.

6. An initial pause of 100µs is required after power-

up, followed by eight RAS# refresh cycles (RAS#-

ONLY or CBR with WE# HIGH), before proper

device operation is ensured. The eight RAS# cycle

wake-ups should be repeated any time the tREF

refresh requirement is exceeded.

7. AC characteristics assume tT = 2.5ns.

8. VIH (MIN) and VIL (MAX) are reference levels for

measuring timing of input signals. Transition

times are measured between VIH and VIL (or

between VIL and VIH).

9. In addition to meeting the transition rate

specification, all input signals must transit

between VIH and VIL (or between VIL and VIH) in a

monotonic manner.

10. If CAS# and RAS# = VIH, data output is High-Z.

11. If CAS# = VIL, data output may contain data from

the last valid READ cycle.

12. Measured with a load equivalent to two TTL

gates and 100pF; and VOL = 0.8V and VOH = 2V.

13. If CAS# is LOW at the falling edge of RAS#,

output data will be maintained from the previous

cycle. To initiate a new cycle and clear the data-

out buffer, CAS# must be pulsed HIGH for tCP.

14. The tRAD (MAX) limit is no longer specified.

tRAD (MAX) was specified as a reference point

only. If tRAD was greater than the specified tRAD

(MAX) limit, then access time was controlled

exclusively by tAA (tRAC and tCAC no longer

applied). With or without the tRAD (MAX) limit,

tAA, tRAC, and tCAC must always be met.

15. The tRCD (MAX) limit is no longer specified.

tRCD (MAX) was specified as a reference point

only. If tRCD was greater than the specified tRCD

(MAX) limit, then access time was controlled

exclusively by tCAC (tRAC [MIN] no longer

applied). With or without the tRCD limit, tAA

and tCAC must always be met.

16. Either tRCH or tRRH must be satisfied for a READ

cycle.

17. tOFF (MAX) defines the time at which the output

achieves the open circuit condition and is not

referenced to VOH or VOL.

18. tWCS, tRWD, tAWD, and tCWD are not restrictive

operating parameters. tWCS applies to EARLY

WRITE cycles. If tWCS > tWCS (MIN), the cycle is

an EARLY WRITE cycle and the data output will

remain an open circuit throughout the entire

cycle. t

RWD, t

AWD, and t

CWD define READ-

MODIFY-WRITE cycles. Meeting these limits

allows for reading and disabling output data and

then applying input data. OE# held HIGH and

WE# taken LOW after CAS# goes LOW results in a

LATE WRITE (OE#-controlled) cycle. t

WCS,

tRWD, t

CWD, and t

AWD are not applicable in a

LATE WRITE cycle.

19. These parameters are referenced to CAS# leading

edge in EARLY WRITE cycles and WE# leading

edge in LATE WRITE or READ-MODIFY-WRITE

cycles.

20. If OE# is tied permanently LOW, LATE WRITE or

READ-MODIFY-WRITE operations are not

possible.

21. A HIDDEN REFRESH may also be performed after

a WRITE cycle. In this case, WE# is LOW and

OE# is HIGH.

22. RAS#-ONLY REFRESH requires that all rows be

refreshed at least once every 64ms (4,096 rows

for the H9 version and 8,192 rows for the G3

version). CBR REFRESH requires that at least

4,096 cycles be completed every 64ms.

23. The DQs open during READ cycles once tOD or

tOFF occur. If CAS# stays LOW while OE# is

brought HIGH, the DQs will open. If OE# is

brought back LOW (CAS# still LOW), the DQs

will provide the previously read data.

24. LATE WRITE and READ-MODIFY-WRITE cycles

must have both tOD and tOEH met (OE# HIGH

during WRITE cycle) in order to ensure that the

output buffers will be open during the WRITE

cycle. If OE# is taken back LOW while CAS#

remains LOW, the DQs will remain open.

25. Column address changed once each cycle.

26. VIH overshoot: VIH (MAX) = VCC + 2V for a pulse

width £ 10ns, and the pulse width cannot be

greater than one third of the cycle rate. VIL

undershoot: VIL (MIN) = -2V for a pulse width £

10ns, and the pulse width cannot be greater than

one third of the cycle rate.

27. NC pins are assumed to be left floating and are

not tested for leakage.

16 Meg x 4 EDO DRAM Micron Technology, Inc., reserves the right to change products or specifications without notice.

16 MEG x 4

EDO DRAM

READ CYCLE

tRRH

tCLZ

tCAC

tRAC

tAA

VALID DATA OPEN

tOFF

tRCH

ROW

tRCS

tASC

tRAH

tRAD

tAR

tCAH

tRCD tCAS

tRSH

tCSH

tRP

tRC

tRAS

tCRP

tASR

ROW

OPEN

RAS#

VIH

ADDR

VIH

DQ V

VOH

VIH

tOD

tOE

OE#

VIH

COLUMN

CAS#

WE#

NOTE 1

tACH

DON’T CARE

UNDEFINED

NOTE: 1. tOFF is referenced from rising edge of RAS# or CAS#, whichever occurs last.

-5 -6

SYMBOL MIN MAX MIN MAX UNITS

tOFF 0 12 0 15 ns

tRAC 50 60 ns

tRAD 9 12 ns

tRAH 9 10 ns

tRAS 50 10,000 60 10,000 ns

tRC 84 104 ns

tRCD 11 14 ns

tRCH 0 0 ns

tRCS 0 0 ns

tRP 30 40 ns

tRRH 0 0 ns

tRSH 13 15 ns

TIMING PARAMETERS

-5 -6

SYMBOL MIN MAX MIN MAX UNITS

tAA 25 30 ns

tACH 12 15 ns

tAR 38 45 ns

tASC 0 0 ns

tASR 0 0 ns

tCAC 13 15 ns

tCAH 8 10 ns

tCAS 8 10,000 10 10,000 ns

tCLZ 0 0 ns

tCRP 5 5 ns

tCSH 38 45 ns

tOD 0 12 0 15 ns

tOE 12 15 ns

16 Meg x 4 EDO DRAM Micron Technology, Inc., reserves the right to change products or specifications without notice.

16 MEG x 4

EDO DRAM

EARLY WRITE CYCLE

DON’T CARE

UNDEFINED

VIH

VALID DATA

ROW

COLUMNROW

tDS

tWP

tWCH

tWCS

tWCR

tRWL

tCWL

tCAH

tASC

tRAH

tASR

tRAD

tAR

tCAS

tRSH

tCSH

tRCD

tCRP

tRAS

tRC

tRP

VIH

ADDR V

VIH

DQ V

VIOH

IOL

VIH

RAS#

OE#

tDH

WE#

CAS#

tACH

-5 -6

SYMBOL MIN MAX MIN MAX UNITS

tRAH 9 10 ns

tRAS 50 10,000 60 10,000 ns

tRC 84 104 ns

tRCD 11 14 ns

tRP 30 40 ns

tRSH 13 15 ns

tRWL 13 15 ns

tWCH 8 10 ns

tWCR 38 45 ns

tWCS 0 0 ns

tWP 5 5 ns

TIMING PARAMETERS

-5 -6

SYMBOL MIN MAX MIN MAX UNITS

tACH 12 15 ns

tAR 38 45 ns

tASC 0 0 ns

tASR 0 0 ns

tCAH 8 10 ns

tCAS 8 10,000 10 10,000 ns

tCRP 5 5 ns

tCSH 38 45 ns

tCWL 8 15 ns

tDH 8 10 ns

tDS 0 0 ns

tRAD 9 12 ns

16 Meg x 4 EDO DRAM Micron Technology, Inc., reserves the right to change products or specifications without notice.

16 MEG x 4

EDO DRAM

READ-WRITE CYCLE

(LATE WRITE and READ-MODIFY-WRITE cycles)

VALID D OUT VALID D IN

ROW COLUMN ROW

VIH

ADDR V

VIH

DQ V

VIOH

IOL

VIH

RAS#

OPENOPEN

tOE tOD

tCAC

tRAC

tAA

tCLZ

tDS tDH

tAWD tWP

tRWL

tCWL

tCWD

tRWD

tRCS

tASC tCAH

tAR

tASR

tRAD

tCRP tRCD tCAS

tRSH

tCSH

tRAS

tRWC

tRP

tRAH

OE#

tOEH

WE#

tACH

CAS#

DON’T CARE

UNDEFINED

-5 -6

SYMBOL MIN MAX MIN MAX UNITS

tOD 0 12 0 15 ns

tOE 12 15 ns

tOEH 8 10 ns

tRAC 50 60 ns

tRAD 9 12 ns

tRAH 9 10 ns

tRAS 50 10,000 60 10,000 ns

tRCD 11 14 ns

tRCS 0 0 ns

tRP 30 40 ns

tRSH 13 15 ns

tRWC 116 140 ns

tRWD 67 79 ns

tRWL 13 15 ns

tWP 5 5 ns

TIMING PARAMETERS

-5 -6

SYMBOL MIN MAX MIN MAX UNITS

tAA 25 30 ns

tACH 12 15 ns

tAR 38 45 ns

tASC 0 0 ns

tASR 0 0 ns

tAWD 42 49 ns

tCAC 13 15 ns

tCAH 8 10 ns

tCAS 8 10,000 10 10,000 ns

tCLZ 0 0 ns

tCRP 5 5 ns

tCSH 38 45 ns

tCWD 28 35 ns

tCWL 8 10 ns

tDH 8 10 ns

tDS 0 0 ns

16 Meg x 4 EDO DRAM Micron Technology, Inc., reserves the right to change products or specifications without notice.

16 MEG x 4

EDO DRAM

EDO-PAGE-MODE READ CYCLE

VALID

DATA VALID

DATA

VALID

DATA

COLUMNCOLUMNCOLUMNROW ROW

DON’T CARE

UNDEFINED

tOD

tCAH

tASC

tCP

tRSH

tCP

tCAS

tRCD

tCRP

tPC

tCSH

tRASP tRP

tCAH

tASC

tCAH

tASC

tAR

tRAH

tRAD

tASR

tRCS

tRRH

tRCH

tOFF

tCAC

tCPA

tAA

tCLZ

tCAC

tCPA

tAA

tCAC

tRAC

tAA

tCLZ

tOE tOD tOE tOD

OPENOPEN

VIH

ADDR V

VIH

DQ V

VOH

VIH

RAS#

OE#

tCAS tCAS

CAS#

WE#

tCOH

tOEP

tOEHC

tOES

tACH

tACH tACH

-5 -6

SYMBOL MIN MAX MIN MAX UNITS

tOEHC 5 10 ns

tOEP 5 5 ns

tOES 4 5 ns

tOFF 0 12 0 15 ns

tPC 20 25 ns

tRAC 50 60 ns

tRAD 9 12 ns

tRAH 9 10 ns

tRASP 50 125,000 60 125,000 ns

tRCH 0 0 ns

tRCD 11 14 ns

tRCS 0 0 ns

tRP 30 40 ns

tRRH 0 0 ns

tRSH 13 15 ns

TIMING PARAMETERS

-5 -6

SYMBOL MIN MAX MIN MAX UNITS

tAA 25 30 ns

tACH 12 15 ns

tAR 38 45 ns

tASC 0 0 ns

tASR 0 0 ns

tCAC 13 15 ns

tCAH 8 10 ns

tCAS 8 10,000 10 10,000 ns

tCLZ 0 0 ns

tCOH 3 3 ns

tCP 8 10 ns

tCPA 28 35 ns

tCRP 5 5 ns

tCSH 38 45 ns

tOD 0 12 0 15 ns

tOE 12 15 ns

16 Meg x 4 EDO DRAM Micron Technology, Inc., reserves the right to change products or specifications without notice.

16 MEG x 4

EDO DRAM

tDS tDH tDS tDH tDS tDH

tWCR

VALID DATA VALID DATA VALID DATA

tRWL

tWP

tCWL

tWCH

tWCS

tWP

tCWL

tWCH

tWCS

tWP

tCWL

tWCH

tWCS

tCAH

tASC

tCAH

tASC

tCAH

tASC

tRAH

tASR

tRAD tACH tACH tACH

tAR

COLUMNCOLUMNCOLUMNROW ROW

tCP

tCAS

tRSH

tCP

tCAS

tCP

tCAS

tRCD

tCRP

tPC

tCSH

tRASP tRP

VIH

CAS# V

VIH

ADDR V

VIH

WE# V

VIH

DQ V

VIOH

IOL

RAS#

DON’T CARE

UNDEFINED

EDO-PAGE-MODE EARLY WRITE CYCLE

-5 -6

SYMBOL MIN MAX MIN MAX UNITS

tPC 20 25 ns

tRAD 9 12 ns

tRAH 9 10 ns

tRASP 50 125,000 60 125,000 ns

tRCD 11 14 ns

tRP 30 40 ns

tRSH 13 15 ns

tRWL 13 15 ns

tWCH 8 10 ns

tWCR 38 45 ns

tWCS 0 0 ns

tWP 5 5 ns

TIMING PARAMETERS

-5 -6

SYMBOL MIN MAX MIN MAX UNITS

tACH 12 15 ns

tAR 38 45 ns

tASC 0 0 ns

tASR 0 0 ns

tCAH 8 10 ns

tCAS 8 10,000 10 10,000 ns

tCP 8 10 ns

tCRP 5 5 ns

tCSH 38 45 ns

tCWL 8 10 ns

tDH 8 10 ns

tDS 0 0 ns

16 Meg x 4 EDO DRAM Micron Technology, Inc., reserves the right to change products or specifications without notice.

16 MEG x 4

EDO DRAM

EDO-PAGE-MODE READ-WRITE CYCLE

(LATE WRITE and READ-MODIFY-WRITE cycles)

VALID D OUT VALID D IN

ROW COLUMN ROW

VIH

ADDR V

VIH

DQ V

VIOH

IOL

VIH

RAS#

OPENOPEN

tOE tOD

tCAC

tRAC

tAA

tCLZ

tDS tDH

tAWD tWP

tRWL

tCWL

tCWD

tRWD

tRCS

tASC tCAH

tAR

tASR

tRAD

tCRP tRCD tCAS

tRSH

tCSH

tRAS

tRWC

tRP

tRAH

OE#

tOEH

WE#

tACH

CAS#

DON’T CARE

UNDEFINED

NOTE: 1. tPC is for LATE WRITE cycles only.

-5 -6

SYMBOL MIN MAX MIN MAX UNITS

tOD 0 12 0 15 ns

tOE 12 15 ns

tOEH 8 10 ns

tPC 20 25 ns

tPRWC 47 56 ns

tRAC 50 60 ns

tRAD 9 12 ns

tRAH 9 10 ns

tRASP 50 125,000 60 125,000 ns

tRCD 11 14 ns

tRCS 0 0 ns

tRP 30 40 ns

tRSH 13 15 ns

tRWD 67 79 ns

tRWL 13 15 ns

tWP 5 5 ns

TIMING PARAMETERS

-5 -6

SYMBOL MIN MAX MIN MAX UNITS

tAA 25 30 ns

tAR 38 45 ns

tASC 0 0 ns

tASR 0 0 ns

tAWD 42 49 ns

tCAC 13 15 ns

tCAH 8 10 ns

tCAS 8 10,000 10 10,000 ns

tCLZ 0 0 ns

tCP 8 10 ns

tCPA 28 35 ns

tCRP 5 5 ns

tCSH 38 45 ns

tCWD 28 35 ns

tCWL 8 10 ns

tDH 8 10 ns

tDS 0 0 ns

16 Meg x 4 EDO DRAM Micron Technology, Inc., reserves the right to change products or specifications without notice.

16 MEG x 4

EDO DRAM

EDO-PAGE-MODE READ EARLY WRITE CYCLE

(Pseudo READ-MODIFY-WRITE)

VIH

RAS#

VIH

ADDR

VIH

WE#

tRASP tRP

ROW COLUMN (A) COLUMN (N) ROW

VIH

OE#

VIOH

IOL

tCRP

tCSH

tCAS

tRCD

ASR tRAH

tRAD

tASC

tAR

tCAH tASC tCAH tASC tCAH

tCP

tRSH

VALID DATA

tRCS tRCH tWCS

tOE

VALID

DATA (B)

VALID DATA (A)

tWHZ

tCAC

tCPA

tAA

tCAC

tAA

OPEN

tPC

RAC

tCOH

tWCH

tDS tDH

tPC

COLUMN (B)

tACH

CAS#

tCAS

tCP tCP

DON’T CARE

UNDEFINED

-5 -6

SYMBOL MIN MAX MIN MAX UNITS

tOE 12 15 ns

tPC 20 25 ns

tRAC 50 60 ns

tRAD 9 12 ns

tRAH 9 10 ns

tRASP 50 125,000 60 125,000 ns

tRCD 11 14 ns

tRCH 0 0 ns

tRCS 0 0 ns

tRP 30 40 ns

tRSH 13 15 ns

tWCH 8 10 ns

tWCS 0 0 ns

tWHZ 0 12 0 15 ns

TIMING PARAMETERS

-5 -6

SYMBOL MIN MAX MIN MAX UNITS

tAA 25 30 ns

tACH 12 15 ns

tAR 38 45 ns

tASC 0 0 ns

tASR 0 0 ns

tCAC 13 15 ns

tCAH 8 10 ns

tCAS 8 10,000 10 10,000 ns

tCOH 3 3 ns

tCP 8 10 ns

tCPA 28 35 ns

tCRP 5 5 ns

tCSH 38 45 ns

tDH 8 10 ns

tDS 0 0 ns

16 Meg x 4 EDO DRAM Micron Technology, Inc., reserves the right to change products or specifications without notice.

16 MEG x 4

EDO DRAM

READ CYCLE

(With WE#-controlled disable)

tCLZ

tCAC

tRAC

tAA

VALID DATA OPEN

tRCH

tRCS

tASC

tRAH

tRAD

tAR

tCAH

tRCD tCAS

tCSH

tCRP

tASR

ROW

OPEN

RAS#

VIH

ADDR

VIH

DQ V

VOH

VIH

tOD

tOE

OE#

VIH

COLUMN

WE#

tWHZ

tWPZ

tCP

tASC

tRCS

COLUMN

tCLZ

DON’T CARE

UNDEFINED

CAS#

-5 -6

SYMBOL MIN MAX MIN MAX UNITS

tOD 0 12 0 15 ns

tOE 12 15 ns

tRAC 50 60 ns

tRAD 9 12 ns

tRAH 9 10 ns

tRCD 11 14 ns

tRCH 0 0 ns

tRCS 0 0 ns

tWHZ 0 12 0 15 ns

tWPZ 10 10 ns

TIMING PARAMETERS

-5 -6

SYMBOL MIN MAX MIN MAX UNITS

tAA 25 30 ns

tAR 38 45 ns

tASC 0 0 ns

tASR 0 0 ns

tCAC 13 15 ns

tCAH 8 10 ns

tCAS 8 10,000 10 10,000 ns

tCLZ 0 0 ns

tCP 8 10 ns

tCRP 5 5 ns

tCSH 38 45 ns

16 Meg x 4 EDO DRAM Micron Technology, Inc., reserves the right to change products or specifications without notice.

16 MEG x 4

EDO DRAM

RAS#-ONLY REFRESH CYCLE

(OE# and WE# = DON’T CARE)

ROW

VIH

CAS# V

VIH

ADDR V

VIH

RAS#

tRC

tRAS tRP

tCRP

tASR tRAH

ROW

OPEN

DQ V

VOH

tRPC

CBR REFRESH CYCLE

(Addresses and OE# = DON’T CARE)

tRP

VIH

RAS#

tRAS NOTE 1

OPEN

tCHR

tCSR

VIH

VOH

CAS#

tRP tRAS

tRPC

tCSR

tRPC tCHR

tCP

VIH

tWRP tWRH

WE#

tWRP tWRH

DON’T CARE

UNDEFINED

-5 -6

SYMBOL MIN MAX MIN MAX UNITS

tRAS 50 10,000 60 10,000 ns

tRC 84 104 ns

tRP 30 40 ns

tRPC 5 5 ns

tWRH 8 10 ns

tWRP 8 10 ns

TIMING PARAMETERS

-5 -6

SYMBOL MIN MAX MIN MAX UNITS

tASR 0 0 ns

tCHR 8 10 ns

tCP 8 10 ns

tCRP 5 5 ns

tCSR 5 5 ns

tRAH 9 10 ns

NOTE: 1. End of first CBR REFRESH cycle.

16 Meg x 4 EDO DRAM Micron Technology, Inc., reserves the right to change products or specifications without notice.

16 MEG x 4

EDO DRAM

HIDDEN REFRESH CYCLE 1

(WE# = HIGH; OE# = LOW)

DON’T CARE

UNDEFINED

tCLZ

tOFF

OPENVALID DATAOPEN

COLUMNROW

tCAC

tRAC

tAA

tCAH

tASC

tRAH

tASR

tRAD

tAR

tCRP tRCD tRSH

tRAS tRP

tCHR

tRAS

DQ V

VOH

VIH

ADDR

VIH

RAS#

VIH

tOE tOD

OE#

tORD

CAS#

-5 -6

SYMBOL MIN MAX MIN MAX UNITS

tOE 12 15 ns

tOFF 0 12 0 15 ns

tORD 0 0 ns

tRAC 50 60 ns

tRAD 9 12 ns

tRAH 9 10 ns

tRAS 50 10,000 60 10,000 ns

tRCD 11 14 ns

tRP 30 40 ns

tRSH 13 15 ns

TIMING PARAMETERS

-5 -6

SYMBOL MIN MAX MIN MAX UNITS

tAA 25 30 ns

tAR 38 45 ns

tASC 0 0 ns

tASR 0 0 ns

tCAC 13 15 ns

tCAH 8 10 ns

tCHR 8 10 ns

tCLZ 0 0 ns

tCRP 5 5 ns

tOD 0 12 0 15 ns

NOTE: 1. A HIDDEN REFRESH may also be performed after a WRITE cycle. In this case, WE# is LOW and OE# is HIGH.

16 Meg x 4 EDO DRAM Micron Technology, Inc., reserves the right to change products or specifications without notice.

16 MEG x 4

EDO DRAM

SELF REFRESH CYCLE

(Addresses and OE# = DON’T CARE)

VIH

RAS#

tRASS

OPEN

VIH

VOH

tRPC

tCHD

tRPS

tRPC

tRP

tCP

CAS#

WE# V

VIH

tWRH

tWRP

tWRH

tWRP

(

)(

)

(

)(

)

(

)(

)

(

)(

)

(

)(

)

NOTE 1

tCSR

DON’T CARE

UNDEFINED

tCP

NOTE 2

(

)(

)

(

)(

)

NOTE: 1. Once tRASS (MIN) is met and RAS# remains LOW, the DRAM will enter self refresh mode.

2. Once tRPS is satisfied, a complete burst of all rows should be executed if RAS#-only por Burst CBR refresh is being used.

-5 -6

SYMBOL MIN MAX MIN MAX UNITS

tRPC 5 5 ns

tRPS 90 105 ns

tWRH 8 10 ns

tWRP 8 10 ns

TIMING PARAMETERS

-5 -6

SYMBOL MIN MAX MIN MAX UNITS

tCHD 15 15 ns

tCP 8 10 ns

tCSR 5 5 ns

tRASS 100 100 µs

tRP 30 40 ns

16 Meg x 4 EDO DRAM Micron Technology, Inc., reserves the right to change products or specifications without notice.

16 MEG x 4

EDO DRAM

32-PIN PLASTIC SOJ (400 mil)

.435 (11.05)

.360 (9.14)

.750 (19.05) TYP

.829 (21.05)

SEATING PLANE

.040 (1.02)

.380 (9.65)

.080 (2.03)

.095 (2.42)

.145 (3.68)

.132 (3.35)

.015 (0.38)

.020 (0.51)

PIN #1 ID .050 (1.27) TYP

.445 (11.31)

.823 (20.90)

.405 (10.29)

.399 (10.13)

.030 (0.77)

.032 (0.82)

.037 (0.95) MAX DAMBAR PROTRUSION

.026 (0.67)

.024 (0.61)

.030 (0.76)

MIN

NOTE: 1. All dimensions in inches (millimeters) MAX or typical where noted.

MIN

2. Package width and length do not include mold protrusion; allowable mold protrusion is .01" per side.

16 Meg x 4 EDO DRAM Micron Technology, Inc., reserves the right to change products or specifications without notice.

16 MEG x 4

EDO DRAM

32-PIN PLASTIC TSOP (400 mil)

.008 (0.20)

.002 (0.05)

.467 (11.86)

.459 (11.66)

.047(1.19)

MAX

.024 (0.60)

.016 (0.40)

116

GAGE PLANE

.010 (0.25)

SEE DETAIL A

.004 (0.10)

.007 (0.18)

.005 (0.13)

.827 (21.01)

.823 (20.91)

DETAIL A

.0375 (0.95)

.402 (10.21)

.398 (10.11)

.020 (0.50)

.012 (0.30)

.0315 (0.80)

.050 (1.27)

TYP

NOTE: 1. All dimensions in inches (millimeters) MAX or typical where noted.

MIN

2. Package width and length do not include mold protrusion; allowable mold protrusion is .01" per side.

8000 S. Federal Way, P.O. Box 6, Boise, ID 83707-0006, Tel: 208-368-3900

E-mail: prodmktg@micron.com, Internet: http://www.micron.com, Customer Comment Line: 800-932-4992

Micron is a registered trademark of Micron Technology, Inc.

16 Meg x 4 EDO DRAM Micron Technology, Inc., reserves the right to change products or specifications without notice.

16 MEG x 4

EDO DRAM

REVISION HISTORY

• 2000 Release

• D84 REV A .................................................................................................................................................. May, 2000

tRASS units changed from ns to µs

Update section on exiting Self Refresh

Correct Hidden Refresh Diagram for tORD