Semiconductor Components Industries, LLC, 2004
May, 2004 − Rev. 9 1Publication Order Number:
LM301A/D
LM301A, LM201A, LM201AV
Non Compensated Single
Operational Amplifiers
A general purpose operational amplifier that allows the user to
choose the compensation capacitor best suited to his needs. With
proper compensation, summing amplifier slew rates to 10 V/s can be
obtained.
Features
•Low Input Offset Current: 20 nA Maximum Over Temperature
Range
•External Frequency Compensation for Flexibility
•Class AB Output Provides Excellent Linearity
•Output Short Circuit Protection
•Guaranteed Drift Characteristics
•Pb−Free Packages are Available
Figure 1. Standard Compensation
and Offset Balancing Circuit
Balance
VEE
VCC
Output
Inverting
Input
Balance
10 M
Freq
Compen
30 pF
VEE
20 k
+
Non−
Inverting
Input
5.1 M
VCC
VO
VUT
VIVEE
VCC
VLT
VEE
MZ4622 or Equiv.
VO
VO = 4.8 V for
VLT ≤ VI ≤ VUT
VO = −0.4 V
VI < VLT or VI > VUT
(Pins Not Shown Are Not Connected)
+
3.9 V
Figure 2. Double−Ended Limit Detector
PDIP−8
N SUFFIX
CASE 626
1
8
SOIC−8
D SUFFIX
CASE 751
1
8
Compensation
VCC
Output
BalanceVEE 4
Balance 1
2
3
8
7
6
5
Inputs
(Top View)
PIN CONNECTIONS
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See detailed ordering and shipping information in the package
dimensions section on page 2 of this data sheet.
ORDERING INFORMATION
See general marking information in the device marking
section on page 3 of this data sheet.
DEVICE MARKING INFORMATION
*For additional information on our Pb−Free strategy
and soldering details, please download the
ON Semiconductor Soldering and Mounting
Techniques Reference Manual, SOLDERRM/D.
LM301A, LM201A, LM201AV
http://onsemi.com
2
Inputs
Balance Compensation
VCC
Output
VEE
Balance
25
500
50
80 k
1.0 k
40k40k
10 k20 k5 k
450
250
+
Figure 3. Representative Circuit Schematic
ORDERING INFORMATION
Device Package Shipping†
LM301AD SOIC−8
LM301ADG SOIC−8
(Pb−Free) 98 Units/Rail
LM301ADR2 SOIC−8
LM301ADR2G SOIC−8
(Pb−Free) 2500 Tape & Reel
LM301AN PDIP−8 50 Units/Rail
LM201AD SOIC−8 98 Units/Rail
LM201ADR2 SOIC−8 2500 Tape & Reel
LM201AN PDIP−8 50 Units/Rail
LM201AVDR2 SOIC−8 2500 Tape & Reel
†For information on tape and reel specifications, including part orientation and tape sizes, please refer to our Tape and Reel Packaging
Specifications Brochure, BRD8011/D.
LM301A, LM201A, LM201AV
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3
MARKING DIAGRAMS
x = 2 or 3
A = Assembly Location
WL, L = Wafer Lot
YY, Y = Year
WW, W = Work Week
1
8
LMx01AN
AWL
YYWW ALYWA
LMx01
1
8
PDIP−8
N SUFFIX
CASE 626
SOIC−8
D SUFFIX
CASE 751
MAXIMUM RATINGS
Value
Rating Symbol LM201A LM201AV LM301A Unit
Power Supply Voltage VCC, VEE ±22 ±22 ±18 Vdc
Input Differential Voltage VID ±30 V
Input Common Mode Range (Note 1) VICR ±15 V
Output Short Circuit Duration tSC Continuous
Power Dissipation (Package Limitation) PD
Plastic Dual−In−Line Package 625 625 625 mW
Derate above TA = +25°C 5.0 5.0 5.0 mW/°C
Operating Ambient Temperature Range TA−25 to +85 −40 to +105 0 to +70 °C
Storage Temperature Range Tstg −65 to +150 °C
Maximum ratings are those values beyond which device damage can occur. Maximum ratings applied to the device are individual stress limit
values (not normal operating conditions) and are not valid simultaneously. If these limits are exceeded, device functional operation is not implied,
damage may occur and reliability may be affected.
LM301A, LM201A, LM201AV
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4
ELECTRICAL CHARACTERISTICS (TA = +25°C, unless otherwise noted.) Unless otherwise specified, these specifications apply
for supply voltages from ±5.0 V to ±20 V for the LM201A and LM201AV, and from ±5.0 V to ±15 V for the LM301A.
LM201A / LM201AV LM301A
Characteristic Symbol Min Typ Max Min Typ Max Unit
Input Offset Voltage (RS ≤ 50 k) VIO − 0.7 2.0 − 2.0 7.5 mV
Input Offset Current IIO − 1.5 10 − 3.0 50 nA
Input Bias Current IIB − 30 75 − 70 250 nA
Input Resistance ri1.5 4.0 − 0.5 2.0 − M
Supply Current ICC,IEE mA
VCC/VEE = ±20 V − 1.8 3.0 − − −
VCC/VEE = ±15 V − − − − 1.8 3.0
Large Signal Voltage Gain AV50 160 − 25 160 − V/mV
(VCC/VEE = ±15 V, VO = ±10 V, RL > 2.0 k)
The following specifications apply over the operating temperature range.
Input Offset Voltage (RS ≤ 50 k) VIO − − 3.0 − − 10 mV
Input Offset Current IIO − − 20 − − 70 nA
Avg Temperature Coefficient of Input Offset
Voltage (Note 2) VIO/T − 3.0 15 − 6.0 30 V/°C
TA(min) ≤ TA ≤ TA (max)
Avg Temperature Coefficient of Input Offset
Current (Note 2) IIO/T nA/°C
+25°C ≤ TA ≤ TA (max) − 0.01 0.1 − 0.01 0.3
TA(min) ≤ TA ≤ 25°C − 0.02 0.2 − 0.02 0.6
Input Bias Current IIB − − 100 − − 300 nA
Large Signal Voltage Gain AVOL 25 − − 15 − − V/mV
(VCC/VEE = ±15 V, VO = ±10V, RL > 2.0 k)
Input Voltage Range VICR V
VCC/VEE = ±20 V −15 − +15 − − −
VCC/VEE = ±15 V − − − −12 − +12
Common Mode Rejection (RS ≤50 k) CMR 80 96 − 70 90 − dB
Supply Voltage Rejection (RS ≤50 k) PSR 80 96 − 70 96 − dB
Output Voltage Swing VO±12 ±14 − ±12 ±14 − V
(VCC/VEE = ±15 V, RL = ±10 k, RL > 2.0 k)±10 ±13 − ±10 ±13 −
Supply Currents (TA = TA(max), VCC/VEE = ±20 V) ICC,IEE − 1.2 2.5 − − − mA
1. For supply voltages less than ±15 V, the absolute maximum input voltage is equal to the supply voltage.
2. Guaranteed by design.
LM301A, LM201A, LM201AV
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5
C1 = 3.0 pF
C1 = 30 pF
Single−Pole Compensation
Figure 4. Minimum Input Voltage Range Figure 5. Minimum Output Voltage Swing
Figure 6. Minimum Voltage Gain Figure 7. Typical Supply Currents
Figure 8. Open Loop Frequency Response Figure 9. Large Signal Frequency Response
VIR, INPUT VOLTAGE RANGE (V)
VOR, OUTPUT VOLTAGE RANGE ( V)
±
AV, VOLTAGE GAIN (dB)
AV, VOLTAGE GAIN (dB)
CC EE, SUPPLY CURRENTS (mA)II,
VCC, ( −VEE), SUPPLY VOLTAGE (V) VCC, ( −VEE), SUPPLY VOLTAGE (V)
VCC, ( −VEE), SUPPLY VOLTAGE (V) VCC, ( −VEE), SUPPLY VOLTAGE (V)
f, FREQUENCY (Hz) f, FREQUENCY (Hz)
Phase
Gain
C1 = 3.0 pF
C1 = 30 pF
20
16
12
8.0
4.0
00 5.0 10 15 20
20
16
12
8.0
4.0
00 5.0 10 15 20
0 5.0 10 15 200 5.0 10 15 20
100
94
88
82
76
70
2.5
2.0
1.5
1.0
0.5
0
1.0 k 10 k 100 k 1.0 M 10 M
1.0 10 100 1.0 k 10 k 100 k 1.0 M 10 M
315
270
225
180
135
90
45
0
180
160
140
120
100
80
60
40
20
0
−20
15
10
5.0
0
Minimum
RL = 10 k
Minimum
RL = 2.0 k
TA = +25°C
Single−Pole Compensation
VOR, OUTPUT VOLTAGE RANGE ( V)
±
Negative
Positive
Applicable to the Specified
Operating Temperature
Ranges
Applicable to the Specified
Operating Temperature
Ranges
Applicable to the Specified
Operating Temperature
Ranges
LM201A
only LM201A
only
LM201A
only
LM201A
only
LM301A, LM201A, LM201AV
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6
Figure 10. Voltage Follower Pulse Response Figure 11. Open Loop Frequency Response
Figure 12. Large Signal Frequency Response Figure 13. Inverter Pulse Response
Figure 14. Single−Pole Compensation Figure 15. Feedforward Compensation
t, TIME (s)
t, TIME (s)
f, FREQUENCY (Hz)
f, FREQUENCY (Hz)
VIR, VOR VOLTAGE RANGE (
,±V)
AV, VOLTAGE GAIN (dB)
PHASE LAG (DEGREES)
10
8.0
6.0
4.0
2.0
0
−2.0
−4.0
−6.0
−8.0
−10
0 1020304050 60708090
140
120
100
80
60
40
20
0
−2010 100 1.0 k 10 k 100 k 1.0 M 10 M 100 M
10
8.0
6.0
4.0
2.0
0
−2.0
−4.0
−6.0
−8.0
−10
0 1.0 2.0 3.0 4.0 5.0 6.0 7.0 8.0 9.01.0 M 10 M100 k
0
18
16
12
8.0
4.0
225
180
135
90
45
0
Balance
1
4
VEE
R2
R1
R3
2
3
7
6
8
C1
VCC
VO
−VI
+VI
Frequency
Compensation
C2
R2
R1
VI
R3 C1
150 pF
Balance
VEE
VO
2
3
6
7
4
1
C2 = 1
2πfoR2
fo = 3.0 MHz
++
C1 ≥R1 Cs
R1 +R2
Cs = 30 pF
VCC
VOR, OUTPUT VOLTAGE RANGE ( V)±
Single−Pole Compensation
Output
Input
VOR, OUTPUT VOLTAGE RANGE ( V)±
Feedforward
Compensation
0
Output
Input
Feedforward
Compensation
Phase
Gain
Feedforward
Compensation
LM301A, LM201A, LM201AV
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7
PACKAGE DIMENSIONS
PDIP−8
N SUFFIX
CASE 626−05
ISSUE L
NOTES:
1. DIMENSION L TO CENTER OF LEAD WHEN
FORMED PARALLEL.
2. PACKAGE CONTOUR OPTIONAL (ROUND OR
SQUARE CORNERS).
3. DIMENSIONING AND TOLERANCING PER ANSI
Y14.5M, 1982.
14
58
F
NOTE 2 −A−
−B−
−T−
SEATING
PLANE
H
J
GDK
N
C
L
M
M
A
M
0.13 (0.005) B M
T
DIM MIN MAX MIN MAX
INCHESMILLIMETERS
A9.40 10.16 0.370 0.400
B6.10 6.60 0.240 0.260
C3.94 4.45 0.155 0.175
D0.38 0.51 0.015 0.020
F1.02 1.78 0.040 0.070
G2.54 BSC 0.100 BSC
H0.76 1.27 0.030 0.050
J0.20 0.30 0.008 0.012
K2.92 3.43 0.115 0.135
L7.62 BSC 0.300 BSC
M−−− 10 −−− 10
N0.76 1.01 0.030 0.040

LM301A, LM201A, LM201AV
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8
SOIC−8
D SUFFIX
CASE 751−07
ISSUE AB
SEATING
PLANE
1
4
58
N
J
X 45
K
NOTES:
1. DIMENSIONING AND TOLERANCING PER
ANSI Y14.5M, 1982.
2. CONTROLLING DIMENSION: MILLIMETER.
3. DIMENSION A AND B DO NOT INCLUDE
MOLD PROTRUSION.
4. MAXIMUM MOLD PROTRUSION 0.15 (0.006)
PER SIDE.
5. DIMENSION D DOES NOT INCLUDE DAMBAR
PROTRUSION. ALLOWABLE DAMBAR
PROTRUSION SHALL BE 0.127 (0.005) TOTAL
IN EXCESS OF THE D DIMENSION AT
MAXIMUM MATERIAL CONDITION.
6. 751−01 THRU 751−06 ARE OBSOLETE. NEW
STANDARD IS 751−07.
A
BS
D
H
C
0.10 (0.004)
DIM
AMIN MAX MIN MAX
INCHES
4.80 5.00 0.189 0.197
MILLIMETERS
B3.80 4.00 0.150 0.157
C1.35 1.75 0.053 0.069
D0.33 0.51 0.013 0.020
G1.27 BSC 0.050 BSC
H0.10 0.25 0.004 0.010
J0.19 0.25 0.007 0.010
K0.40 1.27 0.016 0.050
M0 8 0 8
N0.25 0.50 0.010 0.020
S5.80 6.20 0.228 0.244
−X−
−Y−
G
M
Y
M
0.25 (0.010)
−Z−
Y
M
0.25 (0.010) Z SXS
M

1.52
0.060
7.0
0.275
0.6
0.024 1.270
0.050
4.0
0.155
mm
inches
SCALE 6:1
*For additional information on our Pb−Free strategy and soldering
details, please download the ON Semiconductor Soldering and
Mounting Techniques Reference Manual, SOLDERRM/D.
SOLDERING FOOTPRINT*
ON Semiconductor and are registered trademarks of Semiconductor Components Industries, LLC (SCILLC). SCILLC reserves the right to make changes without further notice
to any products herein. SCILLC makes no warranty , representation or guarantee regarding the suitability of its products for any particular purpose, nor does SCILLC assume any liability
arising out of the application or use of any product or circuit, and specifically disclaims any and all liability, including without limitation special, consequential or incidental damages.
“Typical” parameters which may be provided in SCILLC data sheets and/or specifications can and do vary in different applications and actual performance may vary over time. All
operating parameters, including “Typicals” must be validated for each customer application by customer’s technical experts. SCILLC does not convey any license under its patent rights
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Phone: 81−3−5773−3850
LM301A/D
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