CMOS 4-BiT SinGle ChiP MiCROCOnTROlleR S1C6F016 Technical Manual Rev. 1.1 Evaluation board/kit and Development tool important notice 1. This evaluation board/kit or development tool is designed for use for engineering evaluation, demonstration, or development purposes only. Do not use it for other purpose. It is not intended to meet the requirement of design for finished product. 2. This evaluation board/kit or development tool is intended for use by an electronics engineer, and it is not the product for consumer. The user should use this goods properly and safely. Seiko Epson dose not assume any responsibility and liability of any kind of damage and/or fire coursed by usage of it. User should cease to use it when any abnormal issue occurs even during proper and safe use. 3. The part used for this evaluation board/kit or development tool is changed without any notice. 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COnFiGuRaTiOn OF PRODuCT nuMBeR Configuration of product number Devices S1 C 63158 F 0A01 00 Packing specifications 00 : Besides tape & reel 0A : TCP BL 2 directions 0B : Tape & reel BACK 0C : TCP BR 2 directions 0D : TCP BT 2 directions 0E : TCP BD 2 directions 0F : Tape & reel FRONT 0G : TCP BT 4 directions 0H : TCP BD 4 directions 0J : TCP SL 2 directions 0K : TCP SR 2 directions 0L : Tape & reel LEFT 0M : TCP ST 2 directions 0N : TCP SD 2 directions 0P : TCP ST 4 directions 0Q : TCP SD 4 directions 0R : Tape & reel RIGHT 99 : Specs not fixed Specification Package D: die form; F: QFP, B: BGA Model number Model name C: microcomputer, digital products Product classification S1: semiconductor Development tools S5U1 C 63000 A1 1 00 Packing specifications 00: standard packing Version 1: Version 1 Tool type Hx : ICE Ex : EVA board Px : Peripheral board Wx : Flash ROM writer for the microcomputer Xx : ROM writer peripheral board Cx : C compiler package Ax : Assembler package Dx : Utility tool by the model Qx : Soft simulator Yx : Writer software Corresponding model number 63000: common to S1C63 Family Tool classification C: microcomputer use Product classification S5U1: development tool for semiconductor products S1C6F016 Technical Manual (Rev. 1.1) Seiko Epson Corporation i COnTenTS - Contents 1 Outline ...........................................................................................................................1-1 1.1 Features ...........................................................................................................................1-1 1.2 Block Diagram ..................................................................................................................1-2 1.3 Mask Option .....................................................................................................................1-3 2 Pins and Package .........................................................................................................2-1 2.1 Pin Layout Diagram ..........................................................................................................2-1 2.1.1 QFP15-100pin ...................................................................................................2-1 2.1.2 Chip ...................................................................................................................2-2 2.2 Pin Description .................................................................................................................2-4 2.3 Package ...........................................................................................................................2-6 2.3.1 Plastic Package..................................................................................................2-6 2.3.2 Ceramic Package for Test Samples ...................................................................2-7 3 CPu and Memory ..........................................................................................................3-1 3.1 CPU..................................................................................................................................3-1 3.2 Code Memory Area ..........................................................................................................3-1 3.2.1 Code ROM .........................................................................................................3-1 3.2.2 Flash EEPROM Specifications ..........................................................................3-1 3.3 Data Memory Area ...........................................................................................................3-2 3.3.1 RAM ...................................................................................................................3-2 3.3.2 Data ROM ..........................................................................................................3-3 3.3.3 Display Memory .................................................................................................3-3 3.3.4 I/O Memory ........................................................................................................3-3 4 initial Reset ...................................................................................................................4-1 4.1 4.2 4.3 4.4 4.5 Initial Reset Circuit ...........................................................................................................4-1 Reset Terminal (RESET) ..................................................................................................4-1 Simultaneous High Input to P0x Ports (P00-P03) ...........................................................4-2 Internal Register at Initial Resetting .................................................................................4-2 Terminal Settings at Initial Resetting ................................................................................4-3 5 Power Supply ................................................................................................................5-1 5.1 5.2 5.3 5.4 5.5 5.6 Operating Voltage .............................................................................................................5-1 Internal Power Supply Circuit ...........................................................................................5-1 Controlling LCD Power Supply .........................................................................................5-2 Heavy Load Protection Function ......................................................................................5-2 I/O Memory for Power Supply Circuit ...............................................................................5-3 Precautions ......................................................................................................................5-4 6 interrupt Controller.......................................................................................................6-1 6.1 6.2 6.3 6.4 6.5 6.6 Configuration of Interrupt Controller .................................................................................6-1 Interrupt Factors ...............................................................................................................6-3 Interrupt Mask ..................................................................................................................6-3 Interrupt Vector .................................................................................................................6-4 I/O Memory of Interrupt Controller ...................................................................................6-5 Precautions ......................................................................................................................6-8 7 Oscillation Circuit and Clock Control .........................................................................7-1 7.1 Oscillation Circuit .............................................................................................................7-1 7.1.1 Configuration of Oscillation Circuit .....................................................................7-1 ii Seiko Epson Corporation S1C6F016 TECHNICAL MANUAL (Rev. 1.1) COnTenTS 7.1.2 Mask Option .......................................................................................................7-1 7.1.3 OSC1 Oscillation Circuit ....................................................................................7-1 7.1.4 OSC3 Oscillation Circuit ....................................................................................7-2 7.2 Switching the CPU Clock .................................................................................................7-3 7.3 7.4 7.5 7.6 7.7 HALT and SLEEP .............................................................................................................7-3 Control of Peripheral Circuit Clocks .................................................................................7-4 Clock Output (FOUT) .......................................................................................................7-4 I/O Memory for Oscillation Circuit/Clock Output Control ..................................................7-5 Precautions ......................................................................................................................7-6 8 Watchdog Timer ............................................................................................................8-1 8.1 8.2 8.3 8.4 Configuration of Watchdog Timer .....................................................................................8-1 Interrupt Function .............................................................................................................8-1 I/O Memory of Watchdog Timer .......................................................................................8-1 Precautions ......................................................................................................................8-2 9 Clock Timer ..................................................................................................................9-1 9.1 9.2 9.3 9.4 9.5 9.6 Configuration of Clock Timer ............................................................................................9-1 Controlling Operating Clock .............................................................................................9-1 Data Read and Hold Function ..........................................................................................9-1 Interrupt Function .............................................................................................................9-2 I/O Memory of Clock Timer ..............................................................................................9-2 Precautions ......................................................................................................................9-4 10 Stopwatch Timer ........................................................................................................10-1 10.1 10.2 10.3 10.4 10.5 10.6 10.7 10.8 10.9 Configuration of Stopwatch Timer .................................................................................10-1 Controlling Operating Clock ..........................................................................................10-1 Counter and Prescaler ..................................................................................................10-1 Capture Buffer and Hold Function .................................................................................10-2 Stopwatch Timer RUN/STOP and Reset .......................................................................10-3 Direct Input Function and Key Mask .............................................................................10-3 Interrupt Function ..........................................................................................................10-6 I/O Memory of Stopwatch Timer....................................................................................10-7 Precautions ..................................................................................................................10-10 11 Programmable Timer .................................................................................................11-1 11.1 Configuration of Programmable Timer ..........................................................................11-1 11.2 Controlling Operating Clock ..........................................................................................11-2 11.3 Basic Counter Operation ...............................................................................................11-3 11.4 Event Counter Mode (Timers 0 and 2) ..........................................................................11-4 11.5 PWM mode (Timers 0-3) ..............................................................................................11-5 11.6 16-bit timer mode (Timer 0 + 1, Timer 2 + 3) ................................................................11-6 11.7 Interrupt Function ..........................................................................................................11-6 11.8 TOUT Output Control ....................................................................................................11-7 11.9 Clock Output to Serial Interface and R/F Converter ......................................................11-7 11.10 I/O Memory of Programmable Timer ...........................................................................11-8 11.11 Precautions ................................................................................................................11-13 12 i/O Ports .....................................................................................................................12-1 12.1 Configuration of I/O Ports ..............................................................................................12-1 12.2 Mask Option ..................................................................................................................12-2 S1C6F016 Technical Manual (Rev. 1.1) Seiko Epson Corporation iii COnTenTS 12.3 12.4 12.5 12.6 12.7 12.8 I/O Control Registers and Input/Output Mode ...............................................................12-3 Input Interface Level ......................................................................................................12-3 Pull-down During Input Mode ........................................................................................12-3 Key Input Interrupt Function ..........................................................................................12-3 I/O memory of I/O ports ................................................................................................12-5 Precautions ..................................................................................................................12-10 13 Serial interface ...........................................................................................................13-1 13.1 13.2 13.3 13.4 13.5 Configuration of Serial Interface ....................................................................................13-1 Serial Interface Terminals ..............................................................................................13-1 Mask Option ..................................................................................................................13-2 Operating Mode of Serial Interface ...............................................................................13-2 Setting Synchronous Clock ...........................................................................................13-4 13.5.1 Selecting Source Clock ...................................................................................13-4 13.5.2 Selecting Synchronous Clock Format .............................................................13-4 13.6 Data Input/Output and Interrupt Function......................................................................13-5 13.6.1 Serial Data Output Procedure and Interrupt ...................................................13-5 13.6.2 Serial Data Input Procedure and Interrupt ......................................................13-5 13.6.3 Serial Data Input/Output Permutation .............................................................13-6 13.6.4 SRDY Signal ...................................................................................................13-6 13.6.5 Timing Chart ...................................................................................................13-6 13.7 Data Transfer in SPI Mode ............................................................................................13-8 13.8 I/O Memory of Serial Interface ......................................................................................13-9 13.9 Precautions ..................................................................................................................13-12 14 lCD Driver ..................................................................................................................14-1 14.1 Configuration of LCD Driver ..........................................................................................14-1 14.2 Mask Option ..................................................................................................................14-1 14.2.1 SEG/GPIO/RFC Terminal Configuration ........................................................14-1 14.2.2 Power Source for LCD Driving ........................................................................14-2 14.2.3 Segment Option ..............................................................................................14-2 14.3 LCD Display Control ......................................................................................................14-8 14.3.1 Selecting Display Mode ..................................................................................14-8 14.3.2 Switching Drive Duty .......................................................................................14-8 14.3.3 Switching Frame Frequency ...........................................................................14-8 14.3.4 Drive Waveform...............................................................................................14-8 14.3.5 Static Drive.....................................................................................................14-15 14.3.6 LCD Contrast Adjustment ..............................................................................14-15 14.4 Display Memory ...........................................................................................................14-16 14.5 I/O Memory of LCD Driver............................................................................................14-16 14.6 Precautions ..................................................................................................................14-18 15 Sound Generator .......................................................................................................15-1 15.1 15.2 15.3 15.4 15.5 15.6 15.7 15.8 Configuration of Sound Generator ................................................................................15-1 Controlling Operating Clock ..........................................................................................15-1 Buzzer Output Control ...................................................................................................15-1 Buzzer Frequency and Sound Level Settings ...............................................................15-2 Digital Envelope ...........................................................................................................15-3 One-shot output ...........................................................................................................15-3 I/O Memory of Sound Generator ...................................................................................15-4 Precautions ...................................................................................................................15-6 iv Seiko Epson Corporation S1C6F016 TECHNICAL MANUAL (Rev. 1.1) COnTenTS 16 integer Multiplier........................................................................................................16-1 16.1 16.2 16.3 16.4 16.5 16.6 16.7 Configuration of Integer Multiplier .................................................................................16-1 Controlling Clock Manager ............................................................................................16-1 Multiplication Mode .......................................................................................................16-1 Division Mode................................................................................................................16-2 Execution Cycle.............................................................................................................16-2 I/O Memory of Integer Multiplier ....................................................................................16-3 Precautions ...................................................................................................................16-5 17 R/F Converter .............................................................................................................17-1 17.1 17.2 17.3 17.4 17.5 17.6 17.7 17.8 Configuration of R/F Converter .....................................................................................17-1 Controlling Operating Clock ..........................................................................................17-1 Connection Terminals and CR Oscillation Circuit ..........................................................17-2 Operation of R/F Conversion.........................................................................................17-4 Interrupt Function ..........................................................................................................17-6 Continuous Oscillation Function ....................................................................................17-8 I/O Memory of R/F Converter ........................................................................................17-8 Precautions ..................................................................................................................17-11 18 SVD (Supply Voltage Detection) Circuit ...................................................................18-1 18.1 18.2 18.3 18.4 Configuration of SVD Circuit .........................................................................................18-1 SVD Operation ..............................................................................................................18-1 I/O Memory of SVD Circuit ............................................................................................18-2 Precautions ...................................................................................................................18-2 19 electrical Characteristics..........................................................................................19-1 19.1 19.2 19.3 19.4 Absolute Maximum Rating ............................................................................................19-1 Recommended Operating Conditions ...........................................................................19-1 DC Characteristics ........................................................................................................19-2 Analog Circuit Characteristics and Current Consumption .............................................19-2 19.4.1 LCD Driver ......................................................................................................19-2 19.4.2 SVD Circuit .....................................................................................................19-3 19.4.3 R/F Converter Circuit ......................................................................................19-3 19.4.4 Current Consumption ......................................................................................19-4 19.5 Oscillation Characteristics .............................................................................................19-4 19.6 Serial Interface AC Characteristics ...............................................................................19-5 19.7 Timing Chart ..................................................................................................................19-5 19.8 Characteristics Curves (reference value) ......................................................................19-6 20 Basic external Wiring Diagram ................................................................................20-1 appendix a list of i/O Registers................................................................................ aP-a-1 FF00H FF01H FF02H-FF03H FF04H-FF05H FF10H-FF1BH FF20H-FF3FH FF40H-FF42H FF44H-FF47H FF48H-FF4DH FF50H-FF52H FF58H-FF5CH S1C6F016 Technical Manual (Rev. 1.1) Oscillation Circuit ........................................................................ AP-A-1 Watchdog Timer ......................................................................... AP-A-1 Power Supply Circuit .................................................................. AP-A-1 SVD Circuit ................................................................................. AP-A-1 Clock Manager ........................................................................... AP-A-1 I/O Ports ..................................................................................... AP-A-2 Clock Timer ................................................................................. AP-A-4 Sound Generator ........................................................................ AP-A-4 Stopwatch Timer ......................................................................... AP-A-4 LCD Driver .................................................................................. AP-A-5 Serial Interface ........................................................................... AP-A-5 Seiko Epson Corporation v COnTenTS FF60H-FF6BH FF70H-FF76H FF80H-FF9FH FFE1H-FFFFH R/F Converter .............................................................................. AP-A-5 Integer Multiplier ......................................................................... AP-A-6 Programmable Timer .................................................................. AP-A-7 Interrupt Controller ...................................................................... AP-A-9 appendix B Peripheral Circuit Boards for S1C6F016............................................... aP-B-1 B.1 Names and Functions of Each Part ............................................................................. AP-B-1 B.1.1 S5U1C63000P6............................................................................................. AP-B-1 B.1.2 S5U1C6F016P2 ............................................................................................ AP-B-3 B.2 Connecting to the Target System ................................................................................. AP-B-5 B.3 Downloading to S5U1C63000P6 ................................................................................. AP-B-8 B.4 Usage Precautions ...................................................................................................... AP-B-8 B.4.1 Operational precautions ............................................................................... AP-B-8 B.4.2 Differences with the actual IC ........................................................................ AP-B-9 B.5 Product Specifications ................................................................................................ AP-B-12 B.5.1 Specifications of S5U1C63000P6 ................................................................ AP-B-12 B.5.2 Specifications of S5U1C6F016P2 ................................................................ AP-B-12 appendix C Flash eePROM Programming ............................................................... aP-C-1 C.1 Outline of Writing Tools ................................................................................................ AP-C-1 C.2 Serial Programming ..................................................................................................... AP-C-1 C.2.1 Serial Programming Environment.................................................................. AP-C-1 C.2.2 System Connection for Serial Programming ................................................. AP-C-2 C.2.3 Serial Programming Procedure ..................................................................... AP-C-3 C.2.4 Connection Diagram for Serial Programming ................................................ AP-C-7 C.3 On Board Writer Control Software ............................................................................... AP-C-9 C.3.1 Starting Up .................................................................................................... AP-C-9 C.3.2 Setup ............................................................................................................ AP-C-10 C.3.3 Command Details ......................................................................................... AP-C-12 1. LOAD PROGRAM (HSA file, LSA file) .............................................................. AP-C-12 2. LOAD DATA (CSA file) ...................................................................................... AP-C-13 3. LOAD SEGMENT (SSA file) ............................................................................. AP-C-13 4. ERASE PROGRAM, DATA, SEGMENT ............................................................ AP-C-14 5. BLANK CHECK PROGRAM, DATA, SEGMENT ............................................... AP-C-14 6. PROGRAM PROGRAM, DATA, SEGMENT ...................................................... AP-C-15 7. VERIFY PROGRAM, DATA, SEGMENT ........................................................... AP-C-15 8. READ PROGRAM, DATA, SEGMENT .............................................................. AP-C-16 9. MACRO ............................................................................................................. AP-C-16 10. DUMP MEMORY............................................................................................. AP-C-17 11. OPEN LOG FILE ............................................................................................. AP-C-18 12. SAVE PROGRAM ........................................................................................... AP-C-18 13. SAVE DATA ..................................................................................................... AP-C-18 C.3.4 List of Commands ........................................................................................ AP-C-19 C.3.5 List of Error Messages ................................................................................. AP-C-19 C.4 Flash EEPROM Programming Notes ......................................................................... AP-C-20 appendix D Power Saving .......................................................................................... aP-D-1 D.1 Power Saving by Clock Control .................................................................................... AP-D-1 D.2 Power Saving by Power Supply Control ....................................................................... AP-D-3 appendix e S1C6F016 Mask Data Generation Procedure ....................................... aP-e-1 E.1 E.2 E.3 E.4 Mask Data Generation Flowchart ................................................................................ AP-E-1 Function Option File Generation Procedure ................................................................ AP-E-2 Segment Option File Generation Procedure ................................................................ AP-E-2 Mask Data File Generation Procedure ........................................................................ AP-E-3 vi Seiko Epson Corporation S1C6F016 TECHNICAL MANUAL (Rev. 1.1) COnTenTS appendix F Summary of notes .................................................................................. aP-F-1 F.1 Summary of Notes by Function .................................................................................... AP-F-1 F.2 Precautions on Mounting .............................................................................................. AP-F-5 Revision history S1C6F016 Technical Manual (Rev. 1.1) Seiko Epson Corporation vii 1 OuTline 1 Outline The S1C6F016 is a 4-bit microcontroller that features low voltage operations and low current consumption. It consists of a 4-bit core CPU S1C63000 as the core CPU, Flash EEPROM (16,384 words x 13 bits), RAM (2,048 words x 4 bits), supply voltage detection (SVD) circuit, multiply-divide circuit, serial interface, timers, and sound generator. It also incorporates a segment LCD controller/driver that can drive a maximum 56-segment x 8-common LCD panel, and an R/F converter that can measure temperature and humidity using sensors such as a thermistor. The S1C6F016 is suitable for battery driven clocks and watches with temperature and humidity measurement functions. The S1C6F016 allows choice from eight different models by mask-option selections and shipment form selections as shown in Table 1.1. 1 2 3 4 5 6 7 8 Table 1.1 Model lineup Mask option type * Shipment form Standard mask option Type B QFP15-100pin Die form Standard mask option Type E QFP15-100pin Die form Standard mask option Type G QFP15-100pin Die form Custom mask option QFP15-100pin Die form * See Section 1.3, "Mask Option." This product uses SuperFlash(R) technology licensed from Silicon Storage Technology, Inc. 1.1 Features Core .......................................................... 4-bit core CPU S1C63000 OSC1 oscillation circuit ........................... 32.768 kHz (Typ.) crystal oscillation circuit OSC3 oscillation circuit ........................... 4.2 MHz (Max.) ceramic oscillation circuit, 1.8 MHz (Typ.) CR oscillation circuit (external R), or 500 kHz (Typ.) CR oscillation circuit (built-in R) (*1) Instruction set ........................................... Basic instruction: 47 types (411 instructions with all) Addressing mode: 8 types Instruction execution time ........................ During operation at 32.768 kHz: 61 sec 122 sec 183 sec During operation at 4 MHz: 0.5 sec 1 sec 1.5 sec Flash EEPROM capacity ......................... Code ROM: 16,384 words x 13 bits Data ROM: 4,096 words x 4 bits RAM capacity .......................................... Data memory: 2,048 words x 4 bits Display memory: 448 bits I/O port ..................................................... 24 bits Pull-down resistors can be incorporated. (*1) The pins can be switched for peripheral circuit inputs/outputs. (*2) Serial interface ......................................... 1 port, 8-bit clock synchronous system LCD driver ............................................... 56 segments (Max.) x 8, 7, 6, 5, 4, or 3 commons (*2) Time base counters................................... Clock timer 1/1000-second stopwatch timer with direct key input function Programmable timer................................. 16-bit timer x 2 channels Each 16-bit timer is configurable to two 8-bit timer channels (*2) Watchdog timer ........................................ Built-in Sound generator ....................................... With envelope and 1-shot output functions R/F converter ........................................... 2 channels, CR oscillation type R/F converter with 20-bit counters Supports resistive humidity sensors. Multiply-divide circuit ............................ 8-bit accumulator x 1 channel Multiplication: 8 bits x 8 bits 16-bit product Division: 16 bits / 8 bits 8-bit quotient and 8-bit remainder Supply voltage detection (SVD) circuit ... Programmable 16 detection voltage levels (*2) S1C6F016 Technical Manual (Rev. 1.1) Seiko Epson Corporation 1-1 1 OuTline External interrupt ..................................... Key input interrupt: 8 systems Internal interrupt ...................................... Watchdog timer interrupt (NMI): 1 system Clock timer interrupt: 8 systems Stopwatch timer interrupt: 4 systems Programmable timer interrupt: 8 systems Serial interface interrupt: 1 system R/F converter interrupt: 3 systems Power supply voltage ............................... 1.8 to 3.6 V (for normal operation) 2.7 to 3.6 V (for Flash programming) Operating temperature range.................... -20 to 70C Current consumption (Typ.) ..................... During SLEEP (32 kHz) 0.7 A During HALT (32 kHz) 2 A During running (32 kHz) 9 A During running (4 MHz) 950 A Shipment form ......................................... QFP15-100pin or die form *1: Can be selected with mask option. *2: Can be selected with software. 1.2 Block Diagram Code ROM (Flash) DMOD DCLK DRXD DTXD TEST1-3 Flash Controller 16,384 words x 13 bits Data ROM VC1-3 CA, CB VSS Interrupt Controller Clock Management Unit OSC Stopwatch Timer Watchdog Timer Programmable Timer Clock Timer Serial Interface Power Controller SVD RESET P00 / KEY00 / RUN_STP / KRST00 P01 / KEY01 / LAP / KRST01 P02 / KEY02 / KRST02 P03 / KEY03 / KRST03 RAM 2,048 words x 4 bits VDD VD1 KRST00-03 Core CPu S1C63000 4,096 words x 4 bits OSC1 OSC2 OSC3 OSC4 System Reset Control KEY00-03 KEY10-13 FOUT RUN_STP LAP EVIN_A, B TOUT_A, B SCLK SOUT SIN SRDY_SS Sound Generator R/F Converter BZ RFOUT RFIN0 SEN0, REF0 RFIN1 SEN1, REF1 HUD P10 / KEY10 / EVIN_A P11 / KEY11/ TOUT_A P12 / KEY12 / BZ P13 / KEY13 / FOUT P20 P21 P22 / EVIN_B P23 / TOUT_B SEG44 SEG45 SEG46 SEG47 P30 / SCLK P31 / SOUT P32 / SIN P33 / SRDY_SS SEG40 SEG41 SEG42 SEG43 P40 P41 P42 P43 SEG36 SEG37 SEG38 SEG39 P50 / RFOUT P51 / SEN0 P52 / REF0 P53 / RFIN0 SEG48 SEG49 SEG50 SEG51 HUD SEN1 REF1 RFIN1 SEG36-55 Integer Multiplier TEST Test LCD Controller & Driver SEG55 SEG54 SEG53 SEG52 Mask option SEG0-35 COM0-7 I/O Controller & I/O Port Figure 1.2.1 Block diagram 1-2 Seiko Epson Corporation S1C6F016 TECHNICAL MANUAL (Rev. 1.1) 1 OuTline 1.3 Mask Option S1C6F016 provides three standard mask option models (Type B, Type E, and Type G) and a custom mask option model that allows selection of each optional specification. (See Table 1.1 and Tables 1.3.1-1.3.5.) In the custom option model, several hardware specifications are prepared in each optional item, and one of them can be selected according to the application. Use the function option generator "winfog" and segment option generator "winsog" provided as development tools of S1C6F016 for this selection. Mask pattern of the IC is finally generated based on the data created by winfog and winsog. (The mask pattern for the segment option will be generated using only the segment output specification (S) in the custom mask option data created by winsog. The segment allocation data must be programmed.) Refer to the "S5U1C63000A Manual" for winfog and winsog. <Outline of the mask option> (1) OSC1 oscillation circuit The OSC1 oscillator type is fixed at crystal oscillation. Refer to "OSC1 Oscillation Circuit" in the "Oscillation Circuit and Clock Control" chapter for details. (2) OSC3 oscillation circuit The custom mask option model provides an option to select the OSC3 oscillator type from ceramic oscillation, CR oscillation (external R) and CR oscillation (built-in R). The standard mask option Type B model is configured with a ceramic oscillation circuit. The Type E and Type G models are configured with a CR oscillation circuit (external R). Refer to "OSC3 Oscillation Circuit" in the "Oscillation Circuit and Clock Control" chapter for details. (3) ReSeT terminal pull-down resistor The custom mask option model provides an option to select whether an internal pull-down resistor is incorporated into the RESET input port. The standard mask option models have a built-in pull-down resistor. Refer to "Reset Terminal (RESET)" in the "Initial Reset" chapter for details. (4) SeG/GPiO/RFC selector The I/O port (P20-P23, P30-P33, P40-P43) and R/F converter input/output pins are shared with the SEG36- SEG55 terminals. The custom mask option model allows selection of whether each of these pins are used for the I/O port or R/F converter or used for the SEG output. The standard mask option Type B and Type G models are configured for the I/O port or R/F converter pins. The standard mask option Type E model is configured for the SEG output pins. Refer to "Mask Option" in the "LCD Driver" chapter for details. (5) i/O port pull-down resistor The custom mask option model provides an option to select whether an internal pull-down resistor that will be enabled in input mode is incorporated into each I/O port (P00-P03, P10-P13, P20-P23, P30-P33, P40-P43, P50-P53). The standard mask option Type B and Type E models have built-in pull-down resistors for all I/O ports. The standard mask option Type G model has no built-in pull-down resistors for P10 and P11 and all other I/O ports include a pull-down resistor. Refer to "Mask Option" in the "I/O Ports" chapter for details. (6) Output specification of the i/O port The custom mask option model provides an option to select either complementary output or P-channel open drain output as the output cell type of each I/O port (P00-P03, P10-P13, P20-P23, P30-P33, P40-P43, P50-P53). The standard mask option models are configured with complementary output for all I/O ports. Refer to "Mask Option" in the "I/O Ports" chapter for details. Do not configure the P50-P53 ports to P-channel open drain output if the R/F converter (channel 0) is used. (7) Multiple key entry reset function (by simultaneous high input to the P0x ports) The custom mask option model provides an option to select whether the function to reset the IC by pressing multiple keys simultaneously is implemented or not. A combination of the P0x ports (P00-P03) to be used for this function can also be selected. The standard mask option models do not have this function. Refer to "Simultaneous High Input to P0x Ports (P00-P03)" in the "Initial Reset" chapter for details. S1C6F016 Technical Manual (Rev. 1.1) Seiko Epson Corporation 1-3 1 OuTline (8) Time authorize circuit for the multiple key entry reset function When the multiple key entry reset option (option (7)) is selected in the custom mask option model, the time authorize circuit can also be incorporated. The time authorize circuit measures the high pulse width of the simultaneous input signals and asserts the reset signal if it is longer than the predetermined time. This option is not available when the multiple key entry reset option is not selected. Refer to "Simultaneous High Input to P0x Ports (P00-P03)" in the "Initial Reset" chapter for details. (9) lCD drive power supply The custom mask option model allows use of an external power supply as the LCD drive power source. The standard mask option models support internal power supply only. Refer to "Mask Option" in the "LCD Driver" chapter for details. (10) lCD segment specification The LCD segment specification of the custom mask option model and standard mask option Type B and Type E models is fixed at LCD segment output (S). The LCD segment specification of the standard mask option Type G model is fixed at DC complementary output (C). Refer to "Mask Option" in the "LCD Driver" chapter for details. Table 1.3.1 Option list Optional item Standard Type B Standard Type E OSC1 oscillation circuit n 1. Crystal (32.768 kHz) n 1. Crystal (32.768 kHz) OSC3 oscillation circuit n 2. CR (external R) n 3. Ceramic (4.2 MHz) RESET terminal pulln 1. Use n 1. Use down resistor SEG/GPIO/ P20 n 1. I/O RFC selector n 2. SEG P21 n 1. I/O n 2. SEG P22 n 1. I/O n 2. SEG P23 n 1. I/O n 2. SEG P30 n 1. I/O n 2. SEG P31 n 1. I/O n 2. SEG P32 n 1. I/O n 2. SEG P33 n 1. I/O n 2. SEG P40 n 1. I/O n 2. SEG P41 n 1. I/O n 2. SEG P42 n 1. I/O n 2. SEG P43 n 1. I/O n 2. SEG P50 n 1. I/O n 2. SEG P51 n 1. I/O n 2. SEG P52 n 1. I/O n 2. SEG P53 n 1. I/O n 2. SEG RFIN1 n 1. RFC n 2. SEG REF1 n 1. RFC n 2. SEG SEN1 n 1. RFC n 2. SEG HUD n 1. RFC n 2. SEG Standard Type G Custom n 1. Crystal (32.768 kHz) n 1. Crystal (32.768 kHz) 1. CR (built-in R) n 2. CR (external R) 2. CR (external R) 3. Ceramic (4.2 MHz) 1. Use n 1. Use 2. Not Use 1. I/O n 1. I/O 2. SEG 1. I/O n 1. I/O 2. SEG 1. I/O n 1. I/O 2. SEG 1. I/O n 1. I/O 2. SEG 1. I/O n 1. I/O 2. SEG 1. I/O n 1. I/O 2. SEG 1. I/O n 1. I/O 2. SEG 1. I/O n 1. I/O 2. SEG 1. I/O n 1. I/O 2. SEG 1. I/O n 1. I/O 2. SEG 1. I/O n 1. I/O 2. SEG 1. I/O n 1. I/O 2. SEG 1. I/O n 1. I/O 2. SEG 1. I/O n 1. I/O 2. SEG 1. I/O n 1. I/O 2. SEG 1. I/O n 1. I/O 2. SEG 1. RFC n 1. RFC 2. SEG 1. RFC n 1. RFC 2. SEG 1. RFC n 1. RFC 2. SEG 1. RFC n 1. RFC 2. SEG 1-4 Seiko Epson Corporation S1C6F016 TECHNICAL MANUAL (Rev. 1.1) 1 OuTline Optional item I/O port pullP00 down resistor P01 Standard Type B n 1. Use Standard Type E n 1. Use Standard Type G n 1. Use n 1. Use n 1. Use n 1. Use P02 n 1. Use n 1. Use n 1. Use P03 n 1. Use n 1. Use n 1. Use P10 n 1. Use n 1. Use P11 n 1. Use n 1. Use P12 n 1. Use n 1. Use n 2. Not Use n 1. Use P13 n 1. Use n 1. Use n 1. Use P20 n 1. Use n 1. Use n 1. Use P21 n 1. Use n 1. Use n 1. Use P22 n 1. Use n 1. Use n 1. Use P23 n 1. Use n 1. Use n 1. Use P30 n 1. Use n 1. Use n 1. Use P31 n 1. Use n 1. Use n 1. Use P32 n 1. Use n 1. Use n 1. Use P33 n 1. Use n 1. Use n 1. Use P40 n 1. Use n 1. Use n 1. Use P41 n 1. Use n 1. Use n 1. Use P42 n 1. Use n 1. Use n 1. Use P43 n 1. Use n 1. Use n 1. Use P50 n 1. Use n 1. Use n 1. Use P51 n 1. Use n 1. Use n 1. Use P52 n 1. Use n 1. Use n 1. Use P53 n 1. Use n 1. Use n 1. Use I/O port output P00 specification P01 n 1. Complementary n 1. Complementary n 1. Complementary n 1. Complementary n 1. Complementary n 1. Complementary P02 n 1. Complementary n 1. Complementary n 1. Complementary P03 n 1. Complementary n 1. Complementary n 1. Complementary P10 n 1. Complementary n 1. Complementary n 1. Complementary P11 n 1. Complementary n 1. Complementary n 1. Complementary P12 n 1. Complementary n 1. Complementary n 1. Complementary P13 n 1. Complementary n 1. Complementary n 1. Complementary P20 n 1. Complementary n 1. Complementary n 1. Complementary P21 n 1. Complementary n 1. Complementary n 1. Complementary P22 n 1. Complementary n 1. Complementary n 1. Complementary n 2. Not Use S1C6F016 Technical Manual (Rev. 1.1) Seiko Epson Corporation Custom 1. Use 2. Not Use 1. Use 2. Not Use 1. Use 2. Not Use 1. Use 2. Not Use 1. Use 2. Not Use 1. Use 2. Not Use 1. Use 2. Not Use 1. Use 2. Not Use 1. Use 2. Not Use 1. Use 2. Not Use 1. Use 2. Not Use 1. Use 2. Not Use 1. Use 2. Not Use 1. Use 2. Not Use 1. Use 2. Not Use 1. Use 2. Not Use 1. Use 2. Not Use 1. Use 2. Not Use 1. Use 2. Not Use 1. Use 2. Not Use 1. Use 2. Not Use 1. Use 2. Not Use 1. Use 2. Not Use 1. Use 2. Not Use 1. Complementary 2. Pch Open Drain 1. Complementary 2. Pch Open Drain 1. Complementary 2. Pch Open Drain 1. Complementary 2. Pch Open Drain 1. Complementary 2. Pch Open Drain 1. Complementary 2. Pch Open Drain 1. Complementary 2. Pch Open Drain 1. Complementary 2. Pch Open Drain 1. Complementary 2. Pch Open Drain 1. Complementary 2. Pch Open Drain 1. Complementary 2. Pch Open Drain 1-5 1 OuTline Optional item I/O port output P23 specification P30 Standard Type B n 1. Complementary Standard Type E n 1. Complementary Standard Type G n 1. Complementary n 1. Complementary n 1. Complementary n 1. Complementary P31 n 1. Complementary n 1. Complementary n 1. Complementary P32 n 1. Complementary n 1. Complementary n 1. Complementary P33 n 1. Complementary n 1. Complementary n 1. Complementary P40 n 1. Complementary n 1. Complementary n 1. Complementary P41 n 1. Complementary n 1. Complementary n 1. Complementary P42 n 1. Complementary n 1. Complementary n 1. Complementary P43 n 1. Complementary n 1. Complementary n 1. Complementary P50 n 1. Complementary n 1. Complementary n 1. Complementary P51 n 1. Complementary n 1. Complementary n 1. Complementary P52 n 1. Complementary n 1. Complementary n 1. Complementary P53 n 1. Complementary n 1. Complementary n 1. Complementary P0x port multiple key n 1. Not Use entry reset combination n 1. Not Use n 1. Not Use P0x port multiple key n 1. Not Use entry reset time authorization LCD drive power n 1. Internal 1/3 bias supply n 1. Not Use n 1. Not Use n 1. Internal 1/3 bias n 1. Internal 1/3 bias Custom 1. Complementary 2. Pch Open Drain 1. Complementary 2. Pch Open Drain 1. Complementary 2. Pch Open Drain 1. Complementary 2. Pch Open Drain 1. Complementary 2. Pch Open Drain 1. Complementary 2. Pch Open Drain 1. Complementary 2. Pch Open Drain 1. Complementary 2. Pch Open Drain 1. Complementary 2. Pch Open Drain 1. Complementary 2. Pch Open Drain * 1. Complementary 2. Pch Open Drain * 1. Complementary 2. Pch Open Drain * 1. Complementary 2. Pch Open Drain * 1. Not Use 2. Use <P00, P01> 3. Use <P00, P01, P02> 4. Use <P00, P01, P02, P03> 1. Not Use 2. Use 1. Internal 1/3 bias 2. Ext. 1/3 bias, VDD = VC2 (4.5 V panel) 3. Ext.1/3 bias, VDD = VC3 (3.0 V panel) 4. Ext. 1/2 bias, VDD = VC3, VC1 = VC2 (3.0 V panel) Selectable n Fixed Do not select "Pch Open Drain" as the P50-P53 port output specification if the R/F converter (channel 0) is used. 1-6 Seiko Epson Corporation S1C6F016 TECHNICAL MANUAL (Rev. 1.1) 1 OuTline Table 1.3.2 Segment option (standard mask option Type B) Pin name COM0 H L D COM1 H L D COM2 H L D Address (F0xxH) COM3 COM4 H L D H L D SEG0 SEG1 SEG2 SEG3 SEG4 SEG5 SEG6 SEG7 SEG8 SEG9 SEG10 SEG11 SEG12 SEG13 SEG14 SEG15 SEG16 SEG17 SEG18 SEG19 SEG20 SEG21 SEG22 SEG23 SEG24 SEG25 SEG26 SEG27 SEG28 SEG29 SEG30 SEG31 SEG32 SEG33 SEG34 SEG35 SEG36 SEG37 SEG38 SEG39 SEG40 SEG41 SEG42 SEG43 SEG44 SEG45 SEG46 SEG47 SEG48 SEG49 SEG50 SEG51 SEG52 SEG53 SEG54 SEG55 <address> H: RAM data high-order address (0-7) L: RAM data low-order address (0-F) D: Data bit (0-3) H COM5 L D H COM6 L D H COM7 L D Output specification nS nS nS nS nS nS nS nS nS nS nS nS nS nS nS nS nS nS nS nS nS nS nS nS nS nS nS nS nS nS nS nS nS nS nS nS nS nS nS nS nS nS nS nS nS nS nS nS nS nS nS nS nS nS nS nS C C C C C C C C C C C C C C C C C C C C C C C C C C C C C C C C C C C C C C C C C C C C C C C C C C C C C C C C N N N N N N N N N N N N N N N N N N N N N N N N N N N N N N N N N N N N N N N N N N N N N N N N N N N N N N N N <Output specification> S: Segment output C: Complementary output N: Nch open drain output Notes for using the segment option generator "winsog" (standard mask option Type B) 1. Any display memory address can be allocated to SEG0 to SEG35. 2. Always select "LCD segment output (S)" as the output specification of SEG0 to SEG35, as it is fixed at segment output. 3. Configurations for nonexistent SEG pins (SEG36 to SEG55) * Always select "LCD segment output (S)" as the output specification of SEG36 to SEG55. * Leave the address cells for SEG36 to SEG55 blank. (Unused addresses will be allocated.) S1C6F016 Technical Manual (Rev. 1.1) Seiko Epson Corporation 1-7 1 OuTline Table 1.3.3 Segment option (standard mask option Type E) Pin name COM0 H L D COM1 H L D COM2 H L D Address (F0xxH) COM3 COM4 H L D H L D SEG0 SEG1 SEG2 SEG3 SEG4 SEG5 SEG6 SEG7 SEG8 SEG9 SEG10 SEG11 SEG12 SEG13 SEG14 SEG15 SEG16 SEG17 SEG18 SEG19 SEG20 SEG21 SEG22 SEG23 SEG24 SEG25 SEG26 SEG27 SEG28 SEG29 SEG30 SEG31 SEG32 SEG33 SEG34 SEG35 SEG36 SEG37 SEG38 SEG39 SEG40 SEG41 SEG42 SEG43 SEG44 SEG45 SEG46 SEG47 SEG48 SEG49 SEG50 SEG51 SEG52 SEG53 SEG54 SEG55 <address> H: RAM data high-order address (0-7) L: RAM data low-order address (0-F) D: Data bit (0-3) H COM5 L D H COM6 L D H COM7 L D Output specification nS nS nS nS nS nS nS nS nS nS nS nS nS nS nS nS nS nS nS nS nS nS nS nS nS nS nS nS nS nS nS nS nS nS nS nS nS nS nS nS nS nS nS nS nS nS nS nS nS nS nS nS nS nS nS nS C C C C C C C C C C C C C C C C C C C C C C C C C C C C C C C C C C C C C C C C C C C C C C C C C C C C C C C C N N N N N N N N N N N N N N N N N N N N N N N N N N N N N N N N N N N N N N N N N N N N N N N N N N N N N N N N <Output specification> S: Segment output C: Complementary output N: Nch open drain output Notes for using the segment option generator "winsog" (standard mask option Type E) 1. Any display memory address can be allocated to SEG0 to SEG55. 2. Always select "LCD segment output (S)" as the output specification of SEG0 to SEG55, as it is fixed at segment output. 1-8 Seiko Epson Corporation S1C6F016 TECHNICAL MANUAL (Rev. 1.1) 1 OuTline Table 1.3.4 Segment option (standard mask option Type G) Pin name COM0 H L D COM1 H L D COM2 H L D Address (F0xxH) COM3 COM4 H L D H L D SEG0 SEG1 SEG2 SEG3 SEG4 SEG5 SEG6 SEG7 SEG8 SEG9 SEG10 SEG11 SEG12 SEG13 SEG14 SEG15 SEG16 SEG17 SEG18 SEG19 SEG20 SEG21 SEG22 SEG23 SEG24 SEG25 SEG26 SEG27 SEG28 SEG29 SEG30 SEG31 SEG32 SEG33 SEG34 SEG35 SEG36 SEG37 SEG38 SEG39 SEG40 SEG41 SEG42 SEG43 SEG44 SEG45 SEG46 SEG47 SEG48 SEG49 SEG50 SEG51 SEG52 SEG53 SEG54 SEG55 <address> H: RAM data high-order address (0-7) L: RAM data low-order address (0-F) D: Data bit (0-3) H COM5 L D H COM6 L D H COM7 L D Output specification S S S S S S S S S S S S S S S S S S S S S S S S S S S S S S S S S S S S nS nS nS nS nS nS nS nS nS nS nS nS nS nS nS nS nS nS nS nS nC nC nC nC nC nC nC nC nC nC nC nC nC nC nC nC nC nC nC nC nC nC nC nC nC nC nC nC nC nC nC nC nC nC nC nC C C C C C C C C C C C C C C C C C C C C N N N N N N N N N N N N N N N N N N N N N N N N N N N N N N N N N N N N N N N N N N N N N N N N N N N N N N N N <Output specification> S: Segment output C: Complementary output N: Nch open drain output Notes for using the segment option generator "winsog" (standard mask option Type G) 1. Any display memory address can be allocated to SEG0 to SEG35. Leave the address cells for COM1 to COM7 blank, as Type G supports DC output only. 2. Always select "Complementary output (C)" as the output specification of SEG0 to SEG35, as it is fixed at complementary output. 3. Configurations for nonexistent SEG pins (SEG36 to SEG55) * Always select "LCD segment output (S)" as the output specification of SEG36 to SEG55. * Leave the address cells for SEG36 to SEG55 blank. (Unused addresses will be allocated.) S1C6F016 Technical Manual (Rev. 1.1) Seiko Epson Corporation 1-9 1 OuTline Table 1.3.5 Segment option (custom mask option) Pin name COM0 H L D COM1 H L D COM2 H L D Address (F0xxH) COM3 COM4 H L D H L D SEG0 SEG1 SEG2 SEG3 SEG4 SEG5 SEG6 SEG7 SEG8 SEG9 SEG10 SEG11 SEG12 SEG13 SEG14 SEG15 SEG16 SEG17 SEG18 SEG19 SEG20 SEG21 SEG22 SEG23 SEG24 SEG25 SEG26 SEG27 SEG28 SEG29 SEG30 SEG31 SEG32 SEG33 SEG34 SEG35 SEG36 SEG37 SEG38 SEG39 SEG40 SEG41 SEG42 SEG43 SEG44 SEG45 SEG46 SEG47 SEG48 SEG49 SEG50 SEG51 SEG52 SEG53 SEG54 SEG55 <address> H: RAM data high-order address (0-7) L: RAM data low-order address (0-F) D: Data bit (0-3) H COM5 L D H COM6 L D H COM7 L D Output specification nS nS nS nS nS nS nS nS nS nS nS nS nS nS nS nS nS nS nS nS nS nS nS nS nS nS nS nS nS nS nS nS nS nS nS nS nS nS nS nS nS nS nS nS nS nS nS nS nS nS nS nS nS nS nS nS C C C C C C C C C C C C C C C C C C C C C C C C C C C C C C C C C C C C C C C C C C C C C C C C C C C C C C C C N N N N N N N N N N N N N N N N N N N N N N N N N N N N N N N N N N N N N N N N N N N N N N N N N N N N N N N N <Output specification> S: Segment output C: Complementary output N: Nch open drain output Notes for using the segment option generator "winsog" (custom mask option) 1. Any display memory address can be allocated to SEG0 to SEG55. 2. Always select "LCD segment output (S)" as the output specification of SEG0 to SEG55. 1-10 Seiko Epson Corporation S1C6F016 TECHNICAL MANUAL (Rev. 1.1) 2 PinS anD PaCKaGe 2 Pins and Package 2.1 Pin layout Diagram Mask option (SeG55) (SeG54) (SeG53) (SeG52) 76 77 78 79 80 81 82 83 84 85 86 87 88 89 90 91 92 93 94 95 96 97 98 99 100 50 49 48 47 46 45 44 43 42 41 40 39 38 37 36 35 34 33 32 31 30 29 28 27 26 VC1 VC2 VC3 Ca CB N.C. N.C. N.C. COM0 COM1 COM2 COM3 COM4 COM5 COM6 COM7 SeG0 SeG1 SeG2 SeG3 SeG4 SeG5 SeG6 SeG7 SeG8 SeG33 SeG32 SeG31 SeG30 SeG29 SeG28 SeG27 SeG26 SeG25 SeG24 SeG23 SeG22 SeG21 SeG20 SeG19 SeG18 SeG17 SeG16 SeG15 SeG14 SeG13 SeG12 SeG11 SeG10 SeG9 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 huD Sen1 ReF1 RFin1 VSS RFIN0/P53 (SeG51) REF0/P52 (SeG50) SEN0/P51 (SeG49) (SeG48) RFOUT/P50 (SeG47) TOUT_B/P23 (SeG46) EVIN_B/P22 P21 (SeG45) P20 (SeG44) (SeG43) SRDY_SS/P33 SIN/P32 (SeG42) SOUT/P31 (SeG41) SCLK/P30 (SeG40) VDD P43 (SeG39) P42 (SeG38) P41 (SeG37) P40 (SeG36) N.C. SeG35 SeG34 75 74 73 72 71 70 69 68 67 66 65 64 63 62 61 60 59 58 57 56 55 54 53 52 51 P10/KEY10/EVIN_A P11/KEY11/TOUT_A P12/KEY12/BZ P13/KEY13/FOUT P00/KRST00/KEY00/RUN_STP P01/KRST01/KEY01/LAP P02/KRST02/KEY02 P03/KRST03/KEY03 DTXD DRXD DClK DMOD VSS ReSeT TeST TeST3 TeST2 VDD VD1 OSC4 OSC3 VSS OSC2 OSC1 N.C. 2.1.1 QFP15-100pin Figure 2.1.1.1 Pin layout diagram (QFP15-100pin) S1C6F016 Technical Manual (Rev. 1.1) Seiko Epson Corporation 2-1 2 PinS anD PaCKaGe 2.1.2 Chip Diagram of Pad layout 72 70 65 60 55 50 48 73 47 75 45 80 Y 85 (0, 0) X 35 3.775 mm 40 90 30 95 96 26 1 5 10 15 20 25 Die No. 4.037 mm Figure 2.1.2.1 Pad layout diagram Chip thickness: 400 m Pad opening (X x Y): 85 x 87 m (No. 1 to No. 25, No. 48 to No. 72) 87 x 85 m (No. 26 to No. 47, No. 73 to No. 96) 2-2 Seiko Epson Corporation S1C6F016 TECHNICAL MANUAL (Rev. 1.1) 2 PinS anD PaCKaGe Pad Coordinates Table 2.1.2.1 Pad coordinates No. 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 32 33 34 35 36 37 38 39 40 41 42 43 44 45 46 47 - - Pad name SEG33 SEG32 SEG31 SEG30 SEG29 SEG28 SEG27 SEG26 SEG25 SEG24 SEG23 SEG22 SEG21 SEG20 SEG19 SEG18 SEG17 SEG16 SEG15 SEG14 SEG13 SEG12 SEG11 SEG10 SEG9 SEG8 SEG7 SEG6 SEG5 SEG4 SEG3 SEG2 SEG1 SEG0 COM7 COM6 COM5 COM4 COM3 COM2 COM1 COM0 CB CA VC3 VC2 VC1 - - S1C6F016 Technical Manual (Rev. 1.1) X (m) Y (m) -1369.0 -1786.5 -1169.0 -1786.5 -969.0 -1786.5 -869.0 -1786.5 -769.0 -1786.5 -669.0 -1786.5 -569.0 -1786.5 -469.0 -1786.5 -369.0 -1786.5 -269.0 -1786.5 -169.0 -1786.5 -69.0 -1786.5 31.0 -1786.5 131.0 -1786.5 231.0 -1786.5 331.0 -1786.5 431.0 -1786.5 531.0 -1786.5 631.0 -1786.5 731.0 -1786.5 831.0 -1786.5 931.0 -1786.5 1031.0 -1786.5 1231.0 -1786.5 1431.0 -1786.5 1917.5 -1500.0 1917.5 -1300.0 1917.5 -1100.0 1917.5 -1000.0 1917.5 -900.0 1917.5 -800.0 1917.5 -700.0 1917.5 -600.0 1917.5 -500.0 1917.5 -200.0 1917.5 -100.0 1917.5 0.0 1917.5 100.0 1917.5 200.0 1917.5 300.0 1917.5 400.0 1917.5 500.0 1917.5 900.0 1917.5 1000.0 1917.5 1100.0 1917.5 1200.0 1917.5 1300.0 - - - - No. 48 49 50 51 52 53 54 55 56 57 58 59 60 61 62 63 64 65 66 67 68 69 70 71 72 73 74 75 76 77 78 79 80 81 82 83 84 85 86 87 88 89 90 91 92 93 94 95 96 Pad name OSC1 OSC2 VSS OSC3 OSC4 VD1 VDD TEST1 TEST2 TEST3 TEST RESET VSS DMOD DCLK DRXD DTXD P03/KRST03/KEY03 P02/KRST02/KEY02 P01/KRST01/KEY01/LAP P00/KRST00/KEY00/RUN_STP P13/KEY13/FOUT P12/KEY12/BZ P11/KEY11/TOUT_A P10/KEY10/EVIN_A HUD (SEG55) SEN1 (SEG54) REF1 (SEG53) RFIN1 (SEG52) VSS P53/RFIN0 (SEG51) P52/REF0 (SEG50) P51/SEN0 (SEG49) P50/RFOUT (SEG48) P23/TOUT_B (SEG47) P22/EVIN_B (SEG46) P21 (SEG45) P20 (SEG44) P33/SRDY_SS (SEG43) P32/SIN (SEG42) P31/SOUT (SEG41) P30/SCLK (SEG40) VDD P43 (SEG39) P42 (SEG38) P41 (SEG37) P40 (SEG36) SEG35 SEG34 Seiko Epson Corporation X (m) Y (m) 1431.0 1786.5 1331.0 1786.5 1231.0 1786.5 1131.0 1786.5 1031.0 1786.5 931.0 1786.5 731.0 1786.5 631.0 1786.5 531.0 1786.5 431.0 1786.5 231.0 1786.5 131.0 1786.5 31.0 1786.5 -69.0 1786.5 -169.0 1786.5 -269.0 1786.5 -369.0 1786.5 -569.0 1786.5 -669.0 1786.5 -769.0 1786.5 -869.0 1786.5 -1069.0 1786.5 -1169.0 1786.5 -1269.0 1786.5 -1369.0 1786.5 -1917.5 1300.0 -1917.5 1200.0 -1917.5 1100.0 -1917.5 1000.0 -1917.5 900.0 -1917.5 800.0 -1917.5 700.0 -1917.5 600.0 -1917.5 500.0 -1917.5 300.0 -1917.5 200.0 -1917.5 100.0 -1917.5 0.0 -1917.5 -200.0 -1917.5 -300.0 -1917.5 -400.0 -1917.5 -500.0 -1917.5 -600.0 -1917.5 -700.0 -1917.5 -800.0 -1917.5 -900.0 -1917.5 -1000.0 -1917.5 -1200.0 -1917.5 -1400.0 2-3 2 PinS anD PaCKaGe 2.2 Pin Description Figure 2.2.1 Pin description Pin name Shared Default function Pin/pad No. QFP Chip 58, 93 54, 63, 80 57 50-48 47, 46 52 53 55 54, 90 50, 60, 77 53 47-45 44, 43 48 49 51 OSC4 56 52 ReSeT TeST TeST1 TeST2 62 61 - 59 59 58 55 56 60 64 65 66 67 42-35 34-1, 100, 99 76 57 61 62 63 64 42-35 34-1, 96, 95 73 77 VDD VSS VD1 VC1-VC3 Ca, CB OSC1 OSC2 OSC3 TeST3 DMOD DClK DRXD DTXD COM0-COM7 SeG0-SeG35 huD HUD SEG55 Sen1 SEN1 ReF1 RFin1 P53 P52 P51 P50 P00 SEG54 REF1 SEG53 RFIN1 SEG52 P53 RFIN0 SEG51 P52 REF0 SEG50 P51 SEN0 SEG49 P50 RFOUT SEG48 P00 KRST00 KEY00 RUN_STP I/O OP SFT - - - - - I O I I - O O - I I I/o I/o - - - - - - - OP OP OP OP OP OP - - - - - - - - - - - - - - - - - - - - - 74 I/o - I - I - I - O - O - O - O OP O OP O OP - - - - - - - - - - 78 75 O O OP OP - - 79 76 81 78 OP OP OP OP 82 79 O I O I/o I O I/o O 83 80 84 81 71 68 - - - D SFT OP - OP D SFT O OP - I/o OP D O SFT O I/o O O I/o I I I OP OP - D SFT OP - - D OP - - SFT - SFT P01 P01 KRST01 KEY01 LAP 70 67 I/o - D I OP - I - SFT I - SFT P02 P02 KRST02 KEY02 P03 KRST03 KEY03 69 66 68 65 I/o - D I OP - I - SFT I/o - D I OP - I - SFT P03 Function Power (+) supply pins Power (-) supply pins Internal logic voltage regulator output pin LCD system power supply pins LCD system voltage boost/reduce capacitor connecting pins Crystal oscillation input pin Crystal oscillation output pin Ceramic oscillation input pin CR oscillation (external R) input pin CR oscillation (built-in R) input pin (Leave the pin open.) Ceramic oscillation output pin CR oscillation (external R) output pin CR oscillation (built-in R) output pin (Leave the pin open.) Initial reset input pin Test pin (Connect to VSS during normal operation.) Flash EEPROM test pin (Leave the pin open.) Flash EEPROM test pin (Connect to VDD during normal operation.) Flash EEPROM test pin (Leave the pin open.) Flash programming control pin Clock input pin for Flash programming Serial data input pin for Flash programming Serial data output pin for Flash programming LCD common output pins LCD segment output pins R/F converter CR oscillation output pin for AC bias sensor LCD segment output pin R/F converter Ch.1 CR oscillation output pin for DC bias sensor LCD segment output pin R/F converter Ch.1 CR oscillation output pin for reference resistor LCD segment output pin R/F converter Ch.1 CR oscillation input pin LCD segment output pin I/O port pin R/F converter Ch.0 CR oscillation input pin LCD segment output pin I/O port pin R/F converter Ch.0 CR oscillation output pin for reference resistor LCD segment output pin I/O port pin R/F converter Ch.0 CR oscillation output pin for DC bias sensor LCD segment output pin I/O port pin R/F converter CR oscillation clock output pin LCD segment output pin I/O port pin Key reset input pin Port interrupt input pin Stopwatch direct RUN/STOP input pin (Can be switched to LAP input.) I/O port pin Key reset input pin Port interrupt input pin Stopwatch direct LAP input pin (Can be switched to RUN/STOP input.) I/O port pin Key reset input pin Port interrupt input pin I/O port pin Key reset input pin Port interrupt input pin 2-4 Seiko Epson Corporation S1C6F016 TECHNICAL MANUAL (Rev. 1.1) 2 PinS anD PaCKaGe Pin name Shared Default function P10 P10 KEY10 EVIN_A P11 P11 KEY11 TOUT_A P12 P12 KEY12 BZ P13 P13 KEY13 FOUT P20 P20 SEG44 P21 P21 SEG45 P22 P22 EVIN_B SEG46 P23 P23 TOUT_B SEG47 P30 P30 SCLK SEG40 P31 P31 SOUT SEG41 P32 P32 SIN SEG42 P33 P33 SRDY_SS SEG43 P40 P40 SEG36 P41 P41 SEG37 P42 P42 SEG38 P43 P43 SEG39 Pin/pad No. QFP Chip 75 72 74 71 73 70 72 69 88 85 87 84 86 83 85 82 92 89 91 88 90 87 89 86 97 94 96 93 95 92 94 91 I/O OP SFT I/o I I I/o I O I/o I O I/o I O I/o O I/o O I/o I O I/o O O I/o I/o O I/o O O I/o I O I/o i/O O I/o O I/o O I/o O I/o O - - - - - - - - - - - - OP OP OP OP OP OP OP OP OP OP OP OP OP OP OP OP OP OP OP OP OP OP OP OP D SFT SFT D SFT SFT D SFT SFT D SFT SFT - - - - D SFT - D SFT - D SFT - D SFT - D SFT - D SFT - - - - - - - - - Function I/O port pin Port interrupt input pin Event counter (programmable timer 0) input pin I/O port pin Port interrupt input pin Programmable timer 0/1 output pin I/O port pin Port interrupt input pin Sound generator output pin I/O port pin Port interrupt input pin FOUT clock output pin I/O port pin LCD segment output pin I/O port pin LCD segment output pin I/O port pin Event counter (programmable timer 2) input pin LCD segment output pin I/O port pin Programmable timer 2/3 output pin LCD segment output pin I/O port pin Serial I/F clock input/output pin LCD segment output pin I/O port pin Serial I/F data output pin LCD segment output pin I/O port pin Serial I/F data input pin LCD segment output pin I/O port pin Serial I/F ready output/slave-select input pin LCD segment output pin I/O port pin LCD segment output pin I/O port pin LCD segment output pin I/O port pin LCD segment output pin I/O port pin LCD segment output pin I/O: Capital letters (I, O) represent the input/output direction in the initial settings. OP: Selected by mask option ("-" means "no option provided.") SFT: Switched by software ("-" means "no software switch provided" and "D" means default function.) Notes: * The test terminals must be connected to the power supply or left open as shown below. Be sure to avoid applying other conditions to the terminals during normal operation. TEST: Connect to VSS. TEST1: Leave open. TEST2: Connect to VDD. TEST3: Leave open. * Be sure to leave the DMOD, DTXD, DRXD and DCLK terminals open during normal operation. Particularly, make sure that the DMOD terminal is not pulled up to high from outside the IC, although the terminal is pulled down with an internal resistor. S1C6F016 Technical Manual (Rev. 1.1) Seiko Epson Corporation 2-5 2 PinS anD PaCKaGe 2.3 Package 2.3.1 Plastic Package QFP15-100pin (Unit: mm) 160.4 140.1 75 51 76 160.4 140.1 50 INDEX 100 26 1.40.1 0.5 +0.1 25 0.18 -0.05 +0.05 0.125 -0.025 0 10 0.50.2 0.1 1.7max 1 1 2-6 Seiko Epson Corporation S1C6F016 TECHNICAL MANUAL (Rev. 1.1) 2 PinS anD PaCKaGe 2.3.2 Ceramic Package for Test Samples QFP15-100pin (Unit: mm) 17.00 0.30 12.00Typ. 100 76 75 25 51 13.97 0.15 1 26 50 0.50Typ. GLASS S1C6F016 Technical Manual (Rev. 1.1) 0.20 0.38 0.08 0.95 0.08 0.76 0.13 2.54max. 0.50 CERAMIC Seiko Epson Corporation 0.82 0.30 2-7 3 CPu anD MeMORY 3 CPU and Memory 3.1 CPu The S1C6F016 has a 4-bit core CPU S1C63000 built-in as its CPU part. Refer to the "S1C63000 Core CPU Manual" for the S1C63000. 3.2 Code Memory area 3.2.1 Code ROM The built-in code ROM is a Flash EEPROM for loading programs, and has a capacity of 16,384 words x 13 bits. The core CPU can linearly access the program space up to step FFFFH from step 0000H, however, the program area of the S1C6F016 is step 0000H to step 3FFFH. The program start address after initial reset is assigned to step 0110H. The non-maskable interrupt (NMI) vector and hardware interrupt vectors are allocated to step 0100H and steps 0101H-010FH, respectively. 0000H 0000H S1C6F016 program area Code ROM (Flash) 0100H 0101H 3FFFH 4000H NMI vector Hardware interrupt vectors 0110H Program start address S1C63000 core CPU program space FFFFH Program area Program area Unused area 0100H 0101H 0102H 0103H 0104H 0105H 0106H 0107H 0108H 0109H 010AH 010BH 010CH 13 bits Watchdog timer (NMI) R/F converter Programmable timer 0 Programmable timer 1 Programmable timer 2 Programmable timer 3 - - - - Serial interface Key input interrupt (P0) Key input interrupt (P1) Stopwatch timer 010DH 010EH Clock timer (128/64/32/16 Hz) Clock timer (8/4/2/1 Hz) 010FH Figure 3.2.1.1 Configuration of code ROM 3.2.2 Flash eePROM Specifications The S1C6F016 code ROM is a built-in Flash EEPROM and it can be programmed (erase/program/verify) on the target board with the S1C6F016 mounted. Use the On Board Writer (product name: S5U1C88000W3/S5U1C88000W4) for Flash EEPROM programming. Table 3.2.2.1 shows the Flash EEPROM specifications. Table 3.2.2.1 Flash EEPROM specifications Programming count 1000 times (Min.) *1 Data bit status after erasing 1 Program voltage range VDD = 2.7 to 3.6 V (VD1 = 2.5 V) Security function Programming/erasing protection, On Board Writer read protection *2 1 The programming count assumes that "erasing + programming" or "programming only" is one count and the programmed data is guaranteed to be retained for 10 years. 2 This protection can be set by the On Board Writer only. Refer to the Electrical Characteristics section for other Flash EEPROM characteristics and Appendix (Flash EEPROM Programming) for programming with the On Board Writer. This product uses SuperFlash(R) technology licensed from Silicon Storage Technology, Inc. Notes: * Be sure to leave the DMOD, DTXD, DRXD and DCLK terminals open during normal operation. Particularly, make sure that the DMOD terminal is not pulled up to high from outside the IC, although the terminal is pulled down with an internal resistor. * The OSC1 oscillation circuit must be configured to enable oscillation when programming the Flash EEPROM using the On Board Writer. S1C6F016 Technical Manual (Rev. 1.1) Seiko Epson Corporation 3-1 3 CPu anD MeMORY 3.3 Data Memory area The S1C6F016 data memory consists of 2,048-word RAM, 4,096-word Flash EEPROM, 448-bit display memory and 132-word peripheral I/O memory. Figure 3.3.1 shows the overall memory map of the S1C6F016. 0000H RAM area 0800H F000H Unused area 8000H Data ROM area (Flash) Display memory area F07FH 9000H Unused area Unused area F000H Display memory area FF00H FFFFH FF00H Peripheral I/O area Unused area I/O memory area FFFFH Figure 3.3.1 Memory map Note: Memory is not implemented in unused areas within the memory map. Further, some non-implementation areas and unused (access prohibition) areas exist in the peripheral I/O area. If the program that accesses these areas is generated, its operation cannot be guaranteed. Refer to the I/O memory maps in Appendix for the peripheral I/O area. 3.3.1 RaM The RAM is a data memory for storing various kinds of data, and has a capacity of 2,048 words x 4 bits. The RAM area is assigned to addresses 0000H to 07FFH on the data memory map. Addresses 0100H to 01FFH are 4-bit/16-bit data accessible areas and in other areas it is only possible to access 4-bit data. When programming, keep the following points in mind. (1) Part of the RAM area is used as a stack area for subroutine call and register evacuation, so pay attention not to overlap the data area and stack area. (2) The S1C63000 core CPU handles the stack using the stack pointer for 4-bit data (SP2) and the stack pointer for 16-bit data (SP1). 16-bit data are accessed in stack handling by SP1, therefore, this stack area should be allocated to the area where 4-bit/16-bit access is possible (0100H to 01FFH). The stack pointers SP1 and SP2 change cyclically within their respective range: the range of SP1 is 0000H to 1FFFH and the range of SP2 is 0000H to 00FFH. Therefore, pay attention to the SP1 value because it may be set to 0200H or more exceeding the 4-bit/16-bit accessible range in the S1C6F016 or it may be set to 00FFH or less. Memory accesses except for stack operations by SP1 are 4-bit data access. After initial reset, all the interrupts including NMI are masked until both the stack pointers SP1 and SP2 are set by software. Further, if either SP1 or SP2 is re-set when both are set already, the interrupts including NMI are masked again until the other is re-set. Therefore, the settings of SP1 and SP2 must be done as a pair. (3) Subroutine calls use 4 words (for PC evacuation) in the stack area for 16-bit data (SP1). Interrupts use 4 words (for PC evacuation) in the stack area for 16-bit data (SP1) and 1 word (for F register evacuation) in the stack area for 4-bit data. 3-2 Seiko Epson Corporation S1C6F016 TECHNICAL MANUAL (Rev. 1.1) 3 CPu anD MeMORY 0000H 4-bit access area (SP2 stack area) 00FFH 0100H 4/16-bit access area (SP1 stack area) 01FFH 0200H 4-bit access area (Data area) 07FFH 4 bits Figure 3.3.1.1 RAM configuration 3.3.2 Data ROM The data ROM is a Flash EEPROM for loading various static data such as a character generator, and has a capacity of 4,096 words x 4 bits. The data ROM is assigned to addresses 8000H to 8FFFH on the data memory map, and the data can be read using the same data memory access instructions as the RAM. 3.3.3 Display Memory The display memory is a RAM used for storing LCD display data and is allocated between F000H and F07FH in the data memory area. Each bit can be assigned to the specific segment terminal (SEG0-SEG55) by programming the Flash EEPROM with the segment assignment data created using the segment option generator "winsog." The addresses that are not used for LCD display can be used as general purpose registers. 3.3.4 i/O Memory The peripheral circuits of S1C6F016 (timer, I/O, etc.) are interfaced with the CPU in the memory mapped I/O method. Thus, all the peripheral circuits can be controlled by accessing the I/O memory on the memory map using the memory operation instructions. The control registers for the peripheral circuits are located in the I/O memory area as shown in the figure below. Refer to Appendix for the register list and descriptions of each peripheral circuit for details of the registers. FF00H FF01H FF03H FF04H-FF05H FF10H-FF1BH FF20H-FF3FH FF40H-FF42H FF44H-FF47H FF48H-FF4DH FF50H-FF52H FF58H-FF5CH FF60H-FF6BH FF70H-FF76H FF80H-FF9FH FFE1H-FFFFH Oscillation circuit Watchdog timer Power supply circuit SVD circuit Clock manager I/O ports and input interrupt control Clock timer Sound generator Stopwatch timer LCD driver Serial interface R/F converter Integer multiplier Programmable timer Interrupt controller Figure 3.3.4.1 I/O memory map S1C6F016 Technical Manual (Rev. 1.1) Seiko Epson Corporation 3-3 4 iniTial ReSeT 4 Initial Reset 4.1 initial Reset Circuit The S1C6F016 should be reset to initialize the internal circuits. There are two ways of doing this. (1) External initial reset by the RESET terminal (2) External initial reset by simultaneous high input to P00-P03 ports (mask option) The circuits are initialized by either (1) or (2). When the power is turned on, be sure to initialize using the reset function. It is not guaranteed that the circuits are initialized by only turning the power on. Figure 4.1.1 shows the configuration of the initial reset circuit. OSC1 OSC2 OSC1 oscillation circuit Divider 1 kHz 16 Hz 1 Hz Mask option P00 P01 Mask option Time authorize circuit P02 Noise reject circuit P03 R Internal initial reset Q S RESET VSS Figure 4.1.1 Configuration of initial reset circuit 4.2 Reset Terminal (ReSeT) Initial reset can be executed externally by setting the reset terminal to a high level (VDD). After that the initial reset is released by setting the reset terminal to a low level (VSS) and the CPU starts operating. The reset input signal is maintained by the RS latch and becomes the internal initial reset signal. The RS latch is designed to be released by a 16 Hz signal (high) that is divided by the OSC1 clock. Therefore in normal operation, a maximum of 1,024/fOSC1 seconds (32 msec when fOSC1 = 32.768 kHz) is needed until the internal initial reset is released after the reset terminal goes to low level. After the internal initial reset is released, the hardware executes an initial processing that takes 21,515/ fOSC1 seconds (657 msec when fOSC1 = 32.768 kHz) before the CPU starts operating. Be sure to maintain a reset input of 0.1 msec or more. However, when turning the power on, the reset terminal should be set at a high level as in the timing shown in Figure 4.2.1. Note that a reset pulse shorter than 100 nsec is rejected as noise. VDD 1.3 V 0.9*VDD or more (high level) 0.5*VDD RESET Power on 2.0 msec or more Figure 4.2.1 Initial reset at power on The reset terminal should be set to 0.9*VDD or more (high level) until the supply voltage becomes 1.3 V or more. After that, a level of 0.5*VDD or more should be maintained more than 2.0 msec. The reset terminal incorporates a pull-down resistor and a mask option is provided to select whether the resistor is used or not. S1C6F016 Technical Manual (Rev. 1.1) Seiko Epson Corporation 4-1 4 iniTial ReSeT 4.3 Simultaneous high input to P0x Ports (P00-P03) Another way of executing initial reset externally is to input high level signals simultaneously to the P0x ports (P00- P03) selected by a mask option. Since this initial reset passes through the noise reject circuit, maintain the specified input port terminals at high level for at least 1.5 msec (when the oscillation frequency fOSC1 is 32.768 kHz) during normal operation. The noise reject circuit does not operate immediately after turning the power on until the oscillation circuit starts oscillating. Therefore, maintain the specified input port terminals at high level for at least 1.5 msec (when the oscillation frequency fOSC1 is 32.768 kHz) after oscillation starts. Table 4.3.1 shows the combinations of P0x ports (P00-P03) that can be selected by a mask option. Table 4.3.1 Combinations of P0x ports No. Combination 1 Not used 2 P00 * P01 3 P00 * P01 * P02 4 P00 * P01 * P02 * P03 When, for instance, mask option 4 (P00 P01 P02 P03) is selected, initial reset is executed when the signals input to the four ports P00-P03 are all high at the same time. When 2 or 3 is selected, the initial reset is done when a key entry including a combination of selected input ports is made. Further, the time authorize circuit mask option is selected when this reset function is selected. The time authorize circuit checks the input time of the simultaneous high input and performs initial reset if that time is the defined time (1 to 2 sec) or more. If using this function, make sure that the specified ports do not go high at the same time during ordinary operation. 4.4 internal Register at initial Resetting Initial reset initializes the CPU as shown in Table 4.4.1. The registers and flags which are not initialized by initial reset should be initialized in the program if necessary. In particular, the stack pointers SP1 and SP2 must be set as a pair because all the interrupts including NMI are masked after initial reset until both the SP1 and SP2 stack pointers are set with software. When data is written to the EXT register, the E flag is set and the following instruction will be executed in the extended addressing mode. If an instruction which does not permit extended operation is used as the following instruction, the operation is not guaranteed. Therefore, do not write data to the EXT register for initialization only. Refer to the "S1C63000 Core CPU Manual" for extended addressing and usable instructions. Table 4.4.1 Initial values CPU core Peripheral circuit Name Symbol Bit length Set value Name Bit length Set value Data register A A 4 Undefined RAM 4 Undefined Data register B B 4 Undefined Display memory 4 Undefined Extension register EXT EXT 8 Undefined Other peripheral circuits - * Index register X X 16 Undefined * See "I/O Memory Map." Index register Y Y 16 Undefined Program counter PC 16 0110H Stack pointer SP1 SP1 8 Undefined Stack pointer SP2 SP2 8 Undefined Zero flag Z 1 Undefined Carry flag C 1 Undefined Interrupt flag I 1 0 Extension flag E 1 0 Queue register Q 16 Undefined 4-2 Seiko Epson Corporation S1C6F016 TECHNICAL MANUAL (Rev. 1.1) 4 iniTial ReSeT 4.5 Terminal Settings at initial Resetting The I/O port (P) terminals are shared with special output terminals and input/output terminals of the serial interface, R/F converter, stopwatch timer and programmable timer (event counter). These functions are selected by software. At initial reset, these terminals are configured to the general purpose I/O port terminals. Set them according to the system in the initial routine. Table 4.5.1 shows the list of the shared terminal settings. Table 4.5.1 List of shared terminal settings Terminal name Terminal status at initial reset P00 P01 P02 P03 P10 P11 P12 P13 P20-P21 P22 P23 P30 P31 P32 P33 P40-P43 P50 P51 P52 P53 P00 (IN & PD*) P01 (IN & PD*) P02 (IN & PD*) P03 (IN & PD*) P10 (IN & PD*) P11 (IN & PD*) P12 (IN & PD*) P13 (IN & PD*) P20-P21 (IN & PD*) P22 (IN & PD*) P23 (IN & PD*) P30 (IN & PD*) P31 (IN & PD*) P32 (IN & PD*) P33 (IN & PD*) P40-P43 (IN & PD*) P50 (IN & PD*) P51 (IN & PD*) P52 (IN & PD*) P53 (IN & PD*) When special outputs/peripheral functions are used (selected by software) Special output Serial I/F Stopwatch R/F direct TOUT FOUT BZ Master Slave converter input RUN/STOP LAP Event counter EVIN_A TOUT_A BZ FOUT EVIN_B TOUT_B SCLK(O) SOUT(O) SIN(I) SCLK(I) SOUT(O) SIN(I) SRDY(O)/SS(I) RFOUT SEN0 REF0 RFIN0 * IN & PD (Input with pulled down): When "Pull-Down Used" is selected by mask option (high impedance when "PullDown Not Used" is selected) For setting procedure of the functions, see explanations for each of the peripheral circuits. S1C6F016 Technical Manual (Rev. 1.1) Seiko Epson Corporation 4-3 5 POWeR SuPPlY 5 Power Supply 5.1 Operating Voltage The S1C6F016 operating power voltage (VDD) is as follows: Normal operation mode: 1.8 V to 3.6 V Flash programming mode: 2.7 V to 3.6 V Supply a voltage within this range to between VDD (+) and VSS (GND). 5.2 internal Power Supply Circuit The S1C6F016 incorporates the power supply circuits shown in Figure 5.2.1 so the voltages to drive the CPU, internal logic circuits, oscillation circuits and LCD driver can be generated on the chip. External power supply VDD VD1 Oscillation circuit Internal operating VD1 voltage regulator OSC1, OSC2 OSC3, OSC4 CPU, Internal circuits VDHLMOD VC1 VC1 VC2 VC2 VC3 CA LCD system voltage regulator CB LCD driver VC3 COM0-COM7 SEG0-SEG55 LPWR VCREF VCHLMOD VSS Figure 5.2.1 Built-in power supply circuit The power supply circuit is broadly divided into two blocks. Table 5.2.1 Power supply circuit Circuit Power supply circuit CPU, oscillation and internal circuits Internal operating voltage regulator LCD driver LCD system voltage regulator Output voltage VD1 VC1-VC3 internal operating voltage regulator This voltage regulator always operates to generate the VD1 operating voltage for the CPU, internal logic circuits and oscillation circuits. lCD system voltage regulator The LCD system voltage regulator generates the LCD drive voltages VC1 to VC3. See "Electrical Characteristics" for the voltage values. In the S1C6F016, the LCD drive voltage is supplied to the built-in LCD driver that drives the LCD panel connected to the SEG and COM terminals. The LCD system voltage regulator can be disabled by mask option to supply external voltages. In this case, external elements can be minimized because the external capacitors for the LCD system voltage regulator are not necessary. However when the LCD system voltage regulator is not used, the display quality of the LCD panel, when the supply voltage fluctuates (drops), is inferior to when the LCD system voltage regulator is used. Figure 5.2.2 shows the external element configuration when an external LCD power supply is used. S1C6F016 Technical Manual (Rev. 1.1) Seiko Epson Corporation 5-1 5 POWeR SuPPlY 4.5 V LCD panel, 1/3 bias 3 V LCD panel, 1/3 bias 3 V LCD panel, 1/2 bias VDD VC1 VC2 VC3 CA CB VSS VDD VC1 VC2 VC3 CA CB VSS VDD VC1 VC2 VC3 CA CB VSS C2 C3 C1 3.0 V C2 C3 C1 3.0 V C2 C1 3.0 V Figure 5.2.2 External elements when an external LCD power supply is used Note: Do not use the VD1 and VC1 to VC3 terminal output voltages to drive external circuits. 5.3 Controlling lCD Power Supply The LCD system voltage regulator generates the reference voltage VC1 or VC2 and generates two other voltages (VC2 = VC1 x 2, VC3 = VC1 x 3, or VC1 = VC2 x 1/2, VC3 = VC2 x 3/2) by boosting or reducing VC1/VC2. Use the VCREF register to select the reference voltage from VC1 and VC2 with consideration given to the supply voltage VDD and contrast of display. Also refer to the LCD drive voltage - supply voltage characteristics (in the "Electrical Characteristics - Characteristics Curves" section and select the appropriate reference voltage according to the system. To generate the LCD drive voltages by the LCD system voltage regulator (to start LCD display), turn the LCD system voltage regulator on using the LPWR register. When "1" is written to LPWR, the LCD system voltage regulator goes on and generates the LCD drive voltages. At initial reset, LPWR is set to "0" (Off). When LCD display is not needed, turn the LCD system voltage regulator off to reduce power consumption. Note: The LCD system voltage regulator takes about 100 msec for stabilizing the LCD drive voltages after writing "1" to LPWR. Furthermore, the LCD system voltage regulator uses the boost clock supplied from the clock manager for boosting/ reducing the voltage. The clock supply is controlled by the VCCKS[1:0] register. Set VCCKS[1:0] to "1" before writing "1" to LPWR. When LCD display is not necessary, stop the clock supply by setting VCCKS[1:0] to "0" to reduce power consumption. Table 5.3.1 Controlling boost clock VCCKS[1:0] Boost clock control 3 or 2 Prohibited 1 ON (2 kHz) 0 Off 5.4 heavy load Protection Function In order to ensure a stable circuit behavior and LCD display quality even if the power supply voltage fluctuates due to driving an external load, the internal operating voltage regulator and the LCD system voltage regulator have a heavy load protection function. The internal operating voltage regulator enters heavy load protection mode by writing "1" to the VDHLMOD register and it ensures stable VD1 output. Use the heavy load protection function when a heavy load such as a lamp or buzzer is driven with a port output. The LCD system voltage regulator enters heavy load protection mode by writing "1" to the VCHLMOD register and it ensures stable VC1-VC3 outputs. Use the heavy load protection function when the LCD display has inconsistencies in density. Note: Current consumption increases in heavy load protection mode, therefore do not set heavy load protection mode with software if unnecessary. 5-2 Seiko Epson Corporation S1C6F016 TECHNICAL MANUAL (Rev. 1.1) 5 POWeR SuPPlY 5.5 i/O Memory for Power Supply Circuit Table 5.5.1 shows the I/O address and the control bits for power supply control. Table 5.5.1 Power supply control bits Address Register name R/W Default Setting/data Function FF03H D3 D2 D1 D0 VChlMOD VDhlMOD VCReF lPWR R/W R/W R/W R/W 0 0 0 0 1 1 1 1 On On VC2 On 0 0 0 0 Off Off VC1 Off VC regulator heavy load protection mode On/Off VD regulator heavy load protection mode On/Off VC regulator reference voltage selection VC regulator On/Off FF12H D3 D2 D1 D0 FLCKS1 FLCKS0 VCCKS1 VCCKS0 R/W R/W R/W R/W 0 0 0 0 3 2 3 2 - 16.0 - - 1 0 1 0 21.3 32.0 2048 Off Frame frequency (Hz) selection *1 Initial value at initial reset *2 Not set in the circuit VC boost frequency (Hz) selection *3 Constantly "0" when being read lPWR: VC regulator On/Off register (FF03h*D0) Turns the LCD system voltage regulator on and off. When "1" is written: On When "0" is written: Off Reading: Valid When "1" is written to LPWR, the LCD system voltage regulator goes on and generates the LCD drive voltages. When "0" is written, all the LCD drive voltages go to VSS level. It takes about 100 msec for the LCD drive voltages to stabilize after starting up the LCD system voltage regulator by writing "1" to LPWR. At initial reset, this register is set to "0." VCReF: VC regulator reference voltage select register (FF03h*D1) Selects the reference voltage generated in the LCD system voltage regulator. When "1" is written: VC2 When "0" is written: VC1 Reading: Valid When "1" is written to VCREF, the LCD system voltage regulator generates the reference voltage VC2 and generates two other voltages (VC1 = VC2 x 1/2, VC3 = VC2 x 3/2) by boosting and reducing VC2. When VCREF is "0," the LCD system voltage regulator generates the reference voltage VC1 and generates two other voltages (VC2 = VC1 x 2, VC3 = VC1 x 3) by boosting VC1. The reference voltage should be selected from VC1 and VC2 with consideration given to the supply voltage VDD and contrast of display. Also refer to the LCD drive voltage - supply voltage characteristics (in the "Electrical Characteristics - Characteristics Curves" section and select the appropriate reference voltage according to the system. At initial reset, this register is set to "0." VDhlMOD: VD regulator heavy load protection mode On/Off register (FF03h*D2) Enables heavy load protection function for the internal operating voltage regulator. When "1" is written: On When "0" is written: Off Reading: Valid By writing "1" to VDHLMOD, the internal operating voltage regulator enters heavy load protection mode and it ensures stable VD1 output. The heavy load protection function is effective when the buzzer/FOUT signal is being output. However, heavy load protection mode increases current consumption compared with normal operation mode. Therefore, do not set heavy load protection mode unless it is necessary. At initial reset, this register is set to "0." VChlMOD: VC regulator heavy load protection mode On/Off register (FF03h*D3) Enables heavy load protection function for the LCD system voltage regulator. When "1" is written: On When "0" is written: Off Reading: Valid S1C6F016 Technical Manual (Rev. 1.1) Seiko Epson Corporation 5-3 5 POWeR SuPPlY By writing "1" to VCHLMOD, the LCD system voltage regulator enters heavy load protection mode to minimize degradation in display quality when fluctuations in the supply voltage occurs due to driving a heavy load. The heavy load protection function is effective when the OSC3 clock is used or the buzzer/FOUT signal is being output. However, heavy load protection mode increases current consumption compared with normal operation mode. Therefore, do not set heavy load protection mode unless it is necessary. At initial reset, this register is set to "0." VCCKS[1:0]: VC boost frequency select register (FF12h*D[1:0]) Controls the boost clock supply to the LCD system voltage regulator. Table 5.5.2 Controlling boost clock VCCKS[1:0] Boost clock control 3 or 2 Prohibited 1 ON (2 kHz) 0 Off The LCD system voltage regulator uses the boost clock supplied from the clock manager for boosting/reducing the voltage. Use this register to control the clock supply. Set VCCKS[1:0] to "1" before writing "1" to LPWR. When LCD display is not necessary, stop the clock supply by setting VCCKS[1:0] to "0" to reduce power consumption. At initial reset, this register is set to "0." 5.6 Precautions * Do not use the VD1 and VC1 to VC3 terminal output voltages to drive external circuits. * The LCD system voltage regulator takes about 100 msec for stabilizing the LCD drive voltages after writing "1" to LPWR. * Current consumption increases in heavy load protection mode, therefore do not set heavy load protection mode with software if unnecessary. 5-4 Seiko Epson Corporation S1C6F016 TECHNICAL MANUAL (Rev. 1.1) 6 inTeRRuPT COnTROlleR 6 Interrupt Controller 6.1 Configuration of interrupt Controller The S1C6F016 supports the following seven types of interrupts. External interrupt: * Key input interrupt (8 systems) Internal interrupt: * Watchdog timer interrupt * Programmable timer interrupt * Serial interface interrupt * Clock timer interrupt * Stopwatch timer interrupt * R/F converter interrupt (NMI, 1 system) (8 systems) (1 system) (8 systems) (4 systems) (3 systems) To enable an interrupt, the interrupt flag must be set to "1" (EI) and the corresponding interrupt mask register must be set to "1" (enable). When an interrupt occurs, the interrupt flag is automatically reset to "0" (DI), and interrupts after that are disabled. The watchdog timer interrupt is an NMI (non-maskable interrupt), therefore, the interrupt is generated regardless of the interrupt flag setting. Also the interrupt mask register is not provided. However, it is possible to disable NMI since software can stop the watchdog timer operation. Figure 6.1.1 shows the configuration of the interrupt circuit. Note: After an initial reset, all the interrupts including NMI are masked until both the stack pointers SP1 and SP2 are set with the software. Be sure to set the SP1 and SP2 in the initialize routine. Further, when re-setting the stack pointer, the SP1 and SP2 must be set as a pair. When one of them is set, all the interrupts including NMI are masked and interrupts cannot be accepted until the other one is set. S1C6F016 Technical Manual (Rev. 1.1) Seiko Epson Corporation 6-1 6 inTeRRuPT COnTROlleR IRFE EIRFEIRF Watchdog timer NMI request IRFR EIRFR IRFS EIRFS IPT0 EIPT0 ICTC0 EICTC0 IPT1 EIPT1 Interrupt vector generation circuit ICTC1 EICTC1 IPT2 EIPT2 Program counter (low-order 4 bits) ICTC2 EICTC2 IPT3 EIPT3 ICTC3 EICTC3 ISIF EISIF INT Interrupt request P03 PCP03 SIP03 IK03 EIK03 P02 PCP02 SIP02 IK02 EIK02 P01 PCP01 SIP01 Interrupt flag IK01 EIK01 P00 PCP00 SIP00 IK00 EIK00 SLEEP cancellation P13 PCP13 SIP13 IK13 EIK13 Interrupt factor flag P12 PCP12 SIP12 IK12 EIK12 Interrupt mask register IK11 EIK11 Interrupt select register P11 PCP11 SIP11 Interrupt polarity select register P10 PCP10 SIP10 IK10 EIK10 IRUN EIRUN ILAP EILAP ISW10 EISW10 ISW1 EISW1 IT3 EIT3 IT2 EIT2 IT1 EIT1 IT0 EIT0 IT7 EIT7 IT6 EIT6 IT5 EIT5 IT4 EIT4 Figure 6.1.1 Configuration of the interrupt circuit 6-2 Seiko Epson Corporation S1C6F016 TECHNICAL MANUAL (Rev. 1.1) 6 inTeRRuPT COnTROlleR 6.2 interrupt Factors Table 6.2.1 shows the factors for generating interrupt requests. The interrupt flags are set to "1" depending on the corresponding interrupt factors. The CPU operation is interrupted when an interrupt factor flag is set to "1" if the following conditions are established. * The corresponding mask register is "1" (enabled) * The interrupt flag is "1" (EI) The interrupt factor flag is reset to "0" when "1" is written. At initial reset, the interrupt factor flags are reset to "0." Since the watchdog timer's interrupt is NMI, the interrupt is generated regardless of the setting above, and no interrupt factor flag is provided. Table 6.2.1 Interrupt factors Interrupt factor Interrupt factor flag R/F converter (error) IRFE (FFF1H*D2) R/F converter (end of reference conversion) IRFR (FFF1H*D1) R/F converter (end of sensor conversion) IRFS (FFF1H*D0) Programmable timer 0 (underflow) IPT0 (FFF2H*D1) Programmable timer 0 (compare match) ICTC0 (FFF2H*D0) Programmable timer 1 (underflow) IPT1 (FFF3H*D1) Programmable timer 1 (compare match) ICTC1 (FFF3H*D0) Programmable timer 2 (underflow) IPT2 (FFF4H*D1) Programmable timer 2 (compare match) ICTC2 (FFF4H*D0) Programmable timer 3 (underflow) IPT3 (FFF5H*D1) Programmable timer 3 (compare match) ICTC3 (FFF5H*D0) Serial interface (8-bit data input/output completion) ISIF (FFFAH*D0) Key input interrupt <P03> IK03 (FFFBH*D3) Key input interrupt <P02> IK02 (FFFBH*D2) Key input interrupt <P01> IK01 (FFFBH*D1) Key input interrupt <P00> IK00 (FFFBH*D0) Key input interrupt <P13> IK13 (FFFCH*D3) Key input interrupt <P12> IK12 (FFFCH*D2) Key input interrupt <P11> IK11 (FFFCH*D1) Key input interrupt <P10> IK10 (FFFCH*D0) Stopwatch timer (Direct RUN) IRUN (FFFDH*D3) Stopwatch timer (Direct LAP) ILAP (FFFDH*D2) Stopwatch timer (1 Hz) ISW1 (FFFDH*D1) Stopwatch timer (10 Hz) ISW10 (FFFDH*D0) Clock timer 16 Hz (falling edge) IT3 (FFFEH*D3) Clock timer 32 Hz (falling edge) IT2 (FFFEH*D2) Clock timer 64 Hz (falling edge) IT1 (FFFEH*D1) Clock timer 128 Hz (falling edge) IT0 (FFFEH*D0) Clock timer 1 Hz (falling edge) IT7 (FFFFH*D3) Clock timer 2 Hz (falling edge) IT6 (FFFFH*D2) Clock timer 4 Hz (falling edge) IT5 (FFFFH*D1) Clock timer 8 Hz (falling edge) IT4 (FFFFH*D0) Interrupt mask register EIRFE (FFE1H*D2) EIRFR (FFE1H*D1) EIRFS (FFE1H*D0) EIPT0 (FFE2H*D1) EICTC0 (FFE2H*D0) EIPT1 (FFE3H*D1) EICTC1 (FFE3H*D0) EIPT2 (FFE4H*D1) EICTC2 (FFE4H*D0) EIPT3 (FFE5H*D1) EICTC3 (FFE5H*D0) EISEIF (FFEAH*D0) EIK03 (FFEBH*D3) EIK02 (FFEBH*D2) EIK01 (FFEBH*D1) EIK00 (FFEBH*D0) EIK13 (FFECH*D3) EIK12 (FFECH*D2) EIK11 (FFECH*D1) EIK10 (FFECH*D0) EIRUN (FFEDH*D3) EILAP (FFEDH*D2) EISW1 (FFEDH*D1) EISW10 (FFEDH*D0) EIT3 (FFEEH*D3) EIT2 (FFEEH*D2) EIT1 (FFEEH*D1) EIT0 (FFEEH*D0) EIT7 (FFEFH*D3) EIT6 (FFEFH*D2) EIT5 (FFEFH*D1) EIT4 (FFEFH*D0) Note: After an interrupt occurs, the same interrupt will occur again if the interrupt enabled state (I flag = "1") is set or the RETI instruction is executed unless the interrupt factor flag is reset. Therefore, be sure to reset (write "1" to) the interrupt factor flag in the interrupt handler routine before shifting to the interrupt enabled state. 6.3 interrupt Mask The interrupt factor flags can be masked by the corresponding interrupt mask registers. The interrupt mask registers are read/write registers. They are enabled (interrupt authorized) when "1" is written to them, and masked (interrupt inhibited) when "0" is written to them. At initial reset, the interrupt mask register is reset to "0." Table 6.2.1 shows the correspondence between interrupt mask registers and interrupt factor flags. S1C6F016 Technical Manual (Rev. 1.1) Seiko Epson Corporation 6-3 6 inTeRRuPT COnTROlleR 6.4 interrupt Vector When an interrupt request is input to the CPU, the CPU begins interrupt processing. After the program being executed is terminated, the interrupt processing is executed in the following order. 1. The content of the flag register is evacuated, then the I flag is reset. 2. The address data (value of program counter) of the program to be executed next is saved in the stack area (RAM). 3. The interrupt request causes the value of the interrupt vector (0100H-010FH) to be set in the program counter. 4. The program at the specified address is executed (execution of interrupt handler routine by software). Table 6.4.1 shows the correspondence of interrupt requests and interrupt vectors. Table 6.4.1 Interrupt request and interrupt vectors Interrupt vector Interrupt factor 0100H Watchdog timer 0101H R/F converter 0102H Programmable timer 0 0103H Programmable timer 1 0104H Programmable timer 2 0105H Programmable timer 3 0106H Reserved 0107H Reserved 0108H Reserved 0109H Reserved 010AH Serial interface 010BH Key input interrupt <P0> 010CH Key input interrupt <P1> 010DH Stopwatch timer 010EH Clock timer (128 Hz, 64 Hz, 32 Hz, 16 Hz) 010FH Clock timer (8 Hz, 4 Hz, 2 Hz, 1 Hz) Priority High Low The four low-order bits of the program counter are indirectly addressed through the interrupt request. Note: The interrupt handler routine must be located within the range from "Interrupt vector address (100H-10FH)" -7FH to +80H. If it is difficult, make a relay point within that range as the destination of the vector jump and branch the program to the interrupt handler from there. Example: ;****************************************************************************** ;** interrupt vector area ** ;****************************************************************************** .org 0x0100 JR INT_DUMMY ;WATCH DOG TIMER INTERRUPT VECTOR(0x100) JR INT_RFC ;RFC INTERRUPT VECTOR(0x101) JR INT_DUMMY ;PTIMER0 INTERRUPT VECTOR(0x102) JR INT_DUMMY ;PTIMER1 INTERRUPT VECTOR(0x103) JR INT_DUMMY ;PTIMER2 INTERRUPT VECTOR(0x104) JR INT_DUMMY ;PTIMER3 INTERRUPT VECTOR(0x105) JR INT_DUMMY ;Reserved JR INT_DUMMY ;Reserved JR INT_DUMMY ;Reserved JR INT_DUMMY ;Reserved JR INT_DUMMY ;SIO INTERRUPT VECTOR(0x10A) JR INT_DUMMY ;P0x PORT INTERRUPT VECTOR(0x10B) JR INT_DUMMY ;P1x PORT INTERRUPT VECTOR(0x10C) JR INT_DUMMY ;STOPWATCH INTERRUPT VECTOR(0x10D) JR INT_DUMMY ;CLOCK TIMER1 INTERRUPT VECTOR(0x10E) JR INT_DUMMY ;CLOCK TIMER2 INTERRUPT VECTOR(0x10F) ;****************************************************************************** ;** subinterrupt vector area ** ;****************************************************************************** .org 0x120 INT_RFC: CALR INTRFC ;call Interrupt RFC RETI 6-4 Seiko Epson Corporation S1C6F016 TECHNICAL MANUAL (Rev. 1.1) 6 inTeRRuPT COnTROlleR INT_DUMMY: RETI ;****************************************************************************** ;** Interrupt RFC ** ;****************************************************************************** .org 0x800 INTRFC: LDB %yl,P5CTL0@l LDB %xl,ITC_RFC1@l LD [%y],[%x] ;Port Output RET 6.5 i/O Memory of interrupt Controller Table 6.5.1 shows the I/O addresses and the control bits for controlling interrupts. Table 6.5.1 Control bits of interrupt controller Address Register name R/W Default Setting/data Function - 0 Mask 0 Mask 0 Mask Unused Interrupt mask register (RFC error) Interrupt mask register (RFC REF completion) Interrupt mask register (RFC SEN completion) 0 Mask 0 Mask Unused Unused Interrupt mask register (PT0 underflow) Interrupt mask register (PT0 compare match) 0 Mask 0 Mask Unused Unused Interrupt mask register (PT1 underflow) Interrupt mask register (PT1 compare match) 0 Mask 0 Mask Unused Unused Interrupt mask register (PT2 underflow) Interrupt mask register (PT2 compare match) 0 Mask 0 Mask Unused Unused Interrupt mask register (PT3 underflow) Interrupt mask register (PT3 compare match) 1 Enable 0 Mask Unused Unused Unused Interrupt mask register (Serial I/F) 1 1 1 1 Enable Enable Enable Enable 0 0 0 0 Mask Mask Mask Mask Interrupt mask register (KEY03<P03>) Interrupt mask register (KEY02<P02>) Interrupt mask register (KEY01<P01>) Interrupt mask register (KEY00<P00>) 0 0 0 0 1 1 1 1 Enable Enable Enable Enable 0 0 0 0 Mask Mask Mask Mask Interrupt mask register (KEY13<P13>) Interrupt mask register (KEY12<P12>) Interrupt mask register (KEY11<P11>) Interrupt mask register (KEY10<P10>) R/W R/W R/W R/W 0 0 0 0 1 1 1 1 Enable Enable Enable Enable 0 0 0 0 Mask Mask Mask Mask Interrupt mask register (SW direct RUN) Interrupt mask register (SW direct LAP) Interrupt mask register (Stopwatch 1 Hz) Interrupt mask register (Stopwatch 10 Hz) eiT3 eiT2 eiT1 eiT0 R/W R/W R/W R/W 0 0 0 0 1 1 1 1 Enable Enable Enable Enable 0 0 0 0 Mask Mask Mask Mask Interrupt mask register (Clock timer 16 Hz) Interrupt mask register (Clock timer 32 Hz) Interrupt mask register (Clock timer 64 Hz) Interrupt mask register (Clock timer 128 Hz) eiT7 eiT6 eiT5 eiT4 R/W R/W R/W R/W 0 0 0 0 1 1 1 1 Enable Enable Enable Enable 0 0 0 0 Mask Mask Mask Mask Interrupt mask register (Clock timer 1 Hz) Interrupt mask register (Clock timer 2 Hz) Interrupt mask register (Clock timer 4 Hz) Interrupt mask register (Clock timer 8 Hz) FFE1H D3 D2 D1 D0 0 (*3) eiRFe eiRFR eiRFS R - (*2) R/W 0 R/W 0 R/W 0 FFE2H D3 D2 D1 D0 0 (*3) 0 (*3) eiPT0 eiCTC0 R - (*2) R - (*2) R/W 0 R/W 0 FFE3H D3 D2 D1 D0 0 (*3) 0 (*3) eiPT1 eiCTC1 R - (*2) R - (*2) R/W 0 R/W 0 FFE4H D3 D2 D1 D0 0 (*3) 0 (*3) eiPT2 eiCTC2 R - (*2) R - (*2) R/W 0 R/W 0 FFE5H D3 D2 D1 D0 0 (*3) 0 (*3) eiPT3 eiCTC3 R - (*2) R - (*2) R/W 0 R/W 0 FFEAH D3 D2 D1 D0 0 (*3) 0 (*3) 0 (*3) eiSiF R - (*2) R - (*2) R - (*2) R/W 0 FFEBH D3 D2 D1 D0 eiK03 eiK02 eiK01 eiK00 R/W R/W R/W R/W 0 0 0 0 FFECH D3 D2 D1 D0 eiK13 eiK12 eiK11 eiK10 R/W R/W R/W R/W FFEDH D3 D2 D1 D0 eiRun eilaP eiSW1 eiSW10 FFEEH D3 D2 D1 D0 FFEFH D3 D2 D1 D0 S1C6F016 Technical Manual (Rev. 1.1) 1 Enable 1 Enable 1 Enable - - 1 Enable 1 Enable - - 1 Enable 1 Enable - - 1 Enable 1 Enable - - 1 Enable 1 Enable - - - Seiko Epson Corporation 6-5 6 inTeRRuPT COnTROlleR Address Register name R/W Default Setting/data Function FFF1H D3 D2 D1 D0 0 (*3) iRFe iRFR iRFS R - (*2) R/W 0 R/W 0 R/W 0 FFF2H D3 D2 D1 D0 0 (*3) 0 (*3) iPT0 iCTC0 R - (*2) R - (*2) R/W 0 R/W 0 FFF3H D3 D2 D1 D0 0 (*3) 0 (*3) iPT1 iCTC1 R - (*2) R - (*2) R/W 0 R/W 0 FFF4H D3 D2 D1 D0 0 (*3) 0 (*3) iPT2 iCTC2 R - (*2) R - (*2) R/W 0 R/W 0 FFF5H D3 D2 D1 D0 0 (*3) 0 (*3) iPT3 iCTC3 R - (*2) R - (*2) R/W 0 R/W 0 FFFAH D3 D2 D1 D0 0 (*3) 0 (*3) 0 (*3) iSiF R - (*2) R - (*2) R - (*2) R/W 0 FFFBH D3 D2 D1 D0 iK03 iK02 iK01 iK00 R/W R/W R/W R/W 0 0 0 0 1 Occurred (R) Reset (W) 0 Not occurred (R) Interrupt factor flag (KEY03<P03>) Interrupt factor flag (KEY02<P02>) Invalid (W) Interrupt factor flag (KEY01<P01>) Interrupt factor flag (KEY00<P00>) FFFCH D3 D2 D1 D0 iK13 iK12 iK11 iK10 R/W R/W R/W R/W 0 0 0 0 1 Occurred (R) Reset (W) 0 Not occurred (R) Interrupt factor flag (KEY13<P13>) Interrupt factor flag (KEY12<P12>) Invalid (W) Interrupt factor flag (KEY11<P11>) Interrupt factor flag (KEY10<P10>) FFFDH D3 D2 D1 D0 iRun ilaP iSW1 iSW10 R/W R/W R/W R/W 0 0 0 0 1 Occurred (R) Reset (W) 0 Not occurred (R) Interrupt factor flag (SW direct RUN) Interrupt factor flag (SW direct LAP) Invalid (W) Interrupt factor flag (Stopwatch 1 Hz) Interrupt factor flag (Stopwatch 10 Hz) FFFEH D3 D2 D1 D0 iT3 iT2 iT1 iT0 R/W R/W R/W R/W 0 0 0 0 1 Occurred (R) Reset (W) 0 Not occurred (R) Interrupt factor flag (Clock timer 16 Hz) Interrupt factor flag (Clock timer 32 Hz) Invalid (W) Interrupt factor flag (Clock timer 64 Hz) Interrupt factor flag (Clock timer 128 Hz) FFFFH D3 D2 D1 D0 iT7 iT6 iT5 iT4 R/W R/W R/W R/W 0 0 0 0 1 Occurred (R) Reset (W) 0 Not occurred (R) Interrupt factor flag (Clock timer 1 Hz) Interrupt factor flag (Clock timer 2 Hz) Invalid (W) Interrupt factor flag (Clock timer 4 Hz) Interrupt factor flag (Clock timer 8 Hz) *1: Initial value at initial reset - Unused 0 Not occurred (R) Interrupt factor flag (RFC error) Interrupt factor flag (RFC REF completion) Invalid (W) Interrupt factor flag (RFC SEN completion) - - Unused Unused 0 Not occurred (R) Interrupt factor flag (PT0 underflow) Interrupt factor flag (PT0 compare match) Invalid (W) - - Unused Unused 0 Not occurred (R) Interrupt factor flag (PT1 underflow) Interrupt factor flag (PT1 compare match) Invalid (W) - - Unused Unused 0 Not occurred (R) Interrupt factor flag (PT2 underflow) Interrupt factor flag (PT2 compare match) Invalid (W) - - Unused Unused 0 Not occurred (R) Interrupt factor flag (PT3 underflow) Interrupt factor flag (PT3 compare match) Invalid (W) - - - Unused Unused Unused 0 Not occurred (R) Interrupt factor flag (Serial I/F) Invalid (W) 1 Occurred (R) Reset (W) 1 Occurred (R) Reset (W) 1 Occurred (R) Reset (W) 1 Occurred (R) Reset (W) 1 Occurred (R) Reset (W) 1 Occurred (R) Reset (W) *2: Not set in the circuit *3: Constantly "0" when being read ei***: interrupt mask registers (FFe1h-FFeFh) Selects whether interrupts generated by interrupt factors are masked or not. When "1" is written: Enable When "0" is written: Mask Reading: Valid When the interrupt mask register is set to "1," an interrupt to the CPU will be generated if the corresponding interrupt flag is set to 1. Setting the interrupt mask register to "0" masks the interrupt factor and no interrupt will be generated. At initial reset, the interrupt mask registers are set to "0." 6-6 Seiko Epson Corporation S1C6F016 TECHNICAL MANUAL (Rev. 1.1) 6 inTeRRuPT COnTROlleR i***: interrupt factor flags (FFF1h-FFFFh) These flags indicate that the interrupt factor has occurred or not. When "1" is read: Interrupt factor has occurred When "0" is read: Interrupt factor has not occurred When "1" is written: Flag is reset When "0" is written: Invalid The interrupt factor flags are set to "1" when each interrupt factor in the peripheral circuit has occurred. From the status of the interrupt factor flag, the software can determine if the interrupt factor has occurred. If the corresponding interrupt mask register has been set to "1" (interrupt enabled), an interrupt is generated to the CPU when the interrupt factor flag is set to 1. The interrupt factor flag is always set to "1" when the interrupt factor occurs regardless of the interrupt mask register setting. The interrupt flag is reset to "0" by writing "1." After an interrupt has occurred, the same interrupt will occur again if interrupts are enabled (I flag = "1") or the RETI instruction is executed unless the interrupt factor flag is reset. Therefore, be sure to reset (write "1" to) the interrupt factor flag in the interrupt handler routine before enabling the interrupt. After an initial reset, the interrupt factor flags are set to "0." Table 6.5.2 Interrupt factors Interrupt factor Interrupt factor flag R/F converter (error) IRFE (FFF1H*D2) R/F converter (end of reference conversion) IRFR (FFF1H*D1) R/F converter (end of sensor conversion) IRFS (FFF1H*D0) Programmable timer 0 (underflow) IPT0 (FFF2H*D1) Programmable timer 0 (compare match) ICTC0 (FFF2H*D0) Programmable timer 1 (underflow) IPT1 (FFF3H*D1) Programmable timer 1 (compare match) ICTC1 (FFF3H*D0) Programmable timer 2 (underflow) IPT2 (FFF4H*D1) Programmable timer 2 (compare match) ICTC2 (FFF4H*D0) Programmable timer 3 (underflow) IPT3 (FFF5H*D1) Programmable timer 3 (compare match) ICTC3 (FFF5H*D0) Serial interface (8-bit data input/output completion) ISIF (FFFAH*D0) Key input interrupt <P03> IK03 (FFFBH*D3) Key input interrupt <P02> IK02 (FFFBH*D2) Key input interrupt <P01> IK01 (FFFBH*D1) Key input interrupt <P00> IK00 (FFFBH*D0) Key input interrupt <P13> IK13 (FFFCH*D3) Key input interrupt <P12> IK12 (FFFCH*D2) Key input interrupt <P11> IK11 (FFFCH*D1) Key input interrupt <P10> IK10 (FFFCH*D0) Stopwatch timer (Direct RUN) IRUN (FFFDH*D3) Stopwatch timer (Direct LAP) ILAP (FFFDH*D2) Stopwatch timer (1 Hz) ISW1 (FFFDH*D1) Stopwatch timer (10 Hz) ISW10 (FFFDH*D0) Clock timer 16 Hz (falling edge) IT3 (FFFEH*D3) Clock timer 32 Hz (falling edge) IT2 (FFFEH*D2) Clock timer 64 Hz (falling edge) IT1 (FFFEH*D1) Clock timer 128 Hz (falling edge) IT0 (FFFEH*D0) Clock timer 1 Hz (falling edge) IT7 (FFFFH*D3) Clock timer 2 Hz (falling edge) IT6 (FFFFH*D2) Clock timer 4 Hz (falling edge) IT5 (FFFFH*D1) Clock timer 8 Hz (falling edge) IT4 (FFFFH*D0) Interrupt mask register EIRFE (FFE1H*D2) EIRFR (FFE1H*D1) EIRFS (FFE1H*D0) EIPT0 (FFE2H*D1) EICTC0 (FFE2H*D0) EIPT1 (FFE3H*D1) EICTC1 (FFE3H*D0) EIPT2 (FFE4H*D1) EICTC2 (FFE4H*D0) EIPT3 (FFE5H*D1) EICTC3 (FFE5H*D0) EISEIF (FFEAH*D0) EIK03 (FFEBH*D3) EIK02 (FFEBH*D2) EIK01 (FFEBH*D1) EIK00 (FFEBH*D0) EIK13 (FFECH*D3) EIK12 (FFECH*D2) EIK11 (FFECH*D1) EIK10 (FFECH*D0) EIRUN (FFEDH*D3) EILAP (FFEDH*D2) EISW1 (FFEDH*D1) EISW10 (FFEDH*D0) EIT3 (FFEEH*D3) EIT2 (FFEEH*D2) EIT1 (FFEEH*D1) EIT0 (FFEEH*D0) EIT7 (FFEFH*D3) EIT6 (FFEFH*D2) EIT5 (FFEFH*D1) EIT4 (FFEFH*D0) Refer to the descriptions of the peripheral circuits for interrupt factor occurrence conditions. S1C6F016 Technical Manual (Rev. 1.1) Seiko Epson Corporation 6-7 6 inTeRRuPT COnTROlleR 6.6 Precautions * The interrupt factor flags are set when the interrupt condition is established, even if the interrupt mask registers are set to "0." * After an interrupt occurs, the same interrupt will occur again if the interrupt enabled state (I flag = "1") is set or the RETI instruction is executed unless the interrupt factor flag is reset. Therefore, be sure to reset (write "1" to) the interrupt factor flag in the interrupt handler routine before shifting to the interrupt enabled state. * After an initial reset, all the interrupts including NMI are masked until both the stack pointers SP1 and SP2 are set with the software. Be sure to set the SP1 and SP2 in the initialize routine. Further, when re-setting the stack pointer, the SP1 and SP2 must be set as a pair. When one of them is set, all the interrupts including NMI are masked and interrupts cannot be accepted until the other one is set. * The interrupt handler routine must be located within the range from "Interrupt vector address (100H-10FH)" -7FH to +80H. If it is difficult, make a relay point within that range as the destination of the vector jump and branch the program to the interrupt handler from there. * Both the OSC1 and OSC3 oscillation circuits stop oscillating when the CPU enters SLEEP mode. To prevent the CPU from a malfunction when it resumes operating from SLEEP mode, switch the CPU clock to OSC1 before placing the CPU into SLEEP mode. 6-8 Seiko Epson Corporation S1C6F016 TECHNICAL MANUAL (Rev. 1.1) 7 OSCillaTiOn CiRCuiT anD ClOCK COnTROl 7 Oscillation Circuit and Clock Control 7.1 Oscillation Circuit 7.1.1 Configuration of Oscillation Circuit The S1C6F016 is configured as a twin clock system with two internal oscillation circuits (OSC1 and OSC3). The OSC1 oscillation circuit generates the main-clock (Typ. 32.768 kHz) for low-power operation and the OSC3 oscillation circuit generates the sub-clock (Max. 4.2 MHz) to run the CPU and some peripheral circuits in high speed. Figure 7.1.1.1 shows the configuration of the oscillation circuit. OSC1 (fOSC1) Prescaler oscillation circuit Clock switch OSC3 oscillation circuit (fOSC3) SLEEP status Oscillation circuit control signal OSCC To peripheral circuits To CPU To some peripheral circuits CPU clock selection signal CLKCHG Figure 7.1.1.1 Oscillation circuit block diagram At initial reset, OSC1 oscillation circuit is selected as the CPU operating clock source. The S1C6F016 allows the software to turn the OSC3 oscillation circuit on and off, and to switch the system clock between OSC3 and OSC1. The OSC3 oscillation circuit is used when the CPU and some peripheral circuits need high speed operation. Otherwise, use the OSC1 oscillation circuit to generate the operating clock and stop the OSC3 oscillation circuit to reduce current consumption. 7.1.2 Mask Option Standard mask option Type B The OSC1 oscillator type is fixed at crystal and the OSC3 oscillator type is fixed at ceramic. Standard mask option Type e and Type G The OSC1 oscillator type is fixed at crystal and the OSC3 oscillator type is fixed at CR (external R). Custom mask option The OSC1 oscillator type is fixed at crystal. The OSC3 oscillator type can be selected from ceramic, CR (external R) or CR (built-in R). 7.1.3 OSC1 Oscillation Circuit The OSC1 oscillation circuit generates the 32.768 kHz (Typ.) system clock which is used during low speed (low power) operation of the CPU and peripheral circuits. Furthermore, even when OSC3 is used as the system clock, OSC1 continues to generate the source clock for the clock timer and stopwatch timer. This oscillation circuit stops when the SLP instruction is executed. Figure 7.1.3.1 shows the configuration of the OSC1 oscillation circuit. S1C6F016 Technical Manual (Rev. 1.1) Seiko Epson Corporation 7-1 7 OSCillaTiOn CiRCuiT anD ClOCK COnTROl SLEEP status OSC1 fOSC1 CG1 X'tal OSC2 VSS VSS Figure 7.1.3.1 OSC1 oscillation circuit (crystal oscillation) A crystal oscillation circuit can be configured simply by connecting a crystal resonator X'tal (Typ. 32.768 kHz) between the OSC1 and OSC2 terminals along with a trimmer capacitor CG1 (0-25 pF) between the OSC1 terminal and VSS. 7.1.4 OSC3 Oscillation Circuit The OSC3 oscillation circuit generates the system clock to run the CPU and some peripheral circuits at high speed. This oscillation circuit stops when the SLP instruction is executed or the OSCC register is set to "0." The oscillator type can be selected by mask option. Standard mask option Type B: Ceramic (fixed) Standard mask option Type E and Type G: CR (external R) (fixed) Custom mask option: Ceramic, CR (external R) or CR (built-in R) (selectable) Figure 7.1.4.1 shows the configuration of the OSC3 oscillation circuit. CG3 OSC3 fOSC3 Ceramic Rf Oscillation circuit control signal SLEEP status OSC4 CD3 VSS (1) Ceramic oscillation circuit OSC3 fOSC3 RCR Oscillation circuit control signal SLEEP status OSC4 (2) CR oscillation circuit (external R) fOSC3 RCR Oscillation circuit control signal SLEEP status (3) CR oscillation circuit (built-in R) Figure 7.1.4.1 OSC3 oscillation circuit When ceramic oscillation circuit is selected, connect a ceramic resonator (Ceramic) between the OSC3 and OSC4 terminals and connecting two capacitors (CG3, CD3) between the OSC3 terminal and VSS, and between the OSC4 terminal and VSS, respectively. When CR (external R) is selected, connect a resistor (RCR) between the OSC3 and OSC4 terminals. The CR (built-in R) oscillator does not need any external elements. Leave the OSC3 and OSC4 terminals open. 7-2 Seiko Epson Corporation S1C6F016 TECHNICAL MANUAL (Rev. 1.1) 7 OSCillaTiOn CiRCuiT anD ClOCK COnTROl Table 7.1.4.1 OSC3 oscillation frequency Oscillator type Oscillation frequency Ceramic Max. 4.2 MHz CR (external R) 30 kHz to 2.2 MHz CR (built-in R) Typ. 500 kHz 25% 7.2 Switching the CPu Clock Either the OSC1 clock or the OSC3 clock can be selected as the CPU system clock using the CLKCHG register. The OSC3 oscillation circuit can be turned off (OSCC = "0") to save power while the CPU is operating with the OSC1 clock (CLKCHG = "0"). If the system needs high speed operation, turn the OSC3 oscillation circuit on (OSCC = "1") and switch over the system clock to OSC3 (CLKCHG = "0" "1"). In this case, since several tens of sec to several tens of msec are necessary for the oscillation to stabilize after turning the OSC3 oscillation circuit on, you should switch over the clock after the stabilization time has elapsed. The oscillation start time will vary somewhat depending on the resonator and on the externally attached parts. Refer to the oscillation start time example indicated in the "Electrical Characteristics" chapter. When switching the clock from OSC3 to OSC1 (CLKCHG = "1" "0"), be sure to switch OSC3 oscillation off with separate instructions. Using a single instruction to process simultaneously may cause a malfunction of the CPU. Figure 7.2.1 indicates the status transition diagram for the clock switch over. Program Execution Status RESET High speed operation CLKCHG=0 Low speed operation OSC1 OSC1 ON ON OSC3 OSC3 ON ON CPU clock OSC3 CLKCHG=1 CPU clock OSC1 Interrupt * OSCC=0 OSCC=1 HALT instruction Interrupt * (Key input interrupt) Low speed and low power operation OSC1 ON OSC3 OFF CPU clock OSC1 SLP instruction SLEEP status OSC1 OFF OSC3 OFF CPU clock STOP HALT status OSC1 ON OSC3 ON or OFF CPU clock STOP Standby Status * The return destination from the standby status becomes the program execution status prior to shifting to the standby status. Figure 7.2.1 Status transition diagram for clock switch over 7.3 halT and SleeP The S1C6F016 supports both HALT and SLEEP modes for power saving during standby. halT mode The CPU enters HALT mode and stops operating when it executes the HALT instruction. However, timer counters and peripheral circuits continue operating since the oscillation circuit operates in HALT mode. Reactivating the CPU from HALT status is done by generating a hardware interrupt request including NMI. S1C6F016 Technical Manual (Rev. 1.1) Seiko Epson Corporation 7-3 7 OSCillaTiOn CiRCuiT anD ClOCK COnTROl SleeP mode The CPU enters SLEEP mode when it executes the SLP instruction. In this mode, the CPU, and oscillation circuits (both OSC1 and OSC3) stop operating. Current consumption can considerably be reduced, as SLEEP mode stop all the peripheral circuits that operate with the internal clocks. To prevent improper operation after the CPU wakes up, be sure to run the CPU with the OSC1 clock before setting the CPU into SLEEP mode. The system can only be reactivated from SLEEP mode by a key input interrupt request from a P0x or P1x port. To ensure that the system enters and cancels SLEEP mode properly, follow the procedure shown below to configure/ confirm the CPU clock, interrupt flag, the P0x (P1x) I/O port used to cancel SLEEP mode, and the port input level. 1. Set the CPU system clock switching register CLKCHG to "0." (The OSC1 clock is selected.) 2. Set the interrupt select register SIPxx to "1." (The P0x (P1x) I/O port interrupt is selected.) 3. Set the interrupt mask register EIKxx to "1." (The P0x (P1x) I/O port interrupt is enabled.) 4. Set the key input interrupt noise reject frequency select register NRSPxx to "00." (The noise rejector is bypassed.) 5. Write "1" to the interrupt factor flag IKxx. (The P0x (P1x) interrupt factor flag is reset.) 6. Set the interrupt flag (I flag) to "1." (Interrupts are enabled.) 7a. Make sure the P0x (P1x) port input level is high when P0x (P1x) port interrupt polarity select register PCPxx = "1" (generates an interrupt request at the falling edge). 7b. Make sure the P0x (P1x) port input level is low when P0x (P1x) port interrupt polarity select register PCPxx = "0" (generates an interrupt request at the rising edge). 8. Execute the SLP instruction. When SLEEP status is canceled by an I/O port interrupt, the CPU restarts operating (input port interrupt processing) after waiting for oscillation to stabilize. Refer to the "S1C63000 Core CPU Manual" for transition to HALT/ SLEEP mode and timing of its cancellation. 7.4 Control of Peripheral Circuit Clocks The S1C6F016 incorporates a clock manager that generates operating clocks by dividing the OSC1/OSC3 clock output from the oscillation circuit and supplies the clocks to the peripheral circuits. Some peripheral circuits can select the operating clock to be used from several dividing clocks in the clock manager. If the current processing does not use peripheral circuits, the clock supply to those circuits can be stopped in the clock manager. Disabling unnecessary clocks to be supplied or operating the peripheral circuits with a clock as low frequency as possible can reduce current consumption. For controlling the clock manager, see the descriptions in each peripheral circuit. 7.5 Clock Output (FOuT) In order for the S1C6F016 to provide a clock signal to an external device, the FOUT signal (oscillation clock fOSC1, fOSC3, or a dividing clock) can be output from the FOUT (P13) terminal. The FOUT output is controlled using the FOUT[3:0] register. When the output clock frequency is selected using FOUT[3:0], the FOUT signal is output from the FOUT terminal. The P13 I/O port functions are disabled while the FOUT signal is being output. Setting FOUT[3:0] to 0H disables FOUT output and the P13 port is configured as a general-purpose input/output port. The FOUT signal frequency can be selected from among 15 settings as shown in Table 7.5.1. 7-4 Seiko Epson Corporation S1C6F016 TECHNICAL MANUAL (Rev. 1.1) 7 OSCillaTiOn CiRCuiT anD ClOCK COnTROl Table 7.5.1 FOUT frequency selection FOUT[3:0] FOUT frequency FH fOSC3 EH fOSC3 / 2 DH fOSC3 / 4 CH fOSC3 / 8 BH fOSC3 / 16 AH fOSC3 / 32 9H fOSC3 / 64 8H fOSC3 / 256 7H fOSC1 (32 kHz) 6H fOSC1 / 2 (16 kHz) 5H fOSC1 / 4 (8 kHz) 4H fOSC1 / 16 (2 kHz) 3H fOSC1 / 32 (1 kHz) 2H fOSC1 / 64 (512 Hz) 1H fOSC1 / 256 (128 Hz) 0H Off fOSC1: OSC1 oscillation frequency. ( ) indicates the clock frequency when fOSC1 = 32 kHz. fOSC3: OSC3 oscillation frequency When the FOUT frequency is set to "fOSC3/n," the OSC3 oscillation circuit must be turned on before outputting the FOUT signal. A time interval of several tens of sec to several tens of msec, from turning the OSC3 oscillation circuit on until the oscillation stabilizes, is necessary. Consequently, if an abnormality occurs as the result of an unstable FOUT signal being output externally, you should allow an adequate waiting time after turning the OSC3 oscillation on, before starting FOUT output. Since the FOUT signal is generated asynchronously from the FOUT[3:0] register, a hazard of a 1/2 cycle or less is generated when the signal is turned on or off by setting the registers. Figure 7.5.1 shows the output waveform of the FOUT signal. 0H FOUT[3:0] Other than 0H 0H FOUT output (P13) Figure 7.5.1 Output waveform of FOUT signal 7.6 i/O Memory for Oscillation Circuit/Clock Output Control Table 7.6.1 shows the I/O address and the control bits for the oscillation circuit and FOUT output. Table 7.6.1 Control bits of oscillation circuit/FOUT Address Register name R/W Default Setting/data FF00H D3 D2 D1 D0 ClKChG OSCC 0 (*3) 0 (*3) R/W 0 R/W 0 R - (*2) R - (*2) 1 OSC3 1 On FF10H D3 D2 D1 D0 FOuT3 FOuT2 FOuT1 FOuT0 R/W R/W R/W R/W F E D C *1: Initial value at initial reset 0 0 0 0 Function 0 OSC1 0 Off CPU clock switch OSC3 oscillation On/Off Unused Unused - - f3 f3/2 f3/4 f3/8 B A 9 8 f3/16 f3/32 f3/64 f3/256 *2: Not set in the circuit 7 6 5 4 f1 f1/2 f1/4 f1/16 3 2 1 0 f1/32 FOUT frequency selection f1/64 (f1 = fOSC1, f3 = fOSC3) f1/256 Off *3: Constantly "0" when being read OSCC: OSC3 oscillation control register (FF00h*D2) Turns the OSC3 oscillation circuit on and off. When "1" is written: OSC3 oscillation On When "0" is written: OSC3 oscillation Off Reading: Valid When it is necessary to operate the CPU at high speed, set OSCC to "1." At other times, set it to "0" to reduce current consumption. At initial reset, this register is set to "0." S1C6F016 Technical Manual (Rev. 1.1) Seiko Epson Corporation 7-5 7 OSCillaTiOn CiRCuiT anD ClOCK COnTROl ClKChG: CPu system clock switching register (FF00h*D3) The CPU's operation clock is selected with this register. When "1" is written: OSC3 clock is selected When "0" is written: OSC1 clock is selected Reading: Valid When the CPU clock is to be OSC3, set CLKCHG to "1"; for OSC1, set CLKCHG to "0." At initial reset, this register is set to "0." FOuT[3:0]: FOuT frequency select register (FF10h) Selects the frequency of the FOUT signal and controls the FOUT output. Table 7.6.2 FOUT clock frequency FOUT[3:0] FOUT frequency FH fOSC3 EH fOSC3 / 2 DH fOSC3 / 4 CH fOSC3 / 8 BH fOSC3 / 16 AH fOSC3 / 32 9H fOSC3 / 64 8H fOSC3 / 256 7H fOSC1 (32 kHz) 6H fOSC1 / 2 (16 kHz) 5H fOSC1 / 4 (8 kHz) 4H fOSC1 / 16 (2 kHz) 3H fOSC1 / 32 (1 kHz) 2H fOSC1 / 64 (512 Hz) 1H fOSC1 / 256 (128 Hz) 0H Off fOSC1: OSC1 oscillation frequency. ( ) indicates the clock frequency when fOSC1 = 32 kHz. fOSC3: OSC3 oscillation frequency Selecting an FOUT frequency (writing 1H-FH to this register) outputs the FOUT signal from the FOUT (P13) terminal. Set FOUT[3:0] to "0" to use P13 as a general-purpose input/output port. At initial reset, this register is set to "0." 7.7 Precautions * When high speed CPU operations are not necessary, you should operate the peripheral circuits with the setting shown below. - CPU operating clock: OSC1 - OSC3 oscillation circuit: Off (When the OSC3 clock is not necessary for peripheral circuits.) - Clock manager: Disable the clock supply to unnecessary peripheral circuits. * Since several tens of sec to several tens of msec are necessary for the oscillation to stabilize after turning the OSC3 oscillation circuit on. Consequently, you should switch the CPU operating clock (OSC1 OSC3) after allowing for a sufficient waiting time once the OSC3 oscillation goes on. The oscillation start time will vary somewhat depending on the resonator and externally attached parts. Refer to the oscillation start time example indicated in the "Electrical Characteristics" chapter. * When switching the clock from OSC3 to OSC1, be sure to switch OSC3 oscillation off with separate instructions. Using a single instruction to process simultaneously can cause a malfunction of the CPU. * Both the OSC1 and OSC3 oscillation circuits stop oscillating when the CPU enters SLEEP mode. To prevent the CPU from a malfunction when it resumes operating from SLEEP mode, switch the CPU clock to OSC1 before placing the CPU into SLEEP mode. 7-6 Seiko Epson Corporation S1C6F016 TECHNICAL MANUAL (Rev. 1.1) 8 WaTChDOG TiMeR 8 Watchdog Timer 8.1 Configuration of Watchdog Timer The S1C6F016 has a built-in watchdog timer that operates with a 256 Hz divided clock from the OSC1 as the source clock. The watchdog timer starts operating after initial reset, however, it can be stopped by the software. The watchdog timer must be reset cyclically by the software while it operates. If the watchdog timer is not reset in at least 3-4 seconds, it generates a non-maskable interrupt (NMI) to the CPU. Figure 8.1.1 is the block diagram of the watchdog timer. Non-maskable interrupt (NMI) Watchdog timer OSC1 dividing signal 256 Hz Watchdog timer enable signal Watchdog timer reset signal Figure 8.1.1 Watchdog timer block diagram The watchdog timer contains a 10-bit binary counter, and generates the non-maskable interrupt when the last stage of the counter (0.25 Hz) overflows. Watchdog timer reset processing in the program's main routine enables detection of program overrun, such as when the main routine's watchdog timer processing is bypassed. Ordinarily this routine is incorporated where periodic processing takes place, just as for the timer interrupt routine. The watchdog timer operates in the HALT mode. If a HALT status continues for 3-4 seconds, the non-maskable interrupt releases the HALT status. 8.2 interrupt Function If the watchdog timer is not reset periodically, the non-maskable interrupt (NMI) is generated to the core CPU. Since this interrupt cannot be masked, it is accepted even in the interrupt disable status (I flag = "0"). However, it is not accepted when the CPU is in the interrupt mask state until SP1 and SP2 are set as a pair, such as after initial reset or during re-setting the stack pointer. The interrupt vector of NMI is assigned to 0100H in the program memory. 8.3 i/O Memory of Watchdog Timer Table 8.3.1 shows the I/O address and control bits for the watchdog timer. Table 8.3.1 Control bits of watchdog timer Address FF01H D3 D2 D1 D0 Register name R/W Default 0 (*3) 0 (*3) WDen WDRST (*3) Setting/data R - (*2) R - (*2) R/W 1 1 Enable W (Reset) 1 Reset *1: Initial value at initial reset *2: Not set in the circuit - - 0 Disable 0 Invalid Function Unused Unused Watchdog timer enable Watchdog timer reset (writing) *3: Constantly "0" when being read WDRST: Watchdog timer reset (FF01h*D0) Resets the watchdog timer. When "1" is written: Watchdog timer is reset When "0" is written: No operation Reading: Always "0" When "1" is written to WDRST, the watchdog timer is reset and restarts immediately after that. When "0" is written, no operation results. This bit is dedicated for writing, and is always "0" for reading. S1C6F016 Technical Manual (Rev. 1.1) Seiko Epson Corporation 8-1 8 WaTChDOG TiMeR WDen: Watchdog timer enable register (FF01h*D1) Selects whether the watchdog timer is used (enabled) or not (disabled). When "1" is written: Enabled When "0" is written: Disabled Reading: Valid When "1" is written to the WDEN register, the watchdog timer starts count operation. When "0" is written, the watchdog timer does not count and does not generate the interrupt (NMI). At initial reset, this register is set to "1." 8.4 Precautions * When the watchdog timer is being used, the software must reset it within 3-second cycles. * Because the watchdog timer is set in operation state by initial reset, set the watchdog timer to disabled state (not used) before generating an interrupt (NMI) if it is not used. 8-2 Seiko Epson Corporation S1C6F016 TECHNICAL MANUAL (Rev. 1.1) 9 ClOCK TiMeR 9 Clock Timer 9.1 Configuration of Clock Timer The S1C6F016 has a built-in clock timer that uses OSC1 (crystal oscillator) as the source oscillator. The clock timer consists of an 8-bit binary counter that counts an fOSC1 dividing clock. Timer data (128-16 Hz and 8-1 Hz) can be read out by software. Figure 9.1.1 is the block diagram for the clock timer. Data bus Clock timer OSC1 oscillation circuit (fOSC1) Clock manager fOSC1/128 128 Hz-16 Hz 8 Hz-1 Hz 128 Hz, 64 Hz, 32 Hz, 16 Hz, 8 Hz, 4 Hz, 2 Hz, 1 Hz Clock enable signal Clock timer reset signal Clock timer RUN/STOP signal Interrupt control Interrupt request Figure 9.1.1 Block diagram for the clock timer Ordinarily, this clock timer is used for all types of timing functions such as clocks. 9.2 Controlling Operating Clock The clock manager generates the clock timer operating clock by dividing the OSC1 clock by 128. Before the clock timer can be run, write "1" to the RTCKE register to supply the operating clock to the clock timer. Table 9.2.1 Controlling clock timer operating clock RTCKE Clock timer operating clock 1 fOSC1 / 128 (256 Hz) 0 Off If it is not necessary to run the clock timer, stop the clock supply by setting RTCKE to "0" to reduce current consumption. 9.3 Data Read and hold Function The 8 bits timer data are allocated to the address FF41H and FF42H. <FF41H> <FF42H> D0: TM0 = 128 Hz D0: TM4 = 8 Hz D1: TM1 = 64 Hz D1: TM5 = 4 Hz D2: TM2 = 32 Hz D2: TM6 = 2 Hz D3: TM3 = 16 Hz D3: TM7 = 1 Hz Since two addresses are allocated for the clock timer data, a carry is generated from the low-order data (TM[3:0]: 128-16 Hz) to the high-order data (TM[7:4]: 8-1 Hz) during counting. If this carry is generated between readings of the low-order data and the high-order data, the combined data does not represent the correct value (if a carry occurs after the low-order data is read as FFH, the incremented (+1) value is read as the high-order data). To avoid this problem, the clock timer is designed to latch the high-order data at the time the low-order data is read. The latched high-order data will be maintained until the next reading of the low-order data. Note: The latched value, not the current value, is always read as the high-order data. Therefore, be sure to read the low-order data first. S1C6F016 Technical Manual (Rev. 1.1) Seiko Epson Corporation 9-1 9 ClOCK TiMeR 9.4 interrupt Function The clock timer can generate an interrupt at the falling edge of 128 Hz, 64 Hz, 32 Hz, 16 Hz, 8 Hz, 4 Hz, 2 Hz and 1 Hz signals. Software can enable or mask any of these frequencies to generate interrupts. Figure 9.4.1 is the timing chart of the clock timer. Address Bit Frequency D0 128 Hz D1 64 Hz D2 32 Hz D3 16 Hz D0 8 Hz D1 4 Hz D2 2 Hz D3 1 Hz Clock timer timing chart FF41H FF42H 128 Hz interrupt request 64 Hz interrupt request 32 Hz interrupt request 16 Hz interrupt request 8 Hz interrupt request 4 Hz interrupt request 2 Hz interrupt request 1 Hz interrupt request Figure 9.4.1 Timing chart of clock timer As shown in Figure 9.2, an interrupt is generated at the falling edge of each frequency signal (128 Hz, 64 Hz, 32 Hz, 16 Hz, 8 Hz, 4 Hz, 2 Hz, 1 Hz). At this time, the corresponding interrupt factor flag (IT0, IT1, IT2, IT3, IT4, IT5, IT6, IT7) is set to "1." The interrupt mask registers (EIT0, EIT1, EIT2, EIT3, EIT4, EIT5, EIT6, EIT7) are used to enable or mask each interrupt factor. However, regardless of the interrupt mask register setting, the interrupt factor flag is set to "1" at the falling edge of the corresponding signal. 9.5 i/O Memory of Clock Timer Table 9.5.1 shows the I/O addresses and the control bits for the clock timer. Table 9.5.1 Control bits of clock timer Address Register name R/W Default 0 0 0 0 Setting/data FF16H D3 D2 D1 D0 MDCKE SGCKE SWCKE RTCKe R/W R/W R/W R/W 1 1 1 1 Enable Enable Enable Enable FF40H D3 D2 D1 D0 0 (*3) 0 (*3) TMRST (*3) TMRun R - (*2) R - (*2) W (Reset) 1 Reset R/W 0 1 Run 0 0 0 0 Disable Disable Disable Disable - - 0 Invalid 0 Stop 9-2 Seiko Epson Corporation Function Integer multiplier clock enable Sound generator clock enable Stopwatch timer clock enable Clock timer clock enable Unused Unused Clock timer reset (writing) Clock timer Run/Stop S1C6F016 TECHNICAL MANUAL (Rev. 1.1) 9 ClOCK TiMeR Address Register name R/W Default FF41H D3 D2 D1 D0 TM3 TM2 TM1 TM0 R R R R 0 0 0 0 FF42H D3 D2 D1 D0 TM7 TM6 TM5 TM4 R R R R 0 0 0 0 *1: Initial value at initial reset Setting/data Function 0H-FH Clock timer data (16 Hz) Clock timer data (32 Hz) Clock timer data (64 Hz) Clock timer data (128 Hz) 0H-FH Clock timer data (1 Hz) Clock timer data (2 Hz) Clock timer data (4 Hz) Clock timer data (8 Hz) *2: Not set in the circuit *3: Constantly "0" when being read RTCKe: Clock timer clock enable register (FF16h*D0) Controls the operating clock supply to the clock timer. When "1" is written: On When "0" is written: Off Reading: Valid When "1" is written to RTCKE, the clock timer operating clock is supplied from the clock manager. If it is not necessary to run the clock timer, stop the clock supply by setting RTCKE to "0" to reduce current consumption. At initial reset, this register is set to "0." TMRun: Clock timer Run/Stop control register (FF40h*D0) Controls run/stop of the clock timer. When "1" is written: Run When "0" is written: Stop Reading: Valid The clock timer starts running when "1" is written to the TMRUN register, and stops when "0" is written. In stop status, the timer data is maintained until the next run status or the timer is reset. Also, when stop status changes to run status, the data that is maintained can be used for resuming the count. At initial reset, this register is set to "0." TMRST: Clock timer reset (FF40h*D1) This bit resets the clock timer. When "1" is written: Clock timer reset When "0" is written: No operation Reading: Always "0" The clock timer is reset by writing "1" to TMRST. The clock timer must be reset when it is stopped (TMRUN = "0"). No operation results when "0" is written to TMRST. This bit is write-only, and so is always "0" at reading. TM[7:0]: Timer data (FF42h, FF41h) The 128-1 Hz timer data of the clock timer can be read out with these registers. These eight bits are read only, and writing operations are invalid. By reading the low-order data (FF41H), the high-order data (FF42H) is latched. The latched value, not the current value, is always read as the high-order data. Therefore, be sure to read the loworder data first. At initial reset, the timer data is initialized to "00H." S1C6F016 Technical Manual (Rev. 1.1) Seiko Epson Corporation 9-3 9 ClOCK TiMeR 9.6 Precautions * Be sure to read timer data in the order of low-order data (TM[3:0]) then high-order data (TM[7:4]). * The clock timer count clock does not synch with the CPU clock. Therefore, the correct value may not be obtained depending on the count data read and count-up timings. To avoid this problem, the clock timer count data should be read by one of the procedures shown below. - Read the count data twice and verify if there is any difference between them. - Temporarily stop the clock timer when the counter data is read to obtain proper data. * When resetting the clock timer (TMRST = "1"), do not start the clock timer (TMRUN = "1") simultaneously. If both control bits are set to "1", the clock timer may not reset properly. 9-4 Seiko Epson Corporation S1C6F016 TECHNICAL MANUAL (Rev. 1.1) 10 STOPWaTCh TiMeR 10 Stopwatch Timer 10.1 Configuration of Stopwatch Timer The S1C6F016 has a 1/1,000 sec stopwatch timer. The stopwatch timer is configured of a 3-stage, 4-bit BCD counter serving as the input clock of a 1,000 Hz signal output from the prescaler. Data can be read out four bits (1/1,000 sec, 1/100 sec and 1/10 sec) at a time by software. In addition it has a direct input function that controls the stopwatch timer RUN/STOP and LAP using the input ports P00 and P01. Figure 10.1.1 is the block diagram of the stopwatch timer. SWCKE OSC1 oscillation circuit (fOSC1) SWRST Clock manager fOSC1/32 1,000 / 1,024 (1,000 Hz) 1/1,000 sec prescaler counter 1/100 sec counter 1/10 sec counter 10 Hz interrupt request SWDIR P01 P00 Direct input control Capture control circuit Capture buffer SWD[3:0] reading SWRUN P02, P03, P10-P13 1 Hz interrupt request DKM[2:0] EDIR LCURF CRNWF SWD[7:4] reading SWD[11:8] reading Data bus Direct RUN interrupt request Direct LAP interrupt request Figure 10.1.1 Block diagram of stopwatch timer The stopwatch timer can be used as a separate timer from the clock timer. In particular, digital watch stopwatch functions can be realized easily with software. 10.2 Controlling Operating Clock The clock manager generates the stopwatch timer operating clock by dividing the OSC1 clock by 32. Before the stopwatch timer can be run, write "1" to the SWCKE register to supply the operating clock to the stopwatch timer. Table 10.2.1 Controlling stopwatch timer operating clock SWCKE Stopwatch timer clock 1 fOSC1 / 32 (1 kHz) 0 Off If it is not necessary to run the stopwatch timer, stop the clock supply by setting SWCKE to "0" to reduce current consumption. 10.3 Counter and Prescaler The stopwatch timer is configured of four-bit BCD counters SWD[3:0], SWD[7:4] and SWD[11:8]. The counter SWD[3:0], at the stage preceding the stopwatch timer, has a 1,000 Hz signal generated by the prescaler for the input clock. It counts up every 1/1,000 sec, and generates 100 Hz signal. The counter SWD[7:4] has a 100 Hz signal generated by the counter SWD[3:0] for the input clock. It count-up every 1/100 sec, and generated 10 Hz signal. The counter SWD[11:8] has an approximated 10 Hz signal generated by the counter SWD[7:4] for the input clock. It count-up every 1/10 sec, and generated 1 Hz signal. The prescaler inputs a 1,024 Hz clock dividing fOSC1 (output from the OSC1 oscillation circuit), and outputs 1,000 Hz counting clock for SWD[3:0]. To generate a 1,000 Hz clock from 1,024 Hz, 24 pulses from 1,024 pulses that are input to the prescaler every second are taken out. S1C6F016 Technical Manual (Rev. 1.1) Seiko Epson Corporation 10-1 10 STOPWaTCh TiMeR When the counter becomes the value indicated below, one pulse (1,024 Hz) that is input immediately after to the prescaler will be pulled out. <Counter value (msec) in which the pulse correction is performed> 39, 79, 139, 179, 219, 259, 299, 319, 359, 399, 439, 479, 539, 579, 619, 659, 699, 719, 759, 799, 839, 879, 939, 979 Figure 10.3.1 shows the operation of the prescaler. START Prescaler input clock (1,024 Hz) Prescaler output clock Counter data 000 001 002 037 038 039 040 041 Figure 10.3.1 Timing of the prescaler operation For the above reason, the counting clock is 1,024 Hz (0.9765625 msec) except during pulse correction. Consequently, frequency of the prescaler output clock (1,000 Hz), 100 Hz generated by SWD[3:0] and 10 Hz generated by SWD[7:4] are approximate values. 10.4 Capture Buffer and hold Function The stopwatch timer data, 1/1,000 sec, 1/100 sec and 1/10 sec, can be read from SWD[3:0] (FF4BH), SWD[7:4] (FF4CH) and SWD[11:8] (FF4DH), respectively. The counter data are latched in the capture buffer when reading, and are held until reading of three words is completed. For this reason, correct data can be read even when a carry from lower digits occurs during reading the three words. Further, three counter data are latched in the capture buffer at the same time when SWD[3:0] (1/1,000 sec) is read. The data hold is released when SWD[11:8] (1/10 sec) reading is completed. Therefore, data should be read in order of SWD[3:0] SWD[7:4] SWD[11:8]. If SWD[7:4] or SWD[11:8] is first read when data have not been held, the hold function does not work and data in the counter is directly read out. When data that has not been held is read in the stopwatch timer RUN status, you cannot judge whether it is correct or not. The stopwatch timer has a LAP function using an external key input (explained later). The capture buffer is also used to hold LAP data. In this case, data is held until SWD[11:8] is read. However, when a LAP input is performed before completing the reading, the content of the capture buffer is renewed at that point. Remaining data that have not been read become invalid by the renewal, and the hold status is not released if SWD[11:8] is read. When SWD[11:8] is read after the capture buffer is updated, the capture renewal flag CRNWF is set to "1" at that point. In this case, it is necessary to read from SWD[3:0] again. The capture renewal flag is renewed by reading SWD[11:8]. Figure 10.4.1 shows the timing for data holding and reading. Direct LAP input (P01/P00) Direct LAP internal signal Capture renewal flag CRNWF SWD[3:0] reading SWD[7:4] reading SWD[11:8] reading Data holding Figure 10.4.1 Timing for data holding and reading 10-2 Seiko Epson Corporation S1C6F016 TECHNICAL MANUAL (Rev. 1.1) 10 STOPWaTCh TiMeR 10.5 Stopwatch Timer Run/STOP and Reset RUN/STOP control and reset of the stopwatch timer can be done by software. Stopwatch timer Run/STOP The stopwatch timer enters the RUN status when "1" is written to SWRUN, and the STOP status when "0" is written. In the STOP status, the timer data is maintained until the next RUN status or resets timer. Also, when the STOP status changes to the RUN status, the data that was maintained can be used for resuming the count. The RUN/STOP operation of the stopwatch timer by writing to the SWRUN register is performed in synchronization with the falling edge of the 1,024 Hz same as the prescaler input clock. The SWRUN register can be read, and in this case it indicates the operating status of the stopwatch timer. Figure 10.5.1 shows the operating timing when controlling the SWRUN register. fOSC1/32 (1,024 Hz) SWRUN writing SWRUN register Count clock Figure 10.5.1 Operating timing when controlling SWRUN When the direct input function (explained in next section) is set, RUN/STOP control is done by an external key input. In this case, SWRUN becomes read only register that indicates the operating status of the stopwatch timer. Stopwatch timer reset The stopwatch timer is reset when "1" is written to SWRST. With this, the counter value is cleared to "000." Since this resetting does not affect the capture buffer, data that has been held in the capture buffer is not cleared and is maintained as is. When the stopwatch timer is reset in the RUN status, counting restarts from count "000." Also, in the STOP status the reset data "000" is maintained until the next RUN. 10.6 Direct input Function and Key Mask The stopwatch timer has a direct input function that can control the RUN/STOP and LAP operation of the stopwatch timer by external key input. This function is set by writing "1" to the EDIR register. When EDIR is set to "0," only the software control is possible as explained in the previous section. input port configuration In the direct input function, the input ports P00 and P01 are used as the RUN/STOP and LAP input ports. The key assignment can be selected using the SWDIR register. Table 10.6.1 RUN/STOP and LAP input ports SWDIR P00 P01 0 RUN/STOP LAP 1 LAP RUN/STOP Direct Run When the direct input function is selected, RUN/STOP operation of the stopwatch timer can be controlled by using the key connected to the input port P00/P01 (selected by SWDIR). P00/P01 works as a normal input port, but the input signal is sent to the stopwatch control circuit. The key input signal from the P00/P01 port works as a toggle switch. When it is input in STOP status, the stopwatch timer runs, and in RUN status, the stopwatch timer stops. RUN/STOP status of the stopwatch timer can be checked by reading the SWRUN register. An interrupt is generated by direct RUN input. The sampling for key input signal is performed at the falling edge of 1,024 Hz signal same as the SWRUN control. The chattering judgment is performed at the point where the key turns off, and a chattering less than 46.8-62.5 msec is removed. Therefore, more time is needed for an interval between RUN and STOP key inputs. Figure 10.6.1 shows the operating timing for the direct RUN input. S1C6F016 Technical Manual (Rev. 1.1) Seiko Epson Corporation 10-3 10 STOPWaTCh TiMeR fOSC1/32 (1,024 Hz) Direct RUN input (P00/P01) Direct RUN internal signal SWRUN register Count clock Direct RUN interrupt Figure 10.6.1 Operating timing for direct RUN input Direct laP Control for the LAP can also be done by key input same as the direct RUN. When the direct input function is selected, the input port P01/P00 (selected by SWDIR) becomes the LAP key input port. Sampling for the input signal and the chattering judgment are the same as a direct RUN. By entering the LAP key, the counter data at that point is latched into the capture buffer and is held. The counter continues counting operation. Furthermore, an interrupt occurs by direct LAP input. As stated above, the capture buffer data is held until SWD[11:8] is read. If the LAP key is input when data has been already held, it renews the content of the capture buffer. When SWD[11:8] is read after renewing, the capture renewal flag is set to "1." In this case, the hold status is not released by reading SWD[11:8], and it continues. Normally the LAP data should be read after the interrupt is generated. After that, be sure to check the capture renewal flag. When the capture renewal flag is set, renewed data is held in the capture buffer. So it is necessary to read from SWD[3:0] again. The stopwatch timer sets the 1 Hz interrupt factor flag ISW1 to "1" when requiring a carry-up to 1-sec digit by an SWD[11:8] overflow. If the capture buffer shifts into hold status (when SWD[3:0] is read or when LAP is input) while the 1 Hz interrupt factor flag ISW1 is set to "1," the lap data carry-up request flag LCURF is set to "1" to indicate that a carry-up to 1-sec digit is required for the processing of LAP input. In normal software processing, LAP processing may take precedence over 1-sec or higher digits processing by a 1 Hz interrupt, therefore carryup processing using this flag should be used for time display in the LAP processing to prevent the 1-sec digit data decreasing by 1 second. This flag is renewed when the capture buffer shifts into hold status. Figure 10.6.2 shows the operating timing for the direct LAP input, and Figure 10.6.3 shows the timings for data holding and reading during a direct LAP input and reading. fOSC1/32 (1,024 Hz) Direct LAP input (P01/P00) Direct LAP internal signal Data holding SWD[11:8] reading Direct LAP interrupt Figure 10.6.2 Operating timing for direct LAP input Direct LAP input (P01/P00) Capture renewal flag CRNWF SWD[3:0] reading SWD[7:4] reading SWD[11:8] reading Data holding 1 Hz interrupt factor flag ISW1 Lap data carry-up request flag LCURF Counter data 999 000 Figure 10.6.3 Timing for data holding and reading during direct LAP input 10-4 Seiko Epson Corporation S1C6F016 TECHNICAL MANUAL (Rev. 1.1) 10 STOPWaTCh TiMeR Key mask In stopwatch applications, some functions may be controlled by a combination of keys including direct RUN or direct LAP. For instance, the RUN key can be used for other functions, such as reset and setting a watch, by pressing the RUN key with another key. In this case, the direct RUN function or direct LAP function must be invalid so that it does not function. For this purpose, the key mask function is set so that it judges concurrence of input keys and invalidates RUN and LAP functions. A combination of the key inputs for this judgment can be selected using the DKM[2:0] register. Table 10.6.2 Key mask selection DKM[2:0] Mask key combination 0H None (at initial reset) 1H P02 2H P02, P03 3H P02, P03, P10 4H P10 5H P10, P11 6H P10, P11, P12 7H P10, P11, P12, P13 RUN or LAP inputs become invalid in the following status. 1. The RUN or LAP key is pressed when one or more keys that are included in the selected combination (here in after referred to as mask) are held down. 2. The RUN or LAP key has been pressed when the mask is released. fOSC1/32 (1,024 Hz) Direct RUN/LAP input Key mask valid invalid invalid invalid Figure 10.6.4 Operation of key mask RUN or LAP inputs become valid in the following status. 1. Either the RUN or LAP key is pressed independently if no other key is been held down. 2. Both the RUN and LAP keys are pressed at the same time if no other key is held down. (RUN and LAP functions are effective.) 3. The RUN or LAP key is pressed if either is held down. (RUN and LAP functions are effective.) 4. Either the RUN or LAP key and the mask key are pressed at the same time if no other key is held down. 5. Both the RUN and LAP keys and the mask key are pressed at the same time if no other key is held down. (RUN and LAP functions are effective.) * Simultaneous key input is referred to as two or more key inputs are sampled at the same falling edge of 1,024 Hz clock. S1C6F016 Technical Manual (Rev. 1.1) Seiko Epson Corporation 10-5 10 STOPWaTCh TiMeR 10.7 interrupt Function 10 hz and 1 hz interrupts The 10 Hz and 1 Hz interrupts can be generated through the overflow of stopwatch timers SWD[7:4] and SWD[11:8] respectively. Also, software can set whether to separately mask the frequencies described earlier. Figure 10.7.1 is the timing chart for the counters. Address Register Stopwatch timer (SWD[3:0]) timing chart D0 FF4BH D1 (1/1,000 sec BCD) D2 D3 Address Register Stopwatch timer (SWD[7:4]) timing chart D0 FF4CH D1 (1/100 sec BCD) D2 D3 10 Hz interrupt request Address Register Stopwatch timer (SWD[11:8]) timing chart D0 FF4DH D1 (1/10 sec BCD) D2 D3 1 Hz interrupt request Figure 10.7.1 Timing chart for counters As shown in Figure 10.7.1, the interrupts are generated by the overflow of their respective counters ("9" changing to "0"). Also, at this time the corresponding interrupt factor flag (ISW10, ISW1) is set to "1." The respective interrupts can be masked separately through the interrupt mask registers (EISW10, EISW1). However, regardless of the setting of the interrupt mask registers, the interrupt factor flags are set to "1" by the overflow of their corresponding counters. 10-6 Seiko Epson Corporation S1C6F016 TECHNICAL MANUAL (Rev. 1.1) 10 STOPWaTCh TiMeR Direct Run and direct laP interrupts When the direct input function is selected, the direct RUN and direct LAP interrupts can be generated. The respective interrupts occur at the rising edge of the internal signal for direct RUN and direct LAP after sampling the direct input signal in the falling edge of 1,024 Hz signal. Also, at this time the corresponding interrupt factor flag (IRUN, ILAP) is set to "1." The respective interrupts can be masked separately through the interrupt mask registers (EIRUN, EILAP). However, regardless of the setting of the interrupt mask registers, the interrupt factor flags are set to "1" by the inputs of the RUN and LAP. The direct RUN and LAP functions use the P00 and P01 ports. Therefore, the direct input interrupt and the P00- P03 inputs interrupt may generate at the same time depending on the interrupt condition setting for the input port P00-P03. Consequently, when using the direct input interrupt, set the interrupt select registers SIP00 and SIP01 to "0" so that the input interrupt does not generate by P00 and P01 inputs. fOSC1/32 (1,024 Hz) SWRST writing EDIR writing EDIR register Direct RUN input SWRUN writing SWRUN register Direct LAP input Counter data 000 001 002 003 004 005 006 098 099 100 101 102 Capture buffer 000 001 002 003 004 005 006 007 993 994 995 996 997 998 999 000 001 002 003 004 005 006 003 005 995 001 007 006 SWD[3:0] reading SWD[7:4] reading SWD[11:8] reading CRNWF 1 Hz interrupt factor flag ISW1 LCURF Direct RUN interrupt Direct LAP interrupt 10 Hz interrupt 1 Hz interrupt Figure 10.7.2 Timing chart for stopwatch timer 10.8 i/O Memory of Stopwatch Timer Table 10.8.1 shows the I/O addresses and the control bits for the stopwatch timer. Table 10.8.1 Control bits of stopwatch timer Address FF16H D3 D2 D1 D0 Register name R/W Default MDCKE SGCKE SWCKe RTCKE FF48H D3 0 (*3) D2 0 (*3) D1 SWDiR D0 eDiR FF49H D3 D2 D1 D0 0 (*3) DKM2 DKM1 DKM0 R/W R/W R/W R/W 0 0 0 0 R - (*2) R - (*2) R/W 0 R/W 0 R - (*2) R/W 0 R/W 0 R/W 0 S1C6F016 Technical Manual (Rev. 1.1) Setting/data 1 1 1 1 Enable Enable Enable Enable 0 0 0 0 Disable Disable Disable Disable - - 1 P00 = Lap P01 = Run/Stop 1 Enable 7 P10-13 6 P10-12 5 P10-11 0 P00 = Run/Stop P01 = Lap 0 Disable - 4 P10 1 P02 3 P02-03,10 0 No mask 2 P02-03 Seiko Epson Corporation Function Integer multiplier clock enable Sound generator clock enable Stopwatch timer clock enable Clock timer clock enable Unused Unused Stopwatch direct input switch Direct input enable Unused Key mask selection 10-7 10 STOPWaTCh TiMeR Address Register name R/W Default Setting/data FF4AH D3 D2 D1 D0 lCuRF CRnWF SWRun SWRST (*3) FF4BH D3 D2 D1 D0 SWD3 SWD2 SWD1 SWD0 R R R R 0 0 0 0 0-9 FF4CH D3 D2 D1 D0 SWD7 SWD6 SWD5 SWD4 R R R R 0 0 0 0 0-9 FF4DH D3 D2 D1 D0 SWD11 SWD10 SWD9 SWD8 R R R R 0 0 0 0 0-9 R 0 R 0 R/W 0 W (Reset) *1: Initial value at initial reset 1 1 1 1 Request Renewal Run Reset *2: Not set in the circuit 0 0 0 0 No No Stop Invalid Function Lap data carry-up request flag Capture renewal flag Stopwatch timer Run/Stop Stopwatch timer reset (writing) Stopwatch timer data BCD (1/1000 sec) Stopwatch timer data BCD (1/100 sec) Stopwatch timer data BCD (1/10 sec) *3: Constantly "0" when being read SWCKe: Stopwatch timer clock enable register (FF16h*D1) Controls the operating clock supply to the stopwatch timer. When "1" is written: On When "0" is written: Off Reading: Valid When "1" is written to SWCKE, the stopwatch timer operating clock is supplied from the clock manager. If it is not necessary to run the stopwatch timer, stop the clock supply by setting SWCKE to "0" to reduce current consumption. At initial reset, this register is set to "0." eDiR: Direct input function enable register (FF48h*D0) Enables the direct input (RUN/LAP) function. When "1" is written: Enabled When "0" is written: Disabled Reading: Valid The direct input function is enabled by writing "1" to EDIR, and then RUN/STOP and LAP control can be done by external key input. When "0" is written, the direct input function is disabled, and the stopwatch timer is controlled by the software only. Further the function switching is actually done by synchronizing with the falling edge of fOSC1/32 (1,024 Hz) after the data is written to this register (after 977 sec maximum). At initial reset, this register is set to "0." SWDiR: Direct input switch register (FF48h*D1) Switches the direct-input key assignment for the P00 and P01 ports. When "1" is written: P00 = LAP, P01 = RUN/STOP When "0" is written: P00 = RUN/STOP, P01 = LAP Reading: Valid The direct-input key assignment is selected using this register. The P00 and P01 port statuses are input to the stopwatch timer as the RUN/STOP and LAP inputs according to this selection. At initial reset, this register is set to "0." DKM[2:0]: Direct key mask select register (FF49h*D[2:0]) Selects a combination of the key inputs for concurrence judgment with RUN and LAP inputs when the direct input function is set. 10-8 Seiko Epson Corporation S1C6F016 TECHNICAL MANUAL (Rev. 1.1) 10 STOPWaTCh TiMeR Table 10.8.2 Key mask selection DKM[2:0] Mask key combination 0H None (at initial reset) 1H P02 2H P02, P03 3H P02, P03, P10 4H P10 5H P10, P11 6H P10, P11, P12 7H P10, P11, P12, P13 When the concurrence is detected, RUN and LAP inputs cannot be accepted until the concurrence is released. At initial reset, this register is set to "0." SWRST: Stopwatch timer reset (FF4ah*D0) This bit resets the stopwatch timer. When "1" is written: Stopwatch timer reset When "0" is written: No operation Reading: Always "0" The stopwatch timer is reset when "1" is written to SWRST. When the stopwatch timer is reset in the RUN status, operation restarts immediately. Also, in the STOP status the reset data is maintained. Since this reset does not affect the capture buffer, the capture buffer data in hold status is not cleared and is maintained. This bit is writeonly, and is always "0" at reading. SWRun: Stopwatch timer Run/STOP (FF4ah*D1) This register controls the RUN/STOP of the stopwatch timer, and the operating status can be monitored by reading this register. When writing data When "1" is written: RUN When "0" is written: STOP The stopwatch timer enters the RUN status when "1" is written to SWRUN, and the STOP status when "0" is written. In the STOP status, the timer data is maintained until the next RUN status or resets timer. Also, when the STOP status changes to the RUN status, the data that was maintained can be used for resuming the count. RUN/ STOP control with this register is valid only when the direct input function is set to disable. When the direct input function is set, it becomes invalid. When reading data When "1" is read: RUN When "0" is read: STOP Reading is always valid regardless of the direct input function setting. "1" is read when the stopwatch timer is in the RUN status, and "0" is read in the STOP status. At initial reset, this register is set to "0." CRnWF: Capture renewal flag (FF4ah*D2) This flag indicates that the content of the capture buffer has been renewed. When "1" is read: Renewed When "0" is read: Not renewed Writing: Invalid The content of the capture buffer is renewed if the LAP key is input when the data held into the capture buffer has not yet been read. Reading SWD[11:8] in that status sets this flag to "1," and the hold status is maintained. Consequently, when data that is held by a LAP input is read, read this flag after reading the SWD[11:8] and check whether the data has been renewed or not. This flag is renewed when SWD[11:8] is read. At initial reset, this flag is set to "0." S1C6F016 Technical Manual (Rev. 1.1) Seiko Epson Corporation 10-9 10 STOPWaTCh TiMeR lCuRF: lap data carry-up request flag (FF4ah*D3) This flag indicates a carry that has been generated to 1 sec-digit when the data is held. Note that this flag is invalid when the direct input function is disabled. When "1" is read: Carry is required When "0" is read: Carry is not required Writing: Invalid If the capture buffer shifts into hold status while the 1 Hz interrupt factor flag ISW1 is set to "1," LCURF is set to "1" to indicate that a carry-up to 1-sec digit is required. When performing a processing such as a LAP input preceding with 1 Hz interrupt processing, read this flag before processing and check whether carry-up is needed or not. This flag is renewed (set/reset) every time the capture buffer shifts into hold status. At initial reset, this flag is set to "0." SWD[3:0]: Stopwatch timer data 1/1,000 sec (FF4Bh) Data (BCD) of the 1/1,000 sec column of the capture buffer can be read out. The hold function of the capture buffer works by reading this data. These 4 bits are read-only, and cannot be used for writing operations. At initial reset, the timer data is set to "0." SWD[7:4]: Stopwatch timer data 1/100 sec (FF4Ch) Data (BCD) of the 1/100 sec column of the capture buffer can be read out. These 4 bits are read-only, and cannot be used for writing operations. At initial reset, the timer data is set to "0." SWD[11:8]: Stopwatch timer data 1/10 sec (FF4Dh) Data (BCD) of the 1/10 sec column of the capture buffer can be read out. These 4 bits are read-only, and cannot be used for writing operations. At initial reset, the timer data is set to "0." Note: Be sure to data reading in the order of SWD[3:0] SWD[7:4] SWD[11:8]. 10.9 Precautions * The interrupt factor flag should be reset after resetting the stopwatch timer. * Be sure to data reading in the order of SWD[3:0] SWD[7:4] SWD[11:8]. * When data that is held by a LAP input is read, read the capture buffer renewal flag CRNWF after reading the SWD[11:8] and check whether the data has been renewed or not. * When performing a processing such as a LAP input preceding with 1 Hz interrupt processing, read the LAP data carry-up request flag LCURF before processing and check whether carry-up is needed or not. 10-10 Seiko Epson Corporation S1C6F016 TECHNICAL MANUAL (Rev. 1.1) 11 PROGRaMMaBle TiMeR 11 Programmable Timer 11.1 Configuration of Programmable Timer The S1C6F016 has built-in two (Ch.A and Ch.B) units of 8 bits x 2-channel programmable timers. Each unit may be configured to 8-bit timer x 2 channels or 16-bit timer x 1 channel with software. Ch.A: Timer 0 and Timer 1 (8 bits x 2 channels) or Timer 0 + 1 (16 bits x 1 channel) Ch.B: Timer 2 and Timer 3 (8 bits x 2 channels) or Timer 2 + 3 (16 bits x 1 channel) Figures 11.1.1 and 11.1.2 show the configuration of the programmable timers. Each timer has an 8-bit down counter and an 8-bit reload data register. The down counter counts the internal clock of which the frequency can be selected with software. Furthermore, Timers 0 and 2 also have an event counter function to count the clock input from the EVIN_A (P10) and EVIN_B (P22) terminals. When the down counter underflows during counting with the specified clock, the timer outputs the underflow and interrupt signals and resets the counter to its initial value. The reload data register is used to set the initial value. The underflow signal of Timer 1 is used as the source clock of the R/F converter and serial interface, this makes it possible to program a flexible R/F converter count clock and the transfer rate of the serial interface. Each timer has an 8-bit compare data register in addition to the above registers. This register is used to store data to be compared with the contents of the down counter. When the timer is set to PWM mode, the timer outputs the compare match signal if the contents between the down counter and the compare data register are matched, and an interrupt occurs at the same time. Also the compare match signal is used with the underflow signal to generate a PWM waveform. The signal generated by the programmable timer can be output from the TOUT_A (P11) or TOUT_B (P23) port terminal. Timer 0 P10 port Timer 0 reset PTRST0 Timer 0 Run/Stop PTRUN0 Timer 0 clock Timer function setting FCSEL_A Pulse polarity setting PLPUL_A Event counter EVCNT_A mode setting PTPS0[3:0] Timer 0 clock selection fOSC1 fOSC3 Clock manager Timer control circuit fOSC1/16 (2,048 Hz) Compare match signal PWM waveform generator Timer 1 clock selection PTPS1[3:0] Timer 1 clock Timer 1 Timer 1 reset PTRST1 Timer 1 Run/Stop PTRUN1 Interrupt request Interrupt control circuit Timer control circuit 16-bit mode MOD16_A selection Compare match signal TOUT_A (P11) P11 port Selector Output control PTOUT_A Output selection CHSEL_A 1/2 PWM waveform generator 1/2 Reload data register RLD0[7:0] 8-bit down counter Comparator Data buffer PTD0[7:0] Compare data register CD0[7:0] PTSEL0 PWM output selection Underflow signal Reload data register RLD1[7:0] Data bus EVIN_A (P10) 8-bit down counter Comparator Data buffer PTD1[7:0] Compare data register CD1[7:0] PTSEL1 PWM output selection Underflow signal R/F converter Serial interface Figure 11.1.1 Configuration of programmable timer Ch.A (Timers 0 and 1) S1C6F016 Technical Manual (Rev. 1.1) Seiko Epson Corporation 11-1 11 PROGRaMMaBle TiMeR Timer 2 P22 port Timer 2 reset PTRST2 Timer 2 Run/Stop PTRUN2 Timer 2 clock Timer function setting FCSEL_B Pulse polarity setting PLPUL_B Event counter EVCNT_B mode setting PTPS2[3:0] Timer 2 clock selection fOSC1 fOSC3 Clock manager Timer control circuit fOSC1/16 (2,048 Hz) Compare match signal PWM waveform generator Timer 3 clock selection PTPS3[3:0] Timer 3 clock Timer 3 Run/Stop PTRUN3 Interrupt request Timer 3 Timer 3 reset PTRST3 Interrupt control circuit Timer control circuit 16-bit mode MOD16_B selection Compare match signal TOUT_B (P23) P23 port Selector Output control PTOUT_B Output selection CHSEL_B 1/2 PWM waveform generator 1/2 Reload data register RLD2[7:0] 8-bit down counter Comparator Data buffer PTD2[7:0] Compare data register CD2[7:0] PTSEL2 PWM output selection Underflow signal Reload data register RLD3[7:0] Data bus EVIN_B (P22) 8-bit down counter Comparator Data buffer PTD3[7:0] Compare data register CD3[7:0] PTSEL3 PWM output selection Underflow signal Figure 11.1.2 Configuration of programmable timer Ch.B (Timers 2 and 3) Notes: * All timer units (Ch.A and Ch.B) have the same functions and structure except the register names, I/O ports used and their signal names. To simplify the explanations, the subsequent sections are described using Ch.A (Timers 0 and 1). The register and signal names have a timer number (0 to 3) or unit (Ch.) name (A and B). They are described using the names for Ch.A (Timers 0 and 1) or "x" (= timer number 0 to 3) except when a specific description is required. Description for Ch.A is applied to Ch.B. Examples: Ch.A Can be replaced with Ch.B. EVCNT_A register Can be replaced with EVCNT_B register. TOUT_A Can be replaced with TOUT_B. Descriptions for Timer 0, Timer 1, and Timer x are applied to other timers Examples: Timer 0 Can be replaced with Timer 2. Timer 1 Can be replaced with Timer 3. Timer x Can be replaced with Timer 0 to Timer 3. PTRUNx register Can be replaced with PTRUN0 to PTRUN3 registers * If the TOUT_A and/or TOUT_B terminals are used to drive an external component that consumes a large amount of current such as a bipolar transistor, design the pattern of traces on the printed circuit board so that the operation of the external component does not affect the IC power supply. Refer to "Precautions on Mounting" in Appendix for more information. 11.2 Controlling Operating Clock The clock manager generates the down-count clock for each timer by dividing the OSC1 or OSC3 clock. Table 11.2.1 lists the 15 count clocks that can be generated by the clock manager, and the clock to be used for each timer can be selected using the count clock frequency select register PTPSx[3:0]. At initial reset, the PTPSx[3:0] register is set to "0H" and the clock supply from the clock manager to the programmable timer is disabled. Before the timer can be run, select a clock to enable the clock supply. 11-2 Seiko Epson Corporation S1C6F016 TECHNICAL MANUAL (Rev. 1.1) 11 PROGRaMMaBle TiMeR Table 11.2.1 Selecting count clock frequency PTPSx[3:0] Timer clock FH fOSC3 EH fOSC3 / 2 DH fOSC3 / 4 CH fOSC3 / 8 BH fOSC3 / 16 AH fOSC3 / 32 9H fOSC3 / 64 8H fOSC3 / 256 7H fOSC1 (32 kHz) 6H fOSC1 / 2 (16 kHz) 5H fOSC1 / 4 (8 kHz) 4H fOSC1 / 16 (2 kHz) 3H fOSC1 / 32 (1 kHz) 2H fOSC1 / 64 (512 Hz) 1H fOSC1 / 256 (128 Hz) 0H Off fOSC1: OSC1 oscillation frequency. ( ) indicates the frequency when fOSC1 = 32 kHz. fOSC3: OSC3 oscillation frequency Stop the clock supply to the timers shown below by setting PTPSx[3:0] to "0H" to reduce current consumption. * Unused timer * Timer used as an event counter that inputs an external clock * Upper 8-bit timer (Timer 1, Timer 3) when the timer unit is used as a 16-bit x 1 channel configuration. 11.3 Basic Counter Operation This section explains the basic count operation when each timer is used as an individual 8-bit timer. Each timer has an 8-bit down counter and an 8-bit reload data register. The reload data register RLDx[7:0] is used to set the initial value to the down counter. By writing "1" to the timer reset bit PTRSTx, the down counter loads the initial value set in the reload register. Therefore, down-counting is executed from the stored initial value by the input clock. The PTRUNx register is provided to control the RUN/STOP for each timer. By writing "1" to this register after presetting the reload data to the down counter, the down counter starts counting down. Writing "0" stops the input count clock and the down counter stops counting. This control (RUN/STOP) does not affect the counter data. The counter maintains its data while stopped, and can restart counting continuing from that data. The counter data can be read via the data buffer PTDx[7:0] in optional timing. However, the counter has the data hold function the same as the clock timer, that holds the high-order data (PTDx[7:4]) when the low-order data (PTDx[3:0]) is read in order to prevent the borrowing operation between low- and high-order reading, therefore be sure to read the low-order data first. The counter reloads the initial value set in the reload data register when an underflow occurs through the count down. It continues counting down from the initial value after reloading. In addition to reloading the counter, this underflow signal controls the interrupt generation and pulse (TOUT_A signal) output. The underflow signal of Timer 1 (Ch.A) is also used to generate the clock to be supplied to the serial interface and R/F converter. S1C6F016 Technical Manual (Rev. 1.1) Seiko Epson Corporation 11-3 11 PROGRaMMaBle TiMeR PTRUNx PTRSTx RLDx[7:0] A6H F3H Count clock PTDx7 PTDx6 PTDx5 PTDx4 PTDx3 PTDx2 PTDx1 PTDx0 Preset Reload & underflow interrupt Figure 11.3.1 Basic operation timing of down counter 11.4 event Counter Mode (Timers 0 and 2) Timer 0 has an event counter function that counts an external clock input to an I/O port. Table 11.4.1 lists the timers and their clock input ports. Table 11.4.1 Event counter clock input port Timer External clock input terminal Control register Timer 0 (Ch.A) EVIN_A (P10) EVCNT_A Timer 2 (Ch.B) EVIN_B (P22) EVCNT_B This function is selected by writing "1" to the counter mode select register EVCNT_A. This sets the corresponding I/O port to input mode and enables the port to send the input signal to Timer 0 as the count clock. At initial reset, EVCNT_A is set to "0" and Timer 0 is configured as a normal timer that counts the internal clock. In the event counter mode, the clock is supplied to Timer 0 from outside the IC, therefore, the settings of the count clock frequency select register PTPS0[3:0] becomes invalid. Count down timing can be selected from either the falling or rising edge of the input clock using the pulse polarity select register PLPUL_A. When "0" is written to the PLPUL_A register, the falling edge is selected, and when "1" is written, the rising edge is selected. The count down timing is shown in Figure 11.4.1. EVCNT_A 1 PTRUN0 PLPUL_A 0 1 EVIN_A input Count data n n-1 n-2 n-3 n-4 n-5 n-6 Figure 11.4.1 Timing chart in event counter mode The event counter mode also allows use of a noise reject function to eliminate noise such as chattering on the external clock (EVIN_A). This function is selected by writing "1" to the timer function select register FCSEL_A. When the noise rejector is enabled, an input pulse width for both low and high levels must be 0.98 msec or more to count reliably. The noise rejector allows the counter to input the clock at the second falling edge of the internal 2,048 Hz signal after changing the input level of the EVIN_A input terminal. Consequently, the pulse width of noise that can reliably be rejected is 0.48 msec or less. (: when fOSC1 = 32.768 kHz) 11-4 Seiko Epson Corporation S1C6F016 TECHNICAL MANUAL (Rev. 1.1) 11 PROGRaMMaBle TiMeR Figure 11.4.2 shows the count down timing with noise rejector. 2,048 Hz *1 EVIN_A input Counter input clock *2 Count data n n-1 n-2 n-3 *1 When fOSC1 = 32.768 kHz *2 When PLPUL_A register is set to "0" Figure 11.4.2 Count down timing with noise rejector The operation of the event counter mode is the same as the normal timer except it uses the EVIN_A input as the clock. Refer to "11.3 Basic Counter Operation" for basic operation and control. 11.5 PWM mode (Timers 0-3) Each timer can generate a PWM waveform. When using this function, write "1" to the PTSELx register to set the timer to PWM mode. The compare data register CDx[7:0] is provided for each timer to control the PWM waveform. In PWM mode, the timer compares data between the down counter and the compare data register and outputs the compare match signal if their contents are matched. At the same time a compare match interrupt occurs. Furthermore, the timer output signal rises with the underflow signal and falls with the compare match signal. As shown in Figure 11.5.1, the cycle and duty ratio of the output signal can be controlled using the reload data register and the compare data register, respectively, to generate a PWM signal. Note, however, the following condition must be met: RLD (reload data) > CD (compare data) and CD 0. If RLD CD, the output signal is fixed at "1" after the first underflow occurs and does not fall to "0." The generated PWM signal can be output from the TOUT_A (P11) or TOUT_B (P23) terminal (see Section 11.8). PWM mode Count clock RLD register 7 CD register 6 Down-counter value 0 7 6 5 4 3 2 1 0 7 6 5 4 3 2 1 0 7 6 5 4 3 2 1 Compare match signal Underflow signal Timer output signal Compare match interrupt Underflow interrupt CD register value Normal mode RLD register value + 1 Compare match signal Underflow signal Timer output signal Underflow interrupt Figure 11.5.1 Generating PWM waveform S1C6F016 Technical Manual (Rev. 1.1) Seiko Epson Corporation 11-5 11 PROGRaMMaBle TiMeR 11.6 16-bit timer mode (Timer 0 + 1, Timer 2 + 3) Timers 0 and 1, and Timers 2 and 3 combinations can be used as 16-bit timers. To use Timers 0 and 1 as a 16-bit timer, write "1" to the Timer 0 16-bit mode select register MOD16_A. The 16-bit timer is configured with Timer 0 for low-order byte and Timer 1 for high-order byte as shown in Figure 11.6.1. EVIN_A (P10) Timer 0 Timer 0 reset PTRST0 Timer 1 reset PTRST1 P10 port Timer 0 Run/Stop PTRUN0 Timer 0 clock fOSC1 fOSC3 Interrupt TOUT_A (P11) PTPS0[3:0] Clock manager Timer 0 clock selection fOSC1/16 (2,048 Hz) Timer function setting FCSEL_A Pulse polarity setting PLPUL_A Event counter EVCNT_A mode setting High-order 8 bits Reload data register RLD1[7:0] 8-bit down counter 8-bit down counter Data buffer PTD0[7:0] Data buffer PTD1[7:0] Comparator Compare match signal Interrupt control circuit Compare data register CD0[7:0] PWM waveform generator P11 port Output control PTOUT_A Timer control circuit Selector Timer 1 Low-order 8 bits Reload data register RLD0[7:0] Data bus Timer 0 + 1 Compare data register CD1[7:0] PTSEL1 PWM output selection 1/2 Underflow signal Figure 11.6.1 Configuration of 16-bit timer (Timer 0 + 1) In 16-bit timer mode, the Timer 0 register settings are effective for timer RUN/STOP control and count clock frequency selection. The event counter function can also be used. Timer 1 uses the Timer 0 underflow signal as the count clock, therefore, the Timer 1 RUN/STOP control and count clock frequency select registers become invalid. However, the PWM output function must be controlled using the Timer 1 control register. Timer 1 output signal is automatically selected for the TOUT_A output (the TOUT_A output select register is ineffective). The reload data must be preset to Timer 0 and Timer 1 separately using each PTRSTx register. The counter data of a 16-bit timer must be read from the low-order 4 bits. In 16-bit timer mode, the high-order data (PTD0[7:4], PTD1[3:0], PTD1[7:4]) is latched by reading the low-order 4 bits (PTD0[3:0]). The counter keeps counting. However, the latched high-order data is maintained until the next reading of low-order data. Therefore, after the low-order 4-bit data (PTD0[3:0]) is read, the high-order data (PTD0[7:4], PTD1[3:0], PTD1[7:4]) can be read regardless of the order for reading. If data other than the low-order 4 bits (PTD0[3:0]) is read first, the hold function is not activated. In this case, the correct counter data cannot be read. The description above is applied when Timers 2 and 3 are used as a 16-bit timer. 11.7 interrupt Function The programmable timer can generate interrupts from the underflow and compare match signals of each timer. See Figures 11.3.1 and 11.5.1 for the interrupt timing. Note: The compare match interrupt can be generated only when the timer is set to PWM mode. The underflow and compare match signals set the corresponding interrupt factor flag IPTx and ICTCx to "1," and an interrupt is generated. The interrupt can also be masked by setting the corresponding interrupt mask registers EIPTx and EICTCx. However, the interrupt factor flag is set to "1" by an underflow/compare match of the corresponding timer regardless of the interrupt mask register setting. When Timers 0 and 1 are used as a 16-bit timer, an interrupt is generated by an underflow of Timer 1. In this case, IPT0 is not set to "1" by a Timer 0 underflow. The compare match interrupt uses ICTC1 of Timer 1. The same applies when other timers are used as a 16-bit timer. 11-6 Seiko Epson Corporation S1C6F016 TECHNICAL MANUAL (Rev. 1.1) 11 PROGRaMMaBle TiMeR 11.8 TOuT Output Control The programmable timer Ch.A (Timers 0 and 1) can generate the TOUT_A signal from the timer underflow and compare match signals. The TOUT_A signal is generated by dividing the underflow signal by 2 in normal mode. In PWM mode, the PWM signal generated as described above is output as the TOUT_A signal. Table 11.8.1 TOUT outputs and control registers Output control register Output select register PTOUT_A CHSEL_A = "0" CHSEL_A = "1" PTOUT_B CHSEL_B = "0" CHSEL_B = "1" Output terminal TOUT_A (P11) TOUT_B (P23) Output timer Timer 0 Timer 1 Timer 2 Timer 3 It is possible to select either Timer 0 or Timer 1 output to be used by the TOUT output select register CHSEL_A. In 16-bit timer mode, Timer 1 is always selected for generating the TOUT_A signal regardless of how CHSEL_A is set. The TOUT signal generated by each timer can be output from the TOUT_A (P11) or TOUT_B (P23) terminal to supply a clock to an external device. The output of the TOUT_A signal is controlled by the PTOUT_A register. When "1" is written to the PTOUT_A register, the TOUT_A signal is output from the corresponding I/O port terminal. When TOUT output is enabled, the I/O port is automatically set to output mode and it outputs the TOUT signal sent from the timer. The I/O control register (IOC11/IOC23) and the data register (P11/P23) are ineffective. When PTOUT_A is set to "0," the I/O port control registers become effective. Since the TOUT_A signal is generated asynchronously from the PTOUT_A register, a hazard within 1/2 cycle is generated when the signal is turned on and off by setting the register. Figure 11.8.1 shows the output waveform of the TOUT_A signal. 0 PTOUT_A 1 TOUT_A output Figure 11.8.1 Output waveform of the TOUT_A signal Ch.B can be controlled the same as above to output the TOUT_B signal. 11.9 Clock Output to Serial interface and R/F Converter The signal that is made from underflows of Timer 1 by dividing them by 2, can be used as the clock source for the serial interface and R/F converter. Timer 1 always outputs the clock to the serial interface and R/F converter by setting Timer 1 into RUN state (PTRUN1 = "1"). It is not necessary to control with the PTOUT_A register. PTRUN1 Timer 1 underflow Source clock for serial I/F and R/F converter Figure 11.9.1 Clock output to serial interface and R/F converter A setting value for the RLD1x register according to a transfer rate of the serial interface is calculated by the following expression: fCNT1 RLD1x = ---------- -1 2*bps fCNT1: Timer 1 count clock frequency set by the PTPS1 register (See Table 11.2.1.) bps: Transfer rate (00H can be set to RLD1x) Be aware that the maximum clock frequency for the serial interface is limited to 1 MHz when OSC3 is used as the clock source. S1C6F016 Technical Manual (Rev. 1.1) Seiko Epson Corporation 11-7 11 PROGRaMMaBle TiMeR 11.10 i/O Memory of Programmable Timer Table 11.10.1 shows the I/O addresses and the control bits for the programmable timer. Table 11.10.1 Control bits of programmable timer Address Register name R/W Default Setting/data Function FF18H D3 D2 D1 D0 PTPS03 PTPS02 PTPS01 PTPS00 R/W R/W R/W R/W 0 0 0 0 F E D C f3 f3/2 f3/4 f3/8 B A 9 8 f3/16 f3/32 f3/64 f3/256 7 6 5 4 f1 f1/2 f1/4 f1/16 3 2 1 0 f1/32 Programmable timer 0 count clock frequency f1/64 selection (f1 = fOSC1, f3 = fOSC3) f1/256 Off FF19H D3 D2 D1 D0 PTPS13 PTPS12 PTPS11 PTPS10 R/W R/W R/W R/W 0 0 0 0 F E D C f3 f3/2 f3/4 f3/8 B A 9 8 f3/16 f3/32 f3/64 f3/256 7 6 5 4 f1 f1/2 f1/4 f1/16 3 2 1 0 f1/32 Programmable timer 1 count clock frequency f1/64 selection (f1 = fOSC1, f3 = fOSC3) f1/256 Off FF1AH D3 D2 D1 D0 PTPS23 PTPS22 PTPS21 PTPS20 R/W R/W R/W R/W 0 0 0 0 F E D C f3 f3/2 f3/4 f3/8 B A 9 8 f3/16 f3/32 f3/64 f3/256 7 6 5 4 f1 f1/2 f1/4 f1/16 3 2 1 0 f1/32 Programmable timer 2 count clock frequency f1/64 selection (f1 = fOSC1, f3 = fOSC3) f1/256 Off FF1BH D3 D2 D1 D0 PTPS33 PTPS32 PTPS31 PTPS30 R/W R/W R/W R/W 0 0 0 0 F E D C f3 f3/2 f3/4 f3/8 B A 9 8 f3/16 f3/32 f3/64 f3/256 7 6 5 4 f1 f1/2 f1/4 f1/16 3 2 1 0 f1/32 Programmable timer 3 count clock frequency f1/64 selection (f1 = fOSC1, f3 = fOSC3) f1/256 Off FF80H D3 D2 D1 D0 MOD16_a eVCnT_a FCSel_a PlPul_a R/W R/W R/W R/W 0 0 0 0 1 1 1 1 16 bits Event counter With noise reject (positive) 0 0 0 0 8 bits Timer No noise reject (negative) PTM0-1 16-bit mode selection PTM0 counter mode selection PTM0 function selection (for event counter mode) PTM0 pulse polarity selection (event counter mode) FF81H D3 D2 D1 D0 PTSel1 PTSel0 ChSel_a PTOuT_a R/W R/W R/W R/W 0 0 0 0 1 1 1 1 PWM PWM Timer 1 On 0 0 0 0 Normal Normal Timer 0 Off Programmable timer 1 PWM output selection Programmable timer 0 PWM output selection PTM0-1 TOUT_A output selection PTM0-1 TOUT_A output control FF82H D3 D2 D1 D0 PTRST1 (*3) PTRun1 PTRST0 (*3) PTRun0 W - (*2) R/W 0 W - (*2) R/W 0 1 1 1 1 Reset Run Reset Run 0 0 0 0 Invalid Stop Invalid Stop Programmable timer 1 reset (reload) Programmable timer 1 Run/Stop Programmable timer 0 reset (reload) Programmable timer 0 Run/Stop FF84H D3 D2 D1 D0 RlD03 RlD02 RlD01 RlD00 R/W R/W R/W R/W 0 0 0 0 0H-FH FF85H D3 D2 D1 D0 RlD07 RlD06 RlD05 RlD04 R/W R/W R/W R/W 0 0 0 0 0H-FH FF86H D3 D2 D1 D0 RlD13 RlD12 RlD11 RlD10 R/W R/W R/W R/W 0 0 0 0 0H-FH FF87H D3 D2 D1 D0 RlD17 RlD16 RlD15 RlD14 R/W R/W R/W R/W 0 0 0 0 FF88H D3 D2 D1 D0 PTD03 PTD02 PTD01 PTD00 R R R R 0 0 0 0 0H-FH FF89H D3 D2 D1 D0 PTD07 PTD06 PTD05 PTD04 R R R R 0 0 0 0 0H-FH FF8AH D3 D2 D1 D0 PTD13 PTD12 PTD11 PTD10 R R R R 0 0 0 0 0H-FH FF8BH D3 D2 D1 D0 PTD17 PTD16 PTD15 PTD14 R R R R 0 0 0 0 0H-FH 0H-FH 11-8 Seiko Epson Corporation Programmable timer 0 reload data (low-order 4 bits) RLD00 = LSB Programmable timer 0 reload data (high-order 4 bits) RLD07 = MSB Programmable timer 1 reload data (low-order 4 bits) RLD10 = LSB Programmable timer 1 reload data (high-order 4 bits) RLD17 = MSB Programmable timer 0 data (low-order 4 bits) PTD00 = LSB Programmable timer 0 data (high-order 4 bits) PTD07 = MSB Programmable timer 1 data (low-order 4 bits) PTD10 = LSB Programmable timer 1 data (high-order 4 bits) PTD17 = MSB S1C6F016 TECHNICAL MANUAL (Rev. 1.1) 11 PROGRaMMaBle TiMeR Address Register name R/W Default Setting/data Function FF8CH D3 D2 D1 D0 CD03 CD02 CD01 CD00 R/W R/W R/W R/W 0 0 0 0 FF8DH D3 D2 D1 D0 CD07 CD06 CD05 CD04 R/W R/W R/W R/W 0 0 0 0 0H-FH FF8EH D3 D2 D1 D0 CD13 CD12 CD11 CD10 R/W R/W R/W R/W 0 0 0 0 0H-FH FF8FH D3 D2 D1 D0 CD17 CD16 CD15 CD14 R/W R/W R/W R/W 0 0 0 0 0H-FH FF90H D3 D2 D1 D0 MOD16_B eVCnT_B FCSel_B PlPul_B R/W R/W R/W R/W 0 0 0 0 1 1 1 1 16 bits Event counter With noise reject (positive) 0 0 0 0 8 bits Timer No noise reject (negative) PTM2-3 16-bit mode selection PTM2 counter mode selection PTM2 function selection (for event counter mode) PTM2 pulse polarity selection (event counter mode) FF91H D3 D2 D1 D0 PTSel3 PTSel2 ChSel_B PTOuT_B R/W R/W R/W R/W 0 0 0 0 1 1 1 1 PWM PWM Timer 3 On 0 0 0 0 Normal Normal Timer 2 Off Programmable timer 3 PWM output selection Programmable timer 2 PWM output selection PTM2-3 TOUT_B output selection PTM2-3 TOUT_B output control FF92H D3 D2 D1 D0 PTRST3 (*3) PTRun3 PTRST2 (*3) PTRun2 W - (*2) R/W 0 W - (*2) R/W 0 1 1 1 1 Reset Run Reset Run 0 0 0 0 Invalid Stop Invalid Stop Programmable timer 3 reset (reload) Programmable timer 3 Run/Stop Programmable timer 2 reset (reload) Programmable timer 2 Run/Stop FF94H D3 D2 D1 D0 RlD23 RlD22 RlD21 RlD20 R/W R/W R/W R/W 0 0 0 0 0H-FH FF95H D3 D2 D1 D0 RlD27 RlD26 RlD25 RlD24 R/W R/W R/W R/W 0 0 0 0 0H-FH FF96H D3 D2 D1 D0 RlD33 RlD32 RlD31 RlD30 R/W R/W R/W R/W 0 0 0 0 0H-FH FF97H D3 D2 D1 D0 RlD37 RlD36 RlD35 RlD34 R/W R/W R/W R/W 0 0 0 0 0H-FH FF98H D3 D2 D1 D0 PTD23 PTD22 PTD21 PTD20 R R R R 0 0 0 0 0H-FH FF99H D3 D2 D1 D0 PTD27 PTD26 PTD25 PTD24 R R R R 0 0 0 0 0H-FH FF9AH D3 D2 D1 D0 PTD33 PTD32 PTD31 PTD30 R R R R 0 0 0 0 0H-FH FF9BH D3 D2 D1 D0 PTD37 PTD36 PTD35 PTD34 R R R R 0 0 0 0 0H-FH FF9CH D3 D2 D1 D0 CD23 CD22 CD21 CD20 R/W R/W R/W R/W 0 0 0 0 0H-FH S1C6F016 Technical Manual (Rev. 1.1) 0H-FH Seiko Epson Corporation Programmable timer 0 compare data (high-order 4 bits) CD00 = LSB Programmable timer 0 compare data (high-order 4 bits) CD07 = MSB Programmable timer 1 compare data (low-order 4 bits) CD10 = LSB Programmable timer 1 compare data (high-order 4 bits) CD17 = MSB Programmable timer 2 reload data (low-order 4 bits) RLD20 = LSB Programmable timer 2 reload data (high-order 4 bits) RLD27 = MSB Programmable timer 3 reload data (low-order 4 bits) RLD30 = LSB Programmable timer 3 reload data (high-order 4 bits) RLD37 = MSB Programmable timer 2 data (low-order 4 bits) PTD20 = LSB Programmable timer 2 data (high-order 4 bits) PTD27 = MSB Programmable timer 3 data (low-order 4 bits) PTD30 = LSB Programmable timer 3 data (high-order 4 bits) PTD37 =MSB Programmable timer 2 compare data (low-order 4 bits) CD20 = LSB 11-9 11 PROGRaMMaBle TiMeR Address Register name R/W Default Setting/data FF9DH D3 D2 D1 D0 CD27 CD26 CD25 CD24 R/W R/W R/W R/W 0 0 0 0 FF9EH D3 D2 D1 D0 CD33 CD32 CD31 CD30 R/W R/W R/W R/W 0 0 0 0 0H-FH FF9FH D3 D2 D1 D0 CD37 CD36 CD35 CD34 R/W R/W R/W R/W 0 0 0 0 0H-FH *1: Initial value at initial reset 0H-FH *2: Not set in the circuit Function Programmable timer 2 compare data (high-order 4 bits) CD27 = MSB Programmable timer 3 compare data (low-order 4 bits) CD30 = LSB Programmable timer 3 compare data (high-order 4 bits) CD37 = MSB *3: Constantly "0" when being read PTPS0[3:0]: Timer 0 count clock frequency select register (FF18h) PTPS1[3:0]: Timer 1 count clock frequency select register (FF19h) PTPS2[3:0]: Timer 2 count clock frequency select register (FF1ah) PTPS3[3:0]: Timer 3 count clock frequency select register (FF1Bh) Selects the count clock frequency for each timer. Table 11.10.2 Selecting count clock frequency PTPSx[3:0] Timer clock FH fOSC3 EH fOSC3 / 2 DH fOSC3 / 4 CH fOSC3 / 8 BH fOSC3 / 16 AH fOSC3 / 32 9H fOSC3 / 64 8H fOSC3 / 256 7H fOSC1 (32 kHz) 6H fOSC1 / 2 (16 kHz) 5H fOSC1 / 4 (8 kHz) 4H fOSC1 / 16 (2 kHz) 3H fOSC1 / 32 (1 kHz) 2H fOSC1 / 64 (512 Hz) 1H fOSC1 / 256 (128 Hz) 0H Off fOSC1: OSC1 oscillation frequency. ( ) indicates the frequency when fOSC1 = 32 kHz. fOSC3: OSC3 oscillation frequency The clock manager generates the down-count clock for each timer by dividing the OSC1 or OSC3 clock. Table 11.2.1 lists the 15 count clocks that can be generated by the clock manager, and the clock to be used for each timer can be selected using PTPSx[3:0]. At initial reset, the PTPSx[3:0] register is set to "0H" and the clock supply from the clock manager to the programmable timer is disabled. Before the timer can be run, select a clock to enable the clock supply. Stop the clock supply to the timers shown below by setting PTPSx[3:0] to "0H" to reduce current consumption. * Unused timer * Timer used as an event counter that inputs an external clock * Upper 8-bit timer (Timer 1, Timer 3) when the timer unit is used as 16-bit x 1 channel configuration. At initial reset, these registers are set to "0." PlPul_a: Timer 0 pulse polarity select register (FF80h*D0) PlPul_B: Timer 2 pulse polarity select register (FF90h*D0) Selects the count pulse polarity in the event counter mode. When "1" is written: Rising edge When "0" is written: Falling edge Reading: Valid 11-10 Seiko Epson Corporation S1C6F016 TECHNICAL MANUAL (Rev. 1.1) 11 PROGRaMMaBle TiMeR The count timing in the event counter mode is selected from either the falling edge of the external clock input to the EVIN_A (P10) and EVIN_B (P22) terminals or the rising edge. When "0" is written to these registers, the falling edge is selected and when "1" is written, the rising edge is selected. These registers are effective only when the timer is used in the event counter mode. At initial reset, these registers are set to "0." FCSel_a: Timer 0 function select register (FF80h*D1) FCSel_B: Timer 2 function select register (FF90h*D1) Selects whether the noise rejector of the clock input circuit will be used or not in the event counter mode. When "1" is written: With noise rejector When "0" is written: Without noise rejector Reading: Valid When "1" is written to these registers, the noise rejector is used and counting is done by an external clock (input from EVIN_A or EVIN_B) with 0.98 msec* or more pulse width. The noise rejector allows the counter to input the clock at the second falling edge of the internal 2,048 Hz* signal after changing the input level of the I/O port terminal. Consequently, the pulse width of noise that can reliably be rejected is 0.48 msec* or less. (: When fOSC1 = 32.768 kHz) When "0" is written to these registers, the noise rejector is not used and the counting is done directly by an external clock input to the EVIN_A (P10) or EVIN_B (P22) terminal. These registers are effective only when the timer is used in the event counter mode. At initial reset, these registers are set to "0." eVCnT_a: Timer 0 counter mode select register (FF80h*D2) eVCnT_B: Timer 2 counter mode select register (FF90h*D2) Selects the counter mode for each timer. When "1" is written: Event counter mode When "0" is written: Timer mode Reading: Valid The counter modes for Timers 0 and 2 are selected from either the event counter mode or timer mode. When "1" is written to these registers, event counter mode is selected. In this mode, Timers 0 and 2 count the external clock input from the EVIN_A (P10) and EVIN_B (P22) terminals, respectively. When "0" is written, timer mode is selected. In this mode, the timer counts the internal clock selected by the PTPSx[3:0] register. This selection is effective even when these timer is used in 16-bit timer mode. At initial reset, these registers are set to "0." MOD16_a: Timer 0-1 16-bit timer mode select register (FF80h*D3) MOD16_B: Timer 2-3 16-bit timer mode select register (FF90h*D3) Selects 8-bit or 16-bit timer mode. When "1" is written: 16-bit timer mode When "0" is written: 8-bit timer mode Reading: Valid These registers are used to select whether Timers 0 and 1, and Timers 2 and 3 are used as two channels of independent 8-bit timers or one channel of combined 16-bit timer. When "0" is written to these registers, the timers are set to 8-bit timer mode. When "1" is written, the timers are set to 16-bit timer mode. For example, when Timers 0 and 1 are used in 16-bit timer mode, Timer 1 operates with the Timer 0 underflow signal as the count clock (both timer mode and event counter mode). In 16-bit timer mode, the Timer 0 register settings are effective for timer RUN/STOP control and count clock frequency selection (Timer 1 registers are ineffective). However, the PWM output function must be controlled using the Timer 1 control register. The reload data must be preset to Timer 0 and Timer 1 separately using each PTRSTx register. These operations are the same when Timers 2 and 3 are used as a 16-bit timer. At initial reset, these registers are set to "0." S1C6F016 Technical Manual (Rev. 1.1) Seiko Epson Corporation 11-11 11 PROGRaMMaBle TiMeR PTOuT_a: TOuT_a output control register (FF81h*D0) PTOuT_B: TOuT_B output control register (FF91h*D0) Controls TOUT signal outputs. When "1" is written: TOUT output On When "0" is written: TOUT output Off Reading: Valid When "1" is written to the register, the corresponding TOUT_A/TOUT_B signal is output from the P11/P23 terminal. When TOUT output is enabled, the I/O port is automatically set to output mode and it outputs the TOUT signal sent from the timer. The I/O control register (IOC11/IOC23) and the data register (P11/P23) are ineffective. When this register is set to "0," the I/O port control registers become effective. At initial reset, these registers are set to "0." ChSel_a: TOuT_a output select register (FF81h*D1) ChSel_B: TOuT_B output select register (FF91h*D1) Selects the timer used for TOUT signal output. When "1" is written: Low-order Timer (Timer 1/Timer 3) When "0" is written: High-order Timer (Timer 0/Timer 2) Reading: Valid These registers are used to select whether the low-order timer (Timer 0/Timer 2) output is used as the TOUT signal or the high-order timer (Timer 1/Timer 3) output is used. When "0" is written to the register, the low-order timer output is selected. When "1" is written, the high-order timer output is selected. In 16-bit timer mode, the high-order timer output is always selected regardless of how these registers are set. At initial reset, these registers are set to "0." PTSel0: Timer 0 PWM mode select register (FF81h*D2) PTSel1: Timer 1 PWM mode select register (FF81h*D3) PTSel2: Timer 2 PWM mode select register (FF91h*D2) PTSel3: Timer 3 PWM mode select register (FF91h*D3) Sets Timer x for PWM output. When "1" is written: PWM output When "0" is written: Normal output Reading: Valid When "1" is written to the PTSELx, the compare data register becomes effective and PWM waveform is generated using the underflow and compare match signals. When "0" is written, the timer outputs the normal clock generated from the underflow signal. In 16-bit timer mode, the PTSELx register for the low-order timer (Timer 0/Timer 2) is ineffective. At initial reset, these registers are set to "0." PTRun0: Timer 0 Run/STOP control register (FF82h*D0) PTRun1: Timer 1 Run/STOP control register (FF82h*D2) PTRun2: Timer 2 Run/STOP control register (FF92h*D0) PTRun3: Timer 3 Run/STOP control register (FF92h*D2) Controls the RUN/STOP of the counter. When "1" is written: RUN When "0" is written: STOP Reading: Valid The counter in Timer x starts counting down by writing "1" to the PTRUNx register and stops by writing "0." In STOP status, the counter data is maintained until the counter is reset or is set in the next RUN status. When STOP status changes to RUN status, the data that has been maintained can be used for resuming the count. In 16-bit timer mode, the PTRUNx register for the high-order timer (Timer 1/Timer 3) is ineffective. At initial reset, these registers are set to "0." 11-12 Seiko Epson Corporation S1C6F016 TECHNICAL MANUAL (Rev. 1.1) 11 PROGRaMMaBle TiMeR PTRST0: Timer 0 reset (reload) (FF82h*D1) PTRST1: Timer 1 reset (reload) (FF82h*D3) PTRST2: Timer 2 reset (reload) (FF92h*D1) PTRST3: Timer 3 reset (reload) (FF92h*D3) Resets the timer and preset reload data to the counter. When "1" is written: Reset When "0" is written: No operation Reading: Always "0" By writing "1" to PTRSTx, the reload data in the reload register RLDx[7:0] is preset to the counter in Timer x. When the counter is preset in the RUN status, the counter restarts immediately after presetting. In the case of STOP status, the reload data is preset to the counter and is maintained. No operation results when "0" is written. The PTRSTx registers are all effective even in 16-bit timer mode, and reload data must be preset to both the high-order timer (Timer 1/Timer 3) and the low-order timer (Timer 0/Timer 2) separately. Since these bits are exclusively for writing, always set to "0" during reading. RlD0[7:0]: Timer 0 reload data register (FF85h, FF84h) RlD1[7:0]: Timer 1 reload data register (FF87h, FF86h) RlD2[7:0]: Timer 2 reload data register (FF95h, FF94h) RlD3[7:0]: Timer 3 reload data register (FF97h, FF96h) Sets the initial value for the counter. The reload data written in these registers are loaded to the respective counters. The counter counts down using the data as the initial value for counting. Reload data is loaded to the counter when the counter is reset by writing "1" to the PTRSTx register, or when counter underflow occurs. At initial reset, these registers are set to "00H." PTD0[7:0]: Timer 0 counter data (FF89h, FF88h) PTD1[7:0]: Timer 1 counter data (FF8Bh, FF8ah) PTD2[7:0]: Timer 2 counter data (FF99h, FF98h) PTD3[7:0]: Timer 3 counter data (FF9Bh, FF9ah) Count data in the programmable timer can be read from these latches. The low-order 4 bits of the count data in Timer x can be read from PTDx[3:0], and the high-order data can be read from PTDx[7:4]. Since the high-order 4 bits are held by reading the low-order 4 bits, be sure to read the low-order 4 bits first. In 16-bit timer mode, the high-order 12 bits are held by reading the low-order 4 bits, be sure to read the low-order 4 bits first. Since these latches are exclusively for reading, the writing operation is invalid. At initial reset, these counter data are set to "00H." CD0[7:0]: Timer 0 compare data register (FF8Dh, FF8Ch) CD1[7:0]: Timer 1 compare data register (FF8Fh, FF8eh) CD2[7:0]: Timer 2 compare data register (FF9Dh, FF9Ch) CD3[7:0]: Timer 3 compare data register (FF9Fh, FF9eh) Sets the compare data for PWM output. When the timer is set to PWM mode, the compare data set in this register is compared with the counter data and outputs the compare match signal if they are matched. The compare match signal is used for generating an interrupt and controlling the duty ratio of the PWM waveform. At initial reset, these registers are set to "00H." 11.11 Precautions * When reading counter data, be sure to read the low-order 4 bits (PTDx[3:0]) first. The high-order 4 bits (PTDx[7:4]) are latched when the low-order 4 bits are read and they are held until the next reading of the low-order 4 bits. In 16-bit timer mode, the high-order 12 bits are held by reading the low-order 4 bits, be sure to read the low-order 4 bits first. When the CPU is running with the OSC1 clock and the programmable timer is running with the OSC3 clock, stop the timer before reading the counter data to read the proper data. S1C6F016 Technical Manual (Rev. 1.1) Seiko Epson Corporation 11-13 11 PROGRaMMaBle TiMeR * The programmable timer actually enters RUN/STOP status in synchronization with the falling edge of the input clock after writing to the PTRUNx register. Consequently, when "0" is written to the PTRUNx register, the timer enters STOP status at the point where the counter is decremented (-1). The PTRUNx register maintains "1" for reading until the timer actually stops. Count clock PTRUNx (RD) PTRUNx (WR) PTDx[7:0] "1" (RUN) writing 42H "0" (STOP) writing 41H 40H 3FH 3EH 3DH Figure 11.11.1 Timing chart for RUN/STOP control (timer mode) In event counter mode, the timer starts counting at the first event clock. Count clock PTRUNx (RD) PTRUNx (WR) PTDx[7:0] "1" (RUN) writing "0" (STOP) writing 42H 41H 40H 3FH 3EH 3DH Figure 11.11.2 Timing chart for RUN/STOP control (event counter mode) * Since the TOUT_A and TOUT_B signals are generated asynchronously from the PTOUT_A and PTOUT_B registers, a hazard within 1/2 cycle is generated when the signal is turned on and off by setting the register. * When the OSC3 oscillation clock is selected for the clock source, it is necessary to turn the OSC3 oscillation on, prior to using the programmable timer. However the OSC3 oscillation circuit requires several tens of sec to several tens of msec after turning the circuit on until the oscillation stabilizes. Therefore, allow an adequate interval from turning the OSC3 oscillation circuit on to starting the programmable timer. Refer to the "Oscillation Circuit and Clock Control" chapter, for the control and notes of the OSC3 oscillation circuit. At initial reset, the OSC3 oscillation circuit is set in off state. * For the reason below, pay attention to the reload data write timing when changing the interval of the programmable timer interrupts while the programmable timer is running. The programmable timer counts down at the falling edge of the input clock and at the same time it generates an interrupt if the counter underflows. Then it starts loading the reload data to the counter and the counter data is determined at the next rising edge of the input clock (period shown in as in the figure). Count clock Counter data 03H 02H 01H 00H (continuous mode) Underflow (interrupt is generated) 25H 24H (Reload data = 25H) Counter data is determined by reloading. Figure 11.11.3 Reload timing for programmable timer To avoid improper reloading, do not rewrite the reload data after an interrupt occurs until the counter data is determined including the reloading period . Be especially careful when using the OSC1 (low-speed clock) as the clock source of the programmable timer and the CPU is operating with the OSC3 (high-speed clock). * The programmable timer count clock does not synch with the CPU clock. Therefore, the correct value may not be obtained depending on the count data read and count-up timings. To avoid this problem, the programmable timer count data should be read by one of the procedures shown below. - Read the count data twice and verify if there is any difference between them. - Temporarily stop the programmable timer when the counter data is read to obtain proper data. 11-14 Seiko Epson Corporation S1C6F016 TECHNICAL MANUAL (Rev. 1.1) 12 i/O PORTS 12 I/O Ports 12.1 Configuration of i/O Ports The S1C6F016 is equipped with 24 bits of I/O ports (P00-P03, P10-P13, P20-P23, P30-P33, P40-P43, and P50- P53) in which the input/output direction can be switched with software. Figure 12.1.1 shows the structure of an I/O port. VDD Pull-down control register (PUL) Data bus I/O control register (IOC) Data register *1 *2 Pxx Mask option Input control *1: During output mode *2: During input mode VSS Figure 12.1.1 Structure of I/O port Note: If an output terminal (including a special output terminal) of this IC is used to drive an external component that consumes a large amount of current such as a bipolar transistor, design the pattern of traces on the printed circuit board so that the operation of the external component does not affect the IC power supply. Refer to "Precautions on Mounting" in Appendix, for more information. Each I/O port terminal provides an internal pull-down resistor. The custom mask option model allows selection of the pull-down resistor to be connected or disconnected in 1-bit units. (The standard mask option models come with or without pull-down resistors.) When "Use" is selected by mask option, the port suits input from the push switch, key matrix, and so forth. When "Not use" is selected, the port can be used for slide switch input and interfacing with other LSIs. The P00 and P01 I/O ports can also be used as the Run/Stop and Lap direct inputs for the stopwatch timer. The P10 and P23 ports can also be used as the event counter inputs for the programmable timer. The I/O port terminals P11-P13 and P23 are shared with the special output (TOUT_A, BZ, FOUT, TOUT_B) terminals, P30-P33 are shared with the serial interface input/output terminals, and P50-P53 are shared with the R/F converter input/output terminals. The software can select the function to be used. At initial reset, these terminals are all set to the I/O port. Table 12.1.1 shows the setting of the input/output terminals by function selection. S1C6F016 Technical Manual (Rev. 1.1) Seiko Epson Corporation 12-1 12 i/O PORTS Table 12.1.1 Function settings of input/output terminals Terminal name Terminal status at initial reset P00 P01 P02 P03 P10 P11 P12 P13 P20-P21 P22 P23 P30 P31 P32 P33 P40-P43 P50 P51 P52 P53 P00 (IN & PD*) P01 (IN & PD*) P02 (IN & PD*) P03 (IN & PD*) P10 (IN & PD*) P11 (IN & PD*) P12 (IN & PD*) P13 (IN & PD*) P20-P21 (IN & PD*) P22 (IN & PD*) P23 (IN & PD*) P30 (IN & PD*) P31 (IN & PD*) P32 (IN & PD*) P33 (IN & PD*) P40-P43 (IN & PD*) P50 (IN & PD*) P51 (IN & PD*) P52 (IN & PD*) P53 (IN & PD*) When special outputs/peripheral functions are used (selected by software) Special output Serial I/F Stopwatch R/F direct TOUT FOUT BZ Master Slave converter input RUN/STOP LAP Event counter EVIN_A TOUT_A BZ FOUT EVIN_B TOUT_B SCLK(O) SOUT(O) SIN(I) SCLK(I) SOUT(O) SIN(I) SRDY(O)/SS(I) RFOUT SEN0 REF0 RFIN0 * IN & PD (Input with pulled down): When "Pull-Down Used" is selected by mask option (high impedance when "PullDown Not Used" is selected) When these ports are used as I/O ports, the ports can be set to either input mode or output mode individually (in 1-bit units). The mode can be set by writing data to the I/O control registers. When the special output or peripheral function is used, the input/output direction of the port is automatically configured by switching the terminal function and the I/O control registers becomes ineffective. For switching the terminal function and input/output control, refer to respective peripheral circuit chapter. Note: Before the port function is configured, the circuit that uses the port (e.g. input interrupt, multiple key entry reset, serial interface, R/F converter, event counter input, direct RUN/LAP input for stopwatch) must be disabled. 12.2 Mask Option Custom mask option The output specification of each I/O port during output mode can be selected from either complementary output or P-channel open drain output by mask option. This selection can be done in 1-bit units. When P-channel open drain output is selected, do not apply a voltage exceeding the power supply voltage to the port. The mask option also allows selection of whether the pull-down resistor is used or not during input mode. This selection can be done in 1-bit units. When "Not use" is selected, take care that the floating status does not occur during input mode. The pull-down resistor for input mode and output specification (complementary output or P-channel open drain output) selected by mask option are effective even when I/O ports are used for input/output of the serial interface and R/F converter. The I/O ports P20-P53 input/output terminals are shared with the SEG terminals. This mask option allows selection of whether each of these terminals is used for the I/O port or the SEG output. Refer to "Mask Option" in the "LCD Driver" chapter for details. Standard mask option Type B and Type e The output specification for output mode is fixed at complementary output. The internal pull-down resistor is connected to all the I/O ports. 12-2 Seiko Epson Corporation S1C6F016 TECHNICAL MANUAL (Rev. 1.1) 12 i/O PORTS Standard mask option Type G The output specification for output mode is fixed at complementary output. The internal pull-down resistor is connected to the I/O ports except for P10 and P11. 12.3 i/O Control Registers and input/Output Mode The I/O ports can be placed into input or output mode by writing data to the corresponding I/O control registers IOCxx. To set a port to input mode, write "0" to the I/O control register. When an I/O port is set to input mode, it becomes high impedance status and works as an input port. However, when the pull-down explained in Section 12.5 has been enabled by software, the input line is pulled down only during this input mode. To set a port to output mode, write "1" to the I/O control register. When an I/O port is set to output mode, it works as an output port. The port outputs a high level (VDD) when the port output data is "1," and a low level (VSS) when the port output data is "0." The I/O ports allow software to read data even in output mode. In this case, the data register value is read out. At initial reset, the I/O control registers are set to "0," and the I/O ports enter input mode. When the peripheral input/output or special output function is selected (see Table 12.1.1), the input/output direction is controlled by the hardware. In this case, I/O control register settings are ineffective. 12.4 input interface level The I/O ports P00-P03 and P10-P13 allow software to select an input interface level. When the input interface level select register SMTxx is set to "0," the corresponding port is configured with a CMOS level input interface. When SMTxx is set to "1," the port is configured with a CMOS Schmitt level input interface. At initial reset, all the ports are configured with a CMOS Schmitt level interface. The input interface level select register of the port that is set for a peripheral input functions the same as the I/O port. The input interface level of the P2 to P5 ports are fixed at a CMOS Schmitt level. 12.5 Pull-down During input Mode A pull-down resistor that activates during the input mode can be built into the I/O ports of the S1C6F016 by mask option. The pull-down resistor becomes effective by writing "1" to the pull-down control register PULxx that corresponds to each port, and the input line is pulled down during input mode. When "0" is written to PULxx or in output mode, the port will not be pulled down. At initial reset, the pull-down control registers are set to "1." The pull-down control registers of the ports in which the pull-down resistor is disconnected by custom mask option can be used as general purpose registers. Even if the pull-down resistor has been connected, the pull-down control register of the port that is set for a peripheral output, R/F converter input/output or output special output (see Table 12.1.1) can be used as a general purpose register that does not affect the pull-down control. The pull-down control register of the port that is set for a peripheral input (except for the R/F converter) functions the same as the I/O port. 12.6 Key input interrupt Function Eight bits of the I/O ports (P00-P03, P10-P13) provide the interrupt function. The conditions for generating an interrupt can be set with software. Further, whether to mask the interrupt function can be selected with software. Figure 12.6.1 shows the configuration of the key input interrupt circuit. S1C6F016 Technical Manual (Rev. 1.1) Seiko Epson Corporation 12-3 12 i/O PORTS P00 Sleep cancellation Address Interrupt polarity select register (PCP00) Noise rejector MUX Interrupt factor flag (IK00) Address Address Interrupt request Interrupt select register (SIP00) Address Interrupt mask register (EIK00) Address P01 P02 P03 Data bus Noise reject select register (NRSP[1:0]) Address P10 Sleep cancellation Address Interrupt polarity select register (PCP10) Noise rejector MUX Interrupt factor flag (IK10) Address Address Interrupt request Interrupt select register (SIP10) Address Interrupt mask register (EIK10) Address P11 P12 P13 Noise reject select register (NRSP1[1:0]) Address Figure 12.6.1 Key input interrupt circuit configuration The interrupt select registers (SIP0[3:0], SIP1[3:0]) and interrupt polarity select registers (PCP0[3:0], PCP1[3:0]) are individually provided for the I/O ports P00-P03 and P10-P13. The interrupt select registers (SIPxx) select the ports to be used for generating interrupts or canceling SLEEP mode. Writing "1" to an interrupt select register incorporates that port into the key input interrupt generation conditions. Changing the port where the interrupt select register has been set to "0" does not affect the generation of the interrupt. The key input interrupt timing can be selected using the interrupt polarity select registers (PCPxx) so that an interrupt will be generated at the rising edge or falling edge of the input. By setting these two conditions, an interrupt request signal and a SLEEP cancellation signal are generated at the rising or falling edge (selected by PCPxx) of the signal input to the port (selected by SIPxx). When a key input interrupt factor occurs, the interrupt factor flag (IK00-IK03, IK10-IK13) is set to "1." At the same time, an interrupt request is generated to the CPU if the corresponding interrupt mask register (EIK00-EIK03, EIK10-EIK13) is set to "1." 12-4 Seiko Epson Corporation S1C6F016 TECHNICAL MANUAL (Rev. 1.1) 12 i/O PORTS When the interrupt mask register (EIKxx) is set to "0," the interrupt request is masked and no interrupt is generated to the CPU. The key input interrupt circuit has a noise rejector to avoid unnecessary interrupt generation due to noise or chattering. This noise rejector allows selection of a noise-reject frequency from among three types shown in Table 12.6.1. Use the NRSP0[1:0] register for P00-P03 ports or NRSP1[1:0] register for P10-P13 ports to select a noise-reject frequency. If a pulse shorter than the selected width is input to the port, an interrupt is not generated. When high speed response is required, turns the noise rejecter off (bypassed). Table 12.6.1 Setting up noise rejector NRSP0[1:0]/NRSP1[1:0] Noise reject frequency Reject pulse width 3 fOSC1 / 256 (128 Hz) 7.8 msec 2 fOSC1 / 64 (512 Hz) 2.0 msec 1 fOSC1 / 16 (2 kHz) 0.5 msec 0 Off (bypassed) - Notes: * Be sure to turn the noise rejector off before executing the SLP instruction. * Reactivating from SLEEP status can only be done by generation of a key input interrupt factor. Therefore when using the SLEEP function, it is necessary to set the interrupt select register (SIPxx = "1") of the port to be used for releasing SLEEP status before executing the SLP instruction. Furthermore, enable the key input interrupt using the corresponding interrupt mask register (EIKxx = "1") before executing the SLP instruction to run key input interrupt handler routine after SLEEP status is released. 12.7 i/O memory of i/O ports Table 12.7.1 shows the I/O addresses and the control bits for the I/O ports. Table 12.7.1 Control bits of I/O ports Address Register name R/W Default Setting/data Function FF11H D3 D2 D1 D0 nRSP11 nRSP10 nRSP01 nRSP00 R/W R/W R/W R/W 0 0 0 0 3 2 3 2 f1/256 f1/64 f1/256 f1/64 1 0 1 0 f1/16 Off f1/16 Off P1 key input interrupt noise reject frequency selection (f1 = fOSC1, f3 = fOSC3) P0 key input interrupt noise reject frequency selection (f1 = fOSC1, f3 = fOSC3) FF20H D3 D2 D1 D0 P03 P02 P01 P00 R/W R/W R/W R/W 1 1 1 1 1 1 1 1 High High High High 0 0 0 0 Low Low Low Low P03 I/O port data P02 I/O port data P01 I/O port data P00 I/O port data FF21H D3 D2 D1 D0 iOC03 iOC02 iOC01 iOC00 R/W R/W R/W R/W 0 0 0 0 1 1 1 1 Output Output Output Output 0 0 0 0 Input Input Input Input P03 I/O control register P02 I/O control register P01 I/O control register P00 I/O control register FF22H D3 D2 D1 D0 Pul03 Pul02 Pul01 Pul00 R/W R/W R/W R/W 1 1 1 1 1 1 1 1 Enable Enable Enable Enable 0 0 0 0 Disable Disable Disable Disable P03 pull-down control register P02 pull-down control register P01 pull-down control register P00 pull-down control register FF23H D3 D2 D1 D0 SMT03 SMT02 SMT01 SMT00 R/W R/W R/W R/W 1 1 1 1 1 1 1 1 Schmitt Schmitt Schmitt Schmitt 0 0 0 0 CMOS CMOS CMOS CMOS P03 input I/F level select register P02 input I/F level select register P01 input I/F level select register P00 input I/F level select register FF24H D3 D2 D1 D0 P13 P12 P11 P10 R/W R/W R/W R/W 1 1 1 1 1 1 1 1 High High High High 0 0 0 0 Low Low Low Low P13 I/O port data P12 I/O port data P11 I/O port data P10 I/O port data FF25H D3 D2 D1 D0 iOC13 iOC12 iOC11 iOC10 R/W R/W R/W R/W 0 0 0 0 1 1 1 1 Output Output Output Output 0 0 0 0 Input Input Input Input P13 I/O control register P12 I/O control register P11 I/O control register P10 I/O control register S1C6F016 Technical Manual (Rev. 1.1) Seiko Epson Corporation 12-5 12 i/O PORTS Address Register name R/W Default Setting/data Function FF26H D3 D2 D1 D0 Pul13 Pul12 Pul11 Pul10 R/W R/W R/W R/W 1 1 1 1 1 1 1 1 Enable Enable Enable Enable 0 0 0 0 Disable Disable Disable Disable P13 pull-down control register P12 pull-down control register P11 pull-down control register P10 pull-down control register FF27H D3 D2 D1 D0 SMT13 SMT12 SMT11 SMT10 R/W R/W R/W R/W 1 1 1 1 1 1 1 1 Schmitt Schmitt Schmitt Schmitt 0 0 0 0 CMOS CMOS CMOS CMOS P13 input I/F level select register P12 input I/F level select register P11 input I/F level select register P10 input I/F level select register FF28H D3 D2 D1 D0 P23 P22 P21 P20 R/W R/W R/W R/W 1 1 1 1 1 1 1 1 High High High High 0 0 0 0 Low Low Low Low P23 I/O port data P22 I/O port data P21 I/O port data P20 I/O port data FF29H D3 D2 D1 D0 iOC23 iOC22 iOC21 iOC20 R/W R/W R/W R/W 0 0 0 0 1 1 1 1 Output Output Output Output 0 0 0 0 Input Input Input Input P23 I/O control register P22 I/O control register P21 I/O control register P20 I/O control register FF2AH D3 D2 D1 D0 Pul23 Pul22 Pul21 Pul20 R/W R/W R/W R/W 1 1 1 1 1 1 1 1 Enable Enable Enable Enable 0 0 0 0 Disable Disable Disable Disable P23 pull-down control register P22 pull-down control register P21 pull-down control register P20 pull-down control register FF2CH D3 D2 D1 D0 P33 P32 P31 P30 R/W R/W R/W R/W 1 1 1 1 1 1 1 1 High High High High 0 0 0 0 Low Low Low Low P33 I/O port data P32 I/O port data P31 I/O port data P30 I/O port data FF2DH D3 D2 D1 D0 iOC33 iOC32 iOC31 iOC30 R/W R/W R/W R/W 0 0 0 0 1 1 1 1 Output Output Output Output 0 0 0 0 Input Input Input Input P33 I/O control register P32 I/O control register P31 I/O control register P30 I/O control register FF2EH D3 D2 D1 D0 Pul33 Pul32 Pul31 Pul30 R/W R/W R/W R/W 1 1 1 1 1 1 1 1 Enable Enable Enable Enable 0 0 0 0 Disable Disable Disable Disable P33 pull-down control register P32 pull-down control register P31 pull-down control register P30 pull-down control register FF30H D3 D2 D1 D0 P43 P42 P41 P40 R/W R/W R/W R/W 1 1 1 1 1 1 1 1 High High High High 0 0 0 0 Low Low Low Low P43 I/O port data P42 I/O port data P41 I/O port data P40 I/O port data FF31H D3 D2 D1 D0 iOC43 iOC42 iOC41 iOC40 R/W R/W R/W R/W 0 0 0 0 1 1 1 1 Output Output Output Output 0 0 0 0 Input Input Input Input P43 I/O control register P42 I/O control register P41 I/O control register P40 I/O control register FF32H D3 D2 D1 D0 Pul43 Pul42 Pul41 Pul40 R/W R/W R/W R/W 1 1 1 1 1 1 1 1 Enable Enable Enable Enable 0 0 0 0 Disable Disable Disable Disable P43 pull-down control register P42 pull-down control register P41 pull-down control register P40 pull-down control register FF34H D3 D2 D1 D0 P53 P52 P51 P50 R/W R/W R/W R/W 1 1 1 1 1 1 1 1 High High High High 0 0 0 0 Low Low Low Low P53 I/O port data P52 I/O port data P51 I/O port data P50 I/O port data FF35H D3 D2 D1 D0 iOC53 iOC52 iOC51 iOC50 R/W R/W R/W R/W 0 0 0 0 1 1 1 1 Output Output Output Output 0 0 0 0 Input Input Input Input P53 I/O control register P52 I/O control register P51 I/O control register P50 I/O control register FF36H D3 D2 D1 D0 Pul53 Pul52 Pul51 Pul50 R/W R/W R/W R/W 1 1 1 1 1 1 1 1 Enable Enable Enable Enable 0 0 0 0 Disable Disable Disable Disable P53 pull-down control register P52 pull-down control register P51 pull-down control register P50 pull-down control register FF3CH D3 D2 D1 D0 SiP03 SiP02 SiP01 SiP00 R/W R/W R/W R/W 0 0 0 0 1 1 1 1 Enable Enable Enable Enable 0 0 0 0 Disable Disable Disable Disable P03 (KEY03) interrupt select register P02 (KEY02) interrupt select register P01 (KEY01) interrupt select register P00 (KEY00) interrupt select register FF3DH D3 D2 D1 D0 PCP03 PCP02 PCP01 PCP00 R/W R/W R/W R/W 1 1 1 1 1 1 1 1 (falling edge) (falling edge) (falling edge) (falling edge) 0 0 0 0 (rising edge) (rising edge) (rising edge) (rising edge) P03 (KEY03) interrupt polarity select register P02 (KEY02) interrupt polarity select register P01 (KEY01) interrupt polarity select register P00 (KEY00) interrupt polarity select register 12-6 Seiko Epson Corporation S1C6F016 TECHNICAL MANUAL (Rev. 1.1) 12 i/O PORTS Address Register name R/W Default Setting/data Function FF3EH D3 D2 D1 D0 SiP13 SiP12 SiP11 SiP10 R/W R/W R/W R/W 0 0 0 0 1 1 1 1 Enable Enable Enable Enable 0 0 0 0 Disable Disable Disable Disable P13(KEY13) interrupt select register P12(KEY12) interrupt select register P11(KEY11) interrupt select register P10(KEY10) interrupt select register FF3FH D3 D2 D1 D0 PCP13 PCP12 PCP11 PCP10 R/W R/W R/W R/W 1 1 1 1 1 1 1 1 (falling edge) (falling edge) (falling edge) (falling edge) 0 0 0 0 (rising edge) (rising edge) (rising edge) (rising edge) P13(KEY13) interrupt polarity select register P12(KEY12) interrupt polarity select register P11(KEY11) interrupt polarity select register P10(KEY10) interrupt polarity select register *1: Initial value at initial reset *2: Not set in the circuit *3: Constantly "0" when being read P0[3:0]: P0 i/O port data register (FF20h) P1[3:0]: P1 i/O port data register (FF24h) P2[3:0]: P2 i/O port data register (FF28h) P3[3:0]: P3 i/O port data register (FF2Ch) P4[3:0]: P4 i/O port data register (FF30h) P5[3:0]: P5 i/O port data register (FF34h) I/O port data can be read and output data can be set through these registers. When writing data When "1" is written: High level When "0" is written: Low level When an I/O port is placed into output mode, the written data is output unchanged from the I/O port terminal. When "1" is written as port data, the port terminal goes high (VDD), and when "0" is written, the terminal goes low (VSS). Port data can be written also in the input mode. When reading data When "1" is read: High level When "0" is read: Low level When the I/O port is placed into input mode, the voltage level being input to the port terminal can be read out. When the terminal voltage is high (VDD), the port data that can be read is "1," and when the terminal voltage is low (VSS) the read data is "0." When the pull-down resistor option has been selected and the PULxx register is set to "1," the built-in pull-down resistor goes on during input mode, so that the I/O port terminal is pulled down. When the I/O port is placed into output mode, the register value is read. Therefore, when using the data register of a port that is not used for signal input/output as a general-purpose register, set the port to output mode. At initial reset, these registers are set to "1." The data register of the port, which is set for an input/output of the serial interface or R/F converter or a special output, becomes a general-purpose register that does not affect the input/output status. Note: When I/O ports set in input mode is changed from high to low by the pull-down resistor, the fall of the waveform is delayed on account of the time constant of the pull-down resistor and input gate capacitance. Hence, when fetching input data, set an appropriate wait time. Particular care needs to be taken of the key scan during key matrix configuration. Make this waiting time the amount of time or more calculated by the following expression. 10 x C x R C: terminal capacitance 15 pF + parasitic capacitance ? pF R: pull-down resistance 500 k (Max.) S1C6F016 Technical Manual (Rev. 1.1) Seiko Epson Corporation 12-7 12 i/O PORTS iOC0[3:0]: P0 port i/O control register (FF21h) iOC1[3:0]: P1 port i/O control register (FF25h) iOC2[3:0]: P2 port i/O control register (FF29h) iOC3[3:0]: P3 port i/O control register (FF2Dh) iOC4[3:0]: P4 port i/O control register (FF31h) iOC5[3:0]: P5 port i/O control register (FF35h) Sets the I/O ports to input or output mode. When "1" is written: Output mode When "0" is written: Input mode Reading: Valid The input/output mode of the I/O ports are set in 1-bit units. Writing "1" to the I/O control register places the corresponding I/O port into output mode, and writing "0" sets input mode. At initial reset, these registers are all set to "0," so the I/O ports are placed in input mode. The I/O control register of the port, which is set for an input/output of the serial interface or R/F converter or a special output, are ineffective. Pul0[3:0]: P0 port pull-down control register (FF22h) Pul1[3:0]: P1 port pull-down control register (FF26h) Pul2[3:0]: P2 port pull-down control register (FF2ah) Pul3[3:0]: P3 port pull-down control register (FF2eh) Pul4[3:0]: P4 port pull-down control register (FF32h) Pul5[3:0]: P5 port pull-down control register (FF36h) Enables the pull-down during input mode. When "1" is written: Pull-down On When "0" is written: Pull-down Off Reading: Valid These registers enable the built-in pull-down resistor to be effective during input mode in 1-bit units. (The pulldown resistor is included into the ports selected by mask option.) By writing "1" to the pull-down control register, the corresponding I/O ports are pulled down during input mode, while writing "0" or output mode disables the pull-down function. At initial reset, these registers are all set to "1," so the pull-down function is enabled. The pull-down control register of the port in which the pull-down resistor is not included becomes a generalpurpose register. The register of the port that is set as output for the serial interface, input/output for the R/F converter or a special output can also be used as a general-purpose register that does not affect the pull-down control. The pull-down control register of the port that is set as input for the serial interface functions the same as the I/O port. SMT0[3:0]: P0 port input interface level select register (FF23h) SMT1[3:0]: P1 port input interface level select register (FF27h) Selects an input interface level. When "1" is written: CMOS Schmitt level When "0" is written: CMOS level Reading: Valid These registers select the input interface level of the P0 and P1 I/O ports in 1-bit units. When "1" is written to SMTxx, the corresponding I/O port Pxx is configured with a CMOS Schmitt level input interface. When "0" is written, the port is configured with a CMOS level input interface. At initial reset, these registers are set to "1." The input interface level of the P2 to P5 ports are fixed at a CMOS Schmitt level. 12-8 Seiko Epson Corporation S1C6F016 TECHNICAL MANUAL (Rev. 1.1) 12 i/O PORTS SiP0[3:0]: P0 port interrupt select register (FF3Ch) SiP1[3:0]: P1 port interrupt select register (FF3eh) Selects the ports used for the key input interrupt from P00-P03 and P10-P13. When "1" is written: Interrupt enable When "0" is written: Interrupt disable Reading: Valid By writing "1" to an interrupt select register (SIP0[3:0], SIP1[3:0]), the corresponding I/O port (P00-P03, P10- P13) is enabled to generate interrupts. When "0" is written, the I/O port does not affect the interrupt generation. Reactivating from SLEEP status can only be done by generation of a key input interrupt factor. Therefore when using the SLEEP function, it is necessary to set the interrupt select register (SIPxx = "1") of the port to be used for releasing SLEEP status before executing the SLP instruction. At initial reset, these registers are set to "0." PCP0[3:0]: P0 port interrupt polarity select register (FF3Dh) PCP1[3:0]: P1 port interrupt polarity select register (FF3Fh) Sets the interrupt conditions. When "1" is written: Falling edge When "0" is written: Rising edge Reading: Valid When "1" is written to an interrupt polarity select register (PCP0[3:0], PCP1[3:0]), the corresponding I/O port (P00-P03, P10-P13) generates an interrupt at the falling edge of the input signal. When "0" is written, the I/O port generates an interrupt at the rising edge of the input signal. At initial reset, these registers are set to "1." nRSP0[1:0]: Key input interrupt 0-3 noise reject frequency select register (FF11h*D[1:0]) nRSP1[1:0]: Key input interrupt 4-7 noise reject frequency select register (FF11h*D[3:2]) Selects the noise reject frequency for the key input interrupts. Table 12.7.2 Setting up noise rejector NRSP0[1:0]/NRSP1[1:0] Noise reject frequency Reject pulse width 3 fOSC1 / 256 (128 Hz) 7.8 msec 2 fOSC1 / 64 (512 Hz) 2.0 msec 1 fOSC1 / 16 (2 kHz) 0.5 msec 0 Off (bypassed) - NRSP0[1:0] and NRSP1[1:0] are the noise reject frequency select registers that correspond to the key input interrupts 0-3 (P00-P03) and the key input interrupts 4-7 (P10-P13), respectively. At initial reset, these registers are set to "0." S1C6F016 Technical Manual (Rev. 1.1) Seiko Epson Corporation 12-9 12 i/O PORTS 12.8 Precautions * When an I/O ports in input mode is changed from high to low by the pull-down resistor, the fall of the waveform is delayed on account of the time constant of the pull-down resistor and input gate capacitance. Hence, when fetching input data, set an appropriate wait time. Particular care needs to be taken of the key scan during key matrix configuration. Make this waiting time the amount of time or more calculated by the following expression. 10 x C x R C: terminal capacitance 15 pF + parasitic capacitance ? pF R: pull-down resistance 500 kW (Max.) * Be sure to turn the noise rejector off before executing the SLP instruction. * Reactivating from SLEEP status can only be done by generation of a key input interrupt factor. Therefore when using the SLEEP function, it is necessary to set the interrupt select register (SIPxx = "1") of the port to be used for releasing SLEEP status before executing the SLP instruction. Furthermore, enable the key input interrupt using the corresponding interrupt mask register (EIKxx = "1") before executing the SLP instruction to run key input interrupt handler routine after SLEEP status is released. * Before the port function is configured, the circuit that uses the port (e.g. input interrupt, multiple key entry reset, serial interface, R/F converter, event counter input, direct RUN/LAP input for stopwatch) must be disabled. 12-10 Seiko Epson Corporation S1C6F016 TECHNICAL MANUAL (Rev. 1.1) 13 SeRial inTeRFaCe 13 Serial Interface 13.1 Configuration of Serial interface The S1C6F016 has a built-in 8-bit clock synchronous type serial interface. The CPU, via the 8-bit shift register, can read the serial input data from the SIN terminal. Moreover, via the same 8-bit shift register, it can convert parallel data to serial data and output it to the SOUT terminal. The synchronous clock for serial data input/output may be set by software any one of seven types of master mode (internal clock mode: when the S1C6F016 is to be the master for serial input/output) and one type of slave mode (external clock mode: when the S1C6F016 is to be the slave for serial input/output). The configuration of the serial interface is shown in Figure 13.1.1. Data bus 8-bit shift register SD[7:0] SIN (P32) fOSC1 fOSC3 Programmable timer 1 Clock manager SCPS[1:0] SIFCKS[2:0] Clock format selection SIF clock selection Interrupt request Interrupt control Output latch SOUT (P31) SDP ESOUT Data I/O permutation SOUT enable ESIF SIF enable (P3x) SCTRG SIF clock trigger Clock control SRDY_SS enable (P33) ENCS ESREADY SRDY_SS function selection Mode selection SMOD Transfer mode control SCLK (P30) SS or SRDY (P33) Serial interface Figure 13.1.1 Configuration of serial interface 13.2 Serial interface Terminals The following shows the terminals used in the serial interface and their functions: SCLK (P30) Inputs or outputs the serial clock. By writing "1" to the ESIF register to enable the serial interface, the P30 terminal is switched to the SCLK terminal. In master mode, the SCLK terminal is configured for output and it outputs the synchronous clock generated in the IC during data transfer. In slave mode, the SCLK terminal inputs the synchronous clock output by the external master device. SIN (P32) Inputs serial data. By writing "1" to the ESIF register to enable the serial interface, the P32 terminal is switched to the SIN terminal. SOUT (P31) Outputs serial data. By default, the SOUT terminal is not enabled even if "1" is written to the ESIF register. When using the SOUT output, write "1" to the ESOUT register. If serial input only is required, the P31 terminal can be used as an I/O port terminal. SRDY (P33) In slave mode, this terminal outputs the SRDY signal to the master device to indicate that the serial interface is ready to transfer. By default, the SRDY terminal is not enabled even if the serial interface is set to slave mode. When using the SRDY output in slave mode, write "1" to the ENCS and ESREADY registers. SS (P33) Inputs the SS (Slave Select) signal when the S1C6F016 is used as an SPI slave device. When using the SS input, write "1" to ENCS and write "0" to ESREADY. S1C6F016 Technical Manual (Rev. 1.1) Seiko Epson Corporation 13-1 13 SeRial inTeRFaCe The serial interface input/output ports are shared with the I/O port (P30-P33), and they are configured to the I/O port terminals at initial reset. When using these terminals for the serial interface, switch the function with software as described above. At least ESIF must be set to 1. The switch operation automatically sets the input/output direction of the terminals. It is not necessary to set the I/O port control registers. The I/O control registers and data registers of the I/O ports are ineffective. However, the pull-up control registers of the I/O ports are effective when they are used for the serial inputs. 13.3 Mask Option Since the input/output terminals of the serial interface are shared with the I/O ports (P30-P33), the mask option that selects the terminal specification for the I/O port is also applied to the serial interface terminals. Custom mask option The output specification of the SOUT, SCLK (in master mode) and SRDY (in slave mode) terminals that are used as the serial interface outputs is respectively selected by the mask options for P31, P30 and P33. Either complementary output or P-channel open drain output can be selected as the output specification. However, when Pchannel open drain output is selected, do not apply voltage exceeding the power supply voltage to the terminal. Furthermore, the pull-down resistor for the SIN, SCLK (in slave mode) and SS (in SPI slave mode) terminals that are used as inputs can be incorporated by the mask options for P32, P30 and P33. When the pull-down resistor is not used, take care that a floating status does not occur. Standard mask option Type B, Type e, and Type G The output specification of the P30-P33 I/O ports is fixed at a complementary output. The P30-P33 I/O port terminals have a built-in pull-down resistor. Therefore, the output specification of the SOUT, SCLK (in master mode) and SRDY (in slave mode) terminals that are used as the serial interface outputs is a complementary output only. The SIN, SCLK (in slave mode) and SS (in SPI slave mode) terminals that are used as inputs have a pull-down resistor. Pull-down control when pull-down resistor is incorporated When a pull-down resistor is incorporated at the serial input terminal, the pull-down resistor should be enabled/ disabled using the pull-down control register of the I/O port. SIN terminal: PUL32 register SCLK terminal: PUL30 register SS terminal: PUL33 register Refer to the "I/O Ports" chapter for controlling the pull-down resistors. 13.4 Operating Mode of Serial interface The serial interface supports three operating modes: master mode, slave mode and SPI slave mode. Master mode Master mode is provided to use the S1C6F016 as the master device for serial transfer. In this mode, the serial interface uses the internal clock supplied from the clock manager as the synchronous clock for serial transfer. The synchronous clock is also output from the SCLK terminal to the slave device. The ready signal sent from the slave device should be input through an I/O port (in input mode) and it should be read with software to control data transfer. The S1C6F016 set to master mode is also used as an SPI master device. The SS (Slave Select) signal should be output by controlling an I/O port (in output mode) with software. 13-2 Seiko Epson Corporation S1C6F016 TECHNICAL MANUAL (Rev. 1.1) 13 SeRial inTeRFaCe Slave mode Slave mode is provided to use the S1C6F016 as a slave device for serial transfer. In this mode, the serial interface inputs the synchronous clock that is sent by the external master device from the SCLK terminal to perform serial transfer. For the external master device to control data transfer, the serial interface can output a ready signal indicating that it is ready to transfer from the SRDY terminal by hardware control. SPi slave mode SPI slave mode is provided to use the S1C6F016 as an SPI slave device. In this mode, the serial interface inputs the synchronous clock that is sent by the external master device from the SCLK terminal to perform serial transfer. The SPI master device outputs the SS (Slave Select) signal to select a slave device. SPI slave mode supports the SS signal input. Sample basic serial connection diagrams are shown in Figure 13.4.1. S1C6F016 S1C6F016 External slave device SPI slave device SCLK CLK SCLK CLK SOUT SOUT SOUT SDO SIN SIN SIN SDI Pxx READY Pxx SS (a-1) Master mode S1C6F016 (a-2) Master mode (SPI) S1C6F016 External master device SPI master device SCLK CLK SCLK SCLK SOUT SOUT SOUT SDO SIN SIN SRDY SIN SDI SS SS READY input (b) Slave mode (c) SPI slave mode Figure 13.4.1 Sample basic connection of serial input/output terminals The SMOD, ENCS and ESREADY registers are used for setting the mode. Master mode: SMOD = "1," ENCS = "0," ESREADY = "0" Slave mode: SMOD = "0," ENCS = "1," ESREADY = "1" SPI slave mode: SMOD = "0," ENCS = "1," ESREADY = "0" Table 13.4.1 lists the combination of mode settings and used terminal configurations. Table 13.4.1 Mode settings and configurations of serial interface terminals ESIF SMOD ENCS ESREADY ESOUT Mode 1 1 1 1 1 1 1 1 1 1 1 0 1 1 1 1 1 0 0 0 0 0 0 * 1 * 0 * 0 1 1 0 0 1 1 * 1 0 1 0 1 1 1 * * 0 0 * * 1 1 0 0 1 0 1 0 1 0 * Master mode S1C6F016 Technical Manual (Rev. 1.1) Slave mode SPI slave mode Serial I/F not used Seiko Epson Corporation P30 terminal SCLK (O) SCLK (O) SCLK (O) SCLK (O) SCLK (I) SCLK (I) SCLK (I) SCLK (I) SCLK (I) SCLK (I) P30 (I/O) P31 P32 terminal terminal Prohibited SOUT (O) SIN (I) SOUT (O) SIN (I) P31 (I/O) SIN (I) P31 (I/O) SIN (I) SOUT (O) SIN (I) P31 (I/O) SIN (I) SOUT (O) SIN (I) P31 (I/O) SIN (I) SOUT (O) SIN (I) P31 (I/O) SIN (I) P31 (I/O) P32 (I/O) P33 terminal P33 (I/O) P33 (I/O) P33 (I/O) P33 (I/O) SRDY (O) SRDY (O) P33 (I/O) P33 (I/O) SS (I) SS (I) P33 (I/O) 13-3 13 SeRial inTeRFaCe 13.5 Setting Synchronous Clock 13.5.1 Selecting Source Clock When the serial interface is used in master mode, it uses the internal clock supplied from the clock manager as the synchronous clock for data transfer. The clock manager generates six serial interface clocks by dividing the OSC1 or OSC3 clock. The synchronous clock used in master mode can be selected from seven types (the above six clocks and the programmable timer 1 output clock). Use the SIFCKS[2:0] register to select one of them as shown in Table 13.5.1.1. Table 13.5.1.1 Serial interface clock frequencies SIFCKS[2:0] SIF clock (master mode) 7 fOSC3 / 4 * 6 fOSC3 / 2 * 5 fOSC3 / 1 * 4 Programmable timer 1 * 3 fOSC1 / 4 (8 kHz) 2 fOSC1 / 2 (16 kHz) 1 fOSC1 / 1 (32 kHz) 0 Off (slave mode) * fOSC1: OSC1 oscillation frequency. ( ) indicates the frequency when fOSC1 = 32 kHz. fOSC3: OSC3 oscillation frequency The maximum clock frequency is limited to 1 MHz. When programmable timer 1 is selected, the programmable timer 1 underflow signal is divided by 2 before it is used as the synchronous clock. In this case, the programmable timer must be controlled before operating the serial interface. Refer to the "Programmable Timer" chapter for controlling the programmable timer. Fix SIFCKS[2:0] at "0" in slave mode. At initial reset, "Off (slave mode)" is selected. 13.5.2 Selecting Synchronous Clock Format The format (polarity and phase) of the synchronous clock for the serial interface can be configured using the SCPS[1:0] register. Table 13.5.2.1 Configuration of synchronous clock format SCPS[1:0] Polarity Phase 3 Negative (SCLK) Rising edge () 2 Negative (SCLK) Falling edge () 1 Positive (SCLK) Falling edge () 0 Positive (SCLK) Rising edge () At initial reset, the clock polarity is set to positive and the phase is set to the rising edge. See Figure 13.6.5.1 for the data transfer timings by the synchronous clock format selected. 13-4 Seiko Epson Corporation S1C6F016 TECHNICAL MANUAL (Rev. 1.1) 13 SeRial inTeRFaCe 13.6 Data input/Output and interrupt Function The serial interface of S1C6F016 can input/output data via the internal 8-bit shift register. The shift register operates by synchronizing with either the synchronous clock output from the SCLK (P30) terminal (master mode), or the synchronous clock input to the SCLK (P30) terminal (slave mode). The serial interface generates an interrupt on completion of the 8-bit serial data input/output. Detection of serial data input/output is done by counting of the synchronous clock SCLK; the clock completes input/output operation when 8 counts (equivalent to 8 cycles) have been made and then generates an interrupt. The serial data input/output procedure is explained below: 13.6.1 Serial Data Output Procedure and interrupt The S1C6F016 serial interface is capable of outputting parallel data as serial data, in units of 8 bits. By setting the parallel data to the data registers SD[3:0] and SD[7:4], and writing "1" to SCTRG, it synchronizes with the synchronous clock and the serial data is output to the SOUT (P31) terminal. The synchronous clock used here is as follows: in master mode, internal clock which is output to the SCLK (P30) terminal while in slave mode, external clock which is input from the SCLK (P30) terminal. Shift timing of serial data is as follows: * When positive polarity (SCPS1 = "0") is selected for the synchronous clock: The serial data output to the SOUT (P31) terminal changes at the rising edge of the clock input or output from/to the SCLK (P30) terminal. The data in the shift register is shifted at the rising edge of the SCLK signal when the SCPS0 register is "0" or at the falling edge of the SCLK signal when the SCPS0 register is "1." * When negative polarity (SCPS1 = "1") is selected for the synchronous clock: The serial data output to the SOUT (P31) terminal changes at the falling edge of the clock input or output from/ to the SCLK (P30) terminal. The data in the shift register is shifted at the falling edge of the SCLK signal when the SCPS0 register is "0" or at the rising edge of the SCLK signal when the SCPS0 register is "1." When the output of the 8-bit data from SD0 to SD7 is completed, the interrupt factor flag ISIF is set to "1" and an interrupt occurs. Moreover, the interrupt can be masked by the interrupt mask register EISIF. However, regardless of the interrupt mask register setting, the interrupt factor flag is set to "1" after output of the 8-bit data. 13.6.2 Serial Data input Procedure and interrupt The S1C6F016 serial interface is capable of inputting serial data as parallel data, in units of 8 bits. The serial data is input from the SIN (P32) terminal, synchronizes with the synchronous clock, and is sequentially read in the 8-bit shift register. The synchronous clock used here is the internal clock in master mode or the external clock in slave mode. Shift timing of serial data is as follows: * When positive polarity (SCPS1 = "0") is selected for the synchronous clock: The serial data is read into the built-in shift register at the rising edge of the SCLK signal when the SCPS0 register is "0" or at the falling edge of the SCLK signal when the SCPS0 register is "1." The shift register is sequentially shifted as the data is fetched. * When negative polarity (SCPS1 = "1") is selected for the synchronous clock: The serial data is read into the built-in shift register at the falling edge of the SCLK signal when the SCPS0 register is "0" or at the rising edge of the SCLK signal when the SCPS0 register is "1." The shift register is sequentially shifted as the data is fetched. When the input of the 8-bit data from SD0 to SD7 is completed, the interrupt factor flag ISIF is set to "1" and an interrupt is generated. Moreover, the interrupt can be masked by the interrupt mask register EISIF. However, regardless of the interrupt mask register setting, the interrupt factor flag is set to "1" after input of the 8-bit data. The data input in the shift register can be read from data registers SD[7:0] by software. S1C6F016 Technical Manual (Rev. 1.1) Seiko Epson Corporation 13-5 13 SeRial inTeRFaCe 13.6.3 Serial Data input/Output Permutation The S1C6F016 allows the input/output permutation of serial data to be selected by the SDP register as to either LSB first or MSB first. The block diagram showing input/output permutation in case of LSB first and MSB first is provided in Figure 13.6.3.1. The SDP register should be set before setting data to SD[7:0]. SIN Address [FF5CH] Address [FF5BH] SD7 SD6 SD5 SD4 SD3 SD2 SD1 SD0 Output latch SOUT Output latch SOUT (LSB first) SIN Address [FF5BH] Address [FF5CH] SD0 SD1 SD2 SD3 SD4 SD5 SD6 SD7 (MSB first) Figure 13.6.3.1 Serial data input/output permutation 13.6.4 SRDY Signal When the S1C6F016 serial interface is used in the slave mode, the SRDY signal is used to indicate whether the internal serial interface is ready to transmit or receive data for the master side (external) serial device. The SRDY signal is output from the SRDY (P33) terminal. When using the SRDY output in slave mode, write "1" to the ENCS and ESREADY registers (this signal cannot be used in SPI slave mode). Output timing of SRDY signal is as follows: * When positive polarity (SCPS1 = "0") is selected for the synchronous clock: The SRDY signal goes "1" (high) when the S1C6F016 serial interface is ready to transmit or receive data; normally, it is at "0" (low). The SRDY signal changes from "0" to "1" immediately after "1" is written to SCTRG and returns from "1" to "0" when "1" is input to the SCLK (P30) terminal (i.e., when the serial input/output begins transmitting or receiving data). Moreover, when high-order data is read from or written to SD[7:4], the SRDY signal returns to "0." * When negative polarity (SCPS1 = "1") is selected for the synchronous clock: The SRDY signal goes "0" (low) when the S1C6F016 serial interface is ready to transmit or receive data; normally, it is at "1" (high). The SRDY signal changes from "1" to "0" immediately after "1" is written to SCTRG and returns from "0" to "1" when "0" is input to the SCLK (P30) terminal (i.e., when the serial input/output begins transmitting or receiving data). Moreover, when high-order data is read from or written to SD[7:4], the SRDY signal returns to "1." 13.6.5 Timing Chart The S1C6F016 serial interface timing charts are shown in Figure 13.6.5.1. 13-6 Seiko Epson Corporation S1C6F016 TECHNICAL MANUAL (Rev. 1.1) 13 SeRial inTeRFaCe SCTRG (W) SCTRG (R) SCLK SIN 8-bit shift register SOUT ISIF SRDY (Slave mode) (a) When SCPS1 = "0" and SCPS0="0" SCTRG (W) SCTRG (R) SCLK SIN 8-bit shift register SOUT ISIF SRDY (Slave mode) (b) When SCPS1 = "0" and SCPS0 = "1" SCTRG (W) SCTRG (R) SCLK SIN 8-bit shift register SOUT ISIF SRDY (Slave mode) (c) When SCPS1 = "1" and SCPS0 = "0" SCTRG (W) SCTRG (R) SCLK SIN 8-bit shift register SOUT ISIF SRDY (Slave mode) (d) When SCPS1 = "1" and SCPS0 = "1" Figure 13.6.5.1 Serial interface timing chart S1C6F016 Technical Manual (Rev. 1.1) Seiko Epson Corporation 13-7 13 SeRial inTeRFaCe 13.7 Data Transfer in SPi Mode The serial interface supports serial data transfer in SPI mode. This mode has the same serial master and slave functions and control method except that the SRDY output cannot be used when P33 is configured to the SS terminal. Refer to Section 13.4, "Operating mode of serial interface," and Section 13.6, "Data input/output and interrupt function," for these common descriptions. SPi slave device When using the S1C6F016 as an SPI slave device, set the serial interface to SPI slave mode. ESIF = "1," SMOD = "0," ENCS = "1," ESREADY = "0," ESOUT = "1" (when SOUT is used) The P33 terminal functions as the SS (Slave Select) signal input terminal. To perform data transfer in this mode, write "1" to SCTRG to enable the serial interface to transmit/receive data the same as the slave mode described above. The serial interface starts data transfer when the external master device outputs the synchronous clock to the SCLK terminal after it asserts the slave select signal (set to low) input to the SS (P33) terminal. The external device must hold the SS signal (P33 terminal) active while data is being transferred. When the SS signal is inactive, the serial interface does not start data transfer even if the synchronous clock is input to the SCLK terminal. SPi master device When using the S1C6F016 as an SPI master device, set the serial interface to master mode. ESIF = "1," SMOD = "1," ENCS = "0," ESREADY = "0," ESOUT = "1" (when SOUT is used) The SS signal output terminal is not available in master mode, set an I/O port to output mode and use it as the SS signal output terminal. The SS signal must be set to low before writing "1" to SCTRG and hold that active level while data is being transferred. After 8-bit data is transmitted/received, set the SS signal to high. Timing chart The data transfer timing chart in SPI mode is shown in Figure 13.7.1. SCTRG (W) SCTRG (R) SCLK SIN 8-bit shift register SOUT ISIF SS input (Slave mode) SS output (Master mode) Figure 13.7.1 Timing chart in SPI mode (when SCPS1 = SCPS0 = "0") Notes: * The S1C6F016 serial interface does not have a transmit buffer and a receive buffer, therefore, data transfer must be processed in every one-byte transfer. The interrupt factor flag is set after a transfer for one byte has been completed. A start of data transfer from/to the SPI device cannot be used as a trigger to start the interrupt handler. * If the SS signal becomes inactive during data transfer in SPI slave mode or if the master device outputs the SCLK signal before it asserts the SS signal, the serial interface cannot transmit/ receive data normally. 13-8 Seiko Epson Corporation S1C6F016 TECHNICAL MANUAL (Rev. 1.1) 13 SeRial inTeRFaCe 13.8 i/O Memory of Serial interface Table 13.8.1 shows the I/O addresses and the control bits for the serial interface. Table 13.8.1 Control bits of serial interface Address FF14H D3 D2 D1 D0 Register name R/W Default 0 (*3) SiFCKS2 SiFCKS1 SiFCKS0 FF58H D3 0 (*3) D2 eSOuT D1 SCTRG R - (*2) R/W 0 R/W 0 R/W 0 R - (*2) R/W 0 R/W 0 Setting/data - 4 PT1 3 f1/4 2 f1/2 7 f3/4 6 f3/2 5 f3 R/W 0 FF59H D3 D2 D1 D0 SCPS1 SCPS0 SDP SMOD R/W R/W R/W R/W 0 0 0 0 3 2 1 1 FF5AH D3 D2 D1 D0 0 (*3) 0 (*3) eSReaDY enCS R - (*2) R - (*2) R/W 0 R/W 0 FF5BH D3 D2 D1 D0 SD3 SD2 SD1 SD0 R/W R/W R/W R/W x x x x FF5CH D3 D2 D1 D0 SD7 SD6 SD5 SD4 R/W R/W R/W R/W x x x x *1: Initial value at initial reset 1 f1 0 Off/ External - 1 Enable 1 Trigger (W) Run (R) 1 SIF D0 eSiF Function 0 Disable 0 Invalid (W) Stop (R) 0 I/O Negative, Negative, MSB first Master 1 0 0 0 Positive, Positive, LSB first Slave - - 1 SRDY 1 SRDY_SS 0 SS 0 P33 0H-FH 0H-FH *2: Not set in the circuit Unused Serial I/F clock frequency selection (f1 = fOSC1, f3 = fOSC3) Unused SOUT enable Serial I/F clock trigger (writing) Serial I/F clock status (reading) Serial I/F enable (P3 port function selection) Serial I/F clock format selection (polarity, phase) Serial I/F data input/output permutation Serial I/F mode selection Unused Unused SRDY_SS function selection (ENCS = "1") SRDY_SS enable (P33 port function selection) Serial I/F transmit/receive data (low-order 4 bits) SD0 = LSB Serial I/F transmit/receive data (high-order 4 bits) SD7 = MSB *3: Constantly "0" when being read SiFCKS[2:0]: Serial interface clock frequency select register (FF14h*D[2:0]) Selects the synchronous clock frequency in master mode. Table 13.8.2 Serial interface clock frequencies SIFCKS[2:0] SIF clock (master mode) 7 fOSC3 / 4 * 6 fOSC3 / 2 * 5 fOSC3 / 1 * 4 Programmable timer 1 * 3 fOSC1 / 4 (8 kHz) 2 fOSC1 / 2 (16 kHz) 1 fOSC1 / 1 (32 kHz) 0 Off (slave mode) * fOSC1: OSC1 oscillation frequency. ( ) indicates the frequency when fOSC1 = 32 kHz. fOSC3: OSC3 oscillation frequency The maximum clock frequency is limited to 1 MHz. When programmable timer 1 is selected, the programmable timer 1 underflow signal is divided by 2 before it is used as the synchronous clock. In this case, the programmable timer must be controlled before operating the serial interface. Refer to the "Programmable Timer" chapter for controlling the programmable timer. Fix at "0" in slave mode. At initial reset, this register is set to "0." S1C6F016 Technical Manual (Rev. 1.1) Seiko Epson Corporation 13-9 13 SeRial inTeRFaCe eSiF: Serial interface enable register (P3 port function selection) (FF58h*D0) Sets P30-P33 to the input/output port for the serial interface. When "1" is written: Serial interface When "0" is written: I/O port Reading: Valid When "1" is written to the ESIF register, P30, P31, P32 and P33 function as SIN, SOUT, SCLK and SRDY or SS, respectively. In slave mode, the P33 terminal functions as SRDY output or SS input terminal, while in master mode, it functions as the I/O port terminal. At initial reset, this register is set to "0." SCTRG: Clock trigger/status (FF58h*D1) This is a trigger to start input/output of synchronous clock (SCLK). When writing When "1" is written: Trigger When "0" is written: No operation When this trigger is supplied to the serial interface activating circuit, the synchronous clock (SCLK) input/output is started. As a trigger condition, it is required that data writing or reading on data registers SD[7:0] be performed prior to writing "1" to SCTRG. (The internal circuit of the serial interface is initiated through data writing/reading on data registers SD[7:0].) In addition, be sure to enable the serial interface with the ESIF register before setting the trigger. Supply trigger only once every time the serial interface is placed in the RUN state. Refrain from performing trigger input multiple times, as leads to malfunctioning. Moreover, when the synchronous clock SCLK is external clock, start to input the external clock after the trigger. When reading When "1" is read: RUN (during input/output the synchronous clock) When "0" is read: STOP (the synchronous clock stops) When this bit is read, it indicates the status of serial interface clock. After "1" is written to SCTRG, this value is latched till serial interface clock stops (8 clock counts). Therefore, if "1" is read, it indicates that the synchronous clock is in input/output operation. When the synchronous clock input/output is completed, this latch is reset to "0." At initial reset, this bit is set to "0." eSOuT: SOuT enable register (FF58h*D2) Enables serial data output from the P31 port. When "1" is written: Enabled (SOUT) When "0" is written: Disabled (I/O port) Reading: Valid When serial data output is not used, the SOUT output can be disabled to use P31 as an I/O port. When performing serial output, write "1" to ESOUT to set P31 as the SOUT output port. At initial reset, this register is set to "0." SMOD: Operating mode select register (FF59h*D0) Selects the serial interface operating mode from master mode and slave mode. When "1" is written: Master mode When "0" is written: Slave mode Reading: Valid In master mode, the serial interface uses the internal clock (selected in the clock manager) as the synchronous clock for serial transfer. The synchronous clock is also output from the SCLK (P30) terminal to control the external serial interface (slave device). In slave mode, the serial interface inputs the synchronous clock that is sent by the external serial interface (master device) from the SCLK terminal to perform serial transfer. Master mode is selected by writing "1" to SMOD, and slave mode is selected by writing "0." At initial reset, this register is set to "0." 13-10 Seiko Epson Corporation S1C6F016 TECHNICAL MANUAL (Rev. 1.1) 13 SeRial inTeRFaCe SDP: Data input/output permutation select register (FF59h*D1) Selects the serial data input/output permutation. When "1" is written: MSB first When "0" is written: LSB first Reading: Valid Select whether the data input/output permutation will be MSB first or LSB first. At initial reset, this register is set to "0." SCPS[1:0]: Clock format select register (FF59h*D[3:2]) Selects the timing for reading in the serial data input from the SIN (P32) terminal. Table 13.8.3 Configuration of synchronous clock format SCPS[1:0] Polarity Phase 3 Negative (SCLK) Rising edge () 2 Negative (SCLK) Falling edge () 1 Positive (SCLK) Falling edge () 0 Positive (SCLK) Rising edge () * When positive polarity (SCPS1 = "0") is selected for the synchronous clock: During receiving, the serial data is read into the built-in shift register at the rising edge of the SCLK signal when the SCPS0 register is "0" or at the falling edge of the SCLK signal when the SCPS0 register is "1." The shift register is sequentially shifted as the data is fetched. During transmitting, the serial data output to the SOUT (P31) terminal changes at the rising edge of the clock input or output from/to the SCLK (P30) terminal. The data in the shift register is shifted at the rising edge of the SCLK signal when the SCPS0 register is "0" or at the falling edge of the SCLK signal when the SCPS0 register is "1." * When negative polarity (SCPS1 = "1") is selected for the synchronous clock: During receiving, the serial data is read into the built-in shift register at the falling edge of the SCLK signal when the SCPS0 register is "0" or at the rising edge of the SCLK signal when the SCPS0 register is "1." The shift register is sequentially shifted as the data is fetched. During transmitting, the serial data output to the SOUT (P31) terminal changes at the falling edge of the clock input or output from/to the SCLK (P30) terminal. The data in the shift register is shifted at the falling edge of the SCLK signal when the SCPS0 register is "0" or at the rising edge of the SCLK signal when the SCPS0 register is "1." At initial reset, this register is set to "0." enCS: SRDY_SS enable register (P33 port function selection) (FF5ah*D0) Enables the serial interface function of P33. Use this register with ESREADY. When "1" is written: Enabled (Serial interface) When "0" is written: Disabled (I/O port) Reading: Valid When ENCS is enabled, the P33 terminal can be used as SRDY output or SS input terminal in slave mode (SMOD = "0"). At initial reset, this register is set to "0." eSReaDY: SRDY_SS function select register (FF5ah*D1) Selects the P33 port function when ENCS = "1." When "1" is written: SRDY output When "0" is written: SS input Reading: Valid The P33 port function can be selected from SRDY output and SS input in slave mode (SMOD = "0"). At initial reset, this register is set to "0." S1C6F016 Technical Manual (Rev. 1.1) Seiko Epson Corporation 13-11 13 SeRial inTeRFaCe Slave mode: SMOD="0" ESREADY ENCS * 0 0 1 1 1 Table 13.8.4 Selecting P33 port function Master mode: SMOD="1" P33 terminal ESREADY ENCS P33 (I/O) * 0 SS (I) 0 1 SRDY (O) 1 1 P33 terminal P33 (I/O) P33 (I/O) Prohibited SD[7:0]: Serial interface data register (FF5Ch, FF5Bh) These registers are used for writing and reading serial data. When writing When "1" is written: High level When "0" is written: Low level Write data to be output in these registers. The register data is converted into serial data and output from the SOUT (P31) terminal; data bits set at "1" are output as high (VDD) level and data bits set at "0" are output as low (VSS) level. When reading When "1" is read: High level When "0" is read: Low level The serial data input from the SIN (P32) terminal can be read from these registers. The serial data input from the SIN (P32) terminal is converted into parallel data, as a high (VDD) level bit into "1" and as a low (VSS) level bit into "0," and is loaded to these registers. Perform data reading only while the serial interface is not running (i.e., the synchronous clock is neither being input or output). At initial reset, these registers are undefined. 13.9 Precautions * Perform data writing/reading to the data registers SD[7:0] only while the serial interface is not running (i.e., the synchronous clock is neither being input or output). * As a trigger condition, it is required that data writing or reading on data registers SD[7:0] be performed prior to writing "1" to SCTRG. (The internal circuit of the serial interface is initiated through data writing/reading on data registers SD[7:0].) In addition, be sure to enable the serial interface with the ESIF register before setting the trigger. Supply trigger only once every time the serial interface is placed in the RUN state. Refrain from performing trigger input multiple times, as leads to malfunctioning. Moreover, when the synchronous clock SCLK is external clock, start to input the external clock after the trigger. * Setting of the input/output permutation (MSB first/LSB first) with the SDP register should be done before setting data to SD[7:0]. * Be aware that the maximum clock frequency for the serial interface is limited to 1 MHz when the programmable timer is used as the clock source or the serial interface is used in slave mode. 13-12 Seiko Epson Corporation S1C6F016 TECHNICAL MANUAL (Rev. 1.1) 14 lCD DRiVeR 14 LCD Driver 14.1 Configuration of lCD Driver The S1C6F016 has 8 common terminals (COM0-COM7) and 56 segment terminals (SEG0-SEG55), so that it can drive an LCD panel with a maximum of 448 dots (56 x 8). The driving method is 1/3, 1/4, 1/5, 1/6, 1/7 or 1/8 duty dynamic drive with three drive voltages (1/3 bias), VC1, VC2 and VC3. LCD display can be controlled (turned on and off) by software. 14.2 Mask Option 14.2.1 SeG/GPiO/RFC Terminal Configuration Custom mask option The SEG0 to SEG35 terminals are fixed at segment output. The SEG36 to SEG55 terminals are shared with I/O port or R/F converter, and each terminal can be set to the function to be used by mask option. Table 14.2.1.1 SEG/GPIO/RFC terminal configuration option Function 1 Function 2 (GPIO/RFC terminal) (SEG terminal) P40 SEG36 P41 SEG37 P42 SEG38 P43 SEG39 P30/SCLK SEG40 P31/SOUT SEG41 P32/SIN SEG42 P33/SRDY_SS SEG43 P20 SEG44 P21 SEG45 P22/EVIN_B SEG46 P23/TOUT_B SEG47 P50/RFOUT SEG48 P51/SEN0 SEG49 P52/REF0 SEG50 P53/RFIN0 SEG51 RFIN1 SEG52 REF1 SEG53 SEN1 SEG54 HUD SEG55 Standard mask option Type B The SEG0 to SEG35 terminals can only be used for segment outputs. The maximum number of dots that can be driven is 288 dots (36 x 8). The SEG36 to SEG55 terminals are not available, as they are all configured to the I/O port and R/F converter terminals. The SEG0 to SEG35 terminals cannot be used for DC outputs. Standard mask option Type e All the SEG0 to SEG55 terminals can only be used for segment outputs. The maximum number of dots that can be driven is 448 dots (56 x 8). The R/F converter, serial interface and P20 to P53 I/O ports cannot be used. The SEG0 to SEG55 terminals cannot be used for DC outputs. S1C6F016 Technical Manual (Rev. 1.1) Seiko Epson Corporation 14-1 14 lCD DRiVeR Standard mask option Type G The SEG0 to SEG35 terminals can only be used for DC outputs. The SEG36 to SEG55 terminals are not available, as they are all configured to the I/O port and R/F converter terminals. The SEG0 to SEG35 terminals cannot be used for segment outputs. 14.2.2 Power Source for lCD Driving Custom mask option The power source for driving LCD can be selected from the internal power supply and an external power supply. When the internal power supply is selected, the internal LCD system voltage regulator is enabled to generate the LCD drive voltages VC1-VC3. The LCD system voltage regulator starts operating and outputs the LCD drive voltages VC1-VC3 to the LCD driver when the LPWR register is set to "1." For more information on the LCD system voltage regulator, refer to the "Power Supply" chapter. When using an external power supply, select a drive voltage configuration from the following 3 types and supply the LCD drive voltage to the VC1-VC3 terminals. 1. External power supply 1/3 bias (for 4.5 V panel) VDD = VC2 2. External power supply 1/3 bias (for 3.0 V panel) VDD = VC3 3. External power supply 1/2 bias (for 3.0 V panel) VDD = VC3, VC1 = VC2 For the external connection diagram when an external supply is used, refer to the "Power Supply" chapter. Note that the power control using the LPWR register is necessary even if an external power supply is used. Standard mask option Type B and Type e The internal LCD system voltage regulator is used to generate the LCD drive voltages VC1-VC3. No external power supply can be used. Standard mask option Type G The power source is set to the internal LCD system voltage regulator, but it is not used, as Type G supports DC output only. 14.2.3 Segment Option Output specification Custom mask option The SEG0-SEG55 terminals can be used only for segment signal output. DC output cannot be selected. Standard mask option Type B The SEG0-SEG35 terminals can be used only for segment signal output. DC output cannot be selected. Standard mask option Type e The SEG0-SEG55 terminals can be used only for segment signal output. DC output cannot be selected. Standard mask option Type G The SEG0-SEG35 terminals can be used only for DC output (VDD and VSS binary output). Segment output cannot be selected. The output specification is fixed at complementary output. Each segment terminal outputs COM0 data. 14-2 Seiko Epson Corporation S1C6F016 TECHNICAL MANUAL (Rev. 1.1) 14 lCD DRiVeR Segment allocation Note: Segment allocation is not a mask option item. Create segment allocation data that represents corresponding between display memory bits and segment terminals) using the segment option generator "winsog" and program the Flash EEPROM with the created data. Custom mask option, standard mask option Type B and Type e Each data bits (D0-D3) of the display memory addresses (F000H-F07FH) can be allocated to a segment terminal (SEG0-SEG55) individually. This makes design easy by increasing the degree of freedom with which the LCD panel can be designed. Figure 14.2.3.1 shows an example of the relationship between the LCD segments (on the panel) and the display memory for the case of 1/4 duty. Display memory allocation Address Data bit D3 D2 D1 D0 F010H d c b a F011H p g f c a f b COM0 COM1 g SEG10 SEG11 Pin address allocation COM0 COM1 COM2 11, D1 11, D0 10, D2 (f) (e) (c) 10, D0 11, D2 10, D1 (a) (g) (b) COM3 10, D3 (d) 11, D3 (p) COM2 c e COM3 d p SEG10 SEG11 Figure 14.2.3.1 Segment allocation Standard mask option Type G Each data bits (D0-D3) of the display memory addresses (F000H-F07FH) can be allocated to a segment terminal (SEG0-SEG35) individually. The terminals output the contents of the address/bit corresponding to COM0, so it is not necessary to allocate addresses/bits to COM1-COM7. S1C6F016 Technical Manual (Rev. 1.1) Seiko Epson Corporation 14-3 14 lCD DRiVeR Table 14.2.3.1 Segment option (standard mask option Type B) Pin name COM0 H L D COM1 H L D COM2 H L D Address (F0xxH) COM3 COM4 H L D H L D SEG0 SEG1 SEG2 SEG3 SEG4 SEG5 SEG6 SEG7 SEG8 SEG9 SEG10 SEG11 SEG12 SEG13 SEG14 SEG15 SEG16 SEG17 SEG18 SEG19 SEG20 SEG21 SEG22 SEG23 SEG24 SEG25 SEG26 SEG27 SEG28 SEG29 SEG30 SEG31 SEG32 SEG33 SEG34 SEG35 SEG36 SEG37 SEG38 SEG39 SEG40 SEG41 SEG42 SEG43 SEG44 SEG45 SEG46 SEG47 SEG48 SEG49 SEG50 SEG51 SEG52 SEG53 SEG54 SEG55 <address> H: RAM data high-order address (0-7) L: RAM data low-order address (0-F) D: Data bit (0-3) H COM5 L D H COM6 L D H COM7 L D Output specification nS nS nS nS nS nS nS nS nS nS nS nS nS nS nS nS nS nS nS nS nS nS nS nS nS nS nS nS nS nS nS nS nS nS nS nS nS nS nS nS nS nS nS nS nS nS nS nS nS nS nS nS nS nS nS nS C C C C C C C C C C C C C C C C C C C C C C C C C C C C C C C C C C C C C C C C C C C C C C C C C C C C C C C C N N N N N N N N N N N N N N N N N N N N N N N N N N N N N N N N N N N N N N N N N N N N N N N N N N N N N N N N <Output specification> S: Segment output C: Complementary output N: Nch open drain output Notes for using the segment option generator "winsog" (standard mask option Type B) 1. Any display memory address can be allocated to SEG0 to SEG35. 2. Always select "LCD segment output (S)" as the output specification of SEG0 to SEG35, as it is fixed at segment output. 3. Configurations for nonexistent SEG pins (SEG36 to SEG55) * Always select "LCD segment output (S)" as the output specification of SEG36 to SEG55. * Leave the address cells for SEG36 to SEG55 blank. (Unused addresses will be allocated.) 14-4 Seiko Epson Corporation S1C6F016 TECHNICAL MANUAL (Rev. 1.1) 14 lCD DRiVeR Table 14.2.3.2 Segment option (standard mask option Type E) Pin name COM0 H L D COM1 H L D COM2 H L D Address (F0xxH) COM3 COM4 H L D H L D SEG0 SEG1 SEG2 SEG3 SEG4 SEG5 SEG6 SEG7 SEG8 SEG9 SEG10 SEG11 SEG12 SEG13 SEG14 SEG15 SEG16 SEG17 SEG18 SEG19 SEG20 SEG21 SEG22 SEG23 SEG24 SEG25 SEG26 SEG27 SEG28 SEG29 SEG30 SEG31 SEG32 SEG33 SEG34 SEG35 SEG36 SEG37 SEG38 SEG39 SEG40 SEG41 SEG42 SEG43 SEG44 SEG45 SEG46 SEG47 SEG48 SEG49 SEG50 SEG51 SEG52 SEG53 SEG54 SEG55 <address> H: RAM data high-order address (0-7) L: RAM data low-order address (0-F) D: Data bit (0-3) H COM5 L D H COM6 L D H COM7 L D Output specification nS nS nS nS nS nS nS nS nS nS nS nS nS nS nS nS nS nS nS nS nS nS nS nS nS nS nS nS nS nS nS nS nS nS nS nS nS nS nS nS nS nS nS nS nS nS nS nS nS nS nS nS nS nS nS nS C C C C C C C C C C C C C C C C C C C C C C C C C C C C C C C C C C C C C C C C C C C C C C C C C C C C C C C C N N N N N N N N N N N N N N N N N N N N N N N N N N N N N N N N N N N N N N N N N N N N N N N N N N N N N N N N <Output specification> S: Segment output C: Complementary output N: Nch open drain output Notes for using the segment option generator "winsog" (standard mask option Type E) 1. Any display memory address can be allocated to SEG0 to SEG55. 2. Always select "LCD segment output (S)" as the output specification of SEG0 to SEG55, as it is fixed at segment output. S1C6F016 Technical Manual (Rev. 1.1) Seiko Epson Corporation 14-5 14 lCD DRiVeR Table 14.2.3.3 Segment option (standard mask option Type G) Pin name COM0 H L D COM1 H L D COM2 H L D Address (F0xxH) COM3 COM4 H L D H L D SEG0 SEG1 SEG2 SEG3 SEG4 SEG5 SEG6 SEG7 SEG8 SEG9 SEG10 SEG11 SEG12 SEG13 SEG14 SEG15 SEG16 SEG17 SEG18 SEG19 SEG20 SEG21 SEG22 SEG23 SEG24 SEG25 SEG26 SEG27 SEG28 SEG29 SEG30 SEG31 SEG32 SEG33 SEG34 SEG35 SEG36 SEG37 SEG38 SEG39 SEG40 SEG41 SEG42 SEG43 SEG44 SEG45 SEG46 SEG47 SEG48 SEG49 SEG50 SEG51 SEG52 SEG53 SEG54 SEG55 <address> H: RAM data high-order address (0-7) L: RAM data low-order address (0-F) D: Data bit (0-3) H COM5 L D H COM6 L D H COM7 L D Output specification S S S S S S S S S S S S S S S S S S S S S S S S S S S S S S S S S S S S nS nS nS nS nS nS nS nS nS nS nS nS nS nS nS nS nS nS nS nS nC nC nC nC nC nC nC nC nC nC nC nC nC nC nC nC nC nC nC nC nC nC nC nC nC nC nC nC nC nC nC nC nC nC nC nC C C C C C C C C C C C C C C C C C C C C N N N N N N N N N N N N N N N N N N N N N N N N N N N N N N N N N N N N N N N N N N N N N N N N N N N N N N N N <Output specification> S: Segment output C: Complementary output N: Nch open drain output Notes for using the segment option generator "winsog" (standard mask option Type G) 1. Any display memory address can be allocated to SEG0 to SEG35. Leave the address cells for COM1 to COM7 blank, as Type G supports DC output only. 2. Always select "Complementary output (C)" as the output specification of SEG0 to SEG35, as it is fixed at complementary output. 3. Configurations for nonexistent SEG pins (SEG36 to SEG55) * Always select "LCD segment output (S)" as the output specification of SEG36 to SEG55. * Leave the address cells for SEG36 to SEG55 blank. (Unused addresses will be allocated.) 14-6 Seiko Epson Corporation S1C6F016 TECHNICAL MANUAL (Rev. 1.1) 14 lCD DRiVeR Table 14.2.3.4 Segment option (custom mask option) Pin name COM0 H L D COM1 H L D COM2 H L D Address (F0xxH) COM3 COM4 H L D H L D SEG0 SEG1 SEG2 SEG3 SEG4 SEG5 SEG6 SEG7 SEG8 SEG9 SEG10 SEG11 SEG12 SEG13 SEG14 SEG15 SEG16 SEG17 SEG18 SEG19 SEG20 SEG21 SEG22 SEG23 SEG24 SEG25 SEG26 SEG27 SEG28 SEG29 SEG30 SEG31 SEG32 SEG33 SEG34 SEG35 SEG36 SEG37 SEG38 SEG39 SEG40 SEG41 SEG42 SEG43 SEG44 SEG45 SEG46 SEG47 SEG48 SEG49 SEG50 SEG51 SEG52 SEG53 SEG54 SEG55 <address> H: RAM data high-order address (0-7) L: RAM data low-order address (0-F) D: Data bit (0-3) H COM5 L D H COM6 L D H COM7 L D Output specification nS nS nS nS nS nS nS nS nS nS nS nS nS nS nS nS nS nS nS nS nS nS nS nS nS nS nS nS nS nS nS nS nS nS nS nS nS nS nS nS nS nS nS nS nS nS nS nS nS nS nS nS nS nS nS nS C C C C C C C C C C C C C C C C C C C C C C C C C C C C C C C C C C C C C C C C C C C C C C C C C C C C C C C C N N N N N N N N N N N N N N N N N N N N N N N N N N N N N N N N N N N N N N N N N N N N N N N N N N N N N N N N <Output specification> S: Segment output C: Complementary output N: Nch open drain output Notes for using the segment option generator "winsog" (custom mask option) 1. Any display memory address can be allocated to SEG0 to SEG55. 2. Always select "LCD segment output (S)" as the output specification of SEG0 to SEG55. S1C6F016 Technical Manual (Rev. 1.1) Seiko Epson Corporation 14-7 14 lCD DRiVeR 14.3 lCD Display Control 14.3.1 Selecting Display Mode In addition to the LPWR register for turning the display on and off, the DSPC[1:0] register is provided to select a display mode. There are three display modes available as shown in Table 14.3.1.1. Table 14.3.1.1 Display mode DSPC[1:0] Display mode 3 All on mode 2 All off mode 1 All on mode 0 Normal mode Normal mode: The display memory contents are output without being processed. All on mode: All the LCD segments go on. The SEG terminals output an on waveform. The contents in the display memory are not modified. All off mode: All the LCD segments go off. The SEG terminals output an off waveform. The contents in the display memory are not modified. (default) 14.3.2 Switching Drive Duty In the S1C6F016, the drive duty can be selected from six types (1/3 to 1/8) using the LDUTY[2:0] register. LDUTY[2:0] 7 6 5 4 3 2 1 0 Table 14.3.2.1 Drive duty settings Drive duty Common terminals used Max. number of segments 1/8 COM0-COM7 448 (56 x 8) 1/7 COM0-COM6 392 (56 x 7) 1/8 COM0-COM7 448 (56 x 8) 1/7 COM0-COM6 392 (56 x 7) 1/6 COM0-COM5 336 (56 x 6) 1/5 COM0-COM4 280 (56 x 5) 1/4 COM0-COM3 224 (56 x 4) 1/3 COM0-COM2 168 (56 x 3) 14.3.3 Switching Frame Frequency The frame frequency is determined by the selected drive duty and the clock supplied from the clock manager. The clock to be supplied (16 Hz, 21.3 Hz, or 32 Hz) can be selected using the FLCKS[1:0] register. Selecting a low frame frequency can reduce current consumption. Table 14.3.3.1 Frame frequency settings FLCKS[1:0] 3 2 1 0 Source clock 16.0 Hz 21.3 Hz 32.0 Hz 1/8 duty 16.0 Hz 21.3 Hz 32.0 Hz 1/7 duty 1/6 duty 1/5 duty 1/4 duty 1/3 duty 18.3 Hz 24.4 Hz 36.6 Hz Prohibited 21.3 Hz 28.5 Hz 42.7 Hz 12.8 Hz 17.1 Hz 25.6 Hz 16.0 Hz 21.3 Hz 32.0 Hz 21.3 Hz 28.5 Hz 42.7 Hz (When fOSC1 = 32.768 kHz) Notes: * Be sure to turn the display off (LPWR = "0") before switching the frame frequency. * The frame frequency affects the display quality. We recommend that the frame frequency should be determined after the display quality is evaluated using the actual LCD panel. 14.3.4 Drive Waveform The drive waveforms by duty selection are shown in Figures 14.3.4.1 to 14.3.4.6. 14-8 Seiko Epson Corporation S1C6F016 TECHNICAL MANUAL (Rev. 1.1) 14 lCD DRiVeR VC3 VC2 VC1 VSS COM0 COM1 LCD lighting status COM0 COM1 COM2 COM2 SEGxx VC2 VC1 COM3-7 Not lit Lit VC2 VC1 VC3 VC2 VC1 VSS SEGxx *** Frame Figure 14.3.4.1 LCD drive waveform for 1/3 duty S1C6F016 Technical Manual (Rev. 1.1) Seiko Epson Corporation 14-9 14 lCD DRiVeR VC3 VC2 VC1 VSS COM0 COM1 COM2 LCD lighting status COM0 COM1 COM2 COM3 COM3 VC2 VC1 COM4-7 SEGxx Not lit Lit VC2 VC1 VC3 VC2 VC1 VSS SEGxx *** Frame Figure 14.3.4.2 LCD drive waveform for 1/4 duty 14-10 Seiko Epson Corporation S1C6F016 TECHNICAL MANUAL (Rev. 1.1) 14 lCD DRiVeR VC3 VC2 VC1 VSS COM0 COM1 COM2 LCD lighting status COM0 COM1 COM2 COM3 COM4 COM3 COM4 VC2 VC1 COM5-7 SEGxx Not lit Lit VC2 VC1 VC3 VC2 VC1 VSS SEGxx *** Frame Figure 14.3.4.3 LCD drive waveform for 1/5 duty S1C6F016 Technical Manual (Rev. 1.1) Seiko Epson Corporation 14-11 14 lCD DRiVeR VC3 VC2 VC1 VSS COM0 COM1 COM2 COM3 LCD lighting status COM0 COM1 COM2 COM3 COM4 COM5 COM4 COM5 SEGxx VC2 VC1 COM6-7 Not lit Lit VC2 VC1 VC3 VC2 VC1 VSS SEGxx *** Frame Figure 14.3.4.4 LCD drive waveform for 1/6 duty 14-12 Seiko Epson Corporation S1C6F016 TECHNICAL MANUAL (Rev. 1.1) 14 lCD DRiVeR VC3 VC2 VC1 VSS COM0 COM1 COM2 COM3 COM4 LCD lighting status COM0 COM1 COM2 COM3 COM4 COM5 COM6 COM5 COM6 SEGxx VC2 VC1 COM7 Not lit Lit VC2 VC1 VC3 VC2 VC1 VSS SEGxx *** Frame Figure 14.3.4.5 LCD drive waveform for 1/7 duty S1C6F016 Technical Manual (Rev. 1.1) Seiko Epson Corporation 14-13 14 lCD DRiVeR VC3 VC2 VC1 VSS COM0 COM1 COM2 COM3 COM4 LCD lighting status COM0 COM1 COM2 COM3 COM4 COM5 COM6 COM7 COM5 COM6 SEGxx Not lit Lit COM7 VC2 VC1 VC3 VC2 VC1 VSS SEGxx *** Frame Figure 14.3.4.6 LCD drive waveform for 1/8 duty 14-14 Seiko Epson Corporation S1C6F016 TECHNICAL MANUAL (Rev. 1.1) 14 lCD DRiVeR 14.3.5 Static Drive The LCD driver allows the software to set static drive. To set in static drive, write "1" to the STCD register. Then, by writing "1" to any one of COM0 to COM7 (display memory) corresponding to the SEG terminal, the SEG terminal outputs a static on waveform. When all the COM0 to COM7 bits are set to "0," the SEG terminal outputs an off waveform. Figure 14.3.5.1 shows the static drive waveform. LCD lighting status -VC3 -VC2 -VC1 -VSS COM0-7 COM0 COM1 : COM7 SEGxx Not lit Lit Frame frequency -VC3 -VC2 -VC1 -VSS : -VC3 -VC2 -VC1 -VSS : SEGxx Figure 14.3.5.1 Static drive waveform Note: The static drive function uses all COM outputs (COM0 to COM7) even if a duty other than 1/8 is selected. Hence, for static drive, set the same value for all display memory corresponding to COM0 to COM7. 14.3.6 lCD Contrast adjustment The S1C6F016 allows software to adjust the LCD contrast. This function is realized by controlling the voltages VC1, VC2 and VC3 output from the LCD system voltage regulator. The contrast can be adjusted to 16 levels using the LC[3:0] register as shown in Table 14.3.6.1. LC[3:0] FH EH DH CH BH AH 9H 8H 7H 6H 5H 4H 3H 2H 1H 0H Table 14.3.6.1 LCD contrast Contrast Level 15 Level 14 Level 13 Level 12 Level 11 Level 10 Level 9 Level 8 Level 7 Level 6 Level 5 Level 4 Level 3 Level 2 Level 1 Level 0 (dark) (light) At initial reset, LC[3:0] is set to "0." The software should initialize the register to set to the desired contrast. When an external power supply is selected by mask option, the LCD contrast cannot be adjusted using LC[3:0]. S1C6F016 Technical Manual (Rev. 1.1) Seiko Epson Corporation 14-15 14 lCD DRiVeR 14.4 Display Memory The display memory is located to F000H-F07FH in the data memory area and each data bit can be allocated to an segment terminal (SEG0-SEG55) by programming the Flash EEPROM with the segment assignment data created using the segment option generator "winsog." When a bit in the display memory is set to "1," the corresponding LCD segment goes on, and when it is set to "0," the segment goes off. At initial reset, the data memory contents become undefined hence, there is need to initialize by software. The addresses that are not used for LCD display can be used as general-purpose registers. 14.5 i/O Memory of lCD Driver Table 14.5.1 shows the I/O addresses and the control bits for the LCD driver. Figure 14.5.1 shows the display memory map. Table 14.5.1 Control bits of LCD driver Address Register name R/W Default Setting/data FF12H D3 D2 D1 D0 FlCKS1 FlCKS0 VCCKS1 VCCKS0 R/W R/W R/W R/W FF50H D3 D2 D1 D0 0 (*3) 0 (*3) DSPC1 DSPC0 R - (*2) R - (*2) R/W 1 R/W 0 3 All on 2 All off FF51H D3 D2 D1 D0 STCD lDuTY2 lDuTY1 lDuTY0 R/W R/W R/W R/W 0 0 0 0 1 7 6 5 FF52H D3 D2 D1 D0 lC3 lC2 lC1 lC0 R/W R/W R/W R/W 0 0 0 0 *1: Initial value at initial reset Address Low Base 0 0 0 0 0 3 2 3 2 - 16.0 - - 1 0 1 0 Function 21.3 32.0 2048 Off Frame frequency (Hz) selection VC boost frequency (Hz) selection - - Unused Unused LCD display mode selection 1 All on 0 Normal Static 1/8 1/7 1/8 4 1/7 3 1/6 2 1/5 0 Dynamic 1 1/4 0 1/3 LCD drive mode switch LCD drive duty selection LCD contrast adjustment 0H(light)-FH(dark) *2: Not set in the circuit *3: Constantly "0" when being read 1 6 2 3 F000H F010H F020H F030H F040H F050H F060H F070H 4 5 7 8 9 A B C D E F Display memory (128 words x 4 bits) R/W Figure 14.5.1 Display memory map FlCKS[1:0]: Frame frequency select register (FF12h*D[3:2]) Selects the frequency of the frame clock supplied from the clock manager. Table 14.5.2 Frame frequency settings FLCKS[1:0] 3 2 1 0 Source clock 16.0 Hz 21.3 Hz 32.0 Hz 1/8 duty 16.0 Hz 21.3 Hz 32.0 Hz 1/7 duty 1/6 duty 1/5 duty 1/4 duty 1/3 duty 18.3 Hz 24.4 Hz 36.6 Hz Prohibited 21.3 Hz 28.5 Hz 42.7 Hz 12.8 Hz 17.1 Hz 25.6 Hz 16.0 Hz 21.3 Hz 32.0 Hz 21.3 Hz 28.5 Hz 42.7 Hz (When fOSC1 = 32.768 kHz) At initial reset, this register is set to "0." Notes: * Be sure to turn the display off (LPWR = "0") before switching the frame frequency. * The frame frequency affects the display quality. We recommend that the frame frequency should be determined after the display quality is evaluated using the actual LCD panel. 14-16 Seiko Epson Corporation S1C6F016 TECHNICAL MANUAL (Rev. 1.1) 14 lCD DRiVeR DSPC[1:0]: lCD display mode select register (FF50h*D[1:0]) Sets the display mode. Table 14.5.3 Display mode DSPC[1:0] Display mode 3 All on mode 2 All off mode 1 All on mode 0 Normal mode Normal mode: The display memory contents are output without being processed. All on mode: All the LCD segments go on. The SEG terminals output an on waveform. The contents in the display memory are not modified. All off mode: All the LCD segments go off. The SEG terminals output an off waveform. The contents in the display RAM are not modified. (default) At initial reset, this register is set to "2." lDuTY[2:0]: lCD drive duty select register (FF51h*D[2:0]) Selects the LCD drive duty. LDUTY[2:0] 7 6 5 4 3 2 1 0 Table 14.5.4 Drive duty settings Drive duty Common terminals used Max. number of segments 1/8 COM0-COM7 448 (56 x 8) 1/7 COM0-COM6 392 (56 x 7) 1/8 COM0-COM7 448 (56 x 8) 1/7 COM0-COM6 392 (56 x 7) 1/6 COM0-COM5 336 (56 x 6) 1/5 COM0-COM4 280 (56 x 5) 1/4 COM0-COM3 224 (56 x 4) 1/3 COM0-COM2 168 (56 x 3) At initial reset, this register is set to "0." STCD: lCD drive switch register (FF51h*D3) Switches the LCD driving method. When "1" is written: Static drive When "0" is written: Dynamic drive Reading: Valid By writing "1" to STCD, static drive is selected, and dynamic drive is selected when "0" is written. At initial reset, this register is set to "0." Note: The static drive function uses all COM outputs (COM0 to COM7) even if a duty other than 1/8 is selected. Hence, for static drive, set the same value for all display memory corresponding to COM0 to COM7. lC[3:0]: lCD contrast adjustment register (FF52h) Adjusts the LCD contrast. LC[3:0] = 0H light : : LC[3:0] = FH dark When the LCD drive voltage is supplied from outside by mask option selection, this adjustment becomes invalid. At initial reset, this register is set to 0. S1C6F016 Technical Manual (Rev. 1.1) Seiko Epson Corporation 14-17 14 lCD DRiVeR 14.6 Precautions * Be sure to turn the display off (LPWR = "0") before switching the frame frequency. * The frame frequency affects the display quality. We recommend that the frame frequency should be determined after the display quality is evaluated using the actual LCD panel. * At initial reset, the contents of display memory are undefined and LC[3:0] (LCD contrast) is set to "0," therefore, it is necessary to initialize those contents by software. Also note that the LPWR and DSPC[1:0] registers are set to turn the display off. * When Pxx (P20 to P53) and R/F converter terminals are used as the segment terminals by selecting mask option, do not alter the Pxx port and R/F converter control registers that affect these terminals from their initial values. 14-18 Seiko Epson Corporation S1C6F016 TECHNICAL MANUAL (Rev. 1.1) 15 SOunD GeneRaTOR 15 Sound Generator 15.1 Configuration of Sound Generator The S1C6F016 has a built-in sound generator for generating a buzzer signal. Hence, the generated buzzer signal can be output from the BZ terminal. Aside permitting the respective setting of the buzzer signal frequency and sound level to 8 stages, it permits the adding of a digital envelope by means of duty ratio control. It also has a one-shot output function for outputting key operated sounds. Figure 15.1.1 shows the configuration of the sound generator. SGCKE fOSC1 Clock manager BZFQ[2:0] BDTY[2:0] ENON Programmable dividing circuit Duty ratio control circuit Envelope addition circuit fOSC1/128 One-shot buzzer control circuit ENRST ENRTM Buzzer output control circuit BZSHT BZ (P12) terminal BZE BZSTP SHTPW Figure 15.1.1 Configuration of sound generator Note: If the BZ terminal is used to drive an external component that consumes a large amount of current such as a bipolar transistor, design the pattern of traces on the printed circuit board so that the operation of the external component does not affect the IC power supply. Refer to "Precautions on Mounting" in Appendix for more information. 15.2 Controlling Operating Clock To generate the buzzer signal, the clock for the sound generator must be supplied from the clock manager by writing "1" to the SGCKE register in advance. SGCKE 1 0 Table 15.2.1 Controlling sound generator clock Sound generator clock Programmable dividing circuit input clock: fOSC1 (32 kHz) One-shot buzzer control circuit input clock: fOSC1 / 128 (256 Hz) Off If it is not necessary to run the sound generator, stop the clock supply by setting SGCKE to "0" to reduce current consumption. 15.3 Buzzer Output Control The BZ signal generated by the sound generator is output from the BZ (P12) terminal by setting "1" for the buzzer output enable register BZE. The I/O control register IOC12 and data register P12 settings are ineffective while the BZ signal is being output. When BZE is set to "0," the P12 port is configured as a general-purpose DC input/output port. BZE register "0" "1" "0" BZ output (P12 terminal) Figure 15.3.1 Buzzer signal output timing chart Note: Since it generates the buzzer signal that is out of synchronization with the BZE register, hazards may at times be produced when the signal goes on/off due to the setting of the BZE register. S1C6F016 Technical Manual (Rev. 1.1) Seiko Epson Corporation 15-1 15 SOunD GeneRaTOR 15.4 Buzzer Frequency and Sound level Settings The divided signal of the OSC1 oscillation clock (32.768 kHz) is used for the buzzer signal and it is set up such that 8 types of frequencies can be selected by changing this division ratio. Frequency selection is done by setting the buzzer frequency select register BZFQ[2:0] as shown in Table 15.4.1. Table 15.4.1 Buzzer signal frequency setting BZFQ[2:0] Buzzer frequency (Hz) 0 4096.0 1 3276.8 2 2730.7 3 2340.6 4 2048.0 5 1638.4 6 1365.3 7 1170.3 The buzzer sound level is changed by controlling the duty ratio of the buzzer signal. The duty ratio can be selected from among the 8 types shown in Table 15.4.2 according to the setting of the buzzer duty select register BDTY[2:0]. Level Level 1 (Max.) Level 2 Level 3 Level 4 Level 5 Level 6 Level 7 Level 8 (Min.) Table 15.4.2 Duty ratio setting Duty ratio by buzzer frequency (Hz) BDTY[2:0] 4096.0 3276.8 2730.7 2340.6 2048.0 1638.4 1365.3 1170.3 0 8/16 8/20 12/24 12/28 1 7/16 7/20 11/24 11/28 2 6/16 6/20 10/24 10/28 3 5/16 5/20 9/24 9/28 4 4/16 4/20 8/24 8/28 5 3/16 3/20 7/24 7/28 6 2/16 2/20 6/24 6/28 7 1/16 1/20 5/24 5/28 When the high level output time has been made TH and when the low level output time has been made TL due to the ratio of the pulse width to the pulse synchronization, the duty ratio becomes TH/(TH+TL). When BDTY[2:0] have all been set to "0," the duty ratio becomes maximum and the sound level also becomes maximum. Conversely, when BDTY[2:0] have all been set to "1," the duty ratio becomes minimum and the sound level also becomes minimum. The duty ratio that can be set is different depending on the frequency that has been set, so see Table 15.4.2. TL TH Level 1 (Max.) Level 2 Level 3 Level 4 Level 5 Level 6 Level 7 Level 8 (Min.) Figure 15.4.1 Duty ratio of the buzzer signal waveform Note: When a digital envelope has been added to the buzzer signal, the BDTY[2:0] settings will be invalid due to the control of the duty ratio. 15-2 Seiko Epson Corporation S1C6F016 TECHNICAL MANUAL (Rev. 1.1) 15 SOunD GeneRaTOR 15.5 Digital envelope A digital envelope for duty control can be added to the buzzer signal. The envelope can be controlled by staged changing of the same duty envelope as detailed in Table 15.4.2 in the preceding item from level 1 (maximum) to level 8 (minimum). The addition of an envelope to the buzzer signal can be done by writing "1" into ENON, but when "0" has been written it is not added. When a buzzer signal output is begun (writing "1" into BZE) after setting ENON, the duty ratio shifts to level 1 (maximum) and changes in stages to level 8. When attenuated down to level 8 (minimum), it is retained at that level. The duty ratio can be returned to maximum, by writing "1" into register ENRST during output of an envelope attached buzzer signal. The envelope attenuation time (time for changing of the duty ratio) can be selected by the register ENRTM. The time for a 1 stage level change is 62.5 msec (16 Hz), when "0" has been written into ENRTM and 125 msec (8 Hz), when to "1" has been written. However, there is also a max. 4 msec error from envelope ON, up to the first change. Figure 15.5.1 shows the timing chart of the digital envelope. No change of duty level BZFQ[2:0] ENON ENRST ENRTM BZE BZ signal duty ratio Level 1 (Max.) 2 3 4 5 6 7 8 (Min.) t01 t02 t03 t04 t05 t06 t07 +0 62.5 -4 t01 t01 = msec t02-07 = 62.5 msec t11 t12 t13 t14 t15 t16 t17 +0 125 -4 t11 = msec t12-17 = 125 msec Figure 15.5.1 Timing chart for digital envelope 15.6 One-shot output The sound generator has a one-shot output function for outputting a short duration buzzer signal for key operation sounds and similar effects. Either 125 msec or 31.25 msec can be selected by SHTPW register for one-shot buzzer signal output time. The output of the one-shot buzzer is controlled by writing "1" into the one-shot buzzer trigger BZSHT. When this trigger has been assigned, a buzzer signal in synchronization with the internal 256 Hz signal is output from the buzzer output terminal. Thereafter, when the set time has elapsed, a buzzer signal in synchronization with the 256 Hz signal goes off in the same manner as for the start of output. The BZSHT also permits reading. When BZSHT is "1," the one-shot output circuit is in operation (during one-shot output) and when it is "0," it shows that the circuit is in the ready to output status. In addition, it can also terminate one-shot output prior to the elapsing of the set time. This is done by writing a "1" into the one-shot buzzer stop BZSTP. In this case as well, the buzzer signal goes off in synchronization with the 256 Hz signal. When "1" is written to BZSHT again during a one-shot output, a new one-shot output for 125 msec or 31.25 msec starts from that point (in synchronization with the 256 Hz signal). The one-shot output cannot add an envelope for short durations. However, the sound level can be set by selecting the duty ratio, and the frequency can also be set. One-shot output is invalid during normal buzzer output (during BZE = "1"). Figure 15.6.1 shows timing chart for one-shot output. S1C6F016 Technical Manual (Rev. 1.1) Seiko Epson Corporation 15-3 15 SOunD GeneRaTOR 256 Hz SHTPW BZSHT (W) BZSHT (R) BZSTP BZ output Figure 15.6.1 Timing chart for one-shot output 15.7 i/O Memory of Sound Generator Table 15.7.1 shows the I/O addresses and the control bits for the sound generator. Table 15.7.1 Control bits of sound generator Address Register name R/W Default R/W R/W R/W R/W Enable Enable Enable Enable 0 0 0 0 Disable Disable Disable Disable Integer multiplier clock enable Sound generator clock enable Stopwatch timer clock enable Clock timer clock enable FF44H D3 D2 D1 D0 enRTM enRST (*3) enOn BZe R/W 0 1 1 sec W (Reset) 1 Reset R/W 0 1 On R/W 0 1 Enable 0 0 0 0 0.5 sec Invalid Off Disable Envelope releasing time selection Envelope reset (writing) Envelope On/Off Buzzer output enable D0 ShTPW R - (*2) W 0 R/W 0 R/W 0 1 1 1 1 Function MDCKE SGCKe SWCKE RTCKE FF45H D3 0 (*3) D2 BZSTP (*3) D1 BZShT 0 0 0 0 Setting/data FF16H D3 D2 D1 D0 - 1 Stop 1 Trigger (W) Busy (R) 1 125 msec 0 Invalid 0 Invalid (W) Ready (R) 0 31.25 msec FF46H D3 D2 D1 D0 0 (*3) BZFQ2 BZFQ1 BZFQ0 R - (*2) R/W 0 R/W 0 R/W 0 7 1170.3 6 1365.3 5 1638.4 - 4 2048.0 3 2340.6 2 2730.7 FF47H D3 D2 D1 D0 0 (*3) BDTY2 BDTY1 BDTY0 R - (*2) R/W 0 R/W 0 R/W 0 7 Level 8 6 Level 7 5 Level 6 - 4 Level 5 3 Level 4 2 Level 3 *1: Initial value at initial reset *2: Not set in the circuit 1 3276.8 0 4096.0 1 Level 2 0 Level 1 (max.) Unused 1-shot buzzer stop (writing) 1-shot buzzer trigger (writing) 1-shot buzzer status (reading) 1-shot buzzer pulse width setting Unused Buzzer frequency (Hz) selection Unused Buzzer signal duty ratio selection *3: Constantly "0" when being read SGCKe: Sound generator clock enable register (FF16h*D2) Controls the clock supply to the sound generator. When "1" is written: On When "0" is written: Off Reading: Valid When "1" is written to SGCKE, the sound generator operating clock is supplied from the clock manager. If it is not necessary to run the sound generator, stop the clock supply by setting SGCKE to "0" to reduce current consumption. At initial reset, this register is set to "0." BZe: Buzzer output enable register (FF44h*D0) Controls the buzzer signal output. When "1" is written: Buzzer output On When "0" is written: Buzzer output Off Reading: Valid When "1" is written to BZE, the BZ signal is output from the BZ (P12) terminal. The I/O control register IOC12 and data register P12 settings are ineffective while the BZ signal is being output. When BZE is set to "0," the P12 port is configured as a general-purpose DC input/output port. At initial reset, this register is set to "0." 15-4 Seiko Epson Corporation S1C6F016 TECHNICAL MANUAL (Rev. 1.1) 15 SOunD GeneRaTOR enOn: envelope On/Off control register (FF44h*D1) Controls the addition of an envelope onto the buzzer signal. When "1" is written: On When "0" is written: Off Reading: Valid Writing "1" to ENON causes an envelope to be added during buzzer signal output. When "0" has been written, an envelope is not added. At initial reset, this register is set to "0." enRST: envelope reset (FF44h*D2) Resets the envelope. When "1" is written: Reset When "0" is written: No operation Reading: Always "0" Writing "1" to ENRST resets envelope and the duty ratio becomes maximum. If an envelope has not been added (ENON = "0") and if no buzzer signal is being output, the reset becomes invalid. Writing "0" is also invalid. This bit is dedicated for writing, and is always "0" for reading. enRTM: envelope releasing time select register (FF44h*D3) Selects the envelope releasing time that is added to the buzzer signal. When "1" is written: 1.0 sec (125 msec x 7 = 875 msec) When "0" is written: 0.5 sec (62.5 msec x 7 = 437.5 msec) Reading: Valid The releasing time of the digital envelope is determined by the time for converting the duty ratio. When "1" is written to ENRTM, it becomes 125 msec (8 Hz) units and when "0" is written, it becomes 62.5 msec (16 Hz) units. At initial reset, this register is set to "0." ShTPW: One-shot buzzer pulse width setting register (FF45h*D0) Selects the output time of the one-shot buzzer. When "1" is written: 125 msec When "0" is written: 31.25 msec Reading: Valid Writing "1" to SHTPW causes the one-short output time to be set at 125 msec, and writing "0" causes it to be set to 31.25 msec. It does not affect normal buzzer output. At initial reset, this register is set to "0." BZShT: One-shot buzzer trigger/status (FF45h*D1) Controls the one-shot buzzer output. When writing When "1" is written: Trigger When "0" is written: No operation Writing "1" to BZSHT causes the one-short output circuit to operate and a buzzer signal to be output. This output is automatically turned off after the time set by SHTPW has elapsed. The one-shot output is only valid when the normal buzzer output is off (BZE = "0") and will be invalid when the normal buzzer output is on (BZE = "1"). When a re-trigger is assigned during a one-shot output, the one-shot output time set with SHTPW is measured again from that point (time extension). When reading When "1" is read: BUSY When "0" is read: READY During reading BZSHT shows the operation status of the one-shot output circuit. During one-shot output, BZSHT becomes "1" and the output goes off, it shifts to "0." At initial reset, this bit is set to "0." S1C6F016 Technical Manual (Rev. 1.1) Seiko Epson Corporation 15-5 15 SOunD GeneRaTOR BZSTP: One-shot buzzer stop (FF45h*D2) Stops the one-shot buzzer output. When "1" is written: Stop When "0" is written: No operation Reading: Always "0" Writing "1" to BZSTP permits the one-shot buzzer output to be turned off prior to the elapsing of the time set by SHTPW. Writing "0" is invalid and writing "1" is also invalid except during one-shot output. This bit is dedicated for writing, and is always "0" for reading. BZFQ[2:0]: Buzzer frequency select register (FF46h*D[2:0]) Selects the buzzer signal frequency. Table 15.7.2 Buzzer signal frequency setting BZFQ[2:0] Buzzer frequency (Hz) 0 4096.0 1 3276.8 2 2730.7 3 2340.6 4 2048.0 5 1638.4 6 1365.3 7 1170.3 Select the buzzer frequency from among the above 8 types that have divided the oscillation clock. At initial reset, this register is set to "0." BDTY[2:0]: Duty level select register (FF47h*D[2:0]) Selects the duty ratio of the buzzer signal as shown in Table 15.7.3. Level Level 1 (Max.) Level 2 Level 3 Level 4 Level 5 Level 6 Level 7 Level 8 (Min.) Table 15.7.3 Duty ratio setting Duty ratio by buzzer frequency (Hz) BDTY[2:0] 4096.0 3276.8 2730.7 2340.6 2048.0 1638.4 1365.3 1170.3 0 8/16 8/20 12/24 12/28 1 7/16 7/20 11/24 11/28 2 6/16 6/20 10/24 10/28 3 5/16 5/20 9/24 9/28 4 4/16 4/20 8/24 8/28 5 3/16 3/20 7/24 7/28 6 2/16 2/20 6/24 6/28 7 1/16 1/20 5/24 5/28 The sound level of this buzzer can be set by selecting this duty ratio. However, when the envelope has been set to on (ENON = "1"), this setting becomes invalid. At initial reset, this register is set to "0." 15.8 Precautions * Since it generates a buzzer signal that is out of synchronization with the BZE register, hazards may at times be produced when the signal goes on/off due to the setting of the BZE register. * The one-shot output is only valid when the normal buzzer output is off (BZE = "0") and will be invalid when the normal buzzer output is on (BZE = "1"). 15-6 Seiko Epson Corporation S1C6F016 TECHNICAL MANUAL (Rev. 1.1) 16 inTeGeR MulTiPlieR 16 Integer Multiplier 16.1 Configuration of integer Multiplier The S1C6F016 has a built-in unsigned-integer multiplier. This multiplier performs 8 bits x 8 bits of multiplication or 16 bits / 8 bits of division and returns the results and three flag states. Figure 16.1.1 shows the configuration of the integer multiplier. Data bus Destination register High-order byte (DRH) Low-order byte (DRL) Clock manager System clock Source register (SR) Temporary register A Temporary register B Operation control (CALMD) Adder Flag (NF/VF/ZF) Figure 16.1.1 Configuration of the integer multiplier 16.2 Controlling Clock Manager The integer multiplier operates with the clock supplied by the clock manager (CPU operating clock selected by OSCC and CLKCHG). Before the integer multiplier can be run, write "1" to the MDCKE register to supply the operating clock to the integer multiplier. MDCKE 1 0 Table 16.2.1 Controlling integer multiplier clock Integer multiplier clock When CLKCHG = "0": fOSC1 (32 kHz) When OSCC = 1," CLKCHG = "1": fOSC3 Off If it is not necessary to run the integer multiplier, stop the clock supply by setting MDCKE to "0" to reduce current consumption. 16.3 Multiplication Mode To perform a multiplication, set the multiplier to the source register (SR) and the multiplicand to the low-order 8 bits (DRL) of the destination register, then write "0" to the calculation mode select register (CALMD). The multiplication takes 10 CPU clock cycles from writing "0" to CALMD until the 16-bit product is loaded into the destination register (DRH and DRL). At the same time the result is loaded, the operation flags (NF, VF and ZF) are updated. The following shows the conditions that change the operation flag states and examples of multiplication. N flag: Set when the MSB of DRH is "1" and reset when it is "0." V flag: Always reset after a multiplication. Z flag: Set when the 16-bit value in DRH/DRL is 0000H and reset when it is not 0000H. <examples of multiplication> DRL (multiplicand) 00H 64H C8H C8H SR (multiplier) 64H 58H 58H A5H S1C6F016 Technical Manual (Rev. 1.1) DRH/DRL (product) 0000H 2260H 44C0H 80E8H Seiko Epson Corporation NF 0 0 0 1 VF 0 0 0 0 ZF 1 0 0 0 16-1 16 inTeGeR MulTiPlieR 16.4 Division Mode To perform a division, set the divisor to the source register (SR) and the dividend to the destination register (DRH and DRL), then write "1" to the calculation mode select register (CALMD). The division takes 10 CPU clock cycles from writing "1" to CALMD until the quotient is loaded into the low-order 8 bits (DRL) of the destination register and the remainder is loaded into the high-order 8 bits (DRH) of the destination register. At the same time the result is loaded, the operation flags (NF, VF and ZF) are updated. However, when an overflow results (if the quotient exceeds the 8-bit range), the destination register (DRH and DRL) does not change its contents as it maintains the dividend. The following shows the conditions that change the operation flag states and examples of division. N flag: Set when the MSB of DRL is "1" and reset when it is "0." V flag: Set when the quotient exceeds the 8-bit range and reset when it is within the 8-bit range. Z flag: Set when the 8-bit value in DRL is 00H and reset when it is not 00H. <examples of division> DRH/DRL (dividend) SR (divisor) 1A16H 64H 332CH 64H 0000H 58H 2468H 13H DRL (quotient) DRH (remainder) 42H 4EH 83H 00H 00H 00H 68H 24H NF 0 1 0 1 VF 0 0 0 1 ZF 0 0 1 0 In the example of "2468H" / "13H" shown above, DRH/DRL maintains the dividend because the quotient overflows the 8-bit. To get the correct results when an overflow has occurred, perform the division with two steps as shown below. 1. Divide the high-order 8 bits of the dividend (24H) by the divisor (13H) and then store the quotient (01H) to memory. DRH/DRL (dividend) SR (divisor) 0024H 13H DRL (quotient) DRH (remainder) 01H 11H NF 0 VF 0 ZF 0 2. Keep the remainder (11H) in DRH and load the low-order 8 bits of the dividend (68H) to DRL, then perform division again. DRH/DRL (dividend) SR (divisor) 1168H 13H DRL (quotient) DRH (remainder) EAH 0AH NF 1 VF 0 ZF 0 The correct result is obtained as the quotient = 01EAH (the first and second results of DRL are merged) and the remainder = 0AH. However, since the operation flags (NF/VF/ZF) are changed in each step, they cannot indicate the states according to the final operation results. Note: Make sure that the division results are correct using software as the hardware does not check. 16.5 execution Cycle Both the multiplication and division take 10 CPU cycles for an operation. Therefore, before the results can be read from the destination register DRH/DRL, wait at least 5 bus cycles after writing to CALMD. The same applies to reading the operation flags NF/VF/ZF. The following shows a sample program. ldb %ext, src_data@h ldb %xl, src_data@l ; Set RAM address for operand ldb %ext, au@h ldb %yl, au@l ; Set multiplier I/O memory address ; ldb %ba, [%x]+ ldb [%y]+, %ba ; Set data to SR ldb %ba, [%x]+ ldb [%y]+, %ba ; Set data to DRL ldb %ba, [%x]+ ldb [%y]+, %ba ; Set data to DRH ; ld [%y], 0b0001 ; Start operation (select division mode) ; 16-2 Seiko Epson Corporation S1C6F016 TECHNICAL MANUAL (Rev. 1.1) 16 inTeGeR MulTiPlieR ldb %ext, rslt_data@h ldb %xl, rslt_data@l nop nop nop ; Set result store address ; Dummy instructions to wait end of operation ; bit jrnz [%y], 0b0100 overflow ; Jump to error routine if VF = "1" add %y, -4 ; Set DRL again ldb ldb ldb ldb %ba, [%y]+ [%x]+, %ba %ba, [%y]+ [%x]+, %ba ; ; ; Store result (quotient) into RAM ; Store result (remainder) into RAM 16.6 i/O Memory of integer Multiplier Table 16.6.1 shows the I/O addresses and the control bits for the integer multiplier. Table 16.6.1 Control bits of integer multiplier Address Register name R/W Default Setting/data FF16H D3 D2 D1 D0 MDCKe SGCKE SWCKE RTCKE R/W R/W R/W R/W 0 0 0 0 FF70H D3 D2 D1 D0 SR3 SR2 SR1 SR0 R/W R/W R/W R/W x x x x FF71H D3 D2 D1 D0 SR7 SR6 SR5 SR4 R/W R/W R/W R/W x x x x FF72H D3 D2 D1 D0 DRl3 DRl2 DRl1 DRl0 R/W R/W R/W R/W x x x x 0H-FH FF73H D3 D2 D1 D0 DRl7 DRl6 DRl5 DRl4 R/W R/W R/W R/W x x x x 0H-FH FF74H D3 D2 D1 D0 DRh3 DRh2 DRh1 DRh0 R/W R/W R/W R/W x x x x 0H-FH FF75H D3 D2 D1 D0 DRh7 DRh6 DRh5 DRh4 R/W R/W R/W R/W x x x x 0H-FH FF76H D3 D2 D1 D0 nF VF ZF CalMD R R R R/W 0 0 0 0 *1: Initial value at initial reset S1C6F016 Technical Manual (Rev. 1.1) 1 1 1 1 Enable Enable Enable Enable 0 0 0 0 Disable Disable Disable Disable 0H-FH 0H-FH 1 1 1 1 Negative Overflow Zero Division (W) Run (R) *2: Not set in the circuit 0 0 0 0 Positive No No Multiplication (W) Stop (R) Function Integer multiplier clock enable Sound generator clock enable Stopwatch timer clock enable Clock timer clock enable Source register (low-order 4 bits) SR0 = LSB Source register (high-order 4 bits) SR7 = MSB Low-order 8-bit destination register (low-order 4 bits) DRL0 = LSB Low-order 8-bit destination register (high-order 4 bits) DRL7 = MSB High-order 8-bit destination register (low-order 4 bits) DRH0 = LSB High-order 8-bit destination register (high-order 4 bits) DRH7 = MSB Negative flag Overflow flag Zero flag Calculation mode selection (writing) Operation status (reading) *3: Constantly "0" when being read Seiko Epson Corporation 16-3 16 inTeGeR MulTiPlieR MDCKe: integer multiplier clock enable register (FF16h*D3) Controls the operating clock supply to the integer multiplier. When "1" is written: On When "0" is written: Off Reading: Valid When "1" is written to MDCKE, the integer multiplier operating clock (CPU operating clock selected by OSCC and CLKCHG) is supplied from the clock manager. If it is not necessary to run the integer multiplier, stop the clock supply by setting MDCKE to "0" to reduce current consumption. At initial reset, this register is set to "0." SR[7:0]: Source register (FF71h, FF70h) Used to set multipliers and divisors. Set the low-order 4 bits of data to SR[3:0] and the high-order 4 bits to SR[7:4]. This register maintains the latest set value until the next writing, so it is not necessary to set data for each operation if the same multiplier and divisor is used in a series of operations. At initial reset, this register is undefined. DRl[7:0]: Destination register low-order 8 bits (FF73h, FF72h) Used to set multiplicands and low-order 8 bits of dividends. Set the low-order 4 bits of data to DRL[3:0] and the high-order 4 bits to DRL[7:4]. Data written to this register is loaded to the arithmetic circuit when an operation starts (by writing to FF76H*D0), and then a multiplication or a division is performed in 10 CPU clock cycles (5 bus cycles). After the operation has finished, the low-order 8 bits of the product or the quotient are loaded to this register. However, if an overflow occurs in a division process, the quotient is not loaded and the low-order 8 bits of the dividend remains. At initial reset, this register is undefined. DRh[7:0]: Destination register high-order 8 bits (FF75h, FF74h) Used to set high-order 8 bits of dividends. Set the low-order 4 bits of data to DRH[3:0] and the high-order 4 bits to DRH[7:4]. At the start of a multiplication (by writing "0" to FF76H*D0), the contents in this register are ignored. After 10 CPU cycles (5 bus cycles) of multiplication process has finished, the high-order 8 bits of the product are loaded in this register. In a division process, data written to this register is loaded to the arithmetic circuit when an operation starts (by writing "1" to FF76H*D0), and then a division is performed in 10 CPU clock cycles (5 bus cycles). After the operation has finished, the remainder is loaded to this register. However, if an overflow occurs in a division process, the remainder is not loaded and the high-order 8 bits of the dividend remains. At initial reset, this register is undefined. CalMD: Calculation mode select register/operation status (FF76h*D0) Selects multiplication or division mode and starts operation. When "1" is written: When "0" is written: When "1" is read: When "0" is read: Selects/starts division Selects/starts multiplication Under operating Operation has finished Writing to this register starts the specified operation. After that, this register is set to "1" and returns to "0" when the multiplication or division process has finished. At initial reset, this register is reset to "0." ZF: Zero flag (FF76h*D1) Indicates whether the operation result is zero or not. When "1" is read: Zero When "0" is read: Not zero Writing: Invalid ZF is a read-only bit, so writing operation is invalid. At initial reset, this flag is set to "0." 16-4 Seiko Epson Corporation S1C6F016 TECHNICAL MANUAL (Rev. 1.1) 16 inTeGeR MulTiPlieR VF: Overflow flag (FF76h*D2) Indicates whether an overflow has occurred or not in a division process. When "1" is read: Overflow occurred When "0" is read: Overflow has not occurred Writing: Invalid When a multiplication process has finished, this flag is always set to "0." VF is a read-only bit, so writing operation is invalid. At initial reset, this flag is set to "0." nF: negative flag (FF76h*D3) Indicates whether the operation result is a positive value or a negative value. When "1" is read: Negative value (MSB of the results is "1") When "0" is read: Positive value (MSB of the results is "0") Writing: Invalid NF is a read-only bit, so writing operation is invalid. At initial reset, this flag is set to "0." 16.7 Precautions An operation process takes 10 CPU clock cycles (5 bus cycles) after writing to the calculation mode select register CALMD until the operation result is set to the destination register DRH/DRL and the operation flags. While this operation is in process, do not read/write from/to the destination register DRH/DRL and do not read NF/VF/ZF. S1C6F016 Technical Manual (Rev. 1.1) Seiko Epson Corporation 16-5 17 R/F COnVeRTeR 17 R/F Converter 17.1 Configuration of R/F Converter The S1C6F016 has a built-in CR oscillation type R/F converter that can be used as an A/D converter. Two systems (channel 0 and channel 1) of CR oscillation circuits are built into the R/F converter, so it is possible to compose two types of R/F conversion circuits by connecting different sensors to each CR oscillation circuit. Channel 0 can be used as an R/F (Resistor/Frequency) conversion circuit using a DC bias resistive sensor such as a thermistor, and channel 1 can be used as an R/F conversion circuit the same as channel 0, or for an AC bias resistive sensor such as a humidity sensor. The channel to be used and sensor type for channel 1 are selected with software. Resistance value (relative value to external reference resistance) of the resistive sensor that has been connected to the sensor input terminal is converted into frequency by the CR oscillation circuit and the number of clocks is counted in the built-in measurement counter. By reading the value of the measurement counter, it can obtain the data after digitally-converting the value detected by the sensor. Various sensor circuits such as temperature/humidity measurement circuits can be easily realized using this R/F converter. The configuration of the R/F converter is shown in Figure 17.1.1. OSC1 oscillation circuit (fOSC1) OSC3 oscillation circuit (fOSC3) RFCKS[2:0] R/F converter clock (fTCCLK) Clock manager Time base counter TC00 TC04 TC08 TC12 TC16 -TC03 -TC07 -TC11 -TC15 -TC19 Data bus Programmable timer 1 underflow signal Measurement counter Measurement clock (fMCCLK) counter control RFRUNR Interrupt control Time base counter control RFRUNS MC00 MC04 MC08 MC12 MC16 -MC03 -MC07 -MC11 -MC15 -MC19 Measurement counter Channel control circuit Ch. 0 oscillation control circuit VDD Interrupt request OVMC Ch. 1 oscillation control circuit ERF[1:0] VSS RFOUT (P50) OVTC VDD VSS RFIN0 SEN0 (P53) (P51) REF0 (P52) RFIN1 HUD SEN1 REF1 Figure 17.1.1 Configuration of R/F converter 17.2 Controlling Operating Clock The R/F converter uses the clock supplied from the clock manager as its operating clock and the count clock for the time base counter. The clock manager generates six R/F converter clocks by dividing the OSC1 and OSC3 clocks. The R/F converter clock can be selected from seven types (the above six clocks and the programmable timer 1 output clock). Use the RFCKS[2:0] register to select one of them as shown in Table 17.2.1. S1C6F016 Technical Manual (Rev. 1.1) Seiko Epson Corporation 17-1 17 R/F COnVeRTeR Table 17.2.1 R/F converter clock frequencies RFCKS[2:0] RFC clock 7 fOSC3 / 4 6 fOSC3 / 2 5 fOSC3 / 1 4 Programmable timer 1 3 fOSC1 / 4 (8 kHz) 2 fOSC1 / 2 (16 kHz) 1 fOSC1 / 1 (32 kHz) 0 Off fOSC1: OSC1 oscillation frequency. ( ) indicates the frequency when fOSC1 = 32 kHz. fOSC3: OSC3 oscillation frequency When programmable timer 1 is selected, the programmable timer 1 underflow signal is divided by 2 before it is used as the R/F converter clock. In this case, the programmable timer must be controlled before operating the serial interface. Refer to the "Programmable Timer" chapter for controlling the programmable timer. If it is not necessary to run the R/F converter, stop the clock supply by setting RFCKS[2:0] to "0" to reduce current consumption. 17.3 Connection Terminals and CR Oscillation Circuit The R/F converter channel 0 input/output terminals and the RFOUT output terminal are shared with the I/O port (P50-P53), and the terminal functions must be switched with software when using these terminals for the R/F converter. By setting the ERF[1:0] register to other than "0," P53, P52 and P51 are configured as the RFIN0, REF0 and SEN0 terminals, respectively. The RFOUT output through the P50 port is effective when "1" is written to the RFOUT register. When the RFOUT register is "0," P50 is used as an I/O port. The table below lists the correspondence between the P50 to P53 terminals and the R/F converter input/output. Table 17.3.1 Setting input/output terminal functions Terminal name R/F converter input/output P50 RFOUT P51 SEN0 P52 REF0 P53 RFIN0 Note: At initial reset, P50 to P53 are configured as the I/O ports. When using the R/F converter channel 0, switch the terminal functions (ERF[1:0] = "1," RFOUT = "1") in the initialize routine. Two systems of CR oscillation circuits, channel 0 and channel 1, are built into the R/F converter and perform CR oscillation with the external resistor and capacitor. The counter that is used to obtain R/F converted values is shared with channel 0 and channel 1. Therefore, operation for two channels is realized by switching the CR oscillation circuit that performs R/F conversion. The channel to perform R/F conversion and the sensor type should be selected using the ERF[1:0] register in advance. Table 17.3.2 Selecting channel and sensor type ERF[1:0] Channel and sensor type 3 Ch.1 DC 2 Ch.1 AC 1 Ch.0 DC 0 I/O DC: R/F conversion using a DC bias resistive sensor such as a thermistor AC: R/F conversion using an AC bias resistive sensor such as a humidity sensor 17-2 Seiko Epson Corporation S1C6F016 TECHNICAL MANUAL (Rev. 1.1) 17 R/F COnVeRTeR (1) R/F conversion using a DC bias resistive sensor such as a thermistor Channel 0 supports this conversion method only, and channel 1 is selected into this method by setting ERF[1:0] to "3." This method should be selected for R/F conversion using a normal resistive sensor (DC bias), such as temperature measurement using a thermistor. At initial reset, channel 1 is set into this conversion method. Figure 17.3.1 shows the connection diagram of external elements. HUD SEN0 (P51) REF0 (P52) RFIN0 (P53) Channel 0 Open SEN1 RSEN RSEN REF1 RREF RREF RFIN1 CRFC CRFC Channel 1 VSS VSS RSEN: Resistive sensor (e.g. thermistor) RREF: Reference resistor CRFC: Oscillating capacitor Figure 17.3.1 Connection diagram in case of R/F conversion CR oscillation waveforms are shaped by the schmitt trigger and sent to the measurement counter. The clock sent to the measurement counter is also output from the RFOUT terminal while the sensor is oscillating. As a result, the oscillation frequency can be measured by an oscilloscope or other equipment. Since this monitor has no effect on oscillation frequency, it can be used to adjust R/F conversion accuracy. Oscillation waveforms and waveforms output from the RFOUT terminal are shown in Figure 17.3.2. RFIN0/1 terminal VDD VSS RFOUT output (Measurement counter clock) VDD VSS Figure 17.3.2 Oscillation waveform (2) R/F conversion using an aC bias resistive sensor such as a humidity sensor This conversion is possible only in channel 1, and this method is selected by setting ERF[1:0] to "2." This is basically the same as the R/F conversion described above (1), but the AC bias circuit works for a sensor (e.g. humidity sensor) to which DC bias cannot be applied for a long time. The oscillating operation by reference resistance is the same as the R/F conversion described above (1). Figure 17.3.3 shows the connection diagram of external devices. HUD RSEN SEN1 REF1 RREF RFIN1 CRFC Channel 1 VSS RSEN: Resistive sensor (e.g. humidity sensor) RREF: Reference resistor CRFC: Oscillating capacitor Figure 17.2.3 Connection diagram of resistive humidity sensor The oscillation waveform is the same as Figure 17.3.2. S1C6F016 Technical Manual (Rev. 1.1) Seiko Epson Corporation 17-3 17 R/F COnVeRTeR 17.4 Operation of R/F Conversion Counter The R/F converter incorporates two types of counters: measurement counter MC[19:0] and time base counter TC[19:0]. The measurement counter is a 20-bit up counter that counts the CR oscillation clock with the reference resistance or sensor selected by software. The R/F conversion results can be obtained by reading this counter. The time base counter is a 20-bit up/down counter to equal both oscillation times for the reference resistance and the sensor. The time base counter uses the R/F converter clock selected by the RFCKS[2:0] register. Each counter permits reading and writing on a 4-bit basis. First start an R/F conversion for the reference resistance. The measurement counter starts counting up and the time base counter starts counting down. The counters stop counting when the measurement counter overflows ("FFFFFH" "00000H"). By resetting the time base counter to "00000H" before starting an R/F conversion for the reference resistance, the reference oscillation time will be obtained from the time base counter. Then start an R/F conversion for the sensor, the measurement counter starts counting up from "00000H" and the time base counter starts counting up from the counted value. The counters stop counting when the time base counter overflows ("FFFFFH" "00000H"). The oscillation time in this phase is the same as that of the reference resistance. Therefore, by converting an appropriate initial value for counting of the oscillation of the reference resistance into a complement (value subtracted from "00000H") and setting it into the measurement counter before starting to count, the number of counts for the sensor oscillation is obtained by reading the measurement counter after the R/F conversion. In other words, the difference between the reference resistance and sensor oscillation frequencies can be found easily. For instance, if resistance values of the reference resistance and the sensor are equivalent, the same value as the initial value before converting into a complement will be obtained as the result. The time base counter allows reading of the counter value and presetting of data. By saving the counter value after the reference oscillation has completed into the RAM, the subsequent reference oscillation phase can be omitted. The sensor oscillation can be started after setting the saved value to the time base counter and "00000H" to the measurement counter. Note: When setting the measurement counter or time base counter, always write 5 words of data continuously in order from the lower address (FF62H FF63H FF64H FF65H FF66H, FF67H FF68H FF69H FF6AH FF6BH). Furthermore, an LD instruction should be used for writing data to the measurement counter and a read-modify-write instruction (AND, OR, ADD, SUB, etc.) cannot be used. If data other than low-order 4 bits is written, the counter cannot be set to the desired value. R/F conversion sequence An R/F conversion for the reference resistance starts by writing "1" to the RFRUNR register. However, an initial value must be set to the measurement counter and the time base counter must be cleared to "00000H" before starting the R/F conversion. When R/F conversion is initiated by the RFRUNR register, oscillation by the reference resistance begins, and the measurement counter starts counting up from the initial value by the oscillation clock. The time base counter also starts counting down by the R/F converter clock. If the measurement counter becomes "00000H" due to overflow, the oscillation is terminated. At the same time an interrupt occurs and the RFRUNR register is set to "0," and the R/F converter circuit stops operation completely. The time base counter value should be saved into the RAM for R/F conversion of the sensor. Figure 17.4.1 shows a timing chart for the reference oscillation. 17-4 Seiko Epson Corporation S1C6F016 TECHNICAL MANUAL (Rev. 1.1) 17 R/F COnVeRTeR R/F converter clock RFRUNR register RFIN0/1 Time base counter clock Time base counter Time base counter starts counting (count-down) 00000H FFFFFH FFFFEH FFFFDH FFFFCH FFFFBH x+3 x+2 Measurement counter clock (RFOUT output) x+1 x Measurement counter starts counting Measurement counter n* n+1 n+2 FFFFFH Starts measurement of reference resistance *: Initial setting value (complement) for counting of reference resistance 00000H Interrupt is generated Figure 17.4.1 Reference oscillation timing chart An R/F conversion for the sensor starts by writing "1" to the RFRUNS register. When performing this sensor oscillation after a reference oscillation has completed, it is not necessary to set initial values to the counters. If converting the sensor resistance independently, the measurement counter must be set to "00000H" and the time base counter must be set to the value measured at the time of a reference oscillation. When R/F conversion is initiated by the RFRUNS register, oscillation by the sensor begins, and the measurement counter starts counting up from "00000H" by the oscillation clock. The time base counter also starts counting up by the R/F converter clock. If the time base counter becomes "00000H," the oscillation is terminated. At the same time an interrupt occurs and the RFRUNS register is set to "0," and the R/F converter circuit stops operation completely. Figure 17.4.2 shows a timing chart for the sensor oscillation. R/F converter clock RFRUNS register RFIN0/1 Time base counter clock Time base counter Measurement counter clock (RFOUT output) Measurement counter x x+1 Time base counter starts counting (count-up) x+2 x+3 x+4 x+5 FFFFEH FFFFFH 00000H Measurement counter starts counting 00000H 00001H 00002H Starts measurement of sensor *: Number of counts during sensor oscillation n-1 n* Time up Interrupt is generated Figure 17.4.2 Sensor oscillation timing chart By the above operation, the sensor is oscillated for the same period of time as the reference resistance is oscillated. Therefore, the difference in oscillation frequency can be measured from the values counted by the measurement counter. Since the reference resistance is oscillated until the measurement counter overflows, an appropriate initial value needs to be set before R/F conversion is started. If a smaller initial value is set, a longer counting period is possible, thereby ensuring more accurate detection. Convert the initial value into a complement (value subtracted from "00000H") before setting it on the measurement counter. Since the data output from the measurement counter after R/F conversion matches data detected by the sensor, process the difference between that value and the initial value before it is converted into a complement according to the program and calculate the target value. The above operations are shown in Figure 17.4.3. S1C6F016 Technical Manual (Rev. 1.1) Seiko Epson Corporation 17-5 17 R/F COnVeRTeR Setting by software Reference oscillation (1) Set the initial value Measurement counter (MC) 00000H-n (2) Start reference oscillation (Set RFRUNR to "1") Sensor oscillation (1) Set the initial value (2) Start sensor oscillation (Set RFRUNS to "1") (00000H) (00000H-n) Time base counter (TC) 00000H 00000H Count up Count down FFFFFH : 0 x 0 (x) x Count up Count up : FFFFFH m 00000H (3) Read the measurement counter and process the m - n value by the program Set the complement of the initial value n on the measurement counter. Set "00000H" on the time base counter. Oscillation by reference resistance The CR oscillation stops when the measurement counter overflows and an interrupt occurs. Save the TC value into the memory. (Set "00000H" on the measurement counter. Set x on the time base counter.) Oscillation by sensor When the value of the time base counter reaches "00000H," oscillation and counting stop, and an interrupt occurs. Figure 17.4.3 Sequence of R/F conversion Note: Set the initial value of the measurement counter taking into account the measurable range and the overflow of counters. 17.5 interrupt Function The R/F converter has a function which allows interrupt to occur when an R/F conversion has completed or an error has occurred. When the measurement counter reaches "00000H" during counting of the reference oscillation, both counters stop counting and RFRUNR is set to "0." At the same time, the interrupt factor flag IRFR is set to "1." When the time base counter reaches "00000H" during counting of the sensor oscillation, both counters stop counting and RFRUNS is set to "0." At the same time, the interrupt factor flag IRFS is set to "1." If the measurement counter overflows during counting of the sensor oscillation, both counters stop counting and RFRUNS is set to "0." In this case, the interrupt factor flag IRFE is set to "1." At the same time, the OVMC flag is also set to 1. If the time base counter overflows during counting of the reference oscillation, both counters stop counting and RFRUNR is set to "0." In this case, the interrupt factor flag IRFE is set to "1." At the same time, the OVTC flag is also set to 1. These interrupt factors allow masking by the interrupt mask registers EIRFR, EIRFS and EIRFE, and an interrupt is generated to the CPU when these registers are set to "1." When the interrupt mask register is set to "0," an interrupt is not generated to the CPU even if the interrupt factor flag is set to "1." The interrupt factor flag is reset to "0" by writing "1." Timing of interrupt by the R/F converter is shown in Figures 17.5.1 to 17.5.4. 17-6 Seiko Epson Corporation S1C6F016 TECHNICAL MANUAL (Rev. 1.1) 17 R/F COnVeRTeR R/F converter clock RFRUNR register Time base counter Count-down FFFFFH FFFFEH FFFFDH FFFFCH FFFFBH 0 x+3 x+2 x+1 x Measurement counter clock Measurement counter n n+1 n+2 n+3 FFFFD FFFFEH FFFFFH 0 Oscillation by reference resistance IRFR Interrupt request Figure 17.5.1 Reference oscillate completion interrupt R/F converter clock RFRUNS register Time base counter x+1 x x+2 x+3 Count-up x+4 x+5 FFFFEH FFFFFH 0 Measurement counter clock Measurement counter 0 1 2 3 m-3 m-2 m-1 m Oscillation by sensor resistance IRFS Interrupt request Figure 17.5.2 Sensor oscillate completion interrupt R/F converter clock RFRUNS register Time base counter x+1 x x+2 x+3 Count-up x+4 x+5 y-2 y-1 y Measurement counter clock Measurement counter 0 1 2 Overflow FFFFDH FFFFEH FFFFFH 0 3 Oscillation by sensor resistance IRFE, OVMC Interrupt request Figure 17.5.3 Error interrupt due to measurement counter overflow R/F converter clock RFRUNR register Time base counter Count-down FFFFFH FFFFEH FFFFDH FFFFCH FFFFBH 0 3 2 1 Overflow 0 Measurement counter clock Measurement counter n n+1 n+2 n+3 m-2 m-1 m(0) Undefined Oscillation by reference resistance IRFE, OVTC Interrupt request Figure 17.5.4 Error interrupt due to time base counter overflow Note: When an error interrupt occurs, reset the overflow flag (OVMC or OVTC) by writing "1." The same error interrupt will occur again if the overflow flag is not reset. S1C6F016 Technical Manual (Rev. 1.1) Seiko Epson Corporation 17-7 17 R/F COnVeRTeR 17.6 Continuous Oscillation Function By setting the RFCNT register to "1," the reference oscillation or sensor oscillation can be continued even if the stop condition has been met. This function with RFOUT enabled allows easy measurement of the CR oscillation frequency. 17.7 i/O Memory of R/F Converter Table 17.7.1 shows the I/O addresses and the control bits for the R/F converter. Table 17.7.1 Control bits of R/F converter Address Register name R/W Default Setting/data FF15H D3 D2 D1 D0 0 (*3) RFCKS2 RFCKS1 RFCKS0 R - (*2) R/W 0 R/W 0 R/W 0 7 f3/4 6 f3/2 5 f3 FF60H D3 D2 D1 D0 RFCnT RFOuT eRF1 eRF0 R/W R/W R/W R/W 0 0 0 0 1 1 3 2 Continuous Enable Ch.1 DC Ch.1 AC 0 0 1 0 Normal Disable Ch.0 DC I/O Continuous oscillation enable RFOUT enable R/F conversion selection FF61H D3 D2 D1 D0 OVTC OVMC RFRunR RFRunS R/W R/W R/W R/W 0 0 0 0 1 1 1 1 Overflow error Overflow error Run Run 0 0 0 0 No error No error Stop Stop Time base counter overflow flag Measurement counter overflow flag Reference oscillation Run control/status Sensor oscillation Run control/status FF62H D3 D2 D1 D0 MC3 MC2 MC1 MC0 R/W R/W R/W R/W x x x x 0H-FH FF63H D3 D2 D1 D0 MC7 MC6 MC5 MC4 R/W R/W R/W R/W x x x x 0H-FH FF64H D3 D2 D1 D0 MC11 MC10 MC9 MC8 R/W R/W R/W R/W x x x x FF65H D3 D2 D1 D0 MC15 MC14 MC13 MC12 R/W R/W R/W R/W x x x x 0H-FH FF66H D3 D2 D1 D0 MC19 MC18 MC17 MC16 R/W R/W R/W R/W x x x x 0H-FH FF67H D3 D2 D1 D0 TC3 TC2 TC1 TC0 R/W R/W R/W R/W x x x x 0H-FH FF68H D3 D2 D1 D0 TC7 TC6 TC5 TC4 R/W R/W R/W R/W x x x x FF69H D3 D2 D1 D0 TC11 TC10 TC9 TC8 R/W R/W R/W R/W x x x x 0H-FH FF6AH D3 D2 D1 D0 TC15 TC14 TC13 TC12 R/W R/W R/W R/W x x x x 0H-FH FF6BH D3 D2 D1 D0 TC19 TC18 TC17 TC16 R/W R/W R/W R/W x x x x 0H-FH *1: Initial value at initial reset - 4 PT1 3 f1/4 2 f1/2 Function 1 f1 0 Off Unused R/F converter clock frequency selection (f1 = fOSC1, f3 = fOSC3) Measurement counter MC0-MC3 MC0 = LSB Measurement counter MC4-MC7 Measurement counter MC8-MC11 0H-FH Measurement counter MC12-MC15 Measurement counter MC16-MC19 MC19 = MSB Time base counter TC0-TC3 TC0 = LSB Time base counter TC4-TC7 0H-FH Time base counter TC8-TC11 Time base counter TC12-TC15 *2: Not set in the circuit Time base counter TC16-TC19 TC19 = MSB *3: Constantly "0" when being read 17-8 Seiko Epson Corporation S1C6F016 TECHNICAL MANUAL (Rev. 1.1) 17 R/F COnVeRTeR RFCKS[2:0]: R/F converter clock frequency select register (FF15h*D[2:0]) Selects the R/F converter clock frequency. Table 17.7.2 R/F converter clock frequencies RFCKS[2:0] RFC clock 7 fOSC3 / 4 6 fOSC3 / 2 5 fOSC3 / 1 4 Programmable timer 1 3 fOSC1 / 4 (8 kHz) 2 fOSC1 / 2 (16 kHz) 1 fOSC1 / 1 (32 kHz) 0 Off fOSC1: OSC1 oscillation frequency. ( ) indicates the frequency when fOSC1 = 32 kHz. fOSC3: OSC3 oscillation frequency When programmable timer 1 is selected, the programmable timer 1 underflow signal is divided by 2 before it is used as the R/F converter clock. In this case, the programmable timer must be controlled before operating the R/F converter. Refer to the "Programmable Timer" chapter for controlling the programmable timer. If it is not necessary to run the R/F converter, stop the clock supply by setting this register to "0" to reduce current consumption. At initial reset, this register is set to "0." eRF[1:0]: R/F conversion select register (FF60h*D[1:0]) Selects the channel and sensor type to perform R/F conversion. Table 17.7.3 Selecting channel and sensor type ERF[1:0] Channel and sensor type 3 Ch.1 DC 2 Ch.1 AC 1 Ch.0 DC 0 I/O DC: R/F conversion using a DC bias resistive sensor such as a thermistor AC: R/F conversion using an AC bias resistive sensor such as a humidity sensor The R/F converter channel 0 input/output terminals are shared with the I/O port (P51-P53). By setting this register to other than "0," P53, P52 and P51 are configured as the RFIN0, REF0 and SEN0 terminals, respectively. At initial reset, this register is set to "0." RFOuT: RFOuT enable register (FF60h*D2) Enables RFOUT output from the P50 port. When "1" is written: Enabled (RFOUT) When "0" is written: Disabled (I/O port) Reading: Valid When using the RFOUT output, write "1" to RFOUT to set P50 as the RFOUT output port. At initial reset, this register is set to "0." RFCnT: Continuous oscillation enable register (FF60h*D3) Enables the R/F converter to oscillate continuously. When "1" is written: Continuous oscillation When "0" is written: Normal oscillation Reading: Valid By writing "1" to RFCNT, the reference oscillation or sensor oscillation can be continued even if the stop condition has been met. This function with RFOUT enabled allows easy measurement of the CR oscillation frequency. At initial reset, this register is set to "0." S1C6F016 Technical Manual (Rev. 1.1) Seiko Epson Corporation 17-9 17 R/F COnVeRTeR RFRunS: Sensor oscillation Run control/status (FF61h*D0) Starts R/F conversion for the sensor and indicates the operating (RUN/STOP) status. When "1" is written: When "0" is written: When "1" is read: When "0" is read: R/F conversion starts No operation RUN status STOP status Writing "1" to RFRUNS starts an R/F conversion for the sensor. The register is held at "1" while the R/F conversion is being processed and is set to "0" when the R/F conversion has completed. Writing "0" during an R/F conversion stops the CR oscillation. When the channel 1 sensor type (AC bias and DC bias) is changed by ERF[1:0] during sensor oscillation, RFRUNS is not reset. In this case, reset RFRUNS by writing "0." If RFRUNS and RFRUNR are set to "1" simultaneously, RFRUNR is effective. At initial reset, this register is set to "0." RFRunR: Reference oscillation Run control/status (FF61h*D1) Starts R/F conversion for the reference resistance and indicates the operating (RUN/STOP) status. When "1" is written: When "0" is written: When "1" is read: When "0" is read: R/F conversion starts No operation RUN status STOP status Writing "1" to RFRUNR starts an R/F conversion for the reference resistance. The register is held at "1" while the R/F conversion is being processed and is set to "0" when the R/F conversion has completed. Writing "0" during an R/F conversion stops the CR oscillation. When the channel 1 sensor type (AC bias and DC bias) is changed by ERF[1:0] during reference oscillation, RFRUNR is not reset. In this case, reset RFRUNR by writing "0." RFRUNR is reset when the channel for R/F conversion is changed. If RFRUNS and RFRUNR are set to "1" simultaneously, RFRUNR is effective. At initial reset, this register is set to "0." OVMC: Measurement counter overflow flag (FF61h*D2) Indicates whether the measurement counter has overflown. When "1" is read: When "0" is read: When "1" is written: When "0" is written: Overflow has occurred Overflow has not occurred Flag reset No operation If an overflow occurs while counting the oscillation of the sensor, OVMC is set to "1" and an error interrupt occurs at the same time. This flag is reset by writing "1" or starting R/F conversion. At initial reset, this flag is set to "0." OVTC: Time base counter overflow flag (FF61h*D3) Indicates whether the time base counter has overflown. When "1" is read: Overflow has occurred When "0" is read: Overflow has not occurred When "1" is written: Flag reset When "0" is written: No operation If an overflow occurs while counting the oscillation of the reference resistance, OVTC is set to "1" and an error interrupt occurs at the same time. This flag is reset by writing "1" or starting R/F conversion. At initial reset, this flag is set to "0." 17-10 Seiko Epson Corporation S1C6F016 TECHNICAL MANUAL (Rev. 1.1) 17 R/F COnVeRTeR MC[19:0]: Measurement counter (FF66h-FF62h) The measurement counter counts up according to the CR oscillation clock. It permits writing and reading on a 4-bit basis. The complement of the number of clocks to be counted by the oscillation of the reference resistance must be entered in this counter prior to reference oscillation. When the counter reaches "00000H" due to overflow, the oscillation of the reference resistance stops. When converting a sensor oscillation, "00000H" must be set in this register (it is unnecessary when it is done immediately after a reference oscillation has completed). The sensor oscillation and measurement counter stop when the time base counter overflows. Number of clocks counted by the sensor oscillation can be evaluated from the value indicated by the counter when it stops. Calculate the target value by processing the above counted number according to the program. Measurable range and the overflow of the counter must be taken into account when setting an initial value to be entered prior to R/F conversion. At initial reset, this counter is undefined. TC[19:0]: Time base counter (FF6Bh-FF67h) Writing and reading is possible on a 4-bit basis by the time base counter that is used to adjust the CR oscillation time between the reference resistance and the sensor. The time base counter counts down during oscillation of the reference resistance and counts up to "00000H" during oscillation of the sensor. "00000H" needs to be entered in the counter prior to a reference oscillation in order to adjust the CR oscillating time (number of clocks) of both counts. The counter value after a reference oscillation has completed should be read from this register and save it in the memory. The saved value should be set in this counter before starting a sensor oscillation. At initial reset, this counter is undefined. 17.8 Precautions * When an error interrupt occurs, reset the overflow flag (OVMC or OVTC) by writing "1." The same error interrupt will occur again if the overflow flag is not reset. * When setting the measurement counter or time base counter, always write 5 words of data continuously in order from the lower address (FF62H FF63H FF64H FF65H FF66H, FF67H FF68H FF69H FF6AH FF6BH). Furthermore, an LD instruction should be used for writing data to the measurement counter and a read-modify-write instruction (AND, OR, ADD, SUB, etc.) cannot be used. If data other than low-order 4 bits is written, the counter cannot be set to the desired value. * The R/F converter reference and sensor oscillation frequencies should be determined after an adequate evaluation, since low voltage, 2 V or lower in particular, increases the voltage deviation. Also the voltage deviation depends on the environment including board, resistance, and capacitance (see RFC characteristic curves in the "Electrical Characteristics" chapter). S1C6F016 Technical Manual (Rev. 1.1) Seiko Epson Corporation 17-11 18 SVD (SuPPlY VOlTaGe DeTeCTiOn) CiRCuiT 18 SVD (Supply Voltage Detection) Circuit 18.1 Configuration of SVD Circuit The S1C6F016 has a built-in SVD (supply voltage detection) circuit, so that the software can find when the source voltage lowers. Turning the SVD circuit on/off and the SVD criteria voltage setting can be done with software. Figure 18.1.1 shows the configuration of the SVD circuit. VDD Detection output SVDDT SVDON VSS Criteria voltage setting circuit Data bus SVD circuit SVDS3 | SVDS0 Figure 18.1.1 Configuration of SVD circuit 18.2 SVD Operation The SVD circuit compares the criteria voltage set by software and the supply voltage (VDD terminal-VSS terminal) and sets its results into the SVDDT latch. By reading the data of this SVDDT latch, it can be determined by means of software whether the supply voltage is normal or has dropped. The criteria voltage can be selected from 16 types shown in Table 18.2.1 using the SVDS[3:0] register. Table 18.2.1 Criteria voltage SVDS[3:0] Criteria voltage (V) FH 3.2 EH 3.1 DH 3.0 CH 2.9 BH 2.8 AH 2.7 9H 2.6 8H 2.5 7H 2.4 6H 2.3 5H 2.2 4H 2.1 3H 2.0 2H 1.9 1H 1.8 0H 1.7 When the SVDON register is set to "1," supply voltage detection by the SVD circuit is executed. As soon as the SVDON register is reset to "0," the result is loaded to the SVDDT latch and the SVD circuit goes off. To obtain a stable detection result, the SVD circuit must be on for at least 500 sec. So, to obtain the SVD detection result, follow the programming sequence below. 1. Set SVDON to "1" 2. Maintain for 500 sec minimum 3. Set SVDON to "0" 4. Read SVDDT When the SVD circuit is on, the IC draws a large current, so keep the SVD circuit off unless it is. S1C6F016 Technical Manual (Rev. 1.1) Seiko Epson Corporation 18-1 18 SVD (SuPPlY VOlTaGe DeTeCTiOn) CiRCuiT 18.3 i/O Memory of SVD Circuit Table 18.3.1 shows the I/O addresses and the control bits for the SVD circuit. Table 18.3.1 Control bits of SVD circuit Address Register name R/W Default FF04H D3 D2 D1 D0 SVDS3 SVDS2 SVDS1 SVDS0 R/W R/W R/W R/W FF05H D3 D2 D1 D0 0 (*3) SVDS4 SVDDT SVDOn R - (*2) R/W 0 R 0 R/W 0 *1: Initial value at initial reset 0 0 0 0 Setting/data F E D C 3.2 3.1 3.0 2.9 B A 9 8 2.8 2.7 2.6 2.5 7 6 5 4 2.4 2.3 2.2 2.1 Function 3 2 1 0 2.0 1.9 1.8 1.7 - 1 1 1 Low 1 On *2: Not set in the circuit 0 0 0 Normal 0 Off SVD criteria voltage (V) setting Unused General-purpose register SVD evaluation data SVD circuit On/Off *3: Constantly "0" when being read SVDS[3:0]: VD criteria voltage setting register (FF04h) Criteria voltage for SVD is set as shown in Table 18.2.1. At initial reset, this register is set to "0." SVDOn: SVD circuit On/Off register (FF05h*D0) Turns the SVD circuit on and off. When "1" is written: SVD circuit On When "0" is written: SVD circuit Off Reading: Valid When SVDON is set to "1," a source voltage detection is executed by the SVD circuit. As soon as SVDON is reset to "0," the result is loaded to the SVDDT latch. To obtain a stable detection result, the SVD circuit must be on for at least 500 sec. At initial reset, this register is set to "0." SVDDT: SVD evaluation data (FF05h*D1) This is the result of supply voltage detection. When "1" is read: Supply voltage (VDD-VSS) < Criteria voltage When "0" is read: Supply voltage (VDD-VSS) Criteria voltage Writing: Invalid The result of supply voltage detection at time of SVDON is set to "0" can be read from this latch. At initial reset, SVDDT is set to "0." 18.4 Precautions * To obtain a stable detection result, the SVD circuit must be on for at least 500 sec. So, to obtain the SVD detection result, follow the programming sequence below. 1. Set SVDON to "1" 2. Maintain for 500 sec minimum 3. Set SVDON to "0" 4. Read SVDDT * The SVD circuit should normally be turned off because SVD operation increase current consumption. 18-2 Seiko Epson Corporation S1C6F016 TECHNICAL MANUAL (Rev. 1.1) 19 eleCTRiCal ChaRaCTeRiSTiCS 19 Electrical Characteristics 19.1 absolute Maximum Rating (VSS = 0V) item Power supply voltage LCD power supply voltage Input voltage Output voltage High level output current Symbol VDD VC3 VI VO IOH Low level output current IOL Permissible loss *1 Operating temperature Storage temperature Soldering temperature/time PD Ta Tstg Tsol Condition - - - - 1 pin Total of all pins 1 pin Total of all pins - - - - Rated value -0.3 to +4.0 -0.3 to +6.0 -0.3 to VDD + 0.3 -0.3 to VDD + 0.3 -5 -20 5 20 200 -20 to 70 -65 to 150 260C, 10 seconds (lead section) unit V V V V mA mA mA mA mW C C - *1 In case of plastic package (QFP15-100pin) 19.2 Recommended Operating Conditions (Ta = -20 to 70C) item Power supply voltage Operating frequency Capacitor between CA and CB *1 Capacitor between VSS and VC1 *1 Capacitor between VSS and VC2 *1 Capacitor between VSS and VC3 *1 Capacitor between VSS and VD1 Symbol Condition Normal operation mode VDD Flash programming mode Crystal oscillation fOSC1 Ceramic oscillation fOSC3 CR oscillation (external R) C1 C3 C4 C5 C2 Min. 1.8 2.7 - 30 30 - - - - - Typ. - - 32.768 - - 0.1 0.1 0.1 0.1 0.1 Max. 3.6 3.6 - 4,200 2,200 - - - - - unit V V kHz kHz kHz F F F F F *1 The capacitors are not required when LCD driver is not used. In this case, leave the VC1 to VC3, CA and CB pins open. Flash eePROM programming/erasing Unless otherwise specified: VDD=2.7 to 3.6V (VD1=2.5V), VSS = 0V, Ta=25C Item Programming count Symbol CFEP Condition *1 Min. 1,000 Typ. - Max. - Unit cycle *1 The programming count assumes that "erasing + programming" or "programming only" is one count and the programmed data is guaranteed to be retained for 10 years. S1C6F016 Technical Manual (Rev. 1.1) Seiko Epson Corporation 19-1 19 eleCTRiCal ChaRaCTeRiSTiCS 19.3 DC Characteristics Unless otherwise specified: VDD=1.8 to 3.6V, VSS=0V, Ta=-20 to 70C Item High level input voltage Low level input voltage High level Schmitt input voltage Low level Schmitt input voltage High level output current Low level output current Input leakage current Output leakage current Input pull-down resistance Input pin capacitance Common output current Segment output current (during LCD output) Segment output current (during DC output) Symbol VIH VIL VT+ VTIOH1 IOL1 ILI ILO RIN CIN IOH2 IOL2 IOH3 IOL3 IOH4 IOL4 - - - - VOH1=0.9VDD VOL1=0.1VDD - - - VIN=0V, Ta = 25C VOH2=VC3-0.05V VOL2=VSS+0.05V VOH3=VC3-0.05V VOL3=VSS+0.05V VOH4=0.8VD1 VOL4=0.2VD1 Condition P00-P13 *1 P00-P13 *1 RESET, RFIN1, Pxx *2 RESET, RFIN1, Pxx *2 Pxx, REF1, SEN1, HUD Pxx, REF1, SEN1, HUD RESET, RFIN1, Pxx Pxx, REF1, SEN1, HUD RESET, Pxx RESET, RFIN1, Pxx COM0 to COM7 SEG0 to SEG55 SEG0 to SEG35 Min. 0.8VDD 0 0.5VDD 0.1VDD - 0.5 -1 -1 100 - - 10 - 10 - 330 Typ. - - - - - - - - - - - - - - - - Max. VDD 0.2VDD 0.9VDD 0.5VDD -0.5 - 1 1 500 15 -10 - -10 - -330 - Unit V V V V mA mA A A kW pF A A A A A A *1 When CMOS level is selected as the input interface *2 P00-P13 configured as Schmitt input and other P ports VOUT (V) VDD 0 0 VT+ VT- VDD VIN (V) 19.4 analog Circuit Characteristics and Current Consumption 19.4.1 lCD Driver The typical values in the following LCD driver characteristics varies depending on the panel load (panel size, drive duty, number of display pixels and display contents), so evaluate them by connecting to the actually used LCD panel. lCD drive voltage (VC1 reference) Unless otherwise specified: VDD=1.8 to 3.6V, VSS=0V, Ta=25C, C1-C5=0.1F, When a checker pattern is displayed, No panel load A 1 MW load resistor is connected between VSS and VC1, between VSS and VC2, and between VSS and VC3. Item LCD drive voltage Symbol VC1 Condition VC2 VC3 LC[3:0]=0H LC[3:0]=1H LC[3:0]=2H LC[3:0]=3H LC[3:0]=4H LC[3:0]=5H LC[3:0]=6H LC[3:0]=7H LC[3:0]=8H LC[3:0]=9H LC[3:0]=AH LC[3:0]=BH LC[3:0]=CH LC[3:0]=DH LC[3:0]=EH LC[3:0]=FH 19-2 Seiko Epson Corporation Min. 0.334 x VC3(typ.) 0.653 x VC3(typ.) Typ. x 0.96 Typ. - - 2.75 2.84 2.92 3.00 3.08 3.17 3.25 3.34 3.42 3.50 3.58 3.67 3.75 3.83 3.91 4.00 Max. 0.364 x VC3(typ.) 0.693 x VC3(typ.) Typ. x 1.04 Unit V V V V V V V V V V V V V V V V V V S1C6F016 TECHNICAL MANUAL (Rev. 1.1) 19 eleCTRiCal ChaRaCTeRiSTiCS lCD drive voltage (VC2 reference) Unless otherwise specified: VDD=3.6V, VSS=0V, Ta=25C, C1-C5=0.1F, When a checker pattern is displayed, No panel load A 1 MW load resistor is connected between VSS and VC1, between VSS and VC2, and between VSS and VC3. Item LCD drive voltage Symbol VC1 Condition VC2 VC3 LC[3:0]=0H LC[3:0]=1H LC[3:0]=2H LC[3:0]=3H LC[3:0]=4H LC[3:0]=5H LC[3:0]=6H LC[3:0]=7H LC[3:0]=8H LC[3:0]=9H LC[3:0]=AH LC[3:0]=BH LC[3:0]=CH LC[3:0]=DH LC[3:0]=EH LC[3:0]=FH Min. 0.317 x VC3(typ.) 0.656 x VC3(typ.) Typ. x 0.96 Typ. - - 2.84 2.92 3.01 3.09 3.17 3.26 3.34 3.43 3.51 3.60 3.68 3.77 3.85 3.94 4.02 4.11 Max. 0.357 x VC3(typ.) 0.706 x VC3(typ.) Typ. x 1.04 Unit V V V V V V V V V V V V V V V V V V 19.4.2 SVD Circuit Unless otherwise specified: VDD=1.8 to 3.6V, VSS=0V, Ta=25C Item SVD voltage SVD circuit response time Symbol VSVD Condition Typ. x 1.03 - Typ. 1.7 1.8 1.9 2.0 2.1 2.2 2.3 2.4 2.5 2.6 2.7 2.8 2.9 3.0 3.1 3.2 - 500 Unit V V V V V V V V V V V V V V V V s Min. 1 Typ. - Max. 2,000 Unit kHz DfRFCLK/DIC -40 - 40 % RREF/RSEN CRFC/CSEN 10 100 - - - 2,000 kW pF - - 4.2 MHz SVDS[3:0]=0H SVDS[3:0]=1H SVDS[3:0]=2H SVDS[3:0]=3H SVDS[3:0]=4H SVDS[3:0]=5H SVDS[3:0]=6H SVDS[3:0]=7H SVDS[3:0]=8H SVDS[3:0]=9H SVDS[3:0]=AH SVDS[3:0]=BH SVDS[3:0]=CH SVDS[3:0]=DH SVDS[3:0]=EH SVDS[3:0]=FH Min. Typ. x 0.97 tSVD Max. 19.4.3 R/F Converter Circuit Unless otherwise specified: VDD=1.8 to 3.6V, VSS=0V, Ta=25C Item Reference/sensor oscillation frequencies *1 Reference/sensor oscillation frequency/IC deviation *2 Reference/sensor resistance Reference capacitor and capacitive sensor capacitance *3 Time base counter clock frequency Symbol fRFCLK Condition Ta=-20 to 70C fTCCLK *1 The oscillation frequency/IC deviation characteristic value may increase due to variations in oscillation frequency caused by leakage current if the oscillation frequency is 1 kHz or lower. *2 In these characteristics, unevenness between production lots, and variations in board, resistances and capacitances used in the measurement environment are taken into account (variations in temperature are not included). *3 The CR oscillation can be performed if the resistance or capacitance is out of the range shown in the table (see characteristic curves), note, however, that the oscillation frequency/IC deviation characteristic value may increase due to parasitic elements on the board and those in the IC. S1C6F016 Technical Manual (Rev. 1.1) Seiko Epson Corporation 19-3 19 eleCTRiCal ChaRaCTeRiSTiCS 19.4.4 Current Consumption Unless otherwise specified: VDD=1.8 to 3.6V, VSS=0V, FLCKSx=0x0 (32Hz), Ta=25C, C1-C5=0.1F, No panel load Item Symbol Condition When SLP is executed: OSC1=ON, OSC3=OFF Current consumption in SLEEP ISLP OSC1=32kHz Crystal, OSC3=OFF Current consumption in HALT IHALT1 OSC1=32kHz Crystal, OSC3=4MHz Ceramic IHALT2 OSC1=32kHz Crystal, OSC3=2MHz CR (external R) IHALT3 OSC1=32kHz Crystal, OSC3=500kHz CR (built-in R) IHALT4 OSC1=32kHz Crystal, OSC3=OFF, CPUclk=OSC1 Current consumption IEXE1 during execution OSC1=32kHz Crystal, OSC3=4MHz Ceramic, IEXE2 CPUclk=OSC3 OSC1=32kHz Crystal, OSC3=2MHz CR(external R), IEXE3 CPUclk=OSC3 OSC1=32kHz Crystal, OSC3=500kHz CR(built-in R), IEXE4 CPUclk=OSC3 Current consumption during IEXE1H OSC1=32kHz Crystal, OSC3=OFF, CPUclk=OSC1 VDHLMOD=1 execution in heavy load protection mode LCD circuit current ILCD1 DSPC[1:0]=All on, LC[3:0]=FH, OSC1=32kHz, (VC1 reference) VDD=1.8 to 3.6V, VCREF=0 *1 LCD circuit current in heavy ILCD1H DSPC[1:0]=All on, LC[3:0]=FH, OSC1=32kHz, VDD=1.8 to 3.6V, VCREF=0, VCHLMOD=1 *1 load protection mode (VC1 reference) LCD circuit current ILCD2 DSPC[1:0]=All on, LC[3:0]=FH, OSC1=32kHz, (VC2 reference) VDD=2.8 to 3.6V, VCREF=1 *1 LCD circuit current in heavy ILCD2H DSPC[1:0]=All on, LC[3:0]=FH, OSC1=32kHz, VDD=2.8 to 3.6V, VCREF=1, VCHLMOD=1 *1 load protection mode (VC2 reference) SVD circuit current ISVD VDD=3.6V *2 VDD=3.6V, CREF=CSEN=1000pF, RREF=RSEN=10kW *3 R/F converter circuit current IRFC Min. - - - - - - - Typ. 0.7 2 100 160 50 9 950 Max. 2.5 5 200 300 90 18 1300 Unit A A A A A A A - 600 1100 A - 160 250 A - 16 30 A - 1 3 A - 10 25 A - 0.8 2 A - 15 30 A - - 8 200 15 300 A A *1 This value is added to the current consumption in HALT mode, current consumption during execution, or current consumption during execution in heavy load protection mode when the LCD circuit is active. Current consumption increases according to the display contents and panel load. *2 This value is added to the current consumption during execution or current consumption during execution in heavy load protection mode when the SVD circuit is active. *3 This value is added to the current consumption during execution when the R/F converter circuit is active. 19.5 Oscillation Characteristics The oscillation characteristics change depending on the conditions (components used, board pattern, etc.). Use the following characteristics as reference values. OSC1 crystal oscillation circuit Unless otherwise specified: VDD=1.8 to 3.6V, VSS=0V, Ta=25C, Crystal resonator=C-002RX (R1=30kW Typ., CL=12.5pF), CG1=25pF (external), CD1=Built-in Item Oscillation start time External gate capacitance Built-in drain capacitance Frequency/IC deviation Frequency/voltage deviation Frequency adjustment range Symbol tsta CG1 CD1 Df/DIC Df/DV Df/DCG Condition Including the board capacitance In case of the chip VDD=constant VDD=constant, CG=0 to 25pF Min. - 0 - -10 - 25 Typ. - - 20 - - - Max. 3 25 - 10 1 - Unit s pF pF ppm ppm/V ppm Min. - Typ. - Max. 1 Unit ms OSC3 ceramic oscillation circuit Unless otherwise specified: VDD=1.8 to 3.6V, VSS=0V, Ta=25C, CG3=CD3=30pF Item Oscillation start time Symbol tsta Condition 19-4 Seiko Epson Corporation S1C6F016 TECHNICAL MANUAL (Rev. 1.1) 19 eleCTRiCal ChaRaCTeRiSTiCS OSC3 CR oscillation circuit (external R type) Unless otherwise specified: VDD=1.8 to 3.6V, VSS=0V, Ta=25C Item Oscillation start time Frequency/IC deviation Symbol Condition tsta Df/DIC RCR=constant Min. - -25 Typ. - - Max. 1 25 Unit ms % Min. Typ. x 0.75 - Typ. 500 Max. Typ. x 1.25 20 Unit kHz OSC3 CR oscillation circuit (built-in R type) Unless otherwise specified: VDD=1.8 to 3.6V, VSS=0V, Ta=25C Item Oscillation frequency Symbol fOSC3 Oscillation start time tsta Condition - s 19.6 Serial interface aC Characteristics Master mode Unless otherwise specified: VDD=3.0V, VSS=0V, Ta=-20 to 70C, VIH1=0.8VDD, VIL1=0.2VDD, VOH=0.8VDD, VOL=0.2VDD Item Transmit data output delay time Receive data input set-up time Receive data input hold time Symbol tSMD tSMS tSMH Min. - 400 200 Typ. - - - Max. 200 - - Unit ns ns ns Note that the maximum clock frequency is limited to 1 MHz. Slave mode Unless otherwise specified: VDD=3.0V, VSS=0V, Ta=-20 to 70C, VIH1=0.8VDD, VIL1=0.2VDD, VOH=0.8VDD, VOL=0.2VDD Item Transmit data output delay time Receive data input set-up time Receive data input hold time Symbol tSSD tSSS tSSH Min. - 400 200 Typ. - - - Max. 500 - - Unit ns ns ns Note that the maximum clock frequency is limited to 1 MHz. <Master mode> SCLK OUT VOH VOL tsmd SOUT VOH VOL tsms tsmh VIH1 VIL1 SIN <Slave mode> SCLK IN VIH1 VIL1 tssd SOUT VOH VOL tsss SIN VIH1 VIL1 tssh 19.7 Timing Chart System clock switching timing chart OSCC 10 msec min. CLKCHG S1C6F016 Technical Manual (Rev. 1.1) Seiko Epson Corporation 1 instruction execution time or longer 19-5 19 eleCTRiCal ChaRaCTeRiSTiCS 19.8 Characteristics Curves (reference value) high level output current-voltage characteristic Ta = 70C, Max. value VDD-VOH [V] 0.0 0 0.2 0.4 0.6 0.8 1.0 -3 IOH [mA] VDD = 1.8 V -6 VDD = 2.4 V -9 -12 VDD = 3.6 V -15 low level output current-voltage characteristic Ta = 70C, Min. value 15 12 IOL [mA] VDD = 3.6 V 9 VDD = 2.4 V 6 VDD = 1.8 V 3 0 0.0 0.1 0.2 0.3 VOL [V] 19-6 Seiko Epson Corporation 0.4 0.5 0.6 S1C6F016 TECHNICAL MANUAL (Rev. 1.1) 19 eleCTRiCal ChaRaCTeRiSTiCS lCD drive voltage - supply voltage characteristic (1/3 bias, VC2 reference) Ta = 25C, Typ. value 5.0 LCx = FH VC3 [V] 4.0 LCx = 8H 3.0 2.0 1.5 LCx = 0H 2.0 2.5 3.0 3.5 4.0 VDD [V] lCD drive voltage - supply voltage characteristic (1/3 bias, VC1 reference) Ta = 25C, Typ. value 5.0 4.0 VC3 [V] LCx = FH LCx = 8H 3.0 LCx = 0H 2.0 1.5 2.0 2.5 3.0 3.5 4.0 VDD [V] lCD drive voltage - ambient temperature characteristic (1/3 bias, VC2/VC1 reference) VDD = 3.0 V, Typ. value 1.05VC3 1.04VC3 1.03VC3 1.02VC3 VC3 [V] 1.01VC3 1.00VC3 0.99VC3 0.98VC3 0.97VC3 0.96VC3 0.95VC3 0.94VC3 -50 S1C6F016 Technical Manual (Rev. 1.1) -25 0 25 Ta [C] Seiko Epson Corporation 50 75 100 19-7 19 eleCTRiCal ChaRaCTeRiSTiCS lCD drive voltage - load characteristic (1/3 bias) When a load is connected to VC3 terminal only LCx = FH, Ta = 25C, Typ. value 4.40 VC3 [V] 4.20 4.00 VC2 reference 3.80 VC1 reference 3.60 3.40 0 4 8 12 16 20 -IVC3 [A] SVD voltage - ambient temperature characteristic SVDSx = FH, Typ. value 1.05VSVD 1.04VSVD 1.03VSVD VSVD [V] 1.02VSVD 1.01VSVD 1.00VSVD 0.99VSVD 0.98VSVD 0.97VSVD 0.96VSVD 0.95VSVD -50 -25 0 25 Ta [C] 50 75 100 halT state current consumption - temperature characteristic (during operation with OSC1) <Crystal oscillation, fOSC1 = 32.768 khz> VDD = 3.6 V, OSC3 = OFF, Clock manager = OFF, Typ. value 8 IHALT1 [A] 6 4 2 0 -50 -25 0 25 Ta [C] 19-8 Seiko Epson Corporation 50 75 100 S1C6F016 TECHNICAL MANUAL (Rev. 1.1) 19 eleCTRiCal ChaRaCTeRiSTiCS Run state current consumption - temperature characteristic (during operation with OSC1) <Crystal oscillation, fOSC1 = 32.768 khz> VDD = 3.6 V, OSC3 = OFF, Clock manager = OFF, Typ. value 20 IEXE1 [A] 15 10 5 0 -50 -25 0 25 Ta [C] 50 75 100 Run state current consumption - frequency characteristic (during operation with OSC3) <Ceramic oscillation> VDD = 3.6 V, Ta = 25C, Typ. value 1200 1000 IEXE2 [A] 800 600 400 200 0 0 0.5 1.0 1.5 2.0 2.5 3.0 OSC3 frequency [MHz] 3.5 4.0 4.5 Run state current consumption - resistor characteristic (during operation with OSC3) <CR oscillation (external R)> VDD = 3.6 V, Ta = 25C, Typ. value 1000 IEXE3 [A] 800 600 400 200 0 10 S1C6F016 Technical Manual (Rev. 1.1) 100 RCR3 [k] Seiko Epson Corporation 1000 19-9 19 eleCTRiCal ChaRaCTeRiSTiCS Oscillation frequency - resistor characteristic (OSC3) <CR oscillation (external R)> VDD = 3.6 V, Ta = 25C, Typ. value 10000 fOSC3 [kHz] 1000 100 10 10 100 RCR3 [k] 1000 Oscillation frequency - temperature characteristic (OSC3) <CR oscillation (external R)> RCR3 = 30 kW, Typ. value fOSC3 [kHz] 10000 1000 100 -50 -25 0 25 Ta [C] 50 75 100 Run state current consumption - temperature characteristic (during operation with OSC3) <CR oscillation (built-in R)> VDD = 3.6 V, Typ. value 250 IEXE4 [A] 200 150 100 0 -50 -25 0 25 Ta [C] 19-10 Seiko Epson Corporation 50 75 100 S1C6F016 TECHNICAL MANUAL (Rev. 1.1) 19 eleCTRiCal ChaRaCTeRiSTiCS Oscillation frequency - temperature characteristic (OSC3) <CR oscillation (built-in R)> VDD = 3.6 V, Typ. value 650 600 fOSC3 [kHz] 550 500 450 400 350 -50 -25 0 25 Ta [C] 50 75 100 RFC reference/sensor oscillation frequency - resistance characteristic (DC oscillation mode) CSEN = 1000 pF, Ta = 25C, Typ. value 10,000 fRFCLK [kHz] 1,000 IC deviation 100 10 VDD = 1.8 V 1 0 VDD = 3.6 V 0 1 10 100 RREF/RSEN [k] 1,000 10,000 RFC reference/sensor oscillation frequency - resistance characteristic (aC oscillation mode) CSEN = 1000 pF, Ta = 25C, Typ. value 10,000 fRFCLK [kHz] 1,000 IC deviation 100 10 VDD = 1.8 V 1 0 VDD = 3.6 V 0 S1C6F016 Technical Manual (Rev. 1.1) 1 10 100 RREF/RSEN [k] Seiko Epson Corporation 1,000 10,000 19-11 19 eleCTRiCal ChaRaCTeRiSTiCS RFC reference/sensor oscillation frequency - capacitance characteristic (DC/aC oscillation mode) RSEN = 100 kW, Ta = 25C, Typ. value 1,000 fRFCLK [kHz] 100 IC deviation VDD = 1.8 V 10 VDD = 3.6 V 1 0 10 100 1,000 10,000 CRFC [pF] RFC reference/sensor oscillation frequency - current consumption characteristic (DC/aC oscillation mode) CRFC = 1000 pF, Ta = 25C, Typ. value 10,000 VDD = 3.6 V 1,000 IRFC [A] VDD = 1.8 V 100 10 1 0 1 10 100 1,000 10,000 fRFC [kHz] 19-12 Seiko Epson Corporation S1C6F016 TECHNICAL MANUAL (Rev. 1.1) 20 BaSiC eXTeRnal WiRinG DiaGRaM 20 Basic External Wiring Diagram Standard mask option Type B RREF1 HUD SEN1 REF1 RFIN1 RHUD RREF2 I/O CA CB C1 VDD RESET RFOUT/P50 SEN0/P51 REF0/P52 RFIN0/P53 RTMP Flash EEPROM programmer P00-P03 P10-P13 P20-P23 P30-P33 P40-P43 COM0 | COM7 I/O SEG0 | SEG35 LCD panel 36 x 8/7/6/5/4/3 Cres CP S1C6F016 TYPE-B [The potential of the substrate (back of the chip) is VSS.] DMOD DCLK DRXD DTXD C2 VD1 VC1 VC2 VC3 TEST VSS 3.6 V | 1.8 V C3 C4 C5 CG1 OSC1 OSC2 + X'tal CG3 OSC3 Ceramic TEST1 TEST2 TEST3 OSC4 CD3 Recommended values for external parts Symbol X'tal CG1 Ceramic CG3 CD3 C1 C2 C3 C4 C5 CP Cres Name Crystal resonator Trimmer capacitor Ceramic resonator Gate capacitor Drain capacitor Booster capacitor Capacitor between VSS and VD1 Capacitor between VSS and VC1 Capacitor between VSS and VC2 Capacitor between VSS and VC3 Capacitor for power supply Capacitor for RESET terminal Recommended value 32.768 kHz 0 pF to 25 pF 4 MHz 30 pF (Ceramic oscillation) 30 pF (Ceramic oscillation) 0.1 F 0.1 F 0.1 F 0.1 F 0.1 F 3.3 F 0.47 F Note: The values in the above table are shown only for reference and not guaranteed. S1C6F016 Technical Manual (Rev. 1.1) Seiko Epson Corporation 20-1 20 BaSiC eXTeRnal WiRinG DiaGRaM Standard mask option Type e COM0 | COM7 SEG0 | SEG55 LCD panel 56 x 8/7/6/5/4/3 CA CB C1 VDD I/O P00-P03 P10-P13 RESET Cres CP S1C6F016 TYPE-E [The potential of the substrate (back of the chip) is VSS.] I/O DMOD DCLK DRXD DTXD C2 VD1 VC1 VC2 VC3 TEST VSS 1.8 V C3 C4 C5 CG1 OSC1 OSC2 3.6 V | X'tal OSC3 TEST1 TEST2 TEST3 OSC4 RCR Flash EEPROM programmer + Recommended values for external parts Symbol X'tal CG1 RCR C1 C2 C3 C4 C5 CP Cres Name Crystal resonator Trimmer capacitor Resistor for CR oscillation Booster capacitor Capacitor between VSS and VD1 Capacitor between VSS and VC1 Capacitor between VSS and VC2 Capacitor between VSS and VC3 Capacitor for power supply Capacitor for RESET terminal Recommended value 32.768 kHz 0 pF to 25 pF 22 k to 400 k 0.1 F 0.1 F 0.1 F 0.1 F 0.1 F 3.3 F 0.47 F Note: The values in the above table are shown only for reference and not guaranteed. 20-2 Seiko Epson Corporation S1C6F016 TECHNICAL MANUAL (Rev. 1.1) 20 BaSiC eXTeRnal WiRinG DiaGRaM I/O O CA CB VDD RESET RFOUT/P50 SEN0/P51 REF0/P52 RFIN0/P53 RTMP RREF1 HUD SEN1 REF1 RFIN1 RHUD RREF2 Flash EEPROM programmer P00-P03 P10-P13 P20-P23 P30-P33 P40-P43 SEG0-SEG35 COM0 | COM7 Standard mask option Type G I/O Cres CP S1C6F016 TYPE-G [The potential of the substrate (back of the chip) is VSS. DMOD DCLK DRXD DTXD C2 VD1 VC1 VC2 VC3 TEST VSS 3.6 V | 1.8 V CG1 OSC1 OSC2 + X'tal OSC4 RCR OSC3 TEST1 TEST2 TEST3 Recommended values for external parts Symbol X'tal CG1 RCR C2 CP Cres Name Crystal resonator Trimmer capacitor Resistor for CR oscillation Capacitor between VSS and VD1 Capacitor for power supply Capacitor for RESET terminal Recommended value 32.768 kHz 0 pF to 25 pF 22 k to 400 k 0.1 F 3.3 F 0.47 F Note: The values in the above table are shown only for reference and not guaranteed. S1C6F016 Technical Manual (Rev. 1.1) Seiko Epson Corporation 20-3 aPPenDiX a liST OF i/O ReGiSTeRS Appendix A List of I/O Registers *1: Initial value at initial reset *2: Not set in the circuit *3: Constantly "0" when being read FF00H Address FF00H D3 D2 D1 D0 Oscillation Circuit Register name R/W Default ClKChG OSCC 0 (*3) 0 (*3) R/W 0 R/W 0 R - (*2) R - (*2) Setting/data 1 OSC3 1 On Function 0 OSC1 0 Off CPU clock switch OSC3 oscillation On/Off Unused Unused - - FF01H Address FF01H D3 D2 D1 D0 Watchdog Timer Register name R/W Default 0 (*3) 0 (*3) WDen WDRST (*3) Setting/data R - (*2) R - (*2) R/W 1 1 Enable W (Reset) 1 Reset Function - - Unused Unused Watchdog timer enable Watchdog timer reset (writing) 0 Disable 0 Invalid FF02H-FF03H Address Power Supply Circuit Register name R/W Default Setting/data Function FF02H D3 D2 D1 D0 VDSel VCSel hlOn DBOn R/W R/W R/W R/W 0 0 0 0 1 1 1 1 1 1 1 1 0 0 0 0 0 0 0 0 General-purpose register General-purpose register General-purpose register General-purpose register FF03H D3 D2 D1 D0 VChlMOD VDhlMOD VCReF lPWR R/W R/W R/W R/W 0 0 0 0 1 1 1 1 On On VC2 On 0 0 0 0 Off Off VC1 Off VC regulator heavy load protection mode On/Off VD regulator heavy load protection mode On/Off VC regulator reference voltage selection VC regulator On/Off FF04H-FF05H Address SVD Circuit Register name R/W Default FF04H D3 D2 D1 D0 SVDS3 SVDS2 SVDS1 SVDS0 R/W R/W R/W R/W FF05H D3 D2 D1 D0 0 (*3) SVDS4 SVDDT SVDOn R - (*2) R/W 0 R 0 R/W 0 0 0 0 0 Setting/data F E D C 3.2 3.1 3.0 2.9 B A 9 8 2.8 2.7 2.6 2.5 7 6 5 4 Function 2.4 2.3 2.2 2.1 3 2 1 0 2.0 1.9 1.8 1.7 - 1 1 1 Low 1 On Unused General-purpose register SVD evaluation data SVD circuit On/Off 0 0 0 Normal 0 Off FF10H-FF1BH Address SVD criteria voltage (V) setting Clock Manager Register name R/W Default Setting/data FF10H D3 D2 D1 D0 FOuT3 FOuT2 FOuT1 FOuT0 R/W R/W R/W R/W 0 0 0 0 F E D C f3 f3/2 f3/4 f3/8 FF11H D3 D2 D1 D0 nRSP11 nRSP10 nRSP01 nRSP00 R/W R/W R/W R/W 0 0 0 0 3 2 3 2 FF12H D3 D2 D1 D0 FlCKS1 FlCKS0 VCCKS1 VCCKS0 R/W R/W R/W R/W 0 0 0 0 3 2 3 2 FF14H D3 D2 D1 D0 0 (*3) SiFCKS2 SiFCKS1 SiFCKS0 R - (*2) R/W 0 R/W 0 R/W 0 S1C6F016 Technical Manual (Rev. 1.1) f3/16 f3/32 f3/64 f3/256 Function 7 6 5 4 f1 f1/2 f1/4 f1/16 f1/256 f1/64 f1/256 f1/64 1 0 1 0 f1/16 Off f1/16 Off P1 key input interrupt noise reject frequency selection (f1 = fOSC1, f3 = fOSC3) P0 key input interrupt noise reject frequency selection (f1 = fOSC1, f3 = fOSC3) - 16.0 - - 1 0 1 0 21.3 32.0 2048 Off Frame frequency (Hz) selection 7 f3/4 6 f3/2 5 f3 B A 9 8 - 4 PT1 3 f1/4 2 f1/2 3 2 1 0 f1/32 FOUT frequency selection f1/64 (f1 = fOSC1, f3 = fOSC3) f1/256 Off 1 f1 0 Off/ External Seiko Epson Corporation VC boost frequency (Hz) selection Unused Serial I/F clock frequency selection (f1 = fOSC1, f3 = fOSC3) AP-A-1 aPPenDiX a liST OF i/O ReGiSTeRS Address Register name R/W Default Setting/data FF15H D3 D2 D1 D0 0 (*3) RFCKS2 RFCKS1 RFCKS0 R - (*2) R/W 0 R/W 0 R/W 0 - 4 PT1 3 f1/4 2 f1/2 7 f3/4 6 f3/2 5 f3 FF16H D3 D2 D1 D0 MDCKe SGCKe SWCKe RTCKe R/W R/W R/W R/W 0 0 0 0 1 1 1 1 Enable Enable Enable Enable FF18H D3 D2 D1 D0 PTPS03 PTPS02 PTPS01 PTPS00 R/W R/W R/W R/W 0 0 0 0 F E D C f3 f3/2 f3/4 f3/8 B A 9 8 FF19H D3 D2 D1 D0 PTPS13 PTPS12 PTPS11 PTPS10 R/W R/W R/W R/W 0 0 0 0 F E D C f3 f3/2 f3/4 f3/8 FF1AH D3 D2 D1 D0 PTPS23 PTPS22 PTPS21 PTPS20 R/W R/W R/W R/W 0 0 0 0 F E D C FF1BH D3 D2 D1 D0 PTPS33 PTPS32 PTPS31 PTPS30 R/W R/W R/W R/W 0 0 0 0 F E D C Function Unused R/F converter clock frequency selection (f1 = fOSC1, f3 = fOSC3) 1 f1 0 Off 0 0 0 0 Disable Disable Disable Disable Integer multiplier clock enable Sound generator clock enable Stopwatch timer clock enable Clock timer clock enable f3/16 f3/32 f3/64 f3/256 7 6 5 4 f1 f1/2 f1/4 f1/16 3 2 1 0 f1/32 Programmable timer 0 count clock frequency f1/64 selection (f1 = fOSC1, f3 = fOSC3) f1/256 Off B A 9 8 f3/16 f3/32 f3/64 f3/256 7 6 5 4 f1 f1/2 f1/4 f1/16 3 2 1 0 f1/32 Programmable timer 1 count clock frequency f1/64 selection (f1 = fOSC1, f3 = fOSC3) f1/256 Off f3 f3/2 f3/4 f3/8 B A 9 8 f3/16 f3/32 f3/64 f3/256 7 6 5 4 f1 f1/2 f1/4 f1/16 3 2 1 0 f1/32 Programmable timer 2 count clock frequency f1/64 selection (f1 = fOSC1, f3 = fOSC3) f1/256 Off f3 f3/2 f3/4 f3/8 B A 9 8 f3/16 f3/32 f3/64 f3/256 7 6 5 4 f1 f1/2 f1/4 f1/16 3 2 1 0 f1/32 Programmable timer 3 count clock frequency f1/64 selection (f1 = fOSC1, f3 = fOSC3) f1/256 Off FF20H-FF3FH Address I/O Ports Register name R/W Default Setting/data Function FF20H D3 D2 D1 D0 P03 P02 P01 P00 R/W R/W R/W R/W 1 1 1 1 1 1 1 1 High High High High 0 0 0 0 Low Low Low Low P03 I/O port data P02 I/O port data P01 I/O port data P00 I/O port data FF21H D3 D2 D1 D0 iOC03 iOC02 iOC01 iOC00 R/W R/W R/W R/W 0 0 0 0 1 1 1 1 Output Output Output Output 0 0 0 0 Input Input Input Input P03 I/O control register P02 I/O control register P01 I/O control register P00 I/O control register FF22H D3 D2 D1 D0 Pul03 Pul02 Pul01 Pul00 R/W R/W R/W R/W 1 1 1 1 1 1 1 1 Enable Enable Enable Enable 0 0 0 0 Disable Disable Disable Disable P03 pull-down control register P02 pull-down control register P01 pull-down control register P00 pull-down control register FF23H D3 D2 D1 D0 SMT03 SMT02 SMT01 SMT00 R/W R/W R/W R/W 1 1 1 1 1 1 1 1 Schmitt Schmitt Schmitt Schmitt 0 0 0 0 CMOS CMOS CMOS CMOS P03 input I/F level select register P02 input I/F level select register P01 input I/F level select register P00 input I/F level select register FF24H D3 D2 D1 D0 P13 P12 P11 P10 R/W R/W R/W R/W 1 1 1 1 1 1 1 1 High High High High 0 0 0 0 Low Low Low Low P13 I/O port data P12 I/O port data P11 I/O port data P10 I/O port data FF25H D3 D2 D1 D0 iOC13 iOC12 iOC11 iOC10 R/W R/W R/W R/W 0 0 0 0 1 1 1 1 Output Output Output Output 0 0 0 0 Input Input Input Input P13 I/O control register P12 I/O control register P11 I/O control register P10 I/O control register FF26H D3 D2 D1 D0 Pul13 Pul12 Pul11 Pul10 R/W R/W R/W R/W 1 1 1 1 1 1 1 1 Enable Enable Enable Enable 0 0 0 0 Disable Disable Disable Disable P13 pull-down control register P12 pull-down control register P11 pull-down control register P10 pull-down control register FF27H D3 D2 D1 D0 SMT13 SMT12 SMT11 SMT10 R/W R/W R/W R/W 1 1 1 1 1 1 1 1 Schmitt Schmitt Schmitt Schmitt 0 0 0 0 CMOS CMOS CMOS CMOS P13 input I/F level select register P12 input I/F level select register P11 input I/F level select register P10 input I/F level select register FF28H D3 D2 D1 D0 P23 P22 P21 P20 R/W R/W R/W R/W 1 1 1 1 1 1 1 1 High High High High 0 0 0 0 Low Low Low Low P23 I/O port data P22 I/O port data P21 I/O port data P20 I/O port data AP-A-2 Seiko Epson Corporation S1C6F016 TECHNICAL MANUAL (Rev. 1.1) aPPenDiX a liST OF i/O ReGiSTeRS Address Register name R/W Default Setting/data Function FF29H D3 D2 D1 D0 iOC23 iOC22 iOC21 iOC20 R/W R/W R/W R/W 0 0 0 0 1 1 1 1 Output Output Output Output 0 0 0 0 Input Input Input Input P23 I/O control register P22 I/O control register P21 I/O control register P20 I/O control register FF2AH D3 D2 D1 D0 Pul23 Pul22 Pul21 Pul20 R/W R/W R/W R/W 1 1 1 1 1 1 1 1 Enable Enable Enable Enable 0 0 0 0 Disable Disable Disable Disable P23 pull-down control register P22 pull-down control register P21 pull-down control register P20 pull-down control register FF2CH D3 D2 D1 D0 P33 P32 P31 P30 R/W R/W R/W R/W 1 1 1 1 1 1 1 1 High High High High 0 0 0 0 Low Low Low Low P33 I/O port data P32 I/O port data P31 I/O port data P30 I/O port data FF2DH D3 D2 D1 D0 iOC33 iOC32 iOC31 iOC30 R/W R/W R/W R/W 0 0 0 0 1 1 1 1 Output Output Output Output 0 0 0 0 Input Input Input Input P33 I/O control register P32 I/O control register P31 I/O control register P30 I/O control register FF2EH D3 D2 D1 D0 Pul33 Pul32 Pul31 Pul30 R/W R/W R/W R/W 1 1 1 1 1 1 1 1 Enable Enable Enable Enable 0 0 0 0 Disable Disable Disable Disable P33 pull-down control register P32 pull-down control register P31 pull-down control register P30 pull-down control register FF30H D3 D2 D1 D0 P43 P42 P41 P40 R/W R/W R/W R/W 1 1 1 1 1 1 1 1 High High High High 0 0 0 0 Low Low Low Low P43 I/O port data P42 I/O port data P41 I/O port data P40 I/O port data FF31H D3 D2 D1 D0 iOC43 iOC42 iOC41 iOC40 R/W R/W R/W R/W 0 0 0 0 1 1 1 1 Output Output Output Output 0 0 0 0 Input Input Input Input P43 I/O control register P42 I/O control register P41 I/O control register P40 I/O control register FF32H D3 D2 D1 D0 Pul43 Pul42 Pul41 Pul40 R/W R/W R/W R/W 1 1 1 1 1 1 1 1 Enable Enable Enable Enable 0 0 0 0 Disable Disable Disable Disable P43 pull-down control register P42 pull-down control register P41 pull-down control register P40 pull-down control register FF34H D3 D2 D1 D0 P53 P52 P51 P50 R/W R/W R/W R/W 1 1 1 1 1 1 1 1 High High High High 0 0 0 0 Low Low Low Low P53 I/O port data P52 I/O port data P51 I/O port data P50 I/O port data FF35H D3 D2 D1 D0 iOC53 iOC52 iOC51 iOC50 R/W R/W R/W R/W 0 0 0 0 1 1 1 1 Output Output Output Output 0 0 0 0 Input Input Input Input P53 I/O control register P52 I/O control register P51 I/O control register P50 I/O control register FF36H D3 D2 D1 D0 Pul53 Pul52 Pul51 Pul50 R/W R/W R/W R/W 1 1 1 1 1 1 1 1 Enable Enable Enable Enable 0 0 0 0 Disable Disable Disable Disable P53 pull-down control register P52 pull-down control register P51 pull-down control register P50 pull-down control register FF3CH D3 D2 D1 D0 SiP03 SiP02 SiP01 SiP00 R/W R/W R/W R/W 0 0 0 0 1 1 1 1 Enable Enable Enable Enable 0 0 0 0 Disable Disable Disable Disable P03 (KEY03) interrupt select register P02 (KEY02) interrupt select register P01 (KEY01) interrupt select register P00 (KEY00) interrupt select register FF3DH D3 D2 D1 D0 PCP03 PCP02 PCP01 PCP00 R/W R/W R/W R/W 1 1 1 1 1 1 1 1 (falling edge) (falling edge) (falling edge) (falling edge) 0 0 0 0 (rising edge) (rising edge) (rising edge) (rising edge) P03 (KEY03) interrupt polarity select register P02 (KEY02) interrupt polarity select register P01 (KEY01) interrupt polarity select register P00 (KEY00) interrupt polarity select register FF3EH D3 D2 D1 D0 SiP13 SiP12 SiP11 SiP10 R/W R/W R/W R/W 0 0 0 0 1 1 1 1 Enable Enable Enable Enable 0 0 0 0 Disable Disable Disable Disable P13(KEY13) interrupt select register P12(KEY12) interrupt select register P11(KEY11) interrupt select register P10(KEY10) interrupt select register FF3FH D3 D2 D1 D0 PCP13 PCP12 PCP11 PCP10 R/W R/W R/W R/W 1 1 1 1 1 1 1 1 (falling edge) (falling edge) (falling edge) (falling edge) 0 0 0 0 (rising edge) (rising edge) (rising edge) (rising edge) P13(KEY13) interrupt polarity select register P12(KEY12) interrupt polarity select register P11(KEY11) interrupt polarity select register P10(KEY10) interrupt polarity select register S1C6F016 Technical Manual (Rev. 1.1) Seiko Epson Corporation AP-A-3 aPPenDiX a liST OF i/O ReGiSTeRS FF40H-FF42H Address Clock Timer Register name R/W Default FF40H D3 D2 D1 D0 0 (*3) 0 (*3) TMRST (*3) TMRun FF41H D3 D2 D1 D0 TM3 TM2 TM1 TM0 R R R R 0 0 0 0 FF42H D3 D2 D1 D0 TM7 TM6 TM5 TM4 R R R R 0 0 0 0 Setting/data R - (*2) R - (*2) W (Reset) 1 Reset R/W 0 1 Run Function - - 0 Invalid 0 Stop Unused Unused Clock timer reset (writing) Clock timer Run/Stop 0H-FH Clock timer data (16 Hz) Clock timer data (32 Hz) Clock timer data (64 Hz) Clock timer data (128 Hz) 0H-FH Clock timer data (1 Hz) Clock timer data (2 Hz) Clock timer data (4 Hz) Clock timer data (8 Hz) FF44H-FF47H Address FF44H D3 D2 D1 D0 Sound Generator Register name R/W Default enRTM enRST (*3) enOn BZe FF45H D3 0 (*3) D2 BZSTP (*3) D1 BZShT D0 ShTPW Setting/data R/W 0 1 1 sec W (Reset) 1 Reset R/W 0 1 On R/W 0 1 Enable R - (*2) W 0 R/W 0 R/W 0 0 0 0 0 Function 0.5 sec Invalid Off Disable - 1 Stop 1 Trigger (W) Busy (R) 1 125 msec 0 Invalid 0 Invalid (W) Ready (R) 0 31.25 msec FF46H D3 D2 D1 D0 0 (*3) BZFQ2 BZFQ1 BZFQ0 R - (*2) R/W 0 R/W 0 R/W 0 7 1170.3 6 1365.3 5 1638.4 - 4 2048.0 3 2340.6 2 2730.7 FF47H D3 D2 D1 D0 0 (*3) BDTY2 BDTY1 BDTY0 R - (*2) R/W 0 R/W 0 R/W 0 7 Level 8 6 Level 7 5 Level 6 - 4 Level 5 3 Level 4 2 Level 3 1 3276.8 0 4096.0 1 Level 2 0 Level 1 (max.) Envelope releasing time selection Envelope reset (writing) Envelope On/Off Buzzer output enable Unused 1-shot buzzer stop (writing) 1-shot buzzer trigger (writing) 1-shot buzzer status (reading) 1-shot buzzer pulse width setting Unused Buzzer frequency (Hz) selection Unused Buzzer signal duty ratio selection FF48H-FF4DH Address Stopwatch Timer Register name R/W Default FF48H D3 0 (*3) D2 0 (*3) D1 SWDiR D0 eDiR R - (*2) R - (*2) R/W 0 R/W 0 Setting/data - - 1 P00 = Lap P01 = Run/Stop 1 Enable 0 P00 = Run/Stop P01 = Lap 0 Disable FF49H D3 D2 D1 D0 0 (*3) DKM2 DKM1 DKM0 R - (*2) R/W 0 R/W 0 R/W 0 7 P10-13 6 P10-12 5 P10-11 FF4AH D3 D2 D1 D0 lCuRF CRnWF SWRun SWRST (*3) R 0 R 0 R/W 0 W (Reset) 1 1 1 1 FF4BH D3 D2 D1 D0 SWD3 SWD2 SWD1 SWD0 R R R R 0 0 0 0 FF4CH D3 D2 D1 D0 SWD7 SWD6 SWD5 SWD4 R R R R 0 0 0 0 0-9 FF4DH D3 D2 D1 D0 SWD11 SWD10 SWD9 SWD8 R R R R 0 0 0 0 0-9 Request Renewal Run Reset - 4 P10 1 P02 3 P02-03,10 0 No mask 2 P02-03 0 0 0 0 No No Stop Invalid 0-9 AP-A-4 Seiko Epson Corporation Function Unused Unused Stopwatch direct input switch Direct input enable Unused Key mask selection Lap data carry-up request flag Capture renewal flag Stopwatch timer Run/Stop Stopwatch timer reset (writing) Stopwatch timer data BCD (1/1000 sec) Stopwatch timer data BCD (1/100 sec) Stopwatch timer data BCD (1/10 sec) S1C6F016 TECHNICAL MANUAL (Rev. 1.1) aPPenDiX a liST OF i/O ReGiSTeRS FF50H-FF52H Address LCD Driver Register name R/W Default Setting/data FF50H D3 D2 D1 D0 0 (*3) 0 (*3) DSPC1 DSPC0 R - (*2) R - (*2) R/W 1 R/W 0 - - 3 All on 2 All off FF51H D3 D2 D1 D0 STCD lDuTY2 lDuTY1 lDuTY0 R/W R/W R/W R/W 0 0 0 0 1 7 6 5 FF52H D3 D2 D1 D0 lC3 lC2 lC1 lC0 R/W R/W R/W R/W 0 0 0 0 1 All on 0 Normal Static 1/8 1/7 1/8 0 Dynamic 1 1/4 0 1/3 4 1/7 3 1/6 2 1/5 Address 0H(light)-FH(dark) Serial Interface Register name R/W Default D0 eSiF R - (*2) R/W 0 R/W 0 Setting/data - R/W 0 1 Enable 1 Trigger (W) Run (R) 1 SIF 0 0 0 0 3 2 1 1 0 Disable 0 Invalid (W) Stop (R) 0 I/O Negative, Negative, MSB first Master Positive, Positive, LSB first Slave FF59H D3 D2 D1 D0 SCPS1 SCPS0 SDP SMOD R/W R/W R/W R/W FF5AH D3 D2 D1 D0 0 (*3) 0 (*3) eSReaDY enCS R - (*2) R - (*2) R/W 0 R/W 0 FF5BH D3 D2 D1 D0 SD3 SD2 SD1 SD0 R/W R/W R/W R/W x x x x 0H-FH FF5CH D3 D2 D1 D0 SD7 SD6 SD5 SD4 R/W R/W R/W R/W x x x x 0H-FH 1 0 0 0 - - 1 SRDY 1 SRDY_SS 0 SS 0 P33 FF60H-FF6BH Address LCD drive mode switch LCD drive duty selection LCD contrast adjustment FF58H-FF5CH FF58H D3 0 (*3) D2 eSOuT D1 SCTRG Function Unused Unused LCD display mode selection Function Unused SOUT enable Serial I/F clock trigger (writing) Serial I/F clock status (reading) Serial I/F enable (P3 port function selection) Serial I/F clock format selection (polarity, phase) Serial I/F data input/output permutation Serial I/F mode selection Unused Unused SRDY_SS function selection (ENCS = "1") SRDY_SS enable (P33 port function selection) Serial I/F transmit/receive data (low-order 4 bits) SD0 = LSB Serial I/F transmit/receive data (high-order 4 bits) SD7 = MSB R/F Converter Register name R/W Default Setting/data Function FF60H D3 D2 D1 D0 RFCnT RFOuT eRF1 eRF0 R/W R/W R/W R/W 0 0 0 0 1 1 3 2 Continuous Enable Ch.1 DC Ch.1 AC 0 0 1 0 Normal Disable Ch.0 DC I/O Continuous oscillation enable RFOUT enable R/F conversion selection FF61H D3 D2 D1 D0 OVTC OVMC RFRunR RFRunS R/W R/W R/W R/W 0 0 0 0 1 1 1 1 Overflow error Overflow error Run Run 0 0 0 0 No error No error Stop Stop Time base counter overflow flag Measurement counter overflow flag Reference oscillation Run control/status Sensor oscillation Run control/status FF62H D3 D2 D1 D0 MC3 MC2 MC1 MC0 R/W R/W R/W R/W x x x x FF63H D3 D2 D1 D0 MC7 MC6 MC5 MC4 R/W R/W R/W R/W x x x x FF64H D3 D2 D1 D0 MC11 MC10 MC9 MC8 R/W R/W R/W R/W x x x x S1C6F016 Technical Manual (Rev. 1.1) 0H-FH Measurement counter MC0-MC3 MC0 = LSB Measurement counter MC4-MC7 0H-FH Measurement counter MC8-MC11 0H-FH Seiko Epson Corporation AP-A-5 aPPenDiX a liST OF i/O ReGiSTeRS Address Register name R/W Default Setting/data FF65H D3 D2 D1 D0 MC15 MC14 MC13 MC12 R/W R/W R/W R/W x x x x FF66H D3 D2 D1 D0 MC19 MC18 MC17 MC16 R/W R/W R/W R/W x x x x 0H-FH FF67H D3 D2 D1 D0 TC3 TC2 TC1 TC0 R/W R/W R/W R/W x x x x 0H-FH FF68H D3 D2 D1 D0 TC7 TC6 TC5 TC4 R/W R/W R/W R/W x x x x 0H-FH FF69H D3 D2 D1 D0 TC11 TC10 TC9 TC8 R/W R/W R/W R/W x x x x FF6AH D3 D2 D1 D0 TC15 TC14 TC13 TC12 R/W R/W R/W R/W x x x x 0H-FH FF6BH D3 D2 D1 D0 TC19 TC18 TC17 TC16 R/W R/W R/W R/W x x x x 0H-FH 0H-FH Measurement counter MC16-MC19 MC19 = MSB Time base counter TC0-TC3 TC0 = LSB Time base counter TC4-TC7 Time base counter TC8-TC11 0H-FH Time base counter TC12-TC15 FF70H-FF76H Address Function Measurement counter MC12-MC15 Time base counter TC16-TC19 TC19 = MSB Integer Multiplier Register name R/W Default Setting/data FF70H D3 D2 D1 D0 SR3 SR2 SR1 SR0 R/W R/W R/W R/W x x x x 0H-FH FF71H D3 D2 D1 D0 SR7 SR6 SR5 SR4 R/W R/W R/W R/W x x x x 0H-FH FF72H D3 D2 D1 D0 DRl3 DRl2 DRl1 DRl0 R/W R/W R/W R/W x x x x 0H-FH FF73H D3 D2 D1 D0 DRl7 DRl6 DRl5 DRl4 R/W R/W R/W R/W x x x x FF74H D3 D2 D1 D0 DRh3 DRh2 DRh1 DRh0 R/W R/W R/W R/W x x x x 0H-FH FF75H D3 D2 D1 D0 DRh7 DRh6 DRh5 DRh4 R/W R/W R/W R/W x x x x 0H-FH FF76H D3 D2 D1 D0 nF VF ZF CalMD R R R R/W 0 0 0 0 0H-FH 1 1 1 1 Negative Overflow Zero Division (W) Run (R) 0 0 0 0 Positive No No Multiplication (W) Stop (R) AP-A-6 Seiko Epson Corporation Function Source register (low-order 4 bits) SR0 = LSB Source register (high-order 4 bits) SR7 = MSB Low-order 8-bit destination register (low-order 4 bits) DRL0 = LSB Low-order 8-bit destination register (high-order 4 bits) DRL7 = MSB High-order 8-bit destination register (low-order 4 bits) DRH0 = LSB High-order 8-bit destination register (high-order 4 bits) DRH7 = MSB Negative flag Overflow flag Zero flag Calculation mode selection (writing) Operation status (reading) S1C6F016 TECHNICAL MANUAL (Rev. 1.1) aPPenDiX a liST OF i/O ReGiSTeRS FF80H-FF9FH Address Programmable Timer Register name R/W Default Setting/data Function FF80H D3 D2 D1 D0 MOD16_a eVCnT_a FCSel_a PlPul_a R/W R/W R/W R/W 0 0 0 0 1 1 1 1 16 bits Event counter With noise reject (positive) 0 0 0 0 8 bits Timer No noise reject (negative) PTM0-1 16-bit mode selection PTM0 counter mode selection PTM0 function selection (for event counter mode) PTM0 pulse polarity selection (event counter mode) FF81H D3 D2 D1 D0 PTSel1 PTSel0 ChSel_a PTOuT_a R/W R/W R/W R/W 0 0 0 0 1 1 1 1 PWM PWM Timer 1 On 0 0 0 0 Normal Normal Timer 0 Off Programmable timer 1 PWM output selection Programmable timer 0 PWM output selection PTM0-1 TOUT_A output selection PTM0-1 TOUT_A output control FF82H D3 D2 D1 D0 PTRST1 (*3) PTRun1 PTRST0 (*3) PTRun0 W - (*2) R/W 0 W - (*2) R/W 0 1 1 1 1 Reset Run Reset Run 0 0 0 0 Invalid Stop Invalid Stop Programmable timer 1 reset (reload) Programmable timer 1 Run/Stop Programmable timer 0 reset (reload) Programmable timer 0 Run/Stop FF84H D3 D2 D1 D0 RlD03 RlD02 RlD01 RlD00 R/W R/W R/W R/W 0 0 0 0 0H-FH FF85H D3 D2 D1 D0 RlD07 RlD06 RlD05 RlD04 R/W R/W R/W R/W 0 0 0 0 0H-FH FF86H D3 D2 D1 D0 RlD13 RlD12 RlD11 RlD10 R/W R/W R/W R/W 0 0 0 0 FF87H D3 D2 D1 D0 RlD17 RlD16 RlD15 RlD14 R/W R/W R/W R/W 0 0 0 0 0H-FH FF88H D3 D2 D1 D0 PTD03 PTD02 PTD01 PTD00 R R R R 0 0 0 0 0H-FH FF89H D3 D2 D1 D0 PTD07 PTD06 PTD05 PTD04 R R R R 0 0 0 0 0H-FH FF8AH D3 D2 D1 D0 PTD13 PTD12 PTD11 PTD10 R R R R 0 0 0 0 0H-FH FF8BH D3 D2 D1 D0 PTD17 PTD16 PTD15 PTD14 R R R R 0 0 0 0 0H-FH FF8CH D3 D2 D1 D0 CD03 CD02 CD01 CD00 R/W R/W R/W R/W 0 0 0 0 0H-FH FF8DH D3 D2 D1 D0 CD07 CD06 CD05 CD04 R/W R/W R/W R/W 0 0 0 0 0H-FH FF8EH D3 D2 D1 D0 CD13 CD12 CD11 CD10 R/W R/W R/W R/W 0 0 0 0 0H-FH FF8FH D3 D2 D1 D0 CD17 CD16 CD15 CD14 R/W R/W R/W R/W 0 0 0 0 S1C6F016 Technical Manual (Rev. 1.1) 0H-FH 0H-FH Seiko Epson Corporation Programmable timer 0 reload data (low-order 4 bits) RLD00 = LSB Programmable timer 0 reload data (high-order 4 bits) RLD07 = MSB Programmable timer 1 reload data (low-order 4 bits) RLD10 = LSB Programmable timer 1 reload data (high-order 4 bits) RLD17 = MSB Programmable timer 0 data (low-order 4 bits) PTD00 = LSB Programmable timer 0 data (high-order 4 bits) PTD07 = MSB Programmable timer 1 data (low-order 4 bits) PTD10 = LSB Programmable timer 1 data (high-order 4 bits) PTD17 = MSB Programmable timer 0 compare data (high-order 4 bits) CD00 = LSB Programmable timer 0 compare data (high-order 4 bits) CD07 = MSB Programmable timer 1 compare data (low-order 4 bits) CD10 = LSB Programmable timer 1 compare data (high-order 4 bits) CD17 = MSB AP-A-7 aPPenDiX a liST OF i/O ReGiSTeRS Address Register name R/W Default Setting/data Function FF90H D3 D2 D1 D0 MOD16_B eVCnT_B FCSel_B PlPul_B R/W R/W R/W R/W 0 0 0 0 1 1 1 1 16 bits Event counter With noise reject (positive) 0 0 0 0 8 bits Timer No noise reject (negative) PTM2-3 16-bit mode selection PTM2 counter mode selection PTM2 function selection (for event counter mode) PTM2 pulse polarity selection (event counter mode) FF91H D3 D2 D1 D0 PTSel3 PTSel2 ChSel_B PTOuT_B R/W R/W R/W R/W 0 0 0 0 1 1 1 1 PWM PWM Timer 3 On 0 0 0 0 Normal Normal Timer 2 Off Programmable timer 3 PWM output selection Programmable timer 2 PWM output selection PTM2-3 TOUT_B output selection PTM2-3 TOUT_B output control FF92H D3 D2 D1 D0 PTRST3 (*3) PTRun3 PTRST2 (*3) PTRun2 W - (*2) R/W 0 W - (*2) R/W 0 1 1 1 1 Reset Run Reset Run 0 0 0 0 Invalid Stop Invalid Stop Programmable timer 3 reset (reload) Programmable timer 3 Run/Stop Programmable timer 2 reset (reload) Programmable timer 2 Run/Stop FF94H D3 D2 D1 D0 RlD23 RlD22 RlD21 RlD20 R/W R/W R/W R/W 0 0 0 0 FF95H D3 D2 D1 D0 RlD27 RlD26 RlD25 RlD24 R/W R/W R/W R/W 0 0 0 0 FF96H D3 D2 D1 D0 RlD33 RlD32 RlD31 RlD30 R/W R/W R/W R/W 0 0 0 0 0H-FH FF97H D3 D2 D1 D0 RlD37 RlD36 RlD35 RlD34 R/W R/W R/W R/W 0 0 0 0 0H-FH FF98H D3 D2 D1 D0 PTD23 PTD22 PTD21 PTD20 R R R R 0 0 0 0 0H-FH FF99H D3 D2 D1 D0 PTD27 PTD26 PTD25 PTD24 R R R R 0 0 0 0 0H-FH FF9AH D3 D2 D1 D0 PTD33 PTD32 PTD31 PTD30 R R R R 0 0 0 0 0H-FH FF9BH D3 D2 D1 D0 PTD37 PTD36 PTD35 PTD34 R R R R 0 0 0 0 0H-FH FF9CH D3 D2 D1 D0 CD23 CD22 CD21 CD20 R/W R/W R/W R/W 0 0 0 0 0H-FH FF9DH D3 D2 D1 D0 CD27 CD26 CD25 CD24 R/W R/W R/W R/W 0 0 0 0 0H-FH FF9EH D3 D2 D1 D0 CD33 CD32 CD31 CD30 R/W R/W R/W R/W 0 0 0 0 0H-FH FF9FH D3 D2 D1 D0 CD37 CD36 CD35 CD34 R/W R/W R/W R/W 0 0 0 0 0H-FH 0H-FH 0H-FH AP-A-8 Seiko Epson Corporation Programmable timer 2 reload data (low-order 4 bits) RLD20 = LSB Programmable timer 2 reload data (high-order 4 bits) RLD27 = MSB Programmable timer 3 reload data (low-order 4 bits) RLD30 = LSB Programmable timer 3 reload data (high-order 4 bits) RLD37 = MSB Programmable timer 2 data (low-order 4 bits) PTD20 = LSB Programmable timer 2 data (high-order 4 bits) PTD27 = MSB Programmable timer 3 data (low-order 4 bits) PTD30 = LSB Programmable timer 3 data (high-order 4 bits) PTD37 = MSB Programmable timer 2 compare data (low-order 4 bits) CD20 = LSB Programmable timer 2 compare data (high-order 4 bits) CD27 = MSB Programmable timer 3 compare data (low-order 4 bits) CD30 = LSB Programmable timer 3 compare data (high-order 4 bits) CD37 = MSB S1C6F016 TECHNICAL MANUAL (Rev. 1.1) aPPenDiX a liST OF i/O ReGiSTeRS FFE1H-FFFFH Address Interrupt Controller Register name R/W Default Setting/data Function - 0 Mask 0 Mask 0 Mask Unused Interrupt mask register (RFC error) Interrupt mask register (RFC REF completion) Interrupt mask register (RFC SEN completion) 0 Mask 0 Mask Unused Unused Interrupt mask register (PT0 underflow) Interrupt mask register (PT0 compare match) 0 Mask 0 Mask Unused Unused Interrupt mask register (PT1 underflow) Interrupt mask register (PT1 compare match) 0 Mask 0 Mask Unused Unused Interrupt mask register (PT2 underflow) Interrupt mask register (PT2 compare match) 0 Mask 0 Mask Unused Unused Interrupt mask register (PT3 underflow) Interrupt mask register (PT3 compare match) 1 Enable 0 Mask Unused Unused Unused Interrupt mask register (Serial I/F) 1 1 1 1 Enable Enable Enable Enable 0 0 0 0 Mask Mask Mask Mask Interrupt mask register (KEY03<P03>) Interrupt mask register (KEY02<P02>) Interrupt mask register (KEY01<P01>) Interrupt mask register (KEY00<P00>) 0 0 0 0 1 1 1 1 Enable Enable Enable Enable 0 0 0 0 Mask Mask Mask Mask Interrupt mask register (KEY13<P13>) Interrupt mask register (KEY12<P12>) Interrupt mask register (KEY11<P11>) Interrupt mask register (KEY10<P10>) R/W R/W R/W R/W 0 0 0 0 1 1 1 1 Enable Enable Enable Enable 0 0 0 0 Mask Mask Mask Mask Interrupt mask register (SW direct RUN) Interrupt mask register (SW direct LAP) Interrupt mask register (Stopwatch 1 Hz) Interrupt mask register (Stopwatch 10 Hz) eiT3 eiT2 eiT1 eiT0 R/W R/W R/W R/W 0 0 0 0 1 1 1 1 Enable Enable Enable Enable 0 0 0 0 Mask Mask Mask Mask Interrupt mask register (Clock timer 16 Hz) Interrupt mask register (Clock timer 32 Hz) Interrupt mask register (Clock timer 64 Hz) Interrupt mask register (Clock timer 128 Hz) FFEFH D3 D2 D1 D0 eiT7 eiT6 eiT5 eiT4 R/W R/W R/W R/W 0 0 0 0 1 1 1 1 Enable Enable Enable Enable 0 0 0 0 Mask Mask Mask Mask Interrupt mask register (Clock timer 1 Hz) Interrupt mask register (Clock timer 2 Hz) Interrupt mask register (Clock timer 4 Hz) Interrupt mask register (Clock timer 8 Hz) FFF1H D3 D2 D1 D0 0 (*3) iRFe iRFR iRFS R - (*2) R/W 0 R/W 0 R/W 0 FFF2H D3 D2 D1 D0 0 (*3) 0 (*3) iPT0 iCTC0 R - (*2) R - (*2) R/W 0 R/W 0 FFF3H D3 D2 D1 D0 0 (*3) 0 (*3) iPT1 iCTC1 R - (*2) R - (*2) R/W 0 R/W 0 FFF4H D3 D2 D1 D0 0 (*3) 0 (*3) iPT2 iCTC2 R - (*2) R - (*2) R/W 0 R/W 0 FFE1H D3 D2 D1 D0 0 (*3) eiRFe eiRFR eiRFS R - (*2) R/W 0 R/W 0 R/W 0 FFE2H D3 D2 D1 D0 0 (*3) 0 (*3) eiPT0 eiCTC0 R - (*2) R - (*2) R/W 0 R/W 0 FFE3H D3 D2 D1 D0 0 (*3) 0 (*3) eiPT1 eiCTC1 R - (*2) R - (*2) R/W 0 R/W 0 FFE4H D3 D2 D1 D0 0 (*3) 0 (*3) eiPT2 eiCTC2 R - (*2) R - (*2) R/W 0 R/W 0 FFE5H D3 D2 D1 D0 0 (*3) 0 (*3) eiPT3 eiCTC3 R - (*2) R - (*2) R/W 0 R/W 0 FFEAH D3 D2 D1 D0 0 (*3) 0 (*3) 0 (*3) eiSiF R - (*2) R - (*2) R - (*2) R/W 0 FFEBH D3 D2 D1 D0 eiK03 eiK02 eiK01 eiK00 R/W R/W R/W R/W 0 0 0 0 FFECH D3 D2 D1 D0 eiK13 eiK12 eiK11 eiK10 R/W R/W R/W R/W FFEDH D3 D2 D1 D0 eiRun eilaP eiSW1 eiSW10 FFEEH D3 D2 D1 D0 S1C6F016 Technical Manual (Rev. 1.1) 1 Enable 1 Enable 1 Enable - - 1 Enable 1 Enable - - 1 Enable 1 Enable - - 1 Enable 1 Enable - - 1 Enable 1 Enable - - - - Unused 0 Not occurred (R) Interrupt factor flag (RFC error) Interrupt factor flag (RFC REF completion) Invalid (W) Interrupt factor flag (RFC SEN completion) - - Unused Unused 0 Not occurred (R) Interrupt factor flag (PT0 underflow) Interrupt factor flag (PT0 compare match) Invalid (W) - - Unused Unused 0 Not occurred (R) Interrupt factor flag (PT1 underflow) Interrupt factor flag (PT1 compare match) Invalid (W) - - Unused Unused 0 Not occurred (R) Interrupt factor flag (PT2 underflow) Interrupt factor flag (PT2 compare match) Invalid (W) 1 Occurred (R) Reset (W) 1 Occurred (R) Reset (W) 1 Occurred (R) Reset (W) 1 Occurred (R) Reset (W) Seiko Epson Corporation AP-A-9 aPPenDiX a liST OF i/O ReGiSTeRS Address Register name R/W Default Setting/data Function FFF5H D3 D2 D1 D0 0 (*3) 0 (*3) iPT3 iCTC3 R - (*2) R - (*2) R/W 0 R/W 0 - - Unused Unused 0 Not occurred (R) Interrupt factor flag (PT3 underflow) Interrupt factor flag (PT3 compare match) Invalid (W) FFFAH D3 D2 D1 D0 0 (*3) 0 (*3) 0 (*3) iSiF R - (*2) R - (*2) R - (*2) R/W 0 - - - Unused Unused Unused 0 Not occurred (R) Interrupt factor flag (Serial I/F) Invalid (W) FFFBH D3 D2 D1 D0 iK03 iK02 iK01 iK00 R/W R/W R/W R/W 0 0 0 0 1 Occurred (R) Reset (W) 0 Not occurred (R) Interrupt factor flag (KEY03<P03>) Interrupt factor flag (KEY02<P02>) Invalid (W) Interrupt factor flag (KEY01<P01>) Interrupt factor flag (KEY00<P00>) FFFCH D3 D2 D1 D0 iK13 iK12 iK11 iK10 R/W R/W R/W R/W 0 0 0 0 1 Occurred (R) Reset (W) 0 Not occurred (R) Interrupt factor flag (KEY13<P13>) Interrupt factor flag (KEY12<P12>) Invalid (W) Interrupt factor flag (KEY11<P11>) Interrupt factor flag (KEY10<P10>) FFFDH D3 D2 D1 D0 iRun ilaP iSW1 iSW10 R/W R/W R/W R/W 0 0 0 0 1 Occurred (R) Reset (W) 0 Not occurred (R) Interrupt factor flag (SW direct RUN) Interrupt factor flag (SW direct LAP) Invalid (W) Interrupt factor flag (Stopwatch 1 Hz) Interrupt factor flag (Stopwatch 10 Hz) FFFEH D3 D2 D1 D0 iT3 iT2 iT1 iT0 R/W R/W R/W R/W 0 0 0 0 1 Occurred (R) Reset (W) 0 Not occurred (R) Interrupt factor flag (Clock timer 16 Hz) Interrupt factor flag (Clock timer 32 Hz) Invalid (W) Interrupt factor flag (Clock timer 64 Hz) Interrupt factor flag (Clock timer 128 Hz) FFFFH D3 D2 D1 D0 iT7 iT6 iT5 iT4 R/W R/W R/W R/W 0 0 0 0 1 Occurred (R) Reset (W) 0 Not occurred (R) Interrupt factor flag (Clock timer 1 Hz) Interrupt factor flag (Clock timer 2 Hz) Invalid (W) Interrupt factor flag (Clock timer 4 Hz) Interrupt factor flag (Clock timer 8 Hz) 1 Occurred (R) Reset (W) 1 Occurred (R) Reset (W) AP-A-10 Seiko Epson Corporation S1C6F016 TECHNICAL MANUAL (Rev. 1.1) aPPenDiX B PeRiPheRal CiRCuiT BOaRDS FOR S1C6F016 Appendix B Peripheral Circuit Boards for S1C6F016 This section describes how to use the Peripheral Circuit Boards for the S1C6F016 (S5U1C63000P6 and S5U1C6F016P2), which provide emulation functions when mounted on the debugging tool for the S1C63 Family of 4-bit single-chip microcomputers, the ICE (S5U1C63000H2/S5U1C63000H6). This description of the S1C63 Family Peripheral Circuit Board (S5U1C63000P6) provided in this document assumes that circuit data for the S1C6F016 has already been downloaded to the board. For information on downloading various circuit data, please see Section B.3. Please refer to the S5U1C63000H manual for detailed information on the ICE functions and method of use. Note: The S5U1C63000P1 cannot be used for developing the S1C6F016 applications. B.1 names and Functions of each Part B.1.1 S5u1C63000P6 The S5U1C63000P6 board provides peripheral circuit functions of S1C63 Family microcomputers other than the core CPU. The following explains the names and functions of each part of the S5U1C63000P6 board. (7) (8) (9) (10) (1) (2) CLK (6) VLCD(V2V/V3V) VSVD VC5 CN0 GND 32K LCLK D IOSEL2 E SN0 ST1 ST0 VC5 1 S5U1C63000P6 2 ADOSCA fCera 4 FOSC3(CR) Xtal CPA1 GND FOSC1(CR) OSC1 (CR) Adj (5) Ceramic OSC3 (CR) Adj 8 10 12 14 16 RESET 6 (4) Norm PRG Prog (8) CN3 (not used) CN2 LED1 LED3 LED5 LED7 LED9 LED11 LED13 LED15 LED16 (3) CN1 Figure B.1.1.1 S5U1C63000P6 (1) VlCD This control is used to adjust the LCD drive voltage when an external power supply is selected by mask option for the LCD drive power supply. (2) VSVD Unused The switches on the S5U1C6F016P2 board are used to verify the operation of the supply voltage detection function (SVD). S1C6F016 Technical Manual (Rev. 1.1) Seiko Epson Corporation AP-B-1 aPPenDiX B PeRiPheRal CiRCuiT BOaRDS FOR S1C6F016 (3) Register monitor leDs/pins These LEDs and pins correspond one-to-one to the registers listed below. The LED lights when the register is set to "1" and goes out when the register is set to "0." The monitor pins output a high level when the register is "1" and a low level when the register is "0." Table B.1.1.1 Register monitor LEDs/pins 1 pin Name DONE 2 3 4 OSCC CLKCHG VCSEL - 5 DBON No. 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 1 2 4 6 8 10 12 14 3 5 7 LED Name - 9 6 VCHLMOD 11 7 VDHLMOD 13 8 9 10 11 12 13 14 15 15 16 LED Monitor pins 16 - VCREF LPWR SVDON SVDS0 SVDS1 SVDS2 SVDS3 SVDS4 - - - Register = "1" Initialization of this board has completed normally. OSC3 oscillation: On CPU clock: OSC3 FF02H*D2 = "1" (general-purpose register) FF02H*D0 = "1" (general-purpose register) VC regulator heavy load protection mode: On VD regulator heavy load protection mode: On VC regulator reference voltage: VC2 VC regulator: On SVD circuit: On SVD criteria voltage level FF05H*D2 = "1" (general-purpose register) - Register = "0" During initialization OSC3 oscillation: Off CPU clock: OSC1 FF02H*D2 = "0" (general-purpose register) FF02H*D0 = "0" (general-purpose register) VC regulator heavy load protection mode: Off VD regulator heavy load protection mode: Off VC regulator reference voltage: VC1 VC regulator: Off SVD circuit: Off FF05H*D2 = "0" (general-purpose register) - (4) CR oscillation frequency adjusting control This control is used to adjust the OSC3 oscillation frequency. This function is effective only when CR oscillation is selected for the OSC3 oscillation circuit by mask option. The oscillation frequency can be adjusted in the range of about 100 kHz to 8 MHz. Note that the actual IC may not operate throughout this frequency range. Refer to "Electrical Characteristics" to select the appropriate operating frequency. Not used Not used OSC3 rough adjustment OSC3 fine adjustment Figure B.1.1.2 CR oscillation frequency adjusting control When ceramic oscillation is selected for the OSC3 oscillation circuit by mask option, the OSC3 frequency is fixed at 4.1943 MHz in this board . (5) CR oscillation frequency monitor pins These pins are used to monitor the clock waveform from the CR oscillation circuit with an oscilloscope. Note that the monitor pin always outputs a clock regardless of whether the oscillation is enabled via software or not. RESET OSC3 monitor pin (red) Not used GND pin (black) Figure B.1.1.3 CR oscillation frequency monitor pins (6) ReSeT switch This switch initializes the internal circuits of this board and feeds a reset signal to the ICE. (7) external part connecting socket Unused AP-B-2 Seiko Epson Corporation S1C6F016 TECHNICAL MANUAL (Rev. 1.1) aPPenDiX B PeRiPheRal CiRCuiT BOaRDS FOR S1C6F016 (8) ClK and PRG switches If power to the ICE is shut down before downloading circuit data is completed, the circuit configuration in this board will remain incomplete and the debugger may not be able to start after the ICE is turned on again. In this case, temporarily turn the ICE off and set the CLK switch to the 32K position and the PRG switch to the Prog position, then turn the ICE on again. This should allow the debugger to start up, allowing you to download circuit data. After the circuit data has downloaded, temporarily turn the ICE off and reset the CLK and PRG switch to the LCLK and the Norm position, respectively. Then turn the ICE on again. (9) iOSel2 When downloading circuit data, set IOSEL2 to the "E" position. Otherwise, set to the "D" position. (10) VC5 This control allows fine adjustment of the LCD drive voltage when an internal power supply is selected by mask option. Note, however, that the LCD drive voltage of the actual IC must be controlled using the LCD contrast adjustment register. B.1.2 S5u1C6F016P2 The S5U1C6F016P2 board provides the R/F converter function that supports resistive sensors such as a thermistor and resistive humidity sensors, the SVD function, and the P50-P53 port inputs/outputs. The following explains the names and functions of each part of the S5U1C6F016P2 board. (5) HUD REF1 RFIN0 RFIN1 GND GND SW1 LED1 7 8 9A F0 12 REF0 CH 1 6 SEN1 BCD E CH 0 SEN0 3 4 5 RFOUT SW2 (4) (1) (2) (3) CN1 Figure B.1.2.1 S5U1C6F016P2 (1) R/F converter monitor pins and external part connecting socket (Channel 0) These monitor pins are used to check the operation of R/F converter channel 0. The socket is used to connect external resistors and a capacitor for R/F conversion. Mount resistors and a capacitor on the platform attached with the S5U1C6F016P2 and then connect it to the onboard socket. RFOUT SEN0 REF0 RFIN0 GND CH 0 1 2 3 4 5 6 7 8 16 15 14 13 12 11 10 9 Sensor (resistor) Reference resistor Capacitor Connecting a DC-bias resistive sensor (e.g. thermistor) Figure B.1.2.2 R/F converter monitor pins and external part connecting socket (Channel 0) Seiko Epson Corporation S1C6F016 Technical Manual (Rev. 1.1) AP-B-3 aPPenDiX B PeRiPheRal CiRCuiT BOaRDS FOR S1C6F016 (2) R/F converter monitor pins and external part connecting socket (Channel 1) These monitor pins are used to check the operation of R/F converter channel 1. The socket is used to connect external resistors and a capacitor for R/F conversion. Mount resistors and a capacitor on the platform attached with the S5U1C6F016P2 and then connect it to the onboard socket. HUD CH 1 SEN1 REF1 RFIN1 GND 1 2 3 4 5 6 7 8 16 15 14 13 12 11 10 9 Sensor (resistor) Reference resistor Capacitor 1 2 3 4 5 6 7 8 16 15 14 13 12 11 10 9 Sensor (resistor) Reference resistor Capacitor Connecting a DC-bias Connecting an AC-bias resistive sensor (e.g. thermistor) resistive humidity sensor The sensor connect position changes according to the sensor type to be used. Do not mount an AC bias sensor and a DC bias sensor at the same time as it causes a malfunction. Figure B.1.2.3 R/F converter monitor pins and external part connecting socket (Channel 1) (3) Cn1 (P5 i/O connector) This is a user connector to input/output the P50 to P53 port signals. The P50 to P53 terminals of the actual IC are shared with the terminals for R/F converter channel 0. The S5U1C6F016P2 board provides this connector separated with the R/F converter socket and monitor pins shown in (1) above. Therefore, be sure to leave this connector open when R/F converter channel 0 is used. Furthermore, do not use this connector when the P50 to P53 ports are switched to SEG outputs by mask option. (4) Supply voltage level setting switches for SVD (SW1, SW2) These switches are used to set a supply voltage level for verifying the SVD operation. Table B.1.2.1 shows the relationship between the switch settings and the SVD control register. Note that these switches do not change the actual power supply voltage. These switches are intended to be used only for changing the detection results to debug whether the SVD routine works normally or not. Table B.1.2.1 Relationship between SW1/SW2 settings and SVDS register Switch settings Supply voltage emulation level SW1 SW2 0 DETECTION Voltage level < (SVDS[3:0] = 0) 1 DETECTION (SVDS[3:0] = 0) Voltage level < (SVDS[3:0] = 1) 2 DETECTION (SVDS[3:0] = 1) Voltage level < (SVDS[3:0] = 2) 3 DETECTION (SVDS[3:0] = 2) Voltage level < (SVDS[3:0] = 3) 4 DETECTION (SVDS[3:0] = 3) Voltage level < (SVDS[3:0] = 4) 5 DETECTION (SVDS[3:0] = 4) Voltage level < (SVDS[3:0] = 5) 6 DETECTION (SVDS[3:0] = 5) Voltage level < (SVDS[3:0] = 6) 7 DETECTION (SVDS[3:0] = 6) Voltage level < (SVDS[3:0] = 7) 8 DETECTION (SVDS[3:0] = 7) Voltage level < (SVDS[3:0] = 8) 9 DETECTION (SVDS[3:0] = 8) Voltage level < (SVDS[3:0] = 9) A DETECTION (SVDS[3:0] = 9) Voltage level < (SVDS[3:0] = 0AH) B DETECTION (SVDS[3:0] = 0AH) Voltage level < (SVDS[3:0] = 0BH) C DETECTION (SVDS[3:0] = 0BH) Voltage level < (SVDS[3:0] = 0CH) D DETECTION (SVDS[3:0] = 0CH) Voltage level < (SVDS[3:0] = 0DH) E DETECTION (SVDS[3:0] = 0DH) Voltage level < (SVDS[3:0] = 0EH) F DETECTION (SVDS[3:0] = 0EH) Voltage level < (SVDS[3:0] = 0FH) - MAX (SVDS[3:0] = 0FH) < Voltage level (5) SVD result leD (leD1) This LED indicates the SVD results according to the SW1 and SW2 settings. The LED lights when the voltage level set using the switches is lower than the level set using the SVDS register (SVDDT = "1"). AP-B-4 Seiko Epson Corporation S1C6F016 TECHNICAL MANUAL (Rev. 1.1) aPPenDiX B PeRiPheRal CiRCuiT BOaRDS FOR S1C6F016 B.2 Connecting to the Target System This section explains how to connect the target system. First insert the S5U1C63000P6 board into the second upper slot of the ICE and the S5U1C6F016P2 board into the top slot. Download the circuit data to the S5U1C63000P6 board before installing the S5U1C6F016P2 board if the S5U1C63000P6 board does not include the correct circuit data. See Section B.3 for downloading circuit data. LC1 LC2 6 63000h S5u1C DIAG OFF S5U1C6F016P2 ON S5U1C63000P6 Figure B.2.1 Installing the peripheral circuit boards to the ICE installing the S5u1C63000P6/6F016P2 board Set the jig included with the ICE into position as shown in Figure B.2.2. Using this jig as a lever, push it toward the inside of the board evenly on the left and right sides. After confirming that the board has been firmly fitted into the internal slot of the ICE, remove the jig. Board Figure B.2.2 Installing the board Dismounting the S5u1C63000P6/6F016P2 board Set the jig included with the ICE into position as shown in Figure B.2.3. Using this jig as a lever, push it toward the outside of the board evenly on the left and right sides. After confirming that the board has been dismounted from the backboard connector, pull the board out of the ICE. Board Figure B.2.3 Dismounting the board To connect the S5U1C63000P6 and S5U1C6F016P2 to the target system, use the I/O connecting cables supplied with these boards. Take care when handling the connectors, since they conduct electrical power (VDD = +3.3 V). S1C6F016 Technical Manual (Rev. 1.1) Seiko Epson Corporation AP-B-5 OFF ON DIAG LC2 TR G ST OU OP T O TR UT C BR IN K IN G N D PO W ER SL EM P/H U LT aPPenDiX B PeRiPheRal CiRCuiT BOaRDS FOR S1C6F016 S5U1C6F016P2 CN1 (10 pins) LC1 S5U1C63000H6 ePSOn S5U1C63000P6 CN2 S5U1C63000H6 LC1 S5U1C63000P6 CN1 (80 pins) (100 pins) (100 pins) CN1 (10 pins) CN2-1 (50 pins) LC1-2 (50 pins) LC1-1 (50 pins) CN1-1 (40 pins) CN1-2 (40 pins) CN1 CN2-1 (When SEG DC output is used) LC1-2 LC1-1 CN1-1 CN1-2 Target board Figure B.2.4 Connecting the S5U1C63000P6 and S5U1C6F016P2 to the target system No. 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 Table B.2.1 S5U1C63000P6 CN1 connector pin assignment 40-pin CN1-1 connector 40-pin CN1-2 connector Pin name No. Pin name No. Pin name No. Pin name VDD (= 3.3 V) 21 VDD (= 3.3 V) 1 VDD (= 3.3 V) 21 VDD (= 3.3 V) VDD (= 3.3 V) 22 VDD (= 3.3 V) 2 VDD (= 3.3 V) 22 VDD (= 3.3 V) Cannot be connected 23 P20 3 Cannot be connected 23 Cannot be connected Cannot be connected 24 P21 4 Cannot be connected 24 Cannot be connected Cannot be connected 25 P22 5 Cannot be connected 25 Cannot be connected Cannot be connected 26 P23 6 Cannot be connected 26 Cannot be connected Cannot be connected 27 P30 7 Cannot be connected 27 Cannot be connected Cannot be connected 28 P31 8 Cannot be connected 28 Cannot be connected Cannot be connected 29 P32 9 Cannot be connected 29 Cannot be connected Cannot be connected 30 P33 10 Cannot be connected 30 Cannot be connected VSS 31 VSS 11 VSS 31 VSS VSS 32 VSS 12 VSS 32 VSS P00 33 P40 13 Cannot be connected 33 Cannot be connected P01 34 P41 14 Cannot be connected 34 Cannot be connected P02 35 P42 15 Cannot be connected 35 Cannot be connected P03 36 P43 16 Cannot be connected 36 Cannot be connected P10 37 Cannot be connected 17 Cannot be connected 37 Cannot be connected P11 38 Cannot be connected 18 Cannot be connected 38 RESET P12 39 VSS 19 Cannot be connected 39 VSS P13 40 VSS 20 Cannot be connected 40 VSS AP-B-6 Seiko Epson Corporation S1C6F016 TECHNICAL MANUAL (Rev. 1.1) aPPenDiX B PeRiPheRal CiRCuiT BOaRDS FOR S1C6F016 No. 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 Table B.2.2 S5U1C63000P6 CN2 connector pin assignment 50-pin CN2-1 connector 50-pin CN2-2 connector Pin name No. Pin name No. Pin name No. Pin name VDD (= 3.3 V) 26 SEG19 (DC) 1 VDD (= 3.3 V) 26 Cannot be connected VDD (= 3.3 V) 27 SEG20 (DC) 2 VDD (= 3.3 V) 27 Cannot be connected SEG0 (DC) 28 SEG21 (DC) 3 Cannot be connected 28 Cannot be connected SEG1 (DC) 29 SEG22 (DC) 4 Cannot be connected 29 Cannot be connected SEG2 (DC) 30 SEG23 (DC) 5 Cannot be connected 30 Cannot be connected SEG3 (DC) 31 VSS 6 Cannot be connected 31 VSS SEG4 (DC) 32 VSS 7 Cannot be connected 32 VSS SEG5 (DC) 33 SEG24 (DC) 8 Cannot be connected 33 Cannot be connected SEG6 (DC) 34 SEG25 (DC) 9 Cannot be connected 34 Cannot be connected SEG7 (DC) 35 SEG26 (DC) 10 Cannot be connected 35 Cannot be connected VSS 36 SEG27 (DC) 11 VSS 36 Cannot be connected VSS 37 SEG28 (DC) 12 VSS 37 Cannot be connected SEG8 (DC) 38 SEG29 (DC) 13 Cannot be connected 38 Cannot be connected SEG9 (DC) 39 SEG30 (DC) 14 Cannot be connected 39 Cannot be connected SEG10 (DC) 40 SEG31 (DC) 15 Cannot be connected 40 Cannot be connected SEG11 (DC) 41 VDD (= 3.3 V) 16 Cannot be connected 41 VDD (= 3.3 V) SEG12 (DC) 42 VDD (= 3.3 V) 17 Cannot be connected 42 VDD (= 3.3 V) SEG13 (DC) 43 SEG32 (DC) 18 Cannot be connected 43 Cannot be connected SEG14 (DC) 44 SEG33 (DC) 19 Cannot be connected 44 Cannot be connected SEG15 (DC) 45 SEG34 (DC) 20 Cannot be connected 45 Cannot be connected VDD (= 3.3 V) 46 SEG35 (DC) 21 VDD (= 3.3 V) 46 Cannot be connected VDD (= 3.3 V) 47 Cannot be connected 22 VDD (= 3.3 V) 47 Cannot be connected SEG16 (DC) 48 Cannot be connected 23 Cannot be connected 48 Cannot be connected SEG17 (DC) 49 Cannot be connected 24 Cannot be connected 49 Cannot be connected SEG18 (DC) 50 Cannot be connected 25 Cannot be connected 50 Cannot be connected * The CN2-1 connector outputs the signals from the SEG pins that have been configured as DC outputs by mask option. Do not connect anything to the SEG pins that have been configured as LCD drive outputs. No. 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 Table B.2.3 S5U1C63000H6 LC1 connector pin assignment 50-pin LC1-1 connector 50-pin LC1-2 connector Pin name No. Pin name No. Pin name No. Pin name COM0 26 SEG17 1 SEG42 26 Cannot be connected COM1 27 SEG18 2 SEG43 27 Cannot be connected COM2 28 SEG19 3 SEG44 28 Cannot be connected COM3 29 SEG20 4 SEG45 29 Cannot be connected COM4 30 SEG21 5 SEG46 30 Cannot be connected COM5 31 SEG22 6 SEG47 31 Cannot be connected COM6 32 SEG23 7 SEG48 32 Cannot be connected COM7 33 SEG24 8 SEG49 33 Cannot be connected SEG0 34 SEG25 9 SEG50 34 Cannot be connected SEG1 35 SEG26 10 SEG51 35 Cannot be connected SEG2 36 SEG27 11 SEG52 36 Cannot be connected SEG3 37 SEG28 12 SEG53 37 Cannot be connected SEG4 38 SEG29 13 SEG54 38 Cannot be connected SEG5 39 SEG30 14 SEG55 39 Cannot be connected SEG6 40 SEG31 15 Cannot be connected 40 Cannot be connected SEG7 41 SEG32 16 Cannot be connected 41 Cannot be connected SEG8 42 SEG33 17 Cannot be connected 42 Cannot be connected SEG9 43 SEG34 18 Cannot be connected 43 Cannot be connected SEG10 44 SEG35 19 Cannot be connected 44 Cannot be connected SEG11 45 SEG36 20 Cannot be connected 45 Cannot be connected SEG12 46 SEG37 21 Cannot be connected 46 Cannot be connected SEG13 47 SEG38 22 Cannot be connected 47 Cannot be connected SEG14 48 SEG39 23 Cannot be connected 48 Cannot be connected SEG15 49 SEG40 24 Cannot be connected 49 Cannot be connected SEG16 50 SEG41 25 Cannot be connected 50 Cannot be connected S1C6F016 Technical Manual (Rev. 1.1) Seiko Epson Corporation AP-B-7 aPPenDiX B PeRiPheRal CiRCuiT BOaRDS FOR S1C6F016 Table B.2.4 S5U1C6F016P2 CN1 connector pin assignment 10-pin CN1 connector No. Pin name 1 VDD (= 3.3 V) 2 VDD (= 3.3 V) 3 P50 4 P51 5 P52 6 P53 7 Cannot be connected 8 Cannot be connected 9 VSS 10 VSS B.3 Downloading to S5u1C63000P6 Note: The S1C6F016 circuit data is available only for the S5U1C63000P6, and it cannot be downloaded to the previous S5U1C63000P1 board. Downloading Circuit Data - when new iCe (S5u1C63000h2/S5u1C63000h6) is used The S5U1C63000P6 board comes with the FPGA that contains factory inspection data, therefore the circuit data for the model to be used should be downloaded. The following explains the downloading procedure. (1) Remove the ICE (S5U1C63000H2/S5U1C63000H6) top cover and then set the DIP switch "IOSEL2" on the S5U1C63000P6 board to the "E" position. (2) Connect the ICE to the host PC. Then turn the host PC and ICE on. (3) Invoke the debugger included in the assembler package (ver. 5 or later for the S5U1C63000H2, ver. 9 or later for the S5U1C63000H6). For how to use the ICE and debugger, refer to the manuals supplied with the ICE and assembler package. (4) Download the circuit data file (.mot) corresponding to the model by entering the following commands in the command window. >XFER >XFWR >XFCP <file name> <file name> (erase all) (download the specified file)* (compare the specified file and downloaded data) The downloading takes about 15 minutes in the S5U1C63000H2 or about 3 minutes in the S5U1C63000H6. (5) Terminate the debugger and then turn the ICE off. (6) Set the DIP switch "IOSEL2" on the S5U1C63000P6 board to the "D" position. (7) Turn the ICE on and invoke the debugger again. Debugging can be started here. B.4 usage Precautions To ensure correct use of the peripheral circuit board, please observe the following precautions. B.4.1 Operational precautions (1) Before inserting or removing cables, turn off power to all pieces of connected equipment. (2) Do not turn on power or load mask option data if all of the I/O ports (P00-P03) are held high. Doing so may activate the multiple key entry reset function. (3) Before debugging, always be sure to load mask option data. AP-B-8 Seiko Epson Corporation S1C6F016 TECHNICAL MANUAL (Rev. 1.1) aPPenDiX B PeRiPheRal CiRCuiT BOaRDS FOR S1C6F016 B.4.2 Differences with the actual iC (1) Differences in i/O <interface power supply> This tool and target system interface voltage is set to +3.3 V. To obtain the same interface voltage as in the actual IC, attach a circuit such as a level shifter on the target system side to accommodate the required interface voltage. <Output port drive capability> The drive capability of each output port on this tool is higher than that of the actual IC. When designing application system and software, refer to "Electrical Characteristics" to confirm each output port's drive capability. <Port protective diode> All I/O ports incorporate a protective diode for VDD and VSS, and the interface signals between this tool and the target system are set to +3.3 V. Therefore, this tool and the target system cannot be interfaced with voltages exceeding VDD by setting the output ports for open-drain mode. <Pull-down resistance value> The pull-down resistance values on this tool are set to 220 kW which differ from those for the actual IC. For the resistance values on the actual IC, refer to "Electrical Characteristics." Note that when using pull-down resistors to pull the input pins low, the input pins may require a certain period to reach a valid low level. Exercise caution if a key matrix circuit is configured using a combination of output and input ports, since fall delay times on these input ports differ from those of the actual IC. <Schmitt input> The P00-P03 and P10-P13 ports of the actual IC can be configured to Schmitt level input interface. The P20-P23, P30-P33, P40-P43, and P50-P53 ports support Schmitt level input interface only. This tool supports CMOS level interface only and does not supports Schmitt inputs. (2) Differences in current consumption The amount of current consumed by this tool is different significantly from that of the actual IC. Inspecting the LEDs on S5U1C63000P6 may help you keep track of approximate current consumption. The following factors/ components greatly affect device current consumption: <Those which can be verified by leDs and monitor pins> (a) Run and Halt execution ratio (verified by LEDs and monitor pins on the ICE) (b) OSC3 oscillation on/off circuit (OSCC) (c) CPU clock select circuit (CLKCHG) (d) SVD circuit on/off circuit (SVDON) <Those that can only be counteracted by system or software> (e) Current consumed by the internal pull-down resistors (f) Input ports in a floating state (3) Functional precautions <lCD driver> * Use the LC1 connector (max. 56SEG x 8COM) on the ICE (S5U1C63000H2/S5U1C63000H6) to drive an LCD panel. Do not connect anything to the connector pins shown below. - Unused SEG pins - SEG pins configured for DC output by mask option (Use the S5U1C63000P6 CN2 connector.) - Pins configured for I/O port or R/F converter (SEG36-SEG55) For other precautions on LCD drive outputs, refer to the ICE manual. S1C6F016 Technical Manual (Rev. 1.1) Seiko Epson Corporation AP-B-9 aPPenDiX B PeRiPheRal CiRCuiT BOaRDS FOR S1C6F016 <SVD circuit> * The SVD function in this tool sets the detection results by comparing the SVDS[3:0] register value with the settings of the SW1 and SW2 on S5U1C6F016P2 without changing the supply voltage. * There is a finite delay time from when the power to the SVD circuit turns on until actual detection of the voltage. There is no delay in this tool, which differs from that of the actual IC. Refer to "Electrical Characteristics" when setting the appropriate wait time for the actual IC. <Oscillation circuit> * A wait time is required before oscillation stabilizes after the OSC3 oscillation control circuit (OSCC) is turned on. In this tool, even when OSC3 oscillation is changed (CLKCHG) without a wait time, OSC3 will function normally. Refer to "Electrical Characteristics" when setting the appropriate wait time for the actual IC. * Use separate instructions to switch the clock from OSC3 to OSC1 and to turn off the OSC3 oscillation circuit. If these operations are executed simultaneously with a single instruction, although this tool functions normally, may not function properly in the actual IC. * Because the logic level of the oscillation circuit is high, the timing at which the oscillation starts in this tool differs from that of the actual IC. * This tool includes oscillation circuits for OSC1 and OSC3. Note that the OSC3 oscillation circuit in this tool can generate the OSC3 clock even if no resonator is connected. * The oscillation frequencies in this tool are as follows: - OSC1 oscillation circuit (crystal oscillation): fixed at 32.768 kHz - OSC3 oscillation circuit (ceramic option is selected): 4.1943 MHz (crystal oscillation) - OSC3 oscillation circuit (CR option is selected): about 100 kHz to 8 MHz (CR oscillation) <access to undefined address space> If any undefined space in the S1C6F016's internal ROM/RAM or I/O is accessed for data read or write operations, the read/written value is indeterminate. Additionally, it is important to remain aware that indeterminate state differs between this tool and the actual IC. Note that the ICE incorporates the program break function caused by accessing to an undefined address space. <Reset circuit> Keep in mind that the operation sequence from when the ICE and the peripheral circuit boards (S5U1C63000P6 and S5U1C6F016P2) are powered on until the time at which the program starts running differs from the sequence from when the actual IC is powered on till the program starts running. This is because S5U1C63000P6 becomes capable of operating as a debugging system after the user program and optional data are downloaded. When operating the ICE after placing it in free-running mode*, always apply a system reset. A system reset can be performed by pressing the reset switch on S5U1C63000P6, by a reset pin input, or by holding the input ports high simultaneously. (* Free running mode: supported by S5U1C63000H1/2 only) <i/O ports> Do not set the P0x ports used for multiple key entry reset to output mode as this tool may be reset. <R/F converter> * The R/F converter function is implemented using the S1C6F016 chip included in the S5U1C6F016P2 board. * If the debugger makes program execution to break while the R/F converter is counting the oscillation, the R/F converter does not stop counting. Note that the R/F converter will not able to load a proper result if program execution is resumed from that point. * The following shows the oscillation characteristics (reference value) of the R/F converter on the S5U1C6F016P2: AP-B-10 Seiko Epson Corporation S1C6F016 TECHNICAL MANUAL (Rev. 1.1) aPPenDiX B PeRiPheRal CiRCuiT BOaRDS FOR S1C6F016 R/F converter oscillation frequency - capacitance characteristic (reference value) R = 50 k 1,000,000 Oscillation frequency [Hz] 100,000 10,000 1,000 100 10 1 470 1,000 2,200 Capacitance [pF] 4,700 R/F converter oscillation frequency - resistance characteristic (reference value) C = 1000 pF 1,000,000 Oscillation frequency [Hz] 100,000 10,000 1,000 100 10 1 1 10 100 1,000 Resistance [k] S1C6F016 Technical Manual (Rev. 1.1) Seiko Epson Corporation AP-B-11 aPPenDiX B PeRiPheRal CiRCuiT BOaRDS FOR S1C6F016 B.5 Product Specifications B.5.1 Specifications of S5u1C63000P6 S5u1C63000P6 Dimension: Weight: Power supply: 254 mm (wide) x 144.8 mm (depth) x 16 mm (height) (including screws) Approx. 250 g DC 5 V 5%, less than 1 A (supplied from ICE main unit) i/O connection cable (80-pin) S5U1C63000P6 connector: KEL8830E-080-170L-F Cable connector (80-pin): KEL8822E-080-171-F Cable connector (40-pin): 3M7940-6500SC 1 pair Cable: 40-conductor flat cable (1 pair) Interface: CMOS interface (3.3 V) Length: Approx. 40 cm i/O connection cable (100-pin) S5U1C63000P6 connector: KEL8830E-100-170L-F Cable connector (100-pin): KEL8822E-100-171-F Cable connector (50-pin): 3M7950-6500SC 1 pair Cable: 50-conductor flat cable (1 pair) Interface: CMOS interface (3.3 V) Length: Approx. 40 cm accessories 40-pin connector for connecting to target system: 3M3432-6002LCPL x 2 50-pin connector for connecting to target system: 3M3433-6002LCPL x 2 B.5.2 Specifications of S5u1C6F016P2 S5u1C6F016P2 Dimension: Weight: Power supply: 254 mm (width) x 144.8 mm (depth) x 13 mm (height) (including screws) Approx. 170 g DC 5 V 5%, less than 50 mA (supplied from ICE main unit and converted into 3.3 V by the onboard regulator) i/O connection cable (10-pin) S5U1C6F016P2 connector: 3M3654-5002-PL Cable connector (10-pin): 3M7910-6500SC Cable: 10-conductor flat cable Interface: CMOS interface (3.3 V) Length: Approx. 40 cm accessories 10-pin connector for connecting to target system: 3M3662-6002LCPL x 1 Discreet platform (for mounting external resistors and capacitors of the R/F converter): DIS12-016-403 (KEL) x 2 AP-B-12 Seiko Epson Corporation S1C6F016 TECHNICAL MANUAL (Rev. 1.1) aPPenDiX C FlaSh eePROM PROGRaMMinG Appendix C Flash EEPROM Programming C.1 Outline of Writing Tools The S1C6F016 Flash EEPROM programming tools are available for two interfaces: USB interface and RS-232C interface. These Flash EEPROM writers feature smaller size and weight and are operable with the same power supply as the microcomputer, this makes it possible to simply configure an on-board Flash EEPROM programming environment. uSB interface type * USB-Serial On Board Writer (product name: S5U1C88000W4) * On Board Writer Control Software (OBPW63.EXE, RW6F016.INI) * * USB-Serial conversion driver * Operating voltage: 3.3 V 0.3 V (The power supply for the target can be used.) PC interface: USB Ver. 1.1 Note: When using a USB hub to connect the USB-Serial On Board Writer to the PC, the USB hub should be driven with an external power supply. So use a USB hub that operates with an external power supply. RS-232C interface type * On Board Writer (product name: S5U1C88000W3) * On Board Writer Control Software (OBPW63.EXE, RW6F016.INI) * Operating voltage: 3.3 V 0.3 V (The power supply for the target can be used.) PC interface: EIA-RS-232C The On Board Writer Control Software and USB-Serial conversion driver are included in the S1C63 Family Assembler Package 2 (S5U1C63000A2) or later. The On Board Writer Control Software (OBPW63.EXE, RW6F016.INI) supports both USB interface type and RS-232C interface type Flash EEPROM writers. C.2 Serial Programming C.2.1 Serial Programming environment Prepare a personal computer system as a host computer and the data for writing into the built-in Flash microcomputer. (1) Personal computer * IBM-PC/AT or compatible with a USB port or RS-232C port (2) OS * Windows 2000/XP English or Japanese version (3) Flash eePROM writing tools * S5U1C88000W4 (USB interface type) package or S5U1C88000W3 (RS-232C interface type) package * On Board Writer Control Software (OBPW63.EXE, RW6F016.INI) * * USB-Serial conversion driver (required only when the USB-Serial On Board Writer is used) * The On Board Writer Control Software and USB-Serial conversion driver are included in the S1C63 Family Assembler Package 2 (S5U1C63000A2) or later. S1C6F016 Technical Manual (Rev. 1.1) Seiko Epson Corporation AP-C-1 aPPenDiX C FlaSh eePROM PROGRaMMinG (4) user data (program file, data file for data ROM, and segment option heX file) Execute the HEX converter hx63 to create the program files (C3xxxyyy.HSA, C3xxxyyy.LSA) and data file for the data ROM (C3xxxyyy.CSA) from the object file (C3xxxyyy.ABS). Refer to the "S5U1C63000A Manual" for details of the HEX converter. Object file C3xxxyyy.ABS Execute the HEX Data Converter in the S5U1C63000Axx development system C3xxxyyy.HSA C3xxxyyy.LSA C3xxxyyy.CSA Data file for data ROM Program files Figure C.2.1.1 hx63 execution flow Assign the display memory to the LCD output terminals by executing the segment option generator winsog to create the segment option HEX file (C3xxxyyy.SSA)*. Refer to the "S5U1C63000A Manual" for details of the segment option generator. Device information definition file C3xxxyyy.INI Execute the segment option generator in the S5U1C63000Axx development system C3xxxyyy.SAD C3xxxyyy.SSA C3xxxyyy.SDC Segment assignment data file Segment option HEX data file Segment option document file Figure C.2.1.2 winsog execution flow * Although the segment option generator winsog generates a segment assignment data file (C3xxxyyy.SAD) and a segment option document file (C3xxxyyy.SDC) as well as a segment option HEX file (C3xxxyyy.SSA), these files are not written to the S1C6F016. C.2.2 System Connection for Serial Programming Below shows connection diagrams between the PC and the USB-Serial On Board Writer (S5U1C88000W4) with a target, and between the PC and the On Board Writer (S5U1C88000W3) with a target. When the uSB-Serial On Board Writer (S5u1C88000W4) is used S5u1C88000W4 (uSB-Serial On Board Writer) USB Target VDD VSS USB interface cable + 3.3 V power supply - SIO cable Figure C.2.2.1 Flash EEPROM programming system connection diagram (USB interface type) AP-C-2 Seiko Epson Corporation S1C6F016 TECHNICAL MANUAL (Rev. 1.1) aPPenDiX C FlaSh eePROM PROGRaMMinG When the On Board Writer (S5u1C88000W3) is used S5u1C88000W3 (On Board Writer) COMx Target VDD VSS RS-232C interface cable + 3.3 V power supply - SIO cable Figure C.2.2.2 Flash EEPROM programming system connection diagram (RS-232C interface type) The system should be connected according to the following procedure. (1) Make sure the power for the personal computer is switched off. (2) As shown in the above figures, connect between the USB-Serial On Board Writer (S5U1C88000W4) or On Board Writer (S5U1C88000W3) and the PC using the interface cable included with the package. Notes: * Turn the personal computer off before connecting and disconnecting the On Board Writer (S5U1C88000W3). The USB-Serial On Board Writer (S5U1C88000W4) can be connected after the PC is turned on. * Secure the RS-232C cable with the connector screws to prevent malfunction. C.2.3 Serial Programming Procedure (1) Connecting the system Connect the system as shown in Section C.2.2, "System connection for serial programming." (2) Power on Turn the personal computer on. (3) Checking the serial port assignment (Required only when the On Board Writer is used) Check the serial port assignment on the personal computer. The On Board Writer uses the COM1 port by default setting. (4) installing the uSB-Serial conversion driver (Required only when the uSB-Serial On Board Writer is used) When the USB-Serial On Board Writer (S5U1C88000W4) is connected for the first time, a dialog box appears on the PC screen to prompt the user to install the driver. Install the USB-Serial conversion driver by following the prompts. The USB-Serial conversion driver was copied into the folders shown below when the S1C63 Family Assembler Package 2 (S5U1C63000A2) was installed. Specify a folder according to the serial number of the USB-Serial On Board Writer as the driver location. Table C.2.3.1 USB-Serial conversion driver storing folder S5U1C88000W4100 serial number Driver storing folder (printed on the back side) 0Z04W73001-0Z04W84050 \EPSON\S1C63\writer\driver 0Z04W87001 or later \EPSONVS1C63\writer\driver1 (5) Checking the serial port assignment (Required only when the uSB-Serial On Board Writer is used) Open the Windows [Control Panel] [System] [Hardware] tab [Device Manager] to check the COM port to which the USB-Serial port is assigned. The USB-Serial conversion driver assigns a logical COM port to the physical USB port and transfers the COM port input/output to the USB input/output. Thus the On Board Writer Control Software can control the USBSerial On Board Writer connected to the USB port through the assigned COM port. S1C6F016 Technical Manual (Rev. 1.1) Seiko Epson Corporation AP-C-3 aPPenDiX C FlaSh eePROM PROGRaMMinG (6) Preparing the On Board Writer Control Software The On Board Writer Control Software was copied in the "\EPSON\S1C63\writer\OBPW" folder when the S1C63 Family Assembler Package 2 (S5U1C63000A2) was installed. When using the On Board Writer Control Software in another folder, the following two files should be copied from the OBPW folder. * OBPW63.EXE * RW6F016.INI (7) Connecting the target board to the uSB-Serial On Board Writer or On Board Writer As Figure C.2.2.1 or C.2.2.2 shows, connect the target board to the USB-Serial On Board Writer (S5U1C88000W4) or On Board Writer (S5U1C88000W3) using the supplied SIO cable. (8) Connecting the power supply for Flash eePROM programming Connect the power supply for Flash EEPROM programming (3.3 V) to the target board. Notes: * Turn off the power of the target board except for the Flash EEPROM programming power supply. * Since Flash EEPROM programming uses a 3.3 V power source, be careful of the voltage ratings of the parts on the target board. (9) Turning the Flash eePROM programming power on Turn the Flash EEPROM programming power on. This also supplies the power to the USB-Serial On Board Writer (S5U1C88000W4) or On Board Writer (S5U1C88000W3) through the SIO cable. (10) Starting up the On Board Writer Control Software Double-click the OBPW63.exe icon. The [Initial File] dialog box shown below appears when the On Board Writer Control Software starts up. Select the initial file with the same name as the microcomputer model. RWxxxxx.ini xxxxx: microcomputer model name (e.g. 6F016 for the S1C6F016) After an initial file is selected, the window shown below appears. AP-C-4 Seiko Epson Corporation S1C6F016 TECHNICAL MANUAL (Rev. 1.1) aPPenDiX C FlaSh eePROM PROGRaMMinG (11) Selecting a serial port Click the [Setting] button (or choose [Setting] from the [Option] menu) to display the [Settings] dialog box. [Setting] button Click the [Com] tab to open the page shown below. When USB-Serial On Board Writer (USB interface type) is used, select the COM port that was determined in Step (5). When the On Board Writer (RS-232C interface type) is used, select the COM port to which the RS-232C cable has been connected. (12) loading user data to the personal computer Program files Click the [Load_IP] button (or choose [Load IPROM] from the [Command] menu) to display the [Select file] dialog box. [Load_IP] button Choose the HSA file to be written to the Flash EEPROM using the [Browse] button and then click [OK]. The corresponding LSA file is chosen at the same time. [Browse] button When data is loaded normally, "Complete" is displayed in the output window. Note: Make sure that the HSA and LSA files to be loaded are located in the same folder. S1C6F016 Technical Manual (Rev. 1.1) Seiko Epson Corporation AP-C-5 aPPenDiX C FlaSh eePROM PROGRaMMinG Data file for data ROM Click the [Load_CP] button (or choose [Load CPROM] from the [Command] menu) to display the [Select file] dialog box. [Load_CP] button Choose the CSA file to be written to the Flash EEPROM using the [Browse] button and then click [OK]. When data is loaded normally, "Complete" is displayed in the output window. Segment option heX file Click the [Load_Seg] button (or choose [Load Segment] from the [Command] menu) to display the [Select file] dialog box. [Load_Seg] button Choose the SSA file using the [Browse] button and then click [OK]. When data is loaded normally, "Complete" is displayed in the output window. (13) erasing Flash eePROM data Click the [Erase_IP] button (or choose [Erase IPROM] from the [Command] menu) to display an information dialog box. Clicking the [OK] button starts erasing the program, data and segment option. [Erase_IP] button When the Flash EEPROM is erased normally, "Complete" is displayed in the output window. Notes: * Inspection data is written to the Flash EEPROM at shipment, so erase it once to initialize the contents. * The Flash EEPROM is protected against a read out when user data is written at Seiko Epson's factory. The protection is released after the contents have been erased by executing "Erase_ IP." (14) Blank check after erasing Click the [Blank_IP] button (or choose [Blank Check IPROM] from the [Command] menu) to display an information dialog box. Clicking the [OK] button starts process that checks if the program, data and segment option are completely erased. [Blank_IP] button When the blank check is finished normally, "Complete" is displayed in the output window. (15) Writing user data Click the [Program_IP] button (or choose [Program IPROM] from the [Command] menu) to display an information dialog box. Clicking the [OK] button starts writing the loaded data to the program, data and segment option. [Program_IP] button When writing is finished normally, "Complete" is displayed in the output window. Note: Do not send the writer control window behind any other applications as it may cause a communication error. AP-C-6 Seiko Epson Corporation S1C6F016 TECHNICAL MANUAL (Rev. 1.1) aPPenDiX C FlaSh eePROM PROGRaMMinG (16) Verifying user data after writing Click the [Verify_IP] button (or choose [Verify IPROM] from the [Command] menu) to display an information dialog box. Clicking the [OK] button starts verification of the program, data and segment option. [Verify_IP] button When verification is finished without any error, "Complete" is displayed in the output window. (17) Turning the Flash eePROM programming power off Turn the Flash EEPROM programming power off. (18) Disconnecting the target board Disconnect the target board after checking that writing has finished normally. Note: Make sure that the Flash EEPROM programming power is off before disconnecting and connecting the target board. (19) Terminating the On Board Writer Control Software Choose [Exit] from the [File] menu of the On Board Writer control window or click the close box to terminate the On Board Writer Control Software. To continue writing, repeat from step (7) to step (19). (20) Power off Turn the personal computer off. C.2.4 Connection Diagram for Serial Programming The figures and tables below show the connection diagram on the target board and the signal specifications. uSB interface type: when the uSB-Serial On Board Writer (S5u1C88000W4) is used Target board CG1 OSC1 S1C6F016 X'tal OSC2 RCR CG3 OSC3 Ceramic OSC4 CD3 10-pin target board connector To On Board Writer VDDF VDD CLK VSS RXD TXD RESET SPRG VSS SPRG 1 VD1 C1 VDD DCLK DRXD DTXD RESET DMOD 10 3.3 V + CP - TEST VSS Clock control circuit Serial I/F for debugging Debug control circuit Flash EEPROM 16K + 4K bytes Flash control circuit Data bus Address bus Figure C.2.4.1 Connection diagram for on-board programming (USB interface type) S1C6F016 Technical Manual (Rev. 1.1) Seiko Epson Corporation AP-C-7 aPPenDiX C FlaSh eePROM PROGRaMMinG Connector pin No. 1 2 3 4 5 6 7 8 9 10 Table C.2.4.1 Signal specifications (USB interface type) Signal S1C6F016 pin Description name to be connected VDDF Programming power supply pin VDD pin VDD Power supply pin VDD pin CLK System clock output DCLK pin VSS Ground pin VSS pin RXD Serial I/F data input pin DTXD pin TXD Serial I/F data output pin DRXD pin RESET Initial reset output pin RESET pin SPRG Programming mode setup output pin N.C. (for negative polarity I/O models) VSS Ground pin VSS pin SPRG Programming mode setup output pin DMOD pin (for positive polarity I/O models) Table C.2.4.2 Connectors for connecting USB-Serial On Board Writer Name Product code Box header (male) [target side] 3662-6002LCPL (3M) or equivalent Socket connector (female) [SIO cable side] Socket connector 7910-B500FL (3M) Strain relief 3448-7910 (3M) or equivalent RS-232C interface type: when the On Board Writer (S5u1C88000W3) is used Target board CG1 OSC1 S1C6F016 X'tal OSC2 RCR CG3 OSC3 Ceramic OSC4 CD3 16-pin target board connector VDDF VDD CLK VSS Reserved VSS RXD To VSS On Board TXD Writer VSS RESET VSS SPRG VSS SPRG Reserved 1 VD1 C1 VDD DCLK Clock control circuit Flash EEPROM 16K + 4K bytes DRXD DTXD Serial I/F for debugging RESET DMOD CRES 3.3 V + CP - 16 TEST VSS Debug control circuit Flash control circuit Data bus Address bus Figure C.2.4.2 Connection diagram for on-board programming (RS-232C interface type) AP-C-8 Seiko Epson Corporation S1C6F016 TECHNICAL MANUAL (Rev. 1.1) aPPenDiX C FlaSh eePROM PROGRaMMinG Table C.2.4.3 Signal specifications (RS-232C interface type) Signal S1C6F016 pin Description name to be connected VDDF Programming power supply pin VDD pin VDD Power supply pin VDD pin CLK System clock output pin DCLK pin Reserved Reserved N.C. RXD Serial I/F data input pin DTXD pin TXD Serial I/F data output pin DRXD pin RESET Initial reset output pin RESET pin SPRG Programming mode setup output pin N.C. (for negative polarity I/O models) 15 SPRG Programming mode setup output pin DMOD pin (for positive polarity I/O models) 16 Reserved Reserved N.C. 4, 6, 8, 10, VSS Ground pin VSS pin 12, 14 Connector pin No. 1 2 3 5 7 9 11 13 Table C.2.4.4 Connectors for connecting On Board Writer Name Product code Box header (male) [target side] 3408-6002LCFL (3M) or equivalent Socket connector (female) [SIO cable side] Socket connector 7916-B500FL (3M) Strain relief 3448-7916 (3M) or equivalent Notes: * Prepare a 3.3 V power supply for Flash EEPROM programming, since the power (3.3 V) of the On Board Writer must be supplied from the target board. * Since Flash EEPROM programming uses a 3.3 V power source, be careful of the voltage ratings of the parts on the target board. C.3 On Board Writer Control Software C.3.1 Starting up Double-click the OBPW63.exe icon to start up the On Board Writer system. The dialog box shown below appears when the On Board Writer Control Software starts up. Select the initial file with the same name as the microcomputer model. RWxxxxx.ini xxxxx: microcomputer model name (e.g. 6F016 for the S1C6F016) After an initial file is selected, the window shown below appears. S1C6F016 Technical Manual (Rev. 1.1) Seiko Epson Corporation AP-C-9 aPPenDiX C FlaSh eePROM PROGRaMMinG Command window Accepts the commands input from the keyboard. Output window Displays the execution results. C.3.2 Setup Click the [Setting] button (or choose [Setting] from the [Option] menu) to display the [Settings] dialog box. [Setting] button Selecting a serial port ([Com] tab) Select the same COM channel as the serial port configuration on the personal computer. Specifying the log file ([Folder] tab) When saving the execution results to a log file, enter (or choose) the log file name and place a check in the [Create Log] check box. To disable logging, remove the check from the check box. AP-C-10 Seiko Epson Corporation S1C6F016 TECHNICAL MANUAL (Rev. 1.1) aPPenDiX C FlaSh eePROM PROGRaMMinG Specifying the editor path ([editor] tab) Specify the path to the editor used to open a log file from the On Board Writer Control Software. "notepad.exe" is used as the default editor unless specified. S1C6F016 Technical Manual (Rev. 1.1) Seiko Epson Corporation AP-C-11 aPPenDiX C FlaSh eePROM PROGRaMMinG C.3.3 Command Details All the On Board Writer commands such as Flash EEPROM writing can be executed using the buttons on the window. This section explains the commands individually in the following manner. no. Command name Function: Shows the command function. Usage: Button Menu [Command] menu - [Program IPROM] Keyboard >FWI Shows the button, menu command and typing command line to execute the command. Description: Describes the operation and display contents after executing the command. If "A progress window appears to show progress of the process." is described here, a progress window is displayed while the command is executing and the [Cancel] button on the window allows termination of the command being executed. Note: Describes precautions. 1. lOaD PROGRaM (hSa file, lSa file) Function: Loads program files (xxxxxx.HSA and xxxxxx.LSA) to the memory on the personal computer. Usage: Button Menu [Command] menu - [Load IPROM] Keyboard >LI drive:\folder\file name (drive:\folder\file name: HSA file name) Description: (1) The [Select file] dialog box appears. [Browse] button (2) Clicking the [Browse] button displays the Windows standard file select dialog box. Choose the file to be loaded from the dialog box. Then click the [OK] button. The LSA file will be loaded simultaneously by only choosing the HSA file. (3) When data is loaded normally, "Complete" is displayed in the output window. Notes: * This command can load files in Motorola S2 format only. * Make sure that the HSA and LSA files to be loaded are located in the same folder. AP-C-12 Seiko Epson Corporation S1C6F016 TECHNICAL MANUAL (Rev. 1.1) aPPenDiX C FlaSh eePROM PROGRaMMinG 2. lOaD DaTa (CSa file) Function: Loads a data file for the data ROM (xxxxxx.CSA) to the memory on the personal computer. Usage: Button Menu [Command] menu - [Load CPROM] Keyboard >LC drive:\folder\file name (drive:\folder\file name: CSA file name) Description: (1) The [Select file] dialog box appears. [Browse] button (2) Clicking the [Browse] button displays the Windows standard file select dialog box. Choose the file to be loaded from the dialog box. Then click the [OK] button. (3) When data is loaded normally, "Complete" is displayed in the output window. Note: This command can load files in Motorola S2 format only. 3. lOaD SeGMenT (SSa file) Function: Loads a segment option HEX file (xxxxxx.SSA) to the memory on the personal computer. Usage: Button Menu [Command] menu - [Load Segment] Keyboard >LS drive:\folder\file name (drive:\folder\file name: SSA file name) Description: (1) The [Select file] dialog box appears. [Browse] button (2) Clicking the [Browse] button displays the Windows standard file select dialog box. Choose the file to be loaded from the dialog box. Then click the [OK] button. (3) When data is loaded normally, "Complete" is displayed in the output window. Note: This command can load files in Motorola S2 format only. S1C6F016 Technical Manual (Rev. 1.1) Seiko Epson Corporation AP-C-13 aPPenDiX C FlaSh eePROM PROGRaMMinG 4. eRaSe PROGRaM, DaTa, SeGMenT Function: Erases program, data and segment option HEX data. Usage: Button Menu [Command] menu - [Erase IPROM] Keyboard >FERSI Description: (1) An information dialog box appears. (2) Clicking the [OK] button starts erasing the IPROM, CPROM and segment option HEX data. (3) A progress window appears to show progress of the process while the command is executing. Clicking the [Cancel] button terminates the process. (4) Read protection is removed after the Flash EEPROM contents has been erased. (5) When the Flash EEPROM is erased normally, "Complete" is displayed in the output window. Note: When the process is terminated, the Flash EEPROM must be erased before data can be written. 5. BlanK CheCK PROGRaM, DaTa, SeGMenT Function: Checks whether the program, data and segment option HEX data are completely erased or not. Usage: Button Menu [Command] menu - [Blank Check IPROM] Keyboard >FEI Description: (1) Starts a blank check. (2) A progress window appears to show progress of the process. Clicking the [Cancel] button terminates the process. (3) When the check is finished without finding any address that is not erased in program, data and segment option HEX data, "Complete" is displayed in the output window. (4) If error addresses that have not been erased are found, the address and data are displayed. Example: Address READ 0100 0000 0101 0000 0102 0000 0103 0000 : : Note: When an erase error is detected, the Flash EEPROM must be erased before data can be written. AP-C-14 Seiko Epson Corporation S1C6F016 TECHNICAL MANUAL (Rev. 1.1) aPPenDiX C FlaSh eePROM PROGRaMMinG 6. PROGRaM PROGRaM, DaTa, SeGMenT Function: Writes the data loaded by the [Load IPROM], [Load CPROM] and [Load Segment] commands to the Flash EEPROM. Usage: Button Menu [Command] menu - [Program IPROM] Keyboard >FWI >FWI /P (The protect processing will be performed after data has been written.) Description: (1) An information dialog box appears. (2) Select the [Yes] radio button if data protection is required. (3) Clicking the [OK] button starts write process. (4) A progress window appears to show progress of the process. Clicking the [Cancel] button terminates the process. (5) When protection has been specified, the protect processing is performed. (6) When writing is finished normally, "Complete" is displayed in the output window. Note: Do not send the writer control window behind any other applications as it may cause a communication error. 7. VeRiFY PROGRaM, DaTa, SeGMenT Function: Compares the data loaded by the [Load IPROM], [Load CPROM] and [Load Segment] commands and the data read from the Flash EEPROM. Usage: Button Menu [Command] menu - [Verify IPROM] Keyboard >FVI Description: (1) Starts verification process. (2) A progress window appears to show progress of the process. Clicking the [Cancel] button terminates the process. (3) When both data are the same, "Complete" is displayed in the output window. (4) When a verify error is detected, the error address and data are displayed. S1C6F016 Technical Manual (Rev. 1.1) Seiko Epson Corporation AP-C-15 aPPenDiX C FlaSh eePROM PROGRaMMinG 8. ReaD PROGRaM, DaTa, SeGMenT Function: Reads the program, data and segment option HEX data in the Flash EEPROM to the memory on the personal computer. Usage: Button Menu [Command] menu - [Read IPROM] Keyboard >FRI Description: (1) An information dialog box appears. (2) Clicking the [OK] button starts read process. (3) A progress window appears to show progress of the process. Clicking the [Cancel] button terminates the process. (4) When data is read normally, "Complete" is displayed in the output window. Note: The memory data on the personal computer is overwritten with the read data. 9. MaCRO Function: Successively executes the commands described in a macro file. Usage: Button Menu [Command] menu - [Macro] Keyboard None Description: (1) A file-select dialog box appears. (2) Select a macro file and then click the [OK] button. The macro file will be loaded and the described commands will be executed. Macro file: Use a text editor to create macro files. ".cmd" is recommended for the file extension. Write the commands in order of execution and save as a text file. The command should be written one line by one line in the command line format listed at Usage: Keyboard. Any words following a ";" are regarded as a comment. Example: Macro file <test.cmd> ;-- PROGRAM -Comment LI D:\WORK\C6F016.hsa Load file FERSI Erase data FEI Blank check FWI Program FVI Verify check AP-C-16 Seiko Epson Corporation S1C6F016 TECHNICAL MANUAL (Rev. 1.1) aPPenDiX C FlaSh eePROM PROGRaMMinG 10. DuMP MeMORY Function: Displays the contents of the PC memory in hexadecimal numbers. The memory contents can be edited in the [Dump] window. Usage: Button [Dump IPROM] button Menu [Command] menu - [Dump IPROM] Keyboard >DI address (address: Display start address; optional) Description: (1) The [Dump] window appears. Displays the last page. Displays the next page. Display start address is specified. Displays the previous page. Displays the top page. (2) To edit the memory contents, enter a value after placing the cursor on the address to be edited. When this command is entered from the keyboard, the memory contents are displayed in the output window. Memory dump format: 00000 00008 +0/+8 +1/+9 +2/+A +3/+B +4/+C +5/+D +6/+E +7/+F ASCII 1417 182B 0069 1013 164D 044B 0801 1645 ...+.i...M.K...E 121B 0E29 062D 1203 0613 025B 0471 140F ...).-.....[.q.. The row on the left side indicates addresses in the PC memory area. The second to ninth rows show the 8 steps of program code that begins with the address on the left. For example, "1417," "182B" and "1645" that appear at the second line of the above example indicate the 13-bit program code stored in addresses 00000H, 00001H and 00007H, respectively. "121B" appearing in the third line indicates the 13-bit code stored in address 00008H. The row on the right side indicates the ASCII characters corresponding to the code listed in that line. S1C6F016 Technical Manual (Rev. 1.1) Seiko Epson Corporation AP-C-17 aPPenDiX C FlaSh eePROM PROGRaMMinG 11. OPen lOG File Function: Opens a log file. Usage: Button [Open Log file] button Menu [File] menu - [Open Log File] Keyboard None Description: The specified editor starts up and opens the specified log file. The editor and the log file must be specified beforehand in the [Editor] tab screen of the [Settings] dialog box and the [Folder] tab screen, respectively. 12. SaVe PROGRaM Function: Saves the program stored in the PC memory to a file. Usage: Button [Save IPROM] button Menu [File] menu - [Save IPROM] Keyboard >SI drive:\folder\file name (drive:\folder\file name: HSA file name) Description: (1) The Windows standard file select dialog box appears. Choose or enter the file name for saving data. (2) The contents in the PC memory are saved to Motorola S2 format files (.HSA and .LSA). 13. SaVe DaTa Function: Saves the data stored in the PC memory to a file. Usage: Button [Save CPROM] button Menu [File] menu - [Save CPROM] Keyboard >SC drive:\folder\file name (drive:\folder\file name: CSA file name) Description: (1) The Windows standard file select dialog box appears. Choose or enter the file name for saving data. (2) The contents in the PC memory are saved to a Motorola S2 format file (.CSA). AP-C-18 Seiko Epson Corporation S1C6F016 TECHNICAL MANUAL (Rev. 1.1) aPPenDiX C FlaSh eePROM PROGRaMMinG C.3.4 list of Commands No. Table C.3.4.1 List of commands Menu Button Command line Function 1 LI drive\folder\file name [Command]-[Load IPROM] Load HSA and LSA files 2 LC drive\folder\file name [Command]-[Load CPROM] Load CSA file 3 LS drive\folder\file name [Command]-[Load Segment] Load SSA file 4 FERSI [Command]-[Erase IPROM] 5 FEI [Command]-[Blank Check IPROM] 6 FWI FWI /P [Command]-[Program IPROM] 7 FVI [Command]-[Verify IPROM] 8 FRI [Command]-[Read IPROM] 9 - [Command]-[Macro] Read/execute macro file 10 DI address [Command]-[Dump IPROM] Dump memory data 11 - [File]-[Open Log File] Open log file 12 SI drive\folder\file name [File]-[Save IPROM] Save program 13 SC drive\folder\file name [File]-[Save CPROM] Save data for data ROM 14 LOG - Start logging 15 LOG /E - End logging Erase program/data for data ROM/ segment data and remove read protection Program/data for data ROM/segment data blank check Write program/data for data ROM/ segment data (/P specifies protect processing.) Verify program/data for data ROM/ segment data Read program/data for data ROM/ segment data C.3.5 list of error Messages Error message Command timeout Receive NAK Send error COM Port Open Error Invalid File Format Data Size Over flow Verify Error Erase Error Protected Error Abort by operator Complete Illegal inifile data Can not find ** S1C6F016 Technical Manual (Rev. 1.1) Table C.3.5.1 List of error messages Description Communication time out Communication error Communication error Port open error The file is not a Motorola S2 format file. The data size in the file exceeds the Flash EEPROM size. Verify error The erase process has failed. The Flash EEPROM has read-protected. The process is terminated. The process is terminated normally. The INI file contains illegal description. ** cannot be found. Seiko Epson Corporation Display location Output window Output window Output window Output window Output window Output window Output window Output window Output window Output window Output window Output window/dialog box Dialog box AP-C-19 aPPenDiX C FlaSh eePROM PROGRaMMinG C.4 Flash eePROM Programming notes (1) The Flash EEPROM programming requires a 3.3 V power source voltage. (2) Since Flash EEPROM programming uses a 3.3 V power source, be careful of the voltage ratings of the parts on the target board. (3) After connecting the Flash EEPROM Writer to the serial port of the personal computer, secure the RS-232C cable with the connector screws. (4) Make sure the personal computer is off before connecting or disconnecting the On Board Writer (S5U1C88000W3) to/from the personal computer. The USB-Serial On Board Writer (S5U1C88000W4) can be connected after the PC is turned on. (5) Make sure the target is off before connecting or disconnecting the On Board Writer to/from the target (S1C6F016). AP-C-20 Seiko Epson Corporation S1C6F016 TECHNICAL MANUAL (Rev. 1.1) aPPenDiX D POWeR SaVinG Appendix D Power Saving Current consumption will vary dramatically, depending on CPU operating mode, operation clock frequency, and the peripheral circuits being operated. Listed below are the control methods for saving power. D.1 Power Saving by Clock Control Figure D.1.1 illustrates the S1C6F016 clock system. Oscillation circuit OSC1 oscillation circuit fOSC1 (32.768 kHz) Gate System clock S1C63000 CPU Internal logic fOSC3 OSC3 oscillation circuit SLEEP HALT On/Off fOSC1 divider fOSC3 divider Clock manager Watchdog timer fOSC1*1/128 fOSC1 or fOSC3 Gate Integer multiplier fOSC1*1/128 Gate Clock timer fOSC1*1/128 Gate Stopwatch timer fOSC1, fOSC1*1/128 Gate Sound generator fOSC1*1/16 Gate LCD system voltage regulator (booster) fOSC1*1/16-1/256 Gate P0 key input interrupt noise rejector fOSC1*1/16-1/256 Gate P1 key input interrupt noise rejector fOSC1*1/1-1/256 fOSC3*1/1-1/256 Gate FOUT fOSC1*1/1-1/256 fOSC3*1/1-1/256 Gate Programmable timer 0 fOSC1*1/1-1/256 fOSC3*1/1-1/256 Gate Programmable timer 1 fOSC1*1/1-1/256 fOSC3*1/1-1/256 Gate Programmable timer 2 fOSC1*1/1-1/256 fOSC3*1/1-1/256 Gate Programmable timer 3 fOSC1*1/1-1/4 fOSC3*1/1-1/4 Gate Serial interface fOSC1*1/1-1/4 fOSC3*1/1-1/4 Gate R/F converter Figure D.1.1 Clock system S1C6F016 Technical Manual (Rev. 1.1) Seiko Epson Corporation AP-D-1 aPPenDiX D POWeR SaVinG This section describes clock systems that can be controlled via software and power-saving control details. For more information on control registers and control methods, refer to the respective peripheral circuit sections. System SleeP (all clocks stopped) * Execute the SLP instruction (CPU) Execute the SLP instruction when the entire system can be stopped. The CPU enters SLEEP mode and the OSC1 and OSC3 oscillation circuits stop. This also stops all peripheral circuits using clocks. Starting up the CPU from SLEEP mode is therefore limited to startup using a port (described later). System clock * Clock source selection (oscillation circuit) Select between OSC3 and OSC1 for the system clock source. Reduce current consumption by selecting the OSC1 clock when low-speed processing is possible. Control register: CLKCHG Default setting: CLKCHG = "0" (operated with the OSC1 clock) * OSC3 oscillator circuit stop (oscillation circuit) Operate the oscillation circuit comprising the system clock source. Where possible, stop the other oscillation circuit. You can reduce current consumption by using OSC1 as the system clock and stopping the OSC3 oscillation circuit. Control register: OSCC Default setting: OSCC = "0" (OSC3 oscillation off) CPu clock * Execute the HALT instruction (CPU) Execute the HALT instruction when program execution by the CPU is not required--for example, when only the display is required or for interrupt standby. The CPU enters HALT mode and suspends operations, but the peripheral circuits maintain the status in place at the time of the HALT instruction, enabling use of peripheral circuits for timers and interrupts. You can reduce power consumption even further by suspending unnecessary oscillation circuit and peripheral circuits before executing the HALT instruction. The CPU is started from HALT mode by an interrupt from a port or the peripheral circuit operating in HALT mode. Peripheral circuit clocks * Stop clock supply to the peripheral circuits (clock manager) The S1C6F016 incorporates a clock manager to control the clock supply to the peripheral circuits. Stop the clock supply to the unused peripheral circuits to reduce current consumption. The table below lists the peripheral circuits of which the operating clock can be stopped. Table D.1.1 Peripheral circuits with clock control Peripheral circuit/function Stop control Frequency selection Clock control register FOUT output Possible Possible FOUT[3:0] Key input interrupt noise rejector (P00 to P03) Possible Possible NRSP0[1:0] Key input interrupt noise rejector (P10 to P13) Possible Possible NRSP1[1:0] LCD system voltage regulator (booster clock) Possible - VCCKS[1:0] Serial interface Possible Possible SIFCKS[2:0] R/F converter Possible Possible RFCKS[2:0] Programmable timer 0 Possible Possible PTPS0[3:0] Programmable timer 1 Possible Possible PTPS1[3:0] Programmable timer 2 Possible Possible PTPS2[3:0] Programmable timer 3 Possible Possible PTPS3[3:0] Clock timer Possible - RTCKE Stopwatch timer Possible - SWCKE Sound generator Possible - SGCKE Integer multiplier Possible - MDCKE * Use low-speed clocks (clock manager) Reduce current consumption by setting the clock for the peripheral circuit that supports clock frequency selection as low as possible. AP-D-2 Seiko Epson Corporation S1C6F016 TECHNICAL MANUAL (Rev. 1.1) aPPenDiX D POWeR SaVinG Table D.1.2 shows a list of methods for clock control and starting/stopping the CPU. Table D.1.2 Clock control list Peripheral Peripheral CPU clock (OSC3) (OSC1) Current consumption OSC1 OSC3 Low Stop Stop Stop Stop Stop Stop Stop Stop Run Stop Stop Run Run Stop Run Run Run Stop Run Run Run Run Run Oscillation (system CLK) Oscillation (system CLK) Oscillation (system CLK) Oscillation High Oscillation Oscillation (system CLK) Oscillation (system CLK) CPU stop method Execute SLP instruction Execute HALT instruction Execute HALT instruction Execute HALT instruction CPU startup method 1 1, 2 1, 2, 3 1, 2, 3 HALT and SLEEP mode cancelation methods (CPU startup method) 1. Startup by a port Started up by a key input interrupt. 2. Startup by a peripheral circuit being operated with the OSC1 clock Started up by an interrupt from the clock timer, stopwatch timer, watchdog timer or a peripheral circuit being operated with an OSC1 dividing clock. 3. Startup by a peripheral circuit Started up by a peripheral circuit interrupt. D.2 Power Saving by Power Supply Control The available power supply controls are listed below. internal operating voltage regulator * Note that turning on internal operating voltage regulator heavy load protection will increase current consumption. Turn off heavy load protection for normal operations. Turn on only if operations are unstable. lCD system voltage regulator * Turning on the LCD system voltage regulator heavy load protection will increase current consumption. Turn off heavy load protection for normal operations. Turn on only if the display is unstable. * If no LCD display is being used, turn off the LCD system voltage regulator. Supply voltage detection (SVD) circuit * Operating the SVD circuit will increase current consumption. Turn off power supply voltage detection unless it is required. S1C6F016 Technical Manual (Rev. 1.1) Seiko Epson Corporation AP-D-3 aPPenDiX e S1C6F016 MaSK DaTa GeneRaTiOn PROCeDuRe Appendix E S1C6F016 Mask Data Generation Procedure This chapter shows a procedure to generate an S1C6F016 mask data file (PAx) for submission to Seiko Epson. Before the mask data file can be generated, get the latest device information definition file package from our website. There are four different device information definition files available according to the mask option types. Table E.1 Correspondence between mask option type and device information definition file Mask option type Device information definition file Custom mask option 6F016forCustom Standard mask option Type B 6F016forTYPEB Standard mask option Type E 6F016forTYPEE Standard mask option Type G 6F016forTYPEG Use the appropriate device information definition file according to the mask option type to be used. e.1 Mask Data Generation Flowchart (1) When custom mask option is selected Generate function option file (FDC) See Section E.2. Generate segment option See Section E.3. file (SDC) Performed by Seiko Epson ROM programming Not performed by Seiko Epson Select S1C6F016.HSA S1C6F016.LSA S1C6F016.CSA included in the package Generate ROM HEX data Generate mask data file (PAx) See Section E.4. Figure E.1.1 Mask data generation procedure when custom mask option is selected (2) When standard mask option (Type B, Type e, or Type G) is selected Select 6F016forTYPEx.FDC included in the package Generate segment option See Section E.3. file(SDC) Performed by Seiko Epson ROM programming Not performed by Seiko Epson Select S1C6F016.HSA S1C6F016.LSA S1C6F016.CSA included in the package Generate ROM HEX data Generate mask data file (PAx) See Section E.4. Figure E.1.2 Mask data generation procedure when standard mask option (Type B, Type E, or Type G) is selected S1C6F016 Technical Manual (Rev. 1.1) Seiko Epson Corporation AP-E-1 aPPenDiX e S1C6F016 MaSK DaTa GeneRaTiOn PROCeDuRe e.2 Function Option File Generation Procedure The following shows a function option file generation procedure. These operations are required only when custom mask option is selected. 1. Launch the function option generator (winfog.exe). 2. Load the device information definition file (INI). Select "Device INI select" from the "Tool (T)" menu or click the "Device INI select" button. When the dialog box appears, select the folder and file shown below. * Folder: 6F016forCustom*1 * File: S1c6f016C.INI*1 3. Set up information such as an output folder/file name. Select "Setup (S)" from the "Tool (T)" menu or click the "Setup" button. Enter the information required through the dialog box appeared. 4. Select options to be used. 5. Generate function option files (FDC, FSA). Select "Generate (G)" from the "Tool (T)" menu or click the "Generate" button. The function option files will be generated. e.3 Segment Option File Generation Procedure The following shows a segment option file generation procedure. 1. Launch the segment option generator (winsog.exe). 2. Load the device information definition file (INI). Select "Device INI select" from the "Tool (T)" menu or click the "Device INI select" button. When the dialog box appears, select the folder and file for the mask option type used. * Folder: 6F016forxxx*1 * File: S1c6f016xx.INI*1 3. Set up information such as an output folder/file name. Select "Setup (S)" from the "Tool (T)" menu or click the "Setup" button. Enter the information required through the dialog box appeared. 4. Load a segment assignment data file (SAD). Select "Record (R) Load (L)" from the "Tool (T)" menu or click the "Load" button. When the dialog box appears, select the folder and file for the mask option type used. * Folder: 6F016forxxx*1 * File: S1c6f016xx.SAD*1 The assignable area is displayed as shown in Figure E.3.1. The cells filled in with red indicate fixed area/output specifications that cannot be modified. AP-E-2 Seiko Epson Corporation S1C6F016 TECHNICAL MANUAL (Rev. 1.1) aPPenDiX e S1C6F016 MaSK DaTa GeneRaTiOn PROCeDuRe Assignable area Figure E.3.1 Assignable area 5. Segment assignment Assign an address/data bit to each cell within the assignable area. 6. Generate segment option files (SDC, SSA). Select "Generate (G)" from the "Tool (T)" menu or click the "Generate" button. The segment option files will be generated. e.4 Mask Data File Generation Procedure The following shows a mask data file generation procedure. 1. Launch the mask data checker (winmdc.exe). 2. Load the device information definition file (INI). Select "Device INI select" from the "Tool (T)" menu or click the "Device INI select" button. When the dialog box appears, select the folder and file for the mask option type used. * Folder: 6F016forxxx*1 * File: S1c6f016xx.INI*1 3. Select ROM data files and option document files. Select "Pack (P)" from the "Tool (T)" menu or click the "Pack" button on the toolbar. When the dialog box appears, select the code ROM HEX files (HSA, LSA), data ROM HEX file (CSA), function option document file (FDC), and segment option document file (SDC) to be packed. * Folder: 6F016forxxx*1 or a folder created by the user * File: xxxxxxxx.HSA*2 generated by the user xxxxxxxx.LSA*2 generated by the user xxxxxxxx.CSA*2 generated by the user xxxxxxxx.FDC generated by the user or 6F016forTYPEx.FDC*3 xxxxxxxx.SDC generated by the user 4. Generate a mask data file (PAx). Click the "Pack" button in the dialog box that appears in Step 3. The mask data file will be generated. S1C6F016 Technical Manual (Rev. 1.1) Seiko Epson Corporation AP-E-3 aPPenDiX e S1C6F016 MaSK DaTa GeneRaTiOn PROCeDuRe For details of the function option generator, segment option generator, and mask data checker, refer to the "S5U1C63000A Manual." *1 *2 *3 Included in the device information definition file package. When programming the ROM by Seiko Epson, use the last ROM HEX data generated by the user. If Seiko Epson does not program the ROM, use S1C6F016.HAS, S1C6F016.LSA, and S1C6F016.CSA included in the device information definition file package. Use the function option document file (FDC) generated by the user when custom mask option is selected. Use the function option document file (6F016forTYPEx.FDC) included in the device information definition file package when standard mask option (Type B, Type E, or Type G) is selected. AP-E-4 Seiko Epson Corporation S1C6F016 TECHNICAL MANUAL (Rev. 1.1) aPPenDiX F SuMMaRY OF nOTeS Appendix F Summary of Notes F.1 Summary of notes by Function Here, the cautionary notes are summed up by function category. Keep these notes well in mind when programming. Memory and stack * Memory is not implemented in unused areas within the memory map. Further, some non-implementation areas and unused (access prohibition) areas exist in the peripheral I/O area. If the program that accesses these areas is generated, its operation cannot be guaranteed. * Part of the RAM area is used as a stack area for subroutine call and register evacuation, so pay attention not to overlap the data area and stack area. * The S1C63000 core CPU handles the stack using the stack pointer for 4-bit data (SP2) and the stack pointer for 16-bit data (SP1). 16-bit data are accessed in stack handling by SP1, therefore, this stack area should be allocated to the area where 4-bit/16-bit access is possible (0100H to 01FFH). The stack pointers SP1 and SP2 change cyclically within their respective range: the range of SP1 is 0000H to 1FFFH and the range of SP2 is 0000H to 00FFH. Therefore, pay attention to the SP1 value because it may be set to 0200H or more exceeding the 4-bit/16-bit accessible range in the S1C6F016 or it may be set to 00FFH or less. Memory accesses except for stack operations by SP1 are 4-bit data access. After initial reset, all the interrupts including NMI are masked until both the stack pointers SP1 and SP2 are set by software. Further, if either SP1 or SP2 is re-set when both are set already, the interrupts including NMI are masked again until the other is re-set. Therefore, the settings of SP1 and SP2 must be done as a pair. Power control * Do not use the VD1 and VC1 to VC3 terminal output voltages to drive external circuits. * The LCD system voltage regulator takes about 100 msec for stabilizing the LCD drive voltages after writing "1" to LPWR. * Current consumption increases in heavy load protection mode, therefore do not set heavy load protection mode with software if unnecessary. interrupt * The interrupt factor flags are set when the interrupt condition is established, even if the interrupt mask registers are set to "0." * After an interrupt occurs, the same interrupt will occur again if the interrupt enabled state (I flag = "1") is set or the RETI instruction is executed unless the interrupt factor flag is reset. Therefore, be sure to reset (write "1" to) the interrupt factor flag in the interrupt service routine before shifting to the interrupt enabled state. * After an initial reset, all the interrupts including NMI are masked until both the stack pointers SP1 and SP2 are set with the software. Be sure to set the SP1 and SP2 in the initialize routine. Further, when re-setting the stack pointer, the SP1 and SP2 must be set as a pair. When one of them is set, all the interrupts including NMI are masked and interrupts cannot be accepted until the other one is set. * The interrupt handler routine must be located within the range from "Interrupt vector address (100H-10FH)" -7FH to +80H. If it is difficult, make a relay point within that range as the destination of the vector jump and branch the program to the interrupt handler from there. * Both the OSC1 and OSC3 oscillation circuits stop oscillating when the CPU enters SLEEP mode. To prevent the CPU from a malfunction when it resumes operating from SLEEP mode, switch the CPU clock to OSC1 before placing the CPU into SLEEP mode. S1C6F016 Technical Manual (Rev. 1.1) Seiko Epson Corporation AP-F-1 aPPenDiX F SuMMaRY OF nOTeS Oscillation circuit * When high speed CPU operations are not necessary, you should operate the peripheral circuits with the setting shown below. - CPU operating clock: OSC1 - OSC3 oscillation circuit: Off (When the OSC3 clock is not necessary for peripheral circuits.) - Clock manager: Disable the clock supply to unnecessary peripheral circuits. * Since several tens of sec to several tens of msec are necessary for the oscillation to stabilize after turning the OSC3 oscillation circuit on. Consequently, you should switch the CPU operating clock (OSC1 OSC3) after allowing for a sufficient waiting time once the OSC3 oscillation goes on. The oscillation start time will vary somewhat depending on the resonator and externally attached parts. Refer to the oscillation start time example indicated in the "Electrical Characteristics" chapter. * When switching the clock from OSC3 to OSC1, be sure to switch OSC3 oscillation off with separate instructions. Using a single instruction to process simultaneously can cause a malfunction of the CPU. * Both the OSC1 and OSC3 oscillation circuits stop oscillating when the CPU enters SLEEP mode. To prevent the CPU from a malfunction when it resumes operating from SLEEP mode, switch the CPU clock to OSC1 before placing the CPU into SLEEP mode. Watchdog timer * When the watchdog timer is being used, the software must reset it within 3-second cycles. * Because the watchdog timer is set in operation state by initial reset, set the watchdog timer to disabled state (not used) before generating an interrupt (NMI) if it is not used. Clock timer * Be sure to read timer data in the order of low-order data (TM[3:0]) then high-order data (TM[7:4]). * The clock timer count clock does not synch with the CPU clock. Therefore, the correct value may not be obtained depending on the count data read and count-up timings. To avoid this problem, the clock timer count data should be read by one of the procedures shown below. - Read the count data twice and verify if there is any difference between them. - Temporarily stop the clock timer when the counter data is read to obtain proper data. * When resetting the clock timer (TMRST = "1"), do not start the clock timer (TMRUN = "1") simultaneously. If both control bits are set to "1", the clock timer may not reset properly. Stopwatch timer * The interrupt factor flag should be reset after resetting the stopwatch timer. * Be sure to data reading in the order of SWD[3:0] SWD[7:4] SWD[11:8]. * When data that is held by a LAP input is read, read the capture buffer renewal flag CRNWF after reading the SWD[11:8] and check whether the data has been renewed or not. * When performing a processing such as a LAP input preceding with 1 Hz interrupt processing, read the LAP data carry-up request flag LCURF before processing and check whether carry-up is needed or not. Programmable timer * When reading counter data, be sure to read the low-order 4 bits (PTDx[3:0]) first. The high-order 4 bits (PTDx[7:4]) are latched when the low-order 4 bits are read and they are held until the next reading of the loworder 4 bits. In 16-bit timer mode, the high-order 12 bits are held by reading the low-order 4 bits, be sure to read the low-order 4 bits first. When the CPU is running with the OSC1 clock and the programmable timer is running with the OSC3 clock, stop the timer before reading the counter data to read the proper data. * The programmable timer actually enters RUN/STOP status in synchronization with the falling edge of the input clock after writing to the PTRUNx register. Consequently, when "0" is written to the PTRUNx register, the timer enters STOP status at the point where the counter is decremented (-1). The PTRUNx register maintains "1" for reading until the timer actually stops. AP-F-2 Seiko Epson Corporation S1C6F016 TECHNICAL MANUAL (Rev. 1.1) aPPenDiX F SuMMaRY OF nOTeS Count clock PTRUNx (RD) PTRUNx (WR) PTDx[7:0] "1" (RUN) writing 42H "0" (STOP) writing 41H 40H 3FH 3EH 3DH Figure F.1.1 Timing chart for RUN/STOP control (timer mode) In event counter mode, the timer starts counting at the first event clock. Count clock PTRUNx (RD) PTRUNx (WR) PTDx[7:0] "1" (RUN) writing "0" (STOP) writing 42H 41H 40H 3FH 3EH 3DH Figure F.1.2 Timing chart for RUN/STOP control (event counter mode) * Since the TOUT_A and TOUT_B signals are generated asynchronously from the PTOUT_A and PTOUT_B registers, a hazard within 1/2 cycle is generated when the signal is turned on and off by setting the register. * When the OSC3 oscillation clock is selected for the clock source, it is necessary to turn the OSC3 oscillation on, prior to using the programmable timer. However the OSC3 oscillation circuit requires several tens of sec to several tens of msec after turning the circuit on until the oscillation stabilizes. Therefore, allow an adequate interval from turning the OSC3 oscillation circuit on to starting the programmable timer. Refer to the "Oscillation Circuit and Clock Control" chapter, for the control and notes of the OSC3 oscillation circuit. At initial reset, the OSC3 oscillation circuit is set in off state. * For the reason below, pay attention to the reload data write timing when changing the interval of the programmable timer interrupts while the programmable timer is running. The programmable timer counts down at the falling edge of the input clock and at the same time it generates an interrupt if the counter underflows. Then it starts loading the reload data to the counter and the counter data is determined at the next rising edge of the input clock (period shown in as in the figure). Count clock Counter data 03H 02H 01H 00H (continuous mode) Underflow (interrupt is generated) 25H 24H (Reload data = 25H) Counter data is determined by reloading. Figure F.1.3 Reload timing for programmable timer To avoid improper reloading, do not rewrite the reload data after an interrupt occurs until the counter data is determined including the reloading period . Be especially careful when using the OSC1 (low-speed clock) as the clock source of the programmable timer and the CPU is operating with the OSC3 (high-speed clock). * The programmable timer count clock does not synch with the CPU clock. Therefore, the correct value may not be obtained depending on the count data read and count-up timings. To avoid this problem, the programmable timer count data should be read by one of the procedures shown below. - Read the count data twice and verify if there is any difference between them. - Temporarily stop the programmable timer when the counter data is read to obtain proper data. i/O port * When an I/O ports in input mode is changed from high to low by the pull-down resistor, the fall of the waveform is delayed on account of the time constant of the pull-down resistor and input gate capacitance. Hence, when fetching input data, set an appropriate wait time. Particular care needs to be taken of the key scan during key matrix configuration. Make this waiting time the amount of time or more calculated by the following expression. S1C6F016 Technical Manual (Rev. 1.1) Seiko Epson Corporation AP-F-3 aPPenDiX F SuMMaRY OF nOTeS 10 x C x R C: terminal capacitance 15 pF + parasitic capacitance ? pF R: pull-down resistance 500 kW (Max.) * Be sure to turn the noise rejector off before executing the SLP instruction. * Reactivating from SLEEP status can only be done by generation of a key input interrupt factor. Therefore when using the SLEEP function, it is necessary to set the interrupt select register (SIPxx = "1") of the port to be used for releasing SLEEP status before executing the SLP instruction. Furthermore, enable the key input interrupt using the corresponding interrupt mask register (EIKxx = "1") before executing the SLP instruction to run key input interrupt handler routine after SLEEP status is released. * Before the port function is configured, the circuit that uses the port (e.g. input interrupt, multiple key entry reset, serial interface, R/F converter, event counter input, direct RUN/LAP input for stopwatch) must be disabled. Serial interface * Perform data writing/reading to the data registers SD[7:0] only while the serial interface is not running (i.e., the synchronous clock is neither being input or output). * As a trigger condition, it is required that data writing or reading on data registers SD[7:0] be performed prior to writing "1" to SCTRG. (The internal circuit of the serial interface is initiated through data writing/reading on data registers SD[7:0].) In addition, be sure to enable the serial interface with the ESIF register before setting the trigger. Supply trigger only once every time the serial interface is placed in the RUN state. Refrain from performing trigger input multiple times, as leads to malfunctioning. Moreover, when the synchronous clock SCLK is external clock, start to input the external clock after the trigger. * Setting of the input/output permutation (MSB first/LSB first) with the SDP register should be done before setting data to SD[7:0]. * Be aware that the maximum clock frequency for the serial interface is limited to 1 MHz when the programmable timer is used as the clock source or the serial interface is used in slave mode. lCD driver * Be sure to turn the display off (LPWR = "0") before switching the frame frequency. * The frame frequency affects the display quality. We recommend that the frame frequency should be determined after the display quality is evaluated using the actual LCD panel. * At initial reset, the contents of display memory are undefined and LC[3:0] (LCD contrast) is set to "0," therefore, it is necessary to initialize those contents by software. Also note that the LPWR and DSPC[1:0] registers are set to turn the display off. * When Pxx (P20 to P53) and R/F converter terminals are used as the segment terminals by selecting mask option, do not alter the Pxx port and R/F converter control registers that affect these terminals from their initial values. Sound generator * Since it generates a buzzer signal that is out of synchronization with the BZE register, hazards may at times be produced when the signal goes on/off due to the setting of the BZE register. * The one-shot output is only valid when the normal buzzer output is off (BZE = "0") and will be invalid when the normal buzzer output is on (BZE = "1"). integer multiplier An operation process takes 10 CPU clock cycles (5 bus cycles) after writing to the calculation mode select register CALMD until the operation result is set to the destination register DRH/DRL and the operation flags. While this operation is in process, do not read/write from/to the destination register DRH/DRL and do not read NF/VF/ZF. AP-F-4 Seiko Epson Corporation S1C6F016 TECHNICAL MANUAL (Rev. 1.1) aPPenDiX F SuMMaRY OF nOTeS R/F converter * When an error interrupt occurs, reset the overflow flag (OVMC or OVTC) by writing "1." The same error interrupt will occur again if the overflow flag is not reset. * When setting the measurement counter or time base counter, always write 5 words of data continuously in order from the lower address (FF62H FF63H FF64H FF65H FF66H, FF67H FF68H FF69H FF6AH FF6BH). Furthermore, an LD instruction should be used for writing data to the measurement counter and a read-modify-write instruction (AND, OR, ADD, SUB, etc.) cannot be used. If data other than low-order 4 bits is written, the counter cannot be set to the desired value. * The R/F converter reference and sensor oscillation frequencies should be determined after an adequate evaluation, since low voltage, 2 V or lower in particular, increases the voltage deviation. Also the voltage deviation depends on the environment including board, resistance, and capacitance (see RFC characteristic curves in the "Electrical Characteristics" chapter). SVD circuit * To obtain a stable detection result, the SVD circuit must be on for at least 500 sec. So, to obtain the SVD detection result, follow the programming sequence below. 1. Set SVDON to "1" 2. Maintain for 500 sec minimum 3. Set SVDON to "0" 4. Read SVDDT * The SVD circuit should normally be turned off because SVD operation increase current consumption. Flash eePROM * Be sure to leave the DMOD, DTXD, DRXD and DCLK terminals open during normal operation. Particularly, make sure that the DMOD terminal is not pulled up to high from outside the IC, although the terminal is pulled down with an internal resistor. * The OSC1 oscillation circuit must be configured to enable oscillation when programming the Flash EEPROM using the On Board Writer. F.2 Precautions on Mounting Oscillation circuit * Oscillation characteristics change depending on conditions (board pattern, components used, etc.). In particular, when a ceramic oscillator or crystal oscillator is used, use the oscillator manufacturer's recommended values for constants such as capacitance and resistance. * Disturbances of the oscillation clock due to noise may cause a malfunction. Consider the following points to prevent this: Sample VSS pattern (OSC3) (1) Components which are connected to the OSC1, OSC2, OSC3 and OSC4 terminals, such as oscillators, resistors and capacitors, should be connected in the shortest line. (2) As shown in the right hand figure, make a VSS pattern as large as possible at circumscription of the OSC1, OSC2, OSC3 and OSC4 terminals and the components connected to these terminals. Furthermore, do not use this VSS pattern for any purpose other than the oscillation system. OSC4 OSC3 VSS * In order to prevent unstable operation of the oscillation circuit due to current leak between OSC1/OSC3 and VDD, please keep enough distance between OSC1/OSC3 and VDD or other signals on the board pattern. S1C6F016 Technical Manual (Rev. 1.1) Seiko Epson Corporation AP-F-5 aPPenDiX F SuMMaRY OF nOTeS Reset circuit * The power-on reset signal which is input to the RESET terminal changes depending on conditions (power rise time, components used, board pattern, etc.). Decide the time constant of the capacitor and resistor after enough tests have been completed with the application product. When using the built-in pull-down resistor of the RESET terminal, take into consideration dispersion of the resistance for setting the constant. * In order to prevent any occurrences of unnecessary resetting caused by noise during operating, components such as capacitors and resistors should be connected to the RESET terminal in the shortest line. Power supply circuit * Sudden power supply variation due to noise may cause malfunction. Consider the following points to prevent this: (1) The power supply should be connected to the VDD and VSS terminals with patterns as short and large as possible. (2) When connecting between the VDD and VSS terminals with a bypass capacitor, the terminals should be connected as short as possible. Bypass capacitor connection example VDD VDD VSS VSS (3) Components which are connected to the VD1 and VC1-VC3 terminals, such as capacitors, should be connected in the shortest line. In particular, the VC1-VC3 voltages affect the display quality. * Do not connect anything to the VC1-VC3 terminals when the LCD driver is not used. arrangement of signal lines * When a signal line is parallel with a high-speed line in long distance or intersects a high-speed line, noise may generated by mutual interference between the signals and it may cause a malfunction. Do not arrange a high-speed signal line especially near circuits that are sensitive to noise such as the oscillation unit and analog input unit. Output terminals * When an output terminal is used to drive an external component that consumes a large amount of current, the operation of the external component affects the built-in power supply circuit of this IC and the output voltage may vary. When driving a bipolar transistor by a periodic signal such as the BZ or timer output in particular, it may cause variations in the voltage output from the LCD system voltage circuit that affects the contrast of the LCD display. To prevent this, separate the traces on the printed circuit board. Put one between the power supply and the IC's VDD and VSS terminals, and another between the power supply and the external component that consumes the large amount of current. Furthermore, use an external component with as low a current consumption as possible. AP-F-6 Seiko Epson Corporation Prohibited pattern example OSC4 OSC3 VSS Large current signal line High-speed signal line Example: Buzzer output circuit VDD + BZ * In order to prevent generation of electromagnetic induction noise caused by mutual inductance, do not arrange a large current signal line near the circuits that are sensitive to noise such as the oscillation unit and analog input unit. VSS CP Piezo S1C6F016 TECHNICAL MANUAL (Rev. 1.1) aPPenDiX F SuMMaRY OF nOTeS Precautions for Visible Radiation (when bare chip is mounted) * Visible radiation causes semiconductor devices to change electrical characteristics. It may cause the IC to malfunction or the nonvolatile memory data to be erased. When developing products, consider the following precautions to prevent malfunctions caused by visible radiation. (1) Design the product and bond the IC on the board so that it is shielded from visible radiation in actual use. (2) The inspection process of the product needs an environment that shields the IC from visible radiation. (3) Shield not only the face of the IC but the back and side as well. (4) After the shielded package has been opened, the IC chip should be bonded on the board within one week. If the IC chip must be stored after the package has been opened, be sure to shield the IC from visible radiation. (5) If there is a possibility that heat stress exceeding the reflow soldering condition is applied to the IC in the bonding process, perform enough evaluation of data stored in the nonvolatile memory before the product is shipped. S1C6F016 Technical Manual (Rev. 1.1) Seiko Epson Corporation AP-F-7 ReViSiOn hiSTORY Revision history Code no. 411801400 411801401a Page All 1-1 1-3 1-4 1-4 to 6 1-9 1-10 2-5 Contents New establishment 1 Outline (Old) The S1C6F016 allows choice from six different models by mask-option selections and shipment form selections as shown in Table 1.1. (New) The S1C6F016 allows choice from eight different models by mask-option selections and shipment form selections as shown in Table 1.1. Modified Table 1.1. (Added Type G.) 1.1 Features (Old) Instruction execution time ... During operation at 4 MHz: 0.5 sec 1 sec 1.3 sec (New) Instruction execution time ... During operation at 4 MHz: 0.5 sec 1 sec 1.5 sec 1.3 Mask Option (Old) S1C6F016 provides two standard mask option models (Type B and Type E) and a custom mask option model that allows selection of each optional specification. (See Table 1.1.) ... Mask pattern of the IC is finally generated based on the data created by winfog and winsog. Refer to the "S5U1C63000A Manual" for these tools. (New) S1C6F016 provides three standard mask option models (Type B, Type E, and Type G) and a custom mask option model that allows selection of each optional specification. (See Table 1.1 and Tables 1.3.1-1.3.5.) ... Mask pattern of the IC is finally generated based on the data created by winfog and winsog. (The mask pattern for the segment option will be generated using only the segment output specification (S) in the custom mask option data created by winsog. The segment allocation data must be programmed.) Refer to the "S5U1C63000A Manual" for winfog and winsog. 1.3 Mask Option (2) OSC3 oscillation circuit (Old) ... The standard mask option Type B model is configured with a ceramic oscillation circuit and Type E model is configured with a CR oscillation circuit (external R). (New) ... The standard mask option Type B model is configured with a ceramic oscillation circuit. The Type E and Type G models are configured with a CR oscillation circuit (external R). 1.3 Mask Option (4) SEG/GPIO/RFC selector (Old) ... The standard mask option Type B model is configured for the I/O port or R/F converter pins. (New) ... The standard mask option Type B and Type G models are configured for the I/O port or R/F converter pins. 1.3 Mask Option (5) I/O port pull-down resistor (Old) ... The standard mask option models have built-in pull-down resistors for all I/O ports. (New) ... The standard mask option Type B and Type E models have built-in pull-down resistors for all I/O ports. The standard mask option Type G model has no built-in pull-down resistors for P10 and P11 and all other I/O ports include a pull-down resistor. 1.3 Mask Option (10) LCD segment specification (Old) The display memory bits can be allocated to a desired SEG terminal. It is also possible to set SEG terminals for DC output. (New) The LCD segment specification of the custom mask option model and standard mask option Type B and Type E models is fixed at LCD segment output (S). The LCD segment specification of the standard mask option Type G model is fixed at DC complementary output (C). 1.3 Mask Option Modified Table 1.3.1. (Old) - (New) Added Type G. 1.3 Mask Option Modified Table 1.3.4. (Old) - (New) Replaced with Table 1.3.4 Segment option (standard mask option Type G). 1.3 Mask Option Added Table 1.3.5. (Old) - (New) Table 1.3.5 Segment option (custom mask option), Modified earlier Table 1.3.4. 2.2 Pin Description (Old) Note: The test terminals must be connected to the power supply or left open as shown below. ... TEST3: Leave open. (New) Notes: * The test terminals must be connected to the power supply or left open as shown below. Be sure to avoid applying other conditions to the terminals during normal operation. ... TEST3: Leave open. * Be sure to leave the DMOD, DTXD, DRXD and DCLK terminals open during normal operation. Particularly, make sure that the DMOD terminal is not pulled up to high from outside the IC, although the terminal is pulled down with an internal resistor. ReViSiOn hiSTORY Code no. 411801401a Page 3-1 3-3 4-1 5-3 6-2 7-1 7-2 7-4 12-1 12-2 Contents 3.2.2 Flash EEPROM Specifications (Old) - (New) Notes: * Be sure to leave the DMOD, DTXD, DRXD and DCLK terminals open during normal operation. Particularly, make sure that the DMOD terminal is not pulled up to high from outside the IC, although the terminal is pulled down with an internal resistor. * The OSC1 oscillation circuit must be configured to enable oscillation when programming the Flash EEPROM using the On Board Writer. 3.3.3 Display Memory (Old) ... Each bit can be assigned to the specific segment terminal (SEG0-SEG55) by mask option. (New) ... Each bit can be assigned to the specific segment terminal (SEG0-SEG55) by programming the Flash EEPROM with the segment assignment data created using the segment option generator "winsog." 4.2 Reset Terminal (RESET) (Old) Therefore in normal operation, a maximum of 1,024/fOSC1 seconds (32 msec when fOSC1 = 32.768 kHz) is needed until the internal initial reset is released after the reset terminal goes to low level. Be sure to maintain a reset input of 0.1 msec or more. (New) Therefore in normal operation, a maximum of 1,024/fOSC1 seconds (32 msec when fOSC1 = 32.768 kHz) is needed until the internal initial reset is released after the reset terminal goes to low level. After the internal initial reset is released, the hardware executes an initial processing that takes 21,515/fOSC1 seconds (657 msec when fOSC1 = 32.768 kHz) before the CPU starts operating. Be sure to maintain a reset input of 0.1 msec or more. 5.5 I/O Memory for Power Supply Circuit (Old) VCREF: VC regulator reference voltage select register (FF02H*D2) (New) VCREF: VC regulator reference voltage select register (FF03H*D1) 6.1 Configuration of Interrupt Controller Modified Figure 6.1.1. (Old) ISW0, EISW0 (New) ISW10, EISW10 7.1.2 Mask Option (Old) Standard mask option Type E (New) Standard mask option Type E and Type G 7.1.4 OSC3 Oscillation Circuit (Old) Standard mask option Type E: CR (external R) (fixed) (New) Standard mask option Type E and Type G: CR (external R) (fixed) 7.3 HALT and SLEEP SLEEP mode (Old) ... Therefore, set the following flag and the registers for the I/O port to be used to cancel SLEEP status before executing the SLP instruction. * Interrupt flag (I flag) = "1" (interrupts are enabled) * Interrupt select register SIPxx = "1" (the Pxx I/O port interrupt is selected) * Interrupt mask register EIKxx = "1" (the Pxx I/O port interrupt is enabled) * Noise rejector select register NRSPxx = "00" (noise rejector is bypassed) (New) ... To ensure that the system enters and cancels SLEEP mode properly, follow the procedure shown below to configure/confirm the CPU clock, interrupt flag, the P0x (P1x) I/O port used to cancel SLEEP mode, and the port input level. 1. Set the CPU system clock switching register CLKCHG to "0." (The OSC1 clock is selected.) 2. Set the interrupt select register SIPxx to "1." (The P0x (P1x) I/O port interrupt is selected.) 3. Set the interrupt mask register EIKxx to "1." (The P0x (P1x) I/O port interrupt is enabled.) 4. Set the key input interrupt noise reject frequency select register NRSPxx to "00." (The noise rejector is bypassed.) 5. Write "1" to the interrupt factor flag IKxx. (The P0x (P1x) interrupt factor flag is reset.) 6. Set the interrupt flag (I flag) to "1." (Interrupts are enabled.) 7a. Make sure the P0x (P1x) port input level is high when P0x (P1x) port interrupt polarity select register PCPxx = "1" (generates an interrupt request at the falling edge). 7b. Make sure the P0x (P1x) port input level is low when P0x (P1x) port interrupt polarity select register PCPxx = "0" (generates an interrupt request at the rising edge). 8. Execute the SLP instruction. 12.1 Configuration of I/O Ports (Old) (The standard mask option model comes with pull-down resistors.) (New) (The standard mask option models come with or without pull-down resistors.) 12.2 Mask Option Custom mask option (Old) - (New) The I/O ports P20-P53 input/output terminals are shared with the SEG terminals. This mask option allows selection of whether each of these terminals is used for the I/O port or the SEG output. Refer to "Mask Option" in the "LCD Driver" chapter for details. ReViSiOn hiSTORY Code no. 411801401a Page 12-3 12-4 12-5 12-7 12-10 13-2 13-6 14-1 14-2 Contents 12.2 Mask Option (Old) - (New) Standard mask option Type G The output specification for output mode is fixed at complementary output. The internal pull-down resistor is connected to the I/O ports except for P10 and P11. 12.6 Key Input Interrupt Function Corrected Figure 12.6.1 (SLEEP cancellation path). 12.6 Key Input Interrupt Function (Old) When the interrupt mask register (EIKxx) is set to "0," the interrupt request is masked and no interrupt is generated to the CPU. However, SLEEP mode can be canceled regardless of the interrupt mask register setting. (New) When the interrupt mask register (EIKxx) is set to "0," the interrupt request is masked and no interrupt is generated to the CPU. 12.7 I/O memory of I/O ports Px[3:0]: Px I/O port data register (FFxxH) (Old) 10 x C x R C: terminal capacitance 5 pF + parasitic capacitance ? pF R: pull-down resistance 375 k (Max.) (New) 10 x C x R C: terminal capacitance 15 pF + parasitic capacitance ? pF R: pull-down resistance 500 k (Max.) 12.8 Precautions (Old) 10 x C x R C: terminal capacitance 5 pF + parasitic capacitance ? pF R: pull-down resistance 375 k (Max.) (New) 10 x C x R C: terminal capacitance 15 pF + parasitic capacitance ? pF R: pull-down resistance 500 k (Max.) 13.3 Mask Option (Old) Standard mask option (Type B and Type E) The output specification of the I/O port is fixed as a complementary output. All the I/O port terminals have a built-in pull-down resistor. (New) Standard mask option Type B, Type E, and Type G The output specification of the P30-P33 I/O ports is fixed at a complementary output. The P30-P33 I/O port terminals have a built-in pull-down resistor 13.6.4 SRDY Signal * When negative polarity (SCPS1 = "1") is selected for the synchronous clock: (Old) ... The SRDY signal changes from "1" to "0" immediately after "1" is written to SCTRG and returns from "0" to "1" when "0" is input to the SRDY (P30) terminal (i.e., when the serial input/output begins transmitting or receiving data). (New) ... The SRDY signal changes from "1" to "0" immediately after "1" is written to SCTRG and returns from "0" to "1" when "0" is input to the SCLK (P30) terminal (i.e., when the serial input/output begins transmitting or receiving data). 14.2.1 SEG/GPIO/RFC Terminal Configuration (Old) Custom mask option The SEG0 to SEG35 terminals are fixed at segment/DC outputs. ... Standard mask option Type B The SEG0 to SEG35 terminals can only be used for segment/DC outputs. ... Standard mask option Type E ... The SEG0 to SEG35 terminals can also be used for DC outputs. (New) Custom mask option The SEG0 to SEG35 terminals are fixed at segment output. ... Standard mask option Type B The SEG0 to SEG35 terminals can only be used for segment outputs. ... The SEG0 to SEG35 terminals cannot be used for DC outputs. Standard mask option Type E ... The SEG0 to SEG55 terminals cannot be used for DC outputs. Standard mask option Type G The SEG0 to SEG35 terminals can only be used for DC outputs. The SEG36 to SEG55 terminals are not available, as they are all configured to the I/O port and R/F converter terminals. The SEG0 to SEG35 terminals cannot be used for segment outputs. 14.2.2 for LCD Driving (Old) - (New) Standard mask option Type G The power source is set to the internal LCD system voltage regulator, but it is not used, as Type G supports DC output only. ReViSiOn hiSTORY Code no. 411801401a Page 14-2 to 3 Contents 14.2.3 Segment Option (Old) Segment option is available for both custom mask option and standard mask option models. Segment allocation The display memory addresses (F000H-F07FH) and the data bits (D0-D3) can be allocated to a segment terminal (SEG0-SEG55) individually. This makes design easy by increasing the degree of freedom with which the LCD panel can be designed. Figure 14.2.3.1 shows an example of the relationship between the LCD segments (on the panel) and the display memory for the case of 1/4 duty. (Figure) Figure 14.2.3.1 Segment allocation Output specification Each of SEG0-SEG35 terminals can be configured for either segment signal output or DC output (VDD and VSS binary output) by mask option. When DC output is selected, either complementary output or N-channel open drain output can be selected as the output specification for each terminal pair. When DC output is selected, the data corresponding to COM0 of each segment terminal is output. DC output can be performed even if the LCD system voltage regulator is off (LPWR = "0"). The SEG36-SEG55 terminals can be used only for segment signal output. DC output cannot be selected. (New) Output specification Custom mask option The SEG0-SEG55 terminals can be used only for segment signal output. DC output cannot be selected. Standard mask option Type B The SEG0-SEG35 terminals can be used only for segment signal output. DC output cannot be selected. Standard mask option Type E The SEG0-SEG55 terminals can be used only for segment signal output. DC output cannot be selected. Standard mask option Type G The SEG0-SEG35 terminals can be used only for DC output (VDD and VSS binary output). Segment output cannot be selected. The output specification is fixed at complementary output. Each segment terminal outputs COM0 data. Segment allocation Note: Segment allocation is not a mask option item. Create segment allocation data that represents corresponding between display memory bits and segment terminals) using the segment option generator "winsog" and program the Flash EEPROM with the created data. Custom mask option, standard mask option Type B and Type E Each data bits (D0-D3) of the display memory addresses (F000H-F07FH) can be allocated to a segment terminal (SEG0-SEG55) individually. This makes design easy by increasing the degree of freedom with which the LCD panel can be designed. Figure .2.3.1 shows an example of the relationship between the LCD segments (on the panel) and the display memory for the case of 1/4 duty. (Corrected the figure.) Figure 14.2.3.1 Segment allocation 14-6 14-7 14-16 16-1 Standard mask option Type G Each data bits (D0-D3) of the display memory addresses (F000H-F07FH) can be allocated to a segment terminal (SEG0-SEG35) individually. The terminals output the contents of the address/bit corresponding to COM0, so it is not necessary to allocate addresses/bits to COM1-COM7. 14.2.3 Segment Option Modified Table 14.2.3.3. (Old) - (New) Replaced with Table 14.2.3.3 Segment option (standard mask option Type G). 14.2.3 Segment Option Added Table 14.2.3.4. (Old) - (New) Table 14.2.3.4 Segment option (custom mask option), Modified earlier Table 14.2.3.3. 14.4 Display Memory (Old) The display memory is located to F000H-F07FH in the data memory area and each data bit can be allocated to an segment terminal (SEG0-SEG55) by mask option. (New) The display memory is located to F000H-F07FH in the data memory area and each data bit can be allocated to an segment terminal (SEG0-SEG55) by programming the Flash EEPROM with the segment assignment data created using the segment option generator "winsog." 16.2 Controlling Clock Manager Corrected Table 16.2.1. (Old) SGCKE (New) MDCKE ReViSiOn hiSTORY Code no. 411801401a Page 17-11 Contents 17.8 Precautions (Old) - (New) * The R/F converter reference and sensor oscillation frequencies should be determined after an adequate evaluation, since low voltage, 2 V or lower in particular, increases the voltage deviation. Also the voltage deviation depends on the environment including board, resistance, and capacitance (see RFC characteristic curves in the "Electrical Characteristics" chapter). 18.3 I/O Memory of SVD Circuit 18-2 Corrected the register table (FF05H, D1, R/W). (Old) R/W (New) R 20-1 to 2 20 Basic External Wiring Diagram Recommended values for external parts (Old) (CG1) 5 pF to 25 pF (CG3) 15 pF (Crystal oscillation), 30 pF (Ceramic oscillation) (CD3) 15 pF (Crystal oscillation), 30 pF (Ceramic oscillation) (New) (CG1) 0 pF to 25 pF (CG3) 30 pF (Ceramic oscillation) (CD3) 30 pF (Ceramic oscillation) 20-3 20 Basic External Wiring Diagram (Old) - (New) Added Standard mask option Type G Appendix A List of I/O Registers AP-A-1 Corrected the register table (FF05H, D1, R/W). (Old) R/W (New) R C.2.3 Serial Programming Procedure AP-C-3 (4) Installing the USB-Serial conversion driver (Required only when the USB-Serial On Board Writer is used) (Old) The USB-Serial conversion driver was copied in the "\EPSON\S1C63\writer\driver" folder when the S1C63 Family Assembler Package 2 (S5U1C63000A2) was installed. Specify this folder as the driver location. (New) The USB-Serial conversion driver was copied into the folders shown below when the S1C63 Family Assembler Package 2 (S5U1C63000A2) was installed. Specify a folder according to the serial number of the USB-Serial On Board Writer as the driver location. Table C.2.3.1 USB-Serial conversion driver storing folder (Added the table.) AP-E-1 to 4 Appendix E S1C6F016 Mask Data Generation Procedure Added chapter. AP-F-1 to 7 Appendix F Summary of Notes (Old) Appendix E (New) Appendix F E.1 Summary of Notes by Function AP-F-4 I/O port (Old) 10 x C x R C: terminal capacitance 5 pF + parasitic capacitance ? pF R: pull-down resistance 375 k (Max.) (New) 10 x C x R C: terminal capacitance 15 pF + parasitic capacitance ? pF R: pull-down resistance 500 k (Max.) E.1 Summary of Notes by Function AP-F-5 R/F converter (Old) - (New) * The R/F converter reference and sensor oscillation frequencies should be determined after an adequate evaluation, since low voltage, 2 V or lower in particular, increases the voltage deviation. Also the voltage deviation depends on the environment including board, resistance, and capacitance (see RFC characteristic curves in the "Electrical Characteristics" chapter). E.1 Summary of Notes by Function Flash EEPROM (Old) * Be sure to leave the DMOD, DTXD, DRXD and DCLK terminals open during normal operation. Particularly, make sure that the DMOD pin is not pulled down to low from outside the IC, although the pin is pulled up with the internal resistor. * The OSC1 and OSC3 oscillation circuits must be configured to enable oscillation when programming the Flash EEPROM using the On Board Writer. (New) * Be sure to leave the DMOD, DTXD, DRXD and DCLK terminals open during normal operation. Particularly, make sure that the DMOD terminal is not pulled up to high from outside the IC, although the terminal is pulled down with an internal resistor. * The OSC1 oscillation circuit must be configured to enable oscillation when programming the Flash EEPROM using the On Board Writer. International Sales Operations AMERICA ASIA EPSON ELECTRONICS AMERICA, INC. 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