NOTE: For detailed information on purchasing options, contact your
local Allegro field applications engineer or sales representative.
Allegro MicroSystems, Inc. reserves the right to make, from time to time, revisions to the anticipated product life cycle plan
for a product to accommodate changes in production capabilities, alternative product availabilities, or market demand. The
information included herein is believed to be accurate and reliable. However, Allegro MicroSystems, Inc. assumes no respon-
sibility for its use; nor for any infringements of patents or other rights of third parties which may result from its use.
Recommended Substitutions:
For existing customer transition, and for new customers or new appli-
cations, refer to the A6279.
8-Bit Serial Input Constant-Current Latched LED Driver
A6275
Date of status change: November 1, 2010
Deadline for receipt of LAST TIME BUY orders: April 30, 2011
This part is in production but has been determined to be
LAST TIME BUY. This classification indicates that the product is
obsolete and notice has been given. Sale of this device is currently
restricted to existing customer applications. The device should not be
purchased for new design applications because of obsolescence in the
near future. Samples are no longer available.
Last Time Buy
Description
The A6275 is specifically designed for LED display applications.
Each BiCMOS device includes an 8-bit CMOS shift register,
accompanying data latches, and eight NPN constant-current
sink drivers.
The CMOS shift register and latches allow direct interfacing
with microprocessor-based systems. With a 5 V logic supply,
typical serial data-input rates are up to 20 MHz. The LED drive
current is de ter mined by the user selection of a single resistor.
A CMOS serial data output permits cascade connections in
applications requiring additional drive lines. For inter-digit
blanking, all output drivers can be disabled with an ENABLE
input high. A similar 150 mA output device is available as the
A6277; a similar 16-bit device is available as the A6276.
Two package styles are provided: a through-hole DIP (suffix
A) and a surface-mount SOICW (suffix LW). Under normal
applications, copper leadframes and low logic-power dissipation
allow these devices to sink maximum rated current through
all outputs continuously over the operating temperature range
(90 mA, 0.9 V drop, 85°C). Both packages are lead (Pb) free,
with 100% matte tin leadframe plating.
26185.200F
Features and Benefits
▪ Up to 90 mA constant-current outputs
▪ Undervoltage lockout
▪ Low-power CMOS logic and latches
▪ High data-input rate
▪ Pin-compatible with TB62705CP
8-Bit Serial Input Constant-Current Latched LED Driver
Packages
Functional Block Diagram
Not to scale
A6275
16-pin DIP
(A package)
16-pin SOICW
(LW package)
MOS
BIPOLAR
GROUND
LATCH
ENABLE
OUTPUT ENABLE
(ACTIVE LOW)
SERIAL
DATA OUT
CLOCK
SERIAL
DATA IN SERIAL-PARALLEL SHIFT REGISTER
LATCHES
V
DD
LOGIC
SUPPLY
R
EXT
OUT
0
OUT
1
Dwg. FP-013-3
OUT
2
OUT
N
I
REGULATOR
O
UVLO
Serial-Input Constant-Current Latched LED Driver
with Open LED Detection and Dot Correction
A6275
2
Allegro MicroSystems, Inc.
115 Northeast Cutoff
Worcester, Massachusetts 01615-0036 U.S.A.
1.508.853.5000; www.allegromicro.com
Selection Guide
Part Number Package Packing Ambient Temperature
(°C)
A6275EA-T 16-pin DIP 25 per tube –40 to 85
A6275ELWTR-T 16-pin SOICW 1000 per reel
A6275SLWTR-T 16-pin SOICW 1000 per reel –20 to 85
Absolute Maximum Ratings*
Characteristic Symbol Notes Rating Units
Supply Voltage VDD 7.0 V
Input Voltage Range VI–0.4 to VDD + 0.4 V
Output Voltage Range VO–0.5 to VDD + 17 V
Output Current IO90 mA
Ground Current IGND 750 mA
Operating Ambient Temperature TA
Range E –40 to 85 ºC
Range S –20 to 85 ºC
Maximum Junction Temperature TJ(max) 150 ºC
Storage Temperature Tstg –55 to 150 ºC
*These CMOS devices have input static protection (Class 2) but are still sus cep ti ble to damage if exposed to extremely high static
electrical charges.
Thermal Characteristics may require derating at maximum conditions, see application information
Characteristic Symbol Test Conditions* Value Units
Package Thermal Resistance RθJA
Package A, 4-layer PCB based on JEDEC standard 38 ºC/W
Package LW, 4-layer PCB based on JEDEC standard 48 ºC/W
*Additional thermal information available on the Allegro website.
25 50 75 100 125 150
Temperature (°C)
Power Dissipation, P
D
(mW)
3500
3250
3000
2750
2500
2250
2000
1750
1500
1250
1000
750
500
250
0
Power Dissipation versus Ambient Temperature
(RQJA = 38 ºC/W)
Package A
(R
QJA
= 48 ºC/W)
Package LW
Serial-Input Constant-Current Latched LED Driver
with Open LED Detection and Dot Correction
A6275
3
Allegro MicroSystems, Inc.
115 Northeast Cutoff
Worcester, Massachusetts 01615-0036 U.S.A.
1.508.853.5000; www.allegromicro.com
TUO ATAD LAIRESNI ATAD LAIRES dna KCOLC
LATCH ENABLEOUTPUT ENABLE (active low)
Dwg. EP-010-11
IN
VDD
Dwg. EP-010-12
IN
VDD
Dwg. EP-010-13
IN
VDD
TRUTH TABLE
Serial Shift Register Contents Serial Latch Latch Contents Output Output Contents
elbanEelbanEataDkcolCataD
Input Input I1I2I3... IN-1 INOutput Input I1I2I3... IN-1 INInput I1I2I3... IN-1 IN
HHR
1R2... RN-2 RN-1 RN-1
LLR
1R2... RN-2 RN-1 RN-1
XR
1R2R3... RN-1 RNRN
XXX...X X X L R
1R2R3... RN-1 RN
P1P2P3... PN-1 PNPNHP
1P2P3... PN-1 PNLP
1P2P3... PN-1 PN
X X X ... X X H H H H ... H H
L = Low Logic (Voltage) Level H = High Logic (Voltage) Level X = Irrelevant P = Present State R = Previous State
VDD
Dwg. EP-063-6
OUT
Serial-Input Constant-Current Latched LED Driver
with Open LED Detection and Dot Correction
A6275
4
Allegro MicroSystems, Inc.
115 Northeast Cutoff
Worcester, Massachusetts 01615-0036 U.S.A.
1.508.853.5000; www.allegromicro.com
ELECTRICAL CHARACTERISTICS at TA = +25°C, VDD = 5 V (unless otherwise noted).
Limits
Characteristic Symbol Test Conditions Min. Typ. Max. Unit
Supply Voltage Range VDD Operating 4.5 5.0 5.5 V
Undervoltage Lockout VDD(UV) VDD = 0 → 5 V 3.4 – 4.0 V
Output Current IO V
CE = 0.7 V, REXT = 250 Ω 64.2 75.5 86.8 mA
(any single output) V
CE = 0.7 V, REXT = 470 Ω 34.1 40.0 45.9 mA
Output Current Matching ∆IO 0.4 V ≤ VCE(A) = VCE(B) ≤ 0.7 V:
(difference between any REXT = 250 Ω – ±1.5 ±6.0 %
two outputs at same VCE) R
EXT = 470 Ω – ±1.5 ±6.0 %
Output Leakage Current ICEX V
OH = 15 V – 1.0 5.0 μA
Logic Input Voltage VIH 0.7VDD – VDD V
V
IL GND – 0.3VDD V
SERIAL DATA OUT VOL I
OL = 500 μA – – 0.4 V
Voltage V
OH I
OH = -500 μA 4.6 – – V
Input Resistance RI ENABLE Input, Pull Up 150 300 600 kΩ
LATCH Input, Pull Down 100 200 400 kΩ
Supply Current IDD(OFF) R
EXT = open, VOE = 5 V – 0.8 1.4 mA
R
EXT = 470 Ω, VOE = 5 V 3.5 6.0 8.0 mA
R
EXT = 250 Ω, VOE = 5 V 6.5 11 15 mA
I
DD(ON) R
EXT = 470 Ω, VOE = 0 V 5.0 10 14 mA
R
EXT = 250 Ω, VOE = 0 V 8.0 16 24 mA
Typical Data is at VDD = 5 V and is for design information only.
Serial-Input Constant-Current Latched LED Driver
with Open LED Detection and Dot Correction
A6275
5
Allegro MicroSystems, Inc.
115 Northeast Cutoff
Worcester, Massachusetts 01615-0036 U.S.A.
1.508.853.5000; www.allegromicro.com
RECOMMENDED OPERATING CONDITIONS
Characteristic Symbol Conditions Min. Typ. Max. Unit
Supply Voltage VDD 4.5 5.0 5.5 V
Output Voltage VO – 1.0 4.0 V
Output Current IO Continuous, any one output – – 90 mA
I
OH SERIAL DATA OUT – – -1.0 mA
I
OL SERIAL DATA OUT – – 1.0 mA
Logic Input Voltage VIH 0.7VDD – VDD + 0.3 V
V
IL -0.3 – 0.3VDD V
Clock Frequency fCK Cascade operation – – 10 MHz
SWITCHING CHARACTERISTICS at TA = 25°C, VDD = VIH = 5 V, VCE = 0.4 V, VIL = 0 V,
REXT = 470 Ω, IO = 40 mA, VL = 3 V, RL = 65 Ω, CL = 10.5 pF.
Limits
Characteristic Symbol Test Conditions Min. Typ. Max. Unit
Propagation Delay Time tpHL CLOCK-OUTn – 350 1000 ns
LATCH-OUTn – 350 1000 ns
ENABLE-OUTn – 350 1000 ns
CLOCK-SERIAL DATA OUT – 40 – ns
Propagation Delay Time tpLH CLOCK-OUTn – 300 1000 ns
LATCH-OUTn – 300 1000 ns
ENABLE-OUTn – 300 1000 ns
CLOCK-SERIAL DATA OUT – 40 – ns
Output Fall Time tf 90% to 10% voltage 150 350 1000 ns
Output Rise Time tr 10% to 90% voltage 150 300 600 ns
Serial-Input Constant-Current Latched LED Driver
with Open LED Detection and Dot Correction
A6275
6
Allegro MicroSystems, Inc.
115 Northeast Cutoff
Worcester, Massachusetts 01615-0036 U.S.A.
1.508.853.5000; www.allegromicro.com
TIMING REQUIREMENTS and SPECIFICATIONS
(Logic Levels are VDD and Ground)
Serial data present at the input is transferred to the shift
register on the logic 0-to-logic 1 transition of the CLOCK input
pulse. On succeeding CLOCK pulses, the registers shift data in-
formation towards the SERIAL DATA OUTPUT. The serial data
must appear at the input prior to the rising edge of the CLOCK
input waveform.
Information present at any register is transferred to the
respective latch when the LATCH ENABLE is high (serial-to- sa atad wen tpecca ot eunitnoc sehctal ehT .)nois rev noc lel la rap
erehw snoit ac ilp pA .hgih dleh
si ELBANE HCTAL eht sa gnol
the latches are bypassed (LATCH ENABLE tied high) will laires gnirud hgih eb tupni ELBA NE TUPTUO eht taht eriuqer
data entry.
When the OUTPUT ENABLE input is high, the output sink sehctal eht
ni derots noit am rof ni ehT .)FFO( delbasid era sre vird
is not affected by the OUTPUT ENABLE input. With the OUT-
PUT ENABLE input low, the outputs are con trolled by the state
.sehctal evit ceps er rieht fo
A. Data Active Time Before Clock Pulse
(Data Set-Up Time), tsu(D) ............................. 50 ns
B. Data Active T ime After Clock Pulse
(Data Hold Time), th(D) ................................. 20 ns
C. Clock Pulse Width, tw(CK) .................................. 50 ns
D. noit av it cA kcolC neewteB emiT
and Latch Enable, tsu(L) ............................... 100 ns
E. Latch Enable Pulse Width, tw(L) ...................... 100 ns
F. Output Enable Pulse Width, tw(OE) ................... 4.5 s
NOTE: Timing is representative of a 10 MHz clock. Sig-
.elbaniatta era sdeeps rehgih yl tnac i fin
Max. Clock Transition Time, tr or tf ....................... 10 s
CLOCK
SERIAL
DATA IN
LATCH
ENABLE
OUTPUT
ENABLE
OUTN
Dwg. WP-029-1
50%
SERIAL
DATA OUT
DATA
DATA
50%
50%
50%
C
A B
D E
LOW = ALL OUTPUTS ENABLED
p
t
DATA
50%
p
t
LOW = OUTPUT ON
HIGH = OUTPUT OFF
OUTPUT
ENABLE
OUT
N
Dwg. WP-030-1A
DATA
10%
50%
pHL
t
pLH
t
HIGH = ALL OUTPUTS DISABLED (BLANKED)
f
t
r
t
90%
F
50%
Serial-Input Constant-Current Latched LED Driver
with Open LED Detection and Dot Correction
A6275
7
Allegro MicroSystems, Inc.
115 Northeast Cutoff
Worcester, Massachusetts 01615-0036 U.S.A.
1.508.853.5000; www.allegromicro.com
ALLOWABLE OUTPUT CURRENT AS A FUNC TION OF DUTY CYCLE
A Package LW Package
020
DUTY CYCLE IN PER CENT
100
0
Dwg. GP-062-5
6040
20
40
60
10080
V
CE
= 2 V
V
CE
= 3 V
V
CE
= 4 V
80
T
A
= +25°C
V
DD
= 5 V
Rθ
JA
= 60°C/W
020
DUTY CYCLE IN PER CENT
100
0
Dwg. GP-062-4A
6040
20
40
60
10080
VCE = 2 V
VCE = 3 V
VCE = 1 V
VCE = 4 V
80
TA = +25°C
VDD = 5 V
R
θ
JA = 94°C/W
020
DUTY CYCLE IN PER CENT
100
0
Dwg. GP-062-2A
6040
20
40
60
10080
V CE = 1 V
VCE = 2 V
VCE = 3 V
VCE = 4 V
80
TA = +50°C
VDD = 5 V
R
θ
JA = 94°C/W
020
DUTY CYCLE IN PER CENT
100
0
Dwg. GP-062-3
6040
20
40
60
10080
V
CE
= 2 V
V
CE
= 3 V
V
CE
= 4 V
80
T
A
= +50°C
V
DD
= 5 V
Rθ
JA
= 60°C/W
Serial-Input Constant-Current Latched LED Driver
with Open LED Detection and Dot Correction
A6275
8
Allegro MicroSystems, Inc.
115 Northeast Cutoff
Worcester, Massachusetts 01615-0036 U.S.A.
1.508.853.5000; www.allegromicro.com
020
DUTY CYCLE IN PER CENT
100
0
Dwg. GP-062A
6040
20
40
60
10080
V
CE
= 1 V
V
CE
= 2 V
V
CE
= 3 V
80
T
A
= +85°C
V
DD
= 5 V
R
θ
JA
= 94°C/W
V
CE
= 0.7 V
V
CE
= 4 V
ALLOWABLE OUTPUT CURRENT AS A FUNC TION OF DUTY CYCLE (cont.)
A Package LW Package
TYPICAL CHARACTERISTICS
020
DUTY CYCLE IN PER CENT
100
0
Dwg. GP-062-1
6040
20
40
60
10080
V
CE
= 1 V
V
CE
= 2 V
V
CE
= 3 V
V
CE
= 4 V
80
T
A
= +85°C
V
DD
= 5 V
R
θ
JA
= 60°C/W
0.5
Dwg. GP-063
1.0 2.0
1.5
VCE IN VOLTS
0
60
40
20
0
TA = +25°C
REXT = 500 Ω
Serial-Input Constant-Current Latched LED Driver
with Open LED Detection and Dot Correction
A6275
9
Allegro MicroSystems, Inc.
115 Northeast Cutoff
Worcester, Massachusetts 01615-0036 U.S.A.
1.508.853.5000; www.allegromicro.com
GROUND
REGISTER
LATCHES
1
2
3
10
11
12
13
15
4
5
6
7
14
16
SERIAL
DATA OUT
LOGIC
SUPPLY
SERIAL
DATA IN
OUTPUT
ENABLE
LATCH
ENABLE
CLOCK CK
VDD
OE
OUT 1
OUT
2
OUT
0
OUT 4
OUT 6
OUT 5
OUT
3
OUT 7
REXT
I
REGULATOR
L
O
89
GROUND
REGISTER
LATCHES
1
2
3
10
11
12
13
15
4
5
6
7
14
16
SERIAL
DATA OUT
LOGIC
SUPPLY
SERIAL
DATA IN
OUTPUT
ENABLE
LATCH
ENABLE
CLOCK CK
VDD
OE
OUT 1
OUT
2
OUT
0
OUT 4
OUT 6
OUT 5
OUT
3
OUT 7
REXT
I
REGULATOR
L
O
89
TERMINAL DESCRIPTION
Terminal No. Terminal Name Function
1
GND Reference terminal for control logic.
2 SERIAL DATA IN Serial-data input to the shift-register.
3 CLOCK Clock input terminal for data shift on rising edge.
4 LATCH ENABLE Data strobe input terminal; serial data is latched with high-level input.
5-12 OUT0-7 The eight current-sinking output ter mi nals.
13 OUTPUT ENABLE When (active) low, the output drivers are enabled; when high, all output driv-
ers are turned OFF (blanked).
14 SERIAL DATA OUT CMOS serial-data output to the following shift-register.
15 REXT An external resistor at this terminal establishes the output current for all sink
drivers.
16 SUPPLY (VDD) The logic supply voltage (typically 5 V).
Package A
Pin-out Diagrams
Package LW
Serial-Input Constant-Current Latched LED Driver
with Open LED Detection and Dot Correction
A6275
10
Allegro MicroSystems, Inc.
115 Northeast Cutoff
Worcester, Massachusetts 01615-0036 U.S.A.
1.508.853.5000; www.allegromicro.com
The load current per bit (IO) is set by the external re sis tor
(REXT) as shown in the fi gure below.
300 500 700 1 k 2 k
CURRENT-CONTROL RESISTANCE, R EXT IN OHMS
100
0100
Dwg. GP-061
5 k
200 3 k
20
40
60
80
V
CE
= 0.7 V
Package Power Dissipation (PD). The maximum al-
low able package power dissipation is determined as
PD(max) = (150 - TA)/RθJA.
The actual package power dissipation is
PD(act) = dc(VCE × IO × 8) + (VDD × IDD).
When the load supply voltage is greater than 3 V to 5 V,
considering the package power dissipating limits of these
devices, or if PD(act) > PD(max), an external voltage re-
ducer (VDROP) should be used.
Load Supply Voltage (VLED). These devices are de-
signed to operate with driver voltage drops (VCE) of
0.4 V to 0.7 V with LED forward voltages (VF) of 1.2 V to
4.0 V. If higher voltages are dropped across the driver,
package power dissipation will be increased signifi cantly.
To minimize package power dissipation, it is rec om -
mend ed to use the lowest possible load supply voltage or
to set any series dropping voltage (VDROP) as
VDROP = VLED - VF - VCE
with VDROP = Io × RDROP for a single driver, or a Zener
diode (VZ), or a series string of diodes (approximately
0.7 V per diode) for a group of drivers. If the available
voltage source will cause unacceptable dissipation and
series resistors or diode(s) are undesirable, a regulator
such as the Sanken Series SAI or Series SI can be used to
pro vide supply voltages as low as 3.3 V.
For reference, typical LED forward voltages are:
White 3.5 – 4.0 V
Blue 3.0 – 4.0 V
Green 1.8 – 2.2 V
Yellow 2.0 – 2.1 V
Amber 1.9 – 2.65 V
Red 1.6 – 2.25 V
Infrared 1.2 – 1.5 V
Pattern Layout. This device has a common logic-ground
and power-ground terminal. If ground pattern layout
con tains large common-mode resistance, and the voltage
between the system ground and the LATCH ENABLE or
CLOCK terminals ex ceeds 2.5 V (because of switching
noise), these devices may not operate correctly.
Dwg. EP-064
VLED
VDROP
VF
VCE
Applications Information
Serial-Input Constant-Current Latched LED Driver
with Open LED Detection and Dot Correction
A6275
11
Allegro MicroSystems, Inc.
115 Northeast Cutoff
Worcester, Massachusetts 01615-0036 U.S.A.
1.508.853.5000; www.allegromicro.com
Package A 16-Pin DIP
2
19.05±0.25
5.33 MAX
0.46 ±0.12
1.27 MIN
1
16
A
Dimensions exclusive of mold flash, gate burrs, and dambar protrusions
Exact case and lead configuration at supplier discretion within limits shown
ATerminal #1 mark area
6.35 +0.76
–0.25
3.30 +0.51
–0.38
10.92 +0.38
–0.25
1.52 +0.25
–0.38
0.38 +0.10
–0.05
7.62
2.54
For Reference Only
(reference JEDEC MS-001 BB)
Dimensions in inches, metric dimensions (mm) in brackets, for reference only
Package LW 16-Pin SOICW
9.50
0.65
2.25
1.27
C
SEATING
PLANE
1.27
0.25
0.20 ±0.10
0.41 ±0.10 2.65 MAX
10.30±0.33
7.50±0.10
4° ±4
0.27 +0.07
–0.06
0.84 +0.44
–0.43
10.30±0.20
C0.10
16X
21
16
GAUGE PLANE
SEATING PLANE
For Reference Only
Dimensions in millimeters
(reference JEDEC MS-013 AA)
Dimensions exclusive of mold flash, gate burrs, and dambar protrusions
Exact case and lead configuration at supplier discretion within limits shown
ATerminal #1 mark area
A
BReference pad layout (reference IPC SOIC127P1030X265-16M)
All pads a minimum of 0.20 mm from all adjacent pads; adjust as necessary
to meet application process requirements and PCB layout tolerances
BPCB Layout Reference View
21
16
Copyright ©2000-2008, Allegro MicroSystems, Inc.
The products described here are manufactured under one or more U.S. patents or U.S. patents pending.
Allegro MicroSystems, Inc. reserves the right to make, from time to time, such de par tures from the detail spec i fi ca tions as may be required to per-
mit improvements in the per for mance, reliability, or manufacturability of its products. Before placing an order, the user is cautioned to verify that the
information being relied upon is current.
Allegro’s products are not to be used in life support devices or systems, if a failure of an Allegro product can reasonably be expected to cause the
failure of that life support device or system, or to affect the safety or effectiveness of that device or system.
The in for ma tion in clud ed herein is believed to be ac cu rate and reliable. How ev er, Allegro MicroSystems, Inc. assumes no re spon si bil i ty for its use;
nor for any in fringe ment of patents or other rights of third parties which may result from its use.
For the latest version of this document, visit our website:
www.allegromicro.com
