©2001 Fairchild Semiconductor Corporation FSF250D, FSF250R Rev. A
June 1998
FSF250D, FSF250R
24A, 200V, 0.110 Ohm, Rad Hard,
SEGR Resistant, N-Channel Power MOSFETs
Features
• 24A, 200V, r
DS(ON)
= 0.110
Ω
• Total Dose
- Meets Pre-RAD Specifications to 100K RAD (Si)
• Single Event
- Safe Operating Area Curve for Single Event Effects
- SEE Immunity for LET of 36MeV/mg/cm
2
with
V
DS
up to 80% of Rated Breakdown and
V
GS
of 10V Off-Bias
• Dose Rate
- Typically Survives 3E9 RAD (Si)/s at 80% BV
DSS
- Typically Survives 2E12 if Current Limited to I
DM
• Photo Current
- 12nA Per-RAD(Si)/s Typically
• Neutron
- Maintain Pre-RAD Specifications
for 1E13 Neutrons/cm
2
- Usable to 1E14 Neutrons/cm
2
Formerly available as type TA17657.
Description
The Discrete Products Operation of Intersil Corporation has
developed a series of Radiation Hardened MOSFETs specif-
ically designed for commercial and military space applica-
tions. Enhanced Power MOSFET immunity to Single Event
Effects (SEE), Single Event Gate Rupture (SEGR) in particu-
lar, is combined with 100K RADS of total dose hardness to
provide devices which are ideally suited to harsh space envi-
ronments. The dose rate and neutron tolerance necessary
for military applications have not been sacrificed.
The Intersil portfolio of SEGR resistant radiation hardened
MOSFETs includes N-Channel and P-Channel devices in a
variety of voltage, current and on-resistance ratings.
Numerous packaging options are also available.
This MOSFET is an enhancement-mode silicon-gate power
field-effect transistor of the vertical DMOS (VDMOS) struc-
ture. It is specially designed and processed to be radiation
tolerant. The MOSFET is well suited for applications exposed
to radiation environments such as switching regulation,
switching converters, motor drives, relay drivers and drivers
for high-power bipolar switching transistors requiring high
speed and low gate drive power. This type can be operated
directly from integrated circuits.
Reliability screening is available as either commercial, TXV
equivalent of MIL-S-19500, or Space equivalent of
MIL-S-19500. Contact Intersil for any desired deviations from
the data sheet.
Symbol
Package
TO-254AA
Ordering Information
RAD LEVEL SCREENING LEVEL PART NO./BRAND
10K Commercial FSF250D1
10K TXV FSF250D3
100K Commercial FSF250R1
100K TXV FSF250R3
100K Space FSF250R4
D
G
S
CAUTION: Beryllia Warning per MIL-S-19500
refer to package specifications.
S
G
D
©2001 Fairchild Semiconductor Corporation FSF250D, FSF250R Rev. A
Absolute Maximum Ratings
T
C
= 25
o
C, Unless Otherwise Specified
FSF250D, FSF250R UNITS
Drain to Source Voltage . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .V
DS
200 V
Drain to Gate Voltage (R
GS
= 20k
Ω
) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . V
DGR
200 V
Continuous Drain Current
T
C
= 25
o
C. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . I
D
24 A
T
C
= 100
o
C. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . I
D
15 A
Pulsed Drain Current . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . I
DM
72 A
Gate to Source Voltage. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .V
GS
±
20 V
Maximum Power Dissipation
T
C
= 25
o
C. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . P
T
125 W
T
C
= 100
o
C. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . P
T
50 W
Linear Derating Factor . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 1.00 W/
o
C
Single Pulsed Avalanche Current, L = 100
µ
H, (See Test Figure). . . . . . . . . . . . . . . . . . . . . . I
AS
72 A
Continuous Source Current (Body Diode) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . I
S
24 A
Pulsed Source Current (Body Diode) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . I
SM
72 A
Operating and Storage Temperature . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . T
J
, T
STG
-55 to 150
o
C
Lead Temperature (During Soldering) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . T
L
(Distance >0.063in (1.6mm) from Case, 10s Max)
300
o
C
CAUTION: Stresses above those listed in “Absolute Maximum Ratings” may cause permanent damage to the device. This is a stress only rating and operation
of the device at these or any other conditions above those indicated in the operational sections of this specification is not implied.
Electrical Specifications
T
C
= 25
o
C, Unless Otherwise Specified
PARAMETER SYMBOL TEST CONDITIONS MIN TYP MAX UNITS
Drain to Source Breakdown Voltage BV
DSS
I
D
= 1mA, V
GS
= 0V 200 - - V
Gate Threshold Voltage V
GS(TH)
V
GS
= V
DS
,
I
D
= 1mA
T
C
= -55
o
C - - 5.0 V
T
C
= 25
o
C 1.5 - 4.0 V
T
C
= 125
o
C 0.5 - - V
Zero Gate Voltage Drain Current I
DSS
V
DS
= 160V,
V
GS
= 0V
T
C
= 25
o
C--25
µ
A
T
C
= 125
o
C - - 250
µ
A
Gate to Source Leakage Current I
GSS
V
GS
=
±
20V T
C
= 25
o
C - - 100 nA
T
C
= 125
o
C - - 200 nA
Drain to Source On-State Voltage V
DS(ON)
V
GS
= 12V, I
D
= 24A - - 2.77 V
Drain to Source On Resistance r
DS(ON)12
I
D
= 15A,
V
GS
= 12V
T
C
= 25
o
C - 0.085 0.110
Ω
T
C
= 125
o
C - - 0.189
Ω
Turn-On Delay Time t
d(ON)
V
DD
= 100V, I
D
= 24A,
R
L
= 4.17
Ω
, V
GS
12V,
R
GS
= 2.35
Ω
- - 130 ns
Rise Time t
r
- - 160 ns
Turn-Off Delay Time t
d(OFF)
- - 160 ns
Fall Time t
f
- - 65 ns
Total Gate Charge Q
g(TOT)
V
GS
= 0V to 20V V
DD
= 100V,
I
D
= 24A
- - 250 nC
Gate Charge at 12V Q
g(12)
V
GS
= 0V to 12V - 130 160 nC
Threshold Gate Charge Q
g(TH)
V
GS
= 0V to 2V - - 10 nC
Gate Charge Source Q
gs
-2636nC
Gate Charge Drain Q
gd
-6584nC
Plateau Voltage V
(PLATEAU)
I
D
= 24A, V
DS
= 15V - 7 - V
Input Capacitance C
ISS
V
DS
= 25V, V
GS
= 0V,
f = 1MHz
- 3200 - pF
Output Capacitance C
OSS
- 625 - pF
Reverse Transfer Capacitance C
RSS
- 175 - pF
Thermal Resistance Junction to Case R
θ
JC
- - 1.00
o
C/W
Thermal Resistance Junction to Ambient R
θ
JA
--48
o
C/W
FSF250D, FSF250R
©2001 Fairchild Semiconductor Corporation FSF250D, FSF250R Rev. A
Source to Drain Diode Specifications
PARAMETER SYMBOL TEST CONDITIONS MIN TYP MAX UNITS
Forward Voltage V
SD
I
SD
= 24A 0.6 - 1.8 V
Reverse Recovery Time t
rr
I
SD
= 24A, dI
SD
/dt = 100A/
µ
s - - 540 ns
Electrical Specifications up to 100K RAD
T
C
= 25
o
C, Unless Otherwise Specified
PARAMETER SYMBOL TEST CONDITIONS MIN MAX UNITS
Drain to Source Breakdown Volts (Note 3) BVDSS VGS = 0, ID = 1mA 200 - V
Gate to Source Threshold Volts (Note 3) VGS(TH) VGS = VDS, ID = 1mA 1.5 4.0 V
Gate to Body Leakage (Notes 2, 3) IGSS VGS = ±20V, VDS = 0V - 100 nA
Zero Gate Leakage (Note 3) IDSS VGS = 0, VDS = 160V - 25 µA
Drain to Source On-State Volts (Notes 1, 3) VDS(ON) VGS = 12V, ID = 24A - 2.77 V
Drain to Source On Resistance (Notes 1, 3) rDS(ON)12 VGS = 12V, ID = 15A - 0.110 Ω
NOTES:
1. Pulse test, 300µs Max.
2. Absolute value.
3. Insitu Gamma bias must be sampled for both VGS = 12V, VDS = 0V and VGS = 0V, VDS = 80% BVDSS.
Single Event Effects (SEB, SEGR) (Note 4)
TEST SYMBOL
ENVIRONMENT (NOTE 5) APPLIED
VGS BIAS
(V)
(NOTE 6)
MAXIMUM
VDS BIAS (V)
ION
SPECIES
TYPICAL LET
(MeV/mg/cm)
TYPICAL
RANGE (µ)
Single Event Effects Safe Operating Area SEESOA Ni 26 43 -20 200
Br 37 36 -5 200
Br 37 36 -10 160
Br 37 36 -15 100
Br 37 36 -20 40
NOTES:
4. Testing conducted at Brookhaven National Labs; sponsored by Naval Surface Warfare Center (NSWC), Crane, IN.
5. FLUENCE = 1E5 ions/cm2 (typical), T = 25oC.
6. Does not exhibit Single Event Burnout (SEB) or Single Event Gate Rupture (SEGR).
Typical Performance Curves Unless Otherwise Specified
FIGURE 1. SINGLE EVENT EFFECTS SAFE OPERATING AREA FIGURE 2. DRAIN INDUCTANCE REQUIRED TO LIMIT
GAMMA DOT CURRENT TO IAS
120
80
40
0
0 -10 -15 -20 -25
-5
VGS (V)
VDS (V)
160
200
TEMP = 25oC
LET = 37MeV/mg/cm2, RANGE = 36µ
LET = 26MeV/mg/cm2, RANGE = 43µ
FLUENCE = 1E5 IONS/cm2 (TYPICAL)
30010010
LIMITING INDUCTANCE (HENRY)
DRAIN SUPPLY (V)
1000
ILM = 10A
300A
1E-4
1E-5
1E-6
30
100A
30A
1E-7
1E-3
FSF250D, FSF250R
©2001 Fairchild Semiconductor Corporation FSF250D, FSF250R Rev. A
FIGURE 3. MAXIMUM CONTINUOUS DRAIN CURRENT vs
TEMPERATURE
FIGURE 4. FORWARD BIAS SAFE OPERATING AREA
FIGURE 5. BASIC GATE CHARGE WAVEFORM FIGURE 6. NORMALIZED rDS(ON) vs JUNCTION TEMPERATURE
Typical Performance Curves Unless Otherwise Specified (Continued)
ID, DRAIN (A)
TC, CASE TEMPERATURE (oC)
150100500-50
0
20
30
10
100
10
1
1
0.1
ID, DRAIN CURRENT (A)
VDS, DRAIN TO SOURCE VOLTAGE (V)
10 100 600
100µs
10ms
1ms
100ms
OPERATION IN THIS
AREA MAY BE
LIMITED BY rDS(ON)
TC = 25oC
CHARGE
QGD
QG
VG
QGS
12V
2.5
2.0
1.5
1.0
0.5
0.0
-80 -40 0 40 80 120 160
TJ, JUNCTION TEMPERATURE (oC)
NORMALIZED rDS(ON)
PULSE DURATION = 250ms, VGS = 12V, ID = 15A
FSF250D, FSF250R
©2001 Fairchild Semiconductor Corporation FSF250D, FSF250R Rev. A
FIGURE 7. NORMALIZED MAXIMUM TRANSIENT THERMAL RESPONSE
FIGURE 8. UNCLAMPED INDUCTIVE SWITCHING
Typical Performance Curves Unless Otherwise Specified (Continued)
NORMALIZED
1
0.1
0.01
10-5 10-4 10-3 10-2 10-1 100101
t, RECTANGULAR PULSE DURATION (s)
THERMAL RESPONSE (ZθJC)
0.001
NOTES:
DUTY FACTOR: D = t1/t2
PEAK TJ = PDM x ZθJC + TC
SINGLE PULSE
0.01
0.02
0.05
0.1
0.2
0.5
PDM
t1
t2
300
100
10
1
0.01 0.1 1
tAV , TIME IN AVALANCHE (ms)
IAS, AVALANCHE CURRENT (A)
STARTING TJ = 150oC
STARTING TJ = 25oC
tAV = (L) (IAS) / (1.3 RATED BVDSS - VDD)
IF R = 0
IF R ≠ 0
tAV = (L/R) ln [(IAS*R) / (1.3 RATED BVDSS - VDD) + 1]
10
FSF250D, FSF250R
©2001 Fairchild Semiconductor Corporation FSF250D, FSF250R Rev. A
Test Circuits and Waveforms
FIGURE 9. UNCLAMPED ENERGY TEST CIRCUIT FIGURE 10. UNCLAMPED ENERGY WAVEFORMS
FIGURE 11. RESISTIVE SWITCHING TEST CIRCUIT FIGURE 12. RESISTIVE SWITCHING WAVEFORMS
tP
VGS ≤ 20V
L
+
-
VDS
VDD
DUT
VARY tP TO OBTAIN
REQUIRED PEAK IAS
0V
50Ω
50Ω
50V-150V
IAS
+
-
ELECTRONIC SWITCH OPENS
WHEN IAS IS REACHED
CURRENT
TRANSFORMER
VDD
VDS
BVDSS
tP
IAS
tAV
VDS
DUT
RGS
0V
VGS = 12V
VDD
RL
td(ON)
tr
90%
10%
VDS 90%
10%
tf
td(OFF)
tOFF
90%
50%50%
10% PULSE WIDTH
VGS
tON
FSF250D, FSF250R
©2001 Fairchild Semiconductor Corporation FSF250D, FSF250R Rev. A
Screening Information
Screening is performed in accordance with the latest revision in effect of MIL-S-19500, (Screening Information Table).
Delta Tests and Limits (JANTXV Equivalent, JANS Equivalent) TC = 25oC, Unless Otherwise Specified
PARAMETER SYMBOL TEST CONDITIONS MAX UNITS
Gate to Source Leakage Current IGSS VGS = ±20V ±20 (Note 7) nA
Zero Gate Voltage Drain Current IDSS VDS = 80% Rated Value ±25 (Note 7) µA
Drain to Source On Resistance rDS(ON) TC = 25oC at Rated ID±20% (Note 8) Ω
Gate Threshold Voltage VGS(TH) ID = 1.0mA ±20% (Note 8) V
NOTES:
7. Or 100% of Initial Reading (whichever is greater).
8. Of Initial Reading.
Screening Information
TEST JANTXV EQUIVALENT JANS EQUIVALENT
Gate Stress VGS = 30V, t = 250µsV
GS = 30V, t = 250µs
Pind Optional Required
Pre Burn-In Tests (Note 9) MIL-S-19500 Group A,
Subgroup 2 (All Static Tests at 25oC)
MIL-S-19500 Group A,
Subgroup 2 (All Static Tests at 25oC)
Steady State Gate
Bias (Gate Stress)
MIL-STD-750, Method 1042, Condition B
VGS = 80% of Rated Value,
TA = 150oC, Time = 48 hours
MIL-STD-750, Method 1042, Condition B
VGS = 80% of Rated Value,
TA = 150oC, Time = 48 hours
Interim Electrical Tests (Note 9) All Delta Parameters Listed in the Delta Tests
and Limits Table
All Delta Parameters Listed in the Delta Tests
and Limits Table
Steady State Reverse
Bias (Drain Stress)
MIL-STD-750, Method 1042, Condition A
VDS = 80% of Rated Value,
TA = 150oC, Time = 160 hours
MIL-STD-750, Method 1042, Condition A
VDS = 80% of Rated Value,
TA = 150oC, Time = 240 hours
PDA 10% 5%
Final Electrical Tests (Note 9) MIL-S-19500, Group A, Subgroup 2 MIL-S-19500, Group A,
Subgroups 2 and 3
NOTE:
9. Test limits are identical pre and post burn-in.
Additional Screening Tests
PARAMETER SYMBOL TEST CONDITIONS MAX UNITS
Safe Operating Area SOA VDS = 160V, t = 10ms 1.75 A
Unclamped Inductive Switching IAS VGS(PEAK) = 15V, L = 0.1mH 72 A
Thermal Response ∆VSD tH = 100ms, VH = 25V, IH = 4A 136 mV
Thermal Impedance ∆VSD tH = 500ms, VH = 25V, IH = 4A 187 mV
FSF250D, FSF250R
©2001 Fairchild Semiconductor Corporation FSF250D, FSF250R Rev. A
Rad Hard Data Packages - Intersil Power Transistors
TXV Equivalent
1. Rad Hard TXV Equivalent - Standard Data Package
A. Certificate of Compliance
B. Assembly Flow Chart
C. Preconditioning - Attributes Data Sheet
D. Group A - Attributes Data Sheet
E. Group B - Attributes Data Sheet
F. Group C - Attributes Data Sheet
G. Group D - Attributes Data Sheet
2. Rad Hard TXV Equivalent - Optional Data Package
A. Certificate of Compliance
B. Assembly Flow Chart
C. Preconditioning - Attributes Data Sheet
- Precondition Lot Traveler
- Pre and Post Burn-In Read and Record
Data
D. Group A - Attributes Data Sheet
- Group A Lot Traveler
E. Group B - Attributes Data Sheet
- Group B Lot Traveler
- Pre and Post Read and Record Data for
Intermittent Operating Life (Subgroup B3)
- Bond Strength Data (Subgroup B3)
- Pre and Post High Temperature Operating
Life Read and Record Data (Subgroup B6)
F. Group C - Attributes Data Sheet
- Group C Lot Traveler
- Pre and Post Read and Record Data for
Intermittent Operating Life (Subgroup C6)
- Bond Strength Data (Subgroup C6)
G. Group D - Attributes Data Sheet
- Group D Lot Traveler
- Pre and Post RAD Read and Record Data
Class S - Equivalents
1. Rad Hard “S” Equivalent - Standard Data Package
A. Certificate of Compliance
B. Serialization Records
C. Assembly Flow Chart
D. SEM Photos and Report
E. Preconditioning Attributes Data Sheet
Hi-Rel Lot Traveler
HTRB - Hi Temp Gate Stress Post Reverse
Bias Data and Delta Data
HTRB - Hi Temp Drain Stress Post Reverse
Bias Delta Data
F. Group A - Attributes Data Sheet
G. Group B - Attributes Data Sheet
H. Group C - Attributes Data Sheet
I. Group D - Attributes Data Sheet
2. Rad Hard Max. “S” Equivalent - Optional Data Package
A. Certificate of Compliance
B. Serialization Records
C. Assembly Flow Chart
D. SEM Photos and Report
E. Preconditioning - Attributes Data Sheet
- Hi-Rel Lot Traveler
- HTRB - Hi Temp Gate Stress Post
Reverse Bias Data and Delta Data
- HTRB - Hi Temp Drain Stress Post
Reverse Bias Delta Data
- X-Ray and X-Ray Report
F. Group A - Attributes Data Sheet
- Hi-Rel Lot Traveler
- Subgroups A2, A3, A4, A5 and A7 Data
G. Group B - Attributes Data Sheet
- Hi-Rel Lot Traveler
- Subgroups B1, B3, B4, B5 and B6 Data
H. Group C - Attributes Data Sheet
- Hi-Rel Lot Traveler
- Subgroups C1, C2, C3 and C6 Data
I. Group D - Attributes Data Sheet
- Hi-Rel Lot Traveler
- Pre and Post Radiation Data
FSF250D, FSF250R
©2001 Fairchild Semiconductor Corporation FSF250D, FSF250R Rev. A
FSF250D, FSF250R
TO-254AA
3 LEAD JEDEC TO-254AA HERMETIC METAL PACKAGE
D
L
Q
H1
e
e1
J1
A1
A
EØP
Øb
0.065 R MAX.
TYP.
123
SYMBOL
INCHES MILLIMETERS
NOTESMIN MAX MIN MAX
A 0.249 0.260 6.33 6.60 -
A10.040 0.050 1.02 1.27 -
Øb 0.035 0.045 0.89 1.14 2, 3
D 0.790 0.800 20.07 20.32 -
E 0.535 0.545 13.59 13.84 -
e 0.150 TYP 3.81 TYP 4
e1 0.300 BSC 7.62 BSC 4
H10.245 0.265 6.23 6.73 -
J10.140 0.160 3.56 4.06 4
L 0.520 0.560 13.21 14.22 -
ØP 0.139 0.149 3.54 3.78 -
Q 0.110 0.130 2.80 3.30 -
NOTES:
1. These dimensions are within allowable dimensions of Rev. A of
JEDEC outline TO-254AA dated 11-86.
2. Add typically 0.002 inches (0.05mm) for solder coating.
3. Lead dimension (without solder).
4. Position of lead to be measured 0.250 inches (6.35mm) from bot-
tom of dimension D.
5. Die to base BeO isolated, terminals to case ceramic isolated.
6. Controlling dimension: Inch.
7. Revision 1 dated 1-93.
WARNING!
BERYLLIA WARNING PER MIL-S-19500
Packages containing beryllium oxide (BeO) shall not be ground, machined, sandblasted, or subject to any mechanical
operation which will produce dust containing any beryllium compound. Packages containing any beryllium compound
shall not be subjected to any chemical process (etching, etc.) which will produce fumes containing beryllium or its’
compounds.
TRADEMARKS
The following are registered and unregistered trademarks Fairchild Semiconductor owns or is authorized to use and is
not intended to be an exhaustive list of all such trademarks.
LIFE SUPPORT POLICY
FAIRCHILD’S PRODUCTS ARE NOT AUTHORIZED FOR USE AS CRITICAL COMPONENTS IN LIFE SUPPORT
DEVICES OR SYSTEMS WITHOUT THE EXPRESS WRITTEN APPROV AL OF FAIRCHILD SEMICONDUCTOR CORPORATION.
As used herein:
1. Life support devices or systems are devices or
systems which, (a) are intended for surgical implant into
the body, or (b) support or sustain life, or (c) whose
failure to perform when properly used in accordance
with instructions for use provided in the labeling, can be
reasonably expected to result in significant injury to the
user.
2. A critical component is any component of a life
support device or system whose failure to perform can
be reasonably expected to cause the failure of the life
support device or system, or to affect its safety or
effectiveness.
PRODUCT ST A TUS DEFINITIONS
Definition of Terms
Datasheet Identification Product Status Definition
Advance Information
Preliminary
No Identification Needed
Obsolete
This datasheet contains the design specifications for
product development. Specifications may change in
any manner without notice.
This datasheet contains preliminary data, and
supplementary data will be published at a later date.
Fairchild Semiconductor reserves the right to make
changes at any time without notice in order to improve
design.
This datasheet contains final specifications. Fairchild
Semiconductor reserves the right to make changes at
any time without notice in order to improve design.
This datasheet contains specifications on a product
that has been discontinued by Fairchild semiconductor.
The datasheet is printed for reference information only.
Formative or
In Design
First Production
Full Production
Not In Production
DISCLAIMER
FAIRCHILD SEMICONDUCTOR RESERVES THE RIGHT TO MAKE CHANGES WITHOUT FURTHER
NOTICE TO ANY PRODUCTS HEREIN TO IMPROVE RELIABILITY, FUNCTION OR DESIGN. FAIRCHILD
DOES NOT ASSUME ANY LIABILITY ARISING OUT OF THE APPLICATION OR USE OF ANY PRODUCT
OR CIRCUIT DESCRIBED HEREIN; NEITHER DOES IT CONVEY ANY LICENSE UNDER ITS PATENT
RIGHTS, NOR THE RIGHTS OF OTHERS.
PACMAN™
POP™
PowerTrench
QFET™
QS™
QT Optoelectronics™
Quiet Series™
SILENT SWITCHER
SMART ST ART™
Star* Power™
Stealth™
FAST
FASTr™
GlobalOptoisolator™
GTO™
HiSeC™
ISOPLANAR™
LittleFET™
MicroFET™
MICROWIRE™
OPTOLOGIC™
OPTOPLANAR™
Rev. H
ACEx™
Bottomless™
CoolFET™
CROSSVOLT™
DenseTrench™
DOME™
EcoSPARK™
E2CMOSTM
EnSignaTM
FACT™
F ACT Quiet Series™
SuperSOT™-3
SuperSOT™-6
SuperSOT™-8
SyncFET™
TinyLogic™
UHC™
UltraFET™
VCX™