SC16IS740IPW/Q900,128 - NXP SEMICONDUCTORS

1. General description

The PCF85163 is a CMOS1 Real-T ime Clock ( RTC) and calendar optimized for low power

consumption. A program mable clock output, interrup t output, and volt age-low detector are

also provided. All addresses and data are transferred serially via a two-line bidirectional

I2C-bus. Maximum bus speed is 400 kbit/s. The register address is incremented

automatically after each written or read data byte.

2. Features and benefits

Provides year, month, day, weekday, hours, minutes, and seconds based on a

32.768 kHz quartz crystal

Century flag

Clock operating voltage: 1.8 V to 5.5 V

Low backup current; typical 0.25 μAat V

DD = 3.0 V and Tamb =25°C

400 kHz two-line I2C-bus interface (at VDD = 1.8 V to 5.5 V)

Programmable clo ck output for peripheral devices (32.768 kHz, 1.024 kHz, 32 Hz, and

1Hz)

Alarm and timer functions

Internal Power-On Reset (POR)

I2C-bus slave address: read A3h and write A2h

Open-drain interrupt pin

3. Applications

Mobile telephones

Portable instruments

Electronic metering

Battery powered products

PCF85163

Real-time clock and calendar

Rev. 2 — 28 July 2010 Product data sheet

1. The definition of the abbreviations and acronyms used in this data sheet can be found in Section 18.

Product data sheet Rev. 2 — 28 July 2010 2 of 43

NXP Semiconductors PCF85163

Real-ti m e clo c k an d ca len d ar

4. Ordering information

5. Marking

Ta ble 1. Ordering information

Type number Package

Name Description Version

PCF85163T SO8 plastic small outline package; 8 leads;

body width 3.9 mm SOT96-1

PCF85163TS TSSOP8 plastic thin shrink small outline package;

8 leads; body width 3 mm SOT505-1

Ta ble 2. Marking codes

Type number Marking code

PCF85163T PF85163

PCF85163TS 85163

Product data sheet Rev. 2 — 28 July 2010 3 of 43

NXP Semiconductors PCF85163

Real-ti m e clo c k an d ca len d ar

6. Block diagram

(1) COSCO; values see Table 30.

Fig 1. Block diagram of PCF85163

013aaa038

PCF85163

OSCILLATOR

32.768 kHz DIVIDER CLOCK OUT

INTERRUPT

CLKOUT

INT

MONITOR

POWER ON

RESET

WATCH

DOG

I2C-BUS

INTERFACE

OSCI

SCL

SDA

OSCO

VDD

VSS

TIMER FUNCTION

Timer_control0Eh

Timer0Fh

CONTROL

Control_100h

Control_201h

CLKOUT_control0Dh

TIME

VL_seconds02h

Minutes03h

Hours04h

Days05h

ALARM FUNCTION

Minute_alarm09h

Hour_alarm0Ah

Day_alarm0Bh

Weekday_alarm0Ch

Weekdays06h

Century_months07h

Years08h

(1)

Product data sheet Rev. 2 — 28 July 2010 4 of 43

NXP Semiconductors PCF85163

Real-ti m e clo c k an d ca len d ar

7. Pinning information

7.1 Pinning

7.2 Pin description

Top view. For mechanical details, see Figure 26

Fig 2. Pin configuration for SO8 (PCF8 5163T)

Top view. For mechanical details, see Figure 27

Fig 3. Pin configuration for TSSOP8 (PCF85163TS)

PCF85163T

OSCI VDD

OSCO CLKOUT

INT SCL

VSS SDA

013aaa039

PCF85163TS

OSCI VDD

OSCO CLKOUT

INT SCL

VSS SDA

013aaa040

Ta ble 3. Pin description

Symbol Pin Description

SO8

(PCF85163T) TSSOP8

(PCF85163TS)

OSCI 1 1 oscillator input

OSCO 2 2 oscillator output

INT 3 3 interrupt output (open-drain; active LOW)

VSS 4 4 ground supply voltage

SDA 5 5 serial data input and output

SCL 6 6 serial clock input

CLKOUT 7 7 clock output (open-drain)

VDD 8 8 supply voltage

Product data sheet Rev. 2 — 28 July 2010 5 of 43

NXP Semiconductors PCF85163

Real-ti m e clo c k an d ca len d ar

8. Functional description

The PCF85163 contains sixteen 8-bit regi sters with an auto-incrementing register

address, an on-chip 32.768 kHz oscillator with one integrated capacitor, a frequency

divider which provides the source clock for the Real-Time Clock (RTC) and calender, a

programmable clock output, a timer, an alarm, a voltage-low detector, and a 400 kHz

I2C-bus interface.

All 16 registers (see Table 4) are designed as a ddressable 8-bit p arallel registers a lthough

not all bits are implemente d. The first two re gisters (memory ad d re ss 00h and 01h) are

used as control an d /o r status regis te rs. The addresses 02h through 08h are used as

counters for the clock function (seconds up to years counters). Address locations 09h

through 0Ch contain alarm regis te rs wh ich de fin e the co nditio ns for an alarm.

Address 0Dh controls the CLKO UT ou tp ut freq ue n cy. 0Eh and 0Fh are the timer con tro l

and timer registers, respectively.

The Seconds, Minutes, Hours, Days, Months, Years as well as the Minute_alarm,

Hour_alarm, and Day_alarm registers are all coded in Binary Coded Decimal (BCD)

format.

When one of the RTC registers is written or read, the cont en ts of all time counte rs ar e

frozen. Therefore, faulty writing or reading of the clock and calendar during a carry

condition is prevented.

8.1 CLKOUT output

A programmable square wave is available at the CL KOUT pin. Operation is controlled by

the register CLKOUT_control at address 0Dh. Frequencies of 32.768 kHz (default),

1.024 kHz, 32 Hz, and 1 Hz can be generated for use as a system clock, microcontroller

clock, input to a charge pump, or for calibration of the oscillator . CLKOUT is an open-drain

output and enabled at power-on. If disabled it becomes high-impedance.

Product data sheet Rev. 2 — 28 July 2010 6 of 43

NXP Semiconductors PCF85163

Real-ti m e clo c k an d ca len d ar

8.2 Register organization

Table 4. Register overview

Bit positions labeled as x are not relevant. Bit positions labeled with N should always be written with logic 0; if read, they could

be either logic 0 or logic 1. After reset, all register are set according to Table 27.

Address Register name Bit

7 6 5 4 3 2 1 0

Control and status registers

00h Control_1 TEST1 N STOP N TESTC N N N

01h Control_2 N N N TI_TP AF TF AIE TIE

Time and date registers

02h VL_seconds VL SECONDS (0 to 59)

03h Minutes x MINUTES (0 to 59)

04h Hours x x HOURS (0 to 23)

05h Days x x DAYS (1 to 31)

06h Weekdays x x x x x WEEKDAYS (0 to 6)

07h Century_months C x x MONTHS (1 to 12)

08h Years YEARS (0 to 99)

Alarm registers

09h Minute_alarm AE_M MINUTE_ALARM (0 to 59)

0Ah Hour_alarm AE_H x HOUR_ALARM (0 to 23)

0Bh Day_alarm AE_D x DAY_ALARM (1 to 31)

0Ch Weekday_alarm AE_W x x x x WEEKDAY_ALARM (0 to 6)

CLKOUT control register

0Dh CLKOUT_control FE x x x x x FD[1:0]

Tim er regist ers

0Eh Timer_control TE x x x x x TD[1:0]

0Fh Timer COUNTDOWN_TIMER[7:0]

Product data sheet Rev. 2 — 28 July 2010 7 of 43

NXP Semiconductors PCF85163

Real-ti m e clo c k an d ca len d ar

8.3 Control registers

8.3.1 Register Control_1

[1] Default value.

[2] Bits labeled as N should always be written with logic 0.

8.3.2 Register Control_2

[1] Bits labeled as N should always be written with logic 0.

[2] Default value.

Table 5. Control_1 - control and status register 1 (address 00h) bit description

Bit Symbol Value Description Reference

7 TEST1 0[1] normal mode

must be set to logic 0 during normal operations Section 8.9

1 EXT_CLK test mode

6N 0

[2] unused

5STOP0

[1] RTC clock runs Section 8.10

1 RTC clock is stopped;

all RTC divider chain flip-flops are asynchronously set to logic 0;

the RTC clock is stopped (CLKOUT at 32.768 kHz is still available)

4N 0

[2] unused

3 TESTC 0 Power-On Reset (POR) override facility is disabled;

set to logic 0 for normal operation Section 8.11.1

1[1] Power-On Reset (POR ) override is enabled

2to0 N 000

[2] unused

Table 6. Control_2 - control and status register 2 (address 01h) bit description

Bit Symbol Value Description Reference

7to5 N 000

[1] unused

4TI_TP0

[2] INT is active when TF is active (subject to the status of TIE) Section 8.3.2.1

and

Section 8.8

1INT pulses active according to Table 7 (subject to the status of TIE);

Remark: note that if AF and AIE are active the n IN T will be

permanently active

3AF 0

[2] read: alarm flag inactive Section 8.3.2.1

write: alarm flag is cleared

1 read: alarm flag active

write: alarm flag remains unchanged

2TF 0

[2] read: timer flag inactive

write: timer flag is cleared

1 read: timer flag active

write: timer flag remains unchanged

1AIE 0

[2] alarm interrupt disabled

1 alarm interrupt enabled

0TIE 0

[2] timer interrupt disabled

1 timer interrupt enabled

Product data sheet Rev. 2 — 28 July 2010 8 of 43

NXP Semiconductors PCF85163

Real-ti m e clo c k an d ca len d ar

8.3.2.1 Interrupt output

Bits TF and AF: When an alarm occurs, AF is set to logic 1. Similarly, at the end of a

timer countdown, TF is set to logic 1. These bits maintain their value until overwritten

using the interface. If both timer and alarm interrupts are required in the applicatio n, the

source of the interrupt can be de termined by read ing these bit s. To prevent one flag being

overwritten while clearing another, a logic AND is performed during a write access.

Bits TIE and AIE: These bits activate or deactivate the generation of an inte rrupt when

TF or AF is asserted, respectively. The interrupt is the logical OR of these two conditions

when both AIE and TIE are set .

Countdown timer interrupts: The pulse generator for the count down timer interrupt uses

an internal clock and is dependent on the selected source clock for the countdown timer

and on the countdown value n. As a consequence, the width of the interrupt pulse varies

(see Table 7).

[1] TF and INT become active simultaneously.

[2] n = loaded countdown value. Timer stops when n = 0.

When bits TIE and AIE are disabled, pin INT will remain high-impedance.

Fig 4. Interrupt scheme

013aaa087

COUNTDOWN COUNTER

AF: ALARM

FLAG

CLEAR

SET

to interface:

read AF

TF: TIMER

CLEAR

SET

PULSE

GENERATOR 2

CLEAR

TRIGGER

TIE

INT

from interface:

clear TF

from interface:

clear AF

set alarm

flag AF

to interface:

read TF

TI_TP

AIE

e.g. AIE

Table 7. INT operation (bit TI _TP = 1)[1]

Source clock (Hz) INT period (s)

n=1

[2] n>1

[2]

4096 1⁄8192 1⁄4096

64 1⁄128 1⁄64

11⁄64 1⁄64

1⁄60 1⁄64 1⁄64

Product data sheet Rev. 2 — 28 July 2010 9 of 43

NXP Semiconductors PCF85163

Real-ti m e clo c k an d ca len d ar

8.4 T ime and date registers

The majority of the re gis te rs ar e co de d in th e BCD for m at to simp lify ap plic at ion use .

8.4.1 Register VL_seconds

[1] Start-up value.

8.4.1.1 Voltage-low detector and clock monitor

The PCF85163 has an on-chip voltage-low detector (see Figure 5). When VDD drops

below Vlow, bit VL in the VL_seconds register is set to indicate that the integrity of the

clock information is no longer guaranteed. The VL flag can only be cleared by using the

interface.

Table 8. VL_seconds - seconds an d clock integrity status register (address 02h) bit

description

Bit Symbol Value Place value Description

7 VL 0 - clock integrity is guaranteed

1[1] - integrity of the clock information is not guara nteed

6 t o 4 SECONDS 0 to 5 ten’s place actual seconds coded in BCD format, see Table 9

3 to 0 0 to 9 unit place

Ta ble 9. Seconds coded in BCD format

Seconds val ue in

decimal Upper-digit (ten’s place) Digit (unit place)

Bit 6 Bit 5 Bit 4 Bit 3 Bit 2 Bit 1 Bit 0

00 0000000

01 0000001

02 0000010

: :::::::

09 0001001

10 0010000

: :::::::

58 1011000

59 1011001

Fig 5. Voltage-low detection

VL set

normal power

operation

period of battery

operation

VDD

Vlow

mgr887

Product data sheet Rev. 2 — 28 July 2010 10 of 43

NXP Semiconductors PCF85163

Real-ti m e clo c k an d ca len d ar

The VL flag is intended to detect the situation when VDD is decr easing slowly, for example

under battery operation. Should the oscillator stop or VDD reach Vlow before power is

re-asserted, then the VL flag is set. This will indicate that the time may be corrupted.

8.4.2 Register Minutes

8.4.3 Register Hours

8.4.4 Register Days

[1] The PCF85163 compensates for leap years by adding a 29th day to February if the year counter contains a

value which is exactly divisible by 4, including the year 00.

8.4.5 Register Weekdays

Table 10. Minutes - minutes register (address 03h) bit description

Bit Symbol Value Place value Description

7 - - - unused

6 to 4 MINUTES 0 to 5 ten’s place actual minutes coded in BCD format

3 to 0 0 to 9 unit place

Table 11. Hours - hours register (add ress 04h) bit description

Bit Symbol Value Place value Description

7 to 6 - - - unused

5 to 4 HOURS 0 to 2 ten’s place actual hours coded in BCD format

3to0 0to9 unit place

Table 12. Days - days register (addr ess 05 h) bit description

Bit Symbol Value Place value Description

7 to 6 - - - unused

5to4 DAYS

[1] 0 to 3 ten’s place actual day coded in BCD format

3to0 0to9 unit place

Table 13. Weekdays - weekdays register (addres s 06h ) bit de scription

Bit Symbol Value Description

7 to 3 - - unused

2 t o 0 WEEKDAYS 0 to 6 actual weekday values, see Table 14

Product data sheet Rev. 2 — 28 July 2010 11 of 43

NXP Semiconductors PCF85163

Real-ti m e clo c k an d ca len d ar

[1] Definition may be re-assigned by the user.

8.4.6 Register Century_months

[1] This bit may be re-assigned by the user.

[2] This bit is toggled when the register Years overflows from 99 to 00.

Ta ble 14. Weekday assignments

Day[1] Bit

210

Sunday 0 0 0

Monday 0 0 1

Tuesday 0 1 0

Wednesday 0 1 1

Thursday 1 0 0

Friday 1 0 1

Saturday110

Table 15. Century_months - centu ry flag and months register (a ddress 07h) bit descriptio n

Bit Symbol Value Place value Description

[1] 0[2] - indicates the century is x

1 - indicates the century is x + 1

6 to 5 - - - unused

4 MONTHS 0 to 1 ten’s place actual month coded in BCD format, see Table 16

3 to 0 0 to 9 unit place

Table 16. Month assignments in BCD format

Month Upper-digit

(ten’s place) Digit (unit place)

Bit 4 Bit 3 Bit 2 Bit 1 Bit 0

January 0 0 0 0 1

February 0 0 0 1 0

March 0 0 0 1 1

April00100

May00101

June00110

July00111

August01000

September 0 1 0 0 1

October10000

November10001

December10010

Product data sheet Rev. 2 — 28 July 2010 12 of 43

NXP Semiconductors PCF85163

Real-ti m e clo c k an d ca len d ar

8.4.7 Register Years

[1] When the register Years overflows from 99 to 00, the century bit C in the register Century_months is

toggled.

8.5 Setting and reading the time

Figure 6 shows the data flow and data dependencies starting from the 1 Hz clock tick.

During read/write operations, the time counting circuits (memory locations 02h through

08h) are blocked.

This prevents

•Faulty reading of the clock and calenda r duri ng a carry con d itio n

•Incrementing the time registers, during the read cycle

After this read/write access is completed, the time circuit is released again and any

pending request to increment the time counters that occurred during the read access is

serviced. A maximum of 1 request can be stored; therefore, all accesses must be

completed withi n 1 se con d (s ee Figure 7).

Table 17. Years - years register (08h) bit description

Bit Symbol Value Place value Description

7 t o 4 YEARS 0 to 9 ten’s place actual year coded in BCD format[1]

3to0 0to9 unit place

Fig 6. Data flow for the time function

013aaa09

1 Hz tick

WEEKDAY

SECONDS

MINUTES

HOURS

DAYS

LEAP YEAR

CALCULATION

MONTHS

YEARS

Product data sheet Rev. 2 — 28 July 2010 13 of 43

NXP Semiconductors PCF85163

Real-ti m e clo c k an d ca len d ar

As a consequence of this method, it is very important to make a read or write access in

one go, that is, setting or reading seconds th roug h to ye ars sho uld be made in on e single

access. Failing to comply with this method could result in the time becoming corrupted.

As an example, if the time (seconds through to hours) is set in one access and then in a

second access the date is set, it is possible that the time may increment between the two

accesses. A similar pr ob lem exists when reading. A roll over may occur be twe e n re ad s

thus giving the minutes from one moment and the hours from the next.

Recommended method for reading the time:

1. Send a START condition and the slave address for write (A2h).

2. Set the address pointer to 2 (VL_seconds) by sending 02h.

3. Send a RESTART condition or STOP followed by START.

4. Send the slave address for read (A3h).

5. Read VL_seconds.

6. Read Minutes.

7. Read Hours.

8. Read Days.

9. Read Weekdays.

10. Read Century_months.

11. Read Years.

12. Send a STOP condition.

Fig 7. Access time for read/write operations

t < 1 s

013aaa21

SLAVE ADDRESS DATA STOPDATA

START

Product data sheet Rev. 2 — 28 July 2010 14 of 43

NXP Semiconductors PCF85163

Real-ti m e clo c k an d ca len d ar

8.6 Alarm registers

8.6.1 Register Minute_alarm

[1] Default value.

8.6.2 Register Hour_alarm

[1] Default value.

8.6.3 Register Day_alarm

[1] Default value.

8.6.4 Register Weekday_alarm

[1] Default value.

Table 18. Minute_alarm - minute alarm register (address 09h) bit description

Bit Symbol Value Place value Description

7 AE_M 0 - minute alarm is enabled

1[1] - minute alarm is disabled

6 to 4 MINUTE_ALARM 0 to 5 ten’s place minute alarm information coded in BCD

format

3 to 0 0 to 9 unit place

Table 19. Hour_alarm - hour alarm register (add ress 0Ah) bit description

Bit Symbol Value Place value Description

7 AE_H 0 - hour alarm is enabled

1[1] - hour alarm is disabled

6 - - - unused

5 to 4 HOUR_ALARM 0 to 2 ten’s place hour alarm information coded in BCD

format

3 to 0 0 to 9 unit place

Table 20. Day_alarm - day alarm regis t er (address 0Bh) bit descrip tion

Bit Symbol Value Place value Description

7 AE_D 0 - day alarm is enabled

1[1] - day alarm is disabled

6 - - - unused

5 t o 4 DAY_ALARM 0 to 3 ten’s place day alarm information coded in BCD

format

3 to 0 0 to 9 unit place

Table 21. Weekday_alarm - weekday alarm register (address 0Ch) bit description

Bit Symbol Value Description

7 AE_W 0 weekday alarm is enabled

1[1] weekday alarm is disabled

6 to 3 - - unused

2 to 0 WEEKDAY_ALARM 0 to 6 weekday alarm information coded in BCD format

Product data sheet Rev. 2 — 28 July 2010 15 of 43

NXP Semiconductors PCF85163

Real-ti m e clo c k an d ca len d ar

8.6.5 Alarm flag

By clearing the alarm enable bit (AE_x) of one or more of the alarm registers, the

corresponding alarm condition(s) are active. When an alarm occurs, AF is set to logic 1.

The asserted AF can be used to generate an interrupt (INT). The AF is cleared using the

interface.

The registers at addresses 09 h through 0Ch contain alarm information. When one or

more of these registers is loaded with minute, hour, day or weekday, and its

corresponding AE_x is logic 0, then that information is compared with the current minute,

hour, day, and weekday. When all enabled comparisons first match, the alarm flag (AF in

The generation of interrupts from the alarm function is controlled via bit AIE. If bit AIE is

enabled, the INT pin follows the condition of bit AF. AF will remain set until cleared by the

interface. Once AF has been cleared, it will only be set again when the time increment s to

match the alarm con dition once more . Alarm re giste rs which have their AE_x b it at logic 1

are ignored.

8.7 Register CLKOUT_control and clock output

Frequencies of 32.768 kHz (default), 1.024 kHz, 32 Hz, and 1 Hz can be generated for

use as a system clock, microcontroller clock, input to a charge pump, or for calibratio n of

the oscillator.

(1) O nly when all enabled alarm settings are matching.

It’s only on increment to a matched case that the alarm flag is set, see Section 8.6.5.

Fig 8. Alarm function bloc k dia g ra m

013aaa088

WEEKDAY ALARM

AE_W

WEEKDAY TIME

DAY ALARM

AE_D

DAY TIME

HOUR ALARM

AE_H

HOUR TIME

MINUTE ALARM

AE_M

MINUTE TIME

check now signal

set alarm flag AF (1)

AE_M = 1

example

Product data sheet Rev. 2 — 28 July 2010 16 of 43

NXP Semiconductors PCF85163

Real-ti m e clo c k an d ca len d ar

[1] Default value.

8.8 T imer function

The 8-bit countdown timer at address 0Fh is controlled by the Timer_control register at

address 0Eh. The Time r_control register determines one of 4 source clock frequencies for

the timer (4.096 Hz, 6 4 Hz, 1 Hz, or 1⁄60 Hz) and enables or disables the timer. The timer

counts down from a software-loaded 8-bit binary value. At the end of every countdown,

the timer sets the timer flag TF. The TF may only be cleared by using the interface. The

asserted TF can be used to generate an interrupt on pin INT. The interrupt may be

generated as a pulsed signal every countdown period or as a permanently active signal

which follows the state of TF. Bit TI_TP is used to control this mode selection. When

reading the timer, the current countdown value is returned.

8.8.1 Register Timer_control

[1] Default value.

[2] These bits determine the source clock for the countdown timer; when not in use, TD[1:0] should be set to

1⁄60 Hz for power saving.

Ta ble 22. CLKOUT_control - CLKOUT contro l register (address 0Dh) bit description

Bit Symbol Value Description

7 FE 0 the CLKOUT output is inhibited and CLKOUT output is

set to logic 0

1[1] the CLKOUT output is activated

6 to 2 - - unused

1 to 0 FD[1:0] frequency output at pin CLKOUT

00[1] 32.768 kHz

01 1.024 kHz

10 32 Hz

11 1 Hz

Table 23. Timer_control - timer control register (address 0Eh) bit description

Bit Symbol Value Description

7TE 0

[1] timer is disabled

1 timer is enabled

6 to 2 - - unused

1 to 0 TD[1:0] timer source clock frequency select[2]

00 4.096 kHz

01 64 Hz

10 1 Hz

11[2] 1⁄60 Hz

Product data sheet Rev. 2 — 28 July 2010 17 of 43

NXP Semiconductors PCF85163

Real-ti m e clo c k an d ca len d ar

8.8.2 Register Timer

The register Timer is an 8-bit binary countdown timer. It is ena bled or disa ble d via the

T imer_control register. The source clock for the timer is also selected by the T imer_contr ol

controlled via the register Control_2 (address 01h).

For accurate read back of the count down value, it is recommended to read the register

twice and check for consistent results, since it is not possible to freeze the countdown

timer counter during read back.

8.9 EXT_CLK test mode

A test mode is available which allows for on-board testing. In such a mode it is possib le to

set up test conditions and control the operation of the RTC.

The test mode is entered by setting bit TEST1 in register Control_1. Then pin CLKOUT

becomes an input. The test mode replaces the internal 64 Hz signal with the signal

applied to pin CLKOUT. Every 64 positive edges applied to pin CLKOUT will then

generate an increment of one second.

The signal applied to pin CLKOUT should have a minimum pulse width of 300 ns and a

maximum period of 1000 ns. The internal 64 Hz clock, now sourced from CLKOUT, is

divided down to 1 Hz by a 26divide chain called a prescaler. The prescaler can be set into

a known sta te by using bit STOP. When bit STOP is set, the prescaler is reset to 0 (STOP

must be cleared before the prescaler can operate again).

From a STOP condition, the first 1 second increment will take place after 32 positive

edges on CLKOUT. Thereafter, every 64 positive edges will cause a one second

increment.

Remark: Entry into EXT_CLK test mode is not synchronized to the internal 64 Hz clock.

When entering the test mode, no assumption as to the st ate of the presca ler can be made .

8.9.1 Operation example:

1. Set EXT_CLK test mode (Control_1, bit TEST1 = 1).

2. Set STOP (Control_1, bit STOP = 1).

3. Clear STOP (Control_1, bit STOP = 0).

4. Set time registers to desired value.

Table 24. Timer - timer register (address 0Fh) bit descrip tion

Bit Symbol Value Description

7 to 0 COUNTDOWN_TIMER[7:0] 00h to FFh countdown period in seconds:

where n is the countdown value

Table 25. Timer register bits value range

Bit

76543210

1286432168421

CountdownPeriod n

SourceClockFrequency

---------------------------------------------------------------

Product data sheet Rev. 2 — 28 July 2010 18 of 43

NXP Semiconductors PCF85163

Real-ti m e clo c k an d ca len d ar

5. Apply 32 clock pulses to CLKOUT.

6. Read time registers to see the fir st change.

7. Apply 64 clock pulses to CLKOUT.

8. Read time registers to see th e second change.

Repeat steps 7 and 8 for additional increments.

8.10 STOP bit function

The function of the STOP bit is to allow for accurate starting of the t ime circuits. The ST OP

bit function will cause the upper part of the prescaler (F2 to F14) to be held in reset and

thus no 1 Hz ticks will be generated (see Figure 9). The time circuits can then be set and

will not increment until the STOP bit is released (see Figure 10 and Table 26).

The STOP bit function will not affect the output of 32.768 kHz on CLKOUT, but will stop

the generation of 1.024 kHz, 32 Hz, and 1 Hz.

The lower two stages of the prescaler (F0 and F1) are not reset; and because the I2C-bus

is asynchronous to the crystal oscillator, the accuracy of re-starting the time circuits will be

between zero and one 8.192 kHz cycle (see Figure 10).

Fig 9. STOP bit functional diagram

013aaa08

OSCILLATOR

32768 Hz

16384 Hz

OSCILLATOR STOP

DETECTOR

F0F1F13

RESET

F14

RESET

2 Hz

1024 Hz

32 Hz

1 Hz tick

STOP

CLKOUT source

reset

8192 Hz

4096 Hz

32768 Hz

1 Hz

Fig 10. STOP bit release timing

001aaf91

8192 Hz

stop released

0 μs to 122 μs

Product data sheet Rev. 2 — 28 July 2010 19 of 43

NXP Semiconductors PCF85163

Real-ti m e clo c k an d ca len d ar

[1] F0 is clocked at 32.768 kHz.

The first increment of the time circuit s is betwee n 0.507813 s and 0.507935 s after ST OP

bit is released. The uncertainty is caused by the prescaler bits F0 and F1 not being reset

(see Table 26) and th e un kn ow n state of the 32 kHz clock.

8.11 Reset

The PCF85163 includes an internal reset circuit which is active whenever the oscillator is

stopped. In the reset state the I2C-bus logic is initialized including the address pointer an d

all registers are set acco r din g to Table 27. I2C-bus com m u nic atio n is not possib le du rin g

reset.

Table 26. First increm ent of time circuits after STOP bit release

Bit Prescaler bits [1] 1Hz tick Time Comment

STOP F0F1-F2 to F14 hh:mm:ss

Clock is running normally

01-0 0001 1101 0100

12:45:12 prescaler counting normally

STOP bit is activated by user. F0F1 are not reset and values can not be predicted externally

XX-0 0000 0000 0000

12:45:12 prescaler is reset; time circuits are frozen

New time is set by user

XX-0 0000 0000 0000

08:00:00 prescaler is reset; time circuits are frozen

STOP bit is released by user

XX-0 0000 0000 0000

08:00:00 prescaler is now running

XX-1 0000 0000 0000

08:00:00 -

XX-0 1000 0000 0000

08:00:00 -

XX-1 1000 0000 0000

08:00:00 -

11-1 1111 1111 1110

08:00:00 -

00-0 0000 0000 0001

08:00:01 0 to 1 transition of F14 increments the time circuits

10-0 0000 0000 0001

08:00:01 -

11-1 1111 1111 1111

08:00:01 -

00-0 0000 0000 0000

08:00:01 -

10-0 0000 0000 0000

08:00:01 -

11-1 1111 1111 1110

08:00:01 -

00-0 0000 0000 0001

08:00:02 0 to 1 transition of F14 increments the time circuits

013aaa076

0.507813 to 0.507935 s

1.000000 s

Product data sheet Rev. 2 — 28 July 2010 20 of 43

NXP Semiconductors PCF85163

Real-ti m e clo c k an d ca len d ar

[1] Registers marked x are undefined at power-up and unchanged by subsequent resets.

8.11.1 Power-On Reset (POR) override

The POR duration is directly related to the crystal oscillator start-up time. Due to the long

start-up times experienced by these types of circuits, a mechanism has been built in to

disable the POR and he nce speed up on-board test of the device. The setting of this

mode requires th at the I2C-bus pins, SDA and SCL, are toggled in a specific order as

shown in Figure 11. All timings are required minimums.

Once the override mode has been entered, the device immediately stops, being reset,

and normal operation may commence, i.e., entry into the EXT _CLK test mode via I2C-bus

access. The override mode may be cleare d by writing logic 0 to TESTC. TESTC must be

set to logic 1 before re-entry into the override mode is possible. Setting TESTC to logic 0

during normal operation has no effect, except to prevent entry into the POR override

mode.

Table 27. Register reset values[1]

Address Register name Bit

76543210

00hControl_1 00001000

01hControl_2 00000000

02hVL_seconds 1xxxxxxx

03hMinutes xxxxxxxx

04hHours xxxxxxxx

05hDays xxxxxxxx

06hWeekdays xxxxxxxx

07hCentury_monthsxxxxxxxx

08hYears xxxxxxxx

09hMinute_alarm 1xxxxxxx

0AhHour_alarm 1xxxxxxx

0BhDay_alarm 1xxxxxxx

0ChWeekday_alarm1xxxxxxx

0DhCLKOUT_control1xxxxx00

0EhTimer_control0xxxxx11

0FhTimer xxxxxxxx

Fig 11. POR override sequence

mgm66

SCL

500 ns 2000 ns

SDA

8 ms

override active

power-on

Product data sheet Rev. 2 — 28 July 2010 21 of 43

NXP Semiconductors PCF85163

Real-ti m e clo c k an d ca len d ar

9. Characteristics of the I2C-bus

The I2C-bus is for bidirectional, two-line communication between different ICs or modules.

The two lines are a Serial DAt a line (SDA) and a Serial Clock Line (SCL). Both lines must

be connected to a positi ve supply via a pull-up resistor. Data transfer may be initiated only

when the bus is not busy.

9.1 Bit transfer

One data b it is transferred durin g each clock pulse . The data on th e SDA line must remain

stable during the HIGH period of the clock pulse, as changes in the dat a line at this time

will be interpreted as a control signal (see Figure 12).

9.2 START and STOP conditions

Both data and clock lines remain HIGH when the bus is not busy.

A HIGH-to-LOW transition of the dat a line while the clock is HIGH is defined as the ST AR T

condition - S.

A LOW-to-HIGH transition of the data line while the clock is HIGH is defined as the STOP

condition - P (see Figure 13).

9.3 System configuration

A device generating a message is a transmitter; a device receiving a message is a

receiver. The device that controls the message is the master; and the devices which are

controlled by the ma ste r ar e th e sla ves (see Figure 14).

Fig 12. Bit transfer

mbc62

data line

stable;

data valid

change

of data

allowed

SDA

SCL

Fig 13. Definition of START and STOP condition s

mbc62

SDA

SCL

STOP condition

SDA

SCL

START condition

Product data sheet Rev. 2 — 28 July 2010 22 of 43

NXP Semiconductors PCF85163

Real-ti m e clo c k an d ca len d ar

9.4 Acknowledge

The number of data bytes transf er re d be tween the START and STOP conditions from

transmitter to receiver is unlimited. Each byte of eight bits is followe d by an acknowledge

cycle.

•A slave receiver, which is addressed, must generate an acknowledge after the

reception of each byte.

•Also a master receiver must gener ate an acknowle dge after the rece ption of each

byte that has been clocked out of the slave transmitter.

•The device that acknowledges must pull-down the SDA line during the acknowledge

clock pulse, so that the SDA line is stable LOW during the HIGH period of the

acknowledge related clock pulse (set-up and hold times must be taken into

consideration).

•A master receiver must signal an end of data to the transmitter by not generating an

acknowledge on the last byte tha t has be en clocked out of the slave. In this event the

transmitter must leave the data line HIGH to enable the master to generate a STOP

condition.

Acknowledgement on the I2C-bus is shown in Figure 15.

Fig 14. Syste m configuration

mga80

SDA

SCL

MASTER

TRANSMITTER/

RECEIVER

MASTER

TRANSMITTER

SLAVE

TRANSMITTER/

RECEIVER

SLAVE

RECEIVER

MASTER

TRANSMITTER/

RECEIVER

Fig 15. Acknowled gement on the I2C-bus

mbc60

START

condition

9821

clock pulse for

acknowledgement

not acknowledge

acknowledge

data output

by transmitter

data output

by receiver

SCL from

master

Product data sheet Rev. 2 — 28 July 2010 23 of 43

NXP Semiconductors PCF85163

Real-ti m e clo c k an d ca len d ar

9.5 I2C-bus protocol

9.5.1 Addressing

Before any data is transmitted on the I2C-bus, the device which should respond is

addressed first. The addressing is always carried out with the first byte transmitted after

the start procedure .

The PCF85163 acts as a slave receive r or slave transmitter. Therefore the clock signal

SCL is only an input signal, but the data signal SDA is a bidirectional line.

Two slave addresses are reserved for the PCF85163:

Read: A3h (10100011)

Write: A2h (10100010)

The PCF85163 slave address is illustrated in Figure 16.

9.5.2 Clock and calendar READ or WRITE cycles

The I2C-bus configuration for the different PCF85163 READ and WRITE cycles is shown

in Figure 17, Figure 18, and Figure 19. The register address is a 4-bit value that defines

which register is to be accessed next. The upper four bits of the register address are not

used.

Fig 16. Slave address

mce18

1 0 1 0 0 0 1 R/W

group 1 group 2

Fig 17. Master transmits to slave receiver (WRITE mode)

S0ASLAVE ADDRESS REGISTER ADDRESS A ADATA P

acknowledgement

from slave

acknowledgement

from slave

acknowledgement

from slave

R/W

auto increment

memory register address

013aaa34

n bytes

Product data sheet Rev. 2 — 28 July 2010 24 of 43

NXP Semiconductors PCF85163

Real-ti m e clo c k an d ca len d ar

(1) At this moment master transmitter becomes master receiver and PCF85163 slave receiver becomes slave transmitter.

Fig 18. Master reads after setting register addre ss (write register address; READ d ata)

S0A

SLAVE ADDRESS REGISTER ADDRESS A A

R/W

DATA

013aaa041

auto increment

memory register address

last byte

R/W

n bytes

(1)

acknowledgement

from slave

acknowledgement

from slave

acknowledgement

from slave

acknowledgement

from slave

no acknowledgement

from master

auto increment

memory register address

SLAVE ADDRESS

DATA

Fig 19. Master reads slave immediately after first byte (READ mode)

S1A

SLAVE ADDRESS DATA A1DATA

acknowledgement

from slave

acknowledgement

from master

no acknowledgement

from master

R/W

auto increment

013aaa347

auto increment

n bytes last byte

Product data sheet Rev. 2 — 28 July 2010 25 of 43

NXP Semiconductors PCF85163

Real-ti m e clo c k an d ca len d ar

10. Internal circuitry

Fig 20. Device diode protection diagram

013aaa042

SDA

SCL

INT

CLKOUT

OSCO

OSCI

PCF85163

Product data sheet Rev. 2 — 28 July 2010 26 of 43

NXP Semiconductors PCF85163

Real-ti m e clo c k an d ca len d ar

11. Limiting values

[1] Pass level; Human Body Model (HBM) according to Ref. 5 “JESD22-A114”.

[2] Pass level; Machine Model (MM), according to Ref. 6 “JESD22-A115”.

[3] Pass level; Charged-Device Model (CDM), according to Ref. 7 “JESD22-C101”.

[4] Pass level; latch-up testing, according to Ref. 8 “JESD78” at maximum ambient temperature (Tamb(max)).

[5] According to the NXP store and transport requirements (see Ref. 10 “NX3-00092”) the devices have to be

stored at a temperature of +8 °C to +45 °C and a humidity of 25 % to 75 %. For long term storage products

deviant conditions are described in that document.

Table 28. Limiting values

In accordance with the Absolute Maximum Rating System (IEC 60134).

Symbol Parameter Conditions Min Max Unit

VDD supply voltage −0.5 +6.5 V

IDD supply current −50 +50 mA

VIinput voltage on pins SCL, SDA, and

OSCI −0.5 +6.5 V

VOoutput voltage o n pins CLKOUT and INT −0.5 +6.5 V

IIinput current at any input −10 +10 mA

IOoutput current at any output −10 +10 mA

Ptot total power dissipation - 300 mW

VESD electrostatic discharge

voltage HBM [1] -±2000 V

MM [2] -±100 V

CDM [3]

SO8 (PCF85163T) - ±1500 V

TSSOP8 (PCF85163TS) - ±1750 V

Ilu latch-up current [4] -200mA

Tstg storage temperature [5] −65 +150 °C

Tamb ambient temp erature operating device −40 +85 °C

Product data sheet Rev. 2 — 28 July 2010 27 of 43

NXP Semiconductors PCF85163

Real-ti m e clo c k an d ca len d ar

12. Static characteristics

Table 29. Static characteristics

VDD = 1.8 V to 5.5 V; VSS =0V; T

amb =

−

C to +85

C; fosc = 32.768 kHz; quartz Rs=40k

; CL= 8 pF; unless otherw ise

specified.

Symbol Parameter Conditions Min Typ Max Unit

Supplies

VDD supply voltage interface inactive;

fSCL =0Hz;

Tamb =25°C

[1] 1.0 - 5.5 V

interface acti ve;

fSCL = 400 kHz [1] 1.8 - 5.5 V

clock data integrity;

Tamb =25°CVlow -5.5V

IDD supply current interface active

fSCL =400kHz --800μA

fSCL =100kHz --200μA

interface inactive (fSCL =0Hz);

CLKOUT disabled;

Tamb =25°C; see Figure 22

[2]

VDD = 5.0 V - 290 550 nA

VDD = 3.0 V - 270 500 nA

VDD = 2.0 V - 270 450 nA

interface inactive (fSCL =0Hz);

CLKOUT disabled;

Tamb =−40 °Cto +85°C; see Figure 22

[2]

VDD = 5.0 V - 325 750 nA

VDD = 3.0 V - 325 650 nA

VDD = 2.0 V - 360 600 nA

interface inactive (fSCL =0Hz);

CLKOUT enabled at 32 kHz;

Tamb =25°C; see Figure 22

[2]

VDD = 5.0 V - 580 1600 nA

VDD = 3.0 V - 420 1000 nA

VDD = 2.0 V - 360 800 nA

interface inactive (fSCL =0Hz);

CLKOUT enabled at 32 kHz;

Tamb =−40 °Cto +85°C; see Figure 22

[2]

VDD = 5.0 V - 700 1700 nA

VDD = 3.0 V - 490 1100 nA

VDD = 2.0 V - 420 900 nA

Inputs

VIL LOW-level input

voltage VSS -0.3V

DD V

VIH HIGH-level

input voltage 0.7VDD -V

DD V

Product data sheet Rev. 2 — 28 July 2010 28 of 43

NXP Semiconductors PCF85163

Real-ti m e clo c k an d ca len d ar

[1] For reliable oscillator start-up at power-on: VDD(po)min =V

DD(min) +0.3V.

[2] Timer source clock = 1⁄60 Hz, level of pins SCL and SDA is VDD or VSS.

[3] Tested on sample basis.

ILI input leakage

current VI=V

DD or VSS −10 +1μA

Ciinput

capacitance [3] --7pF

Outputs

IOL LOW-level

output current output sink current;

VOL =0.4V;

VDD =5V

on pin SDA 3 - - mA

on pin INT 1- - mA

on pin CLKOUT 1 - - mA

ILO output leakage

current VO=V

DD or VSS −10 +1μA

Voltage detector

Vlow low voltage Tamb =25°C;

sets bit VL; see Figure 5 -0.9-V

Table 29. Static characteristics …continued

VDD = 1.8 V to 5.5 V; VSS =0V; T

amb =

−

C to +85

C; fosc = 32.768 kHz; quartz Rs=40k

; CL= 8 pF; unless otherw ise

specified.

Symbol Parameter Conditions Min Typ Max Unit

VDD = 3 V; timer = 1 minute; CLKOUT disabled.

Fig 21. IDD as a function of temperature

T (°C)

−60 1006020−20−40 80400

001aal135

400

600

200

800

1000

IDD

(nA)

Product data sheet Rev. 2 — 28 July 2010 29 of 43

NXP Semiconductors PCF85163

Real-ti m e clo c k an d ca len d ar

Tamb =25°C; timer = 1 minute.

a. CLKOUT disabled

Tamb =25°C; timer = 1 minute.

b. fCLKOUT =32kHz

Fig 22. IDD as a function of VDD

VDD (V)

0 642

001aal133

400

600

200

800

1000

IDD

(nA)

VDD (V)

0 642

001aal134

400

600

200

800

1000

IDD

(nA)

Product data sheet Rev. 2 — 28 July 2010 30 of 43

NXP Semiconductors PCF85163

Real-ti m e clo c k an d ca len d ar

Tamb =25°C.

Fig 23. Frequency deviation as a function of VDD

02 6

−4

−2

mgr891

(V)

frequency

deviation

(ppm)

Product data sheet Rev. 2 — 28 July 2010 31 of 43

NXP Semiconductors PCF85163

Real-ti m e clo c k an d ca len d ar

13. Dynamic characteristics

[1] CL is a calculation of Ctrim and COSCO in series: .

[2] Unspecified for fCLKOUT = 32.768 kHz.

[3] All timing values are valid within the operating supply voltage at ambient temperature and referenced to VIL and VIH with an input voltage

swing of VSS to VDD.

[4] A detailed description of the I2C-bus specification is given in Ref. 12 “UM10204”.

[5] I2C-bus access time between two STARTs or between a START and a STOP condition to this device must be less than one second.

Table 30. Dynamic characteristics

VDD = 1.8 V to 5.5 V; VSS =0V; T

amb =

−

C to +85

C; fosc = 32.768 kHz; quartz Rs=40k

; CL= 8 pF; unless otherw ise

specified.

Symbol Parameter Conditions Min Typ Max Unit

Oscillator

COSCO capacitan c e on pi n O SCO 15 25 35 pF

Δfosc/fosc relative oscillator frequency variation ΔVDD =200mV;

Tamb =25°C-0.2-ppm

Quartz crystal parameters (f = 32.768 kHz)

Rsseries resistance - - 100 kΩ

CLload capacitance parallel [1] 7 - 12.5 pF

Ctrim trimmer capacitance external;

on pin OSCI 5- 25pF

CLKOUT output

δCLKOUT duty cycle on pin CLKOUT [2] -50-%

I2C-bus timing characteristics (see Figure 24)[3][4]

fSCL SCL clock frequency [5] - - 400 kHz

tHD;STA hold time (repeate d) START condition 0.6 - - μs

tSU;STA set-up time for a repeated START condition 0.6 - - μs

tLOW LOW period of the SCL clock 1.3 - - μs

tHIGH HIGH period of the SCL clock 0.6 - - μs

trrise time of both SDA and SCL signals - - 0.3 μs

tffall time of both SDA and SCL signals - - 0.3 μs

Cbcapacitive load for each bus line - - 400 pF

tSU;DAT data set-up time 100 - - ns

tHD;DAT data hold time 0 - - ns

tSU;STO set-up time for STOP condition 0.6 - - μs

tw(spike) spike pulse width on bus - - 50 ns

CLCtrim COSCO

⋅()

Ctrim COSCO

+()

-----------------------------------------

Product data sheet Rev. 2 — 28 July 2010 32 of 43

NXP Semiconductors PCF85163

Real-ti m e clo c k an d ca len d ar

14. Application information

Fig 24. I2C-bus timing waveforms

SDA

mga72

SDA

SCL

SU;STA

SU;STO

HD;STA

BUF

LOW

HD;DAT

HIGH

SU;DAT

Fig 25. Application di ag ram

013aaa04

SCL

SDA

VSS

OSCI

OSCO

CLOCK CALENDAR

PCF85163

SDA

SCL

MASTER

TRANSMITTER/

RECEIVER

VDD

SDA SCL

VDD

(I2C-bus)

R: pull-up resistor

R =

1 F

100 nF

Product data sheet Rev. 2 — 28 July 2010 33 of 43

NXP Semiconductors PCF85163

Real-ti m e clo c k an d ca len d ar

14.1 Quartz frequency adjustment

14.1.1 Method 1: fixed OSCI capacitor

By evaluating the average capacitance necessary for the application layout, a fixed

capacitor can be used. The freq uency is best measured via the 32.768 kHz signal

available after power-on at pin CLKOUT. The frequency tolerance depends o n the quartz

crystal tolerance, the capacitor tolerance, and the device-to-device tolerance (on aver age

±5 ppm). Average deviations of less than ±5 minutes per year can easily be achieved.

14.1.2 Method 2: OSCI trimmer

Using the 32.768 kHz signal available after power-on at pin CLKOUT, fast setting of a

trimmer is possible.

14.1.3 Method 3: OSCO output

Direct measurement of OSCO out (accounting for test probe capacitance).

Product data sheet Rev. 2 — 28 July 2010 34 of 43

NXP Semiconductors PCF85163

Real-ti m e clo c k an d ca len d ar

15. Package outline

Fig 26. Package outline SOT96-1 (SO8) of PCF85163T

UNIT A

max. A1A2A3bpcD

(1) E(2) (1)

ELL

pQZywv θ

REFERENCES

OUTLINE

VERSION EUROPEAN

PROJECTION ISSUE DATE

IEC JEDEC JEITA

inches

1.75 0.25

0.10

1.45

1.25 0.25 0.49

0.36

0.25

0.19

5.0

4.8

4.0

3.8 1.27 6.2

5.8 1.05 0.7

0.6

0.7

0.3 8

0.25 0.10.25

DIMENSIONS (inch dimensions are derived from the original mm dimensions)

Notes

1. Plastic or metal protrusions of 0.15 mm (0.006 inch) maximum per side are not included.

2. Plastic or metal protrusions of 0.25 mm (0.01 inch) maximum per side are not included.

1.0

0.4

SOT96-1

detail X

vMA

(A )

pin 1 index

076E03 MS-012

0.069 0.010

0.004

0.057

0.049 0.01 0.019

0.014

0.0100

0.0075

0.20

0.19

0.16

0.15 0.05 0.244

0.228

0.028

0.024

0.028

0.012

0.010.010.041 0.004

0.039

0.016

0 2.5 5 mm

scale

O8: plastic small outline package; 8 leads; body width 3.9 mm SOT96

-1

99-12-27

03-02-18

Product data sheet Rev. 2 — 28 July 2010 35 of 43

NXP Semiconductors PCF85163

Real-ti m e clo c k an d ca len d ar

Fig 27. Package outline SOT505-1 (TSSOP8) of PCF85163TS

UNIT A1

max. A2A3bpLHELpwyv

ceD(1) E(2) Z(1) θ

REFERENCES

OUTLINE

VERSION EUROPEAN

PROJECTION ISSUE DATE

IEC JEDEC JEITA

mm 0.15

0.05

0.95

0.80

0.45

0.25

0.28

0.15

3.1

2.9

3.1

2.9 0.65 5.1

4.7

0.70

0.35

6°

0°

0.1 0.10.10.94

DIMENSIONS (mm are the original dimensions)

Notes

1. Plastic or metal protrusions of 0.15 mm maximum per side are not included.

2. Plastic or metal protrusions of 0.25 mm maximum per side are not included.

0.7

0.4

SOT505-1 99-04-09

03-02-18

0.25

A2A1

(A3)

detail X

vMA

2.5 5 mm0

scale

TSSOP8: plastic thin shrink small outline package; 8 leads; body width 3 mm SOT505

-1

1.1

pin 1 index

Product data sheet Rev. 2 — 28 July 2010 36 of 43

NXP Semiconductors PCF85163

Real-ti m e clo c k an d ca len d ar

16. Handling information

All input and output pins are protected against ElectroStatic Discharge (ESD) under

normal handling. When handling Metal-Oxide Semiconductor (MOS) devices ensure that

all normal precautions are taken as described in JESD625-A, IEC61340-5 or equivalent

standards.

17. Soldering of SMD packages

This text provides a very brief insight into a complex technology. A more in-depth account

of soldering ICs can be found in Application Note AN10365 “Surface mount reflow

soldering description”.

17.1 Introduction to soldering

Soldering is one of the most common methods through which packages are attached to

Printed Circuit Boards (PCBs), to form electrical circuits. The soldered joint provides both

the mechanical and the electrical connection. There is no single soldering method that is

ideal for all IC packages. Wave soldering is often preferred when thro ugh-hole and

Surface Mount Devices (SMDs) are mixed on on e printed wiring board; however, it is not

suitable for fine pitch SMDs. Reflow soldering is ideal for the small pitches and high

densities that come with increased miniaturization.

17.2 Wave and reflow soldering

W ave soldering is a joining te chnology in which the joints are m ade by solder coming from

a standing wave of liquid solder. The wave soldering process is suitable for the following:

•Through-hole components

•Leaded or leadless SMDs, which are glued to the surface of the printed circuit board

Not all SMDs can be wave soldered. Packages with solder balls, and some leadless

packages which have solde r lands underneath the body, cannot be wave soldered. Also,

leaded SMDs with leads ha ving a pitch smaller than ~0.6 mm cannot be wave soldered,

due to an increased probability of bridging.

The reflow soldering process involves applying solder paste to a board, followed by

component placement and exposure to a temperatur e profile. Leaded packages,

packages with solder balls, and leadless packages are all reflow solderable.

Key characteristics in both wave and reflow soldering are:

•Board specifications, including the board finish, solder masks and vias

•Package footprints, including solder thieves and orientation

•The moisture sensitivity level of the packages

•Package placement

•Inspection and repair

•Lead-free soldering ve rsus SnPb soldering

Product data sheet Rev. 2 — 28 July 2010 37 of 43

NXP Semiconductors PCF85163

Real-ti m e clo c k an d ca len d ar

17.3 Wave soldering

Key characteristics in wave soldering are:

•Process issues, such as application of adhesive and flux, clinching of leads, board

transport, the solder wave parameters, and the time during which components are

exposed to the wave

•Solder bath specifications, including temperature and impurities

17.4 Reflow soldering

Key characteristics in reflow soldering are :

•Lead-free ve rsus SnPb soldering; note th at a lead-free reflow process usua lly leads to

higher minimum peak temperatures (see Figure 28) than a SnPb process, thus

reducing the process window

•Solder paste printing issues including smearing, release, and adjusting the process

window for a mix of large and small components on one board

•Reflow temperature profile; this profile includes preheat, reflow (in which the board is

heated to the peak temperature) an d cooling down. It is imperative that the peak

temperature is high enoug h for the solder to make reliable solder joint s (a solder paste

characteristic). In addition, the peak temperature must be low enough that the

packages and/or boards ar e not damaged. The peak temperature of the package

depends on p ackage thickness and volume and is classified in accordance with

Table 31 and 32

Moisture sensitivity precautions, as indicated on the packing, must be respected at all

times.

Studies have shown that small packages reach hig her temperatures during reflow

soldering, see Figure 28.

Table 31. SnPb eutectic process (from J-STD-0 20C)

Package thickness (mm) Package reflow temperature (°C)

Volume (mm3)

< 350 ≥ 350

< 2.5 235 220

≥ 2.5 220 220

Ta ble 32. Lead-free process (from J-STD-020C)

Package thickness (mm) Package reflow temperature (°C)

Volume (mm3)

< 350 350 to 2000 > 2000

< 1.6 260 260 260

1.6 to 2.5 260 250 245

> 2.5 250 245 245

Product data sheet Rev. 2 — 28 July 2010 38 of 43

NXP Semiconductors PCF85163

Real-ti m e clo c k an d ca len d ar

For further informa tion on temperature profiles, refer to Application Note AN10365

“Surface mount reflow soldering description”.

18. Abbreviations

MSL: Moisture Sensitivity Level

Fig 28. Temperature profiles for large and small components

001aac84

temperature

time

minimum peak temperature

= minimum soldering temperature

maximum peak temperature

= MSL limit, damage level

peak

temperature

Table 33. Abbreviations

Acronym Description

BCD Binary Coded Decimal

CMOS Co mplementary Metal Oxide Semiconductor

ESD ElectroSt atic Discharge

HBM Human Body Model

I2C Inter-Integrated Circuit

IC Integrated Circuit

LSB Least Significant Bit

MM Machine Model

MSB Most Significant Bit

MSL Moisture Sensitivity Level

PCB Printe d-Circuit Board

POR Power-On Reset

RTC Real-Time Clock

SCL Serial Clock Line

SDA Serial DAta line

SMD Surface Mount Device

Product data sheet Rev. 2 — 28 July 2010 39 of 43

NXP Semiconductors PCF85163

Real-ti m e clo c k an d ca len d ar

19. References

[1] AN10365 — Surface mount reflow soldering description

[2] IEC 60134 — Rating systems for electronic tubes and valves and analogous

semiconductor devices

[3] IEC 61340-5 — Protection of electronic devices from electrostatic phenomena

[4] IPC/JEDEC J-STD-020 — Moisture/Reflow Sensitivity Classification for

Nonhermetic Solid State Surface Mount Devices

[5] JESD22-A11 4 — Elec trostatic Discharge (ESD) Sensitiv ity Testing Human Body

Model (HBM)

[6] JESD22-A11 5 — Electrostatic Discharge (ESD) Sensitivity Testing Machine Model

(MM)

[7] JESD22-C101 — Field-Induced Charged-Device Mo del Test Method for

Electrostatic-Discharge-Withstand Thresholds of Microelectronic Components

[8] JESD78 — IC Latch-Up Test

[9] JESD625-A — Requirements for Handling Electrostatic-Discharge-Sensitive

(ESDS) Devices

[10] NX3-00092 — NXP store and transport requirements

[11] SNV-FA-01-02 — Marking Formats Integrated Circuits

[12] UM10204 — I2C-bus specification and user manual

Product data sheet Rev. 2 — 28 July 2010 40 of 43

NXP Semiconductors PCF85163

Real-ti m e clo c k an d ca len d ar

20. Revision history

Table 34. Revision history

Document ID Release date Data sheet status Change notice Supersedes

PCF85163 v.2 2 0100728 Product data sheet - PCF85163_1

Modifications: •The format of this data sheet has been redesigned to comply with the new identity guidelines

of NXP Semiconductors.

•Legal texts have been adapted to the new company name where appropriate.

•Inserted CDM value in Table 28

•Deleted inapplicable IOH value for pin CLKOUT in Table 29

PCF85163_1 20091112 Product data sheet - -

Product data sheet Rev. 2 — 28 July 2010 41 of 43

NXP Semiconductors PCF85163

Real-ti m e clo c k an d ca len d ar

21. Legal information

21.1 Data sheet status

[1] Please consult the most recently issued document before initiating or completing a design.

[2] The term ‘short data sheet’ is explained in section “Definitions”.

[3] The product status of de vice(s) descr ibed in th is document m ay have cha nged since thi s document w as publish ed and may di ffe r in case of multiple devices. The latest product status

information is available on the Internet at URL http://www.nxp.com.

21.2 Definitions

Draft — The document is a draft version only. The content is still under

internal review and subject to formal approval, which may result in

modifications or additions. NXP Semiconductors does not give any

representations or warranties as to the accuracy or completeness of

information included herein and shall have no liab ility for the consequences of

use of such information.

Short data sheet — A short data sheet is an extract from a full data sheet

with the same product type number(s) and tit le. A short data sh eet is intended

for quick reference only and shou ld not b e relied u pon to cont ain det ailed and

full information. For detailed and full informatio n see the relevant full dat a

sheet, which is available on request via the local NXP Semicond uctors sales

office. In case of any inconsistency or conflict with the short data sheet, the

full data sheet shall pre va il.

Product specificat ion — The information and data provided in a Product

data sheet shall define the specification of the product as agreed between

NXP Semiconductors and its customer, unless NXP Semiconductors and

customer have explicitly agreed otherwise in writing. In no event however,

shall an agreement be valid in which the NXP Semiconductors product is

deemed to off er functions and qualities beyon d those described in the

Product data sheet.

21.3 Disclaimers

Limited warr a nty and liability — Information in this document is believed to

be accurate and reliable. However, NXP Semiconductors does not give any

representations or warrant ies, expressed or implied, as to the accuracy or

completeness of such information and shall have no liability for the

consequences of use of such information.

In no event shall NXP Semiconductors be liable for any indirect, incidental ,

punitive, special or consequ ential damages (including - wit hout limitation - lost

profits, lost savings, business interruption, costs related to the removal or

replacement of any products or rework charges) whether or not such

damages are based on tort (including negligence), warranty, breach of

contract or any other legal theory.

Notwithstanding any damages that customer might incur for any reason

whatsoever, NXP Semiconductors’ aggreg ate and cumulative l iability towards

customer for the products described herein shall be limited in accordance

with the Terms and conditions of commercial sale of NXP Semiconductors.

Right to make changes — NXP Semiconductors reserves the right to make

changes to information published in this document, including without

limitation specifications and product descriptions, at any time and without

notice. This document supersedes and replaces all informa tion supplied prior

to the publication hereof .

Suitability for use — NXP Semiconductors products are not designed,

authorized or warranted to be suit able for use in life support, life-critical or

safety-critical systems or equipment, nor in applications where failure or

malfunction of an NXP Semiconductors pro duct can reasonably be expected

to result in perso nal injury, death or severe property or environmental

damage. NXP Semiconductors accepts no liab ility for inclusion and/or use of

NXP Semiconductors products in such equipment or application s and

therefore such inclusion and/or use is at the customer’s own risk.

Applications — Applications that are described herein for any of these

products are for illustrative purposes only. NXP Semiconductors makes no

representation or warranty that such applications will be suitable for the

specified use without further testing or modification.

Customers are responsible for the design and ope ration of their applications

and products using NXP Semiconductors product s, and NXP Semiconductors

accepts no liability for any assistance with applications or customer product

design. It is customer’s sole responsibility to determine whether the NXP

Semiconductors product is suit able and fit for the custome r’s applications and

products planned, as well as fo r the planned application and use of

customer’s third party customer(s). Custo mers should provide appropriate

design and operating safeguards to minimize the risks associated with their

applications and products.

NXP Semiconductors does not accept any liabili ty related to any default,

damage, costs or problem which is based on any weakness or default in the

customer’s applications or products, or the application or use by customer’s

third party custo m er(s). Customer is responsible for doing all necessary

testing for the customer’s applications and products using NXP

Semiconductors products in order to avoid a default of the applications and

the products or of the application or use by cust omer’s third party

customer(s). NXP does not accept any liability in this respect.

Limiting values — Stress above one or more limiting values (as defined in

the Absolute Maximum Ratings System of IEC 60134) will cause perman ent

damage to the device. Limiting values are stress ratings only and (proper)

operation of the device at these or any other conditions above those given in

the Recommended operating conditions section (if present) or the

Characteristics sections of this document is not warranted. Constant or

repeated exposure to limiting values will permanently and irreversibly affect

the quality and reliability of the device.

Terms and conditions of commercial sale — NXP Semiconductors

products are sold subject to the general terms and conditions of commercial

sale, as published at http://www.nxp.com/profile/terms, unless otherwise

agreed in a valid written individua l agreement. In case an individual

agreement is concluded only the ter m s and conditions of the respective

agreement shall apply. NXP Semiconductors hereby expressly objects to

applying the customer’s general terms and conditions with regard to the

purchase of NXP Semiconductors products by customer.

No offer to sell or license — Nothing i n this document may be interpreted or

construed as an of fer t o sell product s that is open for accept ance or the gr ant,

conveyance or implication of any license under any copyrights, patents or

other industrial or inte llectual property rights.

Export control — This document as well as the item(s) described herein

may be subject to export control regulatio ns. Export might require a prior

authorization from national authorities.

Document status[1][2] Product status[3] Definition

Objective [short] data sheet Development This document contain s data from the objective specification for product development.

Preliminary [short] dat a sheet Qualification This document contains data from the preliminary specification.

Product [short] data sheet Production This document contains the product specifica tion.

Product data sheet Rev. 2 — 28 July 2010 42 of 43

NXP Semiconductors PCF85163

Real-ti m e clo c k an d ca len d ar

Non-automotive qualified products — Unless this data sheet expressly

states that this specific NXP Semiconductors product is automotive qualified,

the product is not suitable for aut omo tive use. It i s neither qua lif ied nor test ed

in accordance with automotive testing or application requirements. NXP

Semiconductors accepts no liability for inclusion and/or use of

non-automotive qualified products in automotive equipment or applications.

In the event that customer uses the product for design-in and use in

automotive applications to automot ive specifications and standards, custome r

(a) shall use the product without NXP Semiconductors’ warranty of the

product for such au tomotive applications, use and specifications, and (b)

whenever customer uses the product for automotive applications beyond

NXP Semiconductors’ specifications such use shall be solely at customer’s

own risk, and (c) customer fully indemnifies NXP Semiconduct ors for an y

liability, damages or failed product claims result ing from customer design an d

use of the product for automotive applications beyond NXP Semiconductors’

standard warranty and NXP Semiconductors’ product specif ications.

21.4 Trademarks

Notice: All referenced b rands, produc t names, service names and trademarks

are the property of their respective ow ners.

I2C-bus — logo is a trademark of NXP B.V.

22. Contact information

For more information, please visit: http://www.nxp.com

For sales office addresses, please send an email to: salesaddresses@nxp.com

NXP Semiconductors PCF85163

Real-ti m e clo c k an d ca len d ar

For more information, please visit: http://www.nxp.com

For sales office addresses, please send an email to: salesaddresses@nxp.com

Date of release: 28 July 2010

Document identifier: PCF85163

Please be aware that important notices concerning this document and the product(s)

described herein, have been included in section ‘Legal information’.

23. Contents

1 General description. . . . . . . . . . . . . . . . . . . . . . 1

2 Features and benefits . . . . . . . . . . . . . . . . . . . . 1

3 Applications. . . . . . . . . . . . . . . . . . . . . . . . . . . . 1

4 Ordering information. . . . . . . . . . . . . . . . . . . . . 2

5 Marking. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 2

6 Block diagram . . . . . . . . . . . . . . . . . . . . . . . . . . 3

7 Pinning information. . . . . . . . . . . . . . . . . . . . . . 4

7.1 Pinning . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 4

7.2 Pin description . . . . . . . . . . . . . . . . . . . . . . . . . 4

8 Functional description . . . . . . . . . . . . . . . . . . . 5

8.1 CLKOUT output . . . . . . . . . . . . . . . . . . . . . . . . 5

8.2 Register organization . . . . . . . . . . . . . . . . . . . . 6

8.3 Control registers. . . . . . . . . . . . . . . . . . . . . . . . 7

8.3.1 Register Control_1 . . . . . . . . . . . . . . . . . . . . . . 7

8.3.2 Register Control_2 . . . . . . . . . . . . . . . . . . . . . . 7

8.3.2.1 Interrupt output . . . . . . . . . . . . . . . . . . . . . . . . . 8

8.4 Time and date registers . . . . . . . . . . . . . . . . . . 9

8.4.1 Register VL_seconds . . . . . . . . . . . . . . . . . . . . 9

8.4.1.1 Voltage-low detector and clock monitor . . . . . . 9

8.4.2 Register Minutes. . . . . . . . . . . . . . . . . . . . . . . 10

8.4.3 Register Hours . . . . . . . . . . . . . . . . . . . . . . . . 10

8.4.4 Register Days. . . . . . . . . . . . . . . . . . . . . . . . . 10

8.4.5 Register Weekdays. . . . . . . . . . . . . . . . . . . . . 10

8.4.6 Register Century_months. . . . . . . . . . . . . . . . 11

8.4.7 Register Years . . . . . . . . . . . . . . . . . . . . . . . . 12

8.5 Setting and reading the ti me. . . . . . . . . . . . . . 12

8.6 Alarm registers . . . . . . . . . . . . . . . . . . . . . . . . 14

8.6.1 Register Minute_alarm . . . . . . . . . . . . . . . . . . 14

8.6.2 Register Hour_alarm . . . . . . . . . . . . . . . . . . . 14

8.6.3 Register Day_alarm . . . . . . . . . . . . . . . . . . . . 14

8.6.4 Register Weekday_alarm . . . . . . . . . . . . . . . . 14

8.6.5 Alarm flag . . . . . . . . . . . . . . . . . . . . . . . . . . . . 15

8.7 Register CLKOUT_control and clock output. . 15

8.8 Timer function. . . . . . . . . . . . . . . . . . . . . . . . . 16

8.8.1 Register Timer_control . . . . . . . . . . . . . . . . . . 16

8.8.2 Register Timer . . . . . . . . . . . . . . . . . . . . . . . . 17

8.9 EXT_CLK test mode. . . . . . . . . . . . . . . . . . . . 17

8.9.1 Operation example: . . . . . . . . . . . . . . . . . . . . 17

8.10 STOP bit function . . . . . . . . . . . . . . . . . . . . . . 18

8.11 Reset . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 19

8.11.1 Power-On Reset (POR) override . . . . . . . . . . 20

9 Characteristics of the I2C-bus . . . . . . . . . . . . 21

9.1 Bit transfer . . . . . . . . . . . . . . . . . . . . . . . . . . . 21

9.2 START and STOP conditions . . . . . . . . . . . . . 21

9.3 System configuration . . . . . . . . . . . . . . . . . . . 21

9.4 Acknowledge . . . . . . . . . . . . . . . . . . . . . . . . . 22

9.5 I2C-bus protocol. . . . . . . . . . . . . . . . . . . . . . . 23

9.5.1 Addressing. . . . . . . . . . . . . . . . . . . . . . . . . . . 23

9.5.2 Clock and calendar READ or WRITE cycles . 23

10 Internal circuitry . . . . . . . . . . . . . . . . . . . . . . . 25

11 Limiting values . . . . . . . . . . . . . . . . . . . . . . . . 26

12 Static characteristics . . . . . . . . . . . . . . . . . . . 27

13 Dynamic characteristics. . . . . . . . . . . . . . . . . 31

14 Application information . . . . . . . . . . . . . . . . . 32

14.1 Quartz frequency adjustment. . . . . . . . . . . . . 33

14.1.1 Method 1: fixed OSCI capacitor. . . . . . . . . . . 33

14.1.2 Method 2: OSCI trimmer . . . . . . . . . . . . . . . . 33

14.1.3 Method 3: OSCO output . . . . . . . . . . . . . . . . 33

15 Package outline. . . . . . . . . . . . . . . . . . . . . . . . 34

16 Handling information . . . . . . . . . . . . . . . . . . . 36

17 Soldering of SMD packages. . . . . . . . . . . . . . 36

17.1 Introduction to soldering. . . . . . . . . . . . . . . . . 36

17.2 Wave and reflow soldering. . . . . . . . . . . . . . . 36

17.3 Wave soldering . . . . . . . . . . . . . . . . . . . . . . . 37

17.4 Reflow soldering . . . . . . . . . . . . . . . . . . . . . . 37

18 Abbreviations . . . . . . . . . . . . . . . . . . . . . . . . . 38

19 References. . . . . . . . . . . . . . . . . . . . . . . . . . . . 39

20 Revision history . . . . . . . . . . . . . . . . . . . . . . . 40

21 Legal information . . . . . . . . . . . . . . . . . . . . . . 41

21.1 Data sheet status. . . . . . . . . . . . . . . . . . . . . . 41

21.2 Definitions . . . . . . . . . . . . . . . . . . . . . . . . . . . 41

21.3 Disclaimers . . . . . . . . . . . . . . . . . . . . . . . . . . 41

21.4 Trademarks . . . . . . . . . . . . . . . . . . . . . . . . . . 42

22 Contact information . . . . . . . . . . . . . . . . . . . . 42

23 Contents . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 43