UC1625 - Unitrode Semiconductor - Datasheet.Directory

UC1625

UC2625

UC3625

11/97

Brushless DC Motor Controller

•Drives Power MOSFETs or Power

Darlingtons Directly

•50V Open Collector High--Side Drivers

•Latched Soft Start

•High--speed Current--Sense Amplifier with

Ideal Diode

•Pulse--by--Pulse and Average Current

Sensing

•Over--Voltage and Under--Voltage Protection

•Direction Latch for Safe Direction Reversal

•Tachometer

•Trimmed Reference Sources 30mA

•Programmable Cross--Conduction Protection

The UC1625 and UC3625 motor controller ICs integrate most of

the functions required for high-performance brushless DC motor

control into one package. When coupled with external power

MOSFETs or Darlingtons, these ICs perform fixed-frequency PWM

motor control in either voltage or current mode while implementing

closed loop speed control and braking with smart noise rejection,

safe direction reversal, and cross–conduction protection.

Although specified for operation from power supplies between 10V

and 18V, the UC1625 can control higher voltage power devices

with external level-shifting components. The UC1625 contains fast,

high-current push-pull drivers for low-side power devices and 50V

open-collector outputs for high-side power devices or level shifting

circuitry.

The UC1625 is characterized for operation over the military tem-

perature range of –55°C to +125°C, while the UC2625 is

characterized from –40°C to +105°C and the UC3625 is character-

ized from 0°Cto70°C.

(NOTE: ESD Protection to 2kV)

FEATURES DESCRIPTION

BLOCK DIAGRAM

UDG-92029-1

UC1625

UC2625

UC3625

ABSOLUTE MAXIMUM RATINGS

VCC Supply Voltage..............................+20V

Pwr VCC Supply Voltage ..........................+20V

PWMIn...................................–0.3 to 6V

E/A IN(+), E/A IN(–).........................–0.3 to 12V

ISENSE1, ISENSE2............................–1.3 to 6V

OV–Coast, Dir, Speed-In, SSTART, Quad Sel ......–0.3 to 8V

H1,H2,H3................................–0.3 to 12V

PU Output Voltage..........................–0.3 to 50V

PU Output Current ..................+200 mA continuous

PD Output Current ..................±

200 mA continuous

E/A Output Current ............................±

10 mA

ISENSE Output Current..........................-10mA

Tach Out Output Current........................±

10 mA

VREF Output Current ..................–50mAcontinuous

Operating Temperature Range UC1625......–55°C to 125°C

Operating Temperature Range UC2625......–40°C to 105°C

Operating Temperature Range UC3625.........0°Cto70°C

Note 1: Currents are positive into and negative out of the speci-

fied terminal.

Note 2: Consult Unitrode Integrated Circuits databook for infor-

mation regarding thermal specifications and limitations of

packages.

CONNECTION DIAGRAM

ELECTRICAL CHARACTERISTICS: Unless otherwise stated, these specifications apply for: TA=25°C; Pwr VCC =VCC =

12V; ROSC = 20k to VREF;COSC = 2nF; RTACH = 33k; CTACH = 10nF; and all outputs unloaded. TA=TJ.

PARAMETER TEST CONDITIONS MIN TYP MAX UNITS

Overall

Supply current Over Operating Range 14.5 30.0 mA

VCC Turn-On Threshold Over Operating Range 8.65 8.95 9.45 V

VCC Turn-Off Threshold Over Operating Range 7.75 8.05 8.55 V

Overvoltage/Coast

OV-Coast Inhibit Threshold Over Operating Range 1.65 1.75 1.85 V

OV-Coast Restart Threshold 1.55 1.65 1.75 V

OV-Coast Hysteresis 0.05 0.10 0.15 V

OV-Coast Input Current –10 –1 0 µA

Logic Inputs

H1, H2, H3 Low Threshold Over Operating Range 0.8 1.0 1.2 V

H1, H2, H3 High Threshold Over Operating Range 1.6 1.9 2.0 V

H1, H2, H3 Input Current Over Operating Range, to 0V -400 -250 –120 µA

Quad Sel, Dir Thresholds Over Operating Range 0.8 1.4 2.0 V

Quad Sel Hysteresis 70 mV

Dir Hysteresis 0.6 V

Quad Sel Input Current –30 50 150 µA

Dir Input Current –30 –1 30 µA

PWM Amp/Comparator

E/A In(+), E/A In(-) Input Current To 2.5V -5.0 -0.1 5.0 µA

PWM In Input Current To 2.5V 0 3 30 µA

Error Amp Input Offset 0V < VCOMMON-MODE < 3V –10 10 mV

Error Amp Voltage Gain 70 90 dB

E/A Out Range 0.25 3.50 V

SSTART Pull-up Current To 0V –16 –10 –5 µA

SSTART Discharge Current To 2.5V 0.1 0.4 3.0 mA

DIL-28 (TOP VIEW)

J or N PACKAGE

Note 3: This pinout applies to the SOIC (DW), PLCC (Q), and

LCC (L) packages (ie. pin 22 has the same function on all

packages.)

UC1625

UC2625

UC3625

PARAMETER TEST CONDITIONS MIN TYP MAX UNITS

SSTART Restart Threshold 0.1 0.2 0.3 V

Current Amp

Gain ISENSE1 = .3V, ISENSE2 = .5V to .7V 1.75 1.95 2.15 V/V

Current Amp (cont.)

Level Shift ISENSE1 = .3V, ISENSE2 = .3V 2.4 2.5 2.65 V

Peak Current Threshold ISENSE1 = 0V, Force ISENSE2 0.14 0.20 0.26 V

Over Current Threshold ISENSE1 = 0V, Force ISENSE2 0.26 0.30 0.36 V

ISENSE1,ISENSE2 Input Current To 0V –850 –320 0 µA

ISENSE1,ISENSE2 Offset Current To 0V ±2±12 µA

Range ISENSE1,ISENSE2 –1 2 V

Tachometer/Brake

Tach-Out High Level Over Operating Range, 10k to 2.5V 4.7 5 5.3 V

Tach-Out Low Level Over Operating Range, 10k to 2.5V 0.2 V

On Time 170 220 280 µs

On Time Change With Temp Over Operating Range 0.1 %

RC-Brake Input Current To 0V –4.0 –1.9 mA

Threshold to Brake, RC-Brake Over Operating Range 0.8 1.0 1.2 V

Brake Hysteresis, RC-Brake 0.09 V

Speed-In Threshold Over Operating Range 220 257 290 mV

Speed-In Input Current –30 –5 30 µA

Low-Side Drivers

Voh, -1mA, Down From VCC Over Operating Range 1.60 2.1

V Voh, -50mA, Down From VCC Over Operating Range 1.75 2.2 V

Vol, 1mA Over Operating Range 0.05 0.4 V

Vol, 50mA Over Operating Range 0.36 0.8 V

Rise/Fall Time 10% to 90% Slew Time, into 1nF 50 ns

High-Side Drivers

Vol, 1mA Over Operating Range 0.1 0.4 V

Vol, 50mA Over Operating Range 1.0 1.8 V

Leakage Current Output Voltage = 50V 25 µA

Fall Time 10% to 90% Slew Time, 50mA Load 50 ns

Oscillator

Frequency 40 50 60 kHz

Frequency Over Operating Range 35 65 kHz

Reference

Output Voltage 4.9 5.0 5.1 V

Output Voltage Over Operating Range 4.7 5.0 5.3 V

Load Regulation 0mA to -20mA Load –40 –5 mV

Line Regulation 10V to 18V VCC –10 –1 10 mV

Short Circuit Current Over Operating Range 50 100 150 mA

Miscellaneous

Output Turn-On Delay 1 µs

Output Turn-Off Delay 1 µs

ELECTRICAL CHARACTERISTICS (cont): Unless otherwise stated, these specifications apply for: TA=25°C; Pwr VCC =

VCC = 12V; ROSC = 20k to VREF;COSC = 2nF; RTACH = 33k; CTACH = 10nF; and all outputs unloaded. TA=TJ.

UC1625

UC2625

UC3625

PIN DESCRIPTIONS

Dir, Speed-In: The position decoder logic translates the

Hall signals and the Dir signal to the correct driver sig-

nals (PUs and PDs). To prevent output stage damage,

the signal on Dir is first loaded into a direction latch,

then shifted through a two-bit register.

As long as Speed-In is less than 250mV, the direction

latch is transparent. When Speed-In is higher than

250mV, the direction latch inhibits all changes in direc-

tion. Speed-In can be connected to Tach-Out through a

filter, so that the direction latch is only transparent when

the motor is spinning slowly, and has too little stored en-

ergy to damage power devices.

Additional circuitry detects when the input and output of

the direction latch are different, or when the input and

output of the shift register are different, and inhibits all

output drives during that time. This can be used to allow

the motor to coast to a safe speed before reversing.

The shift register guarantees that direction can't be

changed instantaneously. The register is clocked by the

PWM oscillator, so the delay between direction changes

is always going to be between one and two oscillator pe-

riods. At 40kHz, this corresponds to a delay of between

25µs and 50µs. Regardless of output stage, 25µs dead

time should be adequate to guarantee no overlap cross-

conduction. Toggling DIR will cause an output pulse on

Tach-Out regardless of motor speed.

E/A In(+), E/A In(-), E/A Out, PWM In: E/A In(+) and

E/A In(-) are not internally committed to allow for a wide

variety of uses. They can be connected to the ISENSE,to

Tach-Out through a filter, to an external command volt-

age, to a D/A converter for computer control, or to

another op amp for more elegant feedback loops. The

error amplifier is compensated for unity gain stability, so

E/A Out can be tied to E/A In(-) for feedback and major

loop compensation.

E/A Out and PWM In drive the PWM comparator. For

voltage-mode PWM systems, PWM In can be connected

to RC-Osc. The PWM comparator clears the PWM latch,

commanding the outputs to chop.

The error amplifier can be biased off by connecting E/A

In(-) to a higher voltage than E/A In(+). When biased off,

E/A Out will appear to the application as a resistor to

ground. E/A Out can then be driven by an external am-

plifier.

GND: All thresholds and outputs are referred to the GND

pin except for the PD and PU outputs.

H1, H2, H3: The three shaft-position sensor inputs con-

sist of hysteresis comparators with input pull-up

resistors. Logic thresholds meet TTL specifications and

can be driven by 5V CMOS, 12V CMOS, NMOS, or

open-collectors.

Connect these inputs to motor shaft position sensors

that are positioned 120 electrical degrees apart. If noisy

signals are expected, zener clamp and filter these inputs

with 6V zeners and an RC filter. Suggested filtering

components are 1k and 2nF. Edge skew in the filter is

not a problem, because sensors normally generate

modified Gray code with only one output changing at a

time, but rise and fall times must be shorter than 20µs

for correct tachometer operation.

Motors with 60 electrical degree position sensor coding

can be used if one or two of the position sensor signals

is inverted.

ISENSE1,ISENSE2,ISENSE:The current sense amplifier

has a fixed gain of approximately two. It also has a built-

in level shift of approximately 2.5 volts. The signal ap-

pearing on ISENSE is:

SENSE

=2.5V+(2*ABS(

SENSE1

–

SENSE2

))

ISENSE1 and ISENSE2 are interchangeable and can be

used as differential inputs. The differential signal applied

can be as high as ±0.5V before saturation.

If spikes are expected on ISENSE1 or ISENSE2, they are

best filtered by a capacitor from ISENSE to ground. Filter-

ing this way allows fast signal inversions to be correctly

processed by the absolute value circuit. The peak-

current comparator allows the PWM to enter a current-

limit mode with current in the windings never exceeding

approximately 0.2V/RSENSE. The over current compara-

tor provides a fail-safe shutdown in the unlikely case of

current exceeding 0.3V/RSENSE. Then, soft start is com-

manded, and all outputs are turned off until the high

current condition is removed. It is often essential to use

some filter driving ISENSE1 and ISENSE2 to reject extreme

spikes and to control slew rate. Reasonable starting val-

ues for filter components might be 250Ωseries resistors

and a 5nF capacitor between ISENSE1 and ISENSE2. Input

resistors should be kept small and matched to maintain

gain accuracy.

OV-Coast: This input can be used as an over-voltage

shutdown in put, as a coast input, or both.This input can

be driven by TTL, 5V CMOS, or 12V CMOS.

PDA, PDB, PDC: These outputs can drive the gates of

N-Channel power MOSFETs directly or they can drive

the bases of power Darlingtons if some form of current

limiting is used. They are meant to drive low-side power

devices in high-current output stages. Current available

from these pins can peak as high as 0.5A. These out-

puts feature a true totem-pole output stage. Beware of

exceeding IC power dissipation limits when using these

outputs for high continuous currents. These outputs pull

high to turn a “low-side” device on (active high).

UC1625

UC2625

UC3625

PIN DESCRIPTIONS (cont.):

PUA, PUB, PUC: These outputs are open-collector,

high-voltage drivers that are meant to drive high-side

power devices in high-current output stages. These are

active low outputs, meaning that these outputs pull low

to command a high-side device on. These outputs can

drive low-voltage PNP Darlingtons and P-channel MOS-

FETs directly, and can drive any high-voltage device

using external charge-pump techniques, transformer sig-

nal coupling, cascode level-shift transistors, or opto-

isolated drive.(See applications).

PWR VCC:This supply pin carries the current sourced

by the PD outputs. When connecting PD outputs directly

to the bases of power Darlingtons, the PWR VCC pin can

be current limited with a resistor. Darlington outputs can

also be "Baker Clamped" with diodes from collectors

back to PWR VCC. (See Applications)

Quad Sel: The IC can chop power devices in either of

two modes, referred to as “two-quadrant” (Quad Sel low)

and “four-quadrant” (Quad Sel high). When two-quadrant

chopping, the pull-down power devices are chopped by

the output of the PWM latch while the pull-up drivers re-

main on. The load will chop into one commutation diode,

and except for back-EMF, will exhibit slow discharge cur-

rent and faster charge current. Two-quadrant chopping

can be more efficient than four-quadrant.

When four-quadrant chopping, all power drivers are

chopped by the PWM latch, causing the load current to

flow into two diodes during chopping. This mode exhibits

better control of load current when current is low, and is

preferred in servo systems for equal control over accel-

eration and deceleration. The Quad Sel input has no

effect on operation during braking.

RC-Brake: Each time the Tach-Out pulses, the capacitor

tied to RC-Brake discharges from approximately 3.33V

down to 1.67V through a resistor. The tachometer pulse

width is approximately T = 0.67 RTCT, where RTand CT

are a resistor and capacitor from RC-Brake to ground.

Recommended values for RTare 10k to 500k, and rec-

ommended values for CTare 1nF to 100nF, allowing

times between 5µs and 10ms. Best accuracy and stabil-

ity are achieved with values in the centers of those

ranges.

RC-Brake also has another function. If RC-Brake pin is

pulled below the brake threshold, the IC will enter brake

mode. This mode consists of turning off all three high-

side devices, enabling all three low-side devices, and

disabling the tachometer. The only things that inhibit low-

side device operation in braking are low-supply, exceed-

ing peak current, OV-Coast command, and the PWM

comparator signal. The last of these means that if cur-

rent sense is implemented such that the signal in the

current sense amplifier is proportional to braking current,

the low-side devices will brake the motor with current

control. (See applications) Simpler current sense con-

nections will result in uncontrolled braking and potential

damage to the power devices.

RC-Osc: The UC3625 can regulate motor current using

fixed-frequency pulse width modulation (PWM). The RC-

Osc pin sets oscillator frequency by means of timing re-

sistor ROSC from the RC-Osc pin to VREF and capacitor

COSC from RC-Osc to Gnd. Resistors 10k to 100k and

capacitors 1nF to 100nF will work best, but frequency

should always be below 500kHz. Oscillator frequency is

approximately:

F=2/R

OSC

Additional components can be added to this device to

cause it to operate as a fixed off-time PWM rather than

a fixed frequency PWM, using the RC-Osc pin to select

the monostable time constant.

The voltage on the RC-Osc pin is normally a ramp of

about 1.2V peak-to-peak, centered at approximately

1.6V. This ramp can be used for voltage-mode PWM

control, or can be used for slope compensation in

current-mode control.

SSTART:Any time that VCC drops below threshold or the

sensed current exceeds the over-current threshold, the

soft-start latch is set. When set, it turns on a transistor

that pulls down on SSTART. Normally, a capacitor is con-

nected to this pin, and the transistor will completely

discharge the capacitor. A comparator senses when the

NPN transistor has completely discharged the capacitor,

and allows the soft-start latch to clear when the fault is

removed. When the fault is removed, the soft-start ca-

pacitor will charge from the on-chip current source.

SSTART clamps the output of the error amplifier, not al-

lowing the error amplifier output voltage to exceed

SSTART regardless of input.The ramp on RC-Osc can be

applied to PWM In and compared to E/A Out. With

SSTART discharged below 0.2V and the ramp minimum

being approximately 1.0V, the PWM comparator will

keep the PWM latch cleared and the outputs off. As

SSTART rises, the PWM comparator will begin to duty-

cycle modulate the PWM latch until the error amplifier

inputs overcome the clamp. This provides for a safe and

orderly motor start-up from an off or fault condition.

Tach-Out: Any change in the H1, H2, or H3 inputs loads

data from these inputs into the position sensor latches.

At the same time data is loaded, a fixed-width 5V pulse

is triggered on Tach-Out. The average value of the volt-

age on Tach-Out is directly proportional to speed, so this

output can be used as a true tachometer for speed feed-

back with an external filter or averaging circuit.

UC1625

UC2625

UC3625

The UC3625 inserts delays to prevent cross conduc-

tion due to overlapping drive signals. However, some

thought must always be given to cross conduction in

output stage design because no amount of dead time

can prevent fast slewing signals from coupling drive

to a power device through a parasitic capacitance.

The UC3625 contains input latches that serve as

noise blanking filters. These latches remain transpar-

ent through any phase of a motor rotation and latch

immediately after an input transition is detected.They

remain latched for two cycles of the PWM oscillator.

At a PWM oscillator speed of 20kHz, this corre-

sponds to 50µsto100µs of blank time which limits

maximum rotational speed to 100kRPM for a motor

with six transitions per rotation or 50kRPM for a mo-

tor with 12 transitions per rotation.

This prevents noise generated in the first 50µsofa

transition from propagating to the output transistors

and causing cross–conduction or chatter.

The UC3625 also contains six flip flops correspond-

ing to the six output drive signals. One of these flip

flops is set every time that an output drive signal is

turned on, and cleared two PWM oscillator cycles af-

ter that drive signal is turned off. The output of each

flip flop is used to inhibit drive to the opposing output.

(see below) In this way, it is impossible to turn on

driver PUA and PDA at the same time. It is also im-

possible for one of these drivers to turn on without

the other driver having been off for at least two PWM

oscillator clocks.

CROSS CONDUCTION PREVENTION

Whenever Tach-Out is high, the position latches are in-

hibited, such that during the noisiest part of the

commutation cycle, additional commutations are not pos-

sible. Although this will effectively set a maximum

rotational speed, the maximum speed can be set above

the highest expected speed, preventing false commuta-

tion and chatter.

VCC:This device operates with supplies between 10V

and 18V. Under-voltage lockout keeps all outputs off be-

low 7.5V, insuring that the output transistors never turn

on until full drive capability is available. Bypass VCC to

ground with an 0.1µF ceramic capacitor. Using a 10µF

electrolytic bypass capacitor as well can be beneficial in

applications with high supply impedance.

VREF:This pin provides regulated 5 volts for driving Hall-

effect devices and speed control circuitry. VREF will reach

+5V before VCC enables, ensuring that Hall-effect de-

vices powered from VREF will become active before the

UC3625 drives any output. Although VREF is current lim-

ited, operation over 30mA is not advised. For proper

performance VREF should be bypassed with at least a

0.1µF capacitor to ground.

PIN DESCRIPTIONS (cont.):

UC1625

UC2625

UC3625

TYPICAL CHARACTERISTICS:

0.001 0.01 0.1

100Hz

1kHz

10kHz

100kHz

1MHz

Rosc-30k

Rosc-10k

Rosc-100k

OscillatorFrequency

C(F)

OSC

µC(F)

OSC

0.001 0.01 0.1

1sµ

10 sµ

100 sµ

1ms

10ms

100ms

R -500k

R -100k

R -30k

R -10k

OnTime

C(F)

Oscillator Frequency vs COSC and ROSC Tachometer On Time vs RTand CT

Supply Current vs Temperature Soft Start Pull-Up Current vs Temperature

Soft Start Discharge Current vs Temperature

UC1625

UC2625

UC3625

POWER STAGE DESIGN:

The UC3625 is useful in a wide variety of applications,

including high-power in robotics and machinery. The

power output stages used in such equipment can take a

number of forms, according to the intended performance

and purpose of the system. Below are four different

power stages with the advantages and disadvantages of

each shown.

For high-frequency chopping, fast recovery circulating

diodes are essential. Six are required to clamp the wind-

ings. These diodes should have a continuous current

rating at least equal to the operating motor current,

since diode conduction duty-cycle can be high. For low-

voltage systems, Schottky diodes are preferred. In

higher voltage systems, diodes such as Microsemi

UHVP high voltage platinum rectifiers are recom-

mended.

In a pulse-by-pulse current control arrangement, current

sensing is done by resistor RT, through which the tran-

sistor's currents are passed (Figures A, B, and C). In

these cases, RDis not needed. The low-side circulating

diodes go to ground and the current sense terminals of

the UC3625 (ISENSE1 and ISENSE2) are connected to RT

through an Rc filter. The input bias current of the cur-

rent sense amplifier will cause a common mode offset

voltage to appear at both inputs, so for best accuracy,

keep the filter resistors below 2k and matched.

The current that flows through RTis discontinuous be-

cause of chopping. It flows during the on time of the

power stage and is zero during the off time. Conse-

quently, the voltage across RTconsists of a series of

pulses, occurring at the PWM frequency, with a peak

value indicative of the peak motor current.

To sense average motor current instead of peak cur-

rent, add another current sense resistor (RDin Figure

D) to measure current in the low-side circulating diodes,

and operate in four quadrant mode (pin 22 high). The

negative voltage across RDis corrected by the absolute

value current sense amplifier. Within the limitations im-

posed by Table 1, the circuit of Figure B can also sense

average current.

UC1625

UC2625

UC3625

POWER STAGE DESIGN (cont.):

2 4 SAFE POWER CURRENT SENSE

QUADRANT QUADRANT BRAKING REVERSE PULSE BY AVERAGE

PULSE

FIGURE A YES NO NO NO

jsa;hzh;ahfaxzh YES NO

FIGURE B YES YES NO IN 4QUAD

MODE ONLY YES YES

FIGURE C YES YES YES IN 4QUAD

MODE ONLY YES NO

FIGURE D YES YES YES IN 4QUAD

MODE ONLY YES YES

Fast High-Side P-Channel Driver Optocoupled N-Channel High-Side Driver

UC1625

UC2625

UC3625

For drives where speed is critical, P-Channel MOSFETs

can be driven by emitter followers. Here, both the level

shift NPN and the PNP must withstand high voltages. A

zener diode is used to limit gate-source voltage on the

MOSFET. A series gate resistor is not necessary, but al-

ways advisable to control overshoot and ringing.

High-voltage optocouplers can quickly drive high-voltage

MOSFETs if a boost supply of at least 10 volts greater

than the motor supply is provided. To protect the MOS-

FET, the boost supply should not be higher than 18 volts

above the motor supply.

For under 200V 2-quadrent applications, a power NPN

driven by a small P-Channel MOSFET will perform well

as a high-side driver. A high voltage small-signal NPN is

used as a level shift and a high voltage low-current

MOSFET provides drive. Although the NPN will not satu-

rate if used within its limitations, the base-emitter resistor

on the NPN is still the speed limiting component.

This power NPN Darlington drive technique uses a

clamp to prevent deep saturation. By limiting saturation

of the power device, excessive base drive is minimized

and turn-off time is kept fairly short. Lack of base series

resistance also adds to the speed of this approach.

Power NPN High-Side Driver Power NPN Low-Side Driver

UC1625

UC2625

UC3625

Fast High-Side N-Channel Driver with Transformer Isolation

A small pulse transformer can provide excellent isola-

tion between the UC3625 and a high-voltage N-

Channel MOSFET while also coupling gate drive

power. In this circuit, a UC3724 is used as a trans-

former driver/encoder that duty-cycle modulates the

transformer with a 150kHz pulse train. The UC3725

rectifies this pulse train for gate drive power, demodu-

lates the signal, and drives the gate with over 2 amp

peak current.

Both the UC3724 and the UC3725 can operate up to

500kHz if the pulse transformer is selected appropri-

ately. To raise the operating frequency, either lower the

timing resistor of the UC3724 (1k minimum), lower the

timing capacitor of the UC3724 (500pF minimum) or

both.

If there is significant capacitance between transformer

primary and secondary, together with very high output

slew rate, then it may be necessary to add clamp di-

odes from the transformer primary to +12V and ground.

Signal diodes such as 1N4148 are normally adequate.

The UC3725 also has provisions for MOSFET current

limiting. Consult the UC3725 data sheet for more infor-

mation on implementing this.

This table shows the outputs of the gate drive and

open collector outputs for given hall input codes and

direction signals. Numbers at the top of the columns

are pin numbers.

These ICs operate with position sensor encoding that

has either one or two signals high at a time, never all

low or all high. This coding is sometimes referred to

as “120°Coding” because the coding is the same as

coding with position sensors spaced 120 magnetic

degrees about the rotor. In response to these position

sense signals, only one low-side driver will turn on

(go high) and one high-side driver will turn on (pull

low) at any time.

INPUTS OUTPUTS

DIR H1 H2 H3 Low-Side High-Side

6 8 9 10 12 13 14 16 17 18

1001LHLLHH

1011LLHLHH

1010LLHHLH

1110HLLHLH

1100HLLHHL

1101LHLHHL

0101LLHHLH

0100LLHLHH

0110LHLLHH

0010LHLHHL

0011HLLHHL

0001HLLHLH

X111LLLHHH

X000LLLHHH

COMMUTATION TRUTH TABLE

UC1625

UC2625

UC3625

TYPICAL APPLICATION: A 45V/8A Brushless DC Motor Drive Circuit

N–Channel power MOSFETs are used for low–side driv-

ers, while P–Channel power MOSFETs are shown for

high–side drivers. Resistors are used to level shift the

UC3625 open–collector outputs, driving emitter followers

into the MOSFET gate. A 12V zener clamp insures that

the MOSFET gate–source voltage will never exceed

12V. Series 10Ωgate resistors tame gate reactance,

preventing oscillations and minimizing ringing.

The oscillator timing capacitor should be placed close to

pins 15 and 25, to keep ground current out of the ca-

pacitor. Ground current in the timing capacitor causes

oscillator distortion and slaving to the commutation sig-

nal.

The potentiometer connected to pin 1 controls PWM

duty cycle directly, implementing a crude form of speed

control. This control is often referred to as “voltage

mode” because the potentiometer position sets the

average motor voltage. This controls speed because

steady–state motor speed is closely related to applied

voltage.

Pin 20 (Tach-Out) is connected to pin 7 (SPEED IN)

through an RC filter, preventing direction reversal while

the motor is spinning quickly. In two–quadrant operation,

this reversal can cause kinetic energy from the motor to

be forced into the power MOSFETs.

A diode in series with the low-side MOSFETs facilitates

PWM current control during braking by insuring that

braking current will not flow backwards through low–side

MOSFETs. Dual current–sense resistors give continu-

ous current sense, whether braking or running in

four–quadrant operation, an unnecessary luxury for

two–quadrant operation.

The 68k ohm and 3nF tachometer components set

maximum commutation time at 140µs. This permits

smooth operation up to 35,000 RPM for four–pole mo-

tors, yet gives 140µs of noise blanking after

commutation.

UNITRODE CORPORATION

7 CONTINENTAL BLVD.• MERRIMACK, NH 03054

TEL. (603) 424-2410 • FAX (603) 424-3460