Dual Mobile-Friendly DDR / Dual-Output PWM Controller Features Description The FAN5236 PWM controller provides high efficiency and regulation for tw o output voltages adjustable in the range of 0.9V to 5.5V required to pow er I/O, chip-sets, and memory banks in high-performance notebook computers, PDAs, and Internet appliances. Synchronous rectification and hysteretic operation at light loads contribute to high efficiency over a w ide range of loads. The Hysteretic Mode can be disabled separately on each PWM converter if PWM Mode is desired for all load levels. Efficiency is enhanced by using MOSFET RDS(ON) as a current-sense component. Highly Flexible, Dual Synchronous Sw itching PWM Controller that Includes Modes for: - DDR Mode w ith In-phase Operation for Reduced Channel Interference - 90 Phase-shifted, Tw o-stage DDR Mode for Reduced Input Ripple - Dual Independent Regulators, 180 Phase Shifted Complete DDR Memory Pow er Solution V T T Tracks V DDQ/2 V DDQ/2 Buffered Reference Output Lossless Current Sensing on Low -side MOSFET or Precision Over-Current Using Sense Resistor V CC Under-Voltage Lockout Converters can Operate from +5V or 3.3V or Battery Pow er Input (5V to 24V) Excellent Dynamic Response w ith Voltage Feedforw ard and Average-Current-Mode Control Pow er-Good Signal Supports DDR-II and HSTL Light-Load Hysteretic Mode Maximizes Efficiency TSSOP28 Package Applications DDR V DDQ and V T T Voltage Generation Mobile PC Dual Regulator Server DDR Pow er i Hand-held PC Pow er Feedforw ard ramp modulation, average-current-mode control scheme, and internal feedback compensation provide fast response to load transients. Out-of-phase operation w ith 180-degree phase shift reduces input current ripple. The controller can be transformed into a complete DDR memory pow er supply solution by activating a designated pin. In DDR mode, one of the channels tracks the output voltage of another channel and provides output current sink and source capability -- essential for proper pow ering of DDR chips. The buffered reference voltage required by this type of memory is also provided. The FAN5236 monitors these outputs and generates separate PGx (pow er good) signals w hen the soft-start is completed and the output is w ithin 10% of the set point. Built-in over-voltage protection prevents the output voltage from going above 120% of the set point. Normal operation is automatically restored w hen the overvoltage conditions cease. Under-voltage protection latches the chip off w hen output drops below 75% of the set value after the soft-start sequence for this output is completed. An adjustable over-current function monitors the output current by sensing the voltage drop across the low er MOSFET. If precision current-sensing is required, an external current-sense resistor may be used. Related Resources http://w w w .onsemi.com/pub/Collateral/AN6002.pdf.pdf http://w w w .onsemi.com/pub/Collateral/AN1029.pdf.pdf (c) 2002 Semiconductor Components Industries, LLC. Nov ember-2017, Rev . 2 Publication Order Number: FAN5236/D FAN5236 -- Dual Mobile-Friendly DDR / Dual-Output PWM Controller FAN5236 Part Number B Operating Temperature Range FAN5236MTCX -10 to +85C Packing Method Package 28-Lead Thin-Shrink Small-Outline Package (TSSOP) Block Diagrams +5 VCC VIN (BATTERY) = 5 to 24V FAN5236 Q1 ILIM1 L VO UT1 = 2.5V OUT1 PWM 1 C OUT1 Q2 DDR Q3 ILIM2/ REF2 L VO UT 2 = 1.8V OUT2 PWM 2 C OUT2 Q4 Figure 1. Dual-Output Regulator +5 VCC FAN5236 VIN (BATTERY) = 5 to 24V Q1 ILIM1 L OUT1 PWM 1 VDDQ = 2.5V C OUT1 Q2 R +5 DDR R Q3 L PG2/REF OUT2 VTT = VDDQ /2 1.25V Q4 PWM 2 C OUT2 IL IM2/REF2 Figure 2. Com plete DDR Mem ory Pow er Supply www.onsemi.com 2 Tape and Reel FAN5236 -- Dual Mobile-Friendly DDR / Dual-Output PWM Controller Ordering Information AGND LDRV1 PGND1 SW1 HDRV1 BOOT1 ISNS1 EN1 FP WM1 VSEN1 IL IM1 SS1 DDR VIN 1 2 3 4 5 6 VCC LDRV 2 PGND2 SW2 HD RV 2 BOOT2 ISNS2 EN2 FP WM2 VSEN2 ILIM2/REF2 SS2 PG2/RE F2OUT PG1 28 27 26 25 24 23 7 22 FA N5 236 8 21 9 20 10 19 11 18 12 17 13 16 14 15 Figure 3. Pin Configuration Pin Definitions Pin # Name Description 1 AGND Analog Ground. This is the signal ground reference for the IC. All voltage levels are measured w ith respect to this pin. 2 LDRV1 27 LDRV2 3 PGND1 26 PGND2 4 SW1 25 SW2 5 HDRV1 24 HDRV2 6 BOOT1 23 BOOT2 7 ISNS1 22 ISNS2 8 EN1 21 EN2 9 FPWM1 20 FPWM2 10 VSEN1 19 VSEN2 11 ILIM1 Current Lim it 1. A resistor from this pin to GND sets the current limit. 12 SS1 17 SS2 Soft Start. A capacitor from this pin to GND programs the slew rate of the converter during initialization. During initialization, this pin is charged w ith a 5mA current source. Low -Side Drive. The low -side (low er) MOSFET driver output. Connect to gate of low -side MOSFET. Pow er Ground. The return for the low -side MOSFET driver. Connect to source of low -side MOSFET. Sw itching Node. Return for the high-side MOSFET driver and a current sense input. Connect to source of high-side MOSFET and low -side MOSFET drain. High-Side Drive. High-side (upper) MOSFET driver output. Connect to gate of high-side MOSFET. BOOT. Positive supply for the upper MOSFET driver. Connect as show n in Figure 4. Current-Sense Input. Monitors the voltage drop across the low er MOSFET or external sense resistor for current feedback. Enable. Enables operation w hen pulled to logic HIGH. Toggling EN resets the regulator after a latched fault condition. These are CMOS inputs w hose state is indeterminate if left open. Forced PWM Mode. When logic LOW, inhibits the regulator from entering Hysteretic Mode; otherw ise tie to V OUT . The regulator uses V OUT on this pin to ensure a smooth transition from Hysteretic Mode to PWM Mode. When V OUT is expected to exceed V CC, tie to V CC. Output Voltage Sense. The feedback from the outputs. Used for regulation as w ell as PG, under-voltage, and over-voltage protection and monitoring. www.onsemi.com 3 FAN5236 -- Dual Mobile-Friendly DDR / Dual-Output PWM Controller Pin Configuration Pin # Name 13 DDR DDR Mode Control. HIGH = DDR Mode. LOW = tw o separate regulators operating 180 out of phase. 14 VIN Input Voltage. Normally connected to battery, providing voltage feedforw ard to set the amplitude of the internal oscillator ramp. When using the IC for tw o-step conversion from 5V input, connect through 100K resistor to ground, w hich sets the appropriate ramp gain and synchronizes the channels 90 out of phase. 15 PG1 Pow er Good Flag. An open-drain output that pulls LOW w hen V SEN is outside a 10% range of the 0.9V reference. 16 PG2 / REF2OUT 18 ILIM2 / REF2 28 VCC Description Pow er Good 2. When not in DDR Mode, open-drain output that pulls LOW w hen the V OUT is out of regulation or in a fault condition. Reference Out 2. When in DDR Mode, provides a buffered output of REF2. Typically used as the V DDQ/2 reference. Current Lim it 2. When not in DDR Mode, a resistor from this pin to GND sets the current limit. Reference for reg #2 w hen in DDR Mode. Typically set to V OUT 1 / 2. VCC. This pin pow ers the chip as w ell as the LDRV buffers. The IC starts to operate w hen voltage on this pin exceeds 4.6V (UVLO rising) and shuts dow n w hen it drops below 4.3V (UVLO falling). www.onsemi.com 4 FAN5236 -- Dual Mobile-Friendly DDR / Dual-Output PWM Controller Pin Descriptions (Continued) Stresses exceeding the absolute maximum ratings may damage the device. The device may not function or be operable above the recommended operating conditions and stressing the parts to these levels is not recommended. In addition, extended exposure to stresses above the recommended operating conditions may affect device reliability. The absolute maximum ratings are stress ratings only. Symbol Parameter Min. Max. Unit V CC V CC Supply Voltage 6.5 V V IN V IN Supply Voltage 27 V BOOT, SW, ISNS, HDRV 33 V BOOTx to SWx 6.5 V All Other Pins -0.3 V CC+0.3 V TJ Junction Temperature -40 +150 C TST G Storage Temperature -65 +150 C +300 C TL Lead Temperature (Soldering,10 Seconds) Recommended Operating Conditions The Recommended Operating Conditions table defines the conditions for actual device operation. Recommended operating conditions are specified to ensure optimal performance to the datasheet specifications. ON Semiconductor does not recommend exceeding them or designing to Absolute Maximum Ratings. Symbol Parameter V CC V CC Supply Voltage V IN V IN Supply Voltage TA Ambient Temperature JA Thermal Resistance, Junction to Ambient Min. Typ. Max. Unit 4.75 5.00 5.25 V 24 V +85 C 90 C/W -10 www.onsemi.com 5 FAN5236 -- Dual Mobile-Friendly DDR / Dual-Output PWM Controller Absolute Maximum Ratings Recommended operating conditions, unless otherw ise noted. Symbol Parameter Conditions Min. Typ. Max. Units 2.2 3.0 A 30 A 30 A -30 A 1 A Pow er Supplies IVCC V CC Current LDRV, HDRV Open, V SEN Forced Above Regulation Point Shutdow n (EN-0) ISINK ISOURCE ISD V IN Current, Sinking V IN = 24V V IN Current, Sourcing V IN = 0V 10 -15 V IN Current, Shutdow n V UVLO UVLO Threshold V UVLOH UVLO Hysteresis Rising V CC 4.30 4.55 4.75 V Falling 4.10 4.25 4.45 V 300 mV Oscillator f osc Frequency V PP Ramp Amplitude V RAMP G 255 345 KHz V IN = 16V 2 V V IN = 5V 1.25 V 0.5 V V IN 3V 125 mV/V 1V < V IN < 3V 250 mV/V Ramp Offset Ramp / V IN Gain 300 Reference and Soft Start V REF Internal Reference Voltage ISS Soft-Start Current V SS Soft-Start Complete Threshold 0.891 At Startup 0.900 0.909 V 5 A 1.5 V PWM Converters Load Regulators ISEN UVLOT SD IOUT X from 0 to 5A, V IN from 5 to 24V -2 +2 % V SEN Bias Current 50 80 120 nA VOUT Pin Input Impedance 45 55 65 K Under-Voltage Shutdow n % of Set Point, 2s Noise Filter 70 75 80 % UVLO Over-Voltage Threshold % of Set Point, 2s Noise Filter 115 120 125 % ISNS Over-Current Threshold RILIM= 68.5K, Figure 12 112 140 168 A Sourcing 12.0 15.0 Sinking 2.4 4.0 Sourcing 12.0 15.0 Sinking 1.2 2.0 Output Drivers HDRV Output Resistance LDRV Output Resistance Continued on following page... www.onsemi.com 6 FAN5236 -- Dual Mobile-Friendly DDR / Dual-Output PWM Controller Electrical Characteristics Symbol Parameter Conditions Min. Typ. Max. Units Pow er-Good Output and Control Pins Low er Threshold % of Set Point, 2s Noise Filter -86 -94 % Upper Threshold % of Set Point, 2s Noise Filter 108 116 % PG Output Low IPG = 4mA 0.5 V Leakage Current V PULLUP = 5V 1 A PG2/REF2OUT Voltage DDR = 1, 0mA < IREF2OUT 10mA 1.01 % V REF2 99.00 DDR, EN Inputs V INH Input High V INL Input Low 2 V 0.8 V 0.1 V FPWM Inputs FPWM Low FPWM High FPWM Connected to Output Block Diagram Figure 4. IC Block Diagram www.onsemi.com 7 0.9 V FAN5236 -- Dual Mobile-Friendly DDR / Dual-Output PWM Controller Electrical Characteristics (Continued) VIN (BATTERY) = 5 to 24V VIN VCC +5 28 C9 C1 14 6 C4 D1 BOOT1 +5 Q1A 5 R3 ILIM1 EN1 SS1 C2 11 4 PW M 1 12 2 3 7 R4 9 15 10 DDR +5 EN2 SS2 C3 13 23 21 17 24 1.25V at 10mA AGND PW M 2 27 1 26 22 FPWM2 C6A 19 20 18 C6B R5 LDRV1 R7 PGND2 ISNS1 FPWM1 (VOUT1) R1 VSEN1 BOOT2 R6 D2 +5 C7 HDRV2 SW2 L2 Q2B 16 VDDQ = 2.5V L1 SW1 Q2A 25 PG2/REF HDRV1 Q1B 8 +5 PG1 C5 VTT = VDDQ/2 R2 C8A LDRV2 PGND2 R8 ISNS2 C8B VSEN2 ILIM2/REF2 Figure 5. DDR Regulator Application Table 1. DDR Regulator BOM Description Qty. Ref. Vendor Part Number Capacitor 68f, Tantalum, 25V, ESR 150m 1 C1 AVX Capacitor 10nf, Ceramic 2 C2, C3 Any TPSV686*025#0150 Capacitor 68f, Tantalum, 6V, ESR 1.8 1 C4 AVX Capacitor 150nF, Ceramic 2 C5, C7 Any Capacitor 180f, Specialty Polymer 4V, ESR 15m 2 C6A, C6B Panasonic EEFUE0G181R Capacitor 1000f, Specialty Polymer 4V, ESR 10m 1 C8 Kemet T510E108(1)004AS4115 Capacitor 0.1F, Ceramic 2 C9 Any 18.2K, 1% Resistor 3 R1, R2 Any 1.82K, 1% Resistor 1 R6 Any 56.2K, 1% Resistor 2 R3 Any 10K, 5% Resistor 2 R4 Any 3.24K, 1% Resistor 1 R5 Any 1.5K, 1% Resistor 2 R7, R8 Any Schottky Diode 30V 2 D1, D2 ON Semiconductor BAT54 Inductor 6.4H, 6A, 8.64m 1 L1 Panasonic ETQ-P6F6R4HFA Inductor 0.8H, 6A, 2.24m 1 L2 Panasonic ETQ-P6F0R8LFA Dual MOSFET w ith Schottky 1 Q1, Q2 ON Semiconductor FDS6986AS(1) DDR Controller 1 U1 ON Semiconductor FAN5236 TAJB686*006 Note: 1. Suitable for typical notebook computer application of 4A continuous, 6A peak for V DDQ. If continuous operation above 6A is required, use single SO-8 packages. For more information, refer to the Power MOSFET Selection Section and use AN-6002 for design calculations. www.onsemi.com 8 FAN5236 -- Dual Mobile-Friendly DDR / Dual-Output PWM Controller Typical Application V IN (BATTERY) = 5 to 24V VIN C9 C1 14 VCC +5 28 D1 BOOT1 6 C4 +5 Q1A ILIM1 11 EN1 SS1 C2 8 12 C6 LDRV1 2 R6 PGND2 R4 ISNS1 7 R3 FPWM1 (VOUT1) 9 15 10 13 23 VSEN1 V IN BOOT2 R5 D2 Q2A EN2 PG2 SS2 21 24 25 16 17 PW M 2 27 AGND 1 26 22 FPWM2 +5 HDRV2 C7 SW2 L2 1.8V at 6A Q2B C3 2.5V at 6A Q1B PW M 1 3 DDR L1 SW1 4 +5 PG1 C5 HDRV1 5 R2 19 20 18 C8 LDRV2 R7 R8 PGND2 ISNS2 R9 VSEN2 R1 ILIM2 Figure 6. Dual Regulator Application Table 2. DDR Regulator BOM Item Description Qty. Ref. Vendor 1 Capacitor 68f, Tantalum, 25V, ESR 95m 1 C1 AVX 2 Capacitor 10nf, Ceramic 2 C2, C3 Any 3 Capacitor 68f, Tantalum, 6V, ESR 1.8 1 C4 AVX 4 Capacitor 150nF, Ceramic 2 C5, C7 Any 5 Capacitor 330f, Poscap, 4V, ESR 40m 2 C6, C8 Sanyo 5 Capacitor 0.1F, Ceramic 2 C9 Any 11 56.2K, 1% Resistor 2 R1, R2 Any 12 10K, 5% Resistor 2 R3 Any 13 3.24K, 1% Resistor 1 R4 Any Any Part Number TPSV686*025#095 TAJB686*006 4TPB330ML 14 1.82K, 1% Resistor 3 R5, R8, R9 15 1.5K, 1% Resistor 2 R6, R7 Any 27 Schottky Diode 30V 2 D1, D2 ON Semiconductor BAT54 28 Inductor 6.4H, 6A, 8.64m 1 L1, L2 Panasonic ETQ-P6F6R4HFA 29 Dual MOSFET w ith Schottky 1 Q1 ON Semiconductor FDS6986AS(2) 30 DDR Controller 1 U1 ON Semiconductor FAN5236 Note: 2. If currents above 4A continuous are required, use single SO-8 packages. For more information, refer to the Power MOSFET Selection Section and AN-6002 for design calculations. www.onsemi.com 9 FAN5236 -- Dual Mobile-Friendly DDR / Dual-Output PWM Controller Typical Applications (Continued) Overview The FAN5236 is a multi-mode, dual-channel PWM controller intended for graphic chipset, SDRAM, DDR DRAM, or other low -voltage pow er applications in modern notebook, desktop, and sub-notebook PCs. The IC integrates control circuitry for tw o synchronous buck converters. The output voltage of each controller can be set in the range of 0.9V to 5.5V by an external resistor divider. The tw o synchronous buck converters can operate from either an unregulated DC source (such as a notebook battery), w ith voltage ranging from 5.0V to 24V, or from a regulated system rail of 3.3V to 5.0V. In either mode, the IC is biased from a +5V source. The PWM modulators use an average-current-mode control w ith input voltage feedforw ard for simplified feedback loop compensation and improved line regulation. Both PWM controllers have integrated feedback loop compensation that reduces the external components needed. Depending on the load level, the converters can operate in fixed-frequency PWM Mode or in a Hysteretic Mode. Sw itch-over from PWM to Hysteretic Mode improves the converters' efficiency at light loads and prolongs battery run time. In Hysteretic Mode, comparators are synchronized to the main clock, w hich allow s seamless transition betw een the modes and reduces channel-tochannel interaction. The Hysteretic Mode can be inhibited independently for each channel if variable frequency operation is not desired. The FAN5236 can be configured to operate as a complete DDR solution. When the DDR pin is set HIGH, the second channel provides the capability to track the output voltage of the first channel. The PWM2 converter is prevented from going into Hysteretic Mode if the DDR pin is set HIGH. In DDR Mode, a buffered reference voltage (buffered voltage of the REF2 pin), required by DDR memory chips, is provided by the PG2 pin. When V IN is from the battery, it's typically higher than 7.5V. As show n in Figure 7, 180 operation is undesirable because the turn-on of the V DDQ converter occurs very near the decision point of the V T T converter. CLK VD DQ VTT Figure 7. Noise-Susceptible 180 Phasing for DDR1 In-phase operation is optimal to reduce inter-converter interference w hen V IN is higher than 5V (w hen V IN is from a battery), as show n in Figure 8. Because the duty cycle of PWM1 (generating V DDQ) is short, the sw itching point occurs far aw ay from the decision point for the V T T regulator, w hose duty cycle is nominally 50%. Figure 8. Optim al In-Phase Operation for DDR1 CLK When VDDQ V IN VTT 5V, 180 phase-shifted operation can be rejected for the reasons demonstrated in Figure 7. In-phase operation w ith V IN 5V is even w orse, since the sw itch point of either converter occurs near the sw itch point of the other converter, as seen in Figure 9. In this case, as V IN is a little higher than 5V, it tends to cause early termination of the V T T pulse w idth. Conversely, the V T T sw itch point can cause early termination of the V DDQ pulse w idth w hen V IN is slightly low er than 5V. CLK Converter Modes and Synchronization Table 3. Converter Modes and Synchronization VDDQ Mode VIN VIN Pin DDR Pin PWM 2 w.r.t. PWM1 DDR1 Battery V IN HIGH IN PHASE DDR2 +5V R to GND HIGH +90 DUAL ANY V IN LOW +180 When used as a dual converter, as show n in Figure 6, out-of-phase operation w ith 180-degree phase shift reduces input current ripple. For "tw o-step" conversion (w here the V T T is converted from V DDQ as in Figure 5) used in DDR Mode, the duty cycle of the second converter is nominally 50% and the optimal phasing depends on V IN. The objective is to keep noise generated from the sw itching transition in one converter from influencing the "decision" to sw itch in the other converter. VTT Figure 9. Noise-Susceptible In-Phase Operation for DDR2 These problems are solved by delaying the second converter's clock by 90, as show n in Figure 10. In this w ay, all sw itching transitions in one converter take place far aw ay from the decision points of the other converter. CLK VDDQ VTT www.onsemi.com 10 Figure 10. Optim al 90 Phasing for DDR FAN5236 -- Dual Mobile-Friendly DDR / Dual-Output PWM Controller Circuit Description converters operate in fixed-frequency PWM Mode, as show n in Figure 11. This mode achieves high efficiency at nominal load. When the load current decreases to the point w here the inductor current flow s through the low er MOSFET in the `reverse' direction, the SW node becomes positive and the mode is changed to hysteretic, w hich achieves higher efficiency at low currents by decreasing the effective sw itching frequency. Assuming EN is HIGH, FAN5236 is initialized w hen V CC exceeds the rising UVLO threshold. Should V CC drop below the UVLO threshold, an internal pow er-on reset function disables the chip. The voltage at the positive input of the error amplifier is limited by the voltage at the SS pin, w hich is charged w ith a 5A current source. Once CSS has charged to V REF (0.9V) the output voltage is in regulation. The time it takes SS to reach 0.9V is: t 0 .9 = 0.9 xCSS 5 To prevent accidental mode change or "mode chatter," the transition from PWM to Hysteretic Mode occurs w hen the SW node is positive for eight consecutive clock cycles, as show n in Figure 11. The polarity of the SW node is sampled at the end of the low er MOSFET conduction time. At the transition betw een PWM and Hysteretic Mode, the upper and low er MOSFETs are turned off. The phase node "rings" based on the output inductor and the parasitic capacitance on the phase node and settles out at the value of the output voltage. (1) w here t0.9 is in seconds if CSS is in F. When SS reaches 1.5V, the pow er-good outputs are enabled and Hysteretic Mode is allow ed. The converter is forced into PWM Mode during soft-start. The boundary value of inductor current, w here current becomes discontinuous, can be estimated by the follow ing expression: Operation Mode Control The mode-control circuit changes the converter mode from PWM to hysteretic and vice versa, based on the voltage polarity of the SW node w hen the low er MOSFET is conducting and just before the upper MOSFET turns on. For continuous inductor current, the SW node is negative w hen the low er MOSFET is conducting and the (V - V )V OUT OUT I LOAD( DIS ) = IN 2 F L V SW OUT IN (2) VCORE PWMMode IL HystereticMode 0 1 2 3 4 5 6 7 8 VCORE IL HystereticMode 0 1 Figure 11. 2 3 PWMMode 4 5 6 7 8 Transitioning Betw een PWM and Hysteretic Mode Hysteretic Mode Conversely, the transition from Hysteretic Mode to PWM Mode occurs w hen the SW node is negative for eight consecutive cycles. monitored and sw itched off w hen V DS(ON) goes positive (current flow ing back from the load), allow ing the diode to block reverse conduction. A sudden increase in the output current causes a change from Hysteretic to PWM Mode. This load increase causes an instantaneous decrease in the output voltage due to the voltage drop on the output capacitor ESR. If the load causes the output voltage (as presented at V SNS ) to drop below the hysteretic regulation level (20mV below V REF), the mode is changed to PWM on the next clock cycle. The hysteretic comparator initiates a PFM signal to turn on HDRV at the rising edge of the next oscillator clock, w hen the output voltage (at V SNS ) falls below the low er threshold (10mV below V REF) and terminates the PFM signal or w hen V SNS rises over the higher threshold (5mV above V REF). The sw itching frequency is primarily a function of: In Hysteretic Mode, the PWM comparator and the error amplifier that provide control in PWM Mode are inhibited and the hysteretic comparator is activated. In Hysteretic Mode, the low -side MOSFET is operated as a synchronous rectifier, w here the voltage across V DS(ON) is Spread betw een the tw o hysteretic thresholds ILOAD Output inductor and capacitor ESR. www.onsemi.com 11 FAN5236 -- Dual Mobile-Friendly DDR / Dual-Output PWM Controller Initialization and Soft Start VHYSTERESIS I LOAD( CCM ) = 2 ESR (3) Figure 12. w here V HYST ERESIS = 15mV and ESR is the equivalent series resistance of COUT . Because of the different control mechanisms, the value of the load current w here transition into CCM operation takes place is typically higher compared to the load level at w hich transition into Hysteretic Mode occurs. Hysteretic Mode can be disabled by setting the FPWM pin LOW. Current Lim it / Sum m ing Circuits Current Processing Section The current through the RSENSE resistor (ISNS ) is sampled (typically 400ns) after Q2 is turned on, as show n in Figure 12. That current is held and summed w ith the output of the error amplifier. This effectively creates a current-mode control loop. The resistor connected to ISNSx pin (RSENSE ) sets the gain in the current feedback loop. The follow ing expression estimates the recommended value of RSENSE as a function of the maximum load current (ILOAD(MAX)) and the value of the MOSFET RDS(ON): I LOAD( MAX ) * R DS( ON ) RSENSE = - 100 75 A (4) accurate if the voltage drop on the sw itching-node side of RSENSE is an accurate representation of the load current. When using the MOSFET as the sensing element, the variation of RDS(ON) causes proportional variation in the ISNS . This value varies from device to device and has a typical junction temperature coefficient of about 0.4%/C (consult the MOSFET datasheet for actual values), so the actual current limit set point decreases proportional to increasing MOSFET die temperature. A factor of 1.6 in the current limit set point should compensate for MOSFET RDS(ON) variations, assuming the MOSFET heat sinking keeps its operating die temperature below 125C. RSENSE must, how ever, be kept higher than 700 even if the number calculated comes out to be less than 700. Q2 LDRV ISNS Setting the Current Limit R LIM = (100 + R 11 SENSE x I LOAD R DS( ON ) ) R1 A ratio of ISNS is compared to the current established w hen a 0.9V internal reference drives the ILIM pin: RSENSE PGND (5) Figure 13. Since the tolerance on the current limit is largely dependent on the ratio of the external resistors, it is fairly www.onsemi.com 12 Im proving Current-Sensing Accuracy FAN5236 -- Dual Mobile-Friendly DDR / Dual-Output PWM Controller A transition back to PWM continuous conduction mode (CCM) mode occurs w hen the inductor current rises sufficiently to stay positive for eight consecutive cycles. This occurs w hen: Current limit (ILIMIT ) should be set high enough to allow inductor current to rise in response to an output load transient. Typically, a factor of 1.2 is sufficient. In addition, since ILIMIT is a peak current cut-off value, multiply ILOAD(MAX) by the inductor ripple current (e.g. 25%). For example, in Figure 6, the target for ILIMIT : ILIMIT > 1.2 x 1.25 x 1.6 x 6A 14.5A (6) Duty Cycle Clamp During severe load increase, the error amplifier output can go to its upper limit, pushing a duty cycle to almost 100% for significant amount of time. This could cause a large increase of the inductor current and lead to a long recovery from a transient, over-current condition, or even to a failure at especially high input voltages. To prevent this, the output of the error amplifier is clamped to a fixed value after tw o clock cycles if severe output voltage excursion is detected, limiting the maximum duty cycle to: DC MAX = V OUT V IN 2 .4 + VIN (7) This is designed to not interfere w ith normal PWM operation. When FPWM is grounded, the duty cycle clamp is disabled and the maximum duty cycle is 87%. Gate Driver Section Due to the implemented current-mode control, the modulator has a single-pole response w ith -1 slope at frequency determined by load: f PO = 1 2 ROCO (8) w here RO is load resistance; CO is load capacitance. For this type of modulator, a Type-2 compensation circuit is usually sufficient. To reduce the number of external components and simplify the design, the PWM controller has an internally compensated error amplifier. Figure 14 show s a Type-2 amplifier, its response, and the responses of a current-mode modulator and the converter. The Type-2 amplifier, in addition to the pole at the origin, has a zero-pole pair that causes a flat gain region at frequencies betw een the zero and the pole. fZ = 1 = 6 kHz 2 R2C1 (9) fP = 1 = 600kHz 2 2 C2 (10) This region is also associated w ith phase "bump" or reduced phase shift. The amount of phase-shift reduction depends on the w idth of the region of flat gain and has a maximum value of 90. To further simplify the converter compensation, the modulator gain is kept independent of the input voltage variation by providing feedforw ard of V IN to the oscillator ramp. The zero frequency, the amplifier high-frequency gain, and the modulator gain are chosen to satisfy most typical applications. The crossover frequency appears at the point w here the modulator attenuation equals the amplifier high-frequency gain. The system designer must specify the output filter capacitors to position the load main pole somew here w ithin a decade low er than the amplifier zero frequency. With this type of compensation, plenty of phase margin is achieved due to zero-pole pair phase "boost." C2 R2 C1 R1 VIN EA Out REF C am rte or ve e rr on p r The adaptive gate control logic translates the internal PWM control signal into the MOSFET gate drive signals, providing necessary amplification, level shifting, and shoot-through protection. It also has functions that optimize the IC performance over a w ide range of operating conditions. Since MOSFET sw itching time can vary dramatically from type to type and w ith the input voltage, the gate control logic provides adaptive dead time by monitoring the gate-to-source voltages of both upper and low er MOSFETs. The low er MOSFET drive is not turned on until the gate-to-source voltage of the upper MOSFET has decreased to less than approximately 1V. Similarly, the upper MOSFET is not turned on until the gateto-source voltage of the low er MOSFET has decreased to less than approximately 1V. This allow s a w ide variety of upper and low er MOSFETs to be used w ithout a concern for simultaneous conduction or shoot-through. Frequency Loop Compensation modul ator There must be a low -resistance, low -inductance path betw een the driver pin and the MOSFET gate for the adaptive dead-time circuit to function properly. Any delay along that path subtracts from the delay generated by the adaptive dead-time circuit and shoot-through may occur. 18 14 0 f P0 Figure 14. www.onsemi.com 13 f Z Com pensation f P FAN5236 -- Dual Mobile-Friendly DDR / Dual-Output PWM Controller More accurate sensing can be achieved by using a resistor (R1) instead of the RDS(ON) of the FET, as show n in Figure 13. This approach causes higher losses, but yields greater accuracy in both V DROOP and ILIMIT . R1 is a low value resistor (e.g. 10m). clock cycle, the ILIM det is again reached, the overcurrent protection latch is set, disabling the regulator. If ILIM det does not occur betw een cycles nine and sixteen, normal operation is restored and the over-current circuit resets itself. If a larger inductor value or low -ESR values are required by the application, additional phase margin can be achieved by putting a zero at the LC crossover frequency. This can be achieved w ith a capacitor across the feedback resistor (e.g. R5 from Figure 6), as show n in Figure 15. VOUT L(OUT) R5 C(Z) C(OUT) VSEN R6 Figure 15. Im proving Phase Margin Figure 16. The optimal value of C(Z) is: C(Z) = L(OUT) xC(OUT) (11) R Protections The converter output is monitored and protected against extreme overload, short-circuit, over-voltage, and undervoltage conditions. A sustained overload on an output sets the PGx pin LOW and latches off the regulator on w hich the fault occurs. Operation can be restored by cycling the V CC voltage or by toggling the EN pin. If V OUT drops below the under-voltage threshold, the regulator shuts dow n immediately. Over-Current Sensing If the circuit's current limit signal ("ILIM det" in Figure 12) is HIGH at the beginning of a clock cycle, a pulse-skipping circuit is activated and HDRV is inhibited. The circuit continues to pulse skip in this manner for the next eight clock cycles. If at any time from the ninth to the sixteenth Over-Current Protection Waveform s Over-Voltage / Under-Voltage Protection Should the V SNS voltage exceed 120% of V REF (0.9V) due to an upper MOSFET failure or for other reasons, the over-voltage protection comparator forces LDRV HIGH. This action actively pulls dow n the output voltage and, in the event of the upper MOSFET failure, eventually blow s the battery fuse. As soon as the output voltage drops below the threshold, the OVP comparator is disengaged. This OVP scheme provides a "soft" crow bar function, w hich accommodates severe load transients and does not invert the output voltage w hen activated -- a common problem for latched OVP schemes. Similarly, if an output short-circuit or severe load transient causes the output to drop to less than 75% of the regulation set point, the regulator shuts dow n. Over-Tem perature Protection The chip incorporates an over-temperature protection circuit that shuts the chip dow n if a die temperature of about 150C is reached. Normal operation is restored at die temperature below 125C w ith internal pow er-on reset asserted, resulting in a full soft-start cycle. www.onsemi.com 14 FAN5236 -- Dual Mobile-Friendly DDR / Dual-Output PWM Controller Conditional stability may occur only w hen the main load pole is positioned too much to the left side on the frequency axis due to excessive output filter capacitance. In this case, the ESR zero placed w ithin the 10kHz to 50kHz range gives some additional phase boost. There is an opposite trend in mobile applications to keep the output capacitor as small as possible. As an initial step, define operating input voltage range, output voltage, and minimum and maximum load currents for the controller. Setting the Output Voltage The internal reference voltage is 0.9V. The output is divided dow n by a voltage divider to the VSEN pin (for example, R5 and R6 in Figure 5). The output voltage therefore is: 0.9V V OUT - 0.9V = R6 R5 (12) To minimize noise pickup on this node, keep the resistor to GND (R6) below 2K; for example, R6 at 1.82K. Then choose R5: R5 = (1.82 K )(VOUT - 0 .9 0 .9 ) = 3.24K (13) Output Capacitor Selection The output capacitor serves tw o major functions in a sw itching pow er supply. Along w ith the inductor, it filters the sequence of pulses produced by the sw itcher and it supplies the load transient currents. The output capacitor requirements are usually dictated by ESR, inductor ripple current (I), and the allow able ripple voltage (V): ESR < V I (18) In addition, the capacitor's ESR must be low enough to allow the converter to stay in regulation during a load step. The ripple voltage due to ESR for the converter in Figure 6 is 120mV PP . Some additional ripple appears due to the capacitance value itself: V = I COUT x 8 x fSW (19) For DDR applications converting from 3.3V to 2.5V or other applications requiring high duty cycles, the duty cycle clamp must be disabled by tying the converter's FPWM to GND. When converter's FPWM is at GND, the converter's maximum duty cycle is greater than 90%. When using as a DDR converter w ith 3.3V input, set up the converter for in-phase synchronization by tying the VIN pin to +5V. w hich is only about 1.5mV, for the converter in Figure 6, and can be ignored. Output Inductor Selection Input Capacitor Selection The minimum practical output inductor value keeps inductor current just on the boundary of continuous conduction at some minimum load. The industry standard practice is to choose the minimum current somew here from 15% to 35% of the nominal current. At light load, the controller can automatically sw itch to Hysteretic Mode of operation to sustain high efficiency. The follow ing equations help to choose the proper value of the output filter inductor: The input capacitor should be selected by its ripple current rating. I = 2 x 1MIN V = OUT (14) ESR w here I is the inductor ripple current and V OUT is the maximum ripple allow ed: L= VIN - V OUT f SW x I x V OUT VIN (15) for this example, use: Two-Stage Converter Case In DDR Mode (show n in Figure 5), the V T T pow er input is pow ered by the V DDQ output; therefore, all of the input capacitor ripple current is produced by the V DDQ converter. A conservative estimate of the output current required for the 2.5V regulator is: I REGI = I VDDQ + (20) 2 As an example, if the average IVDDQ is 3A and average IVT T is 1A, IVDDQ current is about 3.5A. If average input voltage is 16V, RMS input ripple current is: I RMS = I OUT(MAX ) D - D (16) D< 2 (21) V OUT VIN = 2 .5 16 (22) therefore: therefore: L 6H I VTT w here D is the duty cycle of the PWM1 converter: VIN = 20, V OUT = 2.5 I = 20% * 6 A = 1.2A f SW = 300KHz The capacitor must also be rated to w ithstand the RMS current, w hich is approximately 0.3 X (I), or about 400mA for the converter in Figure 6. High-frequency decoupling capacitors should be placed as close to the loads as physically possible. (17) I RMS www.onsemi.com 15 2.5 2.5 = 3 .5 - 16 16 2 = 1.49 A (23) FAN5236 -- Dual Mobile-Friendly DDR / Dual-Output PWM Controller Design and Component Selection Guidelines In dual mode (show n in Figure 6), both converters contribute to the capacitor input ripple current. With each converter operating 180 out of phase, the RMS currents add in the follow ing fashion: I RMS = I IRMS = 2 RMS(1) +I 2 RMS( 2) or (I1 )2 (D1 - D12 ) + (I2 )2 (D 2 - D 2 2 ) (24) PUPPER is the upper MOSFET's total losses and PSW and PCOND are the sw itching and conduction losses for a given MOSFET. RDS(ON) is at the maximum junction temperature (TJ ). tS is the sw itching period (rise or fall time), show n as t2+t3 in Figure 17. CISS C GD QGS QGD C ISS VDS (25) w hich, for the dual 3A converters show n in Figure 6, calculates to: I RMS ID = 1 .4 A (26) Power MOSFET Selection 4.5V Losses in a MOSFET are the sum of its sw itching (PSW ) and conduction (PCOND) losses. In typical applications, the FAN5236 converter's output voltage is low w ith respect to its input voltage. Therefore, the low er MOSFET (Q2) is conducting the full load current for most of the cycle. Q2 should therefore be selected to minimize conduction losses, thereby selecting a MOSFET w ith low RDS(ON). VSP VTH QG(SW) VGS t1 Figure 17. t4 t3 t2 Sw itching Losses and QG VIN 5V In contrast, the high-side MOSFET (Q1) has a shorter duty cycle and it's conduction loss has less impact. Q1, how ever, sees most of the sw itching losses, so Q1's primary selection criteria should be gate charge. t5 C GD RD HDRV RGATE G CGS High-Side Losses SW Figure 17 show s a MOSFET's sw itching interval, w ith the upper graph being the voltage and current on the drain-tosource and the low er graph detailing V GS vs. time w ith a constant current charging the gate. The X-axis, therefore, is also representative of gate charge (QG). CISS = CGD + CGS and it controls t1, t2, and t4 timing. CGD receives the current from the gate driver during t3 (as V DS is falling). The gate charge (QG) parameters on the low er graph are either specified or can be derived from MOSFET datasheets. Assuming sw itching losses are about the same for both the rising edge and falling edge, Q1's sw itching losses occur during the shaded time w hen the MOSFET has voltage across it and current through it. Figure 18. Drive Equivalent Circuit The driver's impedance and CISS determine t2, w hile t3's period is controlled by the driver's impedance and QGD. Since most of tS occurs w hen V GS = V SP , use a constant current assumption for the driver to simplify the calculation of tS : ts = Q G( SW ) I DRIVER = Q G( SW ) V -V CC SP R DRIVER + R GATE (30) Most MOSFET vendors specify QGD and QGS. QG(SW) can be determined as: These losses are given by: PUPPER = PSW + PCOND (27) QG( SW ) = QGD + QGS - QTH V xI PSW = DS L x 2 x t s f SW 2 (28) w here QT H is the gate charge required to get the MOSFET to its threshold (V T H). PCOND = V OUT VIN x I OUT 2 x R DS( ON) (29) www.onsemi.com 16 (31) FAN5236 -- Dual Mobile-Friendly DDR / Dual-Output PWM Controller Dual Converter 180 Phased PG ATE = Q G x V CC x f SW (32) w here QG is the total gate charge to reach V CC. Low-Side Losses Q2, how ever, sw itches on or off w ith its parallel Schottky diode conducting; therefore V DS 0.5V. Since PSW is proportional to V DS , Q2's sw itching losses are negligible and Q2 is selected based on RDS(ON) only. Conduction losses for Q2 are given by: PCOND = (1 - D ) x I OUT x R DS ( ON ) 2 (33) w here RDS(ON) is the RDS(ON) of the MOSFET at the highest operating junction temperature, and: D= V OUT (34) V IN is the minimum duty cycle for the converter. Since DMIN < 20% for portable computers, (1-D) 1 produces a conservative result, further simplifying the calculation. The maximum pow er dissipation (PD(MAX)) is a function of the maximum allow able die temperature of the low -side MOSFET, the JA , and the maximum allow able ambient temperature rise: PD(MAX ) = TJ(MAX ) - T A (MAX ) JA (35) JA depends primarily on the amount of PCB area that can be devoted to heat sinking (see ON Semiconductor Application Note AN-1029 -- Maximum Power Enhancement Techniques for SO-8 Power MOSFETs). Layout Considerations Sw itching converters, even during normal operation, produce short pulses of current that could cause substantial ringing and be a source of EMI if layout constraints are not observed. There are tw o sets of critical components in a DC-DC converter. The sw itching pow er components process large amounts of energy at high rates and are noise generators. The low -pow er components responsible for bias and feedback functions are sensitive to noise. A multi-layer printed circuit board is recommended. Dedicate one solid layer for a ground plane. Dedicate another solid layer as a pow er plane and break this plane into smaller islands of common voltage levels. Notice all the nodes that are subjected to high-dV/dt voltage sw ing; such as SW, HDRV, and LDRV. All surrounding circuitry tends to couple the signals from these nodes through stray capacitance. Do not oversize copper traces connected to these nodes. Do not place traces connected to the feedback components adjacent to these traces. It is not recommended to use high-density interconnect systems, or micro-vias, on these signals. The use of blind or buried vias should be limited to the low -current signals only. The use of normal thermal vias is at the discretion of the designer. Keep the w iring traces from the IC to the MOSFET gate and source as short as possible and capable of handling peak currents of 2A. Minimize the area w ithin the gatesource path to reduce stray inductance and eliminate parasitic ringing at the gate. Locate small critical components, like the soft-start capacitor and current sense resistors, as close as possible to the respective pins of the IC. The FAN5236 utilizes advanced packaging technology w ith lead pitch of 0.6mm. High-performance analog semiconductors utilizing narrow lead spacing may require special considerations in design and manufacturing. It is critical to maintain proper cleanliness of the area surrounding these devices. www.onsemi.com 17 FAN5236 -- Dual Mobile-Friendly DDR / Dual-Output PWM Controller For the high-side MOSFET, V DS = V IN, w hich can be as high as 20V in a typical portable application. Care should be taken to include the delivery of the MOSFET's gate pow er (PGATE) in calculating the pow er dissipation required for the FAN5236: FAN5236 -- Dual Mobile-Friendly DDR/Dual-Output PWM Controller Physical Dimensions Figure 19. 28-Lead, Thin Shrink Outline Package Package drawings are provided as a service to customers considering ON Semiconductor components. Drawings may change in any manner without notice. Please note the revision and/or date on the drawing and contact an ON Semiconductor representative to verify or obtain the most recent revision. Package specifications do not expand the terms of ON Semiconductor's worldwide terms and conditions, specifically the warranty therein, which covers ON Semiconductor products. www.onsemi.com 18 FAN5236 -- Dual Mobile-Friendly DDR/Dual-Output PWM Controller ON Semiconductor and the ON Semiconductor logo are trademarks of Semiconductor Components Industries, LLC dba ON Semiconductor or its subsidiaries in the United States and/or other countries. ON Semiconductor owns the rights to a number of patents, trademarks, copyrights, trade secrets, and other intellectual property. A listing of ON Semiconductor's product/patent coverage may be accessed at www.onsemi.com/site/pdf/Patent-Marking.pdf. ON Semiconductor reserves the right to make changes without further notice to any products herein. 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