FAN5236MTCX_NA3C246 - ON SEMICONDUCTOR

November-2017, R ev. 2 FAN5236/D

FAN5236 — Dual Mobile-Friendly DDR / Dual-Output PWM Controller

FAN5236

Du a l Mo b ile -Fr iendly DDR / Dual-Output PW M Cont r oller

Features

 Highly Flexible, Dual Synchronous Swi tching PWM

Controller that Includes Modes for:

- DDR Mode w i th In-phase Operati on for Reduced

Channel Interference

- 90° Phase-shifted, Two-stage DDR Mode for

Reduced Input Ripple

- Dual Independent Regulators, 180° Phase Shifted

 Complete DDR Memory Pow er Solution

- VTT Tracks VDDQ/2

- VDDQ/2 Buffered Reference Output

 Lossless Current Sensing on Low-side MOSFET or

Precision Over-Current Using Sense Resistor

 VCC Under-Voltage Lockout

 Converters can Operate from +5V or 3.3V or Battery

Pow er Input (5V to 24V)

 Excellent Dynamic Response with Voltage

Feedforw ard and Average-Current-Mode Control

 Pow er-Good Signal

 Supports DDR-II and HSTL

 Light-Load Hysteretic Mode Maximizes Efficiency

 TSSOP28 Package

Applications

 DDR VDDQ and VTT Voltage Generation

 Mobile PC Dual Regulator

 Server DDR Power i

 Hand-hel d PC Pow er

Related Resources

 http://www.onsemi.com/pub/Collateral/AN-

6002.pdf.pdf

 http://www .onsemi.com/pub/Collateral/AN-

1029.pdf.pdf

Description

The FAN5236 PWM controller provides high efficiency and

regulation f or tw o output v oltages adjustable i n the range

of 0.9V to 5.5V required to power I/O, chip-sets, and

memory banks in high-perf or manc e notebook c omputers,

PDAs, and Internet applianc es. Sync hronous rec tif ication

and hysteretic operation at light loads contribute to high

efficiency over a wide range of loads. The Hysteretic

Mode can be disabled separately on each PWM converter

if PWM Mode is desired for all load levels. Efficiency is

enhanced by using MOSFET RDS(ON) as a current-sense

component.

Feedforw ard ramp modulation, average-current-mode

control scheme, and internal feedback compensation

provide fast response to load transients. Out-of-phase

operation with 180-degree phase shift reduces input

current ripple. The controller can be transformed into a

complete DDR memory power supply solution by

activating a designated pin. In DDR mode, one of the

channels tracks the output voltage of another channel and

provides output current sink and source capability —

essential for proper poweri ng of DDR chips. The buffered

ref er ence voltage required by this type of memory is also

provided. The FAN5236 monitors these outputs and

generates separate PGx (power good) s ignals when the

soft-start is completed and the output is within ±10% of

the s et point. Built-in over-vol tage protecti on prevents the

output voltage from going above 120% of the set point.

Normal operation is automatically restored when the over-

voltage conditions cease. Under-voltage protection

latc hes the c hip of f when output drops below 75% of the

set value after the soft-star t sequence for this output is

completed. An adjustable over-current function monitors

the output current by sensi ng the vol tage drop across the

low er MOSFET. If precision current-sensing is required,

an external current-sense resistor may be used.

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FAN5236 — Dual Mobile-Friendly DDR / Dual-Output PWM Controller

Ordering Information

Part Number B Operating

Temperature

Range Package Packing

Method

FAN5236MTCX -10 to +85°C 28-Lead Thin-Shrink Small-Outli ne Package (TSSOP) Tape and Reel

Block Diagrams

FAN5236VIN(BATTERY)

= 5 to24V

OUT1

VOUT1

=2.5V

DDR

OUT1

OUT2

VOUT 2

=1.8V

OUT2

PWM 1

PWM 2

ILIM1

ILIM2/

REF2

VCC

Figure 1. Dual-Output Regulator

FAN5236

OUT1

VDDQ

=2.5V

DDR

OUT1

OUT2

VTT =

VDDQ /2

OUT2

PWM 1

PWM 2

ILIM1

PG2/REF

VCC

ILIM2/REF2

VIN (BATTERY)

= 5 to24V

1.25V

Figure 2. Complete DDR Memory Power Supply

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FAN5236 — Dual Mobile-Friendly DDR / Dual-Output PWM Controller

Pin Configuration

Figure 3. Pin Configuration

Pin Definitions

Pi n # Name Description

1 AGND Analog Ground. This is the signal ground reference for the IC. All vol tage levels are measured

with respect to this pin.

2 LDRV1 Low-Side Drive. The l ow-side (lower) MOSFET driver output. Connect to gate of low-side

MOSFET.

27 LDRV2

3 PGND1 Power Ground. The return for the low-side MOSFET driver. Connect to source of l ow-side

MOSFET.

26 PGND2

4 SW1 Switching Node. Return for the high-side MOSFET driver and a current sense input. Connect

to source of high-si de MOSFET and low-side MOSFET drai n.

25 SW2

5 HDRV1 High-Side Drive. High-si de (upper) MOSFET driver output. Connect to gate of high-side

MOSFET.

24 HDRV2

6 BOOT1 BOOT. Positive supply for the upper MOSFET dri ver. Connect as show n in Figure 4.

23 BOOT2

7 ISNS1 Current-Sense Input. Monitors the vol tage drop across the lower MO SFET or external sense

resistor for current feedback.

22 ISNS2

8 EN1 Enable. Enables operati on when pulled to logic HIGH. Toggl ing EN resets the regulator after a

l atched fault condition. These are CMOS inputs whose state i s i ndeterminate if left open.

21 EN2

9 FPWM1 Forced PWM Mode. When logic LOW, inhibits the regulator from entering Hysteretic Mode;

otherwise tie to VOUT. The regul ator uses VOUT on this pin to ensure a smooth transition from

Hystereti c Mode to P WM Mode. When VOUT is expected to exceed VCC, ti e to VCC.

20 FPWM2

10 VSEN1 Output Voltage Sense. The feedback from the outputs. Used for regul ation as w ell as PG,

under-voltage, and over-voltage protection and monitori ng.

19 VSEN2

11 ILIM1 Current Limit 1. A resistor from this pin to GND sets the current limit.

12 SS1 Soft Start. A capacitor from this pin to GND programs the slew rate of the converter during

i niti alization. Duri ng initialization, this pin is charged w i th a 5mA current source.

17 SS2

NS1

EN1

SS1

236

NS2

VSE

REF

SS2

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FAN5236 — Dual Mobile-Friendly DDR / Dual-Output PWM Controller

Pin Descriptions

(Continued)

Pi n # Name Description

13 DDR DDR Mode Control. HIGH = DDR Mode. LOW = two separate regulators operating 180° out of

phase.

14 VIN

I nput Voltage. Normally connected to battery, providing voltage feedforward to set the

amplitude of the internal oscillator ramp. W hen usi ng the IC for tw o-step conversion from 5V

i nput, connect through 100KΩ resistor to ground, which sets the appropriate ramp gain and

synchronizes the channel s 90° out of phase.

15 PG1 Power Good Flag. An open-drain output that pulls LOW w hen VSEN is outside a ±10% range

of the 0.9V reference.

16 PG2 /

REF2OUT

Power Good 2. When not i n DDR Mode, open-drain output that pul ls LOW when the VOUT is out

of regulation or i n a faul t condi tion.

Reference Out 2. W hen in DDR Mode, provides a buffered output of REF2. Typically used as

the VDDQ/2 reference.

18 ILIM2 / REF2 Current Li mit 2. When not in DDR Mode, a resistor from this pin to GND sets the current limit.

Reference for reg #2 when in DDR Mode. Typically set to VOUT1 / 2.

28 VCC VCC. This pin powers the chip as well as the LDRV buffers. The IC starts to operate when

voltage on this pi n exceeds 4.6V (UVLO rising) and shuts down w hen i t drops below 4.3V

(UVLO falling).

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FAN5236 — Dual Mobile-Friendly DDR / Dual-Output PWM Controller

Absolute Maximum Ratings

Stres ses exc eeding the abs olute maximum r atings may damage the dev ic e. The dev ic e may not f unction or be operable

above the rec ommended oper ating c onditions and str essing the parts to these levels is not recommended. In addition,

extended ex posur e to stres ses above the rec ommended oper ating conditions may af f ec t device reliability. The abs olute

maximum ratings are stress ratings only.

Symbol Parameter Min. Max. Unit

VCC VCC Supply Voltage 6.5 V

VIN VIN Supply Voltage 27 V

BOOT, SW, ISNS, HDRV 33 V

BOOTx to SWx 6.5 V

All Other Pins -0.3 VCC+0.3 V

TJ Junction Temperature -40 +150 ºC

TSTG Storage Temperature -65 +150 ºC

TL Lead Temperature (Solderi ng,10 Seconds) +300 ºC

Recommended Operating Conditions

The Recommended Operating Conditions table defines the conditions for actual device operation. Recommended

operating conditions are specified to ensure optimal performance to the datasheet specifications. ON Semic onductor

does not recommend exceeding them or designing to Absolute Maximum Ratings.

Symbol Parameter Min. Typ. Max. Unit

VCC VCC Supply Voltage 4.75 5.00 5.25 V

VIN VIN Supply Voltage 24 V

TA Ambient Temperature -10 +85 °C

ΘJA Thermal Resistance, J unction to Ambient 90 °C/W

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FAN5236 — Dual Mobile-Friendly DDR / Dual-Output PWM Controller

Electrical Characteristics

Recommended operating condi tions, unless otherwise noted.

Symbol Parameter Conditions Min. Typ. Max. Units

Power Suppl ies

IVCC VCC Current LDRV, HDRV Open, VSEN Forced Above

Regulation Point 2.2 3.0 µA

Shutdown (EN-0) 30 µA

ISINK VIN Current, Sinking VIN = 24V 10 30 µA

ISOURCE VIN Current, Sourcing VIN = 0V -15 -30 µA

ISD VIN Current, Shutdown 1 µA

VUVLO UVLO Threshold Rising VCC 4.30 4.55 4.75 V

Falling 4.10 4.25 4.45 V

VUVLOH UVLO Hysteresis 300 mV

Oscillator

fosc Frequency 255 300 345 KHz

VPP Ramp Amplitude VIN = 16V 2 V

VIN = 5V 1.25 V

VRAMP Ramp Offset 0.5 V

G Ramp / VIN Gain VIN ≤ 3V 125 mV/V

1V < VIN < 3V 250 mV/V

Reference and Soft Sta rt

VREF Internal Reference Voltage 0.891 0.900 0.909 V

ISS Soft-Start Current At Startup 5 µA

VSS Soft-Start Complete

Threshold 1.5 V

PWM Con verters

Load Regulators IOUTX from 0 to 5A, VIN from 5 to 24V -2 +2 %

ISEN VSEN Bias Current 50 80 120 nA

VOUT Pin Input Impedance 45 55 65 KΩ

UVLOTSD Under-Vol tage Shutdown % of Set Point, 2µs Noise Filter 70 75 80 %

UVLO Over-Voltage Threshold % of Set Point, 2µs Noise Filter 115 120 125 %

ISNS Over-Current T hreshol d RILIM= 68.5KΩ, Figure 12 112 140 168 µA

Output Drivers

HDRV Output Resistance Sourcing 12.0 15.0 Ω

Sinking 2.4 4.0

LDRV Output Resistance Sourcing 12.0 15.0 Ω

Sinking 1.2 2.0

Continued on following page…

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FAN5236 — Dual Mobile-Friendly DDR / Dual-Output PWM Controller

Electrical Characteristics (Continued)

Symbol Parameter Conditions Min. Typ. Max.

Units

Power-Good Output and Control Pins

Lower T hreshol d % of Set Point, 2µs Noise Filter -86 -94 %

Upper Threshold % of Set Point, 2µs Noise Filter 108 116 %

PG Output Low IPG = 4mA 0.5 V

Leakage Current VPULLUP = 5V 1 µA

PG2/REF2OUT Voltage DDR = 1, 0mA < IREF2OUT ≤10mA 99.00 1.01 % VREF2

DDR, EN Inputs

VINH Input High 2 V

VINL Input Low 0.8 V

FPWM Inputs

FPWM Low 0.1 V

FPWM High FPWM Connected to Output 0.9 V

Block Diagram

Figure 4. IC Block Diagram

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FAN5236 — Dual Mobile-Friendly DDR / Dual-Output PWM Controller

Typica l Application

FPWM1(VOUT1)

C6A

VDDQ

=2.5V

DDR

Q1B

C8A

VTT =

VDDQ/2

PWM 1

PWM 2

ILIM1

PG2/REF

VCC

Q2B

D1 +5

23 D2 +5

19 VSEN2

ISNS2

AGND

26 PGND2

SW2

HDRV2

ISNS1

PGND2

EN1 8

EN2 21

Q1A

Q2A

FPWM2

10 VSEN1

LDRV1

BOOT2

HDRV1

SW1

BOOT1

VIN

LDRV2

PG1 15

VIN (BATTERY)

= 5 to24V

SS1 12

SS2 17

C6B

C8B

1.25V at 10mA

ILIM2/REF2

Figure 5. DDR Regulator App lication

Table 1. DDR Regulator BOM

Description Qty.

Ref. Vendor Part Num ber

Capacitor 68µf, Tantal um, 25V, ESR 150mΩ 1 C1 AVX TPSV686*025#0150

Capacitor 10nf, Ceramic

C2, C3

Any

Capacitor 68µf, Tantalum, 6V, ESR 1.8

Ω

AVX

TAJB686*006

Capacitor 150nF, Ceramic

C5, C7

Any

Capacitor 180µf, Specialty Pol ymer 4V, ESR 15m

Ω

C6A, C6B

Panasonic

EEFUE0G181R

Capacitor 1000µf, Speci alty Polymer 4V, ESR 10mΩ 1 C8 Kemet T510E108(1)004AS4115

Capacitor 0.1µF, Ceramic

Any

18.2K

Ω

, 1% Resi stor

R1, R2

Any

1.82KΩ, 1% Resistor

Any

56.2K

Ω

, 1% Resi stor

Any

10KΩ, 5% Resistor 2 R4 Any

3.24K

Ω

, 1% Resi stor

Any

1.5K

Ω

, 1% Resi stor

R7, R8

Any

Schottky Diode 30V

D1, D2

ON Semiconductor

BAT54

Inductor 6.4µH, 6A, 8.64m

Ω

Panasonic

ETQ-P6F6R4HFA

Inductor 0.8µH, 6A, 2.24mΩ 1 L2 Panasonic ETQ-P6F0R8LFA

Dual MOSFET with Schottky

Q1, Q2

ON Semiconductor

FDS6986AS(1)

DDR Controller

ON Semiconductor

FAN5236

Note:

1. Suitable for typical notebook computer application of 4A continuous, 6A peak for VDDQ. If continuous operation above

6A i s required, use single SO-8 packages. For more information, refer to the Power MOSFET Selection Section and

use AN-6002 for design calculations.

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FAN5236 — Dual Mobile-Friendly DDR / Dual-Output PWM Controller

Typica l Applications (Continued)

FPWM1(VOUT1)

DDR

Q1B

1.8V at 6A

PWM 1

PWM 2

ILIM1

VCC

ILIM2

Q2B

D1 +5

D2 +5

19 VSEN2

ISNS2

PG1 15

26 PGND2

SW2

HDRV2

ISNS1

PGND2

Q1A

Q2A

FPWM2

10 VSEN1

LDRV1

BOOT2

HDRV1

SW1

BOOT1

VIN

LDRV2

VIN

2.5V at 6A

PG2 16

EN2 21

VIN (BATTERY)

= 5 to 24V C9

SS2 17

AGND

EN1 8

SS1 12

Figure 6. Dual Regulator Application

Table 2. DDR Regulator BOM

Item

Description

Qty.

Ref.

Vendor

Part Number

Capacitor 68µf, Tantalum, 25V, ESR 95m

Ω

AVX

TPSV686*025#095

Capacitor 10nf, Ceramic

C2, C3

Any

Capacitor 68µf, Tantalum, 6V, ESR 1.8

Ω

AVX

TAJB686*006

4 Capacitor 150nF, Ceramic 2 C5, C7 Any

Capacitor 330µf, Poscap, 4V, ESR 40m

Ω

C6, C8

Sanyo

4TPB330ML

Capacitor 0.1µF, Ceramic

Any

56.2KΩ, 1% Resistor

R1, R2

Any

10K

Ω

, 5% Resi stor

Any

13 3.24KΩ, 1% Resistor 1 R4 Any

14 1.82KΩ, 1% Resistor 3

R5, R8,

R9 Any

1.5K

Ω

, 1% Resi stor

R6, R7

Any

27 Schottky Diode 30V 2 D1, D2 ON Semiconductor BAT54

Inductor 6.4µH, 6A, 8.64mΩ

L1, L2

Panasonic

ETQ-P6F6R4HFA

Dual MOSFET with Schottky

ON Semiconductor

FDS6986AS(2)

DDR Controller

ON Semiconductor

FAN5236

Note:

2. If currents above 4A continuous are required, use si ngle SO-8 packages. For more information, refer to the Power

MOSFET Selection Section and AN-6002 for design calculations.

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FAN5236 — Dual Mobile-Friendly DDR / Dual-Output PWM Controller

DDQ

CLK

DDQ

CLK

DDQ

CLK

Circuit Description

Overview

The FAN5236 is a multi-mode, dual-channel PWM

controller intended for graphic chipset, SDRAM, DDR

DRAM, or other low -voltage power applicati ons in modern

notebook, desktop, and sub-notebook PCs. The IC

integrates control circuitry for two synchronous buck

conv erters . The output v oltage of eac h controller c an be

set in the range of 0.9V to 5.5V by an ex ternal res is tor

divider.

The two s ync hronous buck conver ters can oper ate from

either an unregulated DC source (such as a notebook

battery), w ith voltage ranging from 5.0V to 24V, or from a

regulated sy stem rail of 3.3V to 5.0V . In either mode, the

IC is biased from a +5V source. The PWM modulators use

an average-current-mode control with input voltage

feedforw ard for simplified feedback loop compensation

and improved line regulation. Both PWM controllers have

integrated feedback loop compens ation that r educes the

external components needed.

Depending on the load level , the converters can operate in

fixed-frequency PWM Mode or in a Hysteretic Mode.

Sw itch-over from PWM to Hy steretic Mode improv es the

converters’ efficiency at light loads and prolongs batter y

run time. In Hysteretic Mode, comparators are

synchronized to the main clock, w hich allows seamless

transition between the modes and reduces channel-to-

channel inter action. The Hy ster etic Mode c an be inhibited

independently for each channel if variable frequency

operation is not desired.

The FAN5236 can be configured to operate as a complete

DDR solution. When the DDR pin is s et HIGH, the sec ond

channel provides the capability to track the output voltage

of the first channel. The PWM2 converter is prevented

f rom going into Hystereti c Mode if the DDR pin is set HIGH.

In DDR Mode, a buffered reference voltage (buffered

voltage of the REF2 pin), r equired by DDR memory c hips ,

i s provided by the PG2 pin.

Converter Modes and Synchronization

Table 3. Con verter Modes and Synchronization

Mode VIN VIN Pin DDR

PWM 2 w .r.t.

PWM1

DDR1 Battery VIN HIGH IN PHASE

DDR2 +5V R to GND HIGH +90°

DUAL ANY VIN LOW +180°

When used as a dual converter, as show n in Figure 6,

out-of-phase operation w ith 180-degree phase shift

reduces input current ripple.

For “tw o-step” conversion (w here the VTT is conv erted

from VDDQ as in Figure 5) used in DDR Mode, the duty

cycle of the second converter is nominally 50% and the

optimal phasing depends on V IN. The objective is to keep

noise generated from the switching transition in one

conv erter f r om inf luencing the "dec ision" to s witch in the

other converter.

When VIN is from the battery, it’s typically higher than

7.5V . A s s hown in Figure 7, 180° operation is undesirable

because the turn-on of the VDDQ conv erter occ urs very

near the deci sion point of the VTT converter.

Figure 7. Noise-S usceptible 180° P hasing for DDR1

In-phase operation is optimal to reduce inter-converter

interference when VIN is higher than 5V (w hen VIN is

f rom a batter y), as shown in Figure 8. Because the duty

cycle of PWM1 (generating VDDQ) is short, the sw itching

point oc cur s far away f rom the dec ision point for the VTT

regulator, whose duty cycle is nominally 50%.

Figure 8. Optimal In-Phase Opera tion for DDR1

When

VIN ≈

5V , 180° phas e-shif ted operation can be rejected f or the

reasons demonstrated in Fi gure 7.

In-phase operation with VIN ≈ 5V is even worse, since the

sw itch point of either converter occurs near the sw itch

point of the other converter, as seen in Figure 9. In this

case, as VIN is a little higher than 5V, it tends to c ause

early termination of the V TT pulse width. Conv ers ely , the

VTT sw itc h point c an caus e early ter mination of the V DDQ

pul se width when VIN is slightly lower than 5V.

Figure 9. Noise-Susceptible In-P hase Operation

for DDR2

These problems are solved by delaying the second

converter’s clock by 90°, as show n in Figure 10. In this

way , all switching trans itions in one c onverter take place

far away from the decisi on points of the other converter.

DDQ

CLK

Figure 10. Optimal 90° Phasing for DDR

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FAN5236 — Dual Mobile-Friendly DDR / Dual-Output PWM Controller

Initialization and Soft Start

Assuming EN is HIGH, FAN5236 is initialized w hen VCC

exceeds the rising UVLO threshold. Should VCC drop

below the UVLO threshold, an internal power-on reset

function disables the chip.

The voltage at the positive input of the error amplifier is

l imited by the voltage at the S S pin, w hich is charged w i th

a 5µA current source. Once CSS has charged to VREF

(0.9V ) the output v oltage is i n regul ation. The time it takes

SS to reach 0.9V is:

xC9.0

tSS

.0 =

(1)

where t0.9 is in seconds if CSS is in µF.

When SS reaches 1.5V, the power-good outputs are

enabled and Hy ster etic Mode is allowed. The converter is

forced into PWM Mode during soft-start.

Operation Mode Control

The mode-control circuit changes the converter mode

from PWM to hysteretic and vice versa, based on the

voltage polar ity of the SW node when the lower MO SFET

i s conducting and just before the upper MOSFET turns on.

For continuous inductor current, the SW node is negativ e

when the lower MOSFET is conducting and the

converters operate in fixed-frequency PWM Mode, as

show n i n Figure 11. T his mode achieves high efficiency at

nominal load. When the load current decreases to the

point w here the inductor c urr ent f low s through the l ower

MOSFET in the ‘rev erse’ direc tion, the SW node bec omes

positive and the mode is changed to hysteretic, w hich

achieves higher ef ficiency at low currents by decreasi ng

the effective sw i tchi ng frequency.

To prevent accidental mode change or "mode chatter," the

trans ition f rom PWM to Hys teretic Mode occurs w hen the

SW node is positive for eight consecutive clock cycles, as

show n in Figure 11. The polarity of the SW node is

sampled at the end of the lower MOSFET conduction ti me.

A t the trans ition between PWM and Hy steretic Mode, the

upper and lower MOSFETs are turned off. The phase

node “rings” based on the output inductor and the

paras itic capac itanc e on the phase node and s ettles out

at the value of the output voltage.

The boundary value of inductor current, w here current

becomes discontinuous, can be estimated by the

following expression:











−

INOUTSW

OUTOUTIN

)DIS(LOAD VLF2 V)VV(

(2)

Figure 11. Transitioning Between PWM and Hysteretic Mode

Hysteretic Mode

Conversely, the transition from Hysteretic Mode to PWM

Mode occurs w hen the SW node is negative for eight

consecutive cycle s.

A sudden increase in the output current causes a change

from Hys teretic to PW M Mo d e . This l oad increase causes

an instantaneous decrease in the output voltage due to

the v oltage drop on the output c apacitor ESR. If the load

caus es the output voltage (as pres ented at V SNS) to drop

below the hys teretic regulation level (20mV below V REF),

the mode i s changed to PWM on the next clock cycle.

In Hysteretic Mode, the PWM comparator and the error

amplifier that provide control in PWM Mode are inhibited

and the hysteretic comparator is activated. In Hysteretic

Mode, the low-side MOSFET is operated as a

synchronous rectifier, where the voltage across VDS(ON) is

monitored and sw itched off w hen VDS(ON) goes positive

(current flowing back from the load), allowing the di ode to

bl ock reverse conduction.

The hystereti c comparator initiates a PFM signal to turn on

HDRV at the risi ng edge of the next oscillator clock, w hen

the output voltage (at VSNS) falls below the low er

threshold (10mV below VREF) and terminates the PFM

signal or when V SNS rises over the higher threshold (5mV

above VREF). The switching frequency is primarily a

function of:

 Spread betw een the two hysteretic thresholds

 ILOAD

 Output inductor and capacitor ESR.

PWMModeHystereticMode

HystereticModePWMMode

12345678

CORE

123 45

678

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FAN5236 — Dual Mobile-Friendly DDR / Dual-Output PWM Controller

A transition back to PWM continuous conduction mode

(CCM) mode occurs w hen the inductor current rises

suffic iently to s tay positiv e f or eight cons ecutive cy cles.

This occurs when:











∆

=ESR 2

IHYSTERESIS

)CCM(LOAD

(3)

where ∆VHYSTERESIS = 15mV and ESR is the equivalent

series resistance of COUT.

Because of the di fferent control mechani sms, the value of

the load current where transiti on into CCM operation tak es

place is typically higher compared to the load level at

w hich transition into Hysteretic Mode occurs. Hysteretic

Mode can be disabled by setting the FPWM pi n LOW.

Figure 12. Current Limit / Summing Circuits

Current Process ing Section

The current through the RSENSE resistor (ISNS) is s ampled

(typically 400ns) after Q2 is turned on, as show n in

Figure 12. That current is held and summed with the

output of the error amplifier. This effectively creates a

current-mode control loop. The resistor connected to

ISNSx pin (RSENSE) s ets the gain in the c urrent f eedbac k

loop. The following expression estimates the

recommended value of RSENSE as a function of the

maximum load current (ILOAD(MAX)) and the value of the

MOSFET RDS(ON):











−

•

=100

µA75 RI

R)ON(DS)MAX(LOAD

SENSE

(4)

RSENSE must, however, be kept higher than 700Ω even if

the number calculated comes out to be less than 700Ω.

Setting the Current Limit

A ratio of ISNS is compared to the current established

when a 0.9V internal reference drives the ILIM pin:











+

)ON(DS

SENSE

LOAD

LIM

R)R100(

I11

(5)

Since the tolerance on the current limit is largely

dependent on the ratio of the ex ternal resistor s, it is fairly

accurate if the voltage drop on the sw itching-node side of

RSENSE is an ac curate repr esentation of the load c urr ent.

When using the MOSFET as the sensing element, the

variation of RDS(ON) causes proportional variation in the

ISNS. This value varies from device to device and has a

typical junction temperature c oef f ic ient of about 0.4%/°C

(c onsult the MOSFET datas heet f or ac tual values), s o the

actual current limit set point decreases proportional to

increasing MOSFET die temperature. A factor of 1.6 in the

current limit set point should compensate for MOSFET

RDS(ON) variations, assuming the MOSFET heat sinking

keeps its operati ng die temperature below 125°C.

LDRV

PGND

ISNS R

SENSE

Figure 13. Improving C urrent-Sensing Accuracy

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More accurate sensing can be achieved by using a

res istor (R1) instead of the RDS(ON) of the FET, as s hown

in Figure 13. This approach causes higher losses, but

yields greater ac curac y in both VDROOP and ILIMIT. R1 is a

l ow value resistor (e.g. 10mΩ).

Current limit (ILIMIT) should be set high enough to allow

inductor current to rise in response to an output load

transi ent. Typi cal ly, a factor of 1.2 i s sufficient. In addition,

since ILIMIT is a peak current cut-off value, multiply

ILOAD(MAX) by the inductor ripple current (e.g. 25%). For

example, in Fi gure 6, the target for ILIMIT:

ILIMIT > 1.2 x 1.25 x 1.6 x 6A

≈

14.5A (6)

Duty Cycle Cla mp

During severe load increase, the error amplifier output can

go to its upper limit, pus hing a duty cy cle to almos t 100%

for significant amount of time. This could cause a large

increase of the inductor current and lead to a long

recovery from a transient, over-current condition, or even

to a failure at especially high input voltages. To prevent

this, the output of the err or amplif ier is c lamped to a f ix ed

value after two clock cycles if severe output voltage

excursi on is detected, limiting the maximum duty cycle to:













V4.2

OUT

MAX

(7)

This is designed to not interfere with normal PWM

operation. When FPWM is grounded, the duty cycle clamp

i s di sabled and the maximum duty cycle is 87%.

Gate Driver Section

The adaptive gate control logic translates the internal PWM

control signal into the MOSFET gate drive signals,

providing necessary amplification, level shifting, and

shoot-through protection. It also has functions that

optimize the IC performance over a wide range of

operating conditions. Since MOSFET sw itching time can

vary dramatically from type to type and with the input

voltage, the gate control logic provides adaptive dead time

by monitoring the gate-to-s ource v oltages of both upper

and lower MOSFETs. The lower MOSFET drive is not

turned on until the gate-to-source voltage of the upper

MOSFET has decreased to less than approximately 1V.

Similarly, the upper MOSFET is not turned on until the gate-

to-source voltage of the l ower MOSFET has decreased to

les s than appr oximately 1V . This allow s a w i de variety of

upper and lower MOSFETs to be used without a concern

for simultaneous conduction or shoot-through.

There must be a low-resistance, low -inductance path

between the driver pin and the MOSFET gate for the

adaptive dead-time c ircuit to f unc tion properly. Any delay

along that path subtracts f rom the delay generated by the

adaptive dead-time circuit and shoot-through may occur.

Frequency Loop Compensa tion

Due to the implemented current-mode control, the

modulator has a single-pole response with -1 slope at

frequency determined by l oad:

CR2 1

(8)

where RO i s l oad resi stance; CO is l oad capacitance.

For this ty pe of modulator, a Type-2 compensation circui t

is usually sufficient. To reduce the number of external

components and simplify the design, the PWM controller

has an internally compensated error amplifier. Figure 14

show s a Type-2 amplifier, its response, and the

responses of a current-mode modulator and the

converter. The Type-2 amplif ier, in addition to the pole at

the origin, has a zero-pole pair that causes a flat gain

region at frequenci es between the zero and the pole.

kHz6

CR2 1

(9)

600kHz

C2ππ

(10)

This region is also associated with phase “bump” or

reduc ed phase shift. The amount of phase-shift reduction

depends on the width of the region of flat gain and has a

maximum value of 90°. To further simplify the converter

compensation, the modulator gain is kept independent of

the input voltage variation by providing feedforward of VIN

to the oscillator ramp. The zero frequency, the amplifier

high-frequency gain, and the modulator gain are c hosen

to satisfy most typical applications. The crossover

frequency appears at the point where the modulator

attenuation equals the amplifier high-f requenc y gain. The

sy stem des igner must s pecif y the output f ilter c apacitors

to position the load main pole somewhere w ithin a decade

low er than the amplif ier z ero frequenc y. With this type of

compensation, plenty of phas e mar gin is achieved due to

zero-pole pair phase “boost.”

EA Out

REF

Converter

18 modulator

fP0 fZfP

erroramp

Figure 14. Compensation

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Conditional stability may occur only w hen the main load

pole is positioned too much to the left side on the

frequency axis due to excessi ve output fi lter capacitance.

In this case, the ESR zero placed w ithin the 10kHz to

50kHz range gives s ome additional phase boos t. There is

an opposite trend in mobile appli cations to keep the output

capacitor as small as possible.

If a lar ger inductor v alue or low-ESR v alues are r equired

by the application, additional phase margin can be

achieved by putting a zero at the LC crossover

frequency. T his can be achieved with a capacitor across

the feedback resistor (e.g. R5 from Figure 6), as shown in

Figure 15.

C(OUT)

VOUT

C(Z)R5

VSEN

L(OUT)

Figure 15. Improvin g Pha se Margin

The opti mal value of C(Z) is:

RC(OUT)L(OUT)

C(Z) ×

(11)

Protections

The converter output is monitored and protected against

extreme overload, short-circuit, ov er-v oltage, and under -

voltage conditi ons.

A sus tained ov erload on an output sets the PGx pin LOW

and latches of f the regulator on which the fault occ urs .

Operation can be r estored by cy cling the V CC voltage or

by toggli ng the EN pin.

If VOUT drops below the under-voltage threshold, the

regulator shuts down immediately.

Over-Current Sensing

If the circuit’s current limi t signal (“ILIM det” in Figure 12) is

HIGH at the beginning of a clock cycle, a pulse-skipping

circuit is activated and HDRV is inhibited. The circuit

continues to pulse skip in this manner for the next eight

clock cyc les. If at any time f rom the ninth to the sixteenth

clock cycle, the ILIM det is again reached, the over-

current protection latch is set, disabling the regulator. If

ILIM det does not occur between cycles nine and sixteen,

normal operation is restored and the over-c urr ent cir cuit

resets itself.

Figure 16. Over-Current Protection Waveforms

Over-Voltage / Under-Voltage Protection

Should the V SNS voltage exceed 120% of VREF (0.9V) due

to an upper MOSFET failure or for other reasons, the

over-voltage protection comparator forces LDRV HIGH.

This action actively pulls down the output voltage and, in

the ev ent of the upper MOSFET failure, ev entually blows

the battery fuse. As soon as the output voltage drops

bel ow the threshold, the OVP comparator is disengaged.

This OVP scheme provides a ”soft” crow bar function,

which accommodates severe load transients and does

not invert the output voltage when acti vated — a common

problem for latched OVP schemes.

Similarly, if an output s hort-circuit or severe load transient

causes the output to drop to less than 75% of the

regulation set point, the regulator shuts down.

Over-Temperature Protection

The chip incorporates an over-temperature protection

circuit that shuts the chip dow n if a die temperature of

about 150°C is reached. Normal operation is restored at

di e temperature below 125°C with internal power-on reset

asserted, resulting in a full soft-start cycle .

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Design a nd Component Selection Guidelines

As an initial step, define operating input voltage range,

output voltage, and minimum and maximum load currents

for the control ler.

Setting the Output Voltage

The internal reference voltage is 0.9V. The output is

divided dow n by a voltage divider to the VSEN pin (for

example, R5 and R6 in Figure 5). The output voltage

therefore is:

.0V

6RV9.0

OUT

−

(12)

To minimize noise pic kup on this node, k eep the resistor to

GND (R6) below 2K; for example, R6 at 1.82KΩ. Then

choose R5:

( )

K24.3

9.0 9.0VK82.1

5R OUT =

−Ω

(13)

For DDR applications converting from 3.3V to 2.5V or

other applications requiring high duty cycles, the duty

cycle clamp must be disabled by tying the converter’s

FPWM to GND. When converter’s FPWM is at GND, the

converter’s maximum duty cycle is greater than 90%.

When using as a DDR c onverter w ith 3.3V input, set up

the converter for in-phase synchronization by tying the

VIN pin to +5V.

Output Inductor Selection

The minimum practical output inductor value keeps

inductor current just on the boundary of continuous

conduc tion at s ome minimum load. The indus try s tandard

practice is to choose the minimum current somew here

f rom 15% to 35% of the nominal current. At light load, the

contr oller c an automatic ally switch to Hy steretic Mode of

operation to sustain high efficiency. The following

equations help to choose the proper value of the output

filter inductor:

ESR

12I OUT

MIN

∆

×=∆ =

(14)

where ∆I is the inductor ripple current and ∆VOUT is the

maximum ripple allowed:

OUT

OUTIN V

If VV

L×

∆×

−

(15)

for thi s example, use:

KHz300f A2.1A6•%20I

5.2V,20V

OUTIN

==∆

(16)

therefore:

µH6L ≈

(17)

Output Capacitor Selection

The output capacitor serves two major functions in a

sw itc hing power supply. A long with the inductor, it filters

the s equence of pulses produc ed by the s witcher and it

supplies the load trans ient c urr ents. The output c apacitor

requirements are us ually dictated by ESR, induc tor r ipple

current (∆I), and the allowable ripple voltage (∆V):

ESR ∆

∆

(18)

In addition, the capacitor’s ESR must be low enough to

allow the converter to stay in regulation during a load

step. The ripple voltage due to ESR for the c onverter in

Figure 6 is 120mV PP. Some additional ripple appears due

to the capacitance val ue itself:

SWOUT

V×

∆

=∆

(19)

which is only about 1.5mV, f or the c onverter in Figure 6,

and can be ignored.

The capacitor must also be rated to w ithstand the RMS

current, which is approximately 0.3 X (∆I), or about

400mA for the converter in Figure 6. High-frequency

decoupling capacitors should be placed as close to the

l oads as physically possi ble.

Input Capacitor Selection

The input capacitor should be selected by its ripple

current rating.

Two-Stage Converter Case

In DDR Mode (s hown in Figure 5) , the V TT pow er i nput is

capacitor ripple current is produced by the VDDQ

converter. A conservativ e estimate of the output cur rent

required for the 2.5V regulator is:

II VTT

VDDQREGI +=

(20)

As an example, if the average IVDDQ is 3A and av erage

IVTT is 1A, IVDDQ current is about 3.5A. If average input

voltage i s 16V, RMS input ripple current is:

)MAX(OUTRMS

II −=

(21)

where D i s the duty cycle of the PW M1 converter:

5.2

OUT =<

(22)

therefore:

A49.1

5.2

.3I

RMS













−=

(23)

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Dual Co nverter 180° Phased

In dual mode (show n in Figure 6), both converters

contr ibute to the c apacitor input r ipple c urr ent. With each

conv erter operating 180° out of phas e, the RMS currents

add i n the following fashion:

III 2

)

RMS

)1(RMSRMS +=

(24)

( )

()

1RMS

DDI

DDII −+−=

(25)

w hich, for the dual 3A converters show n in Figure 6,

calculates to:

RMS

(26)

Power MOSFET Selecti on

Losses in a MOSFET are the sum of its sw itching (PSW)

and conduction (PCOND) losses.

In typical applications, the FAN5236 converter’s output

voltage is low with respect to its input voltage. Therefore,

the lower MOSFET (Q2) is conducting the full load current

f or mos t of the c yc le. Q2 should therefore be selected to

minimize conduc tion loss es, ther eby selecting a MOSFET

w ith low RDS(ON).

In co ntrast, the high-side MOSFET (Q1) has a shorter duty

cycle and it’s conduction loss has less impact. Q1,

however, sees most of the sw itching losses, so Q1’s

primary selection criteria should be gate charge.

High-Side Losses

Figur e 17 shows a MOSFET’s sw itchi ng interval, w ith the

upper graph being the voltage and current on the drain-to-

sourc e and the lower graph detailing V GS v s. time w ith a

constant current charging the gate. The X-axis, therefore,

is also representative of gate charge (QG). CISS = CGD +

CGS and it controls t1, t2, and t4 timing. CGD r eceiv es the

cur rent f r om the gate dr iver dur ing t3 (as VDS is falling) .

The gate char ge (QG) parameter s on the lower graph are

either specified or can be derived from MOSFET

datasheets.

A ss uming sw itc hing losses are about the s ame for both

the rising edge and falling edge, Q1’s sw itching losses

occur during the shaded time w hen the MOSFET has

voltage across i t and current through i t.

These losses are given by:

CONDSWUPPER

PPP +=

(27)

LDS

f t2

2IV











××

(28)

)ON(DSOUT

OUT

COND

××=

(29)

PUPPER is the upper MOSFET’s total losses and PSW and

PCOND are the switching and conduction losses for a given

MOSFET. RDS(ON) is at the maximum junction temperature

(TJ). tS is the switching peri od (rise or fall time), shown as

t2+t3 in Fi gure 17.

t1 t2 t3

4.5V

t4 t5

QG(SW)

VDS

VGS

CISSCGD CISS

Figure 17. Switching Losses and QG

GATE

HDRV

VIN

Figure 18. Drive Equivalent Circuit

The driver’s impedance and CISS determine t2, w hile t3’s

period is controlled by the driver’s impedance and QGD.

Since mos t of tS oc curs when V GS = VSP, use a constant

current assumption for the driver to simplify the

calculation of tS:













−

GATEDRIVER

SPCC

)SW(G

DRIVER

)SW(G

RR VV

(30)

Most MOSFET vendors specify QGD and QGS. QG(SW) can

be determined as:

THGSGD)SW(G QQQQ −+=

(31)

wher e QTH is the gate charge required to get the MO SFET

to its threshold (VTH).

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For the high-side MOSFET, VDS = VIN, which c an be as

high as 20V in a typical portable applic ation. Car e should

be taken to include the delivery of the MOSFET’s gate

power (PGATE) in calculating the pow er dissipation

required for the FAN5236:

SWCCG

ATE

fVQP ××=

(32)

where QG is the total gate charge to reach VCC.

Low-Side Lo sses

Q2, however, switches on or off with its parallel Schottky

diode conducting; therefore VDS ≈ 0.5V. Since PSW is

proportional to VDS, Q2’s sw itching losses are negligible

and Q2 is selected based on RDS(ON) only.

Conduction losses for Q2 are given by:

( )

)ON

(DSOUT

COND RID

××

−=

(33)

wher e RDS(ON) is the RDS(ON) of the MOSFET at the highest

operating junction temperature, and:

OUT

(34)

i s the minimum duty cycl e for the converter.

Since DMIN < 20% for portable computers, (1-D) ≈ 1

produces a conservative result, further simplifying the

calculation.

The maximum power dissipation (PD(MAX)) is a f unc tion of

the maximum allow able die temperature of the low -side

MOSFET, the ΘJA, and the maximum allowable ambient

temperature rise:

)MAX(A)MAX(J

)MAX(D

PΘ

−

(35)

ΘJA depends primarily on the amount of PCB area that can

be devoted to heat sinking (see ON Semiconductor

Application Note AN-1029 — Maximum Power

Enhancement Techniques for SO-8 Pow er MOSFETs).

Layout Considerations

Switching converters, even during normal operation,

produce short pulses of current that could cause

substantial ringing and be a source of EMI if layout

constraints are not observed.

There are two sets of critical components in a DC-DC

converter. The switching power components process

large amounts of energy at high rates and are noise

generators. The low -pow er components responsible for

bi as and feedback functions are sensitive to noise.

A multi-layer printed circuit board is recommended.

Dedicate one solid layer for a ground plane. Dedicate

another solid layer as a power plane and break this plane

i nto smaller islands of common voltage levels.

Notice all the nodes that are subjected to high-dV/dt

voltage sw ing; such as SW, HDRV, and LDRV. All

surrounding circuitry tends to couple the signals from

thes e nodes through s tray capacitance. Do not ov ers iz e

copper traces connected to these nodes. Do not place

traces connected to the feedback components adjacent to

these traces. It is not recommended to use high-density

interconnect systems, or micro-vias, on these signals.

The use of blind or buried vias should be limited to the

low -cur rent s ignals only. The us e of normal thermal v ias

is at the discretion of the designer.

Keep the w iring traces from the IC to the MOSFET gate

and sour ce as s hort as possible and c apable of handling

peak currents of 2A. Minimize the area w ithin the gate-

source path to reduce stray inductance and eliminate

parasitic ringing at the gate.

Locate small critical components, like the soft-start

capacitor and current sense resistors, as close as

possible to the respective pins of the IC.

The FAN5236 utilizes advanced packaging technology

with lead pitch of 0.6mm. High-performance analog

semiconductors utilizi ng narrow lead spacing may require

special considerations in design and manuf actur ing. It is

critical to maintain proper cleanliness of the area

surroundi ng these devices.

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Physic a l Dimensions

Figure 19. 28-Lead, Thin Shrink Outl ine Package

Package drawi ngs are provided as a servi ce to customers considering ON Semiconductor components. Drawings may change

i n any manner w i thout noti ce. Please note the revision and/or date on the drawing and contact an ON Semiconductor

representati ve to verify or obtai n the most recent revi sion. Package speci fi cati ons do not expand the terms of ON

Semiconductor’s worldwide terms and conditi ons, speci fi call y the w arranty therein, w hi ch covers ON Semiconductor

products.

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United States and/or other countries. ON Semiconductor owns the rights to a number of patents, trademark s, copy rights, trade secrets, and other intellectual property . A

listing of ON Semiconductor’s product/patent cov erage may be accessed at ww w.onsemi.com/site/pdf/Patent-Mark ing.pdf. ON Semiconductor reserv es the right to mak e

changes without further notice to any products herein. ON Semiconductor makes no w arranty , representation or guarantee regarding the suitability of its products for any

particular purpose, nor does ON Semiconductor assume any liability arising out of the application or use of any product or circuit, and specifically disclaims any and all

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