MXD1210CWE - Maxim Integrated Products, Inc.

General Description

The MXD1210 nonvolatile RAM controller is a very low-

power CMOS circuit that converts standard (volatile)

CMOS RAM into nonvolatile memory. It also continually

monitors the power supply to provide RAM write protec-

tion when power to the RAM is in a marginal (out-of-tol-

erance) condition. When the power supply begins to

fail, the RAM is write-protected, and the device switch-

es to battery-backup mode.

Applications

Microprocessor Systems

Computers

Embedded Systems

Features

♦Battery Backup

♦Memory Write Protection

♦230µA Operating Mode Quiescent Current

♦2nA Backup Mode Quiescent Current

♦Battery Freshness Seal

♦Optional Redundant Battery

♦Low Forward-Voltage Drop on VCC Supply Switch

♦5% or 10% Power-Fail Detection Options

♦Tests Battery Condition During Power-Up

♦8-Pin SO Available

MXD1210

Nonvolatile RAM Controller

________________________________________________________________

Maxim Integrated Products

VCCI

+5V 1

7VBATT2

GND

VCC

CMOS

RAM

MXD1210

FROM

DECODER

VBATT1

VCCO

PART TEMP RANGE PIN-PACKAGE

MXD1210C/D 0°C to +70°C Dice*

MXD1210CPA 0°C to +70°C 8 PDIP

MXD1210CSA 0°C to +70°C 8 SO

MXD1210CWE 0°C to +70°C 16 Wide SO

MXD1210EPA -40°C to +85°C 8 PDIP

MXD1210ESA -40°C to +85°C 8 SO

MXD1210EWE -40°C to +85°C 16 Wide SO

MXD1210MJA -55°C to +125°C 8 CERDIP

Typical Operating Circuit

Ordering Information

CEO

CEGND

VCCI

VBATT2VBATT1

TOL

VCCO

DIP/SO

TOP VIEW

MXD1210

N.C. N.C.

VCCI

N.C.

VBATT2

N.C.

CEO

N.C.

MXD1210

WIDE SO

VCCO

N.C.

TOL

VBATT1

N.C.

GND

Pin Configurations

19-0154; Rev 2; 11/05

For pricing, delivery, and ordering information, please contact Maxim/Dallas Direct! at

1-888-629-4642, or visit Maxim’s website at www.maxim-ic.com.

Contact factory for dice specifications.

Devices in PDIP and SO packages are available in both lead-

ed and lead-free packaging. Specify lead free by adding the +

symbol at the end of the part number when ordering. Lead free

not available for CERDIP package.

MXD1210

Nonvolatile RAM Controller

2 _______________________________________________________________________________________

ABSOLUTE MAXIMUM RATINGS

RECOMMENDED OPERATING CONDITIONS

(TA= TMIN to TMAX, unless otherwise noted.)

Stresses beyond those listed under “Absolute Maximum Ratings” may cause permanent damage to the device. These are stress ratings only, and functional

operation of the device at these or any other conditions beyond those indicated in the operational sections of the specifications is not implied. Exposure to

absolute maximum rating conditions for extended periods may affect device reliability.

VCCI to GND ..........................................................-0.3V to +7.0V

VBATT1 to GND.....................................................-0.3V to +7.0V

VBATT2 to GND.....................................................-0.3V to +7.0V

VCCO to GND ................................................-0.3V to (VS+ 0.3V)

(VS= greater of VCCI, VBATT1, VBATT2)

Digital Input and Output

Voltages to GND.....................................-0.3V to (VCCI + 0.3V)

Continuous Power Dissipation (TA= +70°C)

8-Pin PDIP (derate 9.09mW/°C above +70°C)..............727mW

8-Pin SO (derate 5.88mW/°C above +70°C).................471mW

8-Pin CERDIP (derate 8.00mW/°C above +70°C).........640mW

16-Pin Wide SO (derate 9.52mW/°C above +70°C) .....762mW

Operating Temperature Range

C Suffix.................................................................0°C to +70°C

E Suffix..............................................................-40°C to +85°C

M Suffix ...........................................................-55°C to +125°C

Storage Temperature Range .............................-65°C to +150°C

Lead Temperature (soldering, 10s) .................................+300°C

PARAMETER SYMBOL CONDITIONS MIN TYP MAX UNITS

TOL = GND 4.75 5.50

Supply Voltage VCCI TOL = VCCO 4.50 5.50 V

Input High Voltage VIH 2.2 V

Input Low Voltage VIL 0.8 V

Battery Voltage VBATT1

VBATT2 1 or 2 batteries (Note 1) 2.0 4.0 V

ELECTRICAL CHARACTERISTICS—Normal Supply Mode, TOL = VCCO

(VCCI = +4.75V to +5.5V, TOL = GND; or VCCI = +4.5V to +5.5V, TOL = VCCO; TA= TMIN to TMAX, unless otherwise noted.)

PARAMETER SYMBOL CONDITIONS MIN TYP MAX UNITS

Supply Current ICCI VCCO, CEO open, VBATT1 = VBATT2 = 3V 0.23 0.5 mA

MXD1210C VCCI -

0.20

MXD1210E VCCI -

0.21

Output Supply Voltage VCCO ICCO1 = 80mA (Note 2)

MXD1210M VCCI -

0.25

MXD1210C 80

MXD1210E 0.23 75

Output Supply Current ICCO VCCI - VCCO ≤ 0.2V (Note 2)

MXD1210M 0.23 65

Input Leakage Current IIL ±1.0 µA

Output Leakage Current IOL ±1.0 µA

High-Level Output Voltage VOH IOH = -1mA 2.4 V

Low-Level Output Voltage VOL IOL = 4mA 0.4 V

TOL = GND 4.50 4.74

VCCI Trip Point VCCTP TOL = VCCO 4.25 4.49 V

MXD1210

Nonvolatile RAM Controller

_______________________________________________________________________________________ 3

Note 1: Only one battery input is required. Unused battery inputs must be grounded.

Note 2: ICCO1 is the maximum average load current the MXD1210 can supply to the memories.

Note 3: ICCO2 is the maximum average load current the MXD1210 can supply to the memories in battery-backup mode.

Note 4: CEO can sustain leakage current only in battery-backup mode.

Note 5: Guaranteed by design.

Note 6: tCE max must be met to ensure data integrity on power loss.

ELECTRICAL CHARACTERISTICS—Battery-Backup Mode

(VCCI < VBATT, positive edge rate at VBATT1, VBATT2 > 0.1V/µs, TA= TMIN to TMAX, unless otherwise noted.)

PARAMETER SYMBOL CONDITIONS MIN TYP MAX UNITS

MXD1210C/E 2 100 nA

Quiescent Current (Note 1) IBATT VCCO, CEO open,

VCCI = 0V MXD1210M 5 µA

Output Supply Current ICCO2 VBATT - VCCO ≤ 0.2V (Notes 3, 4) 300 µA

CEO Output Voltage VOOutput open VBATT -

0.2 V

CAPACITANCE

(TA= TMIN to TMAX, unless otherwise noted.) (Note 5)

PARAMETER SYMBOL CONDITIONS MIN TYP MAX UNITS

Input Capacitance CIN 5pF

Output Capacitance COUT 7pF

VCC POWER TIMING CHARACTERISTICS

(VCCI = +4.75V to +5.5V, TOL = GND; or VCCI = +4.5V to +5.5V, TOL = VCCO, TA= TMIN to TMAX, unless otherwise noted.)

PARAMETER SYMBOL CONDITIONS MIN TYP MAX UNITS

MXD1210C 5 10 20

MXD1210E 5 10 22

CE Propagation Delay tPD RL = 1kΩ, CL = 50pF

MXD1210M 5 10 25

CE High to Power-Fail tPF (Note 5) 0 ns

TIMING CHARACTERISTICS

(VCCI <+4.75V to +5.5V, TOL = GND; or VCCI <+4.5V, TOL = VCCO, TA= TMIN to TMAX, unless otherwise noted.)

PARAMETER SYMBOL CONDITIONS MIN TYP MAX UNITS

Recovery at Power-Up tREC 2520ms

tFTo out-of-tolerance condition 300

VCC Slew-Rate Power-Down tFB Tolerance to battery power 10 µs

VCC Slew-Rate Power-Up tR0µs

CE Pulse Width tCE (Note 6) 1.5 µs

MXD1210

Nonvolatile RAM Controller

4 _______________________________________________________________________________________4 _______________________________________________________________________________________

Pin Description

8-PIN PDIP/SO 16-PIN WIDE SO NAME FUNCTION

12V

CCO Backed-Up Supply to RAM

2 4 VBATT1 Battery 1 Positive Connection

3 6 TOL Tolerance Select Pin

4 8 GND Ground

59CE Chip-Enable Input

611CEO Chip-Enable Output

7 13 VBATT2 Battery 2 Positive Connection

815V

CCI 5V Power Supply to Chip

—1, 3, 5, 7, 10, 12,

14, 16 N.C. No Connection. Not internally connected.

VCCI

VCCO

GND

CEO

GND

FRESHNESS-

SEAL MODE

VOLTAGE LEVEL

DETECTION

BATTERY

TEST

BATTERY

SELECT

CEO

CONTROL

VBATT1

VBATT2

TOL

MXD1210

Figure 1. Block Diagram

MXD1210

Nonvolatile RAM Controller

_______________________________________________________________________________________ 5_______________________________________________________________________________________ 5

Detailed Description

Main Functions

The MXD1210 executes five main functions to perform

reliable RAM operation and battery backup (see the

Typical Operating Circuit

and Figure 1):

1) RAM Power-Supply Switch: The switch directs

power to the RAM from the incoming supply or

from the selected battery, whichever is at the

greater voltage. The switch control uses the same

criterion to direct power to MXD1210 internal cir-

cuitry.

2) Power-Failure Detection: The write-protection

function is enabled when a power failure is

detected. The power-failure detection range

depends on the state of the TOL pin as follows:

Power-failure detection is independent of the bat-

tery-backup function and precedes it sequentially

as the power-supply voltage drops during a typi-

cal power failure.

3) Write Protection: This holds the chip-enable out-

put (CEO) to within 0.2V of VCCI or of the selected

battery, whichever is greater. If the chip-enable

input (CE) is low (active) when power failure is

detected, then CEO is held low until CE is brought

high, at which time CEO is gated high for the

duration of the power failure. The preceding

sequence completes the current RD/WR cycle,

preventing data corruption if the RAM access is a

WR cycle.

4) Battery Redundancy: A second battery is option-

al. When two batteries are connected, the

stronger battery is selected to provide RAM back-

up and to power the MXD1210. The battery-selec-

tion circuitry remains active while in the

battery-backup mode, selecting the stronger bat-

tery and isolating the weaker one. The battery-

selection activity is transparent to the user and

the system. If only one battery is connected, the

second battery input should be grounded.

5) Battery-Status Warning: This notifies the system

when the stronger of the two batteries measures ≤

2.0V. Each time the MXD1210 is repowered (VCCI

>VCCTP) after detecting a power failure, the bat-

tery voltage is measured. If the battery in use is

low, following the MXD1210 recovery period, the

device issues a warning to the system by inhibit-

ing the second memory cycle. The sequence is

as follows:

First access: read memory location n, loc(n) = x

Second access: write memory location n,

loc(n) = complement (x)

Third access: read memory location n, loc(n) = ?

If the third access (read) is complement (x), then the

battery is good; otherwise the battery is not good.

Return to loc(n) = x following the test sequence.

Freshness-Seal Mode

The freshness-seal mode relates to battery longevity

during storage rather than directly to battery backup.

This mode is activated when the first battery is con-

nected, and is defeated when the voltage at VCCI first

exceeds VCCTP. In the freshness-seal mode, both bat-

teries are isolated from the system; that is, no current is

drained from either battery, and the RAM is not pow-

ered by either battery. This means that batteries can be

installed and the system can be held in inventory with-

out battery discharge. The positive edge rate at

VBATT1 and VBATT2 should exceed 0.1V/µs. The bat-

teries will maintain their full shelf life while installed in

the system.

Battery Backup

The

Typical Operating Circuit

shows the MXD1210 con-

nected to write-protect the RAM when VCC is less than

4.75V, and to provide battery backup to the supply.

CONDITION VCCTP RANGE (V)

TOL = GND 4.75 to 4.50

TOL = VCCO 4.50 to 4.25

MXD1210

Nonvolatile RAM Controller

6 _______________________________________________________________________________________

VIH

tPD

tREC

VBATT - 0.2V

VCCI

CEO

4.75V

4.5V

4.25V

Figure 2. Power-Up Timing Diagram

VIH

VIL

tCE

tFB

tPF

tPD

VCCI

CEO

4.75V

4.5V

4.25V

VBATT - 0.2V

Figure 3. Power-Down Timing Diagram

MXD1210

Nonvolatile RAM Controller

_______________________________________________________________________________________ 7

Chip Topography

VBATT1

VCCO

TOL

0.121"

(3.073mm)

0.080"

(2.032mm)

VCCI VBATT2

CEO

GND

TRANSISTOR COUNT: 1436;

LEAVE SUBSTRATE UNCONNECTED.

MXD1210

Nonvolatile RAM Controller

8 _______________________________________________________________________________________

Package Information

(The package drawing(s) in this data sheet may not reflect the most current specifications. For the latest package outline information

go to www.maxim-ic.com/packages.)

SOICN .EPS

PACKAGE OUTLINE, .150" SOIC

21-0041 B

REV.DOCUMENT CONTROL NO.APPROVAL

PROPRIETARY INFORMATION

TITLE:

TOP VIEW

FRONT VIEW

MAX

0.010

0.069

0.019

0.157

0.010

INCHES

0.150

0.007

DIM

0.014

0.004

MIN

0.053A

0.19

3.80 4.00

0.25

MILLIMETERS

0.10

0.35

1.35

MIN

0.49

0.25

MAX

1.75

0.050

0.016L0.40 1.27

0.3940.386D

MINDIM

INCHES

MAX

9.80 10.00

MILLIMETERS

MIN MAX

16 AC

0.337 0.344 AB8.758.55 14

0.189 0.197 AA5.004.80 8

N MS012

SIDE VIEW

H 0.2440.228 5.80 6.20

e 0.050 BSC 1.27 BSC

eBA1

0∞-8∞

VARIATIONS:

MXD1210

Nonvolatile RAM Controller

Maxim cannot assume responsibility for use of any circuitry other than circuitry entirely embodied in a Maxim product. No circuit patent licenses are

implied. Maxim reserves the right to change the circuitry and specifications without notice at any time.

Maxim Integrated Products, 120 San Gabriel Drive, Sunnyvale, CA 94086 408-737-7600 _____________________

Package Information (continued)

(The package drawing(s) in this data sheet may not reflect the most current specifications. For the latest package outline information

go to www.maxim-ic.com/packages.)

PDIPN.EPS