General Description
The MAX7030 crystal-based, fractional-N transceiver is
designed to transmit and receive ASK/OOK data at fac-
tory-preset carrier frequencies of 315MHz or
433.92MHz with data rates up to 33kbps (Manchester
encoded) or 66kbps (NRZ encoded). This device gen-
erates a typical output power of +10dBm into a 50Ω
load and exhibits typical sensitivity of -114dBm. The
MAX7030 features separate transmit and receive pins
(PAOUT and LNAIN) and provides an internal RF switch
that can be used to connect the transmit and receive
pins to a common antenna.
The MAX7030 transmit frequency is generated by a 16-
bit, fractional-N, phase-locked loop (PLL), while the
receiver’s local oscillator (LO) is generated by an inte-
ger-N PLL. This hybrid architecture eliminates the need
for separate transmit and receive crystal reference
oscillators because the fractional-N PLL is preset to be
10.7MHz above the receive LO. Retaining the fixed-N
PLL for the receiver avoids the higher current-drain
requirements of a fractional-N PLL and keeps the
receiver current drain as low as possible. All frequency-
generation components are integrated on-chip, and
only a crystal, a 10.7MHz IF filter, and a few discrete
components are required to implement a complete
antenna/digital data solution.
The MAX7030 is available in a small, 5mm x 5mm, 32-
pin thin QFN package, and is specified to operate over
the automotive -40°C to +125°C temperature range.
Applications
2-Way Remote Keyless Entry
Security Systems
Home Automation
Remote Controls
Remote Sensing
Smoke Alarms
Garage Door Openers
Local Telemetry Systems
Features
♦+2.1V to +3.6V or +4.5V to +5.5V Single-Supply
Operation
♦Single-Crystal Transceiver
♦Factory-Preset Frequency (No Serial Interface
Required)
♦ASK/OOK Modulation
♦+10dBm Output Power into 50ΩLoad
♦Integrated TX/RX Switch
♦Integrated Transmit and Receive PLL, VCO, and
Loop Filter
♦> 45dB Image Rejection
♦Typical RF Sensitivity*: -114dBm
♦Selectable IF Bandwidth with External Filter
♦< 12.5mA Transmit-Mode Current
♦< 6.7mA Receive-Mode Current
♦< 800nA Shutdown Current
♦Fast-On Startup Feature, < 250µs
♦Small, 32-Pin, Thin QFN Package
MAX7030
Low-Cost, 315MHz and 433.92MHz
ASK Transceiver with Fractional-N PLL
Ordering Information
19-3706; Rev 4; 6/12
1
For pricing, delivery, and ordering information, please contact Maxim Direct
at 1-888-629-4642, or visit Maxim’s website at www.maxim-ic.com.
PART TEMP RANGE PIN-PACKAGE
MAX7030_ATJ+ -40°C to +125°C 32 Thin QFN-EP**
Product Selector Guide
PART CARRIER FREQUENCY (MHz)
MAX7030LATJ+ 315
MAX7030HATJ+ 433.92
*
0.2% BER, 4kbps Manchester-encoded data, 280kHz IF BW
+
Denotes a lead(Pb)-free/RoHS-compliant package.
**
EP = Exposed pad.
Note: The MAX7030 is available with factory-preset operating
frequencies. See the
Product Selector Guide
for complete part
numbers.
Pin Configuration, Typical Application Circuit, and
Functional Diagram appear at end of data sheet.
MAX7030
Low-Cost, 315MHz and 433.92MHz
ASK Transceiver with Fractional-N PLL
2
ABSOLUTE MAXIMUM RATINGS
Stresses beyond those listed under “Absolute Maximum Ratings” may cause permanent damage to the device. These are stress ratings only, and functional
operation of the device at these or any other conditions beyond those indicated in the operational sections of the specifications is not implied. Exposure to
absolute maximum rating conditions for extended periods may affect device reliability.
HVIN to GND .........................................................-0.3V to +6.0V
PAVDD, AVDD, DVDD to GND..............................-0.3V to +4.0V
ENABLE, T/R, DATA, AGC0, AGC1,
AGC2 to GND .......................................-0.3V to (VHVIN+ 0.3V)
All Other Pins to GND .............................-0.3V to (V_VDD + 0.3V)
Continuous Power Dissipation (TA= +70°C)
32-Pin Thin QFN (derate 21.3mW/°C
above +70°C).............................................................1702mW
Operating Temperature Range .........................-40°C to +125°C
Storage Temperature Range .............................-65°C to +150°C
Lead Temperature (soldering, 10s) .................................+300°C
Soldering Temperature (reflow) .......................................+260°C
DC ELECTRICAL CHARACTERISTICS
(
Typical Application Circuit
, 50Ωsystem impedance, VAVDD = VDVDD = VHVIN = VPAVDD = +2.1V to +3.6V, fRF = 315MHz or 433.92MHz,
TA= -40°C to +125°C, unless otherwise noted. Typical values are at VAVDD = VDVDD = VHVIN = VPAVDD = +2.7V,
TA= +25°C, unless otherwise noted.) (Note 1)
PARAMETER SYMBOL CONDITIONS MIN TYP MAX UNITS
Supply Voltage (3V Mode) VDD HVIN, PAVDD, AVDD, and DVDD
connected to power supply 2.1 2.7 3.6 V
Supply Voltage (5V Mode) HVIN PAVDD, AVDD, and DVDD unconnected
from HVIN, but connected together 4.5 5.0 5.5 V
fRF = 315MHz 3.5 5.4
Transmit mode, PA off,
VDATA at 0% duty
cycle (Note 2) fRF = 434MHz 4.3 6.7
fRF = 315MHz 7.6 12.3
Transmit mode, VDATA
at 50% duty cycle
(Notes 3, 4) fRF = 434MHz 8.4 13.6
fRF = 315MHz 11.6 19.1
Transmit mode, VDATA
at 100% duty cycle
(Note 2) fRF = 434MHz 12.4 20.4
Receiver 315MHz 6.1 7.9
Receiver 434MHz 6.4 8.3
mA
Deep-sleep
(3V mode) 0.8 8.8
TA < +85°C,
typ at +25°C
(Note 4)
Deep-sleep
(5V mode) 2.4 10.9
µA
Receiver 315MHz 6.4 8.2
Receiver 434MHz 6.7 8.4 mA
Deep-sleep
(3V mode) 8.0 34.2
Supply Current IDD
TA < +125°C,
typ at +125°C
(Note 2)
Deep-sleep
(5V mode) 14.9 39.3
µA
Voltage Regulator VREG VHVIN = 5V, ILOAD = 15mA 3.0 V
DIGITAL I/O
Input-High Threshold VIH (Note 2) 0.9 x
VHVIN V
Input-Low Threshold VIL (Note 2) 0.1 x
VHVIN V
MAX7030
Low-Cost, 315MHz and 433.92MHz
ASK Transceiver with Fractional-N PLL
3
AC ELECTRICAL CHARACTERISTICS
(
Typical Application Circuit
, 50Ωsystem impedance, VPAVDD = VAVDD = VDVDD = VHVIN = +2.1V to +3.6V, fRF = 315MHz or
433.92MHz, TA= -40°C to +125°C, unless otherwise noted. Typical values are at VPAVDD = VAVDD = VDVDD = VHVIN = +2.7V,
TA= +25°C, unless otherwise noted.) (Note 1)
PARAMETER SYMBOL CONDITIONS MIN TYP MAX UNITS
GENERAL CHARACTERISTICS
Frequency Range 315/433.92 MHz
Maximum Input Level PRFIN 0 dBm
fRF = 315MHz (Note 6) 32
Transmit Efficiency 100% Duty
Cycle fRF = 434MHz (Note 6) 30 %
fRF = 315MHz (Note 6) 24
Transmit Efficiency 50% Duty
Cycle fRF = 434MHz (Note 6) 22 %
ENABLE or T/R transition low to high,
transmitter frequency settled to within
50kHz of the desired carrier
200
ENABLE or T/R transition low to high,
transmitter frequency settled to within
5kHz of the desired carrier
350
Power-On Time tON
ENABLE transition low to high, or T/R
transition high to low, receiver startup
time (Note 5)
250
μs
RECEIVER
315MH
z -114
Sensitivity
0.2% BER, 4kbps Manchester
data rate, 280kHz IF BW,
average RF power 434MH
z
-113
dBm
Image Rejection 46 dB
POWER AMPLIFIER
TA = +25°C (Note 4) 4.6 10.0 15.5
TA = +125°C, VPAVDD = VAVDD = VDVDD =
VHVIN = +2.1V (Note 2) 3.9 6.7
Output Power POUT
TA = -40°C, VPAVDD = VAVDD = VDVDD =
VHVIN = +3.6V (Note 4) 13.1 15.8
dBm
Modulation Depth 82 dB
Maximum Carrier Harmonics With output-matching network -40 dBc
Reference Spur -50 dBc
DC ELECTRICAL CHARACTERISTICS (continued)
(
Typical Application Circuit
, 50Ωsystem impedance, VAVDD = VDVDD = VHVIN = VPAVDD = +2.1V to +3.6V, fRF = 315MHz or 433.92MHz,
TA= -40°C to +125°C, unless otherwise noted. Typical values are at VAVDD = VDVDD = VHVIN = VPAVDD = +2.7V,
TA= +25°C, unless otherwise noted.) (Note 1)
PARAMETER SYMBOL CONDITIONS MIN TYP MAX UNITS
Pulldown Sink Current AGC 0- 2, E N ABLE , T/R, D ATA ( V
H V I N
= 5.5V ) 20 µA
Output-Low Voltage VOL ISINK = 500µA 0.15 V
Output-High Voltage VOH ISOURCE = 500µA V
H V IN
- 0.26 V
MAX7030
Low-Cost, 315MHz and 433.92MHz
ASK Transceiver with Fractional-N PLL
4
AC ELECTRICAL CHARACTERISTICS (continued)
(
Typical Application Circuit
, 50Ωsystem impedance, VPAVDD = VAVDD = VDVDD = VHVIN = +2.1V to +3.6V, fRF = 315MHz or
433.92MHz, TA= -40°C to +125°C, unless otherwise noted. Typical values are at VPAVDD = VAVDD = VDVDD = VHVIN = +2.7V,
TA= +25°C, unless otherwise noted.) (Note 1)
PARAMETER SYMBOL CONDITIONS MIN TYP MAX UNITS
PHASE-LOCKED LOOP
Transmit VCO Gain KVCO 340 MHz/V
10kHz offset, 200kHz loop BW -68
Transmit PLL Phase Noise 1MHz offset, 200kHz loop BW -98 dBc/Hz
Receive VCO Gain 340 MHz/V
10kHz offset, 500kHz loop BW -80
Receive PLL Phase Noise 1MHz offset, 500kHz loop BW -90 dBc/Hz
Transmit PLL 200
Loop Bandwidth Receive PLL 500 kHz
Reference Frequency Input
Level 0.5 VP-P
LOW-NOISE AMPLIFIER/MIXER (Note 8)
fRF = 315MHz 1 - j4.7
LNA Input Impedance ZINLNA Normalized to
50fRF = 434MHz 1- j3.3
fRF = 315MHz 50
High-gain state fRF = 434MHz 45
fRF = 315MHz 13
Voltage-Conversion Gain
Low-gain state fRF = 434MHz 9
dB
High-gain state -42
Input-Referred, 3rd-Order
Intercept Point IIP3 Low-gain state -6 dBm
Mixer-Output Impedance 330
LO Signal Feedthrough to
Antenna -100 dBm
RSSI
Input Impedance 330
Operating Frequency fIF 10.7 MHz
3dB Bandwidth 10 MHz
Gain 15 mV/dB
ANALOG BASEBAND
Maximum Data-Filter Bandwidth 50 kHz
Maximum Data-Slicer Bandwidth 100 kHz
Maximum Peak-Detector
Bandwidth 50 kHz
Manchester coded 33
Maximum Data Rate Nonreturn to zero (NRZ) 66 kbps
MAX7030
Low-Cost, 315MHz and 433.92MHz
ASK Transceiver with Fractional-N PLL
5
AC ELECTRICAL CHARACTERISTICS (continued)
(
Typical Application Circuit
, 50Ωsystem impedance, VPAVDD = VAVDD = VDVDD = VHVIN = +2.1V to +3.6V, fRF = 315MHz or
433.92MHz, TA= -40°C to +125°C, unless otherwise noted. Typical values are at VPAVDD = VAVDD = VDVDD = VHVIN = +2.7V,
TA= +25°C, unless otherwise noted.) (Note 1)
Note 1: Supply current, output power, and efficiency are greatly dependent on board layout and PAOUT match.
Note 2: 100% tested at TA= +125°C. Guaranteed by design and characterization overtemperature.
Note 3: 50% duty cycle at 10kHz ASK data (Manchester coded).
Note 4: Guaranteed by design and characterization. Not production tested.
Note 5: Time for final signal detection; does not include baseband filter settling.
Note 6: Efficiency = POUT/(VDD x IDD).
Note 7: Dependent on PCB trace capacitance.
Note 8: Input impedance is measured at the LNAIN pin. Note that the impedance at 315MHz includes the 12nH inductive degenera-
tion from the LNA source to ground. The impedance at 434MHz includes a 10nH inductive degeneration connected from
the LNA source to ground. The equivalent input circuit is 50Ωin series with ~2.2pF. The voltage conversion is measured
with the LNA input-matching inductor, the degeneration inductor, and the LNA/mixer tank in place, and does not include the
IF filter insertion loss.
Typical Operating Characteristics
(
Typical Application Circuit
, VPAVDD = VAVDD = VDVDD = VHVIN = +3.0V, fRF = 433.92MHz, IF BW = 280kHz, 4kbps Manchester encod-
ed, 0.2% BER, TA= +25°C, unless otherwise noted.)
SUPPLY CURRENT vs. SUPPLY VOLTAGE
MAX7030 toc01
SUPPLY VOLTAGE (V)
SUPPLY CURRENT (mA)
3.33.02.72.4
5.8
6.0
6.2
6.4
6.6
6.8
7.0
5.6
2.1 3.6
+85°C
+125°C
+25°C
-40°C
SUPPLY CURRENT vs. RF FREQUENCY
MAX7030 toc02
RF FREQUENCY (MHz)
SUPPLY CURRENT (mA)
425400325 350 375
6.1
6.2
6.3
6.4
6.5
6.6
6.7
6.8
6.0
300 450
+85°C
+125°C
+25°C
-40°C
DEEP-SLEEP CURRENT vs. TEMPERATURE
MAX7030 toc03
TEMPERATURE (°C)
DEEP-SLEEP CURRENT (μA)
1108535 60-10-15
2
4
6
8
10
12
14
16
18
0
-40
VCC = +3.6V
VCC = +3.0V
VCC = +2.1V
RECEIVER
PARAMETER SYMBOL CONDITIONS MIN TYP MAX UNITS
CRYSTAL OSCILLATOR
Crystal Frequency fXTAL (fRF -10.7)
/24 MHz
Frequency Pulling by VDD 2 ppm/V
Crystal Load Capacitance (Note 7) 4.5 pF
MAX7030
Low-Cost, 315MHz and 433.92MHz
ASK Transceiver with Fractional-N PLL
6
BIT-ERROR RATE
vs. AVERAGE INPUT POWER
MAX7030 toc04
AVERAGE INPUT POWER (dBm)
BIT-ERROR RATE (%)
-113-115-117-119
0.1
1
10
100
0.01
-121 -111
fRF = 434MHz
fRF = 315MHz
0.2% BER
SENSITIVITY vs. TEMPERATURE
TEMPERATURE (°C)
SENSITIVITY (dBm)
11085603510-15
-117
-114
-111
-108
-105
-102
-120
-40
MAX7030 toc05
fRF = 434MHz
fRF = 315MHz
RSSI vs. RF INPUT POWER
MAX7030 toc06
RF INPUT POWER (dBm)
RSSI (V)
-10-30-70 -50-90-110
0.2
0.4
0.6
0.8
1.0
1.2
1.4
1.6
1.8
0
-130 10
LOW-GAIN MODE
HIGH-GAIN MODE
AGC SWITCH
POINT
AGC HYSTERESIS: 3dB
RSSI AND DELTA vs. IF INPUT POWER
MAX7030 toc07
IF INPUT POWER (dBm)
RSSI (V)
-10-30-50-70
0.3
0.6
0.9
1.2
1.5
1.8
2.1
0
-90 10
-2.5
-1.5
-0.5
0.5
1.5
2.5
3.5
-3.5
DELTA (%)
RSSI
DELTA
SYSTEM GAIN vs. IF FREQUENCY
MAX7030 toc08
IF FREQUENCY (MHz)
SYSTEM GAIN (dBm)
252015105
-10
0
10
20
30
40
50
-20
030
LOWER SIDEBAND
UPPER SIDEBAND
FROM RFIN
TO MIXOUT
fRF = 434MHz
48dB IMAGE
REJECTION
IMAGE REJECTION vs. TEMPERATURE
MAX7030 toc09
TEMPERATURE (°C)
IMAGE REJECTION (dB)
11085603510-15
44
46
48
42
-40
fRF = 433MHz
fRF = 315MHz
S11 SMITH PLOT OF RFIN
MAX7030 toc12
433MHz
500MHz
400MHz
S11 vs. RF FREQUENCY
MAX7030 toc11
RF FREQUENCY (MHz)
S11 (dB)
450400350300250
-18
-12
-6
0
-24
200 500
433.92MHz
Typical Operating Characteristics (continued)
(
Typical Application Circuit
, VPAVDD = VAVDD = VDVDD = VHVIN = +3.0V, fRF = 433.92MHz, IF BW = 280kHz, 4kbps Manchester encod-
ed, 0.2% BER, TA= +25°C, unless otherwise noted.) RECEIVER
MAX7030
Low-Cost, 315MHz and 433.92MHz
ASK Transceiver with Fractional-N PLL
7
INPUT IMPEDANCE
vs. INDUCTIVE DEGENERATION
MAX7030 toc14
INDUCTIVE DEGENERATION (nH)
REAL IMPEDANCE (Ω)
10
30
40
50
60
70
80
90
20
IMAGINARY IMPEDANCE (Ω)
-210
-200
-190
-180
-170
-160
-150
-220
1 100
fRF = 434MHz
IMAGINARY
IMPEDANCE
REAL IMPEDANCE
PHASE NOISE vs. OFFSET FREQUENCY
MAX7030 toc15
OFFSET FREQUENCY (Hz)
PHASE NOISE (dBc/Hz)
1M100k10k1k
-110
-100
-90
-80
-70
-60
-50
-120
100 10M
fRF = 315MHz
PHASE NOISE vs. OFFSET FREQUENCY
MAX7030 toc16
OFFSET FREQUENCY (Hz)
PHASE NOISE (dBc/Hz)
-110
-100
-90
-80
-70
-60
-50
-120
fRF = 433MHz
1M100k10k1k100 10M
Typical Operating Characteristics (continued)
(
Typical Application Circuit
, VPAVDD = VAVDD = VDVDD = VHVIN = +3.0V, fRF = 433.92MHz, IF BW = 280kHz, 4kbps Manchester encod-
ed, 0.2% BER, TA= +25°C, unless otherwise noted.) RECEIVER
INPUT IMPEDANCE
vs. INDUCTIVE DEGENERATION
MAX7030 toc13
INDUCTIVE DEGENERATION (nH)
REAL IMPEDANCE (Ω)
10
30
40
50
60
70
80
90
20
IMAGINARY IMPEDANCE (Ω)
-280
-270
-260
-250
-240
-230
-220
-290
1 100
fRF = 315MHz
IMAGINARY
IMPEDANCE
REAL IMPEDANCE
MAX7030
Low-Cost, 315MHz and 433.92MHz
ASK Transceiver with Fractional-N PLL
8
Typical Operating Characteristics (continued)
(
Typical Application Circuit
, VPAVDD = VAVDD = VDVDD = VHVIN = +3.0V, fRF = 433.92MHz, IF BW = 280kHz, 4kbps Manchester encod-
ed, 0.2% BER, TA= +25°C, unless otherwise noted.)
SUPPLY CURRENT vs. SUPPLY VOLTAGE
MAX7030 toc17
SUPPLY VOLTAGE (V)
SUPPLY CURRENT (mA)
3.33.02.72.4
10
12
14
16
8
2.1 3.6
fRF = 315MHz
PA ON
WITHOUT ENVELOPE SHAPING
TA = +85°C
TA = +125°C
TA = -40°C
TA = +25°C
SUPPLY CURRENT (mA)
2.5
3.0
3.5
4.0
5.0
4.5
5.5
6.0
2.0
SUPPLY CURRENT
vs. SUPPLY VOLTAGE
MAX7030 toc18
SUPPLY VOLTAGE (V)
3.33.02.72.42.1 3.6
fRF = 315MHz
PA OFF
TA = +85°C
TA = +125°C
TA = -40°C
TA = +25°C
SUPPLY CURRENT vs. SUPPLY VOLTAGE
MAX7030 toc19
SUPPLY VOLTAGE (V)
SUPPLY CURRENT (mA)
3.33.02.72.4
11
13
15
17
9
2.1 3.6
fRF = 434MHz
PA ON
WITHOUT ENVELOPE SHAPING
TA = +85°C
TA = +125°CTA = -40°C
TA = +25°C
SUPPLY CURRENT (mA)
3.0
3.5
4.0
5.0
4.5
5.5
6.0
SUPPLY CURRENT
vs. SUPPLY VOLTAGE
MAX7030 toc20
SUPPLY VOLTAGE (V)
3.33.02.72.42.1 3.6
fRF = 434MHz
PA OFF
TA = +85°C
TA = +125°C
TA = -40°C
TA = +25°C
SUPPLY CURRENT vs. OUTPUT POWER
AVERAGE OUTPUT POWER (dBm)
62-10 -6 -2
5
6
7
8
9
10
11
12
4
-14 10
MAX7030 toc21
SUPPLY CURRENT (mA)
fRF = 315MHz
PA ON
ENVELOPE SHAPING ENABLED
PA ON
50% DUTY CYCLE
SUPPLY CURRENT vs. OUTPUT POWER
AVERAGE OUTPUT POWER (dBm)
62-10 -6 -2
5
6
7
8
9
10
11
12
13
14
-14 10
MAX7030 toc22
SUPPLY CURRENT (mA)
fRF = 434MHz
PA ON
ENVELOPE SHAPING ENABLED
PA ON
50% DUTY CYCLE
SUPPLY CURRENT AND OUTPUT POWER
vs. EXTERNAL RESISTOR
MAX7030 toc23-1
EXTERNAL RESISTOR (Ω)
SUPPLY CURRENT (mA)
1k1001 10
4
6
8
10
12
14
16
18
2
0.1 10k
-12
-8
-4
0
4
8
12
16
-16
OUTPUT POWER (dBm)
fRF = 315MHz
PA ON
POWER
CURRENT
SUPPLY CURRENT AND OUTPUT POWER
vs. EXTERNAL RESISTOR
MAX7030 toc23-2
EXTERNAL RESISTOR (Ω)
SUPPLY CURRENT (mA)
1k1001 10
4
6
8
10
12
14
16
18
2
0.1 10k
-12
-8
-4
0
4
8
12
16
-16
OUTPUT POWER (dBm)
fRF = 433MHz
PA ON
POWER
CURRENT
TRANSMITTER
MAX7030
Low-Cost, 315MHz and 433.92MHz
ASK Transceiver with Fractional-N PLL
9
OUTPUT POWER vs. SUPPLY VOLTAGE
MAX7030 24-1
SUPPLY VOLTAGE (V)
OUTPUT POWER (dBm)
3.33.02.72.4
6
8
10
12
14
4
2.1 3.6
fRF = 315MHz
PA ON
ENVELOPE SHAPING DISABLED
TA = -40°C
TA = +25°C
TA = +125°C
TA = +85°C
OUTPUT POWER vs. SUPPLY VOLTAGE
MAX7030 24-2
SUPPLY VOLTAGE (V)
OUTPUT POWER (dBm)
3.33.02.72.4
6
8
10
12
14
4
2.1 3.6
fRF = 315MHz
PA ON
ENVELOPE SHAPING ENABLED
TA = +125°C
TA = +25°C
TA = -40°C
TA = +85°C
OUTPUT POWER vs. SUPPLY VOLTAGE
MAX7030 25-1
SUPPLY VOLTAGE (V)
OUTPUT POWER (dBm)
3.33.02.72.4
6
8
10
12
14
4
2.1 3.6
fRF = 434MHz
PA ON
ENVELOPE SHAPING DISABLED
TA = +85°C
TA = +125°C
TA = +25°C
TA = -40°C
OUTPUT POWER vs. SUPPLY VOLTAGE
MAX7030 25-2
SUPPLY VOLTAGE (V)
OUTPUT POWER (dBm)
3.33.02.72.4
6
8
10
12
14
2.1 3.6
fRF = 434MHz
PA ON
ENVELOPE SHAPING ENABLED
TA = +85°C
TA = +125°C
TA = +25°C
TA = -40°C
EFFICIENCY vs. SUPPLY VOLTAGE
MAX7030 toc26
SUPPLY VOLTAGE (V)
EFFICIENCY (%)
3.33.02.72.4
25
30
35
40
20
2.1 3.6
TA = +85°C
TA = +125°C
TA = +25°C
TA = -40°C
fRF = 315MHz
PA ON
EFFICIENCY vs. SUPPLY VOLTAGE
MAX7030 toc27
SUPPLY VOLTAGE (V)
EFFICIENCY (%)
3.33.02.72.4
25
30
35
40
20
2.1 3.6
TA = +85°C
TA = +125°C
TA = +25°C
TA = -40°C
fRF = 434MHz
PA ON
EFFICIENCY vs. SUPPLY VOLTAGE
MAX7030 toc28
SUPPLY VOLTAGE (V)
EFFICIENCY (%)
3.33.02.72.4
15
20
25
30
10
2.1 3.6
TA = +85°CTA = +125°C
TA = +25°C
TA = -40°C
fRF = 315MHz
50% DUTY CYCLE
EFFICIENCY vs. SUPPLY VOLTAGE
MAX7030 toc29
SUPPLY VOLTAGE (V)
EFFICIENCY (%)
3.33.02.72.4
20
25
30
15
2.1 3.6
TA = +85°C
TA = +125°C
TA = +25°C
TA = -40°C
fRF = 434MHz
50% DUTY CYCLE
PHASE NOISE vs. OFFSET FREQUENCY
MAX7030 toc30
OFFSET FREQUENCY (Hz)
PHASE NOISE (dBc/Hz)
1M100k10k1k
-130
-120
-110
-100
-90
-80
-70
-60
-50
-40
-140
100 10M
fRF = 315MHz
Typical Operating Characteristics (continued)
(
Typical Application Circuit
, VPAVDD = VAVDD = VDVDD = VHVIN = +3.0V, fRF = 433.92MHz, IF BW = 280kHz, 4kbps Manchester
encoded, 0.2% BER, TA= +25°C, unless otherwise noted.)
TRANSMITTER
MAX7030
Low-Cost, 315MHz and 433.92MHz
ASK Transceiver with Fractional-N PLL
10
PHASE NOISE vs. OFFSET FREQUENCY
MAX7030 toc31
OFFSET FREQUENCY (Hz)
PHASE NOISE (dBc/Hz)
-130
-120
-110
-100
-90
-80
-70
-60
-50
-40
-140
fRF = 434MHz
1M100k10k1k100 10M
REFERENCE SPUR MAGNITUDE
vs. SUPPLY VOLTAGE
MAX7030 toc32
SUPPLY VOLTAGE (V)
REFERENCE SPUR MAGNITUDE (dBc)
3.33.02.72.4
-65
-60
-55
-50
-45
-40
-70
2.1 3.6
434MHz
315MHz
-8
-6
-4
-2
0
2
4
6
8
10
-10
FREQUENCY STABILITY
vs. SUPPLY VOLTAGE
MAX7030 toc33
SUPPLY VOLTAGE (V)
FREQUENCY STABILITY (ppm)
3.33.02.72.42.1 3.6
fRF = 434MHz
fRF = 315MHz
Typical Operating Characteristics (continued)
(
Typical Application Circuit
, VPAVDD = VAVDD = VDVDD = VHVIN = +3.0V, fRF = 433.92MHz, IF BW = 280kHz, 4kbps Manchester encod-
ed, 0.2% BER, TA= +25°C, unless otherwise noted.)
TRANSMITTER
MAX7030
Low-Cost, 315MHz and 433.92MHz
ASK Transceiver with Fractional-N PLL
11
Pin Description
PIN NAME FUNCTION
1 PAVDD Power-Amplifier Supply Voltage. Bypass to GND with 0.01µF and 220pF capacitors placed as close
as possible to the pin.
2 ROUT
Envelope-Shaping Output. ROUT controls the power-amplifier envelope’s rise and fall times. Connect
ROUT to the PA pullup inductor or optional power-adjust resistor. Bypass the inductor to GND as
close as possible to the inductor with 680pF and 220pF capacitors, as shown in the Typical
Application Circuit.
3 TX/RX1 Transmit/Receive Switch Throw. Drive T/R high to short TX/RX1 to TX/RX2. Drive T/R low to disconnect
TX/RX1 from TX/RX2. Functionally identical to TX/RX2.
4 TX/RX2 Transmit/Receive Switch Pole. Typically connected to ground. See the Typical Application Circuit.
5 PAOUT Power-Amplifier Output. Requires a pullup inductor to the supply voltage (or ROUT if envelope
shaping is desired), which can be part of the output-matching network to an antenna.
6 AVDD Analog Power-Supply Voltage. AVDD is connected to an on-chip +3.0V regulator in 5V operation.
Bypass AVDD to GND with a 0.1µF and 220pF capacitor placed as close as possible to the pin.
7 LNAIN Low-Noise Amplifier Input. Must be AC-coupled.
8 LNASRC Low-Noise Amplifier Source for External Inductive Degeneration. Connect an inductor to GND to set
the LNA input impedance.
9 LNAOUT Low-Noise Amplifier Output. Must be connected to AVDD through a parallel LC tank filter. AC-couple
to MIXIN+.
10 MIXIN+ Noninverting Mixer Input. Must be AC-coupled to the LNA output.
11 MIXIN- Inverting Mixer Input. Bypass to AVDD with a capacitor as close as possible to the LNA LC tank filter.
12 MIXOUT 330Ω Mixer Output. Connect to the input of the 10.7MHz filter.
13 IFIN- Inverting 330Ω IF Limiter-Amplifier Input. Bypass to GND with a capacitor.
14 IFIN+ Noninverting 330Ω IF Limiter-Amplifier Input. Connect to the output of the 10.7MHz IF filter.
15 PDMIN Minimum-Level Peak Detector for Demodulator Output
16 PDMAX Maximum-Level Peak Detector for Demodulator Output
17 DS- Inverting Data Slicer Input
18 DS+ Noninverting Data Slicer Input
19 OP+ Noninverting Op-Amp Input for the Sallen-Key Data Filter
20 DF Data-Filter Feedback Node. Input for the feedback capacitor of the Sallen-Key data filter.
21, 25 N.C. No Connection. Do not connect to this pin.
22 T/RTransmit/Receive. Drive high to put the device in transmit mode. Drive low or leave unconnected to
put the device in receive mode. It is internally pulled down.
23 ENABLE Enable. Drive high for normal operation. Drive low or leave unconnected to put the device into shut-
down mode.
24 DATA Receiver Data Output/Transmitter Data Input
26 DVDD Digital Power-Supply Voltage. Bypass to GND with a 0.01µF and 220pF capacitor placed as close as
possible to the pin.
27 HVIN
High-Voltage Supply Input. For 3V operation, connect HVIN to AVDD, DVDD, and PAVDD. For 5V
operation, connect only HVIN to 5V. Bypass HVIN to GND with a 0.01µF and 220pF capacitor placed
as close as possible to the pin.
MAX7030
Low-Cost, 315MHz and 433.92MHz
ASK Transceiver with Fractional-N PLL
12
Detailed Description
The MAX7030 315MHz and 433.92MHz CMOS trans-
ceiver and a few external components provide a com-
plete transmit and receive chain from the antenna to
the digital data interface. This device is designed for
transmitting and receiving ASK data. All transmit fre-
quencies are generated by a fractional-N-based syn-
thesizer, allowing for very fine frequency steps in
increments of fXTAL/4096. The receive LO is generated
by a traditional integer-N-based synthesizer.
Depending on component selection, data rates as high
as 33kbps (Manchester encoded) or 66kbps (NRZ
encoded) can be achieved.
Receiver
Low-Noise Amplifier (LNA)
The LNA is a cascode amplifier with off-chip inductive
degeneration that achieves approximately 30dB of volt-
age gain that is dependent on both the antenna-match-
ing network at the LNA input and the LC tank network
between the LNA output and the mixer inputs.
The off-chip inductive degeneration is achieved by
connecting an inductor from LNASRC to GND. This
inductor sets the real part of the input impedance at
LNAIN, allowing for a more flexible match for low-input
impedances such as a PCB trace antenna. A nominal
value for this inductor with a 50Ωinput impedance is
12nH at 315MHz and 10nH at 434MHz, but the induc-
tance is affected by PCB trace length. LNASRC can be
shorted to ground to increase sensitivity by approxi-
mately 1dB, but the input match must then be reopti-
mized.
The LC tank filter connected to LNAOUT consists of L5
and C9 (see the
Typical Application Circuit
). Select L5
and C9 to resonate at the desired RF input frequency.
The resonant frequency is given by:
where LTOTAL = L5 + LPARASITICS and CTOTAL = C9 +
CPARASITICS.
LPARASITICS and CPARASITICS include inductance and
capacitance of the PCB traces, package pins, mixer-
input impedance, LNA-output impedance, etc. These
parasitics at high frequencies cannot be ignored, and
can have a dramatic effect on the tank filter center fre-
quency. Lab experimentation should be done to opti-
mize the center frequency of the tank. The total
parasitic capacitance is generally between 5pF and
7pF.
Automatic Gain Control (AGC)
When the AGC is enabled, it monitors the RSSI output.
When the RSSI output reaches 1.28V, which corre-
sponds to an RF input level of approximately -55dBm,
the AGC switches on the LNA gain-reduction attenua-
tor. The attenuator reduces the LNA gain by 36dB,
thereby reducing the RSSI output by about 540mV to
740mV. The LNA resumes high-gain mode when the
RSSI output level drops back below 680mV (approxi-
mately -59dBm at the RF input) for a programmable
interval called the AGC dwell time (see Table 1). The
AGC has a hysteresis of approximately 4dB. With the
AGC function, the RSSI dynamic range is increased,
allowing the MAX7030 to reliably produce an ASK out-
put for RF input levels up to 0dBm with a modulation
depth of 18dB. AGC is not required and can be dis-
abled (see Table 1).
f
LC
TOTAL TOTAL
=×
1
2π
Pin Description (continued)
PIN NAME FUNCTION
28 AGC2 AGC Enable/Dwell Time Control 2 (MSB). See Table 1. Bypass to GND with a 10pF capacitor.
29 AGC1 AGC Enable/Dwell Time Control 1. See Table 1. Bypass to GND with a 10pF capacitor.
30 AGC0 AGC Enable/Dwell Time Control 0 (LSB). See Table 1. Bypass to GND with a 10pF capacitor.
31 XTAL1 Crystal Input 1. Bypass to GND if XTAL2 is driven by an AC-coupled external reference.
32 XTAL2 Crystal Input 2. XTAL2 can be driven from an external AC-coupled reference.
— EP Exposed Pad. Solder evenly to the board’s ground plane for proper operation.
MAX7030
Low-Cost, 315MHz and 433.92MHz
ASK Transceiver with Fractional-N PLL
13
AGC Dwell-Time Settings
The AGC dwell timer holds the AGC in low-gain state
for a set amount of time after the power level drops
below the AGC switching threshold. After that set
amount of time, if the power level is still below the AGC
threshold, the LNA goes into high-gain state. This is
important for ASK since the modulated data may have
a high level above the threshold and low level below
the threshold, which without the dwell timer would
cause the AGC to switch on every bit.
The MAX7030 uses the three AGC control pins (AGC0,
AGC1, AGC2) to set seven user-controlled, dwell-timer
settings. The AGC dwell time is dependent on the crys-
tal frequency and the bit settings of the AGC control
pins. To calculate the dwell time, use the following
equation:
where K is an odd integer in decimal from 11 to 23, deter-
mined by the control pin settings shown in Table 1.
To calculate the value of K, use the following equation
and use the next integer higher than the calculated
result:
K ≥3.3 x log10 (Dwell Time x fXTAL)
For Manchester Code (50% duty cycle), set the dwell
time to at least twice the bit period. For nonreturn-to-
zero (NRZ) data, set the dwell to greater than the peri-
od of the longest string of zeros or ones. For example,
using Manchester Code at 315MHz (fXTAL =
12.679MHz) with a data rate of 2kbps (bit period =
250µs), the dwell time needs to be greater than 500µs:
K ≥3.3 x log10 (500µs x 12.679) ≈12.546
Choose the AGC pin settings for K to be the next odd-
integer value higher than 12.546, which is 13. This says
that AGC1 is set high and AGC0 and AGC2 are set low.
Mixer
A unique feature of the MAX7030 is the integrated
image rejection of the mixer. This eliminates the need
for a costly front-end SAW filter for many applications.
The advantage of not using a SAW filter is increased
sensitivity, simplified antenna matching, less board
space, and lower cost.
The mixer cell is a pair of double-balanced mixers that
perform an IQ downconversion of the RF input to the
10.7MHz intermediate frequency (IF) with low-side
injection (i.e., fLO = fRF - fIF). The image-rejection circuit
then combines these signals to achieve a typical 46dB
of image rejection over the full temperature range. Low-
side injection is required as high-side injection is not
possible due to the on-chip image rejection. The IF out-
put is driven by a source follower, biased to create a
driving impedance of 330Ωto interface with an off-chip
330Ωceramic IF filter. The voltage-conversion gain dri-
ving a 330Ωload is approximately 20dB. Note that the
MIXIN+ and MIXIN- inputs are functionally identical.
Integer-N Phase-Locked Loop (PLL)
The MAX7030 utilizes a fixed-integer-N PLL to generate
the receive LO. All PLL components, including the loop
filter, voltage-controlled oscillator, charge pump, asyn-
chronous 24x divider, and phase-frequency detector
are integrated internally. The loop bandwidth is approx-
imately 500kHz. The relationship between RF, IF, and
crystal reference frequencies is given by:
fXTAL = (fRF - fIF)/24
Dwell Time f
K
XTAL
=2
AGC2 AGC1 AGC0 DESCRIPTION
0 0 0 AGC disabled, high gain selected
001
K = 11
010
K = 13
011
K = 15
100
K = 17
101
K = 19
110
K = 21
111
K = 23
Table 1. AGC Dwell Time Settings for
MAX7030
MAX7030
Low-Cost, 315MHz and 433.92MHz
ASK Transceiver with Fractional-N PLL
14
Intermediate Frequency (IF)
The IF section presents a differential 330Ωload to pro-
vide matching for the off-chip ceramic filter. The internal
six AC-coupled limiting amplifiers produce an overall
gain of approximately 65dB, with a bandpass filter type
response centered near the 10.7MHz IF frequency with
a 3dB bandwidth of approximately 10MHz. For ASK
data, the RSSI circuit demodulates the IF to baseband
by producing a DC output proportional to the log of the
IF signal level with a slope of approximately 15mV/dB.
Data Filter
The data filter for the demodulated data is implemented
as a 2nd-order, lowpass, Sallen-Key filter. The pole
locations are set by the combination of two on-chip
resistors and two external capacitors. Adjusting the
value of the external capacitors changes the corner fre-
quency to optimize for different data rates. Set the cor-
ner frequency in kHz to approximately 3 times the
fastest expected Manchester data rate in kbps from the
transmitter (1.5 times the fastest expected NRZ data
rate). Keeping the corner frequency near the data rate
rejects any noise at higher frequencies, resulting in an
increase in receiver sensitivity.
The configuration shown in Figure 1 can create a
Butterworth or Bessel response. The Butterworth filter
offers a very-flat-amplitude response in the passband
and a rolloff rate of 40dB/decade for the two-pole filter.
The Bessel filter has a linear phase response, which
works well for filtering digital data. To calculate the
value of the capacitors, use the following equations,
along with the coefficients in Table 2:
where fCis the desired 3dB corner frequency.
For example, choose a Butterworth filter response with
a corner frequency of 5kHz:
Choosing standard capacitor values changes CF1 to
470pF and CF2 to 220pF. In the
Typical Application Circuit
,
CF1 and CF2 are named C16 and C17, respectively.
Data Slicer
The data slicer takes the analog output of the data filter
and converts it to a digital signal. This is achieved by
using a comparator and comparing the analog input to
a threshold voltage. The threshold voltage is set by the
voltage on the DS- pin, which is connected to the nega-
tive input of the data slicer comparator.
Numerous configurations can be used to generate the
data-slicer threshold. For example, the circuit in Figure
2 shows a simple method using only one resistor and
one capacitor. This configuration averages the analog
output of the filter and sets the threshold to approxi-
mately 50% of that amplitude. With this configuration,
the threshold automatically adjusts as the analog signal
varies, minimizing the possibility for errors in the digital
data. The values of R and C affect how fast the thresh-
old tracks the analog amplitude. Be sure to keep the
corner frequency of the RC circuit much lower (about
10 times) than the lowest expected data rate.
With this configuration, a long string of NRZ zeros or
ones can cause the threshold to drift. This configuration
works best if a coding scheme, such as Manchester
coding, which has an equal number of zeros and ones,
is used.
Figure 3 shows a configuration that uses the positive and
negative peak detectors to generate the threshold. This
configuration sets the threshold to the midpoint between
a high output and a low output of the data filter.
Ck kHz pF
Ck kHz pF
F
F
1
2
1 000
1 414 100 3 14 5 450
1 414
4 100 3 14 5 225
=≈
=≈
.
( . )( )( . )( )
.
( )( )( . )( )
Ω
Ω
Cb
ak f
Ca
kf
Fc
Fc
1
2
100
4 100
=Ω
=Ω
()()()
()()()
π
π
MAX7030
RSSI
100kΩ
CF2 CF1
100kΩ
DFOP+DS+
Figure 1. Sallen-Key Lowpass Data Filter
FILTER TYPE a b
Butterworth
(Q = 0.707) 1.414 1.000
Bessel
(Q = 0.577) 1.3617 0.618
Table 2. Coefficients to Calculate CF1 and
CF2
MAX7030
Low-Cost, 315MHz and 433.92MHz
ASK Transceiver with Fractional-N PLL
15
Peak Detectors
The maximum peak detector (PDMAX) and minimum
peak detector (PDMIN), with resistors and capacitors
shown in Figure 3, create DC output voltages equal to
the high- and low-peak values of the filtered demodulat-
ed signal. The resistors provide a path for the capaci-
tors to discharge, allowing the peak detectors to
dynamically follow peak changes of the data filter out-
put voltages.
The maximum and minimum peak detectors can be
used together to form a data slicer threshold voltage at
a value midway between the maximum and minimum
voltage levels of the data stream (see the
Data Slicer
section and Figure 3). Set the RC time constant of the
peak detector combining network to at least 5 times the
data period.
If there is an event that causes a significant change in
the magnitude of the baseband signal, such as an AGC
gain-switch or a power-up transient, the peak detectors
may “catch” a false level. If a false peak is detected, the
slicing level is incorrect. The MAX7030 peak detectors
correct these problems by temporarily tracking the
incoming baseband filter voltage when an AGC state
switch occurs, or forcing the peak detectors to track the
baseband filter output voltage until all internal circuits are
stable following an enable pin low-to-high transition and
also T/Rpin high-to-low transition. The peak detectors
exhibit a fast attack/slow decay response. This feature
allows for an extremely fast startup or AGC recovery.
Transmitter
Power Amplifier (PA)
The PA of the MAX7030 is a high-efficiency, open-
drain, switch-mode amplifier. The PA with proper
output-matching network can drive a wide range of
antenna impedances, which includes a small-loop PCB
trace and a 50Ωantenna. The output-matching network
for a 50Ωantenna is shown in the
Typical Application
Circuit
. The output-matching network suppresses the
carrier harmonics and transforms the antenna imped-
ance to an optimal impedance at PAOUT (pin 5). The
optimal impedance at PAOUT is between 100Ωand
150Ωto transmit +10dBm with a 2.7V supply.
When the output-matching network is properly tuned,
the PA transmits power with a high overall efficiency of
up to 32%. The efficiency of the PA itself is more than
46%. The output power is set by an external resistor at
PAOUT and is also dependent on the external antenna
and antenna-matching network at the PA output.
Envelope Shaping
The MAX7030 features an internal envelope-shaping
resistor, which connects between the open-drain output
of the PA and the power supply (see the
Typical
Application Circuit
). The envelope-shaping resistor
slows the turn-on/turn-off of the PA in ASK mode and
results in a smaller spectral width of the modulated PA
output signal.
Fractional-N Phase-Locked Loop (PLL)
The MAX7030 utilizes a fully integrated, fractional-N,
PLL for its transmit frequency synthesizer. All PLL com-
ponents, including the loop filter, are integrated inter-
nally. The loop bandwidth is approximately 200kHz.
Power-Supply Connections
The MAX7030 can be powered from a 2.1V to 3.6V sup-
ply or a 4.5V to 5.5V supply. If a 4.5V to 5.5V supply is
used, then the on-chip linear regulator reduces the 5V
supply to the 3V needed to operate the chip.
To operate the MAX7030 from a 3V supply, connect
PAVDD, AVDD, DVDD, and HVIN to the 3V supply.
When using a 5V supply, connect the supply to HVIN
MAX7030
C
PDMAX PDMIN
R
C
R
DATA
SLICER
DATA
PEAK
DET
PEAK
DET
Figure 3. Generating Data-Slicer Threshold Using the Peak
Detectors
MAX7030
C
DS- DS+
R
DATA
SLICER
DATA
Figure 2. Generating Data-Slicer Threshold Using a Lowpass
Filter
only and connect AVDD, PAVDD, and DVDD together.
In both cases, bypass DVDD, HVIN, and PAVDD to
GND with 0.01µF and 220pF capacitors and bypass
AVDD to GND with 0.1µF and 220pF capacitors.
Bypass T/R, ENABLE, DATA, and AGC0-2 with 10pF
capacitors to GND. Place all bypass capacitors as
close as possible to the respective pins.
Transmit/
Receive
Antenna Switch
The MAX7030 features an internal SPST RF switch that,
when combined with a few external components, allows
the transmit and receive pins to share a common
antenna (see the
Typical Application Circuit)
. In receive
mode, the switch is open and the power amplifier is
shut down, presenting a high impedance to minimize
the loading of the LNA. In transmit mode, the switch
closes to complete a resonant tank circuit at the PA
output and forms an RF short at the input to the LNA. In
this mode, the external passive components couple the
output of the PA to the antenna and protect the LNA
input from strong transmitted signals.
The switch state is controlled by the T/Rpin (pin 22).
Drive T/Rhigh to put the device in transmit mode; drive
T/Rlow to put the device in receive mode.
Control Interface Considerations
When operating the MAX7030 with a +4.5V to +5.5V
supply voltage, the AGC0, ACG1, AGC2, DATA,
ENABLE and T/Rpins may be driven by a microcon-
troller with either 3V or 5V interface logic levels. When
operating the MAX7030 with a +2.1V to +3.6V supply,
the microcontroller must produce logic levels which
conform to the VIH and VIL specifications in the
DC
Electrical Characteristics
for the MAX7030.
Crystal Oscillator (XTAL)
The XTAL oscillator in the MAX7030 is designed to pre-
sent a capacitance of approximately 3pF between the
XTAL1 and XTAL2 pins. In most cases, this corre-
sponds to a 4.5pF load capacitance applied to the
external crystal when typical PCB parasitics are added.
It is very important to use a crystal with a load
capacitance that is equal to the capacitance of the
MAX7030 crystal oscillator plus PCB parasitics. If a
crystal designed to oscillate with a different load
capacitance is used, the crystal is pulled away from its
stated operating frequency, introducing an error in the
reference frequency. Crystals designed to operate with
higher differential load capacitance always pull the ref-
erence frequency higher.
In actuality, the oscillator pulls every crystal. The crys-
tal’s natural frequency is really below its specified fre-
quency, but when loaded with the specified load
capacitance, the crystal is pulled and oscillates at its
specified frequency. This pulling is already accounted
for in the specification of the load capacitance.
Additional pulling can be calculated if the electrical
parameters of the crystal are known. The frequency
pulling is given by:
where:
fpis the amount the crystal frequency is pulled in ppm.
Cmis the motional capacitance of the crystal.
CCASE is the case capacitance.
CSPEC is the specified load capacitance.
CLOAD is the actual load capacitance.
When the crystal is loaded as specified, i.e.,
CLOAD = CSPEC, the frequency pulling equals zero.
fC
CC CC
x
Pm
CASE LOAD CASE SPEC
=+−+
⎛
⎝
⎜⎞
⎠
⎟
2
11
106
MAX7030
Low-Cost, 315MHz and 433.92MHz
ASK Transceiver with Fractional-N PLL
16
32
31
30
29
28
27
26
9
10
11
12
13
14
15
18192021222324
7654321
MAX7030
THIN QFN
TOP VIEW
ROUT
PAVDD
TX/RX1
TX/RX2
PAOUT
AVDD
LNAIN
8
LNASRC
XTAL2
XTAL1
AGC0
AGC1
AGC2
HVIN
DVDD
25
+
N.C.
DATA
ENABLE
T/R
N.C.
DF
OP+
DS+
17
DS-
PDMIN
IFIN+
16
PDMAX
IFIN-
MIXOUT
MIXIN-
MIXIN+
LNAOUT
Pin Configuration
MAX7030
COMPONENT VALUE FOR
433.92MHz RF
VALUE FOR
315MHz RF DESCRIPTION
C1 220pF 220pF 5%
C2 680pF 680pF 5%
C3 6.8pF 12pF 5%
C4 6.8pF 10pF 5%
C5 10pF 22pF 5%
C6 220pF 220pF 5%
C7 0.1μF 0.1μF 10%
C8 100pF 100pF 5%
C9 1.8pF 2.7pF ±0.1pF
C10 100pF 100pF 5%
C11 220pF 220pF 5%
C12 100pF 100pF 5%
C13 1500pF 1500pF 10%
C14 0.047μF 0.047μF 10%
C15 0.047μF 0.047μF 10%
C16 470pF 470pF 5%
C17 220pF 220pF 5%
C18 220pF 220pF 5%
C19 0.01μF 0.01μF 5%
C20 100pF 100pF 5%
C21 100pF 100pF 5%
C22 220pF 220pF 5%
C23 0.01μF 0.01μF 10%
C24 0.01μF 0.01μF 10%
L1 22nH 27nH 5% or better*
L2 22nH 30nH 5% or better*
L3 22nH 30nH 5% or better*
L4 10nH 12nH 5% or better*
L5 16nH 30nH 5% or better*
L6 68nH 100nH 5% or better*
R1 100k100k5%
R2 100k100k5%
R3 00—
X1 17.63416MHz 12.67917MHz Crystal, 4.5pF CLOAD,
Crystek or Hong Kong Crystal
Y1 10.7MHz ceramic filter 10.7MHz ceramic filter Murata
Table 3. Component Values for Typical Application Circuit
Low-Cost, 315MHz and 433.92MHz
ASK Transceiver with Fractional-N PLL
17
*
Wire Wound recommended.
Note: Component values vary depending on PCB layout.
MAX7030
Low-Cost, 315MHz and 433.92MHz
ASK Transceiver with Fractional-N PLL
18
1
2
3
4
5
6
7
8
C8
L3
C6
910 11
C10 C12
C9
12
L5
C11
13
IN OUTGND
14 15 16
Y1
C13
17
18
19
20
21
22
23
24
C17
R1
25262728293032 31
AGC1
AGC0
MAX7030
3.0V
C23
VDD
VDD
PAVDD
ROUT
TX/RX1
TX/RX2
PAOUT
AVDD
LNAIN
LNASRC
LNAOUT
MIXIN+
MIXIN-
IFIN+
IFIN-
PDMIN
PDMAX
MIXOUT
DS-
DS+
OP+
DF
N.C.
T/R
ENABLE
DATA
N.C.
DVDD
HVIN
AGC2
AGC1
AGC0
XTAL1
XTAL2
AGC2
C20
C21
X1
L4
C14
C15
DATA
ENABLE
C16
TRANSMIT/
RECEIVE
C22
C5
C4
C18 C19
C7
L1
L2
C1C2
R2
R3*
*OPTIONAL POWER-ADJUST RESISTOR
C24
EXPOSED
PAD
C3
L6
VDD
VDD
VDD
Typical Application Circuit
Chip Information
PROCESS: CMOS
Package Information
For the latest package outline information and land patterns
(footprints), go to www.maxim-ic.com/packages. Note that a
“+”, “#”, or “-” in the package code indicates RoHS status only.
Package drawings may show a different suffix character, but
the drawing pertains to the package regardless of RoHS status.
PACKAGE
TYPE
PACKAGE
CODE
OUTLINE
NO.
LAND
PATTERN NO.
32 Thin QFN-EP T3255+3 21-0140 90-0001
MAX7030
Low-Cost, 315MHz and 433.92MHz
ASK Transceiver with Fractional-N PLL
19
LNA
90°
0°
RSSI
IF LIMITING
AMPS
100kΩ
100kΩ
DATA FILTER
7
8
9 10 11 12 14 13
20
19
RX
DATA
18
15
16
17
30
29
28
24
23
22
DIGITAL LOGIC
31
32
CRYSTAL
OSCILLATOR
27 3.0V
REGULATOR
6
26
PA
MAX7030
5
12
RX VCO
RX
FREQUENCY
DIVIDER
PHASE
DETECTOR
CHARGE
PUMP
LOOP FILTER
TX
FREQUENCY
DIVIDER
Σ
I
Q
TX VCO
ΔΣ
MODULATOR
EXPOSED
PAD
LNAIN
LNASRC
TX/RX1 TX/RX2
XTAL1
XTAL2
HVIN
AVDD
ROUT PAVDD PAOUT T/R DVDD ENABLE
DATA
AGC2
AGC1
AGC0
DS-
PDMAX
PDMIN
DS+
OP+
DF
IFIN+ IFIN-MIXOUT
MIXIN-MIXIN+LNAOUT
34
Functional Diagram
MAX7030
Low-Cost, 315MHz and 433.92MHz
ASK Transceiver with Fractional-N PLL
Maxim cannot assume responsibility for use of any circuitry other than circuitry entirely embodied in a Maxim product. No circuit patent licenses are
implied. Maxim reserves the right to change the circuitry and specifications without notice at any time. The parametric values (min and max limits) shown in
the Electrical. Characteristics table are guaranteed. Other parametric values quoted in this data sheet are provided for guidance.
20
____________________Maxim Integrated Products, 160 Rio Robles, San Jose, CA 95134 USA 1-408-601-1000
© 2012 Maxim Integrated Products Maxim is a registered trademark of Maxim Integrated Products, Inc.
Revision History
REVISION
NUMBER
REVISION
DATE DESCRIPTION PAGES
CHANGED
0 5/05 Initial release —
1 9/08
Added + to each part to denote lead-free/RoHS-compliant package and explicitly
calling out the odd frequency as contact factory for availability 1
2 6/09 Made correction in Power Amplifier (PA) section 15
3 11/10
Updated AC Electrical Characteristics, Absolute Maximum Ratings, and Package
Information 2, 5, 18
4 6/12
Deleted the MAX7030MATJ+ from the Selector Guide and all references to the
MAX7030MATJ+ throughout the data sheet; updated fXTAL reference in the Phase-
Locked Loop section; updated Power Amplifier section; inserted Control Interface
Considerations; updated Table 3
1, 13, 15, 16,
17, 18