N74F74D,602 - NXP Semiconductors - Datasheet.Directory

April 1988

Revised September 2000

74F74 Dual D-Type Positive Edge-Triggered Flip-Flop

74F74

Dual D-Type Positive Edge-Triggered Flip-Flop

General Description

The F74 is a du al D-typ e flip-f lop with Di rect Cl ear and Set

inputs and complementary (Q, Q) outputs. Information at

the inp ut is transfe rred to t he outputs on the positive ed ge

of the clock pulse. Clock triggering occurs at a voltage level

of the clock pulse and is not directly related to the transition

time of the positive-going pulse. After the Clock Pulse input

threshold voltage has been passed, the Data input is

locked out and information present will not be transferred to

the outputs until the next rising edge of the Clock Pulse

input.

Asynchronous Inputs:

LOW input to SD sets Q to HIGH level

LOW input to CD sets Q to LOW level

Clear and Set are indepe nde nt of clock

Simultaneous LOW on CD and SD

makes both Q and Q HIGH

Ordering Code:

Devices also available in Tape and Reel. Spe ci fy by append ing the suffix let t er “X” to the o rdering code.

Logic Symbols

IEEE/IEC

Connection Diagram

Order Number Package Number Package Description

74F74SC M14A 14-Lead Small Outline Integrated Circuit (SOIC), JEDEC MS-120, 0.150 Narrow

74F74SJ M14D 14-Lead Small Outline Package (SOP), EIAJ TYPE II, 5.3mm Wide

74F74PC N14A 14-Lead Plastic Dual-In-Line Package (PDIP), JEDEC MS-001, 0.300 Wide

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74F74

Unit Loading/Fan Out

Truth Table

H (h) = HIGH Voltage Level

L (l) = LOW Voltage Level

X = Immaterial

Q0 = Previo us Q (Q) before LOW-to-HIGH Clock Transition

Lower case letters indicate the state of the referenced input or output one setup time prior to the LOW-to-HIGH clock transition.

Logic Diagram

Please note that this diagram is provided only for the understanding of logic operations and should not be used to estimate propagatio n delays.

Pin Names Description U.L. Input IIH/IIL

HIGH/LOW Output IOH/IOL

D1, D2Data Inp uts 1.0/1.0 20 µA/−0.6 mA

CP1, CP2Clock Pulse Inputs (Active Rising Edge) 1.0/1.0 20 µA/−0.6 mA

CD1, CD2 Direct Clear Inputs (Active LOW) 1.0/3.0 20 µA/−1.8 mA

SD1, SD2 Direct Set Inputs (Active LOW) 1.0/3.0 20 µA/−1.8 mA

Q1, Q1, Q2, Q2Outputs 50/33.3 −1 mA/20 mA

Inputs Outputs

SDCDCP D Q Q

LHXXHL

HLXXLH

LLXXHH



hH L



lLH

HHLXQ

0Q0

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74F74

Absolute Maximum Ratings(Note 1) Recommended Operating

Conditions

Note 1: Absolute maximum ratings are values beyond which the device

may be damaged or have its useful life impaired. Functional operation

under these conditions is not implied.

Note 2: Eith er v oltage lim it or c urrent limit is sufficie nt to protect inputs.

DC Electrical Characteristics

Storage Temperature −65°C to +150°C

Ambient Temper atu re und er Bias −55°C to +125°C

Junction Temperature under Bias −55°C to +150°C

VCC Pin Potential to Ground Pin −0.5V to +7.0V

Input Voltage (Note 2) −0.5V to +7.0V

Input Current (Note 2) −30 mA to +5.0 mA

Voltage Applied to Output

in HIGH State (with VCC = 0V)

Standa rd Outp ut −0.5V to VCC

3-STATE Output −0.5V to +5.5V

Current Applied to Output

in LOW State (Ma x) twice the rat ed IOL (mA)

ESD Last P assing Volt age (Min) 4000V

Free Air Ambient Temperatur e 0°C to +70°C

Supply Voltage +4.5V to +5.5V

Symbol Parameter Min Typ Max Units VCC Conditions

VIH Input HIGH Voltage 2.0 V Recognized as a HIGH Signal

VIL Input LOW Voltage 0.8 V Recognized as a LOW Signal

VCD Input Clamp Diode Voltage −1.2 V Min IIN = −18 mA

VOH Output HIGH 10% VCC 2.5 VMin

IOH = −1 mA

Voltage 5 % VCC 2.7 IOH = −1 mA

VOL Output LOW 10% VCC 0.5 V Min IOL = 20 mA

Voltage

IIH Input HIGH 5.0 µAMaxV

IN = 2.7 V

Current

IBVI Input HIGH Current 7.0 µAMaxV

IN = 7.0 V

Breakdown Test

ICEX Output HIGH 50 µAMaxV

OUT = VCC

Leakage Current

VID Input Leakage 4.75 V 0.0 IID = 1.9 µA

Test All Other Pins Grounded

IOD Output Leakage 3.75 µA0.0

VIOD = 150 mV

Circuit Current All Other Pins Grounded

IIL Input LOW Current −0.6 mA Max VIN = 0.5V (D, CP)

−1.8 VIN = 0.5V (CD, SD)

IOS Output Short-Circuit Current −60 −150 mA Max VOUT = 0V

ICC Power Supply Current 10.5 16.0 mA Max

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74F74

AC Electrical Characteristi cs

AC Operating Requirements

Symbol Parameter

TA = +25°CT

A = 0°C to +70°C

Units

VCC = +5.0V VCC = +5.0V

CL = 50 pF CL = 50 pF

Min Typ Max Min Max

fMAX Maximum Clock Frequency 100 125 100 MHz

tPLH Propagation Delay 3.8 5.3 6.8 3.8 7.8 ns

tPHL CPn to Qn or Qn4.4 6.2 8.0 4.4 9.2

tPLH Propagation Delay 3.2 4.6 6.1 3.2 7.1 ns

tPHL CDn or SDn to Qn or Qn3.5 7.0 9.0 3.5 10.5

Symbol Parameter

TA = +25°CT

A = 0°C to +70°C

UnitsVCC = +5.0V VCC = +5.0V

Min Max Min Max

tS(H) Setup Time, HIGH or LOW 2.0 2.0

tS(L) Dn to CPn3.0 3.0

tH(H) Hold Time, HIGH or LOW 1.0 1.0

tH(L) Dn to CPn1.0 1.0

tW(H) CPn Pulse Width 4.0 4.0 ns

tW(L) H IGH or LOW 5.0 5.0

tW(L) CDn or SDn Pulse Width 4.0 4.0 ns

LOW

tREC Recovery Time 2.0 2.0 ns

CDn or SDn to CP

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74F74

Physical Dimensions inches (millimeters) unless otherwise noted

14-Lead Small Outline Integrated Circuit (SOIC), JEDEC MS-120, 0.150 Narrow

Package Number M14A

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74F74

Physical Dimensions inches (millimeters) unless otherwise noted (Continued)

14-Lead Sma ll Outline Package (SOP), EIAJ TYPE II, 5.3mm Wide

Package Number M14D

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74F74 Dual D-Type Positive Edge-Triggered Flip-Flop

Physical Dimensions inches (millimeters) unless otherwise noted (Continued)

14-Lead Plastic Dual-In-Line Package (PDIP), JEDEC MS-001, 0.300 Wide

Package Number N14A

Fairchild does not assume an y responsibility for u se of any circuitry d escribed, no circu it patent licenses are im plied and

Fairchild reserves the right at any time without notice to change said circuitry and specifications.

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to perform when properly used in accordance with

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user.

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