DS8023
Smart Card Interface
________________________________________________________________
Maxim Integrated Products
1
Rev 0; 8/08
For pricing, delivery, and ordering information, please contact Maxim Direct at 1-888-629-4642,
or visit Maxim’s website at www.maxim-ic.com.
General Description
The DS8023 smart card interface IC is a low-cost, low-
power, analog front-end for a smart card reader designed
for all ISO 7816, EMV*, and GSM11-11 applications. The
DS8023 supports 5V, 3V, and 1.8V smart cards, and pro-
vides an option for ultra-low stop-mode power consump-
tion. The DS8023 is available in 28-pin TSSOP and SO
packages, and can often be used as a replacement for
the TDA8024 with little or no application changes.
The DS8023 is designed to interface between a system
microcontroller and the smart card interface, providing
all power supply, protection, and level shifting required
for IC card applications.
Applications
Set-Top Box Conditional Access
Access Control
Banking Applications
POS Terminals
Debit/Credit Payment Terminals
PIN Pads
Automated Teller Machines
Telecommunications
Pay/Premium Television
Features
♦Analog Interface and Level Shifting for IC Card
Communication
♦±8kV (min) ESD (IEC) Protection on Card Interface
Pins
♦Ultra-Low Stop-Mode Current, Less Than 10nA (typ)
♦Internal IC Card-Supply Voltage Generation
5.0V ±5%, 80mA (max)
3.0V ±8%, 65mA (max)
1.8V ±10%, 30mA (max)
♦Automatic Card Activation and Deactivation
Controlled by Dedicated Internal Sequencer
♦I/O Lines from Host Directly Level Shifted for
Smart Card Communication
♦Flexible Card Clock Generation, Supporting
External Crystal Frequency Divided by 1, 2, 4, or 8
♦High-Current/Short-Circuit and High-Temperature
Protection
Ordering Information
Note: Contact the factory for availability of other variants and
package options.
+
Denotes a lead(Pb)-free/RoHS-compliant package.
*
EMV is a trademark owned by EMVCo LLC. EMV Level 1 library and hardware reference design available. Contact factory for details.
Note: Some revisions of this device may incorporate deviations from published specifications known as errata. Multiple revisions of any device may be
simultaneously available through various sales channels. For information about device errata, go to: www.maxim-ic.com/errata.
PART TEMP RANGE PIN-PACKAGE
DS8023-RJX+ -40°C to +85°C 28 TSSOP
DS8023-RRX+ -40°C to +85°C 28 SO
Selector Guide appears at end of data sheet.
PGND
28
27
26
25
24
23
22
AUX2IN
AUX1IN
I/OIN
XTAL2
TOP VIEW
DS8023
XTAL1
OFF
GND
21 VDD
20 RSTIN
19 CMDVCC
18 1_8V
17 VCC
16 RST
15 CLK
5V/3V
CLKDIV2
CLKDIV1
CP1
VDDA
VUP
PRES
PRES
I/O
AUX2
AUX1
4
1
2
3
5
6
7
8
9
10
11
12
13
14CGND
CP2
SO/TSSOP
Pin Configuration
DS8023
Smart Card Interface
2 _______________________________________________________________________________________
ABSOLUTE MAXIMUM RATINGS
RECOMMENDED DC OPERATING CONDITIONS
(VDD = +3.3V, VDDA = +5.0V, TA= +25°C, unless otherwise noted.) (Note 1)
Stresses beyond those listed under “Absolute Maximum Ratings” may cause permanent damage to the device. These are stress ratings only, and functional
operation of the device at these or any other conditions beyond those indicated in the operational sections of the specifications is not implied. Exposure to
absolute maximum rating conditions for extended periods may affect device reliability.
Voltage Range on VDD Relative to GND ...............-0.5V to +6.5V
Voltage Range on VDDA Relative to PGND ...........-0.5V to +6.5V
Voltage Range on CP1, CP2, and VUP
Relative to PGND...............................................-0.5V to +7.5V
Voltage Range on All Other Pins
Relative to GND......................................-0.5V to (VDD + 0.5V)
Maximum Junction Temperature .....................................+125°C
Maximum Power Dissipation (TA= -40°C to +85°C) .......700mW
Storage Temperature Range .............................-55°C to +150°C
Soldering Temperature.........Refer to the IPC/JEDEC J-STD-020
Specification.
PARAMETER SYMBOL CONDITIONS MIN TYP MAX UNITS
POWER SUPPLY
Digital Supply Voltage VDD 2.7 6.0 V
VCC = 5V, |ICC| < 80mA 4.0 6.0
Card-Voltage-Generator Supply Voltage VDDA VCC = 5V, |ICC| < 30mA 3.0 6.0 V
VTH2 Threshold voltage (falling) 2.30 2.45 2.60 V
Reset Voltage Thresholds VHYS2 Hysteresis 50 100 150 mV
CURRENT CONSUMPTION
Active VDD Current 5V Cards
(Including 80mA Draw from 5V Card) IDD_50V ICC = 80mA, fXTAL = 20MHz,
fCLK = 10MHz, VDDA = 5.0V 215 mA
Active VDD Current 5V Cards
(Current Consumed by DS8023 Only) IDD_IC ICC = 80mA, fXTAL = 20MHz,
fCLK = 10MHz, VDDA = 5.0V (Note 2) 135 mA
Active VDD Current 3V Cards
(Including 65mA Draw from 3V Card) IDD_30V ICC = 65mA, fXTAL = 20MHz,
fCLK = 10MHz, VDDA = 5.0V 100 mA
Active VDD Current 3V Cards
(Current Consumed by DS8023 Only) IDD_IC ICC = 65mA, fXTAL = 20MHz,
fCLK = 10MHz, VDDA = 5.0V (Note 2) 35 mA
Active VDD Current 1.8V Cards
(Including 30mA Draw from 1.8V Card) IDD_18V ICC = 30mA, fXTAL = 20MHz,
fCLK = 10MHz, VDDA = 5.0V 70 mA
Active VDD Current 1.8V Cards
(Current Consumed by DS8023 Only) IDD_IC ICC = 30mA, fXTAL = 20MHz,
fCLK = 10MHz, VDDA = 5.0V (Note 2) 35 mA
Inactive-Mode Current IDD Card inactive 500 μA
Stop-Mode Current IDD_STOP DS8023 in ultra-low-power stop
mode (Note 3) 10 nA
CLOCK SOURCE
Crystal Frequency fXTAL External crystal 0 20 MHz
fXTAL1 0 20 MHz
VIL_XTAL1 -0.3 0.3 x
VDD
XTAL1 Operating Conditions
VIH_XTAL1 0.7 x
VDD
VDD +
0.3
V
External Capacitance for Crystal CXTAL1,
CXTAL2 15 pF
Internal Oscillator fINT 2.7 MHz
DS8023
Smart Card Interface
_______________________________________________________________________________________ 3
RECOMMENDED DC OPERATING CONDITIONS (continued)
(VDD = +3.3V, VDDA = +5.0V, TA= +25°C, unless otherwise noted.) (Note 1)
PARAMETER SYMBOL CONDITIONS MIN TYP MAX UNITS
SHUTDOWN TEMPERATURE
Shutdown Temperature TSD +150 °C
RST PIN
Output Low Voltage VOL_RST1 I
OL_RST = 1mA 0 0.3 V
Card-Inactive Mode Output Current IOL_RST1 V
O_LRST = 0V 0 -1 mA
Output Low Voltage VOL_RST2 I
OL_RST = 200μA 0 0.3 V
Output High
Voltage VOH_RST2 I
OH_RST = -200μA VCC -
0.5 V
CC V
Rise Time tR_RST C
L= 30pF 0.1 μs
Fall Time tF_RST C
L= 30pF 0.1 μs
Shutdown Current
Threshold IRST(SD) -20 mA
Current Limitation IRST(LIMIT) -20 +20 mA
Card-Active Mode
RSTIN to RST Delay tD(RSTIN-RST) 2 μs
CLK PIN
Output Low Voltage VOL_CLK1 IOLCLK = 1mA 0 0.3 V
Card-Inactive Mode Output Current IOL_CLK1 V
OLCLK = 0V 0 -1 mA
Output Low Voltage VOL_CLK2 I
OLCLK = 200μA 0 0.3 V
Output High
Voltage VOH_CLK2 IOHCLK = -200μA VCC -
0.5 V
CC V
Rise Time tR_CLK C
L= 30pF (Note 4) 8 ns
Fall Time tF_CLK C
L= 30pF (Note 4) 8 ns
Current Limitation ICLK(LIMIT) -70 +70 mA
Clock Frequency fCLK Operational 0 10 MHz
Duty Factor C
L= 30pF 45 55 %
Card-Active Mode
Slew Rate SR CL= 30pF 0.2 V/ns
VCC PIN
Output Low Voltage VCC1 I
CC = 1mA 0 0.3 V
Card-Inactive Mode Output Current ICC1 V
CC = 0V 0 -1 mA
ICC(5V) < 80mA 4.75 5.00 5.25
ICC(3V) < 65mA 2.78 3.00 3.22
ICC(1.8V) < 30mA 1.65 1.8 1.95
5V card: current pulses of 40nC
with I < 200mA, t < 400ns,
f < 20MHz
4.6 5.4
3V card: current pulses of 24nC
with I < 200mA, t < 400ns,
f < 20MHz
2.75 3.25
Card-Active Mode Output Low Voltage VCC2
1.8V card: current pulses of 12nC
with I < 200mA, t < 400ns,
f < 20MHz
1.62 1.98
V
DS8023
Smart Card Interface
4 _______________________________________________________________________________________
RECOMMENDED DC OPERATING CONDITIONS (continued)
(VDD = +3.3V, VDDA = +5.0V, TA= +25°C, unless otherwise noted.) (Note 1)
PARAMETER SYMBOL CONDITIONS MIN TYP MAX UNITS
VCC(5V) = 0 to 5V -80
VCC(3V) = 0 to 3V -65
Output Current ICC2
VCC(1.8V) = 0 to 1.8V -30
mA
Shutdown Current
Threshold ICC(SD) 120 mA
Card-Active Mode
Slew Rate VCCSR Up/down, C < 300nF (Note 5) 0.05 0.16 0.22 V/μs
DATA LINES (I/O AND I/OIN)
I/O I/OIN Falling Edge Delay tD(IO-IOIN) 200 ns
Pullup Pulse Active Time tPU 100 ns
Maximum Frequency fIOMAX 1 MHz
Input Capacitance CI 10 pF
I/O, AUX1, AUX2 PINS
Output Low Voltage VOL_IO1 I
OL_IO = 1mA 0 0.3 V
Output Current IOL_IO1 V
OL_IO = 0V 0 -1 mA
Card-Inactive Mode
Internal Pullup
Resistor RPU_IO To VCC 7 11 15 k
Output Low Voltage VOL_IO2 IOL_IO = 1mA 0 0.3 V
Output High
Voltage VOH_IO2 I
OH_IO = < -40μA (3V/5V) 0.75 x VCC V
CC V
Output Rise/Fall
Time tOT C
L= 30pF (Note 3) 0.1 μs
Input Low Voltage VIL_IO -0.3 +0.8
Input High Voltage VIH_IO 1.5 VCC
V
Input Low Current IIL_IO VIL_IO = 0V 700 μA
Input High Current IIH_IO V
IH_IO = VCC 20 μA
Input Rise/Fall Time tIT 1.2 μs
Current Limitation IIO(LIMIT) C
L= 30pF -15 +15 mA
Card-Active Mode
Current When
Pullup Active IPU C
L= 80pF, VOH = 0.9 x VDD -1 mA
I/OIN, AUX1IN, AUX2IN PINS
Output Low Voltage VOL I
OL = 1mA 0 0.3 V
No load 0.9 x
VDD
VDD +
0.1
Output High Voltage VOH
IOH < -40μA 0.75 x
VDD
VDD +
0.1
V
Output Rise/Fall Time tOT C
L= 30pF, 10% to 90% 0.1 μs
Input Low Voltage VIL -0.3
0.3 x
VDD V
Input High Voltage VIH 0.7 x
VDD
VDD +
0.3 V
DS8023
Smart Card Interface
_______________________________________________________________________________________ 5
RECOMMENDED DC OPERATING CONDITIONS (continued)
(VDD = +3.3V, VDDA = +5.0V, TA= +25°C, unless otherwise noted.) (Note 1)
PARAMETER SYMBOL CONDITIONS MIN TYP MAX UNITS
Input Low Current IIL_IO V
IL = 0V 600 μA
Input High Current IIH_IO V
IH = VDD 10 μA
Input Rise/Fall Time tIT V
IL to VIH 1.2 μs
Integrated Pullup Resistor RPU Pullup to VDD 7 11 15 k
Current When Pullup Active IPU C
L= 30pF, VOH = 0.9 x VDD -1 mA
CONTROL PINS (CLKDIV1, CLKDIV2, CMDVCC, RSTIN, 5V/3V)
Input Low Voltage VIL -0.3
0.3 x
VDD V
Input High Voltage VIH 0.7 x
VDD
VDD +
0.3 V
Input Low Current IIL_IO 0 < VIL < VDD 5 μA
Input High Current IIH_IO 0 < VIH < VDD 5 μA
INTERRUPT OUTPUT PIN (OFF)
Output Low Voltage VOL I
OL = 2mA 0 0.3 V
Output High Voltage VOH I
OH = -15μA 0.75 x
VDD V
Integrated Pullup Resistor RPU Pullup to VDD 15 24 33 k
PRES, PRES PINS
Input Low Voltage VIL_PRES
0.3 x
VDD V
Input High Voltage VIH_PRES 0.7 x
VDD V
Input Low Current IIL_PRES VIL_PRES = 0V 5 μA
Input High Current IIH_PRES VIH_PRES = VDD 5 μA
TIMING
Activation Time tACT 160 μs
Deactivation Time tDEACT 80 μs
Window Start t3 95
CLK to Card Start
Time Window End t5 160 μs
PRES/PRES Debounce Time tDEB OUNCE 8 ms
Note 1: Operation guaranteed at TA= -40°C and TA= +85°C, but not tested.
Note 2: IDD_IC measures the amount of current used by the DS8023 to provide the smart card current minus the load.
Note 3: Stop mode is enabled by setting CMDVCC, 5V/3V, and 1_8V to logic-high.
Note 4: Parameters are guaranteed to meet all ISO 7816, GSM11-11, and EMV 2000 requirements. For the 1.8V card, the maximum
rise time and fall time is 10ns.
Note 5: Parameter is guaranteed to meet all ISO 7816, GSM11-11, and EMV 2000 requirements. For the 1.8V card, the minimimum
slew rate is 0.05V/µs and the maximum slew rate is 0.5V/µs.
DS8023
Smart Card Interface
6 _______________________________________________________________________________________
Pin Description
PIN NAME FUNCTION
1, 2 CLKDIV1,
CLKDIV2
Clock Divider. Determines the divided-down input clock frequency (presented at XTAL1 or from a
crystal at XTAL1 and XTAL2) on the CLK output pin. Dividers of 1, 2, 4, and 8 are available.
3 5V/3V
5V/3V Selection Pin. Allows selection of 5V or 3V for communication with an IC card. Logic-high
selects 5V operation; logic-low selects 3V operation. See Table 3 for a complete description of
choosing card voltages.
4 PGND Analog Ground
5, 7 CP2, CP1 Step-Up Converter Contact. Charge-pump capacitor. Connect a 100nF capacitor (ESR < 100m)
between CP1 and CP2.
6 VDDA Charge-Pump Supply. Must be equal to or higher than VDD. Connect a supply of at least 3.0V.
8 VUP Charge-Pump Output. Connect a 100nF capacitor (ESR < 100m) between VUP and GND.
9PRES Card Presence Indicator. Active-low card presence inputs. When the presence indicator becomes
active, a debounce timeout begins. After 8ms (typ) the OFF signal becomes active.
10 PRES
Card Presence Indicator. Active-high card presence inputs. When the presence indicator becomes
active, a debounce timeout begins. After 8ms (typ) the OFF signal becomes active.
11 I/O Smart Card Data-Line Output. Card data communication line, contact C7.
12, 13 AUX2,
AUX1
Smart Card Auxiliary Line (C4, C8) Output. Data line connected to card reader contacts C4 (AUX1)
and C8 (AUX2).
14 CGND Smart Card Ground
15 CLK Smart Card Clock. Card clock, contact C3.
16 RST Smart Card Reset. Card reset output from contact C2.
17 VCC Smart Card Supply Voltage. Decouple to CGND (card ground) with 2 x 100nF or 100 + 220nF
capacitors (ESR < 100m).
18 1_8V
1.8V Operation Selection. Active-high selection for 1.8V smart card communication. An active-high
signal on this pin overrides any setting on the 5V/3V pin.
19 CMDVCC Activation Sequence Initiate. Active-low input from host.
20 RSTIN Card Reset Input. Reset input from the host.
21 VDD Supply Voltage
22 GND Digital Ground
23 OFF Status Output. Active-low interrupt output to the host. Use a 20k integrated pullup resistor to VDD.
24, 25 XTAL1,
XTAL2
Crystal/Clock Input. Connect an input from an external clock to XTAL1 or connect a crystal across
XTAL1 and XTAL2. For the low idle-mode current variant, an external clock must be driven on
XTAL1.
26 I/OIN I/O Input. Host-to-interface chip data I/O line.
27, 28 AUX1IN,
AUX2IN C4/C8 Input. Host-to-interface I/O line for auxiliary connections to C4 and C8.
DS8023
Smart Card Interface
_______________________________________________________________________________________ 7
Detailed Description
The DS8023 is an analog front-end for communicating
with 1.8V, 3V, and 5V smart cards. Using an integrated
charge pump, the DS8023 can operate from a single
input voltage. The device translates all communication
lines to the correct voltage level and provides power for
smart card operation. It can operate from a wide input
voltage range (3.0V to 6.0V) and provides an extremely
low-power stop mode, consuming only 10nA while in
stop mode. The DS8023 is very compatible with the
NXP TDA8024. Many applications can upgrade with
very minor hardware changes, and only need to add
support in software to activate the ultra-low-power stop
mode. (Note that the PORADJ pin is not present in the
DS8023. It is replaced by the 1_8V selection pin.)
Power Supply
The DS8023 can operate from a single supply or a dual
supply. The supply pins for the device are VDD, GND,
VDDA, and PGND. VDD should be in the 2.7V to 6.0V
range, and is the supply for signals that interface with
the host controller. It should, therefore, be the same
supply as used by the host controller. All smart card
contacts remain inactive during power on or power off.
The internal circuits are kept in the reset state until VDD
reaches VTH2 + VHYS2 and for the duration of the inter-
nal power-on reset pulse, tW. A deactivation sequence
is executed when VDD falls below VTH2.
An internal charge pump and regulator generate the
3V or 5V card supply voltage (VCC). The charge pump
and regulator are supplied by VDDA and PGND. VDDA
should be connected to a minimum 3.0V (maximum
6.0V) supply and should be at a potential that is equal
to or higher than VDD.
The charge pump operates in a 1x (voltage follower) or
2x (voltage doubler) mode depending on the input
VDDA and the selected card voltage (5V or 3V).
• For 5V cards, the DS8023 operates in a 1x mode
for VDDA > 5.8V and in a 2x mode for VDDA < 5.8V.
• For 3V cards, the DS8023 operates in a 1x mode
for VDDA > 4.1V and in a 2x mode for VDDA < 4.1V.
• For 1.8V cards, the DS8023 operates in a 1x mode
for VDDA > 2.9V and in a 2x mode for VDDA < 2.9V.
Voltage Supervisor
The voltage supervisor monitors the VDD supply. A
220µs reset pulse (tW) is used internally to keep the
device inactive during power on or power off of the VDD
supply. See Figure 2.
TEMPERATURE
MONITOR
CARD VOLTAGE
GENERATOR
AND
CHARGE PUMP
CLOCK
GENERATION
CONTROL
SEQUENCER
POWER-SUPPLY
SUPERVISOR
I/O TRANSCEIVER
VDD
GND
VDDA
PGND
CP1
CP2
VUP
VCC
XTAL1
XTAL2
CLKDIV1
CLKDIV2
1_8V
5V/3V
CMDVCC
RSTIN
CGND
RST
CLK
I/O
AUX1
AUX2
OFF PRES
PRES
I/OIN
AUX1IN
AUX2IN
DS8023
Figure 1. Functional Diagram
VDD
ALARM
(INTERNAL SIGNAL)
POWER ON
tWtW
POWER OFF
VTH2 + VHYS2
VTH2
SUPPLY DROPOUT
Figure 2. Voltage Supervisor Behavior
DS8023
Smart Card Interface
8 _______________________________________________________________________________________
The DS8023 card interface remains inactive no matter
the levels on the command lines until duration tWafter
VDD has reached a level higher than VTH2 + VHYS2.
When VDD falls below VTH2, the DS8023 executes a
card deactivation sequence if its card interface is active.
Clock Circuitry
The clock signal from the DS8023 to the smart card
(CLK) is generated from the clock input on XTAL1 or
from a crystal operating at up to 20MHz connected
between pins XTAL1 and XTAL2. The inputs CLKDIV1
and CLKDIV2 determine the frequency of the CLK sig-
nal, which can be fXTAL, fXTAL/2, fXTAL/4, or fXTAL/8.
Table 1 shows the relationship between CLKDIV1 and
CLKDIV2 and the frequency of CLK.
Do not change the state of pins CLKDIV1 and CLKDIV2
simultaneously; a delay of 10ns minimum between
changes is required. The minimum duration of any state
of CLK is 8 periods of XTAL1.
The hardware in the DS8023 guarantees that the fre-
quency change is synchronous. During a transition of
the clock divider, no pulse is shorter than 45% of the
smallest period, and the clock pulses before and after
the instant of change have the correct width.
To achieve a 45% to 55% duty factor on pin CLK when
no crystal is present, the input signal on XTAL1 should
have a 48% to 52% duty factor. Transition time on
XTAL1 should be less than 5% of the period.
With a crystal, the duty factor on pin CLK may be 45%
to 55% depending on the circuit layout and on the crys-
tal characteristics and frequency.
The DS8023 crystal oscillator runs when the device is
powered up. If the crystal oscillator is used or the clock
pulse on pin XTAL1 is permanent, the clock pulse is
applied to the card at time t4(see Figures 7 and 8). If
the signal applied to XTAL1 is controlled by the host
microcontroller, the clock pulse is applied to the card
when it is sent by the system microcontroller (after
completion of the activation sequence).
I/O Transceivers
The three data lines I/O, AUX1, and AUX2 are identical.
This section describes the characteristics of I/O and
I/OIN, but also applies to AUX1, AUX1IN, AUX2, and
AUX2IN.
I/O and I/OIN are pulled high with an 11kΩresistor (I/O
to VCC and I/OIN to VDD) in the inactive state. The first
side of the transceiver to receive a falling edge
becomes the master. When the master is decided, the
opposite side switches to slave mode, ignoring subse-
quent edges until the master releases. After a time delay
tD(EDGE), an n transistor on the slave side is turned on,
thus transmitting the logic 0 present on the master side.
When the master side asserts a logic 1, a p transistor
on the slave side is activated during the time delay,
tPU, and then both sides return to their inactive (pulled
up) states. This active pullup provides fast low-to-high
transitions. After the duration of tPU, the output voltage
depends only on the internal pullup resistor and the
load current. Current to and from the card I/O lines is
limited internally to 15mA. The maximum frequency on
these lines is 1MHz.
Inactive Mode
The DS8023 powers up with the card interface in the
inactive mode. Minimal circuitry is active while waiting
for the host to initiate a smart card session.
• All card contacts are inactive (approximately 200Ω
to GND).
• Pins I/OIN, AUX1IN, and AUX2IN are in the high-
impedance state (11kΩpullup resistor to VDD).
• Voltage generators are stopped.
• XTAL oscillator is running (if included in the device).
• Voltage supervisor is active.
• The internal oscillator is running at its low frequency.
Activation Sequence
After power-on and the reset delay, the host microcon-
troller can monitor card presence with signals OFF and
CMDVCC, as shown in Table 2.
Table 1. Clock Frequency Selection
CLKDIV1 CLKDIV2 fCLK
0 0 fXTAL/8
0 1 fXTAL/4
1 1 fXTAL/2
1 0 fXTAL
Table 2. Card Presence Indication
OFF CMDVCC STATUS
High High Card present.
Low High Card not present.
DS8023
Smart Card Interface
_______________________________________________________________________________________ 9
When a card is inserted into the reader (if PRES is
active), the host microcontroller can begin an activation
sequence (start a card session) by pulling CMDVCC
low. The following events form an activation sequence
(Figure 3):
1) Host: CMDVCC is pulled low.
2) DS8023: The internal oscillator changes to high
frequency (t0).
3) DS8023: The voltage generator is started
(between t0and t1).
4) DS8023: Raise VCC from 0 to 5V, 3V, or 1.8V with
a controlled slope (t2= t1+ 1.5 ×T). T is 64 times
the internal oscillator period (approximately 25µs).
5) DS8023: I/O, AUX1, and AUX2 are enabled
(t3= t1+ 4T).
6) DS8023: The CLK signal is applied to the C3 con-
tact (t4).
7) DS8023: RST is enabled (t5= t1+ 7T).
An alternate sequence allows the application to control
when the clock is applied to the card.
1) Host: Set RSTIN high.
2) Host: Set CMDVCC low.
3) Host: Set RSTIN low between t3and t5; CLK will now
start.
4) DS8023: RST stays low until t5, then RST becomes
the copy of RSTIN.
5) DS8023: RSTIN has no further effect on CLK after t5.
If the applied clock is not needed, set CMDVCC low
with RSTIN low. In this case, CLK starts at t3(minimum
200ns after the transition on I/O, see Figure 4); after t5,
RSTIN can be set high to obtain an answer to request
(ATR) from an inserted smart card. Do not perform acti-
vation with RSTIN held permanently high.
ATR
CMDVCC
RST
RSTIN
CLK
VCC
I/O
I/OIN
t0t1t2t3t4t5 = tACT
Figure 3. Activation Sequence Using RSTIN and CMDVCC
DS8023
Smart Card Interface
10 ______________________________________________________________________________________
ATR
CMDVCC
RST
RSTIN
CLK
VCC
I/O
I/OIN
t0t1t2t3t4t5 = tACT
200ns
Figure 4. Activation Sequence at t3
RST
CLK
VCC
CMDVCC
I/O
t10
tDE
t12 t13 t14 t15
Figure 5. Deactivation Sequence
DS8023
Smart Card Interface
______________________________________________________________________________________ 11
Deactivation Sequence
When the host microcontroller is done communicating
with the smart card, it sets the CMDVCC line high to
execute an automatic deactivation sequence and
returns the card interface to the inactive mode.
The following sequence of events occurs during a
deactivation sequence (Figure 5):
1) RST goes low (t10).
2) CLK is held low (t12 = t10 + 0.5 ×T), where T is 64
times the period of the internal oscillator (approxi-
mately 25µs).
3) I/O, AUX1, and AUX2 are pulled low (t13 = t10 + T).
4) VCC starts to fall (t14 = t10 + 1.5 ×T).
5) When VCC reaches its inactive state, the deactiva-
tion sequence is complete (at tDE).
6) All card contacts become low impedance to GND;
I/OIN, AUX1IN, and AUX2IN remain at VDD (pulled
up through an internal 11kΩresistor).
7) The internal oscillator returns to its lower frequency.
VCC Generator
The card voltage (VCC) generator can supply up to
80mA continuously at 5V, 65mA at 3V, or 30mA at 1.8V.
An internal overload detector triggers at approximately
120mA. Current samples to the detector are filtered.
This allows spurious current pulses (with a duration of a
few µs) up to 200mA to be drawn without causing
deactivation. The average current must stay below the
specified maximum current value.
See the
Applications Information
section for recommen-
dations to help maintain VCC voltage accuracy.
Fault Detection
The DS8023 integrates circuitry to monitor the following
fault conditions:
• Short circuit or high current on VCC
• Card removal while the interface is activated
•V
DD dropping below threshold
• Card voltage generator operating out of the speci-
fied values (VDDA too low or current consumption
too high)
• Overheating
There are two different cases for how the DS8023
reacts to fault detection (Figure 6):
•Outside a Card Session (CMDVCC High). Output
OFF is low if a card is not in the card reader and
high if a card is in the reader. The VDD supply is
monitored—a decrease in input voltage generates
an internal power-on reset pulse but does not
affect the OFF signal. Short-circuit and tempera-
ture detection are disabled because the card is
not powered up.
•Within a Card Session (CMDVCC Low). Output
OFF goes low when a fault condition is detected,
and an emergency deactivation is performed auto-
matically (Figure 7). When the system controller
resets CMDVCC to high, it may sense the OFF
level again after completing the deactivation
sequence. This distinguishes between a card
extraction and a hardware problem (OFF goes high
again if a card is present).
Depending on the connector’s card-present switch
(normally closed or normally open) and the mechanical
characteristics of the switch, bouncing can occur on
the PRES signals at card insertion or withdrawal. The
DS8023 has a debounce feature with an 8ms typical
duration (Figure 6). When a card is inserted, output
OFF goes high after the debounce time delay. When
the card is extracted, an automatic deactivation
sequence of the card is performed on the first true/false
transition on PRES and output OFF goes low.
Stop Mode (Low-Power Mode)
A low-power state, stop mode, can be entered by forc-
ing the CMDVCC, 5V/3V, and 1_8V input pins to a
logic-high state. Stop mode can only be entered when
the smart card interface is inactive. In stop mode all
internal analog circuits are disabled. The OFF pin fol-
lows the status of the PRES pin. To exit stop mode,
change the state of one or more of the three control
pins to a logic-low. An internal 220µs (typ) power-up
delay and the 8ms PRES debounce delay are in effect
and OFF is asserted to allow the internal circuitry to sta-
bilize. This prevents smart card access from occurring
after leaving the stop mode. Figure 8 shows the control
sequence for entering and exiting stop mode. Note that
an in-progress deactivation sequence always finishes
before the DS8023 enters low-power stop mode.
DEBOUNCE DEBOUNCE
VCC
PRES
OFF
DEACTIVATION CAUSED
BY CARDS WITHDRAWAL
DEACTIVATION CAUSED
BY SHORT CIRCUIT
CMDVCC
Figure 6. Behavior of PRES, OFF, CMDVCC, and VCC
RST
CLK
VCC
PRES
OFF
I/O
t10
tDE
t12 t13 t14 t15
Figure 7. Emergency Deactivation Sequence (Card Extraction)
DS8023
Smart Card Interface
12 ______________________________________________________________________________________
DS8023
CMDVCC
1_8V
5V/3V
STOP MODE
OFF
PRES
VCC
DEACTIVATE INTERFACE
ACTIVATE
STOP MODE
DEACTIVATE
STOP MODE
8ms
WARMUP DELAY
OFF FOLLOWS
PRES IN STOP MODE
OFF ASSERTED TO
WAIT FOR DELAY
8ms DEBOUNCE
Figure 8. Stop-Mode Sequence
Smart Card Interface
______________________________________________________________________________________ 13
DS8023
Smart Card Interface
14 ______________________________________________________________________________________
Smart Card Power Select
The DS8023 supports three smart card VCC voltages:
1.8V, 3V, and 5V. The power select is controlled by the
1_8V and 5V/3V signals as shown in Table 3. The 1_8V
signal has priority over 5V/3V. When 1_8V is asserted
high, 1.8V is applied to VCC when the smart card is
active. When 1_8V is deasserted, 5V/3V dictates VCC
power range. VCC is 5V if 5V/3V is asserted to a logic-
high state, and VCC is 3V if 5V/3V is pulled to a
logic-low state. Care must be exercised when switching
from one VCC power selection to the other. If both 1_8V
and 5V/3V are high with CMDVCC high at the same
time, the DS8023 enters stop mode. To avoid acciden-
tal entry into stop mode, the state of 1_8V and 5V/3V
must not be changed simultaneously. A minimum delay
of 100ns should be observed between changing the
states of 1_8V and 5V/3V. See Figure 9 for the recom-
mended sequence of changing the VCC range.
VCC SELECT STOP MODE1.8V 1.8V3V 3V5V
1_8V
5V/3V
CMDVCC
Figure 9. Smart Card Power Select
Table 3. VCC Select and Operation Mode
1_8V 5V/3V CMDVCC VCC SELECT (V) CARD INTERFACE STATUS
0 0 0 3 Activated
0 0 1 3 Deactivated
0 1 0 5 Activated
0 1 1 5 Deactivated
1 0 0 1.8 Activated
1 0 1 1.8 Deactivated
1 1 0 1.8 Reserved (Activated)
1 1 1 1.8 Not Applicable—Stop Mode
DS8023
DS8023
MAXQ1103
100nF 100nF
+3.3V
+3.3V
+3.3V
100kΩ
100kΩ
33pF
100nF* 220nF*
*PLACE A 100nF CAPACITOR CLOSE TO DS8023 AND PLACE A 220nF CAPACITOR CLOSE TO CARD CONTACT.
100nF
33pF
CLKDIV1
CLKDIV2
5V/3V
1_8V
1_8V
OFF
RSTIN
CMDVCC
AUX2IN
AUX1IN
I/OIN
PRESGPIO
...
...
...
...
GPIO
ISOIO0
GPIO
...
...
...
GPIO
ISOIO1
VCC
RST
CLK
I/O
AUX1
AUX2
CGND
XTAL1 XTAL2 VUP
GND VDD CP1 CP2
+10μF
PGND VDDA
100nF
100nF* 220nF*
VDD
DS8023
100nF 100nF
+3.3V
33pF
100nF
33pF
I/OIN
AUX1IN
AUX2IN
CMDVCC
RSTIN
OFF
5V/3V
CLKDIV2
CLKDIV1
PRES
CGND
AUX2
AUX1
I/O
CLK
RST
VCC
XTAL1 XTAL2 VUP
GND VDD CP1 CP2
+10μF
PGND VDDA
100nF
VDD
Figure 10. Typical Application Diagram
Smart Card Interface
______________________________________________________________________________________ 15
DS8023
Smart Card Interface
EMVCo approval of the interface module (IFM) contained in this Terminal shall mean only that the IFM has been tested in accordance and for sufficient
conformance with the EMV Specifications, Version 3.1.1, as of the date of testing. EMVCo approval is not in any way an endorsement or warranty regarding
the completeness of the approval process or the functionality, quality or performance of any particular product or service. EMVCo does not warrant any
products or services provided by third parties, including, but not limited to, the producer or provider of the IFM and EMVCo approval does not under any
circumstances include or imply any product warranties from EMVCo, including, without limitation, any implied warranties of merchantability, fitness for pur-
pose, or noninfringement, all of which are expressly disclaimed by EMVCo. All rights and remedies regarding products and services which have received
EMVCo approval shall be provided by the party providing such products or services, and not by EMVCo and EMVCo accepts no liability whatsoever in
connection therewith.
Maxim cannot assume responsibility for use of any circuitry other than circuitry entirely embodied in a Maxim product. No circuit patent licenses are
implied. Maxim reserves the right to change the circuitry and specifications without notice at any time.
16
____________________Maxim Integrated Products, 120 San Gabriel Drive, Sunnyvale, CA 94086 408-737-7600
© 2008 Maxim Integrated Products Maxim is a registered trademark of Maxim Integrated Products, Inc.
Applications Information
Performance can be affected by the layout of the appli-
cation. For example, an additional cross-capacitance of
1pF between card reader contacts C2 (RST) and C3
(CLK) or C2 (RST) and C7 (I/O) can cause contact C2
to be polluted with high-frequency noise from C3 (or
C7). In this case, include a 100pF capacitor between
contacts C2 and CGND.
Application recommendations include the following:
• Ensure there is ample ground area around the
DS8023 and the connector; place the DS8023
very near to the connector; decouple the VDD and
VDDA lines separately. These lines are best posi-
tioned under the connector.
• The DS8023 and the host microcontroller must use
the same VDD supply. Pins CLKDIV1, CLKDIV2,
RSTIN, PRES, AUX1IN, I/OIN, AUX2IN, 5V/3V,
CMDVCC, and OFF are referenced to VDD; if pin
XTAL1 is to be driven by an external clock, also
reference this pin to VDD.
• Trace C3 (CLK) should be placed as far as possi-
ble from the other traces.
• The trace connecting CGND to C5 (GND) should
be straight (the two capacitors on C1 (VCC) should
be connected to this ground trace).
• Avoid ground loops among CGND, PGND, and
GND.
• Decouple VDDA and VDD separately; if the two
supplies are the same in the application, they
should be connected in a star on the main trace.
• Connect a 100nF capacitor (ESR < 100mΩ)
between VCC and CGND and place near the
DS8023’s VCC pin.
• Connect a 100nF or 220nF capacitor (220nF pre-
ferred, ESR < 100mΩ) between VCC and CGND
and place near the smart card socket’s C1 contact.
With all these layout precautions, noise should be kept
to an acceptable level and jitter on C3 (CLK) should be
less than 100ps.
Technical Support
For technical support, go to https://support.maxim-
ic.com/micro.
Selector Guide
Note: Contact the factory for availability of other variants and
package options.
+
Denotes a lead(Pb)-free/RoHS-compliant package.
PART
CURRENT
VOLTAGES
SUPPORTED (V)
SUPPORTS
STOP
MODE?
PIN-
PACKAGE
DS8023-RJX+ 1.8, 3.0, 5.0 Yes 28 TSSOP
DS8023-RRX+ 1.8, 3.0, 5.0 Yes 28 SO
PACKAGE TYPE PACKAGE CODE DOCUMENT NO.
28 SO (300 mils) —21-0042
28 TSSOP —21-0066
Package Information
For the latest package outline information and land patterns, go
to www.maxim-ic.com/packages.
