ST10F280 16-bit MCU with MAC unit, 512 Kbyte Flash memory and 18 Kbyte RAM Datasheet - production data Features High performance cpu with dsp functions - 16-bit CPU with 4-stage pipeline. - 50ns Instruction cycle time at 40MHz CPU clock - Multiply/accumulate unit (MAC) 16 x 16-bit multiplication, 40-bit accumulator - Repeat unit - Enhanced boolean bit manipulation facilities - Additional instructions to support hll and operating systems - Single-cycle context switching support PBGA208 (23 x 23 x 1.96 - Pitch 1.27 mm) (Plastic Bold Grid Array) ORDER CODE: ST10F280-JT3 A/D converter - 2X16-channel 10-bit - 4.85s conversion time - One timer for adc channel injection 8-channel PWM unit Memory organization - 512KB on-chip Flash memory single voltage with erase/program controller - 100K erasing/programming cycles - 20 year data retention time - Up to 16MB linear address space for code and data (5MB with CAN) - 2KB on-chip internal ram (IRAM) - 16KB extension RAM (XRAM) Serial channels - Synchronous/async serial channel - High-speed synchronous channel Fail-safe protection - Programmable watchdog timer - Oscillator watchdog Two CAN 2.0b interfaces operating on one or two can busses (30 or 2x15 message objects) Fast and flexible bus - Programmable external bus characteristics for different address ranges - 8-bit or 16-bit external data bus - Multiplexed or demultiplexed external address/data buses - Five programmable chip-select signals - Hold-acknowledge bus arbitration support On-chip bootstrap loader Clock generation - On-chip PLL - Direct or prescaled clock input Up to 143 general purpose i/o lines - Individually programmable as input, output or special function - Programmable threshold (hysteresis) Interrupt - 8-channel peripheral event controller for single cycle, interrupt driven data transfer - 16-priority-level interrupt system with 56 sources, sample-rate down to 25ns Idle and power down modes Maximum cpu frequency 40MHz Package PBGA 208 balls (23 x 23 x 1.96 mm pitch 1.27 mm) Single voltage supply: 5 V 10% (embedded regulator for 3.3 V core supply) Temperature range: -40C to 125C Two multi-functional general purpose timer units with 5 timers Two 16-channel capture/compare units August 2012 This is information on a product in full production. Doc ID 8673 Rev. 3 1/239 www.st.com 1 Contents ST10F280 Contents 1 Description . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 12 2 Ball data . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 14 3 Functional description . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 26 4 Memory organization . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 27 4.1 5 Visibility of XBUS peripherals . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 28 Internal Flash memory . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 31 5.1 Overview . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 31 5.2 Operational overview . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 31 5.3 5.2.1 Read mode . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 31 5.2.2 Instructions and commands . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 32 5.2.3 Status register . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 33 5.2.4 Erase operation . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 33 5.2.5 Erase suspend . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 33 5.2.6 In-system programming . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 33 5.2.7 Read/write protection . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 33 5.2.8 Power supply, reset . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 34 Architectural description . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 34 5.3.1 Read mode . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 34 5.3.2 Command mode . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 34 5.3.3 Flash Status Register . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 35 5.3.4 Flash Protection Register . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 36 5.3.5 Instructions description . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 36 5.3.6 Reset processing and initial State . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 41 5.4 Flash memory configuration . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 41 5.5 Application examples . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 41 5.6 5.5.1 Handling of Flash addresses . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 41 5.5.2 Basic Flash access control . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 42 5.5.3 Programming examples . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 43 Bootstrap loader . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 46 5.6.1 2/239 Entering the bootstrap loader . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 47 Doc ID 8673 Rev. 3 ST10F280 6 Contents 5.6.2 Memory configuration after reset . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 48 5.6.3 Loading the startup code . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 49 5.6.4 Exiting bootstrap loader mode . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 50 5.6.5 Choosing the baud rate for the BSL . . . . . . . . . . . . . . . . . . . . . . . . . . . . 50 Central Processing Unit (CPU) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 52 6.1 Multiplier-accumulator Unit (MAC) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 54 6.1.1 7 8 Features . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 54 6.2 Instruction set summary . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 55 6.3 MAC coprocessor specific instructions . . . . . . . . . . . . . . . . . . . . . . . . . . . 57 External bus controller . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 62 7.1 Programmable chip select timing control . . . . . . . . . . . . . . . . . . . . . . . . . 63 7.2 READY programmable polarity . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 63 Interrupt system . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 66 8.1 External interrupts . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 67 8.2 Interrupt registers and vectors location list . . . . . . . . . . . . . . . . . . . . . . . . 68 8.3 Interrupt Control Registers . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 72 8.4 Exception and error traps list . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 73 9 Capture/Compare (CAPCOM) units . . . . . . . . . . . . . . . . . . . . . . . . . . . . 75 10 General purpose timer unit . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 78 11 10.1 GPT1 . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 78 10.2 GPT2 . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 79 PWM module . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 81 11.1 Standard PWM module . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 81 11.2 New PWM module: XPWM . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 81 11.2.1 Operating modes . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 83 11.2.2 XPWM module registers . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 87 11.2.3 XPWM Control Registers . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 89 11.2.4 Interrupt request generation . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 90 11.2.5 XPWM output signals . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 91 11.2.6 XPOLAR Register (polarity of the XPWM channel) . . . . . . . . . . . . . . . . 92 Doc ID 8673 Rev. 3 3/239 Contents 12 ST10F280 Parallel ports . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 93 12.1 12.2 Introduction . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 95 12.1.1 Open drain mode . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 95 12.1.2 Input threshold control . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 96 12.1.3 Output driver control . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 96 12.1.4 Alternate port functions . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 99 Port 0 . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 100 12.2.1 12.3 Port 1 . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 103 12.3.1 12.4 Alternate functions of Port 5 . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 121 Port 6 . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 124 12.8.1 12.9 Alternate functions of Port 4 . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 116 Port 5 . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 120 12.7.1 12.8 Alternate functions of Port 3 . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 112 Port 4 . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 115 12.6.1 12.7 Alternate functions of Port 2 . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 107 Port 3 . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 111 12.5.1 12.6 Alternate functions of Port 1 . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 104 Port 2 . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 106 12.4.1 12.5 Alternate functions of Port 0 . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 102 Alternate functions of Port 6 . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 125 Port 7 . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 127 12.9.1 Alternate functions of Port 7 . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 128 12.10 Port 8 . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 131 12.10.1 Alternate functions of Port 8 . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 132 12.11 XPort 9 . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 134 12.12 XPort 10 . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 138 12.12.1 Alternate functions of XPort 10 . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 138 12.12.2 New disturb protection on analog inputs . . . . . . . . . . . . . . . . . . . . . . . 139 13 4/239 A/D converter . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 140 13.1 A/D converter module . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 140 13.2 Multiplexage of two blocks of 16 analog Inputs . . . . . . . . . . . . . . . . . . . 140 13.3 XTIMER peripheral (trigger for ADC channel injection) . . . . . . . . . . . . . 141 13.3.1 Main features . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 142 13.3.2 Register description . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 143 Doc ID 8673 Rev. 3 ST10F280 Contents 13.3.3 14 Serial channels . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 148 14.1 14.2 Asynchronous / Synchronous Serial Interface (ASCO) . . . . . . . . . . . . . 148 14.1.1 ASCO in asynchronous mode . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 149 14.1.2 ASCO in synchronous mode . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 151 High speed synchronous serial channel (SSC) . . . . . . . . . . . . . . . . . . . 152 14.2.1 15 Block diagram . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 145 Baud rate generation . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 153 CAN modules . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 155 15.1 15.2 Memory mapping . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 155 15.1.1 CAN1 . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 155 15.1.2 CAN2 . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 155 CAN bus configurations . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 155 15.2.1 Single CAN bus . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 156 15.2.2 Multiple CAN bus . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 156 15.3 Register and message object organization . . . . . . . . . . . . . . . . . . . . . . 157 15.4 CAN interrupt handling . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 160 15.4.1 Bit timing configuration . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 162 15.4.2 Mask registers . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 163 15.5 The message object . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 165 15.6 Arbitration Registers . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 168 16 Watchdog timer . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 169 17 System reset . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 171 17.1 17.2 Asynchronous reset (long hardware reset) . . . . . . . . . . . . . . . . . . . . . . 171 17.1.1 Power-on reset . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 171 17.1.2 Hardware reset . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 171 17.1.3 Exit of asynchronous reset state . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 171 Synchronous reset (warm reset) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 172 17.2.1 Exit of synchronous reset state . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 172 17.3 Software reset . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 174 17.4 Watchdog timer reset . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 174 17.5 RSTOUT pin and bidirectional reset . . . . . . . . . . . . . . . . . . . . . . . . . . . . 175 17.6 Reset circuitry . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 175 Doc ID 8673 Rev. 3 5/239 Contents 18 19 20 ST10F280 Power reduction modes . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 180 18.1 Idle mode . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 180 18.2 Power down mode . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 180 18.2.1 Protected power down mode . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 181 18.2.2 Interruptable power down mode . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 181 Special function register overview . . . . . . . . . . . . . . . . . . . . . . . . . . . 185 19.1 Identification registers . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 194 19.2 System configuration registers . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 196 Electrical characteristics . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 205 20.1 Absolute maximum ratings . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 205 20.2 Parameter interpretation . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 205 20.3 DC characteristics . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 205 20.4 20.3.1 A/D converter characteristics . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 208 20.3.2 Conversion timing control . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 209 AC characteristics . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 210 20.4.1 Test waveforms . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 210 20.4.2 Definition of internal timing . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 210 20.4.3 Clock generation modes . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 211 20.4.4 Prescaler operation . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 212 20.4.5 Direct drive . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 212 20.4.6 Oscillator Watchdog (OWD) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 213 20.4.7 Phase locked loop . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 213 20.4.8 External clock drive XTAL1 . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 214 20.4.9 Memory cycle variables . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 215 20.4.10 Multiplexed bus . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 215 20.4.11 Demultiplexed bus . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 222 20.4.12 CLKOUT and READY . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 227 20.4.13 External bus arbitration . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 229 20.4.14 High-speed synchronous serial interface (SSC) timing . . . . . . . . . . . . 231 21 6/239 Package information . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 235 21.1 ECOPACK(R) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 235 21.2 PBGA 208 (23 x 23 x 1.96 mm) mechanical data . . . . . . . . . . . . . . . . . 235 Doc ID 8673 Rev. 3 ST10F280 Contents 22 Ordering information . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 237 23 Revision history . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 238 Doc ID 8673 Rev. 3 7/239 List of tables ST10F280 List of tables Table 1. Table 2. Table 3. Table 4. Table 5. Table 6. Table 7. Table 8. Table 9. Table 10. Table 11. Table 12. Table 13. Table 14. Table 15. Table 16. Table 17. Table 18. Table 19. Table 20. Table 21. Table 22. Table 23. Table 24. Table 25. Table 26. Table 27. Table 28. Table 29. Table 30. Table 31. Table 32. Table 33. Table 34. Table 35. Table 36. Table 37. Table 38. Table 39. Table 40. Table 41. Table 42. Table 43. Table 44. Table 45. Table 46. Table 47. Table 48. 8/239 Ball description . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 15 512 Kbyte Flash memory block organization . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 32 Instructions . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 39 Instruction set summary . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 55 MAC coprocessor specific instructions . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 58 Pointer post-modification combinations for IDXi and Rwn . . . . . . . . . . . . . . . . . . . . . . . . . 60 MAC registers referenced as `CoReg` . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 60 Interrupt sources . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 68 Exceptions or error conditions that can arise during run-time. . . . . . . . . . . . . . . . . . . . . . . 74 Compare modes . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 77 CAPCOM timer input frequencies, resolution and periods . . . . . . . . . . . . . . . . . . . . . . . . . 77 GPT1 timer input frequencies, resolution and periods . . . . . . . . . . . . . . . . . . . . . . . . . . . . 79 GPT2 timer input frequencies, resolution and period . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 80 PWM unit frequencies and resolution at 40MHz CPU clock . . . . . . . . . . . . . . . . . . . . . . . . 81 XPWM module channel specific register addresses. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 88 XPWM frequency . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 88 POCON registers . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 98 Port 2 alternate function . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 108 Port 3 alternate functions . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 112 Port 4 alternate functions . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 117 Port 5 alternate functions . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 121 Port 6 alternate functions . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 125 Port 7 alternate functions . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 128 Port 8 alternate functions . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 132 XPort 10 alternate functions . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 138 The different counting Modes . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 142 Timer registers mapping . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 145 Commonly used baud rates by reload value and deviation errors . . . . . . . . . . . . . . . . . . 150 Commonly used baud rates by reload value and deviation errors . . . . . . . . . . . . . . . . . . 152 Synchronous baud rate and reload values . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 154 INTID values and corresponding interrupt sources . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 161 Functions of complementary bit of message control register . . . . . . . . . . . . . . . . . . . . . . 166 WDTCON bits value on different resets . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 170 WDTREL reload value . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 170 Reset event definition . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 171 PORT0 latched configuration for the different resets . . . . . . . . . . . . . . . . . . . . . . . . . . . . 178 PORT0 bit latched into the different registers after reset . . . . . . . . . . . . . . . . . . . . . . . . . 179 Special function registers listed by name . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 185 X registers listed by name . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 192 Stack size selection . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 197 Absolute maximum ratings . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 205 DC characteristics. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 205 A/D converter characteristics . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 208 ADC sampling and conversion timing . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 209 CPU frequency generation . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 211 External clock drive XTAL1. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 214 Memory cycle variables . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 215 Multiplexed bus characteristics . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 215 Doc ID 8673 Rev. 3 ST10F280 Table 49. Table 50. Table 51. Table 52. Table 53. Table 54. Table 55. Table 56. List of tables Demultiplexed bus characteristics . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 222 CLKOUT and READY characteristics . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 227 External bus arbitration . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 229 SSC master timing . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 231 SSC slave timing . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 233 PBGA 208 (23 x 23 x 1.96 mm) mechanical data. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 236 Device summary . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 237 Document revision history . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 238 Doc ID 8673 Rev. 3 9/239 List of figures ST10F280 List of figures Figure 1. Figure 2. Figure 3. Figure 4. Figure 5. Figure 6. Figure 7. Figure 8. Figure 9. Figure 10. Figure 11. Figure 12. Figure 13. Figure 14. Figure 15. Figure 16. Figure 17. Figure 18. Figure 19. Figure 20. Figure 21. Figure 22. Figure 23. Figure 24. Figure 25. Figure 26. Figure 27. Figure 28. Figure 29. Figure 30. Figure 31. Figure 32. Figure 33. Figure 34. Figure 35. Figure 36. Figure 37. Figure 38. Figure 39. Figure 40. Figure 41. Figure 42. Figure 43. Figure 44. Figure 45. Figure 46. Figure 47. Figure 48. 10/239 Logic symbol . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 13 Ball Configuration (bottom view) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 14 Block diagram . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 26 ST10F280 on-chip memory mapping . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 29 Bootstrap loader sequence . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 47 Hardware provisions to activate the BSL . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 49 Memory configuration after reset . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 49 Baud rate deviation between host and ST10F280 . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 51 CPU block diagram (MAC unit not included) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 52 MAC unit architecture . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 55 Chip select delay . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 63 CAPCOM unit block diagram . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 75 Block diagram of CAPCOM timers T0 and T7 . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 76 Block diagram of CAPCOM timers T1 and T . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 76 Block diagram of GPT1. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 79 Block diagram of GPT2. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 80 Block diagram of PWM module . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 81 SFRs and port pins associated with the XPWM module. . . . . . . . . . . . . . . . . . . . . . . . . . . 82 XPWM channel block diagram . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 82 Operation and output waveform in mode 0. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 84 Operation and output waveform in mode 1. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 85 Operation and output waveform in burst mode. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 86 Operation and output waveform in single shot mode . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 87 XPWM output signal generation . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 91 SFRs associated with the parallel ports . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 94 XBUS registers associated with the parallel ports . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 95 Output drivers in push/pull mode and in open drain mode . . . . . . . . . . . . . . . . . . . . . . . . . 95 Hysteresis for special input thresholds . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 96 Port 0 I/O and alternate functions . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 102 Block diagram of a Port 0 pin . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 103 Port 1 I/O and alternate functions . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 105 Block diagram of a Port 1 pin . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 106 Port 2 I/O and alternate functions . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 109 Block diagram of a Port 2 pin . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 110 Port 3 I/O and alternate functions . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 113 Block diagram of Port 3 pin with alternate input or alternate output function . . . . . . . . . . 114 Block diagram of pins P3.15 (CLKOUT) and P3.12 (BHE/WRH) . . . . . . . . . . . . . . . . . . . 115 Port 4 I/O and alternate functions . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 117 Block diagram of a Port 4 pin . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 118 Block diagram of P4.4 and P4.5 pins . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 119 Block diagram of P4.6 and P4.7 pins . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 120 Port 5 I/O and alternate functions . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 122 Block diagram of a Port 5 pin . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 122 Port 6 I/O and alternate functions . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 125 Block diagram of Port 6 pins with an alternate output function . . . . . . . . . . . . . . . . . . . . . 126 Port 7 I/O and alternate functions . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 129 Block diagram of Port 7 pins P7.3...P7.0 . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 129 Block diagram of Port 7 pins P7.7...P7.4 . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 130 Doc ID 8673 Rev. 3 ST10F280 List of figures Figure 49. Figure 50. Figure 51. Figure 52. Figure 53. Figure 54. Figure 55. Figure 56. Figure 57. Figure 58. Figure 59. Figure 60. Figure 61. Figure 62. Figure 63. Figure 64. Figure 65. Figure 66. Figure 67. Figure 68. Figure 69. Figure 70. Figure 71. Figure 72. Figure 73. Figure 74. Figure 75. Figure 76. Figure 77. Figure 78. Figure 79. Figure 80. Figure 81. Figure 82. Port 8 I/O and alternate functions . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 132 Block diagram of Port 8 pins P8.7...P8.0 . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 133 PORT10 I/O and alternate functions. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 139 Block diagram . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 141 XTIMER block diagram . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 145 XADCINJ timer output . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 146 External connection for ADC channel injection. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 147 Asynchronous mode of serial channel ASC0 . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 149 Synchronous mode of serial channel ASC0 . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 151 Synchronous serial channel SSC block diagram . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 153 Single CAN bus multiple interfaces - multiple transceivers. . . . . . . . . . . . . . . . . . . . . . . 156 Single CAN bus dual interfaces - single transceiver . . . . . . . . . . . . . . . . . . . . . . . . . . . . 156 Connection to two different CAN buses (e.g. for gateway application). . . . . . . . . . . . . . . 157 CAN module address map . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 158 Bit timing definition . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 162 Message object address map . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 166 Asynchronous reset timing . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 172 Synchronous warm reset (short low pulse on RSTIN) . . . . . . . . . . . . . . . . . . . . . . . . . . . 173 Synchronous warm reset (long low pulse on RSTIN) . . . . . . . . . . . . . . . . . . . . . . . . . . . 174 Internal (simplified) reset circuitry . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 177 Minimum external reset circuitry . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 177 External reset hardware circuitry . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 178 External RC circuit on RPD pin for exiting power down mode with external interrupt . . . 183 Simplified power down exit circuitry . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 184 Power down exit sequence when using an external interrupt (PLL x 2) . . . . . . . . . . . . . . 184 Supply / idle current as a function of operating frequency . . . . . . . . . . . . . . . . . . . . . . . . 207 Input / output waveforms . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 210 Float waveforms . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 210 Generation mechanisms for the CPU clock . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 211 Approximated maximum PLL Jitter . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 214 External clock drive XTAL1. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 215 External memory cycle: multiplexed bus, with / without read / write delay, normal ALE. . 218 External memory cycle: multiplexed bus, with / without read / write delay, extended ALE219 External memory cycle: multiplexed bus, with / without read / write delay, normal ALE, read / write chip select . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 220 External memory cycle: multiplexed bus, with / without read / write delay, extended ALE, read / write chip select . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 221 External memory cycle: demultiplexed bus, with / without read / write delay, normal ALE224 External memory cycle: demultiplexed bus, with / without read / write delay, extended ALE . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 225 External memory cycle: demultiplexed bus, with / without read / write delay, normal ALE, read / write chip select . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 226 External memory cycle: demultiplexed bus, no read / write delay, extended ALE, read /write chip select. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 227 CLKOUT and READY . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 229 External bus arbitration, releasing the bus . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 230 External bus arbitration, (regaining the bus) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 231 SSC master timing . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 232 SSC slave timing . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 234 Package outline PBGA 208 (23 x 23 x 1.96 mm) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 235 Figure 83. Figure 84. Figure 85. Figure 86. Figure 87. Figure 88. Figure 89. Figure 90. Figure 91. Figure 92. Figure 93. Doc ID 8673 Rev. 3 11/239 Description 1 ST10F280 Description The ST10F280 is a new derivative of the STMicroelectronics(R) ST10 family of 16-bit singlechip CMOS microcontrollers. It combines high CPU performance (up to 20 million instructions per second) with high peripheral functionality and enhanced I/O-capabilities. It also provides on-chip high-speed single voltage FLASH memory, on-chip high-speed RAM, and clock generation via PLL. ST10F280 is processed in 0.35m CMOS technology. The MCU core and the logic is supplied with a 5V to 3.3V on chip voltage regulator. The part is supplied with a single 5V supply and I/Os work at 5V. The device is upward compatible with the ST10F269 device, with the following set of differences: 12/239 Two supply pins (DC1,DC2) on the PBGA-208 package are used for decoupling the internally generated 3.3V core logic supply. Do not connect these two pins to 5.0V external supply. Instead, these pins should be connected to a decoupling capacitor (ceramic type, value 330nF). The A/D Converter characteristics stay identical but 16 new input channel are added. A bit in a new register (XADCMUX) control the multiplexage between the first block of 16 channel (on Port5) and the second block (on XPort10). The conversion result registers stay identical and the software management can determine the block in use. A new dedicated timer controls now the ADC channel injection mode on the input CC31 (P7.7). The output of this timer is visible on a dedicated pin (XADCINJ) to emulate this new functionality. A second XPWM peripheral (4 new channels) is added. Four dedicated pins are reserved for the outputs (XPWM[0:3]) A new general purpose I/O port named XPORT9 (16 bits) is added. Due to the bit addressing management, it will be different from other standard general purpose I/O ports. Doc ID 8673 Rev. 3 ST10F280 Description Figure 1. Logic symbol 6$$ 633 84!, 84!, 0ORT BIT 234). 234/54 0ORT BIT 6!2%& 0ORT BIT 6!'.$ 0ORT BIT .-) %! 2%!$9 !,% 0ORT BIT 34& 2$ 7272, 0ORT BIT 0ORT BIT 0ORT BIT 0ORT BIT 80ORT BIT 80ORT BIT 807 BIT 8!$#).* $# $# $ECOUPLING CAPACITOR FOR INTERNAL REGULATOR ("1($'5 Doc ID 8673 Rev. 3 13/239 Ball data 2 ST10F280 Ball data The ST10F280 package is a PBGA of 23 x 23 x 1.96 mm. The pitch of the balls is 1.27 mm. The signal assignment of the 208 balls is described in Figure 2 for the configuration and in Table 1 for the ball signal assignment. This package has 25 additional thermal balls. Figure 2. Ball Configuration (bottom view) 1 U1 U XP10.15 T1 T XP10.14 P N2 XP10.3 L1 L F G2 F2 VSS E VDD D1 D C P6.7 P6.3 P6.2 VSS P8.1 P2.6 P9 P2.1 P2.9 P10 P2.5 P2.10 P2.11 R11 P2.12 P11 P2.14 P2.13 T12 P2.15 R12 P3.0 P12 P3.2 13 U13 VSS T13 P3.1 R13 P3.3 P13 P3.5 L8 L9 VSS K7 P7.6 VSS K8 VSS J7 P7.0 H7 G7 K10 J10 VSS H10 VSS G9 VSS VSS VSS H9 VSS G8 VSS VSS VSS G10 VSS VSS VSS P3.7 P4.2 K14 K11 VSS P4.6 J14 J11 VSS RD H14 H11 VSS P0.2 G14 G11 VSS P0.5 P6.6 P0.10 E14 P6.0 P0.15 D5 xpwm.0 D6 VSS C5 NMI B4 VSS P3.6 P14 F14 C4 A3 P3.4 R14 L14 L11 VSS VSS J9 VSS H8 VSS L10 VSS K9 VSS J8 VSS P8.5 D4 B3 VSS T14 P3.13 L7 P6.5 P6.1 14 U14 P3.10 E4 xpwm.3 xpwm.1 xpwm.2 P2.2 P2.8 R10 DC2 T11 12 U12 F4 C3 A2 1 14/239 P6.4 P2.4 R9 P8 P5.14 VSS P8.3 D3 B2 A1 A P8.0 P2.3 VSS T10 11 U11 M14 G4 E3 C2 B1 B P8.2 D2 C1 P8.6 F3 E2 P5.10 H4 G3 P8.4 DC1 P5.15 P2.7 T9 R8 P7 J4 P7.1 H3 P8.7 P5.11 K4 P7.5 J3 P7.2 H2 E1 XADCINJ K3 P7.4 P5.6 P2.0 R7 P6 VDD T8 10 U10 XP10.4 L4 VSS F1 XP10.5 L3 P7.7 P5.12 R6 P5.7 VSS T7 9 U9 N14 XP10.0 J2 G1 G XP10.8 P5.13 8 U8 N4 XP10.1 K2 H1 XP10.9 P5.8 7 U7 T6 P5 XP10.2 P7.3 H P5.3 P4 M4 VDD J1 P5.1 P5.9 R5 M3 L2 J P5.4 6 U6 T5 R4 N3 XP10.6 P5.5 M2 VSS K1 K P5.2 5 U5 T4 P3 XP10.11 XP10.10 XP10.7 VAGND R3 P2 M1 M P5.0 4 U4 T3 XP10.13 XP10.12 N1 N VAREF R2 P1 3 U3 T2 R1 R 2 U2 A4 VSS C6 P1.14 B5 RSTOUT D7 VSS P1.13 C7 P1.15 B6 A5 D8 VSS P1.9 C8 P1.12 B7 A6 D9 P1.11 P1.6 C9 P1.8 B8 A7 D10 P1.7 B9 VSS A8 RSTIN VSS XTAL1 XTAL2 P1.10 VSS 2 3 4 5 6 7 8 P1.3 B10 VSS A9 VDD P1.2 C10 P1.4 A10 D11 XP9.14 C11 P1.0 B11 P1.1 A11 VDD P1.5 VSS 9 10 11 Doc ID 8673 Rev. 3 D12 XP9.11 C12 XP9.13 B12 XP9.15 A12 VDD 12 D13 XP9.5 C13 XP9.10 B13 XP9.12 A13 D14 XP9.2 C14 XP9.6 B14 XP9.9 A14 VSS VDD 13 14 15 U15 VDD T15 VSS R15 P3.8 P15 P3.11 N15 VSS M15 P4.1 L15 P4.4 K15 P4.7 J15 WR H15 P0.1 G15 P0.4 F15 P0.8 E15 P0.12 D15 XP9.0 C15 XP9.3 B15 XP9.7 A15 XP9.8 15 16 U16 VSS T16 VSS R16 P3.9 P16 P3.12 N16 P4.0 M16 P4.3 L16 P4.5 K16 VSS J16 READY H16 P0.0 G16 P0.3 F16 P0.6 E16 P0.9 D16 P0.13 C16 XP9.1 B16 XP9.4 A16 17 U17 VSS U T17 P3.15 T R17 VSS R P17 VDD P N17 VSS N M17 RPD M L17 VDD L K17 VSS K J17 ALE J H17 EA H G17 VDD G F17 VSS F E17 P0.7 E D17 P0.11 D C17 P0.14 C B17 VSS B A17 VSS VSS 16 17 A ST10F280 Ball data Table 1. Symbol P6.0 - P6.7 P8.0 - P8.7 Ball description Ball Type number Function I/O Port 6 is an 8-bit bidirectional I/O port. It is bit-wise programmable for input or output via direction bits. For a pin configured as input, the output driver is put into high-impedance state. Port 6 outputs can be configured as push/pull or open drain drivers. The following Port 6 pins also serve for alternate functions: E4 O P6.0 CS0 Chip Select 0 Output D3 O P6.1 CS1 Chip Select 1 Output B1 O P6.2 CS2 Chip Select 2 Output C1 O P6.3 CS3 Chip Select 3 Output D2 O P6.4 CS4 Chip Select 4 Output E3 I P6.5 HOLD External Master Hold Request Input F4 O P6.6 HLDA Hold Acknowledge Output D1 O P6.7 BREQ Bus Request Output I/O Port 8 is an 8-bit bidirectional I/O port. It is bit-wise programmable for input or output via direction bits. For a pin configured as input, the output driver is put into high-impedance state. Port 8 outputs can be configured as push/pull or open drain drivers. The input threshold of Port 8 is selectable (TTL or special). The following Port 8 pins also serve for alternate functions: E2 I/O P8.0 CC16IO CAPCOM2: CC16 Capture Input / Compare Output F3 I/O P8.1 CC17IO CAPCOM2: CC17 Capture Input / Compare Output F2 I/O P8.2 CC18IO CAPCOM2: CC18 Capture Input / Compare Output G3 I/O P8.3 CC19IO CAPCOM2: CC19 Capture Input / Compare Output G2 I/O P8.4 CC20IO CAPCOM2: CC20 Capture Input / Compare Output H4 I/O P8.5 CC21IO CAPCOM2: CC21 Capture Input / Compare Output H3 I/O P8.6 CC22IO CAPCOM2: CC22 Capture Input / Compare Output H2 I/O P8.7 CC23IO CAPCOM2: CC23 Capture Input / Compare Output Doc ID 8673 Rev. 3 15/239 Ball data ST10F280 Table 1. Symbol P7.0 - P7.7 XP10.0 - XP10.15 16/239 Ball description (continued) Ball Type number Function I/O Port 7 is an 8-bit bidirectional I/O port. It is bit-wise programmable for input or output via direction bits. For a pin configured as input, the output driver is put into high-impedance state. Port 7 outputs can be configured as push/pull or open drain drivers. The input threshold of Port 7 is selectable (TTL or special). The following Port 7 pins also serve for alternate functions: J4 O P7.0 POUT0 PWM Channel 0 Output J3 O P7.1 POUT1 PWM Channel 1 Output J2 O P7.2 POUT2 PWM Channel 2 Output J1 O P7.3 POUT3 PWM Channel 3 Output K2 I/O P7.4 CC28IO CAPCOM2: CC28 Capture Input / Compare Output K3 I/O P7.5 CC29IO CAPCOM2: CC29 Capture Input / Compare Output K4 I/O P7.6 CC30IO CAPCOM2: CC30 Capture Input / Compare Output L2 I/O P7.7 CC31IO CAPCOM2: CC31 Capture Input / Compare Output I XPort 10 is a 16-bit input-only port with Schmitt-Trigger characteristics. The pins of XPort10 also serve as the analog input channels (up to 16) for the A/D converter, where XP10.X equals ANx (Analog input channel x). I I I I I I I I I I I I I I I I XP10.0 XP10.1 XP10.2 XP10.3 XP10.4 XP10.5 XP10.6 XP10.7 XP10.8 XP10.9 XP10.10 XP10.11 XP10.12 XP10.13 XP10.14 XP10.15 M4 M3 M2 M1 N4 N3 N2 N1 P4 P3 P2 P1 R2 R1 T1 U1 Doc ID 8673 Rev. 3 ST10F280 Ball data Table 1. Ball description (continued) Symbol P5.0 - P5.15 Ball Type number Function I Port 5 is a 16-bit input-only port with Schmitt-Trigger characteristics. The pins of Port 5 also serve as the analog input channels (up to 16) for the A/D converter, where P5.x equals ANx (Analog input channel x), or they serve as timer inputs: T2 I P5.0 R3 I P5.1 T3 I P5.2 R4 I P5.3 T4 I P5.4 U4 I P5.5 P5 I P5.6 R5 I P5.7 T5 I P5.8 U5 I P5.9 P6 I P5.10 T6EUD GPT2 Timer T6 External Up / Down Control Input R6 I P5.11 T5EUD GPT2 Timer T5 External Up / Down Control Input T6 I P5.12 T6IN GPT2 Timer T6 Count Input U6 I P5.13 T5IN GPT2 Timer T5 Count Input P7 I P5.14 T4EUD GPT1 Timer T4 External Up / Down Control Input R7 I P5.15 T2EUD GPT1 Timer T2 External Up / Down Control Input Doc ID 8673 Rev. 3 17/239 Ball data ST10F280 Table 1. Ball description (continued) Symbol P2.0 - P2.15 18/239 Ball Type number Function I/O Port 2 is a 16-bit bidirectional I/O port. It is bit-wise programmable for input or output via direction bits. For a pin configured as input, the output driver is put into high-impedance state. Port 2 outputs can be configured as push/pull or open drain drivers. The input threshold of Port 2 is selectable (TTL or special). The following Port 2 pins also serve for alternate functions: T7 I/O P2.0 CC0IO CAPCOM: CC0 Capture Input / Compare Output P8 I/O P2.1 CC1IO CAPCOM: CC1 Capture Input / Compare Output R8 I/O P2.2 CC2IO CAPCOM: CC2 Capture Input / Compare Output T8 I/O P2.3 CC3IO CAPCOM: CC3 Capture Input / Compare Output T9 I/O P2.4 CC4IO CAPCOM: CC4 Capture Input / Compare Output P9 I/O P2.5 CC5IO CAPCOM: CC5 Capture Input / Compare Output R9 I/O P2.6 CC6IO CAPCOM: CC6 Capture Input / Compare Output U9 I/O P2.7 CC7IO CAPCOM: CC7 Capture Input / Compare Output T10 I/O I P2.8 CC8IO CAPCOM: CC8 Capture Input / Compare Output, EX0IN Fast External Interrupt 0 Input R10 I/O I P2.9 CC9IO CAPCOM: CC9 Capture Input / Compare Output, EX1IN Fast External Interrupt 1 Input P10 I/O I P2.10 CC10IO CAPCOM: CC10 Capture Input / Compare Output, EX2IN Fast External Interrupt 2 Input T11 I/O I P2.11 CC11IO CAPCOM: CC11 Capture Input / Compare Output, EX3IN Fast External Interrupt 3 Input R11 I/O I P2.12 CC12IO CAPCOM: CC12 Capture Input / Compare Output, EX4IN Fast External Interrupt 4 Input U12 I/O I P2.13 CC13IO CAPCOM: CC13 Capture Input / Compare Output, EX5IN Fast External Interrupt 5 Input P11 I/O I P2.14 CC14IO CAPCOM: CC14 Capture Input / Compare Output, EX6IN Fast External Interrupt 6 Input T12 I/O I I P2.15 CC15IO CAPCOM: CC15 Capture Input / Compare Output, EX7IN Fast External Interrupt 7 Input T7IN CAPCOM2 Timer T7 Count Input Doc ID 8673 Rev. 3 ST10F280 Ball data Table 1. Ball description (continued) Symbol Ball Type number I/O P3.0 - P3.13, P3.15 Function Port 3 is a 15-bit (P3.14 is missing) bidirectional I/O port. It is bitwise programmable for input or output via direction bits. For a pin configured as input, the output driver is put into high-impedance state. Port 3 outputs can be configured as push/pull or open drain drivers. The input threshold of Port 3 is selectable (TTL or special). The following Port 3 pins also serve for alternate functions: R12 I P3.0 T0IN CAPCOM Timer T0 Count Input T13 O P3.1 T6OUT GPT2 Timer T6 Toggle Latch Output P12 I P3.2 CAPIN GPT2 Register CAPREL Capture Input R13 O P3.3 T3OUT GPT1 Timer T3 Toggle Latch Output T14 I P3.4 T3EUD GPT1 Timer T3 External Up / Down Control Input P13 I P3.5 T4IN GPT1 Timer T4 Input for Count / Gate / Reload / Capture R14 I P3.6 T3IN GPT1 Timer T3 Count / Gate Input P14 I P3.7 T2IN GPT1 Timer T2 Input for Count / Gate / Reload / Capture R15 I/O P3.8 MRST SSC Master-Receive / Slave-Transmit I/O R16 I/O P3.9 MTSR SSC Master-Transmit / Slave-Receive O/I N14 I/O P3.10 TxD0 ASC0 Clock / Data Output (Asynchronous / Synchronous) P15 O P3.11 RxD0 ASC0 Data Input (Asynchronous) or I/O (Synchronous) P16 O P3.12 BHE External Memory High Byte Enable Signal, WRH External Memory High Byte Write Strobe M14 I/O P3.13 SCLK SSC Master Clock Output / Slave Clock Input T17 O P3.15 CLKOUT System Clock Output (= CPU Clock) Doc ID 8673 Rev. 3 19/239 Ball data ST10F280 Table 1. Symbol P4.0 - P4.7 RD WR/WRL Ball Type number Function I/O Port 4 is an 8-bit bidirectional I/O port. It is bit-wise programmable for input or output via direction bits. For a pin configured as input, the output driver is put into high-impedance state. The input threshold is selectable (TTL or special). P4.6 & P4.7 outputs can be configured as push-pull or open-drain drivers. In case of an external bus configuration, Port 4 can be used to output the segment address lines: N16 O P4.0 A16 Least Significant Segment Address Line M15 O P4.1 A17 Segment Address Line L14 O P4.2 A18 Segment Address Line M16 O P4.3 A19 Segment Address Line L15 O I P4.4 A20 Segment Address Line CAN2_RxD CAN2 Receive Data Input L16 O I P4.5 A21 Segment Address Line CAN1_RxD CAN1 Receive Data Input K14 O O P4.6 A22 Segment Address Line, CAN_TxD CAN1_TxD CAN1 Transmit Data Output K15 O O P4.7 A23 Most Significant Segment Address Line CAN2_TxD CAN2 Transmit Data Output J14 O External Memory Read Strobe. RD is activated for every external instruction or data read access. O External Memory Write Strobe. In WR-mode this pin is activated for every external data write access. In WRL-mode this pin is activated for low byte data write accesses on a 16-bit bus, and for every data write access on an 8-bit bus. See WRCFG in register SYSCON for mode selection. J15 READY/ READY J16 I Ready Input. The active level is programmable. When the Ready function is enabled, the selected inactive level at this pin during an external memory access will force the insertion of memory cycle time waitstates until the pin returns to the selected active level. ALE J17 O Address Latch Enable Output. Can be used for latching the address into external memory or an address latch in the multiplexed bus modes. I External Access Enable pin. A low level at this pin during and after Reset forces the ST10F280 to begin instruction execution out of external memory. A high level forces execution out of the internal Flash Memory. EA 20/239 Ball description (continued) H17 Doc ID 8673 Rev. 3 ST10F280 Ball data Table 1. Ball description (continued) Symbol PORT0: P0L.0 - P0L.7, P0H.0 - P0H.7 Ball Type number Function I/O PORT0 consists of the two 8-bit bidirectional I/O ports P0L and P0H. It is bit-wise programmable for input or output via direction bits. For a pin configured as input, the output driver is put into highimpedance state. In case of an external bus configuration, PORT0 serves as the address (A) and address/data (AD) bus in multiplexed bus modes and as the data (D) bus in demultiplexed bus modes. Demultiplexed bus modes: Data Path Width: 8-bit 16-bit P0L.0 - P0L.7: D0 - D7 D0 - D7 P0H.0 - P0H.7: I/O D8 - D15 Multiplexed bus modes: Data Path Width: 8-bit 16-bit P0L.0 - P0L.7: AD0 - AD7 AD0 - AD7 P0H.0 - P0H.7: A8 - A15 AD8 - AD15 H16 I/O P0L.0 H15 I/O P0L.1 H14 I/O P0L.2 G16 I/O P0L.3 G15 I/O P0L.4 G14 I/O P0L.5 F16 I/O P0L.6 E17 I/O P0L.7 F15 I/O P0H.0 E16 I/O P0H.1 F14 I/O P0H.2 D17 I/O P0H.3 E15 I/O P0H.4 D16 I/O P0H.5 C17 I/O P0H.6 E14 I/O P0H.7 Doc ID 8673 Rev. 3 21/239 Ball data ST10F280 Table 1. Symbol XPORT9.0 XPORT9.15 22/239 Ball description (continued) Ball Type number Function I/O XPort 9 is a 16-bit bidirectional I/O port. It is bit-wise programmable for input or output via direction bits. For a pin configured as input, the output driver is put into high-impedance state. XPort 9 outputs can be configured as push/pull or open drain drivers. D15 I/O XPORT9.0 C16 I/O XPORT9.1 D14 I/O XPORT9.2 C15 I/O XPORT9.3 B16 I/O XPORT9.4 D13 I/O XPORT9.5 C14 I/O XPORT9.6 B15 I/O XPORT9.7 A15 I/O XPORT9.8 B14 I/O XPORT9.9 C13 I/O XPORT9.10 D12 I/O XPORT9.11 B13 I/O XPORT9.12 C12 I/O XPORT9.13 D11 I/O XPORT9.14 B12 I/O XPORT9.15 Doc ID 8673 Rev. 3 ST10F280 Ball data Table 1. Ball description (continued) Symbol PORT1: P1L.0 - P1L.7, P1H.0 - P1H.7 XTAL1 XTAL2 RSTIN RSTOUT Ball Type number Function I/O PORT1 consists of the two 8-bit bidirectional I/O ports P1L and P1H. It is bit-wise programmable for input or output via direction bits. For a pin configured as input, the output driver is put into highimpedance state. PORT1 is used as the 16-bit address bus (A) in demultiplexed bus modes and also after switching from a demultiplexed bus mode to a multiplexed bus mode. The following PORT1 pins also serve for alternate functions: C11 I/O P1L.0 B11 I/O P1L.1 D10 I/O P1L.2 C10 I/O P1L.3 B10 I/O P1L.4 A10 I/O P1L.5 D9 I/O P1L.6 C9 I/O P1L.7 C8 I/O P1H.0 D8 I/O P1H.1 A7 I/O P1H.2 B7 I/O P1H.3 C7 I P1H.4 CC24IO CAPCOM2: CC24 Capture Input D7 I P1H.5 CC25IO CAPCOM2: CC25 Capture Input C5 I P1H.6 CC26IO CAPCOM2: CC26 Capture Input C6 I P1H.7 CC27IO CAPCOM2: CC27 Capture Input A5 I XTAL1: Input to the oscillator amplifier and input to the internal clock generator O XTAL2: Output of the oscillator amplifier circuit. To clock the device from an external source, drive XTAL1, while leaving XTAL2 unconnected. Minimum and maximum high/low and rise/fall times specified in the AC Characteristics must be observed. I Reset Input with Schmitt-Trigger characteristics. A low level at this pin for a specified duration while the oscillator is running resets the ST10F280. An internal pull-up resistor permits power-on reset using only a capacitor connected to VSS. In bidirectional reset mode (enabled by setting bit BDRSTEN in SYSCON register), the RSTIN line is pulled low for the duration of the internal reset sequence. O Internal Reset Indication Output. This pin is set to a low level when the part is executing either a hardware, a software or a watchdog timer reset. RSTOUT remains low until the EINIT (end of initialization) instruction is executed. A6 A3 B4 Doc ID 8673 Rev. 3 23/239 Ball data ST10F280 Table 1. Symbol 24/239 Ball description (continued) Ball Type number Function NMI C4 I Non-Maskable Interrupt Input. A high to low transition at this pin causes the CPU to vector to the NMI trap routine. If bit PWDCFG = `0' in SYSCON register, when the PWRDN (power down) instruction is executed, the NMI pin must be low in order to force the ST10F280 to go into power down mode. If NMI is high and PWDCFG ='0', when PWRDN is executed, the part will continue to run in normal mode. If not used, pin NMI should be pulled high externally. XPWM.0 D4 O XPWM Channel 0 Output XPWM.1 C3 O XPWM Channel 1 Output XPWM.2 B2 O XPWM Channel 2 Output XPWM.3 C2 O XPWM Channel 3 Output XADCINJ L3 O Output trigger for ADC channel injection VAREF U2 - Reference voltage for the A/D converter. VAGND U3 - Reference ground for the A/D converter. RPD M17 I/O Timing pin for the return from powerdown circuit and synchronous/asynchronous reset selection. DC1 G1 O 3.3V Decoupling pin: a decoupling capacitor of ~330 nF must be connected between this pin and nearest VSS pin. DC2 U11 O 3.3V Decoupling pin: a decoupling capacitor of ~330 nF must be connected between this pin and VSS nearest pin. VDD A2 A9 A12 A14 E1 K1 U8 U15 P17 L17 G17 - Digital Supply Voltage: + 5 V during normal operation, idle mode and power down mode Doc ID 8673 Rev. 3 ST10F280 Ball data Table 1. Symbol VSS Ball description (continued) Ball Type number A1 A4 A8 A11 A13 A16 A17 B3 B5 B6 B8 B9 B17 D5 D6 F1 F17 G4 H1 K16 K17 L1 L4 N15 N17 R17 T15 T16 U7 U10 U13 U14 U16 U17 - Function Digital ground. Doc ID 8673 Rev. 3 25/239 Functional description 3 ST10F280 Functional description The architecture of the ST10F280 combines advantages of both RISC and CISC processors and an advanced peripheral subsystem. The block diagram gives an overview of the different on-chip components and the high bandwidth internal bus structure of the ST10F280. Block diagram + "YTE &LASH -EMORY + "YTE )NTERNAL 2!- #05 #ORE AND -!# 5NIT 7ATCHDOG 0%# + "YTE 82!- )NTERRUPT #ONTROLLER 0ORT 0ORT 80/24 80/24 807- 84)-%2 #!0#/- "2' #!0#/- "2' 07- 33# '04 0ORT 0ORT !3# USART '04 "IT !$# 84!, 6OLTAGE 2EGULATOR 6 #!. %XTERNAL "US #ONTROLLER 0 #!.?2X$ 0 #!.?4X$ 84!, #!. 0ORT 0ORT 0ORT 0 #!.?2X$ 0 #!.?4X$ /SCILLATOR AND 0,, 0ORT Figure 3. 0ORT 0 4RIGGER FOR !$# CHANNEL INJECTION %XTERNAL CONNEXION 8!$#).* ("1($'5 26/239 Doc ID 8673 Rev. 3 ST10F280 4 Memory organization Memory organization The memory space of the ST10F280 is configured in a unified memory architecture. Code memory, data memory, registers and I/O ports are organized within the same linear address space of 16M Bytes. The entire memory space can be accessed byte-wise or word-wise. Particular portions of the on-chip memory have additionally been made directly bit addressable. FLASH: 512K Bytes of on-chip single voltage FLASH memory. IRAM: 2K Bytes of on-chip internal RAM (dual-port) is provided as a storage for data, system stack, general purpose register banks and code. The register bank can consist of up to 16 word-wide (R0 to R15) and/or byte-wide (RL0, RH0, ..., RL7, RH7) general purpose registers. Base address is 00'F600h, upper address is 00'FDFFh. XRAM: 16K Bytes of on-chip extension RAM (single port XRAM) is provided as a storage for data, user stack and code. The XRAM is a single bank, connected to the internal XBUS and are accessed like an external memory in 16-bit demultiplexed bus-mode without waitstate or read/write delay (50ns access at 40MHz CPU clock). Byte and word access is allowed. The XRAM address range is 00'8000h - 00'BFFFh if enabled (XPEN set bit 2 of SYSCON register-, and XRAMEN set bit 2 of XPERCON register-). If bit XRAMEN or XPEN is cleared, then any access in the address range 00'8000h 00'BFFFh will be directed to external memory interface, using the BUSCONx register corresponding to address matching ADDRSELx register As the XRAM appears like external memory, it cannot be used for the ST10F280's system stack or register banks. The XRAM is not provided for single bit storage and therefore is not bit addressable. SFR/ESFR: 1024 bytes (2 * 512 bytes) of address space is reserved for the special function register areas. SFRs are word-wide registers which are used for controlling and monitoring functions of the different on-chip units. CAN1: Address range 00'EF00h 00'EFFFh is reserved for the CAN1 Module access. The CAN1 is enabled by setting XPEN bit 2 of the SYSCON register and bit 0 of the new XPERCON register. Accesses to the CAN Module use demultiplexed addresses and a 16bit data bus (byte accesses are possible). Two waitstates give an access time of 100 ns at 40MHz CPU clock. No tristate waitstate is used. CAN2: Address range 00'EE00h 00'EEFFh is reserved for the CAN2 Module access. The CAN2 is enabled by setting XPEN bit 2 of the SYSCON register and bit 1 of the new XPERCON register. Accesses to the CAN Module use demultiplexed addresses and a 16bit data bus (byte accesses are possible). Two waitstates give an access time of 100 ns at 40MHz CPU clock. No tristate waitstate is used. In order to meet the needs of designs where more memory is required than is provided on chip, up to 16M Bytes of external RAM and/or ROM can be connected to the microcontroller. If one or the two CAN modules are used, Port 4 can not be programmed to output all 8 segment address lines. Thus, only 4 segment address lines can be used, reducing the external memory space to 5M Bytes (1M Byte per CS line). XPWM: Address range 00'EC00h 00'ECFFh is reserved for the XPWM Module access. The XPWM is enabled by setting XPEN bit 2 of the SYSCON register and bit 4 of the new XPERCON register. Accesses to the XPWM Module use demultiplexed addresses and a 16- Doc ID 8673 Rev. 3 27/239 Memory organization ST10F280 bit data bus (byte accesses are possible). Two waitstates give an access time of 100 ns at 40MHz CPU clock. No tristate waitstate is used. XPORT9, XTIMER, XPORT10, XADCMUX: Address range 00'C000h 00'C3FFh is reserved for the XPORT9, XPORT10, XTIMER and XADCMUX peripherals access. The XPORT9, XTIMER, XPORT10, XADCMUX are enabled by setting XPEN bit 2 of the SYSCON register and the bit 3 of the new XPERCON register. Accesses to the XPORT9, XTIMER, XPORT10 and XADCMUX modules use a 16-bit demultiplexed bus mode without waitstate or read/write delay (50ns access at 40MHz CPU clock). Byte and word access is allowed. 4.1 Visibility of XBUS peripherals The XBUS peripherals can be separately selected for being visible to the user by means of corresponding selection bits in the XPERCON register. If not selected (not activated with XPERCON bit) before the global enabling with XPEN-bit in SYSCON register, the corresponding address space, port pins and interrupts are not occupied by the peripheral, thus the peripheral is not visible and not available. SYSCON register is described in Section 19.2: System configuration registers. 28/239 Doc ID 8673 Rev. 3 ST10F280 Memory organization ST10F280 on-chip memory mapping 6HJPHQW 6HJPHQW 6HJPHQW 6HJPHQW "LOCK + "YTES 2!- 3&2 AND 8 PHERIPHERALS ARE MAPPED INTO THE ADDRESS SPACE &&&& "LOCK + "YTES 3&2 "YTES )( &$&& "LOCK + "YTES # )2!- + "YTES ) "LOCK + "YTES &&& %3&2 "YTES 6HJPHQW "LOCK + "YTES ) %&&& "LOCK "LOCK "LOCK #!. "YTES () %%&& #!. "YTES (( # "&&& %#&& 6HJPHQW Figure 4. 82!- + "YTES 807 (& "LOCK + "YTES "LOCK + "YTES #&& "LOCK + "YTES 80/24 84)-%2 80/24 8!$#-58 & 'DWD 3DJH 1XPEHU $EVROXWH 0HPRU\ $GGUHVV ,QWHUQDO )ODVK 0HPRU\ "LOCKS AND MAY BE REMAPPED FROM SEGMENT TO SEGMENT BY SETTING 393#/. 2/-3 BEFORE %).)4 $ATA 0AGE .UMBER AND !BSOLUTE -EMORY !DDRESS ARE HEXADECIMAL VALUES ("1($'5 Doc ID 8673 Rev. 3 29/239 Memory organization ST10F280 XPERCON 15 14 13 12 11 10 9 8 7 6 5 - - - - - - - - - - - 4 R/W Address: 0xF024h / 12h ESFR Reset: 0x--05h Type: R/W 3 XPWMEN XPERCONEN3 R/W 2 1 0 XRAMEN CAN2EN CAN1EN R/W R/W R/W CAN1EN CAN1 Enable Bit 0: Accesses to the on-chip CAN1 XPeripheral and its functions are disabled. P4.5 and P4.6 pins can be used as general purpose I/Os. Address range 00'EF00h00'EFFFh is only directed to external memory if CAN2EN and XPWM bits are cleared also. 1: The on-chip CAN1 XPeripheral is enabled and can be accessed. CAN2EN CAN2 Enable Bit 0: Accesses to the on-chip CAN2 XPeripheral and its functions are disabled. P4.4 and P4.7 pins can be used as general purpose I/Os. Address range 00'EE00h00'EEFFh is only directed to external memory if CAN1EN and XPWM bits are cleared also. 1: The on-chip CAN2 XPeripheral is enabled and can be accessed. XRAMEN XRAM Enable Bit 0: Accesses to the on-chip 16K Byte XRAM are disabled, external access performed. 1: The on-chip 16K Byte XRAM is enabled and can be accessed. XPERCONEN3 XPORT9, XTIMER, XPORT10, XADCMUX Enable Bit 0: Accesses to the XPORT9, XTIMER, XPORT10, XADCMUX peripherals are disabled, external access performed. 1: The on-chip XPORT9, XTIMER, XPORT10, XADCMUX peripherals are enabled and can be accessed. XPWMEN XPWM Enable Bit 0: Accesses to the on-chip XPWM are disabled, external access performed. Address range 00'EC00h-00'ECFFh is only directed to external memory if CAN1EN and CAN2EN are `0' also 1: The on-chip XPWM is enabled and can be accessed. Note: When both CAN and XPWM are disabled via XPERCON setting, then any access in the address range 00'EC00h 00'EFFFh will be directed to external memory interface, using the BUSCONx register corresponding to address matching ADDRSELx register. P4.4 and P4.7 can be used as General Purpose I/O when CAN2 is not enabled, and P4.5 and P4.6 can be used as General Purpose I/O when CAN1 is not enabled. The default XPER selection after Reset is: XCAN1 is enabled, XCAN2 is disabled, XRAM is enabled, XPORT9, XTIMER, XPORT10, XPWM, XADCMUX are disabled. Register XPERCON cannot be changed after the global enabling of XPeripherals, i.e. after setting of bit XPEN in SYSCON register. 30/239 Doc ID 8673 Rev. 3 ST10F280 Internal Flash memory 5 Internal Flash memory 5.1 Overview 512K Byte on-chip Flash memory Two possibilities of Flash mapping into the CPU address space Flash memory can be used for code and data storage 32-bit, zero waitstate read access (50ns cycle time at fCPU = 40MHz) Erase-Program Controller (EPC) similar to M29F400B STM's stand-alone Flash memory - Word-by-Word Programmable (16s typical) - Data polling and Toggle Protocol for EPC Status - Internal Power-On detection circuit Memory Erase in blocks - One 16K Byte, two 8K Byte, one 32K Byte, seven 64K Byte blocks - Each block can be erased separately (1.5 second typical) - Chip erase (8.5 second typical) - Each block can be separately protected against programming and erasing - Each protected block can be temporary unprotected - When enabled, the read protection prevents access to data in Flash memory using a program running out of the Flash memory space. Access to data of internal Flash can only be performed with an inner protected program Erase Suspend and Resume Modes - Read and Program another Block during erase suspend Single Voltage operation, no need of dedicated supply pin Low Power Consumption: - 45mA max. Read current - 60mA max. Program or Erase current - Automatic Stand-by-mode (50A maximum) 100,000 Erase-Program Cycles per block, 20 year data retention time Operating temperature: -40 to +125oC 5.2 Operational overview 5.2.1 Read mode In standard mode (the normal operating mode) the Flash appears like an on-chip ROM with the same timing and functionality. The Flash module offers a fast access time, allowing zero waitstate access with CPU frequency up to 40MHz. Instruction fetches and data operand reads are performed with all addressing modes of the ST10F280 instruction set. In order to optimize the programming time of the internal Flash, blocks of 8K Bytes, 16K Bytes, 32K Bytes, 64K Bytes can be used. But the size of the blocks does not apply to the whole memory space, see details in Table 2. Doc ID 8673 Rev. 3 31/239 Internal Flash memory Table 2. 5.2.2 ST10F280 512 Kbyte Flash memory block organization Block Addresses (segment 0) Addresses (segment 1) Size (Kbyte) 0 1 2 3 4 5 6 7 8 9 10 00'0000h to 00'3FFFh 00'4000h to 00'5FFFh 00'6000h to 00'7FFFh 01'8000h to 01'FFFFh 02'0000h to 02'FFFFh 03'0000h to 03'FFFFh 04'0000h to 04'FFFFh 05'0000h to 05'FFFFh 06'0000h to 06'FFFFh 07'0000h to 07'FFFFh 08'0000h to 08'FFFFh 01'0000h to 01'3FFFh 01'4000h to 01'5FFFh 01'6000h to 01'7FFFh 01'8000h to 01'FFFFh 02'0000h to 02'FFFFh 03'0000h to 03'FFFFh 04'0000h to 04'FFFFh 05'0000h to 05'FFFFh 06'0000h to 06'FFFFh 07'0000h to 07'FFFFh 08'0000h to 08'FFFFh 16 8 8 32 64 64 64 64 64 64 64 Instructions and commands All operations besides normal read operations are initiated and controlled by command sequences written to the Flash Command Interface (CI). The Command Interface (CI) interprets words written to the Flash memory and enables one of the following operations: Read memory array Program word Block erase Chip erase Erase suspend Erase resume Block protection Block temporary unprotection Code protection Commands are composed of several write cycles at specific addresses of the Flash memory. The different write cycles of such command sequences offer a fail-safe feature to protect against an inadvertent write. A command only starts when the Command Interface has decoded the last write cycle of an operation. Until that last write is performed, Flash memory remains in Read Mode Note: As it is not possible to perform write operations in the Flash while fetching code from Flash, the Flash commands must be written by instructions executed from internal RAM or external memory. Command write cycles do not need to be consecutively received, pauses are allowed, save for Block Erase command. During this operation all Erase Confirm commands must be sent to complete any block erase operation before time-out period expires (typically 96s). Command sequencing must be followed exactly. Any invalid combination of commands will reset the Command Interface to Read Mode. 32/239 Doc ID 8673 Rev. 3 ST10F280 5.2.3 Internal Flash memory Status register This register is used to flag the status of the memory and the result of an operation. This register can be accessed by read cycles during the Erase-Program Controller (EPC) operation. 5.2.4 Erase operation This Flash memory features a block erase architecture with a chip erase capability too. Erase is accomplished by executing the six cycle erase command sequence. Additional command write cycles can then be performed to erase more than one block in parallel. When a time-out period elaps (96s) after the last cycle, the Erase-Program Controller (EPC) automatically starts and times the erase pulse and executes the erase operation. There is no need to program the block to be erased with `0000h' before an erase operation. Termination of operation is indicated in the Flash status register. After erase operation, the Flash memory locations are read as 'FFFFh' value. 5.2.5 Erase suspend A block erase operation is typically executed within 1.5 second for a 64K Byte block. Erasure of a memory block may be suspended, in order to read data from another block or to program data in another block, and then resumed. 5.2.6 In-system programming In-system programming is fully supported. No special programming voltage is required. Because of the automatic execution of erase and programming algorithms, write operations are reduced to transferring commands and data to the Flash and reading the status. Any code that programs or erases Flash memory locations (that writes data to the Flash) must be executed from memory outside the on-chip Flash memory itself (on-chip RAM or external memory). A boot mechanism is provided to support in-system programming. It works using serial link via USART interface and a PC compatible or other programming host. 5.2.7 Read/write protection The Flash module supports read and write protection in a very comfortable and advanced protection functionality. If Read Protection is installed, the whole Flash memory is protected against any "external" read access; read accesses are only possible with instructions fetched directly from program Flash memory. For update of the Flash memory a temporary disable of Flash Read Protection is supported. The device also features a block write protection. Software locking of selectable memory blocks is provided to protect code and data. This feature will disable both program and erase operations in the selected block(s) of the memory. Block Protection is accomplished by block specific lock-bit which are programmed by executing a four cycle command sequence. The locked state of blocks is indicated by specific flags in the according block status registers. A block may only be temporarily unlocked for update (write) operations. With the two possibilities for write protection whole memory or block specific a flexible installation of write protection is supported to protect the Flash memory or parts of it from unauthorized programming or erase accesses and to provide virus-proof protection for all system code blocks. All write protection also is enabled during boot operation. Doc ID 8673 Rev. 3 33/239 Internal Flash memory 5.2.8 ST10F280 Power supply, reset The Flash module uses a single power supply for both read and write functions. Internally generated and regulated voltages are provided for the program and erase operations from 5V supply. Once a program or erase cycle has been completed, the device resets to the standard read mode. At power-on, the Flash memory has a setup phase of some microseconds (dependent on the power supply ramp-up). During this phase, Flash can not be read. Thus, if EA pin is high (execution will start from Flash memory), the CPU remains in reset state until the Flash can be accessed. 5.3 Architectural description The Flash module distinguishes two basic operating modes, the standard read mode and the command mode. The initial state after power-on and after reset is the standard read mode. 5.3.1 Read mode The Flash module enters the standard operating mode, the read mode: After reset command After every completed erase operation After every completed programming operation After every other completed command execution Few microseconds after a CPU-reset has started After incorrect address and data values of command sequences or writing them in an improper sequence After incorrect write access to a read protected Flash memory The read mode remains active until the last command of a command sequence is decoded which starts directly a Flash array operation, such as: Erase one or several blocks Program a word into Flash array Protect / temporary unprotect a block. In the standard read mode read accesses are directly controlled by the Flash memory array, delivering a 32-bit double Word from the addressed position. Read accesses are always aligned to double Word boundaries. Thus, both low order address bit A1 and A0 are not used in the Flash array for read accesses. The high order address bit A18/A17/A16 define the physical 64K Bytes segment being accessed within the Flash array. 5.3.2 Command mode Every operation besides standard read operations is initiated by commands written to the Flash command register. The addresses used for command cycles define in conjunction with the actual state the specific step within command sequences. With the last command of a command sequence, the Erase-Program Controller (EPC) starts the execution of the command. The EPC status is indicated during command execution by: 34/239 Status Register Ready/Busy signal Doc ID 8673 Rev. 3 ST10F280 5.3.3 Internal Flash memory Flash Status Register The Flash Status register is used to flag the status of the Flash memory and the result of an operation. This register can be accessed by Read cycles during the program-Erase Controller operations. The program or erase operation can be controlled by data polling on bit FSB.7 of Status Register, detection of Toggle on FSB.6 and FSB.2, or Error on FSB.5 and Erase Timeout on FSB.3 bit. Any read attempt in Flash during EPC operation will automatically output these five bits. The EPC sets bit FSB.2, FSB.3, FSB.5, FSB.6 and FSB.7. Other bit are reserved for future use and should be masked. Flash Status 15 14 13 12 11 10 9 8 - - - - - - - - 7 R Address: See note for address Type: R 6 5 FSB.7 FSB.6 FSB.5 R R 4 - 3 2 FSB.3 FSB.2 R 1 0 - - R FSB.7 Flash Status bit 7: Data Polling Bit Programming Operation: this bit outputs the complement of the bit 7 of the word being programmed, and after completion, will output the bit 7 of the word programmed. Erasing Operation: outputs a `0' during erasing, and `1' after erasing completion. If the block selected for erasure is (are) protected, FSB.7 will be set to `0' for about 100 s, and then return to the previous addressed memory data value. FSB.7 will also flag the Erase Suspend Mode by switching from `0' to `1' at the start of the Erase Suspend. During Program operation in Erase Suspend Mode, FSB.7 will have the same behaviour as in normal Program execution outside the Suspend mode. FSB.6 Flash Status bit 6: Toggle Bit Programming or Erasing Operations: successive read operations of Flash Status register will deliver complementary values. FSB.6 will toggle each time the Flash Status register is read. The Program operation is completed when two successive reads yield the same value. The next read will output the bit last programmed, or a `1' after Erase operation FSB.6 will be set to`1' if a read operation is attempted on an Erase Suspended block. In addition, an Erase Suspend/Resume command will cause FSB.6 to toggle. FSB.5 Flash Status bit 5: Error Bit This bit is set to `1' when there is a failure of Program, block or chip erase operations.This bit will also be set if a user tries to program a bit to `1' to a Flash location that is currently programmed with `0'. The error bit resets after Read/Reset instruction. In case of success, the Error bit will be set to `0' during Program or Erase and then will output the bit last programmed or a `1' after erasing FSB.3 Flash Status bit 3: Erase Time-out Bit This bit is cleared by the EPC when the last Block Erase command has been entered to the Command Interface and it is awaiting the Erase start. When the time-out period is finished, after 96 s, FSB.3 returns back to `1'. Doc ID 8673 Rev. 3 35/239 Internal Flash memory ST10F280 FSB.2 Flash Status bit 2: Toggle Bit This toggle bit, together with FSB.6, can be used to determine the chip status during the Erase Mode or Erase Suspend Mode. It can be used also to identify the block being Erased Suspended. A Read operation will cause FSB.2 to Toggle during the Erase Mode. If the Flash is in Erase Suspend Mode, a Read operation from the Erase suspended block or a Program operation into the Erase suspended block will cause FSB.2 to toggle. When the Flash is in Program Mode during Erase Suspend, FSB.2 will be read as `1' if address used is the address of the word being programmed. After Erase completion with an Error status, FSB.2 will toggle when reading the faulty sector. Note: The Address of Flash Status Register is the address of the word being programmed when Programming operation is in progress, or an address within block being erased when Erasing operation is in progress. 5.3.4 Flash Protection Register The Flash Protection register is a non-volatile register that contains the protection status. This register can be read by using the Read Protection Status (RP) command, and programmed by using the dedicated Set Protection command. Flash Protection Register (PR) 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0 CP - - - - BP10 BP9 BP8 BP7 BP6 BP5 BP4 BP3 BP2 BP1 BP0 R/W R/W R/W R/W R/W R/W R/W R/W R/W R/W R/W R/W Type: R/W BPx Block x Protection bit (x = 0...10) `0': the Block Protection is enabled for block x. Programming or erasing the block is not possible, unless a Block Temporary Unprotection command is issued. 1': the Block Protection is disabled for block x. Bit is `1' by default, and can be programmed permanently to `0' using the Set Protection command but then cannot be set to `1' again. It is therefore possible to temporally disable the Block Protection using the Block Temporary Unprotection instruction. CP Code Protection Bit `0': the Flash Code Protection is enabled. Read accesses to the Flash for execution not performed in the Flash itself are not allowed, the returned value will be 009Bh, whatever the content of the Flash is. 1': the Flash Code Protection is disabled: read accesses to the Flash from external or internal RAM are allowed Bit is `1' by default, and can be programmed permanently to `0' using the Set Protection command but then cannot be set to `1' again. It is therefore possible to temporarily disable the Code Protection using the Code Temporary Unprotection instruction. 5.3.5 Instructions description Twelve instructions dedicated to Flash memory accesses are defined as follow: Read/Reset (RD). The Read/Reset instruction consist of one write cycle with data XXF0h. it can be optionally preceded by two CI enable coded cycles (data xxA8h at address 1554h + 36/239 Doc ID 8673 Rev. 3 ST10F280 Internal Flash memory data xx54h at address 2AA8h). Any successive read cycle following a Read/Reset instruction will read the memory array. A Wait cycle of 10s is necessary after a Read/Reset command if the memory was in program or Erase mode. Program Word (PW). This instruction uses four write cycles. After the two Cl enable coded cycles, the Program Word command xxA0h is written at address 1554h. The following write cycle will latch the address and data of the word to be programmed. Memory programming can be done only by writing 0's instead of 1's, otherwise an error occurs. During programming, the Flash Status is checked by reading the Flash Status bit FSB.2, FSB.5, FSB.6 and FSB.7 which show the status of the EPC. FSB.2, FSB.6 and FSB.7 determine if programming is on going or has completed, and FSB.5 allows a check to be made for any possible error. Block Erase (BE). This instruction uses a minimum of six command cycles. The erase enable command xx80h is written at address 1554h after the two-cycle CI enable sequence. The erase confirm code xx30h must be written at an address related to the block to be erased preceded by the execution of a second CI enable sequence. Additional erase confirm codes must be given to erase more than one block in parallel. Additional erase confirm commands must be written within a defined time-out period. The input of a new Block Erase command will restart the time-out period. When this time-out period has elapsed, the erase starts. The status of the internal timer can be monitored through the level of FSB.3, if FSB.3 is `0', the Block Erase command has been given and the timeout is running; if FSB.3 is `1', the timeout has expired and the EPC is erasing the block(s). If the second command given is not an erase confirm or if the coded cycles are wrong, the instruction aborts, and the device is reset to Read Mode. It is not necessary to program the block with 0000h as the EPC will do this automatically before the erasing to FFFFh. Read operations after the EPC has started, output the Flash Status Register. During the execution of the erase by the EPC, the device accepts only the Erase Suspend and Read/Reset instructions. Data Polling bit FSB.7 returns `0' while the erasure is in progress, and `1' when it has completed. The Toggle bit FSB.2 and FSB.6 toggle during the erase operation. They stop when erase is completed. After completion, the Error bit FSB.5 returns `1' if there has been an erase failure because erasure has not completed even after the maximum number of erase cycles have been executed by the EPC, in this case, it will be necessary to input a Read/Reset to the Command Interface in order to reset the EPC. Chip Erase (CE). This instruction uses six write cycles. The Erase Enable command xx80h, must be written at address 1554h after CI-Enable cycles. The Chip Erase command xx10h must be given on the sixth cycle after a second CI-Enable sequence. An error in command sequence will reset the CI to Read mode. It is NOT necessary to program the block with 0000h as the EPC will do this automatically before the erasing to FFFFh. Read operations after the EPC has started output the Flash Status Register. During the execution of the erase by the EPC, Data Polling bit FSB.7 returns `0' while the erasure is in progress, and `1' when it has completed. The FSB.2 and FSB.6 bit toggle during the erase operation. They stop when erase is finished. The FSB.5 error bit returns "1" in case of failure of the erase operation. The error flag is set after the maximum number of erase cycles have been executed by the EPC. In this case, it will be necessary to input a Read/Reset to the Command Interface in order to reset the EPC. Erase Suspend (ES). This instruction can be used to suspend a Block Erase operation by giving the command xxB0h without any specific address. No CI-Enable cycles is required. Erase Suspend operation allows reading of data from another block and/or the programming in another block while erase is in progress. If this command is given during the time-out Doc ID 8673 Rev. 3 37/239 Internal Flash memory ST10F280 period, it will terminate the time-out period in addition to erase Suspend. The Toggle Bit FSB.6, when monitored at an address that belongs to the block being erased, stops toggling when Erase Suspend Command is effective, It happens between 0.1s and 15s after the Erase Suspend Command has been written. The Flash will then go in normal Read Mode, and read from blocks not being erased is valid, while read from block being erased will output FSB.2 toggling. During a Suspend phase the only instructions valid are Erase Resume and Program Word. A Read / Reset instruction during Erase suspend will definitely abort the Erase and result in invalid data in the block being erased. Erase Resume (ER). This instruction can be given when the memory is in Erase Suspend State. Erase can be resumed by writing the command xx30h at any address without any Clenable sequence. Program during Erase Suspend. The Program Word instruction during Erase Suspend is allowed only on blocks that are not Erase-suspended. This instruction is the same than the Program Word instruction. Set Protection (SP). This instruction can be used to enable both Block Protection (to protect each block independently from accidental Erasing-Programming Operation) and Code Protection (to avoid code dump). The Set Protection Command must be given after a special CI-Protection Enable cycles (see instruction table). The following Write cycle, will program the Protection Register. To protect the block x (x = 0 to 10), the data bit x must be at `0'. To protect the code, bit 15 of the data must be `0'. Enabling Block or Code Protection is permanent and can be cleared only by STM. Block Temporary Unprotection and Code Temporary Unprotection instructions are available to allow the customer to update the code. Note: The new value programmed in protection register will only become active after a reset. Bit that are already at '0' in protection register must be confirmed at '0' also in data latched during the 4th cycle of set protection command, otherwise an error may occur. Read Protection Status (RP). This instruction is used to read the Block Protection status and the Code Protection status. To read the protection register (see Table 3), the CIProtection Enable cycles must be executed followed by the command xx90h at address x2A54h. The following Read Cycles at any odd word address will output the Block Protection Status. The Read/Reset command xxF0h must be written to reset the protection interface. Note: After a modification of protection register (using Set Protection command), the Read Protection Status will return the new PR value only after a reset. Block Temporary Unprotection (BTU). This Instruction can be used to temporary unprotect all the blocks from Program / Erase protection. The Unprotection is disabled after a Reset cycle. The Block Temporary Unprotection command xxC1h must be given to enable Block Temporary Unprotection. The Command must be preceded by the CI-Protection Enable cycles and followed by the Read/Reset command xxF0h. Set Code Protection (SCP). This kind of protection allows the customer to protect the proprietary code written in Flash. If installed and active, Flash Code Protection prevents data operand accesses and program branches into the on-chip Flash area from any location outside the Flash memory itself. Data operand accesses and branches to Flash locations are only and exclusively allowed for instructions executed from the Flash memory itself. Every read or jump to Flash performed from another memory (like internal RAM, external memory) while Code Protection is enabled, will give the opcode 009Bh related to TRAP #00 illegal instruction. The CI-Protection Enable cycles must be sent to set the Code Protection. By writing data 7FFFh at any odd word address, the Code Protected status is stored in the Flash Protection Register (PR). Protection is permanent and cannot be cleared by the user. 38/239 Doc ID 8673 Rev. 3 ST10F280 Internal Flash memory It is possible to temporarily disable the Code Protection using Code Temporary Unprotection instruction. Note: Bits that are already at '0' in protection register must be confirmed at '0' also in data latched during the 4th cycle of set protection command, otherwise an error may occur. Code Temporary Unprotection (CTU). This instruction must be used to temporary disable Code Protection. This instruction is effective only if executed from Flash memory space. To restore the protection status, without using a reset, it is necessary to use a Code Temporary Protection instruction. System reset will reset also the Code Temporary Unprotected status. The Code Temporary Unprotection command consists of the following write cycle: MOV MEM, Rn ; This instruction MUST be executed from Flash memory space Where MEM is an absolute address inside memory space, Rn is a register loaded with data 0FFFFh. Code Temporary Protection (CTP). This instruction allows to restore Code Protection. This operation is effective only if executed from Flash memory and is necessary to restore the protection status after the use of a Code Temporary Unprotection instruction. The Code Temporary Protection command consists of the following write cycle: MOV MEM, Rn ; This instruction MUST be executed from Flash memory space Where MEM is an absolute address inside memory space, Rn is a register loaded with data 0FFFBh. Note that Code Temporary Unprotection instruction must be used when it is necessary to modify the Flash with protected code (SCP), since the write/erase routines must be executed from a memory external to Flash space. Usually, the write/erase routines, executed in RAM, ends with a return to Flash space where a CTP instruction restore the protection. Table 3. Instructions Instruction Read/Reset Read/Reset Program Word Block Erase Chip Erase Erase Suspend 1st Cycle Mne Cycle RD RD PW BE CE ES 2nd Cycle 3rd Cycle 4th Cycle 5th Cycle 6th Cycle 7th Cycle Addr.(1) X(2) Data xxF0h Addr.(1) x1554h x2AA8h xxxxxh Data xxA8h xx54h xxF0h Addr.(1) x1554h x2AA8h x1554h WA(3) Data xxA8h xx54h xxA0h WD(4) Addr.(1) x1554h x2AA8h x1554h x1554h x2AA8h BA BA'(5) Data xxA8h xx54h xx80h xxA8h xx54h xx30h xx30h Addr.(1) x1554h x2AA8h x1554h x1554h Data xxA8h xx54h xx80h xxA8h Addr.(1) X(2) Data xxB0h 1+ Read Memory Array until a new write cycle is initiated 3+ 4 Read Memory Array until a new write cycle is initiated Read Data Polling or Toggle Bit until Program completes. 6 x2AA8h x1554h 6 1 xx54h xx10h Note (6) Read until Toggle stops, then read or program all data needed from block(s) not being erased then Resume Erase. Doc ID 8673 Rev. 3 39/239 Internal Flash memory Table 3. ST10F280 Instructions (continued) Instruction Erase Resume Set Block/Code Protection Read Protection Status Block Temporary Unprotection ER SP RP BTU Code Temporary Unprotection CTU Code Temporary Protection 1st Cycle Mne Cycle CTP 2nd Cycle 3rd Cycle 4th Cycle Addr.(1) X(2) Data xx30h Addr.(1) x2A54h x15A8h x2A54h Any odd word address(7) Data xxA8h xx54h xxC0h WPR(8) Addr.(1) x2A54h x15A8h x2A54h Data xxA8h xx54h xx90h Addr.(1) x2A54h x15A8h x2A54h X(2) Data xxA8h xx54h xxC1h xxF0h Addr.(1) MEM(9) Data FFFFh Addr.(1) MEM(9) Data FFFBh 1 5th Cycle 6th Cycle 7th Cycle Read Data Polling or Toggle bit until Erase completes or Erase is suspended another time. 4 4 Any odd word Read Protection Register address(7) until a new write cycle is initiated. Read PR 4 Write cycles must be executed from Flash. 1 Write cycles must be executed from Flash. 1 1. Address bit A14, A15 and above are don't care for coded address inputs. 2. X = do not care. 3. WA = Write Address: address of memory location to be programmed. 4. WD = Write Data: 16-bit data to be programmed. 5. Optional, additional blocks addresses must be entered within a time-out delay (96 s) after last write entry, timeout status can be verified through FSB.3 value. When full command is entered, read Data Polling or Toggle bit until Erase is completed or suspended 6. Read Data Polling or Toggle bit until Erase completes. 7. Odd word address = 4n-2 where n = 0, 1, 2, 3..., ex. 0002h, 0006h... 8. WPR = Write protection register. To protect code, bit 15 of WPR must be `0'. To protect block N (N=0,1,...), bit N of WPR must be `0'. Bit that are already at `0' in protection register must also be `0' in WPR, else a writing error will occurs (it is not possible to write a `1' in a bit already programmed at `0'). 9. MEM = any address inside the Flash memory space. Absolute addressing mode must be used (MOV MEM, Rn), and instruction must be executed from Flash memory space. 40/239 Generally, command sequences cannot be written to Flash by instructions fetched from the Flash itself. Thus, the Flash commands must be written by instructions, executed from internal RAM or external memory. Command cycles on the CPU interface need not to be consecutively received (pauses allowed). The CPU interface delivers dummy read data for not used cycles within command sequences. All addresses of command cycles shall be defined only with Register-indirect addressing mode in the according move instructions. Direct addressing is not allowed for command sequences. Address segment or data page pointer are taken into account for the command address value. Doc ID 8673 Rev. 3 ST10F280 5.3.6 Internal Flash memory Reset processing and initial State The Flash module distinguishes two kinds of CPU reset types The lengthening of CPU reset: 5.4 Is not reported to external devices by bidirectional pin Is not enabled in case of external start of CPU after reset. Flash memory configuration The default memory configuration of the ST10F280 Memory is determined by the state of the EA pin at reset. This value is stored in the Internal ROM Enable bit (named ROMEN) of the SYSCON register. When ROMEN = 0, the internal Flash is disabled and external ROM is used for startup control. Flash memory can later be enabled by setting the ROMEN bit of SYSCON to 1. The code performing this setting must not run from a segment of the external ROM to be replaced by a segment of the Flash memory, otherwise unexpected behaviour may occur. For example, if external ROM code is located in the first 32K Bytes of segment 0, the first 32K Bytes of the Flash must then be enabled in segment 1. This is done by setting the ROMS1 bit of SYSCON to 0 before or simultaneously with setting of ROMEN bit. This must be done in the externally supplied program before the execution of the EINIT instruction. If program execution starts from external memory, but access to the Flash memory mapped in segment 0 is later required, then the code that performs the setting of ROMEN bit must be executed either in the segment 0 but above address 00'8000h, or from the internal RAM. Bit ROMS1 only affects the mapping of the first 32K Bytes of the Flash memory. All other parts of the Flash memory (addresses 01'8000h 08'FFFFh) remain unaffected. The SGTDIS Segmentation Disable / Enable must also be set to 0 to allow the use of the full 512K Bytes of on-chip memory in addition to the external boot memory. The correct procedure on changing the segmentation registers must also be observed to prevent an unwanted trap condition: Instructions that configure the internal memory must only be executed from external memory or from the internal RAM. An Absolute Inter-Segment Jump (JMPS) instruction must be executed after Flash enabling, to the next instruction, even if this next instruction is located in the consecutive address. Whenever the internal Memory is disabled, enabled or remapped, the DPPs must be explicitly (re)loaded to enable correct data accesses to the internal memory and/or external memory. 5.5 Application examples 5.5.1 Handling of Flash addresses All command, Block, Data and register addresses to the Flash have to be located within the active Flash memory space. The active space is that address range to which the physical Flash addresses are mapped as defined by the user. When using data page pointer (DPP) Doc ID 8673 Rev. 3 41/239 Internal Flash memory ST10F280 for block addresses make sure that address bit A15 and A14 of the block address are reflected in both LSBs of the selected DPPS. Note: For Command Instructions, address bit A14, A15, A16, A17 and A18 are don't care. This simplify a lot the application software, because it minimize the use of DPP registers when using Command in the Command Interface. Direct addressing is not allowed for Command sequence operations to the Flash. Only Register-indirect addressing can be used for command, block or write-data accesses. 5.5.2 Basic Flash access control When accessing the Flash all command write addresses have to be located within the active Flash memory space. The active Flash memory space is that logical address range which is covered by the Flash after mapping. When using data page pointer (DPP) for addressing the Flash, make sure that address bit A15 and A14 of the command addresses are reflected in both LSBs of the selected data page pointer (A15 DPPx.1 and A14 DPPx.0). In case of the command write addresses, address bit A14, A15 and above are "don't care". Thus, command writes can be performed by only using one DPP register. This allows to have a simpler and more compact application software. Another advantageous possibility is to use the extended segment instruction for addressing. Note: The direct addressing mode is not allowed for write access to the Flash address/command register. Be aware that the C compiler may use this kind of addressing. For write accesses to Flash module always the indirect addressing mode has to be selected. The following basic instruction sequences show examples for different addressing possibilities. Principle example of address generation for Flash commands and registers: When using data page pointer (DPP0 is this example) MOV DPP0,#08h ;adjust data page pointers according to the ;addresses: DPP0 is used in this example, thus ;ADDRESS must have A14 and A15 bit set to `0'. MOV Rwm,#ADDRESS ;ADDRESS could be a dedicated command sequence ;address 2AA8h, 1554h ... ) or the Flash write ;address MOV Rwn,#DATA ;DATA could be a dedicated command sequence data ;(xxA0h,xx80h ... ) or data to be programmed MOV [Rwm],Rwn ;indirect addressing When using the extended segment instruction: MOV Rwm,#ADDRESS ;ADDRESS could be a dedicated command sequence ;address (2AA8h, 1554h ... ) or the Flash write ;address 42/239 MOV Rwo,#DATA ;DATA could be a dedicated command sequence data ;(xxA0h,xx80h ... ) or data to be programmed MOV Rwn,#SEGMENT ;the value of SEGMENT represents the segment ;number and could be 0, 1, 2, 3 or 4 (depending ;on sector mapping) for 256KByte Flash. Doc ID 8673 Rev. 3 ST10F280 Internal Flash memory EXTS Rwn,#LENGTH ;the value of Rwn determines the 8-bit segment ;valid for the corresponding data access for any ;long or indirect address in the following(s) ;instruction(s). LENGTH defines the number of ;the effected instruction(s) and has to be a value ;between 1...4 MOV [Rwm],Rwo ;indirect addressing with segment number from ;EXTS 5.5.3 Programming examples Most of the microcontroller programs are written in the C language where the data page pointers are automatically set by the compiler. But because the C compiler may use the not allowed direct addressing mode for Flash write addresses, it is necessary to program the organizational Flash accesses (command sequences) with assembler in-line routines which use indirect addressing. Example 1: Performing the command Read/Reset We assume that in the initialization phase the lowest 32K Bytes of Flash memory (sector 0) have been mapped to segment 1. According to the usual way of ST10 data addressing with data page pointers, address bit A15 and A14 of a 16-bit command write address select the data page pointer (DPP) which contains the upper 10-bit for building the 24-bit physical data address. Address bit A13...A0 represent the address offset. As the bit A14...A18 are "don't care" when written a Flash command in the Command Interface (CI), we can choose the most convenient DPPx register for address handling. The following examples are making usage of DPP0. We just have to make sure, that DPP0 points to active Flash memory space. To be independent of mapping of sector 0 we choose for all DPPs which are used for Flash address handling, to point to segment 2. For this reason we load DPP0 with value 08h (00 0000 l000b). MOV R5, #01554h ;load auxilary register R5 with command address ;(used in command cycle 1) MOV R6, #02AA8h ;load auxilary register R6 with command address ;(used in command cycle 2) SCXT DPPO, #08h ;push data page pointer 0 and load it to point to ;segment 2 MOV R7, #0A8h ;load register R7 with 1st CI enable command MOV [R5], R7 ;command cycle 1 MOV R7, #054h ;load register R7 with 2cd CI enable command MOV [R6], R7 ;command cycle 2 MOV R7, #0F0h ;load register R7 with Read/Reset command MOV [R5], R7 ;command cycle 3. Address is don't care POP DPP0 ;restore DPP0 value In the example above the 16-bit registers R5 and R6 are used as auxiliary registers for indirect addressing. Doc ID 8673 Rev. 3 43/239 Internal Flash memory ST10F280 Example 2: Performing a Program Word command We assume that in the initialization phase the lowest 32K Bytes of Flash memory (sector 0) have been mapped to segment 1.The data to be written is loaded in register R13, the address to be programmed is loaded in register R11/R12 (segment number in R11, segment offset in R12). MOV R5, #01554h ;load auxilary register R5 with command address ;(used in command cycle 1) MOV R6, #02AA8h ;load auxilary register R6 with command address ;(used in command cycle 2) SXCT DPPO, #08h ;push data page pointer 0 and load it to point to ;segment 2 MOV R7, #0A8h ;load register R7 with 1st CI enable command MOV [R5], R7 ;command cycle 1 MOV R7, #054h ;load register R7 with 2cd CI enable command MOV [R6], R7 ;command cycle 2 MOV R7, #0A0h ;load register R7 with Program Word command MOV [R5], R7 ;command cycle 3 POP DPP0 ;restore DPP0: following addressing to the Flash ;will use EXTended instructions ;R11 contains the segment to be programmed ;R12 contains the segment offset address to be ;programmed ;R13 contains the data to be programmed EXTS R11, #1 MOV [R12], R13 ;use EXTended addressing for next MOV instruction ;command cycle 4: the EPC starts execution of ;Programming Command Data_Polling: EXTS R11, #1 ;use EXTended addressing for next MOV instruction MOV R7, [R12] ;read Flash Status register (FSB) in R7 MOV R6, R7 ;save it in R6 register ;Check if FSB.7 = Data.7 (i.e. R7.7 = R13.7) XOR R7, R13 JNB R7.7, Prog_OK ;Check if FSB.5 = 1 (Programming Error) JNB R6.5, Data_Polling ;Programming Error: verify is Flash programmed ;data is OK EXTS R11, #1 MOV R7, [R12] ;use EXTended addressing for next MOV instruction ;read Flash Status register (FSB) in R7 ;Check if FSB.7 = Data.7 XOR R7, R13 JNB R7.7, Prog_OK ;Programming failed: Flash remains in Write ;Operation. ;To go back to normal Read operations, a Read/Reset 44/239 Doc ID 8673 Rev. 3 ST10F280 Internal Flash memory ;command ;must be performed Prog_Error: MOV R7, #0F0h ;load register R7 with Read/Reset command EXTS R11, #1 ;use EXTended addressing for next MOV instruction MOV [R12], R7 ;address is don't care for Read/Reset command ... ;here place specific Error handling code ... ... ;When programming operation finished succesfully, ;Flash is set back automatically to normal Read Mode Prog_OK: .... .... Example 3: Performing the Block Erase command We assume that in the initialization phase the lowest 32K Bytes of Flash memory (sector 0) have been mapped to segment 1.The registers R11/R12 contain an address related to the block to be erased (segment number in R11, segment offset in R12, for example R11 = 01h, R12= 4000h will erase the block 1 first 8K byte block). MOV R5, #01554h ;load auxilary register R5 with command address ;(used in command cycle 1) MOV R6, #02AA8h ;load auxilary register R6 with command address ;(used in command cycle 2) SXCT DPPO, #08h ;push data page pointer 0 and load it to point ;to ;segment 2 MOV R7, #0A8h ;load register R7 with 1st CI enable command MOV [R5], R7 ;command cycle 1 MOV R7, #054h ;load register R7 with 2cd CI enable command MOV [R6], R7 ;command cycle 2 MOV R7, #080h ;load register R7 with Block Erase command MOV [R5], R7 ;command cycle 3 MOV R7, #0A8h ;load register R7 with 1st CI enable command MOV [R5], R7 ;command cycle 4 MOV R7, #054h ;load register R7 with 2cd CI enable command MOV [R6], R7 ;command cycle 5 POP DPP0 ;restore DPP0: following addressing to the Flash ;will use EXTended instructions ;R11 contains the segment of the block to be erased ;R12 contains the segment offset address of the ;block to be erased MOV R7, #030h ;load register R7 with erase confirm code EXTS R11, #1 ;use EXTended addressing for next MOV instruction MOV [R12], R7 ;command cycle 6: the EPC starts execution of Doc ID 8673 Rev. 3 45/239 Internal Flash memory ST10F280 ;Erasing Command Erase_Polling: EXTS R11, #1 MOV R7, [R12] ;use EXTended addressing for next MOV instruction ;read Flash Status register (FSB) in R7 ;Check if FSB.7 = `1' (i.e. R7.7 = `1') JB R7.7, Erase_OK ;Check if FSB.5 = 1 (Erasing Error) JNB R7.5, Erase_Polling ;Programming failed: Flash remains in Write ;Operation. ;To go back to normal Read operations, a Read/Reset ;command ;must be performed Erase_Error: MOV R7, #0F0h ;load register R7 with Read/Reset command EXTS R11, #1 ;use EXTended addressing for next MOV instruction MOV [R12], R7 ;address is don't care for Read/Reset command ... ;here place specific Error handling code ... ... ;When erasing operation finished succesfully, ;Flash is set back automatically to normal Read Mode Erase_OK: .... .... 5.6 Bootstrap loader The built-in bootstrap loader (BSL) of the ST10F280 provides a mechanism to load the startup program through the serial interface after reset. In this case, no external memory or internal Flash memory is required for the initialization code starting at location 00'0000h (see Figure 5). The bootstrap loader moves code/data into the internal RAM, but can also transfer data via the serial interface into an external RAM using a second level loader routine. ROM Memory (internal or external) is not necessary, but it may be used to provide lookup tables or "corecode" like a set of general purpose subroutines for I/O operations, number crunching, system initialization, etc. The bootstrap loader can be used to load the complete application software into ROMless systems, to load temporary software into complete systems for testing or calibration, or to load a programming routine for Flash devices. The BSL mechanism can be used for standard system startup as well as for special occasions like system maintenance (firmer update) or end-of-line programming or testing. 46/239 Doc ID 8673 Rev. 3 ST10F280 5.6.1 Internal Flash memory Entering the bootstrap loader The ST10F280 enters BSL mode when pin P0L.4 is sampled low at the end of a hardware reset. In this case the built-in bootstrap loader is activated independent of the selected bus mode. The bootstrap loader code is stored in a special Boot-ROM. No part of the standard mask Memory or Flash Memory area is required for this. After entering BSL mode and the respective initialization the ST10F280 scans the RxD0 line to receive a zero Byte, one start Bit, eight `0' data Bits and one stop Bit. From the duration of this zero Byte it calculates the corresponding Baud rate factor with respect to the current CPU clock, initializes the serial interface ASC0 accordingly and switches pin TXD0 to output. Using this Baud rate, an identification Byte is returned to the host that provides the loaded data. This identification Byte identifies the device to be booted. Identification byte is D5h for the ST10F280. Figure 5. Bootstrap loader sequence 234). 0, 2X$ 48$ #30)0 )NTERNAL "OOT -EMORY "3, ROUTINE "YTE USER SOFTWARE "3, INITIALIZATION TIME :ERO "YTE START "IT EIGHT @ DATA "ITS STOP "IT SENT BY HOST )DENTIFICATION "YTE $H SENT BY 34& "YTES OF CODE DATA SENT BY HOST #AUTION 48$ IS ONLY DRIVEN A CERTAIN TIME AFTER RECEPTION OF THE ZERO "YTE )NTERNAL "OOT 2/- ("1($'5 Doc ID 8673 Rev. 3 47/239 Internal Flash memory ST10F280 When the ST10F280 has entered BSL mode, the following configuration is automatically set (values that deviate from the normal reset values, are marked): Watchdog Timer: Disabled Register SYSCON: 0E00h Context Pointer CP: FA00h Register STKUN: FA40h Stack Pointer SP: FA40h Register STKOV: FA0Ch 0<->C Register S0CON: 8011h Register BUSCON0: acc. to startup configuration P3.10 / TXD0: `1' Register S0BG: Acc. to `00' Byte DP3.10: `1' In this case, the watchdog timer is disabled, so the bootstrap loading sequence is not time limited. Pin TXD0 is configured as output, so the ST10F280 can return the identification Byte. Even if the internal Flash is enabled, no code can be executed out of it. The hardware that activates the BSL during reset may be a simple pull-down resistor on P0L.4 for systems that use this feature upon every hardware reset. A switchable solution (via jumper or an external signal) can be used for systems that only temporarily use the bootstrap loader (see Figure 6). After sending the identification Byte the ASC0 receiver is enabled and is ready to receive the initial 32 Bytes from the host. A half duplex connection is therefore sufficient to feed the BSL. 5.6.2 Memory configuration after reset The configuration (and the accessibility) of the ST10F280's memory areas after reset in Bootstrap-Loader mode differs from the standard case. Pin EA is not evaluated when BSL mode is selected, and accesses to the internal Flash area are partly redirected, while the ST10F280 is in BSL mode (see Figure 7). All code fetches are made from the special BootROM, while data accesses read from the internal user Flash. Data accesses will return undefined values on ROMless devices. The code in the Boot-ROM is not an invariant feature of the ST10F280. User software should not try to execute code from the internal Flash area while the BSL mode is still active, as these fetches will be redirected to the Boot-ROM. The Boot-ROM will also "move" to segment 1, when the internal Flash area is mapped to segment 1 (see Figure 7). 48/239 Doc ID 8673 Rev. 3 ST10F280 Internal Flash memory Figure 6. Hardware provisions to activate the BSL %XTERNAL 3IGNAL .ORMAL "OOT 0/, 0/, "3, 20/, K: 20/, K: #IRCUIT #IRCUIT ("1($'5 Figure 7. Memory configuration after reset Segment 16 MBytes Access to: 255 16 MBytes 255 external bus disabled 2 1 2 1 0 16 MBytes Access: depends on reset config EA, Port0 2 1 IRAM IRAM 0 Test Flash internal Flash Flash enabled User Test Flash internal Flash Flash enabled User 0 User Flash depends on reset config EA, Port0 Yes (P0L.4='0') Yes (P0L.4='0') No (P0L.4='1') High Low Access to application Code fetch from internal Flash area Test-Flash access Test-Flash access User Flash access Data fetch from internal Flash area User Flash access User Flash access User Flash access EA pin 5.6.3 Segment 255 external bus enabled IRAM BSL mode active Access to: Segment Loading the startup code After sending the identification Byte the BSL enters a loop to receive 32 Bytes via ASC0. These Byte are stored sequentially into locations 00'FA40h through 00'FA5Fh of the internal RAM. So up to 16 instructions may be placed into the RAM area. To execute the loaded code the BSL then jumps to location 00'FA40h, which is the first loaded instruction. The bootstrap loading sequence is now terminated, the ST10F280 remains in BSL mode, however. Most probably the initially loaded routine will load additional code or data, as an average application is likely to require substantially more than 16 instructions. This second receive loop may directly use the pre-initialized interface ASC0 to receive data and store it to arbitrary user-defined locations. This second level of loaded code may be the final application code. It may also be another, more sophisticated, loader routine that adds a transmission protocol to enhance the integrity Doc ID 8673 Rev. 3 49/239 Internal Flash memory ST10F280 of the loaded code or data. It may also contain a code sequence to change the system configuration and enable the bus interface to store the received data into external memory. This process may go through several iterations or may directly execute the final application. In all cases the ST10F280 will still run in BSL mode, that means with the watchdog timer disabled and limited access to the internal Flash area. All code fetches from the internal Flash area (00'0000h...00'7FFFh or 01'0000h...01'7FFFh, if mapped to segment 1) are redirected to the special Boot-ROM. Data fetches access will access the internal Boot-ROM of the ST10F280, if any is available, but will return undefined data on ROMless devices. 5.6.4 Exiting bootstrap loader mode In order to execute a program in normal mode, the BSL mode must be terminated first. The ST10F280 exits BSL mode upon a software reset (ignores the level on P0L.4) or a hardware reset (P0L.4 must be high). After a reset the ST10F280 will start executing from location 00'0000h of the internal Flash or the external memory, as programmed via pin EA. 5.6.5 Choosing the baud rate for the BSL The calculation of the serial Baud rate for ASC0 from the length of the first zero Byte that is received, allows the operation of the bootstrap loader of the ST10F280 with a wide range of Baud rates. However, the upper and lower limits have to be kept, in order to insure proper data transfer. f CPU B ST10F280 = ----------------------------------------------32 x ( S0BRL + 1 ) The ST10F280 uses timer T6 to measure the length of the initial zero Byte. The quantization uncertainty of this measurement implies the first deviation from the real Baud rate, the next deviation is implied by the computation of the S0BRL reload value from the timer contents. The formula below shows the association: T6 - 36 S0BRL = -------------------72 9 , T6 = --4 f CPU x ----------------B Host For a correct data transfer from the host to the ST10F280 the maximum deviation between the internal initialized Baud rate for ASC0 and the real Baud rate of the host should be below 2.5%. The deviation (FB, in percent) between host Baud rate and ST10F280 Baud rate can be calculated via the formula below: F B B -B Contr Host- x 100 % = ------------------------------------------, B Contr F B 2.5 % Note: Function (FB) does not consider the tolerances of oscillators and other devices supporting the serial communication. This Baud rate deviation is a nonlinear function depending on the CPU clock and the Baud rate of the host. The maxima of the function (FB) increase with the host Baud rate due to the 50/239 Doc ID 8673 Rev. 3 ST10F280 Internal Flash memory smaller Baud rate pre-scaler factors and the implied higher quantization error (see Figure 8). The minimum Baud rate (BLow in the Figure 8) is determined by the maximum count capacity of timer T6, when measuring the zero Byte, and it depends on the CPU clock. Using the maximum T6 count 216 in the formula the minimum Baud rate can be calculated. The lowest standard Baud rate in this case would be 1200 Baud. Baud rates below BLow would cause T6 to overflow. In this case ASC0 cannot be initialized properly. The maximum Baud rate (BHigh in the Figure 8) is the highest Baud rate where the deviation still does not exceed the limit, so all Baud rates between BLow and BHigh are below the deviation limit. The maximum standard Baud rate that fulfills this requirement is 19200 Baud. Higher Baud rates, however, may be used as long as the actual deviation does not exceed the limit. A certain Baud rate (marked 'I' in Figure 8) may violate the deviation limit, while an even higher Baud rate (marked 'II' in Figure 8) stays very well below it. This depends on the host interface. Figure 8. Baud rate deviation between host and ST10F280 ) &" ",OW "(IGH "(/34 )) ("1($'5 Doc ID 8673 Rev. 3 51/239 Central Processing Unit (CPU) 6 ST10F280 Central Processing Unit (CPU) The CPU includes a 4-stage instruction pipeline, a 16-bit arithmetic and logic unit (ALU) and dedicated SFRs. Additional hardware has been added for a separate multiply and divide unit, a bit-mask generator and a barrel shifter. Most of the ST10F280's instructions can be executed in one instruction cycle which requires 50ns at 40MHz CPU clock. For example, shift and rotate instructions are processed in one instruction cycle independent of the number of bits to be shifted. Multiple-cycle instructions have been optimized: branches are carried out in 2 cycles, 16 x 16 bit multiplication in 5 cycles and a 32/16 bit division in 10 cycles. The jump cache reduces the execution time of repeatedly performed jumps in a loop, from 2 cycles to 1 cycle. The CPU uses a bank of 16 word registers to run the current context. This bank of General Purpose Registers (GPR) is physically stored within the on-chip Internal RAM (IRAM) area. A Context Pointer (CP) register determines the base address of the active register bank to be accessed by the CPU. The number of register banks is only restricted by the available Internal RAM space. For easy parameter passing, a register bank may overlap others. A system stack of up to 1024 bytes is provided as a storage for temporary data. The system stack is allocated in the on-chip RAM area, and it is accessed by the CPU via the stack pointer (SP) register. Two separate SFRs, STKOV and STKUN, are implicitly compared against the stack pointer value upon each stack access for the detection of a stack overflow or underflow. Figure 9. CPU block diagram (MAC unit not included) #05 30 34+/6 34+5. + "YTE &LASH MEMORY %XEC 5NIT )NSTR 0TR 3TAGE 0IPELINE 037 393#/. "53#/. "53#/. "53#/. "53#/. "53#/. $ATA 0G 0TRS -$( -$, -UL$IV (7 "IT -ASK 'EN !,5 + "YTE )NTERNAL 2!- 2 "ANK N 'ENERAL 0URPOSE 2EGISTERS "IT "ARREL 3HIFT #0 !$$23%, !$$23%, !$$23%, !$$23%, #ODE 3EG 0TR 2 "ANK I "ANK ("1($'5 52/239 Doc ID 8673 Rev. 3 ST10F280 Central Processing Unit (CPU) The system configuration register SYSCON This bit-addressable register provides general system configuration and control functions. The reset value for register SYSCON depends on the state of the PORT0 pins during reset. 12 11 10 9 8 7 6 5 4 3 2 STKSZ SGTDIS ROMEN BYTDIS CLKEN WRCFG CSCFG PWDCFG OWDDIS BDRSTEN XPEN VISIBLE XPER-SHARE 15 ROMS1 SYSCON 14 13 R/W R/W R/W R/W R/W(1) R/W R/W R/W R/W R/W R/W R/W R/W(1) R/W(1) 1 0 1. These bit are set directly or indirectly according to PORT0 and EA pin configuration during reset sequence. Register SYSCON cannot be changed after execution of the EINIT instruction. Address: 0xFF12h / 89h SFR Reset: 0x0XX0h Type: R/W 1. XPEN XBUS Peripheral Enable Bit 0: Accesses to the on-chip X-Peripherals and their functions are disabled 1: The on-chip X-Peripherals are enabled and can be accessed. BDRSTEN Bidirectional Reset Enable 0: RSTIN pin is an input pin only. SW Reset or WDT Reset have no effect on this pin 1: RSTIN pin is a bidirectional pin. This pin is pulled low during 1024 TCL during reset sequence. OWDDIS Oscillator Watchdog Disable Control 0: Oscillator Watchdog (OWD) is enabled. If PLL is bypassed, the OWD monitors XTAL1 activity. If there is no activity on XTAL1 for at least 1 s, the CPU clock is switched automatically to PLL's base frequency (2 to 10MHz). 1: OWD is disabled. If the PLL is bypassed, the CPU clock is always driven by XTAL1 signal. The PLL is turned off to reduce power supply current. PWDCFG Power Down Mode Configuration Control 0: Power Down Mode can only be entered during PWRDN instruction execution if NMI pin is low, otherwise the instruction has no effect. To exit Power Down Mode, an external reset must occurs by asserting the RSTIN pin. 1: Power Down Mode can only be entered during PWRDN instruction execution if all enabled fast external interrupt EXxIN pins are in their inactive level. Exiting this mode can be done by asserting one enabled EXxIN pin. CSCFG Chip Select Configuration Control 0: Latched Chip Select lines: CSx change 1 TCL after rising edge of ALE 1: Unlatched Chip Slect lines: CSx change with rising edge of ALE Doc ID 8673 Rev. 3 53/239 Central Processing Unit (CPU) 6.1 ST10F280 Multiplier-accumulator Unit (MAC) The MAC co-processor is a specialized co-processor added to the ST10 CPU Core in order to improve the performances of the ST10 Family in signal processing algorithms. Signal processing needs at least three specialized units operating in parallel to achieve maximum performance: A Multiply-Accumulate Unit, An Address Generation Unit, able to feed the MAC Unit with 2 operands per cycle, A Repeat Unit, to execute series of multiply-accumulate instructions. The existing ST10 CPU has been modified to include new addressing capabilities which enable the CPU to supply the new co-processor with up to 2 operands per instruction cycle. This new co-processor (so-called MAC) contains a fast multiply-accumulate unit and a repeat unit. The co-processor instructions extend the ST10 CPU instruction set with multiply, multiplyaccumulate, 32-bit signed arithmetic operations. A new transfer instruction CoMOV has also been added to take benefit of the new addressing capabilities. 6.1.1 Features Enhanced addressing capabilities New addressing modes including a double indirect addressing mode with pointer postmodification. Parallel Data Move: this mechanism allows one operand move during MultiplyAccumulate instructions without penalty. New transfer instructions CoSTORE (for fast access to the MAC SFRs) and CoMOV (for fast memory to memory table transfer). Multiply-accumulate unit One-cycle execution for all MAC operations. 16 x 16 signed/unsigned parallel multiplier. 40-bit signed arithmetic unit with automatic saturation mode. 40-bit accumulator. 8-bit left/right shifter. Full instruction set with multiply and multiply-accumulate, 32-bit signed arithmetic and compare instructions. Program control 54/239 Repeat Unit: allows some MAC co-processor instructions to be repeated up to 8192 times. Repeated instructions may be interrupted. MAC interrupt (Class B Trap) on MAC condition flags. Doc ID 8673 Rev. 3 ST10F280 Central Processing Unit (CPU) Figure 10. MAC unit architecture 2SHUDQG '02 0OINTERS 2SHUDQG )$8 0OINTER )$8 0OINTER 12 '02 /FFSET 2EGISTER 12 '02 /FFSET 2EGISTER 18 )$8 /FFSET 2EGISTER 18 )$8 /FFSET 2EGISTER X SIGNEDUNSIGNED -ULTIPLIER #ONCATENATION -UX 3IGN %XTEND 05: 3CALER H 5HSHDW8QLW ,QWHUUXSW &RQWUROOHU H H -UX -UX 0&: ! " BIT 3IGNED !RITHMETIC 5NIT 67&38 06: &LAGS -!% &RQWURO8QLW 0$+ 0$/ BIT ,EFT2IGHT 3HIFTER 4IBSFEXJUITUBOEBSE"-6 ("1($'5 6.2 Instruction set summary The Table 4 lists the instructions of the ST10F280. The various addressing modes, instruction operation, parameters for conditional execution of instructions, opcodes and a detailed description of each instruction can be found in the "ST10 Family Programming Manual". Table 4. Instruction set summary Mnemonic Description Bytes ADD(B) Add word (byte) operands 2/4 ADDC(B) Add word (byte) operands with Carry 2/4 SUB(B) Subtract word (byte) operands 2/4 SUBC(B) Subtract word (byte) operands with Carry 2/4 MUL(U) (Un)Signed multiply direct GPR by direct GPR (16-16-bit) 2 DIV(U) (Un)Signed divide register MDL by direct GPR (16-/16-bit) 2 DIVL(U) (Un)Signed long divide reg. MD by direct GPR (32-/16-bit) 2 CPL(B) Complement direct word (byte) GPR 2 NEG(B) Negate direct word (byte) GPR 2 Doc ID 8673 Rev. 3 55/239 Central Processing Unit (CPU) Table 4. ST10F280 Instruction set summary (continued) Mnemonic 56/239 Description Bytes AND(B) Bitwise AND, (word/byte operands) 2/4 OR(B) Bitwise OR, (word/byte operands) 2/4 XOR(B) Bitwise XOR, (word/byte operands) 2/4 BCLR Clear direct bit 2 BSET Set direct bit 2 BMOV(N) Move (negated) direct bit to direct bit 4 BAND, BOR, BXOR AND/OR/XOR direct bit with direct bit 4 BCMP Compare direct bit to direct bit 4 BFLDH/L Bitwise modify masked high/low byte of bit-addressable direct word memory with immediate data 4 CMP(B) Compare word (byte) operands 2/4 CMPD1/2 Compare word data to GPR and decrement GPR by 1/2 2/4 CMPI1/2 Compare word data to GPR and increment GPR by 1/2 2/4 PRIOR Determine number of shift cycles to normalize direct word GPR and store result in direct word GPR 2 SHL / SHR Shift left/right direct word GPR 2 ROL / ROR Rotate left/right direct word GPR 2 ASHR Arithmetic (sign bit) shift right direct word GPR 2 MOV(B) Move word (byte) data 2/4 MOVBS Move byte operand to word operand with sign extension 2/4 MOVBZ Move byte operand to word operand with zero extension 2/4 JMPA, JMPI, JMPR Jump absolute/indirect/relative if condition is met 4 JMPS Jump absolute to a code segment 4 J(N)B Jump relative if direct bit is (not) set 4 JBC Jump relative and clear bit if direct bit is set 4 JNBS Jump relative and set bit if direct bit is not set 4 CALLA, CALLI, CALLR Call absolute/indirect/relative subroutine if condition is met 4 CALLS Call absolute subroutine in any code segment 4 PCALL Push direct word register onto system stack and call absolute subroutine 4 TRAP Call interrupt service routine via immediate trap number 2 PUSH, POP Push/pop direct word register onto/from system stack 2 SCXT Push direct word register onto system stack and update register with word operand 4 RET Return from intra-segment subroutine 2 Doc ID 8673 Rev. 3 ST10F280 Central Processing Unit (CPU) Table 4. Instruction set summary (continued) Mnemonic 6.3 Description Bytes RETS Return from inter-segment subroutine 2 RETP Return from intra-segment subroutine and pop direct word register from system stack 2 RETI Return from interrupt service subroutine 2 SRST Software Reset 4 IDLE Enter Idle Mode 4 PWRDN Enter Power Down Mode (supposes NMI-pin being low) 4 SRVWDT Service Watchdog Timer 4 DISWDT Disable Watchdog Timer 4 EINIT Signify End-of-Initialization on RSTOUT-pin 4 ATOMIC Begin ATOMIC sequence 2 EXTR Begin EXTended Register sequence 2 EXTP(R) Begin EXTended Page (and Register) sequence 2/4 EXTS(R) Begin EXTended Segment (and Register) sequence 2/4 NOP Null operation 2 MAC coprocessor specific instructions The following table gives an overview of the MAC instruction set. All the mnemonics are listed with the addressing modes that can be used with each instruction. For each combination of mnemonic and addressing mode this table indicates if it is repeatable or not New addressing capabilities enable the CPU to supply the MAC with up to 2 operands per instruction cycle. MAC instructions: multiply, multiply-accumulate, 32-bit signed arithmetic operations and the CoMOV transfer instruction have been added to the standard instruction set. Full details are provided in the `ST10 Family Programming Manual'. Double indirect addressing requires two pointers. Any GPR can be used for one pointer, the other pointer is provided by one of two specific SFRs IDX0 and IDX1. Two pairs of offset registers QR0/QR1 and QX0/QX1 are associated with each pointer (GPR or IDXi). The GPR pointer allows access to the entire memory space, but IDXi are limited to the internal Dual-Port RAM, except for the CoMOV instruction. Doc ID 8673 Rev. 3 57/239 Central Processing Unit (CPU) Table 5. ST10F280 MAC coprocessor specific instructions Mnemonic Addressing modes Repeatability CoMUL CoMULu CoMULus CoMULsu CoMULCoMULuCoMULus- Rwn, Rwm [IDXi], [Rwm] Rwn, [Rwm] No No No Rwn, Rwm [IDXi], [Rwm] Rwn, [Rwm] No Yes Yes Rwn, Rwm [IDXi], [Rwn] Rwn, [RWm] No No No [Rwm] Yes [IDXi] Yes [IDXi], [Rwm] Yes CoMULsuCoMUL, rnd CoMULu, rnd CoMULus, rnd CoMULsu, rnd CoMAC CoMACu CoMACus CoMACsu CoMACCoMACuCoMACusCoMACsuCoMAC, rnd CoMACu, rnd CoMACus, rnd CoMACsu, rnd CoMACR CoMACRu CoMACRus CoMACRsu CoMACR, rnd CoMACRu, rnd CoMACRus, rnd CoMACRsu, rnd CoNOP 58/239 Doc ID 8673 Rev. 3 ST10F280 Central Processing Unit (CPU) Table 5. MAC coprocessor specific instructions (continued) Mnemonic Addressing modes Repeatability CoNEG CoNEG, rnd - No Rwn, CoReg No [Rwn], Coreg Yes [IDXi], [Rwm] Yes [IDXi], [Rwm] Yes Rwn, Rwm [IDXi], [Rwm] Rwn, [Rwm] No Yes Yes CoRND CoSTORE CoMOV CoMACM CoMACMu CoMACMus CoMACMsu CoMACMCoMACMuCoMACMusCoMACMsuCoMACM, rnd CoMACMu, rnd CoMACMus, rnd CoMACMsu, rnd CoMACMR CoMACMRu CoMACMRus CoMACMRsu CoMACMR, rnd CoMACMRu, rnd CoMACMRus, rnd CoMACMRsu, rnd CoADD CoADD2 CoSUB CoSUB2 CoSUBR CoSUB2R CoMAX CoMIN Doc ID 8673 Rev. 3 59/239 Central Processing Unit (CPU) Table 5. ST10F280 MAC coprocessor specific instructions (continued) Mnemonic Addressing modes Repeatability CoLOAD CoLOADCoLOAD2 CoLOAD2- Rwn, Rwm [IDXi], [Rwm] Rwn, [Rwm] No Rwm #data4 [Rwm] Yes No Yes Rwn, Rwm [IDXi], [Rwm] Rwn, [Rwm] No No No No No CoCMP CoSHL CoSHR CoASHR CoASHR, rnd CoABS The Table 6 shows the various combinations of pointer post-modification for each of these 2 new addressing modes. In this document the symbols "[Rwn]" and "[IDXi]" refer to these addressing modes. Table 6. Pointer post-modification combinations for IDXi and Rwn Symbol "[IDXi]" stands for "[Rwn]" stands for Table 7. Address pointer operation [IDXi] (IDXi) (IDXi) (no-op) [IDXi+] (IDXi) (IDXi) +2 (i=0,1) [IDXi] (IDXi) (IDXi)2 (i=0,1) [IDXi + QXj] (IDXi) (IDXi) + (QXj) (i, j =0,1) [IDXi QXj] (IDXi) (IDXi) (QXj) (i, j =0,1) [Rwn] (Rwn) (Rwn) (no-op) [Rwn+] (Rwn) (Rwn) +2 (n=0-15) [Rwn-] (Rwn) (Rwn)2 (k=0-15) [Rwn+QRj] (Rwn) (Rwn) + (QRj) (n=0-15;j =0,1) [Rwn QRj] (Rwn) (Rwn) (QRj) (n=0-15; j =0,1) MAC registers referenced as `CoReg` Registers 60/239 Mnemonic Description Address in Opcode MSW MAC-Unit Status Word 00000b MAH MAC-Unit Accumulator High 00001b MAS "limited" MAH /signed 00010b Doc ID 8673 Rev. 3 ST10F280 Central Processing Unit (CPU) Table 7. MAC registers referenced as `CoReg` (continued) Registers Description Address in Opcode MAL MAC-Unit Accumulator Low 00100b MCW MAC-Unit Control Word 00101b MRW MAC-Unit Repeat Word 00110b Doc ID 8673 Rev. 3 61/239 External bus controller 7 ST10F280 External bus controller All of the external memory accesses are performed by the on-chip external bus controller. The EBC can be programmed to single chip mode when no external memory is required, or to one of four different external memory access modes: 16-/18-/20-/24-bit addresses 16-bit data, demultiplexed 16-/18-/20-/24-bit addresses 16-bit data, multiplexed 16-/18-/20-/24-bit addresses 8-bit data, multiplexed 16-/18-/20-/24-bit addresses 8-bit data, demultiplexed In demultiplexed bus modes addresses are output on PORT1 and data is input/output on PORT0 or P0L, respectively. In the multiplexed bus modes both addresses and data use PORT0 for input/output. Timing characteristics of the external bus interface (memory cycle time, memory tri-state time, length of ale and read write delay) are programmable giving the choice of a wide range of memories and external peripherals. Up to 4 independent address windows may be defined (using register pairs ADDRSELx / BUSCONx) to access different resources and bus characteristics. These address windows are arranged hierarchically where BUSCON4 overrides BUSCON3 and BUSCON2 overrides BUSCON1. All accesses to locations not covered by these 4 address windows are controlled by BUSCON0. Up to 5 external CS signals (4 windows plus default) can be generated in order to save external glue logic. Access to very slow memories is supported by a `Ready' function. A HOLD/HLDA protocol is available for bus arbitration which shares external resources with other bus masters. The bus arbitration is enabled by setting bit HLDEN in register PSW. After setting HLDEN once, pins P6.7...P6.5 (BREQ, HLDA, HOLD) are automatically controlled by the EBC. In master mode (default after reset) the HLDA pin is an output. By setting bit DP6.7 to'1' the slave mode is selected where pin HLDA is switched to input. This directly connects the slave controller to another master controller without glue logic. For applications which require less external memory space, the address space can be restricted to 1 MByte, 256 KByte or to 64 KByte. Port 4 outputs all 8 address lines if an address space of 16 MBytes is used, otherwise four, two or no address lines. Chip select timing can be made programmable. By default (after reset), the CSx lines change half a CPU clock cycle after the rising edge of ALE. With the CSCFG bit set in the SYSCON register the CSx lines change with the rising edge of ALE. The active level of the READY pin can be set by bit RDYPOL in the BUSCONx registers. When the READY function is enabled for a specific address window, each bus cycle within the window must be terminated with the active level defined by bit RDYPOL in the associated BUSCON register. 62/239 Doc ID 8673 Rev. 3 ST10F280 7.1 External bus controller Programmable chip select timing control The ST10F280 allows the user to adjust the position of the CSx lines changes. By default (after reset), the CSx lines are changing half a CPU clock cycle (12.5 ns at fCPU = 40MHz) after the rising edge of ALE. With the CSCFG bit set in the SYSCON register, the CSx lines are changing with the rising edge of ALE, thus the CSx lines are changing at the same time the address lines are changing. See Section 19.2: System configuration registers for detailed description of SYSCON register. Figure 11. Chip select delay 3EGMENT 0 .ORMAL $EMULTIPLEXED !,% ,ENGTHEN $EMULTIPLEXED "US #YCLE "US #YCLE !DDRESS 0 !,% .ORMAL #3X 5NLATCHED #3X $ATA $ATA "53 0 2$ $ATA "53 0 $ATA 72 2EAD7RITE 2EAD7RITE $ELAY $ELAY ("1($'5 7.2 READY programmable polarity The active level of the READY pin can be selected by software via the RDYPOL bit in the BUSCONx registers. When the READY function is enabled for a specific address window, Doc ID 8673 Rev. 3 63/239 External bus controller ST10F280 each bus cycle within this window must be terminated with the active level defined by this RDYPOL bit in the associated BUSCON register. 9 8 CSREN0 RDYPOL0 RDYEN0 - - R/W R/W R/W R/W Address: 0xFF0Ch / 86h SFR Reset: 0x0XX0h Type: R/W R/W R/W 5 4 BTYP RWDC0 10 MCTC R/W R/W R/W R/W 5 4 RWDC1 11 MTTC0 12 MTTC1 13 ALECTL0 14 BUSACT0 15 CSWEN0 BUSCON0 7 6 3 2 1 0 1 0 15 14 13 12 11 10 9 8 CSWEN1 CSREN1 RDYPOL1 RDYEN1 - BUSACT1 ALECTL1 BUSCON1 - R/W R/W R/W R/W 7 BTYP R/W R/W Address: 0xFF14h / 8Ah SFR Reset: 0x0000h Type: R/W 6 R/W 3 2 MCTC R/W R/W R/W 13 12 11 10 9 8 CSREN2 RDYPOL2 RDYEN2 - BUSACT2 ALECTL2 - R/W R/W R/W R/W R/W R/W Address: 0xFF16h / 8Bh SFR Reset: 0x0000h Type: R/W 64/239 Doc ID 8673 Rev. 3 5 4 BTYP RWDC2 14 MTTC2 15 CSWEN2 BUSCON2 7 6 3 2 1 MCTC R/W R/W R/W R/W 0 ST10F280 External bus controller 9 8 CSREN3 RDYPOL3 RDYEN3 - - R/W R/W R/W R/W Address: 0xFF18h / 8Ch SFR Reset: 0x0000h Type: R/W R/W R/W 5 4 BTYP RWDC3 10 MCTC R/W R/W R/W R/W 5 4 BTYP RWDC4 11 MTTC3 12 MTTC4 13 ALECTL3 14 BUSACT3 15 CSWEN3 BUSCON3 7 6 3 2 MCTC R/W R/W R/W R/W 1 0 1 0 15 14 13 12 11 10 9 8 CSWEN4 CSREN4 RDYPOL4 RDYEN4 - BUSACT4 ALECTL4 BUSCON4 - R/W R/W R/W R/W R/W R/W Address: 0xFF1Ah / 8Dh SFR Reset: 0x0000h Type: R/W 7 6 3 2 RDYPOLx Ready Active Level Control 0: The active level on the READY pin is low, bus cycle terminates with a `0' on READY pin, 1: The active level on the READY pin is high, bus cycle terminates with a `1' on READY pin. Doc ID 8673 Rev. 3 65/239 Interrupt system 8 ST10F280 Interrupt system The interrupt response time for internal program execution is from 125ns to 300ns at 40MHz CPU clock. The ST10F280 architecture supports several mechanisms for fast and flexible response to service requests that can be generated from various sources (internal or external) to the microcontroller. Any of these interrupt requests can be serviced by the Interrupt Controller or by the Peripheral Event Controller (PEC). In contrast to a standard interrupt service where the current program execution is suspended and a branch to the interrupt vector table is performed, just one cycle is `stolen' from the current CPU activity to perform a PEC service. A PEC service implies a single Byte or Word data transfer between any two memory locations with an additional increment of either the PEC source or destination pointer. An individual PEC transfer counter is implicitly decremented for each PEC service except when performing in the continuous transfer mode. When this counter reaches zero, a standard interrupt is performed to the corresponding source related vector location. PEC services are very well suited to perform the transmission or the reception of blocks of data. The ST10F280 has 8 PEC channels, each of them offers such fast interrupt-driven data transfer capabilities. An interrupt control register which contains an interrupt request flag, an interrupt enable flag and an interrupt priority bitfield is dedicated to each existing interrupt source. Thanks to its related register, each source can be programmed to one of sixteen interrupt priority levels. Once starting to be processed by the CPU, an interrupt service can only be interrupted by a higher prioritized service request. For the standard interrupt processing, each of the possible interrupt sources has a dedicated vector location. Software interrupts are supported by means of the `TRAP' instruction in combination with an individual trap (interrupt) number. 66/239 Doc ID 8673 Rev. 3 ST10F280 8.1 Interrupt system External interrupts Fast external interrupt inputs are provided to service external interrupts with high precision requirements. These fast interrupt inputs feature programmable edge detection (rising edge, falling edge or both edges). Fast external interrupts may also have interrupt sources selected from other peripherals; for example the CANx controller receive signal (CANx_RxD) can be used to interrupt the system. This new function is controlled using the `External Interrupt Source Selection' register EXISEL. EXISEL 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0 EXI7SS EXI6SS EXI5SS EXI4SS EXI3SS EXI2SS EXI1SS EXI0SS R/W R/W R/W R/W R/W R/W R/W R/W Address: 0xF1DAh / EDh ESFR Reset: 0x0000h Type: R/W EXIxSS External Interrupt x Source Selection (x=7...0) `00': Input from associated Port 2 pin. `01': Input from "alternate source". `10': Input from Port 2 pin ORed with "alternate source". `11': Input from Port 2 pin ANDed with "alternate source". EXIxSS Port 2 pin Alternate Source 0 P2.8 CAN1_RxD 1 P2.9 CAN2_RxD 2...7 P2.10...15 Not used (zero) Doc ID 8673 Rev. 3 67/239 Interrupt system ST10F280 EXICON E 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0 EXI7ES EXI6ES EXI5ES EXI4ES EXI3ES EXI2ES EXI1ES EXI0ES R/W R/W R/W R/W R/W R/W R/W R/W Address: 0xF1C0h / E0h ESFR Reset: 0x0000h Type: R/W EXIxES(x=7...0) External Interrupt x Edge Selection Field (x=7...0) 00: Fast external interrupts disabled: standard mode EXxIN pin not taken in account for entering/exiting Power Down mode. 01: Interrupt on positive edge (rising) Enter Power Down mode if EXiIN = `0', exit if EXxIN = `1' (referred as `high' active level) 10: Interrupt on negative edge (falling) Enter Power Down mode if EXiIN = `1', exit if EXxIN = `0' (referred as `low' active level) 11: Interrupt on any edge (rising or falling) Always enter Power Down mode, exit if EXxIN level changed. 8.2 Interrupt registers and vectors location list Table 8 shows all the available ST10F280 interrupt sources and the corresponding hardware-related interrupt flags, vectors, vector locations and trap (interrupt) numbers: Table 8. Interrupt sources Source of Interrupt or PEC service request 68/239 Request flag Enable flag Interrupt vector Vector location Trap number CAPCOM Register 0 CC0IR CC0IE CC0INT 00'0040h 10h CAPCOM Register 1 CC1IR CC1IE CC1INT 00'0044h 11h CAPCOM Register 2 CC2IR CC2IE CC2INT 00'0048h 12h CAPCOM Register 3 CC3IR CC3IE CC3INT 00'004Ch 13h CAPCOM Register 4 CC4IR CC4IE CC4INT 00'0050h 14h CAPCOM Register 5 CC5IR CC5IE CC5INT 00'0054h 15h CAPCOM Register 6 CC6IR CC6IE CC6INT 00'0058h 16h CAPCOM Register 7 CC7IR CC7IE CC7INT 00'005Ch 17h CAPCOM Register 8 CC8IR CC8IE CC8INT 00'0060h 18h CAPCOM Register 9 CC9IR CC9IE CC9INT 00'0064h 19h CAPCOM Register 10 CC10IR CC10IE CC10INT 00'0068h 1Ah CAPCOM Register 11 CC11IR CC11IE CC11INT 00'006Ch 1Bh CAPCOM Register 12 CC12IR CC12IE CC12INT 00'0070h 1Ch Doc ID 8673 Rev. 3 ST10F280 Interrupt system Table 8. Interrupt sources (continued) Source of Interrupt or PEC service request Request flag Enable flag Interrupt vector Vector location Trap number CAPCOM Register 13 CC13IR CC13IE CC13INT 00'0074h 1Dh CAPCOM Register 14 CC14IR CC14IE CC14INT 00'0078h 1Eh CAPCOM Register 15 CC15IR CC15IE CC15INT 00'007Ch 1Fh CAPCOM Register 16 CC16IR CC16IE CC16INT 00'00C0h 30h CAPCOM Register 17 CC17IR CC17IE CC17INT 00'00C4h 31h CAPCOM Register 18 CC18IR CC18IE CC18INT 00'00C8h 32h CAPCOM Register 19 CC19IR CC19IE CC19INT 00'00CCh 33h CAPCOM Register 20 CC20IR CC20IE CC20INT 00'00D0h 34h CAPCOM Register 21 CC21IR CC21IE CC21INT 00'00D4h 35h CAPCOM Register 22 CC22IR CC22IE CC22INT 00'00D8h 36h CAPCOM Register 23 CC23IR CC23IE CC23INT 00'00DCh 37h CAPCOM Register 24 CC24IR CC24IE CC24INT 00'00E0h 38h CAPCOM Register 25 CC25IR CC25IE CC25INT 00'00E4h 39h CAPCOM Register 26 CC26IR CC26IE CC26INT 00'00E8h 3Ah CAPCOM Register 27 CC27IR CC27IE CC27INT 00'00ECh 3Bh CAPCOM Register 28 CC28IR CC28IE CC28INT 00'00F0h 3Ch CAPCOM Register 29 CC29IR CC29IE CC29INT 00'0110h 44h CAPCOM Register 30 CC30IR CC30IE CC30INT 00'0114h 45h CAPCOM Register 31 CC31IR CC31IE CC31INT 00'0118h 46h CAPCOM Timer 0 T0IR T0IE T0INT 00'0080h 20h CAPCOM Timer 1 T1IR T1IE T1INT 00'0084h 21h CAPCOM Timer 7 T7IR T7IE T7INT 00'00F4h 3Dh CAPCOM Timer 8 T8IR T8IE T8INT 00'00F8h 3Eh GPT1 Timer 2 T2IR T2IE T2INT 00'0088h 22h GPT1 Timer 3 T3IR T3IE T3INT 00'008Ch 23h GPT1 Timer 4 T4IR T4IE T4INT 00'0090h 24h GPT2 Timer 5 T5IR T5IE T5INT 00'0094h 25h GPT2 Timer 6 T6IR T6IE T6INT 00'0098h 26h GPT2 CAPREL Register CRIR CRIE CRINT 00'009Ch 27h A/D Conversion Complete ADCIR ADCIE ADCINT 00'00A0h 28h A/D Overrun Error ADEIR ADEIE ADEINT 00'00A4h 29h ASC0 Transmit S0TIR S0TIE S0TINT 00'00A8h 2Ah S0TBIR S0TBIE S0TBINT 00'011Ch 47h ASC0 Transmit Buffer Doc ID 8673 Rev. 3 69/239 Interrupt system Table 8. ST10F280 Interrupt sources (continued) Source of Interrupt or PEC service request Request flag Enable flag Interrupt vector Vector location Trap number CAPCOM Register 13 CC13IR CC13IE CC13INT 00'0074h 1Dh CAPCOM Register 14 CC14IR CC14IE CC14INT 00'0078h 1Eh CAPCOM Register 15 CC15IR CC15IE CC15INT 00'007Ch 1Fh CAPCOM Register 16 CC16IR CC16IE CC16INT 00'00C0h 30h CAPCOM Register 17 CC17IR CC17IE CC17INT 00'00C4h 31h CAPCOM Register 18 CC18IR CC18IE CC18INT 00'00C8h 32h CAPCOM Register 19 CC19IR CC19IE CC19INT 00'00CCh 33h CAPCOM Register 20 CC20IR CC20IE CC20INT 00'00D0h 34h CAPCOM Register 21 CC21IR CC21IE CC21INT 00'00D4h 35h CAPCOM Register 22 CC22IR CC22IE CC22INT 00'00D8h 36h CAPCOM Register 23 CC23IR CC23IE CC23INT 00'00DCh 37h CAPCOM Register 24 CC24IR CC24IE CC24INT 00'00E0h 38h CAPCOM Register 25 CC25IR CC25IE CC25INT 00'00E4h 39h CAPCOM Register 26 CC26IR CC26IE CC26INT 00'00E8h 3Ah CAPCOM Register 27 CC27IR CC27IE CC27INT 00'00ECh 3Bh CAPCOM Register 28 CC28IR CC28IE CC28INT 00'00F0h 3Ch CAPCOM Register 29 CC29IR CC29IE CC29INT 00'0110h 44h CAPCOM Register 30 CC30IR CC30IE CC30INT 00'0114h 45h CAPCOM Register 31 CC31IR CC31IE CC31INT 00'0118h 46h CAPCOM Timer 0 T0IR T0IE T0INT 00'0080h 20h CAPCOM Timer 1 T1IR T1IE T1INT 00'0084h 21h CAPCOM Timer 7 T7IR T7IE T7INT 00'00F4h 3Dh CAPCOM Timer 8 T8IR T8IE T8INT 00'00F8h 3Eh GPT1 Timer 2 T2IR T2IE T2INT 00'0088h 22h GPT1 Timer 3 T3IR T3IE T3INT 00'008Ch 23h GPT1 Timer 4 T4IR T4IE T4INT 00'0090h 24h GPT2 Timer 5 T5IR T5IE T5INT 00'0094h 25h GPT2 Timer 6 T6IR T6IE T6INT 00'0098h 26h GPT2 CAPREL Register CRIR CRIE CRINT 00'009Ch 27h A/D Conversion Complete ADCIR ADCIE ADCINT 00'00A0h 28h A/D Overrun Error ADEIR ADEIE ADEINT 00'00A4h 29h ASC0 Transmit S0TIR S0TIE S0TINT 00'00A8h 2Ah S0TBIR S0TBIE S0TBINT 00'011Ch 47h ASC0 Transmit Buffer 70/239 Doc ID 8673 Rev. 3 ST10F280 Interrupt system Table 8. Interrupt sources (continued) Source of Interrupt or PEC service request Request flag Enable flag Interrupt vector Vector location Trap number CAPCOM Register 13 CC13IR CC13IE CC13INT 00'0074h 1Dh CAPCOM Register 14 CC14IR CC14IE CC14INT 00'0078h 1Eh CAPCOM Register 15 CC15IR CC15IE CC15INT 00'007Ch 1Fh CAPCOM Register 16 CC16IR CC16IE CC16INT 00'00C0h 30h CAPCOM Register 17 CC17IR CC17IE CC17INT 00'00C4h 31h CAPCOM Register 18 CC18IR CC18IE CC18INT 00'00C8h 32h CAPCOM Register 19 CC19IR CC19IE CC19INT 00'00CCh 33h CAPCOM Register 20 CC20IR CC20IE CC20INT 00'00D0h 34h CAPCOM Register 21 CC21IR CC21IE CC21INT 00'00D4h 35h CAPCOM Register 22 CC22IR CC22IE CC22INT 00'00D8h 36h CAPCOM Register 23 CC23IR CC23IE CC23INT 00'00DCh 37h CAPCOM Register 24 CC24IR CC24IE CC24INT 00'00E0h 38h CAPCOM Register 25 CC25IR CC25IE CC25INT 00'00E4h 39h CAPCOM Register 26 CC26IR CC26IE CC26INT 00'00E8h 3Ah CAPCOM Register 27 CC27IR CC27IE CC27INT 00'00ECh 3Bh CAPCOM Register 28 CC28IR CC28IE CC28INT 00'00F0h 3Ch CAPCOM Register 29 CC29IR CC29IE CC29INT 00'0110h 44h CAPCOM Register 30 CC30IR CC30IE CC30INT 00'0114h 45h CAPCOM Register 31 CC31IR CC31IE CC31INT 00'0118h 46h CAPCOM Timer 0 T0IR T0IE T0INT 00'0080h 20h CAPCOM Timer 1 T1IR T1IE T1INT 00'0084h 21h CAPCOM Timer 7 T7IR T7IE T7INT 00'00F4h 3Dh CAPCOM Timer 8 T8IR T8IE T8INT 00'00F8h 3Eh GPT1 Timer 2 T2IR T2IE T2INT 00'0088h 22h GPT1 Timer 3 T3IR T3IE T3INT 00'008Ch 23h GPT1 Timer 4 T4IR T4IE T4INT 00'0090h 24h GPT2 Timer 5 T5IR T5IE T5INT 00'0094h 25h GPT2 Timer 6 T6IR T6IE T6INT 00'0098h 26h GPT2 CAPREL Register CRIR CRIE CRINT 00'009Ch 27h A/D Conversion Complete ADCIR ADCIE ADCINT 00'00A0h 28h A/D Overrun Error ADEIR ADEIE ADEINT 00'00A4h 29h ASC0 Transmit S0TIR S0TIE S0TINT 00'00A8h 2Ah S0TBIR S0TBIE S0TBINT 00'011Ch 47h ASC0 Transmit Buffer Doc ID 8673 Rev. 3 71/239 Interrupt system Table 8. ST10F280 Interrupt sources (continued) Source of Interrupt or PEC service request Request flag Enable flag Interrupt vector Vector location Trap number ASC0 Receive S0RIR S0RIE S0RINT 00'00ACh 2Bh ASC0 Error S0EIR S0EIE S0EINT 00'00B0h 2Ch SSC Transmit SCTIR SCTIE SCTINT 00'00B4h 2Dh SSC Receive SCRIR SCRIE SCRINT 00'00B8h 2Eh SSC Error SCEIR SCEIE SCEINT 00'00BCh 2Fh PWM Channel 0...3 PWMIR PWMIE PWMINT 00'00FCh 3Fh CAN1 Interface XP0IR XP0IE XP0INT 00'0100h 40h CAN2 Interface XP1IR XP1IE XP1INT 00'0104h 41h XPWM XP2IR XP2IE XP2INT 00'0108h 42h PLL Unlock/OWD XP3IR XP3IE XP3INT 00'010Ch 43h Hardware traps are exceptions or error conditions that arise during run-time. They cause immediate non-maskable system reaction similar to a standard interrupt service (branching to a dedicated vector table location). The occurrence of a hardware trap is additionally signified by an individual bit in the trap flag register (TFR). Except when another higher prioritized trap service is in progress, a hardware trap will interrupt any other program execution. Hardware trap services cannot not be interrupted by standard interrupt or by PEC interrupts. 8.3 Interrupt Control Registers All interrupt control registers are identically organized. The lower 8 bit of an interrupt control register contain the complete interrupt status information of the associated source, which is required during one round of prioritization, the upper 8 bit of the respective register are reserved. All interrupt control registers are bit-addressable and all bit can be read or written via software. This allows each interrupt source to be programmed or modified with just one instruction. When accessing interrupt control registers through instructions which operate on Word data types, their upper 8 bit (15...8) will return zeros, when read, and will discard written data. The layout of the Interrupt Control registers shown below applies to each xxIC register, where xx stands for the mnemonic for the respective source. 72/239 Doc ID 8673 Rev. 3 ST10F280 Interrupt system xxIC 15 14 13 12 11 10 9 8 7 6 - - - - - - - - xxIR xxIE ILVL GLVL R/W R/W R/W R/W Address: 0xyyyyh / zzh SFR area Reset: 0x--00h Type: R/W 5 4 3 2 1 0 GLVL Group Level Defines the internal order for simultaneous requests of the same priority. 11: Highest group priority 00: Lowest group priority ILVL Interrupt Priority Level Defines the priority level for the arbitration of requests. Fh: Highest priority level 0h: Lowest priority level xxIE Interrupt Enable Control Bit (individually enables/disables a specific source) 0: Interrupt Request is disabled 1: Interrupt Request is enabled xxIR Interrupt Request Flag 0: No request pending 1: This source has raised an interrupt request 8.4 Exception and error traps list Table 9 shows all of the possible exceptions or error conditions that can arise during runtime: Doc ID 8673 Rev. 3 73/239 Interrupt system Table 9. ST10F280 Exceptions or error conditions that can arise during run-time Exception condition Trap flag Trap vector Vector location Trap number Reset Functions Trap priority(1) MAXIMUM Hardware Reset RESET 00'0000h 00h III Software Reset RESET 00'0000h 00h III Watchdog Timer Overflow RESET 00'0000h 00h III NMI NMITRAP 00'0008h 02h II Stack Overflow STKOF STOTRAP 00'0010h 04h II Stack Underflow STKUF STUTRAP 00'0018h 06h II UNDOPC BTRAP 00'0028h 0Ah I Protected Instruction Fault PRTFLT BTRAP 00'0028h 0Ah I Illegal Word Operand Access ILLOPA BTRAP 00'0028h 0Ah I Illegal Instruction Access ILLINA BTRAP 00'0028h 0Ah I Illegal External Bus Access ILLBUS BTRAP 00'0028h 0Ah I MACTRP BTRAP 00'0028h 0Ah I Class A Hardware Traps Non-Maskable Interrupt Class B Hardware Traps Undefined Opcode MAC Trap MINIMUM Reserved Software Traps TRAP Instruction [2Ch -3Ch] [0Bh - 0Fh] Any [00'0000h- 00'01FCh] in steps of 4h Any [00h - 7Fh] Current CPU Priority 1. All the class B traps have the same trap number (and vector) and the same lower priority compare to the class A traps and to the resets. Each class A traps has a dedicated trap number (and vector). They are prioritized in the second priority level. The resets have the highest priority level and the same trap number. The PSW.ILVL CPU priority is forced to the highest level (15) when these exceptions are serviced 74/239 Doc ID 8673 Rev. 3 ST10F280 9 Capture/Compare (CAPCOM) units Capture/Compare (CAPCOM) units The ST10F280 has two 16 channels CAPCOM units as described in Figure 12. These support generation and control of timing sequences on up to 32 channels with a maximum resolution of 200ns at 40MHz CPU clock. The CAPCOM units are typically used to handle high speed I/O tasks such as pulse and waveform generation, pulse width modulation (PMW), Digital to Analog (D/A) conversion, software timing, or time recording relative to external events. Four 16-bit timers (T0/T1, T7/T8) with reload registers provide two independent time bases for the capture/compare register array (See Figure 13 and Figure 14). The input clock for the timers is programmable to several prescaled values of the internal system clock, or may be derived from an overflow/underflow of timer T6 in module GPT2. This provides a wide range of variation for the timer period and resolution and allows precise adjustments to application specific requirements. In addition, external count inputs for CAPCOM timers T0 and T7 allow event scheduling for the capture/compare registers relative to external events. Each of the two capture/compare register arrays contain 16 dual purpose capture/compare registers, each of which may be individually allocated to either CAPCOM timer T0 or T1 (T7 or T8, respectively), and programmed for capture or compare functions. Each of the 32 registers has one associated port pin which serves as an input pin for triggering the capture function, or as an output pin to indicate the occurrence of a compare event. Figure 12 shows the basic structure of the two CAPCOM units. Figure 12. CAPCOM unit block diagram 2ELOAD 2EGISTER 4X2%, #05 #LOCK X N N 4X). 0IN )NTERRUPT 2EQUEST 4X )NPUT #ONTROL #!0#/- 4IMER 4X -ODE #ONTROL #APTURE OR #OMPARE 3IXTEEN BIT #APTURE#OMPARE 2EGISTERS 4Y )NPUT #ONTROL #!0#/- 4IMER 4Y '04 4IMER 4 /VER 5NDERFLOW 0IN #APTURE INPUTS #OMPARE OUTPUTS #APTURE #OMPARE )NTERRUPT 2EQUESTS 0IN #05 #LOCK N N )NTERRUPT 2EQUEST '04 4IMER 4 /VER 5NDERFLOW 2ELOAD 2EGISTER 4Y2%, Y ("1($'5 Doc ID 8673 Rev. 3 75/239 Capture/Compare (CAPCOM) units Note: ST10F280 The CAPCOM2 unit provides 16 capture inputs, but only 12 compare outputs. CC24I to CC27I are inputs only. Figure 13. Block diagram of CAPCOM timers T0 and T7 2ELOAD 2EGISTER 4X2%, 4XL )NPUT #ONTROL #05 #LOCK 8 '04 4IMER 4 /VER 5NDERFLOW -58 #!0#/- 4IMER 4X 4X)2 )NTERRUPT 2EQUEST %DGE 3ELECT 4X2 4XL 4X- 4X). 0IN X 4XL ("1($'5 Figure 14. Block diagram of CAPCOM timers T1 and T 2ELOAD 2EGISTER 4X2%, 4XL #05 #LOCK 8 '04 4IMER 4 /VER 5NDERFLOW -58 #!0#/- 4IMER 4X 4X- 4X2 4X)2 )NTERRUPT 2EQUEST X ("1($'5 Note: When an external input signal is connected to the input lines of both T0 and T7, these timers count the input signal synchronously. Thus the two timers can be regarded as one timer whose contents can be compared with 32 capture registers. When a capture/compare register has been selected for capture mode, the current contents of the allocated timer will be latched (captured) into the capture/compare register in response to an external event at the port pin which is associated with this register. In addition, a specific interrupt request for this capture/compare register is generated. Either a positive, a negative, or both a positive and a negative external signal transition at the pin can be selected as the triggering event. The contents of all registers which have been selected for one of the five compare modes are continuously compared with the contents of the allocated timers. When a match occurs between the timer value and the value in a capture /compare register, specific actions will be taken based on the selected compare mode (see Table ). 76/239 Doc ID 8673 Rev. 3 ST10F280 Capture/Compare (CAPCOM) units The input frequencies fTx, for the timer input selector Tx, are determined as a function of the CPU clocks. The timer input frequencies, resolution and periods which result from the selected pre-scaler option in TxI when using a 40MHz CPU clock are listed in the Table 11. The numbers for the timer periods are based on a reload value of 0000h. Note that some numbers may be rounded to 3 significant figures. Table 10. Compare modes Compare modes Table 11. Function Mode 0 Interrupt-only compare mode; several compare interrupts per timer period are possible Mode 1 Pin toggles on each compare match; several compare events per timer period are possible Mode 2 Interrupt-only compare mode; only one compare interrupt per timer period is generated Mode 3 Pin set `1' on match; pin reset `0' on compare time overflow; only one compare event per timer period is generated Double Register Mode Two registers operate on one pin; pin toggles on each compare match; several compare events per timer period are possible. CAPCOM timer input frequencies, resolution and periods Timer input selection TxI fCPU = 40MHz Pre-scaler for fCPU 000b 001b 010b 011b 100b 101b 110b 111b 8 16 32 64 128 256 512 1024 Input Frequency 5MHz 2.5MHz 1.25MHz 625kHz Resolution 200ns 400ns 0.8s 1.6s 3.2s 6.4s 12.8s 25.6s Period 13.1ms 26.2ms 52.4ms 104.8ms 209.7ms 419.4ms 838.9ms 1.678s Doc ID 8673 Rev. 3 312.5kHz 156.25kHz 78.125kHz 39.1kHz 77/239 General purpose timer unit 10 ST10F280 General purpose timer unit The GPT unit is a flexible multifunctional timer/counter structure which is used for time related tasks such as event timing and counting, pulse width and duty cycle measurements, pulse generation, or pulse multiplication. The GPT unit contains five 16-bit timers organized into two separate modules GPT1 and GPT2. Each timer in each module may operate independently in several different modes, or may be concatenated with another timer of the same module. 10.1 GPT1 Each of the three timers T2, T3, T4 of the GPT1 module can be configured individually for one of four basic modes of operation: timer, gated timer, counter mode and incremental interface mode. In timer mode, the input clock for a timer is derived from the CPU clock, divided by a programmable prescaler. In counter mode, the timer is clocked in reference to external events. Pulse width or duty cycle measurement is supported in gated timer mode where the operation of a timer is controlled by the `gate' level on an external input pin. For these purposes, each timer has one associated port pin (TxIN) which serves as gate or clock input. Table 12 lists the timer input frequencies, resolution and periods for each pre-scaler option at 40MHz CPU clock. This also applies to the Gated Timer Mode of T3 and to the auxiliary timers T2 and T4 in Timer and Gated Timer Mode. The count direction (up/down) for each timer is programmable by software or may be altered dynamically by an external signal on a port pin (TxEUD). In Incremental Interface Mode, the GPT1 timers (T2, T3, T4) can be directly connected to the incremental position sensor signals A and B by their respective inputs TxIN and TxEUD. Direction and count signals are internally derived from these two input signals so that the contents of the respective timer Tx corresponds to the sensor position. The third position sensor signal TOP0 can be connected to an interrupt input. Timer T3 has output toggle latches (TxOTL) which changes state on each timer over flow / underflow. The state of this latch may be output on port pins (TxOUT) for time out monitoring of external hardware components, or may be used internally to clock timers T2 and T4 for high resolution of long duration measurements. In addition to their basic operating modes, timers T2 and T4 may be configured as reload or capture registers for timer T3. When used as capture or reload registers, timers T2 and T4 are stopped. The contents of timer T3 is captured into T2 or T4 in response to a signal at their associated input pins (TxIN). Timer T3 is reloaded with the contents of T2 or T4 triggered either by an external signal or by a selectable state transition of its toggle latch T3OTL. When both T2 and T4 are configured to alternately reload T3 on opposite state transitions of T3OTL with the low and high times of a PWM signal, this signal can be constantly generated without software intervention. 78/239 Doc ID 8673 Rev. 3 ST10F280 Table 12. General purpose timer unit GPT1 timer input frequencies, resolution and periods Timer input selection T2I / T3I / T4I fCPU = 40MHz 000b 001b 010b 011b 100b 101b 110b 111b 8 16 32 64 128 256 512 1024 Input Freq 5MHz 2.5MHz 1.25MHz 625kHz 312.5kHz Resolution 200ns 400ns 0.8s 1.6s 3.2s 6.4s 12.8s 25.6s Period maximum 13.1ms 26.2ms 52.4ms 104.8ms 209.7ms 419.4ms 838.9ms 1.678s Pre-scaler factor 156.25kHz 78.125kHz 39.1kHz Figure 15. Block diagram of GPT1 4%5$ #05 #LOCK 5$ N N 4). 4 -ODE CONTROL )NTERRUPT 2EQUEST '04 4IMER 4 #LEAR #APTURE )NTERRUPT 2EQUEST #!0). '04 #!02%, 2ELOAD 4). #05 #LOCK N N 4 -ODE CONTROL )NTERRUPT 2EQUEST 4OGGLE && '04 4IMER 4 5$ 4%5$ 44, 4/54 TO #!0#/4IMERS ("1($'5 10.2 GPT2 The GPT2 module provides precise event control and time measurement. It includes two timers (T5, T6) and a capture/reload register (CAPREL). Both timers can be clocked with an input clock which is derived from the CPU clock via a programmable prescaler or with external signals. The count direction (up/down) for each timer is programmable by software or may additionally be altered dynamically by an external signal on a port pin (TxEUD). Concatenation of the timers is supported via the output toggle latch (T6OTL) of timer T6 which changes its state on each timer overflow/underflow. The state of this latch may be used to clock timer T5, or it may be output on a port pin (T6OUT). The overflow / underflow of timer T6 can additionally be used to clock the CAPCOM timers T0 or T1, and to cause a reload from the CAPREL register. The CAPREL register may capture the contents of timer T5 based on an external signal transition on the corresponding port pin (CAPIN), and timer T5 may optionally be cleared after the capture procedure. This allows absolute time differences to be measured or pulse multiplication to be performed without software overhead. Doc ID 8673 Rev. 3 79/239 General purpose timer unit ST10F280 The capture trigger (timer T5 to CAPREL) may also be generated upon transitions of GPT1 timer T3 inputs T3IN and/or T3EUD. This is advantageous when T3 operates in Incremental Interface Mode. Table 13 lists the timer input frequencies, resolution and periods for each pre-scaler option at 40MHz CPU clock. This also applies to the Gated Timer Mode of T6 and to the auxiliary timer T5 in Timer and Gated Timer Mode. Table 13. GPT2 timer input frequencies, resolution and period Timer input selection T5I / T6I fCPU = 40MHz 000b 001b 010b 011b 100b 101b 110b 111b 4 8 16 32 64 128 256 512 Input Freq 10MHz 5MHz 2.5MHz 1.25MHz 625kHz Resolution 100ns 200ns 400ns 0.8s 1.6s 3.2s 6.4s 12.8s Period maximum 6.55ms 13.1ms 26.2ms 52.4ms 104.8ms 209.7ms 419.4ms 838.9ms Pre-scaler factor 312.5kHz 156.25kHz 78.125kHz Figure 16. Block diagram of GPT2 4%5$ #05 #LOCK 5$ N N 4). 4 -ODE CONTROL )NTERRUPT 2EQUEST '04 4IMER 4 #LEAR #APTURE )NTERRUPT 2EQUEST #!0). '04 #!02%, 2ELOAD 4). #05 #LOCK N N 4 -ODE CONTROL )NTERRUPT 2EQUEST 4OGGLE && '04 4IMER 4 5$ 4%5$ 44, 4/54 TO #!0#/4IMERS ("1($'5 80/239 Doc ID 8673 Rev. 3 ST10F280 PWM module 11 PWM module 11.1 Standard PWM module The pulse width modulation module can generate up to four PWM output signals using edge-aligned or centre-aligned PWM. In addition, the PWM module can generate PWM burst signals and single shot outputs. The Table 14 shows the PWM frequencies for different resolutions. The level of the output signals is selectable and the PWM module can generate interrupt requests. Figure 17. Block diagram of PWM module 00X 0ERIOD 2EGISTER #OMPARATOR #LOCK )NPUT #ONTROL #LOCK -ATCH 04X BIT 5P$OWN #OUNTER 2UN #OMPARATOR 5P$OWN #LEAR #ONTROL -ATCH 0/54X /UTPUT #ONTROL %NABLE 3HADOW 2EGISTER 5SER READABLE WRITEABLE REGISTER 7RITE #ONTROL 07X 0ULSE 7IDTH 2EGISTER ("1($'5 Table 14. 11.2 PWM unit frequencies and resolution at 40MHz CPU clock Mode 0 Resolution 8-bit 10-bit 12-bit 14-bit 16-bit CPU Clock/1 25ns 156.25kHz 39.06kHz 9.77kHz 2.44Hz 610.35Hz CPU Clock/64 1.6s 2.44Hz 610.35Hz 152.58Hz 38.15Hz 9.54Hz Mode 1 Resolution 8-bit 10-bit 12-bit 14-bit 16-bit CPU Clock/1 25ns 78.12kHz 19.53kHz 4.88kHz 1.22kHz 305.17Hz CPU Clock/64 1.6s 1.22kHz 305.17Hz 76.29Hz 19.07Hz 4.77Hz New PWM module: XPWM The new Pulse Width Modulation (XPWM) Module of the ST10F280 is mapped on the XBUS interface (Address range 00'EC00h-00'ECFFh) and allows the generation of up to 4 independent PWM signals.The XPWM is enabled by setting XPEN bit 2 of the SYSCON register and bit 4 of the new XPERCON register. The frequency range of these XPWM signals for a 40MHz CPU clock is from 9.6Hz up to 20MHz for edge aligned signals. For center aligned signals the frequency range is 4.8Hz up to 10MHz (see detailed description). The minimum values depend on the width (16 bit) and the resolution (CLK/1 or CLK/64) of Doc ID 8673 Rev. 3 81/239 PWM module ST10F280 the XPWM timers. The maximum values assume that the XPWM output signal changes with every cycle of the respective timer. In a real application the maximum XPWM frequency will depend on the required resolution of the XPWM output signal (see Figure 18). The Pulse Width Modulation Module consists of 4 independent PWM channels. Each channel has a 16-bit up/down counter XPTx, a 16-bit period register XPPx with a shadow latch, a 16-bit pulse width register XPWx with a shadow latch, two comparators, and the necessary control logic. The operation of all four channels is controlled by two common control registers, XPWMCON0 and XPWMCON1, and the interrupt control and status is handled by one interrupt control register XP2IC, which is also common for all channels (see Figure 11.2.1). Figure 18. SFRs and port pins associated with the XPWM module $ATA 2EGISTERS #OUNTER 2EGISTERS 800 9 9 9 9 9 9 9 9 9 9 9 9 9 9 9 9 807 9 9 9 9 9 9 9 9 9999999 9 800 9 9 9 9 9 9 9 9 9999999 9 807 9 9 9 9 9 9 9 9 9999999 9 800 9 9 9 9 9 9 9 9 9999999 9 807 9 9 9 9 9 9 9 9 9999999 9 800 9 9 9 9 9 9 9 9 9999999 9 807 9 9 9 9 9 9 9 9 9999999 9 /UTPUT ON DEDICATED PINS 807- 807- 807- 807- #ONTROL 2EGISTERS AND )NTERRUPT #ONTROL 804 9 9 9 9 9 9 9 9 9 9 9 9 9 9 9 9 804 9 9 9 9 9 9 9999999 9 9 9 804 9 9 9 9 9 9 9999999 9 9 9 804 9 9 9 9 9 9 9999999 9 9 9 807-#/. 9 9 9 9 9 9 9 9 9 9 9 9 9 9 9 9 807-#/. 9 9 9 9999999 80/,!2 80)# % 800X 807X 804X 807-#/.X 80/,!2X 80)# 807- 0ERIOD 2EGISTER X 807- 0ULSE 7)DTH 2EGISTER X 807- #OUNTER 2EGISTER X 807- #ONTROL 2EGISTER 807- /UTPUT 0OLARITY #ONTROL 2EGISTER 807- )NTERRUPT #ONTROL 2EGISTER 999 9 9999999 % ("1($'5 800X 0ERIOD 2EGISTER #LOCK #LOCK )NPUT #ONTROL 2UN -ATCH 5P$OWN #LEAR #ONTROL 804X BIT 5P$OWN #OUNTER #OMPARATOR -ATCH /UTPUT #ONTROL 80/54X %NABLE 3HADOW 2EGISTER 5SER READABLE WRITEABLE REGISTER 7RITE #ONTROL 807X 0ULSE 7IDTH 2EGISTER ("1($'5 82/239 Doc ID 8673 Rev. 3 9 4HIS BIT HAS A 807- FUNCTION 4HIS BIT HAS NO 807( FUNCTION OR IS NOT IMPLEMNENTED 4HIS REGISTER BELONGS TO %3&2 AREA 9 Figure 19. XPWM channel block diagram #OMPARATOR 9 ST10F280 11.2.1 PWM module Operating modes The XPWM module provides four different operating modes: Note: Mode 0 Standard PWM generation (edge aligned PWM) available on all four channels Mode 1 Symmetrical PWM generation (center aligned PWM) available on all four channels Burst mode combines channels 0 and 1 Single shot mode available on channels 2 and 3 The output signals of the XPWM module are XORed with the outputs of the respective bits of XPOLAR register. After reset these bits are cleared, so the PWM signals are directly driven to the output pins. By setting the respective bits of XPOLAR register to `1' the PWM signal may be inverted (XORed with `1') before being driven to the output pin. The descriptions below refer to the standard case after reset, i.e. direct driving. Mode 0: standard PWM generation (edge aligned PWM) Mode 0 is selected by clearing the respective bit XPMx in register XPWMCON1 to `0'. In this mode the timer XPTx of the respective XPWM channel is always counting up until it reaches the value in the associated period shadow register. Upon the next count pulse the timer is reset to 0000h and continues counting up with subsequent count pulses. The XPWM output signal is switched to high level when the timer contents are equal to or greater than the contents of the pulse width shadow register. The signal is switched back to low level when the respective timer is reset to 0000h, i.e. below the pulse width shadow register. The period of the resulting PWM signal is determined by the value of the respective XPPx shadow register plus 1, counted in units of the timer resolution. PWM_PeriodMode0 = [XPPx] + 1 The duty cycle of the XPWM output signal is controlled by the value in the respective pulse width shadow register. This mechanism allows the selection of duty cycles from 0% to 100% including the boundaries. For a value of 0000h the output will remain at a high level, representing a duty cycle of 100%. For a value higher than the value in the period register the output will remain at a low level, which corresponds to a duty cycle of 0%. The Figure 20 illustrates the operation and output waveforms of a XPWM channel in mode 0 for different values in the pulse width register. This mode is referred to as Edge Aligned PWM, because the value in the pulse width (shadow) register only effects the positive edge of the output signal. The negative edge is always fixed and related to the clearing of the timer. Doc ID 8673 Rev. 3 83/239 PWM module ST10F280 Figure 20. Operation and output waveform in mode 0 800X 0ERIOD 804X #OUNT 6ALUE 807X 0ULSE 7IDTH $UTY #YCLE 807X 807X 807X 807X 807X 807X ,32 ,ATCH 3HADOW 2EGISTERS )NTERRUPT 2EQUEST ,32 ,32 ("1($'5 Mode 1: symmetrical PWM generation (center aligned PWM) Mode 1 is selected by setting the respective bit XPMx in register XPWMCON1 to `1'. In this mode the timer XPTx of the respective XPWM channel is counting up until it reaches the value in the associated period shadow register. Upon the next count pulse the count direction is reversed and the timer starts counting down now with subsequent count pulses until it reaches the value 0000H. Upon the next count pulse the count direction is reversed again and the count cycle is repeated with the following count pulses. The XPWM output signal is switched to a high level when the timer contents are equal to or greater than the contents of the pulse width shadow register while the timer is counting up. The signal is switched back to a low level when the respective timer has counted down to a value below the contents of the pulse width shadow register. So in mode 1 this PWM value controls both edges of the output signal. Note that in mode 1 the period of the PWM signal is twice the period of the timer: PWM_PeriodMode1 = 2 * ([XPPx] + 1) The figure below illustrates the operation and output waveforms of a XPWM channel in mode 1 for different values in the pulse width register. This mode is referred to as Center Aligned PWM, because the value in the pulse width (shadow) register effects both edges of the output signal symmetrically. 84/239 Doc ID 8673 Rev. 3 ST10F280 PWM module Figure 21. Operation and output waveform in mode 1 800X 0ERIOD 804X #OUNT 6ALUE 807X 0ULSE 7IDTH $UTY #YCLE 807X 807X 807X 807X 807X 807X ,32 ,ATCH 3HADOW 2EGISTERS )NTERRUPT 2EQUES #HANGE #OUNT $IRECTION ,32 ("1($'5 Burst mode Burst mode is selected by setting bit PB01 in register XPWMCON1 to `1'. This mode combines the signals from XPWM channels 0 and 1 onto the port pin of channel 0. The output of channel 0 is replaced with the logical AND of channels 0 and 1. The output of channel 1 can still be used at its associated output pin (if enabled). Each of the two channels can either operate in mode 0 or 1. Note: It is guaranteed by design, that no spurious spikes will occur at the output pin of channel 0 in this mode. The output of the AND gate will be transferred to the output pin synchronously to internal clocks. XORing of the PWM signal and the port output latch value is done after the ANDing of channel 0 and 1. Doc ID 8673 Rev. 3 85/239 PWM module ST10F280 Figure 22. Operation and output waveform in burst mode 800 0ERIOD 6ALUE 804 #OUNT 6ALUE #HANNEL 800 804 #HANNEL 2ESULTING /UTPUT 80/54 ("1($'5 Single shot mode Single shot mode is selected by setting the respective bit PSx in register XPWMCON1 to `1'. This mode is available for XPWM channels 2 and 3. In this mode the timer XPTx of the respective XPWM channel is started via software and is counting up until it reaches the value in the associated period shadow register. Upon the next count pulse the timer is cleared to 0000h and stopped via hardware, i.e. the respective PTRx bit is cleared. The XPWM output signal is switched to high level when the timer contents are equal to or greater than the contents of the pulse width shadow register. The signal is switched back to low level when the respective timer is cleared, i.e. is below the pulse width shadow register. Thus starting a XPWM timer in single shot mode produces one single pulse on the respective port pin, provided that the pulse width value is between 0000h and the period value. In order to generate a further pulse, the timer has to be started again via software by setting bit PTRx (see Figure 23). After starting the timer (i.e. PTRx = `1') the output pulse may be modified via software. Writing to timer XPTx changes the positive and/or negative edge of the output signal, depending on whether the pulse has already started (i.e. the output is high) or not (i.e. the output is still low). This (multiple) re-triggering is always possible while the timer is running, i.e. after the pulse has started and before the timer is stopped. Loading counter XPTx directly with the value in the respective XPPx shadow register will abort the current PWM pulse upon the next clock pulse (counter is cleared and stopped by hardware). By setting the period (XPPx), the timer start value (XPTx) and the pulse width value (XPWx) appropriately, the pulse width (tw) and the optional pulse delay (td) may be varied in a wide range. 86/239 Doc ID 8673 Rev. 3 ST10F280 PWM module Figure 23. Operation and output waveform in single shot mode 800X 0ERIOD 804X #OUNT 6ALUE 807X 0ULSE 7IDTH ,32 042X 2ESET BY (ARDWARE 04X STOPPED 3ET 042X BY 3OFTWARE 800X 0ERIOD ,32 3ET 042X BY 3OFTWARE FOR .EXT 0ULSE 804X #OUNT 6ALUE 807X 0ULSE 7IDTH T7 T$ T7 T$ 2ETRIGGER AFTER 0ULSE HAS STARTED 7RITE 07X VALUE TO 04X 4R IGGER BEFORE 0ULSE HAS STARTED 7RITE 07X VALUE TO 04X 3HORTENS $ELAY 4IME T$ ("1($'5 11.2.2 XPWM module registers The XPWM module is controlled via two sets of registers. The waveforms are selected by the channel specific registers XPTx (timer), XPPx (period) and XPWx (pulse width). Three common registers control the operating modes and the general functions (XPWMCON0 and XPWMCON1) of the PWM module as well as the interrupt behavior (XP2IC). Up/down counters XPTx Each counter XPTx of a PWM channel is clocked either directly by the CPU clock or by the CPU clock divided by 64. Bit PTIx in register XPWMCON0 selects the respective clock source. A XPWM counter counts up or down (controlled by hardware), while its respective run control bit PTRx is set. A timer is started (PTRx = '1') via software and is stopped (PTRx = '0') either via hardware or software, depending on its operating mode. Control bit PTRx enables or disables the clock input of counter XPTx rather than controlling the XPWM output signal. Note: For the register locations please refer to the Table 15. Table 16 summarizes the XPWM frequencies that result from various combinations of operating mode, counter resolution (input clock) and pulse width resolution. Period registers XPPx The 16-bit period register XPPx of a XPWM channel determines the period of a PWM cycle, i.e. the frequency of the PWM signal. This register is buffered with a shadow register. The shadow register is loaded from the respective XPPx register at the beginning of every new Doc ID 8673 Rev. 3 87/239 PWM module ST10F280 PWM cycle, or upon a write access to XPPx, while the timer is stopped. The CPU accesses the XPPx register while the hardware compares the contents of the shadow register with the contents of the associated counter XPTx. When a match is found between counter and XPPx shadow register, the counter is either reset to 0000h, or the count direction is switched from counting up to counting down, depending on the selected operating mode of that XPWM channel. For the register locations refer to the Table 15. Pulse width registers XPWx This 16-bit register holds the actual PWM pulse width value which corresponds to the duty cycle of the PWM signal. This register is buffered with a shadow register. The CPU accesses the XPWx register while the hardware compares the contents of the shadow register with the contents of the associated counter XPTx. The shadow register is loaded from the respective XPWx register at the beginning of every new PWM cycle, or upon a write access to XPWx, while the timer is stopped.When the counter value is greater than or equal to the shadow register value, the PWM signal is set, otherwise it is reset. The output of the comparators may be described by the boolean formula: PWM output signal = [XPTx] [XPWx shadow latch]. This type of comparison allows a flexible control of the PWM signal. For the register locations refer to the Table 15. Table 15. XPWM module channel specific register addresses Register Address Register Address XPW0 EC30h XPT0 EC10h XPW1 EC32h XPT1 EC12h XPW2 EC34h XPT2 EC14h XPW3 EC36h XPT3 EC16h XPP0 EC20h XPP1 EC22h XPP2 EC24h XPP3 EC26h These registers are not bit-addressable. Table 16. 88/239 XPWM frequency Mode 0 Resolution 8-bit 10-bit 12-bit 14-bit 16-bit CPU Clock/1 25ns 156.25kHz 39.06kHz 9.77kHz 2.44Hz 610.35Hz CPU Clock/64 1.6s 2.44Hz 610.35Hz 152.58Hz 38.15Hz 9.54Hz Mode 1 Resolution 8-bit 10-bit 12-bit 14-bit 16-bit CPU Clock/1 25ns 78.12kHz 19.53kHz 4.88kHz 1.22kHz 305.17Hz CPU Clock/64 1.6s 1.22kHz 305.17Hz 76.29Hz 19.07Hz 4.77Hz Doc ID 8673 Rev. 3 ST10F280 11.2.3 PWM module XPWM Control Registers XPWMCON0 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0 PIR3 PIR2 PIR1 PIR0 PIE3 PIE2 PIE1 PIE0 PTI3 PTI2 PTI1 PTI0 PTR3 PTR2 PTR1 PTR0 R/W R/W R/W R/W R/W R/W R/W R/W R/W R/W R/W R/W R/W R/W R/W R/W Address: 0xEC00h Reset: 0x0000h Type: R/W PTRx XPWM Timer x Run Control Bit 0: Timer XPTx is disconnected from its input clock 1: Timer XPTx is running PTIx XPWM Timer x Input Clock Selection 0: Timer XPTx clocked with CLKCPU 1: TimerX PTx clocked with CLKCPU / 64 PIEx XPWM Channel x Interrupt Enable Flag 0: Interrupt from channel x disabled 1: Interrupt from channel x enabled PIRx XPWM Channel x Interrupt Request Flag 0: No interrupt request from channel x 1: Channel x interrupt pending (must be reset via software) Register XPWMCON0 controls the function of the timers of the four XPWM channels and the channel specific interrupts. Having the control bits organized in functional groups allows e.g. to start or stop all 4 XPWM timers simultaneously with one bitfield instruction. Note: This register is not bit-addressable. Doc ID 8673 Rev. 3 89/239 PWM module ST10F280 XPWMCON1 15 14 13 12 11 10 9 8 7 6 5 4 PS3 PS2 - PB01 - - - - PM3 PM2 PM1 PM0 R/W R/W - R/W - - - - R/W R/W R/W R/W Address: 0xEC02h Reset: 0x0000h Type: R/W 3 2 PEN3 PEN2 R/W R/W 1 0 PEN1 PEN0 R/W R/W PENx XPWM Channel x Output Enable Bit 0: Channel x output signal disabled, generate interrupt only 1: Channel x output signal enabled PMx XPWM Channel x Mode Control Bit 0: Channel x operates in mode 0, edge aligned PWM 1: Channel x operates in mode 1, center aligned PWM PB01 XPWM Channel 0/1 Burst Mode Control Bit 0: Channels 0 and 1 work independently in respective standard mode 1: Outputs of channels 0 and 1 are ANDed to XPWM0 in burst mode PSx XPWM Channel x Single Shot Mode Control Bit 0: Channel x works in respective standard mode 1: Channel x operates in single shot mode Register XPWMCON1 controls the operating modes and the outputs of the four XPWM channels. The basic operating mode for each channel (standard = edge aligned, or symmetrical = center aligned PWM mode) is selected by the mode bits XPMx. Burst mode (channels 0 and 1) and single shot mode (channel 2 or 3) are selected by separate control bits. The output signal of each XPWM channel is individually enabled by bit PENx. If the output is not enabled the respective pin can only be used to generate an interrupt request. Note: This register is not bit-addressable. 11.2.4 Interrupt request generation Each of the four channels of the XPWM module can generate an individual interrupt request. Each of these "channel interrupts" can activate the common "module interrupt", which actually interrupts the CPU. This common module interrupt is controlled by the XPWM Module Interrupt Control register XP2IC(Xperipherals 2 control register). The interrupt service routine can determine the active channel interrupt(s) from the channel specific interrupt request flags PIRx in register XPWMCON0. The interrupt request flag PIRx of a channel is set at the beginning of a new PWM cycle, i.e. upon loading the shadow registers. This indicates that registers XPPx and XPWx are now ready to receive a new value. If a channel interrupt is enabled via its respective PIEx bit, also the common interrupt request flag XP2IR in register XP2IC is set, provided that it is enabled via the common interrupt enable bit XP2IE. Note: 90/239 The channel interrupt request flags (PIRx in register XPWMCON0) are not automatically cleared by hardware upon entry into the interrupt service routine, so they must be cleared via software. The module interrupt request flag XP2IR is cleared by hardware upon entry into the service routine, regardless of how many channel interrupts were active. However, it Doc ID 8673 Rev. 3 ST10F280 PWM module will be set again if during execution of the service routine a new channel interrupt request is generated. XP2IC 15 14 13 12 11 10 9 8 7 6 - - - - - - - - XP2IR XP2IE ILVL GLVL R/W R/W R/W R/W Address: 0xF196h / CBh ESFR Reset: 0x--00h Type: R/W 5 4 3 2 1 0 Note: Refer to the general Interrupt Control Register description for an explanation of the control fields. 11.2.5 XPWM output signals The output signals of the four XPWM channels are XPWM3...XPWM0. The output signal of each PWM channel is individually enabled by control bit PENx in register XPWMCON1. The XPWM signals are XORed with the outputs of the register XPOLAR(3...0) before being driven to the output pins. This allows driving the XPWM signal directly to the output pin (XPOLAR.x='0') or driving the inverted XPWM signal (XPOLAR.x='1'). Figure 24. XPWM output signal generation 807-#/.0%. ,ATCH 80/,!2 8/2 0IN 807- 807-#/.0%. ,ATCH 80/,!2 8/2 0IN 807- 807-#/.0%. ,ATCH 80/,!2 8/2 0IN 807- 8/2 07- 0IN 807- 07- 07- 07- 807-#/.0%. 807-#/.0" ,ATCH 80/,!2 ("1($'5 Doc ID 8673 Rev. 3 91/239 PWM module 11.2.6 ST10F280 XPOLAR Register (polarity of the XPWM channel) XPOLAR 15 14 13 12 11 10 9 8 7 6 5 4 - - - - - - - - - - - - 3 R/W Address: 0xEC04h Reset: 0x0000h Type: R/W 2 1 0 XPOLAR.3 XPOLAR.2 XPOLAR.1 XPOLAR.0 R/W R/W R/W XPOLAR.x XPOLAR Channel x polarity Bit 0: Polarity of Channel x is normal 1: Polarity of Channel x is inverted Software control of the XPWM outputs In an application the XPWM output signals are generally controlled by the XPWM module. However, it may be necessary to influence the level of the XPWM output pins via software either to initialize the system or to react on some extraordinary condition, e.g. a system fault or an emergency. Clearing the timer run bit PTRx stops the associated counter and leaves the respective output at its current level. The individual XPWM channel outputs are controlled by comparators according to the formula: PWM output signal = [PTx] [PWx shadow latch]. So whenever software changes registers XPTx, the respective output will reflect the condition after the change. Loading timer XPTx with a value greater than or equal to the value in XPWx immediately sets the respective output, a XPTx value below the XPWx value clears the respective output. Note: 92/239 To prevent further PWM pulses from occurring after such a software intervention the respective counter must be stopped first. Doc ID 8673 Rev. 3 ST10F280 12 Parallel ports Parallel ports In order to accept or generate single external control signals or parallel data, the ST10F280 provides up to 143 parallel I/O lines, organized into two 16-bit I/O port (Port 2, XPort9), eight 8-bit I/O ports (PORT0 made of P0H and P0L, PORT1 made of P1H and P1L, Port 4, Port 6, Port 7, Port 8), one 15-bit I/O port (Port 3) and two 16-bit input port (Port 5, XPort10). These port lines may be used for general purpose Input/Output, controlled via software, or may be used implicitly by ST10F280's integrated peripherals or the External Bus Controller. All port lines are bit addressable, and all input/output lines are individually (bit-wise) programmable as inputs or outputs via direction registers (except Port 5, XPort10). The I/O ports are true bidirectional ports which are switched to high impedance state when configured as inputs. The output drivers of seven I/O ports (2, 3, 4, 6, 7, 8, 9) can be configured (pin by pin) for push/pull operation or open-drain operation via ODPx control registers. The output driver of the pads are programmable to adapt the edge characteristics to the application requirement and to improve the EMI behaviour. This is possible using the POCONx registers for Ports P0L, P0H, P1L, P1H, P2, P3, P4, P6, P7, P8. The output driver capabilities of ALE, RD and WR control lines are programmable with the dedicated bits of POCON20 control register. The input threshold levels are programmable (TTL/CMOS) for five ports (2, 3, 4, 7, 8) with the PICON register control bits. The logic level of a pin is clocked into the input latch once per state time, regardless whether the port is configured for input or output. A write operation to a port pin configured as an input causes the value to be written into the port output latch, while a read operation returns the latched state of the pin itself. A readmodify-write operation reads the value of the pin, modifies it, and writes it back to the output latch. Writing to a pin configured as an output (DPx.y=`1') causes the output latch and the pin to have the written value, since the output buffer is enabled. Reading this pin returns the value of the output latch. A read-modify-write operation reads the value of the output latch, modifies it, and writes it back to the output latch, thus also modifying the level at the pin. Note: The new I/O ports (XPort9, XPort10) are not mapped on the SFR space but on the internal XBUS interface. The XPort9 and XPort10 are enabled by setting XPEN bit 2 of the SYSCON register and bit 3 of the new XPERCON register. On the XBUS interface, the registers are not bit-addressable. Doc ID 8673 Rev. 3 93/239 94/239 Doc ID 8673 Rev. 3 9 9 9 9 9 9 9 9 9 9 9 9 9 9 9 9 9 9 9 9 9 9 9 9 0 0 0 9 % 9 9 9 9 9 9 9 9 9 9 9 9 9 9 9 9 $0 $0 9 9 9 9 9 9 9 9 9 9 9 9 9 9 9 9 /$0 % /$0 % /$0 % 0$)$)3 /$0 % /$0 % 9 9 9 9 9 9 9 9 9 9 9 9 9 9 9 $0 "IT HAS AN )/ FUNCTION "IT HAS NO )/ DEDICATED FUNCTION OR IS NOT IMPLEMENTED 2EGISTER BELONGS TO %3&2 AREA 0,). 0(). 0,). 0(). 0,). 0,). 0,). 9 9 9 9 9 9 9 9 9 9 9 9 9 9 9 9 0 0)#/. 9 9 9 9 9 9 9 9 0 $0 $0 9 9 9 9 9 9 9 9 9 9 9 9 9 9 9 /$0 % 9 9 9 9 9 9 9 9 9 9 9 9 9 9 9 9 9 9 9 9 9 9 9 9 $0( % 0 9 9 9 9 9 9 9 9 0( 9 9 9 9 9 9 9 9 $0, % $0 9 9 9 9 9 9 9 9 0, 9 9 9 9 9 9 9 9 $0( % 9 9 9 9 9 9 9 9 9 9 9 9 9 9 9 9 9 9 9 9 9 9 9 9 0( 9 9 9 9 9 9 9 9 0)#/. % $IRECTION #ONTROL 2EGISTERS $0, % 0 9 9 9 9 9 9 9 9 0, $ATA )NPUT /UTPUT 2EGISTER 0/#/.( % 0/#/., % 0/#/.( % 9 9 9 9 9 0/#/., % 9 9 9 9 9 9 9 9 9 9 9 9 9 9 9 9 9 9 9 9 9 9 9 9 9 9 9 9 9 9 9 9 9 9 9 9 9 9 9 9 9 9 9 9 9 9 9 9 9 9 9 9 9 9 9 9 9 9 9 9 9 9 9 9 9 9 9 9 9 9 9 9 9 9 9 9 9 9 9 9 9 9 9 9 9 9 9 9 9 9 9 9 9 9 9 9 9 9 9 9 9 9 9 9 9 /UTPUT $RIVER #ONTROL 2EGISTER 2$ 72 !,% LINES ONLY 0/#/. % 9 9 9 9 9 9 9 9 0/#/. % 9 9 9 9 9 9 9 9 0/#/. % 9 9 9 9 9 9 9 9 0/#/. % 0/#/. % 9 9 9 9 9 9 9 9 9 9 9 9 0/#/. % 9 9 9 9 9 9 9 9 9 9 9 9 9 9 9 9 9 9 9 9 9 9 9 9 9 9 9 9 9 9 9 9 9 0/#/. % 9 9 4HRESHOLD /PEN $RAIN #ONTROL Parallel ports ST10F280 Figure 25. SFRs associated with the parallel ports ("1($'5 ST10F280 Parallel ports Figure 26. XBUS registers associated with the parallel ports 9 9 9 9 9 9 9 9 9 9 9 9 9 9 9 9 80 9 9 9 9 9 9 9 9 9 9 9 9 9 9 9 9 8$0 803%4 9 9 9 9 9 9 9 9 9 99 9 99 9 9 803%4 9 9 9 9 9 9 9 9 9 99 9 99 9 9 8/03%4 9 9 9 9 9 9 99 9 99 9 99 9 9 80#,2 9 9 9 9 9 9 9 9 9 99 9 99 9 9 80#,2 9 9 9 9 9 9 9 9 9 99 9 99 9 9 8/0#,2 9 9 9 9 9 9 99 9 99 9 99 9 9 80 9 9 9 9 9 9 9 9 9 99 9 99 9 9 80$)$)3 9 9 9 9 9 9 9 9 9 99 9 99 9 9 8!$#-58 8/0 9 9 9 9 9 9 9 9 9 9 9 9 9 9 9 9 9 ("1($'5 12.1 Introduction 12.1.1 Open drain mode In the ST10F280 some ports provide Open Drain Control. This makes it possible to switch the output driver of a port pin from a push/pull configuration to an open drain configuration. In push/pull mode a port output driver has an upper and a lower transistor, thus it can actively drive the line either to a high or a low level. In open drain mode the upper transistor is always switched off, and the output driver can only actively drive the line to a low level. When writing a `1' to the port latch, the lower transistor is switched off and the output enters a high-impedance state. The high level must then be provided by an external pull-up device. With this feature, it is possible to connect several port pins together to a Wired-AND configuration, saving external glue logic and/or additional software overhead for enabling/disabling output signals. This feature is implemented for ports P2, P3, P4, P6, P7 and P8 (see respective sections), and is controlled through the respective Open Drain Control Registers ODPx. These registers allow the individual bit-wise selection of the open drain mode for each port line. If the respective control bit ODPx.y is `0' (default after reset), the output driver is in the push/pull mode. If ODPx.y is `1', the open drain configuration is selected. Note that all ODPx registers are located in the ESFR space. Figure 27. Output drivers in push/pull mode and in open drain mode %XTERNAL 0ULLUP 0IN 1 0IN 1 0USH 0ULL /UTPUT $RIVER /PEN $RAIN /UTPUT $RIVER ("1($'5 Doc ID 8673 Rev. 3 95/239 Parallel ports 12.1.2 ST10F280 Input threshold control The standard inputs of the ST10F280 determine the status of input signals according to TTL levels. In order to accept and recognize noisy signals, CMOS-like input thresholds can be selected instead of the standard TTL thresholds for all pins of Port 2, Port 3, Port4, Port 7 and Port 8. These special thresholds are defined above the TTL thresholds and feature a defined hysteresis to prevent the inputs from toggling while the respective input signal level is near the thresholds. The Port Input Control register PICON is used to select these thresholds for each byte of the indicated ports, i.e. the 8-bit ports P7 and P8 are controlled by one bit each while ports P2 and P3 are controlled by two bits each. PICON 15 14 13 12 11 10 9 8 - - - - - - - - 7 P8LIN P7LIN R/W Address: 0xF1C4h / E2h ESFR Reset: 0x--00h Type: R/W 6 R/W 5 - 4 3 2 1 0 P4LIN P3HIN P3LIN P2HIN P2LIN R/W R/W R/W R/W R/W R/W PxLIN Port x Low Byte Input Level Selection 0: Pins Px.7...Px.0 switch on standard TTL input levels 1: Pins Px.7...Px.0 switch on special threshold input levels PxHIN Port x High Byte Input Level Selection 0: Pins Px.15...Px.8 switch on standard TTL input levels 1: Pins Px.15...Px.8 switch on special threshold input levels All options for individual direction and output mode control are available for each pin, independent of the selected input threshold. The input hysteresis provides stable inputs from noisy or slowly changing external signals. Figure 28. Hysteresis for special input thresholds (YSTERESIS )NPUT LEVEL "IT STATE ("1($'5 12.1.3 Output driver control The port output control registers POCONx allow to select the port output driver characteristics of a port. The aim of these selections is to adapt the output drivers to the application's requirements, and to improve the EMI behaviour of the device. Two characteristics may be selected: 96/239 Doc ID 8673 Rev. 3 ST10F280 Parallel ports Edge characteristic defines the rise/fall time for the respective output, ie. the transition time. Slow edge reduce the peak currents that are sinked/sourced when changing the voltage level of an external capacitive load. For a bus interface or pins that are changing at frequency higher than 1MHz, however, fast edges may still be required. Driver characteristic defines either the general driving capability of the respective driver, or if the driver strength is reduced after the target output level has been reached or not. Reducing the driver strength increases the output's internal resistance, which attenuates noise that is imported via the output line. For driving LEDs or power transistors, however, a stable high output current may still be required. For each feature, a 2-bit control field (ie. 4 bits) is provided for each group of 4 port pads (ie. a port nibble), in port output control registers POCONx. POCONx 15 14 13 12 11 10 9 8 - - - - - - - - Address: 0xF0yyh / zzh for 8-bit Ports ESFR Reset: 0x--00h Type: R/W 7 6 5 4 3 2 1 0 PN1DC PN1EC PN0DC PN0EC R/W R/W R/W R/W POCONx 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0 PN3DC PN3EC PN2DC PN2EC PN1DC PN1EC PN0DC PN0EC R/W R/W R/W R/W R/W R/W R/W R/W Address: 0xF0yyh / zzh for 16-bit Ports ESFR Reset: 0x0000h Type: R/W PNxEC Port Nibble x Edge Characteristic (rise/fall time) 00: Fast edge mode, rise/fall times depend on the driver's dimensioning. 01: Slow edge mode, rise/fall times ~60 ns 10: Reserved 11: Reserved PNxDC Port Nibble x Driver Characteristic (output current) 00: High Current mode: Driver always operates with maximum strength. 01: Dynamic Current mode: Driver strength is reduced after the target level has been reached. 10: Low Current mode: Driver always operates with reduced strength. 11: Reserved Note: In case of reading an 8 bit P0CONX register, high Byte (bit 15..8) is read as 00h. Doc ID 8673 Rev. 3 97/239 Parallel ports ST10F280 Port control register allocation The table below lists the defined POCON registers and the allocation of control bitfields and port pins: Table 17. Control register POCON registers Physical address 8-Bit address POCON0L F080h 40h P0L.7...4 P0L.3...0 POCON0H F082h 41h P0H.7...4 P0H.3...0 POCON1L F084h 42h P1L.7...4 P1L.3...0 POCON1H F086h 43h P1H.7...4 P1H.3...0 POCON2 F088h 44h P2.15...12 P2.11...8 P2.7...4 P2.3...0 POCON3 F08Ah 45h P3.15, P3.13...12 P3.11...8 P3.7...4 P3.3...0 POCON4 F08Ch 46h P4.7...4 P4.3...0 POCON6 F08Eh 47h P6.7...4 P6.3...0 POCON7 F090h 48h P7.7...4 P7.3...0 POCON8 F092h 49h P8.7...4 P8.3...0 Controlled port Dedicated pins output control Programmable pad drivers also are supported for the dedicated pins ALE, RD and WR. For these pads, a special POCON20 register is provided. POCON20 15 14 13 12 11 10 9 8 - - - - - - - - Address: 0xF0AAh / 5h ESFR Reset: 0x0000h Type: R/W 7 6 5 4 3 2 1 0 PN1DC PN1EC PN0DC PN0EC R/W R/W R/W R/W PN0EC RD, WR Edge Characteristic (rise/fall time) 00: Fast edge mode, rise/fall times depend on the driver's dimensioning. 01: Slow edge mode, rise/fall times ~60 ns 10: Reserved 11: Reserved PN0DC RD, WR Driver Characteristic (output current) 00: High Current mode: Driver always operates with maximum strength. 01: Dynamic Current mode: Driver strength is reduced after the target level has been reached. 10: Low Current mode: Driver always operates with reduced strength. 11: Reserved 98/239 Doc ID 8673 Rev. 3 ST10F280 Parallel ports PN1EC ALE Edge Characteristic (rise/fall time) 00: Fast edge mode, rise/fall times depend on the driver's dimensioning. 01: Slow edge mode, rise/fall times ~60 ns 10: Reserved 11: Reserved PN1DC ALE Driver Characteristic (output current) 00: High Current mode: Driver always operates with maximum strength. 01: Dynamic Current mode: Driver strength is reduced after the target level has been reached. 10: Low Current mode: Driver always operates with reduced strength. 11: Reserved 12.1.4 Alternate port functions Each port line has one associated programmable alternate input or output function. PORT0 and PORT1 may be used as the address and data lines when accessing external memory. Port 4 outputs the additional segment address bits A23/A19/A18/A16 in systems where more than 64 KBytes of memory are to be accessed directly. Port 6 provides the optional chip select outputs and the bus arbitration lines. Port 2, Port 7 and Port 8 are associated with the capture inputs or compare outputs of the CAPCOM units and/or with the outputs of the PWM module. Port 2 is also used for fast external interrupt inputs and for timer 7 input. Port 3 includes alternate input/output functions of timers, serial interfaces, the optional bus control signal BHE/WRH and the system clock output (CLKOUT). Port 5 is used for the analog input channels to the A/D converter or timer control signals. If an alternate output function of a pin is to be used, the direction of this pin must be programmed for output (DPx.y=`1'), except for some signals that are used directly after reset and are configured automatically. Otherwise the pin remains in the high-impedance state and is not effected by the alternate output function. The respective port latch should hold a `1', because its output is ANDed with the alternate output data (except for PWM output signals). If an alternate input function of a pin is used, the direction of the pin must be programmed for input (DPx.y=`0') if an external device is driving the pin. The input direction is the default after reset. If no external device is connected to the pin, however, one can also set the direction for this pin to output. In this case, the pin reflects the state of the port output latch. Thus, the alternate input function reads the value stored in the port output latch. This can be used for testing purposes to allow a software trigger of an alternate input function by writing to the port output latch. On most of the port lines, the user software is responsible for setting the proper direction when using an alternate input or output function of a pin. This is done by setting or clearing the direction control bit DPx.y of the pin before enabling the alternate function. There are port lines, however, where the direction of the port line is switched automatically. For instance, in the multiplexed external bus modes of PORT0, the direction must be switched several times for an instruction fetch in order to output the addresses and to input the data. Obviously, this cannot be done through instructions. In these cases, the direction of the port line is switched automatically by hardware if the alternate function of such a pin is enabled. Doc ID 8673 Rev. 3 99/239 Parallel ports ST10F280 To determine the appropriate level of the port output latches check how the alternate data output is combined with the respective port latch output. There is one basic structure for all port lines with only an alternate input function. Port lines with only an alternate output function, however, have different structures due to the way the direction of the pin is switched and depending on whether the pin is accessible by the user software or not in the alternate function mode. All port lines that are not used for these alternate functions may be used as general purpose I/O lines. When using port pins for general purpose output, the initial output value should be written to the port latch prior to enabling the output drivers, in order to avoid undesired transitions on the output pins. This applies to single pins as well as to pin groups (see examples below). SINGLE_BIT: BSET P4.7 BSET DP4.7 ; Initial output level is "high" ; Switch on the output driver BIT_GROUP: BFLDH P4, #24H, #24H ; Initial output level is "high" BFLDH DP4, #24H, #24H ; Switch on the output drivers Note: When using several BSET pairs to control more pins of one port, these pairs must be separated by instructions, which do not reference the respective port (see "Particular Pipeline Effects" in Chapter 6: Central Processing Unit (CPU)). 12.2 Port 0 The two 8-bit ports P0H and P0L represent the higher and lower part of PORT0, respectively. Both halves of PORT0 can be written (e.g. via a PEC transfer) without effecting the other half. If this port is used for general purpose I/O, the direction of each line can be configured via the corresponding direction registers DP0H and DP0L. 100/239 Doc ID 8673 Rev. 3 ST10F280 Parallel ports P0L 15 14 13 12 11 10 9 8 7 - - - - - - - - P0L.7 Address: 0xFF00h / 80h SFR Reset: 0x--00h Type: R/W 6 5 4 P0L.6 P0L.5 3 P0L.4 2 P0L.3 P0L.2 1 0 P0L.1 P0L.0 R/W R/W R/W R/W R/W R/W R/W R/W 7 6 5 4 3 2 1 0 P0H 15 14 13 12 11 10 9 8 - - - - - - - - P0H.7 P0H.6 P0H.5 P0H.4 P0H.3 P0H.2 P0H.1 P0H.0 R/W Address: 0xFF020h / 81h SFR Reset: 0x--00h Type: R/W R/W R/W 5 4 R/W R/W R/W R/W R/W 1 0 P0X.y Port data register P0H or P0L bit y DP0L 15 14 13 12 11 10 9 8 - - - - - - - - Address: 0xF100h / 80h ESFR Reset: 0x--00h Type: R/W 7 6 3 2 DP0L.7 DP0L.6 DP0L.5 DP0L.4 DP0L.3 DP0L.2 DP0L.1 DP0L.0 R/W R/W R/W R/W R/W R/W R/W R/W 7 6 5 4 3 2 1 0 DP0H 15 14 13 12 11 10 9 8 - - - - - - - - DP0H.7 DP0H.6 DP0H.5 DP0H.4 DP0H.3 DP0H.2 DP0H.1 DP0H.0 R/W Address: 0xF102h / 81h ESFR Reset: 0x--00h Type: R/W R/W R/W R/W R/W R/W R/W R/W DP0X.y Port direction register DP0H or DP0L bit y DP0X.y = 0: Port line P0X.y is an input (high-impedance) DP0X.y = 1: Port line P0X.y is an output Doc ID 8673 Rev. 3 101/239 Parallel ports 12.2.1 ST10F280 Alternate functions of Port 0 When an external bus is enabled, PORT0 is used as data bus or address/data bus. Note that an external 8-bit de-multiplexed bus only uses P0L, while P0H is free for I/O (provided that no other bus mode is enabled). PORT0 is also used to select the system start-up configuration. During reset, PORT0 is configured to input, and each line is held high through an internal pull-up device. Each line can now be individually pulled to a low level (see DC-level specifications) through an external pull-down device. A default configuration is selected when the respective PORT0 lines are at a high level. Through pulling individual lines to a low level, this default can be changed according to the needs of the applications. The internal pull-up devices are designed such that an external pull-down resistors can be used to apply a correct low level. These external pull-down resistors can remain connected to the PORT0 pins also during normal operation, however, care has to be taken such that they do not disturb the normal function of PORT0 (this might be the case, for example, if the external resistor is too strong). With the end of reset, the selected bus configuration will be written to the BUSCON0 register. The configuration of the high byte of PORT0, will be copied into the special register RP0H. This read-only register holds the selection for the number of chip selects and segment addresses. Software can read this register in order to react according to the selected configuration, if required. When the reset is terminated, the internal pull-up devices are switched off, and PORT0 will be switched to the appropriate operating mode. During external accesses in multiplexed bus modes PORT0 first outputs the 16-bit intrasegment address as an alternate output function. PORT0 is then switched to highimpedance input mode to read the incoming instruction or data. In 8-bit data bus mode, two memory cycles are required for word accesses, the first for the low byte and the second for the high byte of the word. During write cycles PORT0 outputs the data byte or word after outputting the address. During external accesses in de-multiplexed bus modes PORT0 reads the incoming instruction or data word or outputs the data byte or word. Figure 29. Port 0 I/O and alternate functions $OWHUQDWH)XQFWLRQ 3+ 3257 3/ 3+ 3+ 3+ 3+ 3+ 3+ 3+ 3+ 3/ 3/ 3/ 3/ 3/ 3/ 3/ 3/ *HQHUDO3XUSRVH ,QSXW2XWSXW D E ' ' ' ' ' ' ' ' ELW 'HPXOWLSOH[HG%XV F ' ' ' ' ' ' ' ' ' ' ' ' ' ' ' ' ELW 'HPXOWLSOH[HG%XV G $ $ $ $ $ $ $ $ $' $' $' $' $' $' $' $' ELW 0XOWLSOH[HG%XV $' $' $' $' $' $' $' $' $' $' $' $' $' $' $' $' ELW 0XOWLSOH[HG%XV ("1($'5 When an external bus mode is enabled, the direction of the port pin and the loading of data into the port output latch are controlled by the bus controller hardware. The input of the port output latch is disconnected from the internal bus and is switched to the line labeled "Alternate Data Output" via a multiplexer. The alternate data can be the 16-bit 102/239 Doc ID 8673 Rev. 3 ST10F280 Parallel ports intra-segment address or the 8/16-bit data information. The incoming data on PORT0 is read on the line "Alternate Data Input". While an external bus mode is enabled, the user software should not write to the port output latch, otherwise unpredictable results may occur. When the external bus modes are disabled, the contents of the direction register last written by the user becomes active. The Figure 30 shows the structure of a PORT0 pin. Figure 30. Block diagram of a Port 0 pin 7RITE $0(Y $0,Y !LTERNATE $IRECTION -58 $IRECTION ,ATCH 2EAD $0(Y $0,Y !LTERNATE &UNCTION %NABLE )NTERNAL "US !LTERNATE $ATA /UTPUT 7RITE 0(Y 0,Y 0ORT $ATA /UTPUT 0ORT /UTPUT ,ATCH -58 0(Y 0,Y /UTPUT "UFFER 2EAD 0(Y 0,Y #05 #LOCK -58 )NPUT ,ATCH Y ("1($'5 12.3 Port 1 The two 8-bit ports P1H and P1L represent the higher and lower part of PORT1, respectively. Both halves of PORT1 can be written (e.g. via a PEC transfer) without effecting the other half. If this port is used for general purpose I/O, the direction of each line can be configured via the corresponding direction registers DP1H and DP1L. P1L 15 14 13 12 11 10 9 8 7 - - - - - - - - P1L.7 R/W Address: 0xFF04h / 82h SFR Reset: 0x--00h Type: R/W Doc ID 8673 Rev. 3 6 5 P1L.6 P1L.5 R/W R/W 4 P1L.4 R/W 3 2 P1L.3 P1L.2 R/W R/W 1 0 P1L.1 P1L.0 R/W R/W 103/239 Parallel ports ST10F280 P1H 15 14 13 12 11 10 9 8 - - - - - - - - 7 6 R/W Address: 0xFF06h / 83h SFR Reset: 0x--00h Type: R/W 5 4 3 2 1 0 P1H.7 P1H.6 P1H.5 P1H.4 P1L.3 P1H.2 P1H.1 P1H.0 R/W R/W R/W R/W R/W R/W 2 1 R/W P1X.y Port data register P1H or P1L bit y DP1L 15 14 13 12 11 10 9 8 - - - - - - - - Address: 0xF104h / 82h ESFR Reset: 0x--00h Type: R/W 7 6 5 4 3 0 DP1L.7 DP1L.6 DP1L.5 DP1L.4 DP1L.3 DP1L.2 DP1L.1 DP1L.0 R/W R/W R/W R/W R/W R/W R/W R/W 7 6 5 4 3 2 1 0 8 - - - - - - - - Address: 0xF106h / 83h ESFR Reset: 0x--00h Type: R/W DP1H.0 9 DP1H.1 10 DP1H.2 11 DP1H.3 12 DP1H.4 13 DP1H.5 14 DP1H.6 15 DP1H.7 DP1H R/W R/W R/W R/W R/W R/W R/W R/W DP1X.y Port direction register DP1H or DP1L bit y DP1X.y = 0: Port line P1X.y is an input (high-impedance) DP1X.y = 1: Port line P1X.y is an output 12.3.1 Alternate functions of Port 1 When a de-multiplexed external bus is enabled, PORT1 is used as address bus. Note that de-multiplexed bus modes use PORT1 as a 16-bit port. Otherwise all 16 port lines can be used for general purpose I/O. The upper four pins of PORT1 (P1H.7...P1H.4) also serve as capture input lines for the CAPCOM2 unit (CC27IO...CC24IO). 104/239 Doc ID 8673 Rev. 3 ST10F280 Parallel ports As all other capture inputs, the capture input function of pins P1H.7...P1H.4 can also be used as external interrupt inputs (200 ns sample rate at 40MHz CPU clock). During external accesses in de-multiplexed bus modes PORT1 outputs the 16-bit intrasegment address as an alternate output function. During external accesses in multiplexed bus modes, when no BUSCON register selects a de-multiplexed bus mode, PORT1 is not used and is available for general purpose I/O (see Figure 31). When an external bus mode is enabled, the direction of the port pin and the loading of data into the port output latch are controlled by the bus controller hardware. The input of the port output latch is disconnected from the internal bus and is switched to the line labeled "Alternate Data Output" via a multiplexer. The alternate data is the 16-bit intra-segment address. While an external bus mode is enabled, the user software should not write to the port output latch, otherwise unpredictable results may occur. When the external bus modes are disabled, the contents of the direction register last written by the user becomes active. Figure 31. Port 1 I/O and alternate functions $OWHUQDWH)XQFWLRQ 3+ 3257 3/ D 0( 0( 0( 0( 0( 0( 0( 0( 0, 0, 0, 0, 0, 0, 0, 0, 'ENERAL 0URPOSE )NPUT/UTPUT E ! ! ! ! ! ! ! ! ! ! ! ! ! ! ! ! BIT $EMULTIPLEXED "US ##) ##) ##) ##) #!0#/- #APTURE )NPUTS ("1($'5 The figure below shows the structure of a PORT1 pin. Doc ID 8673 Rev. 3 105/239 Parallel ports ST10F280 Figure 32. Block diagram of a Port 1 pin 7RITE $0(Y $0,Y hv -58 $IRECTION ,ATCH 2EAD $0(Y $0,Y !LTERNATE &UNCTION %NABLE )NTERNAL "US !LTERNATE $ATA /UTPUT 7RITE 0(Y 0,Y 0ORT $ATA /UTPUT 0ORT /UTPUT ,ATCH -58 0(Y 0,Y /UTPUT "UFFER 2EAD 0(Y 0,Y #05 #LOCK -58 )NPUT ,ATCH Y ("1($'5 12.4 Port 2 If this 16-bit port is used for general purpose I/O, the direction of each line can be configured via the corresponding direction register DP2. Each port line can be switched into push/pull or open drain mode via the open drain control register ODP2. P2 15 P2.15 R/W 14 13 12 P2.14 P2.13 P2.12 R/W R/W R/W 11 10 P2.11 P2.10 R/W Address: 0xFFC0h / E0h SFR Reset: 0x0000h Type: R/W R/W 9 8 7 6 5 4 3 2 1 0 P2.9 P2.8 P2.7 P2.6 P2.5 P2.4 P2.3 P2.2 P2.1 P2.0 R/W R/W R/W R/W R/W R/W R/W R/W R/W R/W P2.y Port data register P2 bit y 106/239 Doc ID 8673 Rev. 3 ST10F280 Parallel ports DP2 DP2.0 0 DP2.1 1 DP2.2 2 DP2.3 3 DP2.4 4 DP2.5 5 DP2.6 6 DP2.7 7 DP2.8 8 DP2.9 9 DP2.10 10 DP2.11 11 DP2.12 12 DP2.13 13 DP2.14 14 DP2.15 15 R/W R/W R/W R/W R/W R/W R/W R/W R/W R/W R/W R/W R/W R/W R/W R/W Address: 0xFFC2h / E1h SFR Reset: 0x0000h Type: R/W DP2.y Port direction register DP2 bit y DP2.y = 0: Port line P2.y is an input (high-impedance) DP2.y = 1: Port line P2.y is an output ODP2 ODP2.0 0 ODP2.1 1 ODP2.2 2 ODP2.3 3 ODP2.4 4 ODP2.5 5 ODP2.6 6 ODP2.7 7 ODP2.8 8 ODP2.9 9 ODP2.10 10 ODP2.11 11 ODP2.12 12 ODP2.13 13 ODP2.14 14 ODP2.15 15 R/W R/W R/W R/W R/W R/W R/W R/W R/W R/W R/W R/W R/W R/W R/W R/W Address: 0xF1C2h / E1h ESFR Reset: 0x0000h Type: R/W ODP2.y Port 2 Open Drain control register bit y ODP2.y = 0: Port line P2.y output driver in push/pull mode ODP2.y = 1: Port line P2.y output driver in open drain mode 12.4.1 Alternate functions of Port 2 All Port 2 lines (P2.15...P2.0) serve as capture inputs or compare outputs (CC15IO...CC0IO) for the CAPCOM1 unit. When a Port 2 line is used as a capture input, the state of the input latch, which represents the state of the port pin, is directed to the CAPCOM unit via the line "Alternate Pin Data Input". If an external capture trigger signal is used, the direction of the respective pin must be set to input. If the direction is set to output, the state of the port output latch will be read since the pin represents the state of the output latch. This can be used to trigger a capture event through software by setting or clearing the port latch. Note that in the output configuration, no external device may drive the pin, otherwise conflicts would occur. When a Port 2 line is used as a compare output (compare modes 1 and 3), the compare event (or the timer overflow in compare mode 3) directly effects the port output latch. In compare mode 1, when a valid compare match occurs, the state of the port output latch is read by the CAPCOM control hardware via the line "Alternate Latch Data Input", inverted, and written back to the latch via the line "Alternate Data Output". Doc ID 8673 Rev. 3 107/239 Parallel ports ST10F280 The port output latch is clocked by the signal "Compare Trigger" which is generated by the CAPCOM unit. In compare mode 3, when a match occurs, the value '1' is written to the port output latch via the line "Alternate Data Output". When an overflow of the corresponding timer occurs, a '0' is written to the port output latch. In both cases, the output latch is clocked by the signal "Compare Trigger". The direction of the pin should be set to output by the user, otherwise the pin will be in the high-impedance state and will not reflect the state of the output latch. As can be seen from the port structure below, the user software always has free access to the port pin even when it is used as a compare output. This is useful for setting up the initial level of the pin when using compare mode 1 or the double-register mode. In these modes, unlike in compare mode 3, the pin is not set to a specific value when a compare match occurs, but is toggled instead. When the user wants to write to the port pin at the same time a compare trigger tries to clock the output latch, the write operation of the user software has priority. Each time a CPU write access to the port output latch occurs, the input multiplexer of the port output latch is switched to the line connected to the internal bus. The port output latch will receive the value from the internal bus and the hardware triggered change will be lost. As all other capture inputs, the capture input function of pins P2.15...P2.0 can also be used as external interrupt inputs (200 ns sample rate at 40MHz CPU clock). The upper eight Port 2 lines (P2.15...P2.8) also can serve as Fast External Interrupt inputs from EX0IN to EX7IN. (Fast external interrupt sampling rate is 25ns at 40MHz CPU clock). P2.15 in addition serves as input for CAPCOM2 timer T7 (T7IN). The table below summarizes the alternate functions of Port 2. Table 18. 108/239 Port 2 alternate function Port 2 pin Alternate function a) P2.0 P2.1 P2.2 P2.3 P2.4 P2.5 P2.6 P2.7 P2.8 P2.9 P2.10 P2.11 P2.12 P2.13 P2.14 P2.15 CC0IO CC1IO CC2IO CC3IO CC4IO CC5IO CC6IO CC7IO CC8IO CC9IO CC10IO CC11IO CC12IO CC13IO CC14IO CC15IO Alternate function b) EX0IN Fast External Interrupt 0 Input EX1IN Fast External Interrupt 1 Input EX2IN Fast External Interrupt 2 Input EX3IN Fast External Interrupt 3 Input EX4IN Fast External Interrupt 4 Input EX5IN Fast External Interrupt 5 Input EX6IN Fast External Interrupt 6 Input EX7IN Fast External Interrupt 7 Input Doc ID 8673 Rev. 3 Alternate function c) T7IN Timer T7 Ext. Count Input ST10F280 Parallel ports Figure 33. Port 2 I/O and alternate functions $OWHUQDWH)XQFWLRQ 3RUW 3 3 3 3 3 3 3 3 3 3 3 3 3 3 3 3 *HQHUDO3XUSRVH ,QSXW2XWSXW D E &&,2 &&,2 &&,2 &&,2 &&,2 &&,2 &&,2 &&,2 &&,2 &&,2 &&,2 &&,2 &&,2 &&,2 &&,2 &&,2 &$3&20 &DSWXUH,QSXW&RPSDUH2XWSXW F (;,1 (;,1 (;,1 (;,1 (;,1 (;,1 (;,1 (;,1 )DVW([WHUQDO ,QWHUUXSW,QSXW 7,1 &$3&20 7LPHU7,QSXW ("1($'5 The pins of Port 2 combine internal bus data with alternate data output before the port latch input. Doc ID 8673 Rev. 3 109/239 Parallel ports ST10F280 Figure 34. Block diagram of a Port 2 pin :ULWH2'3\ 2SHQ'UDLQ /DWFK 5HDG2'3\ :ULWH'3\ ,QWHUQDO%XV 'LUHFWLRQ /DWFK 5HDG'3\ $OWHUQDWH 'DWD 2XWSXW 2XWSXW /DWFK 08; 2XWSXW %XIIHU :ULWH3RUW3\ 3\ &&\,2 (;[,1 t &RPSDUH7ULJJHU 5HDG3\ &38&ORFN 08; $OWHUQDWH'DWD,QSXW )DVW([WHUQDO,QWHUUXSW,QSXW ,QSXW /DWFK [ \ ("1($'5 110/239 Doc ID 8673 Rev. 3 ST10F280 12.5 Parallel ports Port 3 If this 15-bit port is used for general purpose I/O, the direction of each line can be configured by the corresponding direction register DP3. Most port lines can be switched into push/pull or open drain mode by the open drain control register ODP3 (pins P3.15, P3.14 and P3.12 do not support open drain mode). Due to pin limitations register bit P3.14 is not connected to an output pin. P3 15 14 P3.15 - 13 12 P3.13 P3.12 R/W R/W R/W 11 10 P3.11 P3.10 R/W Address: 0xFFC4h / E2h SFR Reset: 0x0000h Type: R/W R/W 9 8 7 6 5 4 3 2 1 0 P3.9 P3.8 P3.7 P3.6 P3.5 P3.4 P3.3 P3.2 P3.1 P3.0 R/W R/W R/W R/W R/W R/W R/W R/W R/W R/W 8 7 6 5 4 3 2 1 0 P3.y Port data register P3 bit y 15 14 DP3.15 - DP3.13 DP3.12 DP3.11 DP3.10 DP3.9 DP3.8 DP3.7 DP3.6 DP3.5 DP3.4 DP3.3 DP3.2 DP3.1 DP3.0 DP3 13 12 11 R/W R/W R/W R/W R/W R/W R/W R/W R/W R/W R/W R/W R/W R/W R/W R/W Address: 0xFFC6h / E3h SFR Reset: 0x0000h Type: R/W 10 9 DP3.y Port direction register DP3 bit y DP3.y = 0: Port line P3.y is an input (high-impedance) DP3.y = 1: Port line P3.y is an output Doc ID 8673 Rev. 3 111/239 Parallel ports ST10F280 3 2 1 0 ODP3.0 4 ODP3.1 5 ODP3.2 6 ODP3.3 7 ODP3.4 R/W 8 ODP3.5 - 9 ODP3.6 - 10 ODP3.7 - 11 ODP3.8 12 ODP3.9 13 ODP3.10 14 ODP3.11 15 ODP3.13 ODP3 R/W R/W R/W R/W R/W R/W R/W R/W R/W R/W R/W R/W Address: 0xF1C6h / E3h ESFR Reset: 0x0000h Type: R/W ODP3.y Port 3 Open Drain control register bit y ODP3.y = 0: Port line P3.y output driver in push-pull mode ODP3.y = 1: Port line P3.y output driver in open drain mode 12.5.1 Alternate functions of Port 3 The pins of Port 3 serve for various functions which include external timer control lines, the two serial interfaces and the control lines BHE/WRH and CLKOUT. Table 19. Port 3 pin P3.0 P3.1 P3.2 P3.3 P3.4 P3.5 P3.6 P3.7 P3.8 P3.9 P3.10 P3.11 P3.12 P3.13 P3.14 P3.15 112/239 Port 3 alternate functions Alternate function T0IN CAPCOM1 Timer 0 Count Input T6OUT Timer 6 Toggle Output CAPIN GPT2 Capture Input T3OUT Timer 3 Toggle Output T3EUD Timer 3 External Up/Down Input T4IN Timer 4 Count Input T3IN Timer 3 Count Input T2IN Timer 2 Count Input MRST SSC Master Receive / Slave Transmit MTSR SSC Master Transmit / Slave Receive TxD0 ASC0 Transmit Data Output RxD0 ASC0 Receive Data Input / (Output in synchronous mode) BHE/WRH Byte High Enable / Write High Output SCLK SSC Shift Clock Input/Output --- No pin assigned! CLKOUT System Clock Output Doc ID 8673 Rev. 3 ST10F280 Parallel ports Figure 35. Port 3 I/O and alternate functions $OWHUQDWH)XQFWLRQ 1R3LQ 3RUW D E 3 &/.287 3 3 3 3 3 3 3 3 3 3 3 3 3 3 6&/. %+( 5[' 7[' 0765 0567 7,1 7,1 7,1 7(8' 7287 &$3,1 7287 7,1 :5+ *HQHUDO3XUSRVH,QSXW2XWSXW ("1($'5 The port structure of the Port 3 pins depends on their alternate function (see Figure 36). When the on-chip peripheral associated with a Port 3 pin is configured to use the alternate input function, it reads the input latch, which represents the state of the pin, via the line labeled "Alternate Data Input". Port 3 pins with alternate input functions are: T0IN, T2IN, T3IN, T4IN, T3EUD and CAPIN. When the on-chip peripheral associated with a Port 3 pin is configured to use the alternate output function, its "Alternate Data Output" line is ANDed with the port output latch line. When using these alternate functions, the user must set the direction of the port line to output (DP3.y=1) and must set the port output latch (P3.y=1). Otherwise the pin is in its high-impedance state (when configured as input) or the pin is stuck at '0' (when the port output latch is cleared). When the alternate output functions are not used, the "Alternate Data Output" line is in its inactive state, which is a high level ('1'). Port 3 pins with alternate output functions are: T6OUT, T3OUT, TxD0 and CLKOUT. When the on-chip peripheral associated with a Port 3 pin is configured to use both the alternate input and output function, the descriptions above apply to the respective current operating mode. The direction must be set accordingly. Port 3 pins with alternate input/output functions are: MTSR, MRST, RxD0 and SCLK. Note: Enabling the CLKOUT function automatically enables the P3.15 output driver. Setting bit DP3.15='1' is not required. Doc ID 8673 Rev. 3 113/239 Parallel ports ST10F280 Figure 36. Block diagram of Port 3 pin with alternate input or alternate output function :ULWH2'3\ 2SHQ'UDLQ /DWFK ,QWHUQDO%XV 5HDG2'3\ :ULWH'3\ 'LUHFWLRQ /DWFK 5HDG'3\ $OWHUQDWH 'DWD2XWSXW :ULWH3\ 3RUW2XWSXW /DWFK 3RUW'DWD 2XWSXW 2XWSXW %XIIHU 3\ 5HDG3\ &38&ORFN 08; $OWHUQDWH 'DWD ,QSXW ,QSXW /DWFK \ ("1($'5 Pin P3.12 (BHE/WRH) is another pin with an alternate output function, however, its structure is slightly different (see Figure 37). After reset the BHE or WRH function must be used depending on the system start-up configuration. In either of these cases, there is no possibility to program any port latches before. Thus, the appropriate alternate function is selected automatically. If BHE/WRH is not used in the system, this pin can be used for general purpose I/O by disabling the alternate function (BYTDIS = `1' / WRCFG='0'). 114/239 Doc ID 8673 Rev. 3 ST10F280 Parallel ports Figure 37. Block diagram of pins P3.15 (CLKOUT) and P3.12 (BHE/WRH) :ULWH'3[ 08; 'LUHFWLRQ /DWFK 5HDG'3[ ,QWHUQDO%XV $OWHUQDWH )XQFWLRQ (QDEOH :ULWH3[ $OWHUQDWH 'DWD 2XWSXW 3RUW2XWSXW /DWFK 08; 3%+( 3&/.287 2XWSXW %XIIHU 5HDG3[ &38&ORFN 08; ,QSXW /DWFK [ ("1($'5 Note: Enabling the BHE or WRH function automatically enables the P3.12 output driver. Setting bit DP3.12='1' is not required. During bus hold, pin P3.12 is switched back to its standard function and is then controlled by DP3.12 and P3.12. Keep DP3.12 = '0' in this case to ensure floating in hold mode. 12.6 Port 4 If this 8-bit port is used for general purpose I/O, the direction of each line can be configured via the corresponding direction register DP4. P4 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0 - - - - - - - - P4.7 P4.6 P4.5 P4.4 P4.3 P4.2 P4.1 P4.0 R/W R/W R/W R/W R/W R/W R/W R/W Address: 0xFFC8h / E4h SFR Reset: 0x--00h Type: R/W P4.y Port data register P4 bit y Doc ID 8673 Rev. 3 115/239 Parallel ports ST10F280 DP4 15 14 13 12 11 10 9 8 - - - - - - - - 7 R/W Address: 0xFFCAh / E5h SFR Reset: 0x--00h Type: R/W 6 5 4 3 2 1 0 DP4.7 DP4.6 DP4.5 DP4.4 DP4.3 DP4.2 DP4.1 DP4.0 R/W R/W R/W R/W R/W R/W R/W DP4.y Port direction register DP4 bit y DP4.y = 0: Port line P4.y is an input (high-impedance) DP4.y = 1: Port line P4.y is an output For CAN configuration support (see Chapter 15: CAN modules), Port 4 has a new open drain function, controlled with the new ODP4 register: ODP4 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0 - - - - - - - - ODP4.7 ODP4.6 - - - - - - R/W R/W Address: 0xF1CAh / E5h ESFR Reset: 0x--00h Type: R/W ODP4.y Port 4 Open drain control register bit y ODP4.y = 0: Port line P4.y output driver in push/pull mode ODP4.y = 1: Port line P4.y output driver in open drain mode if P4.y is not a segment address line output Note: Only bits 6 and 7 are implemented, all other bits will be read as "0". 12.6.1 Alternate functions of Port 4 During external bus cycles that use segmentation (i.e. an address space above 64K Bytes) a number of Port 4 pins may output the segment address lines. The number of pins used for segment address output determines the directly accessible external address space. The other pins of Port 4 may be used for general purpose I/O. If segment address lines are selected, the alternate function of Port 4 may be necessary to access e.g. external memory directly after reset. For this reason Port 4 will be switched to this alternate function automatically. The number of segment address lines is selected via PORT0 during reset. The selected value can be read from bitfield SALSEL in register RP0H (read only) to check the configuration during run time. 116/239 Doc ID 8673 Rev. 3 ST10F280 Parallel ports Devices with CAN interfaces use 2 pins of Port 4 to interface each CAN Module to an external CAN transceiver. In this case the number of possible segment address lines is reduced. The table below summarizes the alternate functions of Port 4 depending on the number of selected segment address lines (coded via bitfield SALSEL). . Table 20. Port 4 pin Port 4 alternate functions Std. Function SALSEL=01 64 KB GPIO GPIO GPIO GPIO GPIO/CAN2_RxD GPIO/CAN1_RxD GPIO/CAN1_TxD GPIO/CAN2_TxD P4.0 P4.1 P4.2 P4.3 P4.4 P4.5 P4.6 P4.7 Altern. Function SALSEL=11 256KB Altern. Function SALSEL=00 1MB Seg. Address A16 Seg. Address A17 Seg. Address A18 Seg. Address A19 GPIO/CAN2_RxD GPIO/CAN1_RxD GPIO/CAN1_TxD GPIO/CAN2_TxD Seg. Address A16 Seg. Address A17 GPIO GPIO GPIO/CAN2_RxD GPIO/CAN1_RxD GPIO/CAN1_TxD GPIO/CAN2_TxD Altern. Function SALSEL=10 16MB Seg. Address A16 Seg. Address A17 Seg. Address A18 Seg. Address A19 Seg. Address A20 Seg. Address A21 Seg. Address A22 Seg. Address A23 Figure 38. Port 4 I/O and alternate functions $OWHUQDWH)XQFWLRQ 3RUW 3 3 3 3 3 3 3 3 *HQHUDO3XUSRVH ,QSXW2XWSXW E D $ $ $ $ $ $ $ $ 6HJPHQW$GGUHVV /LQHV &$1B7[' &$1B7[' &$1B5[' &$1B5[' S 3 3 3 &DQV,2DQG*HQHUDO3XUSRVH ,QSXW2XWSXW ("1($'5 Doc ID 8673 Rev. 3 117/239 Parallel ports ST10F280 Figure 39. Block diagram of a Port 4 pin :ULWH'3\ 08; 'LUHFWLRQ /DWFK 5HDG'3\ ,QWHUQDO%XV $OWHUQDWH )XQFWLRQ (QDEOH :ULWH3\ $OWHUQDWH 'DWD 2XWSXW 3RUW2XWSXW /DWFK 3\ 08; 2XWSXW %XIIHU 5HDG3\ &38&ORFN 08; ,QSXW /DWFK \ ("1($'5 118/239 Doc ID 8673 Rev. 3 ST10F280 Parallel ports Figure 40. Block diagram of P4.4 and P4.5 pins :ULWH'3[ 08; 'LUHFWLRQ /DWFK 08; 5HDG'3[ ,QWHUQDO%XV $OWHUQDWH )XQFWLRQ (QDEOH :ULWH3[ 08; $OWHUQDWH 'DWD 2XWSXW 3RUW2XWSXW /DWFK 3[ 08; 2XWSXW %XIIHU 5HDG3[ &ORFN 08; ,QSXW /DWFK &$1\5[' ;3(5&21D &$1\(1 ;3(5&21E &$1](1 d [ \ ] D E &$1&KDQQHO ("1($'5 Doc ID 8673 Rev. 3 119/239 Parallel ports ST10F280 Figure 41. Block diagram of P4.6 and P4.7 pins :ULWH2'3[ 2SHQ'UDLQ /DWFK 08; 5HDG2'3[ :ULWH'3[ 08; 08; ,QWHUQDO%XV 'LUHFWLRQ /DWFK 5HDG'3[ :ULWH3[ 08; $OWHUQDWH )XQFWLRQ (QDEOH $OWHUQDWH 'DWD 2XWSXW 3RUW2XWSXW /DWFK 08; 5HDG3[ 08; 2XWSXW %XIIHU 3[ &ORFN 08; ,QSXW /DWFK &$1\7[' 'DWDRXWSXW ;3(5&21D &$1\(1 ;3(5&21E &$1](1 [ \ ] D E d &$1&KDQQHO ("1($'5 12.7 Port 5 This 16-bit input port can only read data. There is no output latch and no direction register. Data written to P5 will be lost. 120/239 Doc ID 8673 Rev. 3 ST10F280 Parallel ports P5 15 P5.15 R 14 13 12 11 P5.14 P5.13 P5.12 R R R 10 P5.11 P5.10 R Address: 0xFFA2h / D1h SFR Reset: 0xXXXXh Type: R 9 8 7 6 5 4 3 2 1 0 P5.9 P5.8 P5.7 P5.6 P5.5 P5.4 P5.3 P5.2 P5.1 P5.0 R R R R R R R R R R R P5.y Port data register P5 bit y (Read only) 12.7.1 Alternate functions of Port 5 Each line of Port 5 is also connected to one of the multiplexer of the Analog/Digital Converter. All port lines (P5.15...P5.0) can accept analog signals (AN15...AN0) that can be converted by the ADC. No special programming is required for pins that shall be used as analog inputs. Some pins of Port 5 also serve as external timer control lines for GPT1 and GPT2. The table below summarizes the alternate functions of Port 5. Table 21. Port 5 pin P5.0 P5.1 P5.2 P5.3 P5.4 P5.5 P5.6 P5.7 P5.8 P5.9 P5.10 P5.11 P5.12 P5.13 P5.14 P5.15 Port 5 alternate functions Alternate function a) Alternate function b) T6EUD Timer 6 ext. Up/Down Input T5EUD Timer 5 ext. Up/Down Input T6IN Timer 6 Count Input T5IN Timer 5 Count Input T4EUD Timer 4 ext. Up/Down Input T2EUD Timer 2 ext. Up/Down Input Analog Input AN0 Analog Input AN1 Analog Input AN2 Analog Input AN3 Analog Input AN4 Analog Input AN5 Analog Input AN6 Analog Input AN7 Analog Input AN8 Analog Input AN9 Analog Input AN10 Analog Input AN11 Analog Input AN12 Analog Input AN13 Analog Input AN14 Analog Input AN15 Doc ID 8673 Rev. 3 121/239 Parallel ports ST10F280 Figure 42. Port 5 I/O and alternate functions $OWHUQDWH)XQFWLRQ D 3 3 3 3 3 3 3 3 3 3 3 3 3 3 3 3 3RUW E 7(8' 7(8' 7,1 7,1 7(8' 7(8' $1 $1 $1 $1 $1 $1 $1 $1 $1 $1 $1 $1 $1 $1 $1 $1 $'&RQYHUWHU,QSXWV *HQHUDO3XUSRVH,QSXWV 7LPHU,QSXWV ("1($'5 Port 5 pins have a special port structure (see Figure 43), first because it is an input only port, and second because the analog input channels are directly connected to the pins rather than to the input latches. Figure 43. Block diagram of a Port 5 pin ,QWHUQDO%XV &KDQQHO 6HOHFW $QDORJ 6ZLWFK WR6DPSOH+ROG &LUFXLW 5HDG3RUW3\ 5HDG %XIIHU 3\$1\ &38&ORFN ,QSXW /DWFK \ ("1($'5 122/239 Doc ID 8673 Rev. 3 ST10F280 Parallel ports Port 5 Schmitt trigger analog inputs A Schmitt trigger protection can be activated on each pin of Port 5 by setting the dedicated bit of register P5DIDIS. P5DIDIS P5DIDIS.0 0 P5DIDIS.1 1 P5DIDIS.2 2 P5DIDIS.3 3 P5DIDIS.4 4 P5DIDIS.5 5 P5DIDIS.6 6 P5DIDIS.7 7 P5DIDIS.8 8 P5DIDIS.9 9 P5DIDIS.10 10 P5DIDIS.11 11 P5DIDIS.12 12 P5DIDIS.13 13 P5DIDIS.14 14 P5DIDIS.15 15 R/W R/W R/W R/W R/W R/W R/W R/W R/W R/W R/W R/W R/W R/W R/W R/W Address: 0xFFA4h / D2h SFR Reset: 0x0000h Type: R/W P5DIDIS.y Port 5 Digital Disablel register bit y P5DIDIS.y = 0: Port line P5.y digital input is enabled (Schmitt trigger enabled) P5DIDIS.y = 1: Port line P5.y digital input is disabled (Schmitt trigger disabled, necessary for input leakage current reduction) Doc ID 8673 Rev. 3 123/239 Parallel ports 12.8 ST10F280 Port 6 If this 8-bit port is used for general purpose I/O, the direction of each line can be configured via the corresponding direction register DP6. Each port line can be switched into push/pull or open drain mode via the open drain control register ODP6. P6 (FFCCh / E6h) 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0 - - - - - - - - P6.7 P6.6 P6.5 P6.4 P6.3 P6.2 P6.1 P6.0 R/W R/W R/W R/W R/W R/W R/W R/W 7 6 5 4 3 2 1 0 Address: 0xFFCCh / E6h SFR Reset: 0x--00h Type: R/W P6.y Port data register P6 bit y DP6 15 14 13 12 11 10 9 8 - - - - - - - - DP6.7 DP6.6 DP6.5 DP6.4 DP6.3 DP6.2 DP6.1 DP6.0 R/W Address: 0xFFCEh / E7h SFR Reset: 0x--00h Type: R/W R/W R/W R/W R/W R/W R/W R/W DP6.y Port direction register DP6 bit y DP6.y = 0: Port line P6.y is an input (high-impedance) DP6.y = 1: Port line P6.y is an output ODP6 - - - - - - - - Address: 0xF1CEh / E7h ESFR Reset: 0x--00h Type: R/W 7 6 5 4 3 1 0 R/W R/W R/W R/W R/W R/W R/W R/W ODP6.y Port 6 Open Drain control register bit y ODP6.y = 0: Port line P6.y output driver in push/pull mode ODP6.y = 1: Port line P6.y output driver in open drain mode 124/239 2 ODP6.0 8 ODP6.1 9 ODP6.2 10 ODP6.3 11 ODP6.4 12 ODP6.5 13 ODP6.6 14 ODP6.7 15 Doc ID 8673 Rev. 3 ST10F280 12.8.1 Parallel ports Alternate functions of Port 6 A programmable number of chip select signals (CS4...CS0) derived from the bus control registers (BUSCON4...BUSCON0) can be output on the 5 pins of Port 6. The number of chip select signals is selected via PORT0 during reset. The selected value can be read from bitfield CSSEL in register RP0H (read only) e.g. in order to check the configuration during run time. The table below summarizes the alternate functions of Port 6 depending on the number of selected chip select lines (coded via bitfield CSSEL). Table 22. Port 6 Pin Port 6 alternate functions Altern. Function CSSEL = 10 Altern. Function CSSEL = 01 P6.0 P6.1 P6.2 P6.3 P6.4 General purpose I/O General purpose I/O General purpose I/O General purpose I/O General purpose I/O Chip select CS0 Chip select CS1 Gen. purpose I/O Gen. purpose I/O Gen. purpose I/O P6.5 P6.6 P6.7 HOLD External hold request input HLDA Hold acknowledge output BREQ Bus request output Altern. Function CSSEL = 00 Chip select CS0 Chip select CS1 Chip select CS2 Gen. purpose I/O Gen. purpose I/O Altern. Function CSSEL = 11 Chip select Chip select Chip select Chip select Chip select CS0 CS1 CS2 CS3 CS4 Figure 44. Port 6 I/O and alternate functions $OWHUQDWH)XQFWLRQ 3RUW 3 3 3 3 3 3 3 3 D %5(4 +/'$ +2/' &6 &6 &6 &6 &6 *HQHUDO3XUSRVH,QSXW2XWSXW ("1($'5 The chip select lines of Port 6 have an internal weak pull-up device. This device is switched on during reset. This feature is implemented to drive the chip select lines high during reset in order to avoid multiple chip selection. After reset the CS function must be used, if selected so. In this case there is no possibility to program any port latches before. Thus the alternate function (CS) is selected automatically in this case. Note: The open drain output option can only be selected via software earliest during the initialization routine; at least signal CS0 will be in push/pull output driver mode directly after reset. Doc ID 8673 Rev. 3 125/239 Parallel ports ST10F280 Figure 45. Block diagram of Port 6 pins with an alternate output function :ULWH2'3\ 2SHQ'UDLQ /DWFK 08; 5HDG2'3\ :ULWH'3\ 08; ,QWHUQDO%XV 'LUHFWLRQ /DWFK 5HDG'3\ $OWHUQDWH )XQFWLRQ (QDEOH :ULWH3\ $OWHUQDWH 'DWD 2XWSXW 3RUW2XWSXW /DWFK 08; 2XWSXW %XIIHU 3\ 5HDG3\ &38&ORFN 08; ,QSXW /DWFK \ ("1($'5 Note: 126/239 * P6.5 has only alternate input function. Doc ID 8673 Rev. 3 ST10F280 12.9 Parallel ports Port 7 If this 8-bit port is used for general purpose I/O, the direction of each line can be configured via the corresponding direction register DP7. Each port line can be switched into push/pull or open drain mode via the open drain control register ODP7. P7 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0 - - - - - - - - P7.7 P7.6 P7.5 P7.4 P7.3 P7.2 P7.1 P7.0 R/W R/W R/W R/W R/W R/W R/W R/W 7 6 5 4 3 2 1 0 Address: 0xFFD0h / E8h SFR Reset: 0x--00h Type: R/W P7.y Port data register P7 bit y DP7 15 14 13 12 11 10 9 8 - - - - - - - - DP7.7 DP7.6 DP7.5 DP7.4 DP7.3 DP7.2 DP7.1 DP7.0 R/W Address: 0xFFD2h / E9h SFR Reset: 0x--00h Type: R/W R/W R/W R/W R/W R/W R/W R/W DP7.y Port direction register DP7 bit y DP7.y = 0: Port line P7.y is an input (high impedance) DP7.y = 1: Port line P7.y is an output Doc ID 8673 Rev. 3 127/239 Parallel ports ST10F280 ODP7 15 14 13 12 11 10 9 8 - - - - - - - - 7 R/W Address: 0xF1D2h / E9h ESFR Reset: 0x--00h Type: R/W 6 5 4 3 2 1 0 ODP7.7 ODP7.6 ODP7.5 ODP7.4 ODP7.3 ODP7.2 ODP7.1 ODP7.0 R/W R/W R/W R/W R/W R/W R/W ODP7.y Port 7 Open Drain control register bit y ODP7.y = 0: Port line P7.y output driver in push-pull mode ODP7.y = 1: Port line P7.y output driver in open drain mode 12.9.1 Alternate functions of Port 7 The upper 4 lines of Port 7 (P7.7...P7.4) serve as capture inputs or compare outputs (CC31IO...CC28IO) for the CAPCOM2 unit. The usage of the port lines by the CAPCOM unit, its accessibility via software and the precautions are the same as described for the Port 2 lines. As all other capture inputs, the capture input function of pins P7.7...P7.4 can also be used as external interrupt inputs (200 ns sample rate at 40MHz CPU clock). The lower 4 lines of Port 7 (P7.3...P7.0) serve as outputs from the PWM module (POUT3...POUT0). At these pins the value of the respective port output latch is XORed with the value of the PWM output rather than ANDed, as the other pins do. This allows to use the alternate output value either as it is (port latch holds a `0') or invert its level at the pin (port latch holds a `1'). Note that the PWM outputs must be enabled via the respective PENx bits in PWMCON1. The table below summarizes the alternate functions of Port 7. Table 23. Port 7 pin P7.0 P7.1 P7.2 P7.3 P7.4 P7.5 P7.6 P7.7 128/239 Port 7 alternate functions Alternate function POUT0 PWM mode channel 0 output POUT1 PWM mode channel 1 output POUT2 PWM mode channel 2 output POUT3 PWM mode channel 3 output CC28IO Capture input / compare output channel 28 CC29IO Capture input / compare output channel 29 CC30IO Capture input / compare output channel 30 CC31IO Capture input / compare output channel 31 Doc ID 8673 Rev. 3 ST10F280 Parallel ports Figure 46. Port 7 I/O and alternate functions 3RUW 3 3 3 3 3 3 3 3 &&,2 &&,2 &&,2 &&,2 3287 3287 3287 3287 $OWHUQDWH)XQFWLRQ *HQHUDO3XUSRVH,QSXW2XWSXW ("1($'5 The port structures of Port 7 differ in the way the output latches are connected to the internal bus and to the pin driver (see the two Figure 47). Pins P7.3...P7.0 (POUT3...POUT0) XOR the alternate data output with the port latch output, which allows to use the alternate data directly or inverted at the pin driver. Figure 47. Block diagram of Port 7 pins P7.3...P7.0 :ULWH2'3\ 2SHQ'UDLQ /DWFK 5HDG2'3\ ,QWHUQDO%XV :ULWH'3\ 'LUHFWLRQ /DWFK 5HDG'3\ $OWHUQDWH 'DWD 2XWSXW :ULWH3\ 3RUW2XWSXW /DWFK 3RUW'DWD 2XWSXW 2XWSXW %XIIHU (;25 3\3287\ 5HDG3\ &38&ORFN 08; ,QSXW /DWFK \ ("1($'5 Doc ID 8673 Rev. 3 129/239 Parallel ports ST10F280 Figure 48. Block diagram of Port 7 pins P7.7...P7.4 :ULWH2'3\ 2SHQ'UDLQ /DWFK 5HDG2'3\ :ULWH'3\ ,QWHUQDO%XV 'LUHFWLRQ /DWFK 5HDG'3\ $OWHUQDWH 'DWD 2XWSXW 2XWSXW /DWFK 08; 2XWSXW %XIIHU 3\ &&],2 :ULWH3RUW3\ &RPSDUH7ULJJHU t 5HDG3\ &ORFN 08; ,QSXW /DWFK $OWHUQDWH/DWFK 'DWD,QSXW $OWHUQDWH3LQ 'DWD,QSXW \ ] ("1($'5 130/239 Doc ID 8673 Rev. 3 ST10F280 12.10 Parallel ports Port 8 If this 8-bit port is used for general purpose I/O, the direction of each line can be configured via the corresponding direction register DP8. Each port line can be switched into push/pull or open drain mode via the open drain control register ODP8. P8 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0 - - - - - - - - P8.7 P8.6 P8.5 P8.4 P8.3 P8.2 P8.1 P8.0 R/W R/W R/W R/W R/W R/W R/W R/W 7 6 5 4 3 2 1 0 Address: 0xFFD40h / EAh SFR Reset: 0x--00h Type: R/W P8.y Port data register P8 bit y DP8 15 14 13 12 11 10 9 8 - - - - - - - - DP8.7 DP8.6 DP8.5 DP8.4 DP8.3 DP8.2 DP8.1 DP8.0 R/W Address: 0xFFD6h / EBh SFR Reset: 0x--00h Type: R/W R/W R/W R/W R/W R/W R/W R/W DP8.y Port direction register DP8 bit y DP8.y = 0: Port line P8.y is an input (high impedance) DP8.y = 1: Port line P8.y is an output ODP8 15 14 13 12 11 10 9 8 - - - - - - - - 7 0xF1D6h / EBh ESFR Reset: 0x--00h Type: R/W 5 4 3 2 1 0 ODP8.7 ODP8.6 ODP8.5 ODP8.4 ODP8.3 ODP8.2 ODP8.1 ODP8.0 R/W Address: 6 R/W R/W R/W R/W R/W R/W R/W ODP8.y Port 8 Open Drain control register bit y ODP8.y = 0: Port line P8.y output driver in push-pull mode ODP8.y = 1: Port line P8.y output driver in open drain mode Doc ID 8673 Rev. 3 131/239 Parallel ports 12.10.1 ST10F280 Alternate functions of Port 8 The 8 lines of Port 8 (P8.7...P8.0) serve as capture inputs or compare outputs (CC23IO...CC16IO) for the CAPCOM2 unit. The usage of the port lines by the CAPCOM unit, its accessibility via software and the precautions are the same as described for the Port 2 lines. As all other capture inputs, the capture input function of pins P8.7...P8.0 can also be used as external interrupt inputs (200 ns sample rate at 40MHz CPU clock). The Table 24 summarizes the alternate functions of Port 8. Table 24. Port 8 alternate functions Port 7 P8.0 P8.1 P8.2 P8.3 P8.4 P8.5 P8.6 P8.7 Alternate function CC16IO Capture input / compare output channel 16 CC17IO Capture input / compare output channel 17 CC18IO Capture input / compare output channel 18 CC19IO Capture input / compare output channel 19 CC20IO Capture input / compare output channel 20 CC21IO Capture input / compare output channel 21 CC22IO Capture input / compare output channel 22 CC23IO Capture input / compare output channel 23 Figure 49. Port 8 I/O and alternate functions 3RUW 3 3 3 3 3 3 3 3 *HQHUDO3XUSRVH,QSXW2XWSXW &&,2 &&,2 &&,2 &&,2 &&,2 &&,2 &&,2 &&,2 $OWHUQDWH)XQFWLRQ ("1($'5 The port structures of Port 8 differ in the way the output latches are connected to the internal bus and to the pin driver (see the Figure 50). Pins P8.7...P8.0 (CC23IO...CC16IO) combine internal bus data and alternate data output before the port latch input, as do the Port 2 pins. 132/239 Doc ID 8673 Rev. 3 ST10F280 Parallel ports Figure 50. Block diagram of Port 8 pins P8.7...P8.0 :ULWH'3\ 2SHQ'UDLQ /DWFK 5HDG'3\ :ULWH'3\ ,QWHUQDO%XV 'LUHFWLRQ /DWFK 5HDG'3\ $OWHUQDWH 'DWD 2XWSXW 2XWSXW /DWFK 08; 2XWSXW %XIIHU 3\ &&],2 :ULWH3RUW3\ &RPSDUH7ULJJHU t 5HDG3\ &38&ORFN 08; ,QSXW /DWFK $OWHUQDWH/DWFK 'DWD,QSXW $OWHUQDWH3LQ'DWD,QSXW \ ] ("1($'5 Doc ID 8673 Rev. 3 133/239 Parallel ports 12.11 ST10F280 XPort 9 The XPort9 is enabled by setting XPEN bit 2 of the SYSCON register and XPORT9EN bit 3 of the new XPERCON register. On the XBUS interface, the register are not bit-addressable This 16-bit port is used for general purpose I/O, the direction of each line can be configured via the corresponding direction register XDP9. Each port line can be switched into push/pull or open drain mode via the open drain control register XODP9. All port lines can be individually (bit-wise) programmed. The "bit-addressable" feature is available via specific "Set" and "Clear" registers: XP9SET, XP9CLR, XDP9SET, XDP9CLR, XODP9SET, XODP9CLR. XP9 XP9.0 0 XP9.1 1 XP9.2 2 XP9.3 3 XP9.4 4 XP9.5 5 XP9.6 6 XP9.7 7 XP9.8 8 XP9.9 9 XP9.10 10 XP9.11 11 XP9.12 12 XP9.13 13 XP9.14 14 XP9.15 15 R/W R/W R/W R/W R/W R/W R/W R/W R/W R/W R/W R/W R/W R/W R/W R/W Address: 0xC100h Reset: 0x0000h Type: R/W XP9.y Port data register XP9 bit y XP9SET (C102h) XP9SET.0 0 XP9SET.1 1 XP9SET.2 2 XP9SET.3 3 XP9SET.4 4 XP9SET.5 5 XP9SET.6 6 XP9SET.7 7 XP9SET.8 8 XP9SET.9 9 XP9SET.10 10 XP9SET.11 11 XP9SET.12 12 XP9SET.13 13 XP9SET.14 14 XP9SET.15 15 W W W W W W W W W W W W W W W W Address: 0xC102h Reset: 0x0000h Type: W XP9SET.y Writing a `1' will set the corresponding bit in XP9 register, Writing a `0' has no effect. 134/239 Doc ID 8673 Rev. 3 ST10F280 Parallel ports XP9CLR XP9CLR.0 0 XP9CLR.1 1 XP9CLR.2 2 XP9CLR.3 3 XP9CLR.4 4 XP9CLR.5 5 XP9CLR.6 6 XP9CLR.7 7 XP9CLR.8 8 XP9CLR.9 9 XP9CLR.10 10 XP9CLR.11 11 XP9CLR.12 12 XP9CLR.13 13 XP9CLR.14 14 XP9CLR.15 15 W W W W W W W W W W W W W W W W Address: 0xC104h Reset: 0x0000h Type: W XP9CLR.y Writing a `1' will clear the corresponding bit in XP9 register, Writing a `0' has no effect. XDP9 XDP9.0 0 XDP9.1 1 XDP9.2 2 XDP9.3 3 XDP9.4 4 XDP9.5 5 XDP9.6 6 XDP9.7 7 XDP9.8 8 XDP9.9 9 XDP9.10 10 XDP9.11 11 XDP9.12 12 XDP9.13 13 XDP9.14 14 XDP9.15 15 R/W R/W R/W R/W R/W R/W R/W R/W R/W R/W R/W R/W R/W R/W R/W R/W Address: 0xC200h Reset: 0x0000h Type: R/W XDP9.y Port direction register XDP9 bit y XDP9.y = 0: Port line XP9.y is an input (high-impedance) XDP9.y = 1: Port lineX P9.y is an output XDP9SET XDP9 SET.0 0 XDP9 SET.1 1 XDP9 SET.2 2 XDP9 SET.3 3 XDP9 SET.4 4 XDP9 SET.5 5 XDP9 SET.6 6 XDP9 SET.7 7 XDP9 SET.8 8 XDP9 SET.9 9 XDP9 SET.10 10 XDP9 SET.11 11 XDP9 SET.12 12 XDP9 SET.13 13 XDP9 SET.14 14 XDP9 SET.15 15 W W W W W W W W W W W W W W W W Address: 0xC202h Reset: 0x0000h Type: W XDP9SET.y Writing a `1' will set the corresponding bit in XDP9 register, Writing a `0' has no effect. Doc ID 8673 Rev. 3 135/239 Parallel ports ST10F280 XDP9CLR XDP9 CLR.0 0 XDP9 CLR.1 1 XDP9 CLR.2 2 XDP9 CLR.3 3 XDP9 CLR.4 4 XDP9 CLR.5 5 XDP9 CLR.6 6 XDP9 CLR.7 7 XDP9 CLR.8 8 XDP9 CLR.9 9 XDP9 CLR.10 10 XDP9 CLR.11 11 XDP9 CLR.12 12 XDP9 CLR.13 13 XDP9 CLR.14 14 XDP9 CLR.15 15 W W W W W W W W W W W W W W W W Address: 0xC204h Reset: 0x0000h Type: W XDP9CLR.y Writing a `1' will clear the corresponding bit in XDP9 register, Writing a `0' has no effect. XODP9 XODP9 .1 XODP9 .0 0 XODP 9.2 1 R/W R/W R/W R/W R/W R/W R/W R/W R/W R/W R/W R/W R/W R/W R/W R/W Address: 0xC300h Reset: 0x0000h Type: R/W XODP9.y Port 9 Open Drain control register bit y XODP9.y = 0: Port line XP9.y output driver in push/pull mode XODP9.y = 1: Port line XP9.y output driver in open drain mode 136/239 2 XODP9 .3 3 XODP9 .4 4 XODP9 .5 5 XODP9 .6 6 XODP9 .7 7 XODP9 .8 8 XODP9 .9 9 XODP9 .10 10 XODP9 .11 11 XODP9 .12 12 XODP9 .13 13 XODP9 .14 14 XODP9 .15 15 Doc ID 8673 Rev. 3 ST10F280 Parallel ports XODP9SET (C302h) XODP9SET.0 0 XODP9SET.1 1 XODP9SET.2 2 XODP9SET.3 3 XODP9SET.4 4 XODP9SET.5 5 XODP9SET.6 6 XODP9SET.7 7 XODP9SET.8 8 XODP9SET.9 9 XODP9SET.10 10 XODP9SET.11 11 XODP9SET.12 12 XODP9SET.13 13 XODP9SET.14 14 XODP9SET.15 15 W W W W W W W W W W W W W W W W Address: 0xC302h Reset: 0x0000h Type: W XODP9SET.y Writing a `1' will set the corresponding bit in XODP9 register, Writing a `0' has no effect. XODP9CLR XODP9CLR.0 0 XODP9CLR.1 1 XODP9CLR.2 2 XODP9CLR.3 3 XODP9CLR.4 4 XODP9CLR.5 5 XODP9CLR.6 6 XODP9CLR.7 7 XODP9CLR.8 8 XODP9CLR.9 9 XODP9CLR.10 10 XODP9CLR.11 11 XODP9CLR.12 12 XODP9CLR.13 13 XODP9CLR.14 14 XODP9CLR.15 15 W W W W W W W W W W W W W W W W Address: 0xC304h Reset: 0x0000h Type: W XODP9CLR.y Writing a `1' will clear the corresponding bit in XODP9 register, Writing a `0' has no effect. Doc ID 8673 Rev. 3 137/239 Parallel ports 12.12 ST10F280 XPort 10 The XPort10 is enabled by setting XPEN bit 2 of the SYSCON register and bit 3 of the new XPERCON register. On the XBUS interface, the register are not bit-addressable. This 16-bit input port can only read data. There is no output latch and no direction register. Data written to XP10 will be lost. 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0 XP10 .15 XP10 .14 XP10 .13 XP10 .12 XP10 .11 XP10 .10 XP10 .9 XP10 .8 XP10 .7 XP10 .6 XP10 .5 XP10 .4 XP10 .3 XP10 .2 XP10 .1 XP10 .0 XP10 R R R R R R R R R R R R R R R R Address: 0xC380h Reset: 0xXXXXh Type: R XP10.y Port data register XP10 bit y (Read only) 12.12.1 Alternate functions of XPort 10 Each line of XPort 10 is also connected to one of the multiplexer of the Analog/Digital Converter. All port lines (XP10.15...XP10.0) can accept analog signals (AN31...AN16) that can be converted by the ADC. No special programming is required for pins that shall be used as analog inputs. The Table 25 summarizes the alternate functions of XPort 10. Table 25. 138/239 XPort 10 alternate functions XPort 10 Pin Alternate function P10.0 P10.1 P10.2 P10.3 P10.4 P10.5 P10.6 P10.7 P10.8 P10.9 P10.10 P10.11 P10.12 P10.13 P10.14 P10.15 Analog Input AN16 Analog Input AN17 Analog Input AN18 Analog Input AN19 Analog Input AN20 Analog Input AN21 Analog Input AN22 Analog Input AN23 Analog Input AN24 Analog Input AN25 Analog Input AN26 Analog Input AN27 Analog Input AN28 Analog Input AN29 Analog Input AN30 Analog Input AN31 Doc ID 8673 Rev. 3 ST10F280 Parallel ports Figure 51. PORT10 I/O and alternate functions ;3 ;3 ;3 ;3 ;3 ;3 ;3 ;3 ;3 ;3 ;3 ;3 ;3 ;3 ;3 ;3 ;3RUW $1 $1 $1 $1 $1 $1 $1 $1 $1 $1 $1 $1 $1 $1 $1 $1 $OWHUQDWH)XQFWLRQ $'&RQYHUWHU,QSXW *HQHUDO3XUSRVH,QSXW ("1($'5 12.12.2 New disturb protection on analog inputs A new register is provided for additional disturb protection support on analog inputs for Port XP10: XP10DIDIS Address: 0xC382h Reset: 0x0000h Type: R/W 0 XP10DIDIS.0 1 XP10DIDIS.1 2 XP10DIDIS.2 3 XP10DIDIS.3 4 XP10DIDIS.4 5 XP10DIDIS.5 6 XP10DIDIS.6 7 XP10DIDIS.7 8 XP10DIDIS.8 R/W 9 XP10DIDIS.9 R/W 10 XP10DIDIS .10 R/W 11 XP10DIDIS .11 R/W 12 XP10DIDIS .12 XP10DIDIS .13 13 XP10DIDIS .14 14 XP10DIDIS .15 15 R/W R/W R/W R/W R/W R/W R/W R/W R/W R/W R/W R/W XP10DIDIS.y XPort 10 Digital Disable register bit y 0: Port line XP10.y digital input is enabled (Schmitt trigger enabled) 1: Port line XP10.y digital input is disabled (Schmitt trigger disabled, necessary for input leakage current reduction) Doc ID 8673 Rev. 3 139/239 A/D converter ST10F280 13 A/D converter 13.1 A/D converter module A 10-bit A/D converter with 2 x 16 multiplexed input channels and a sample and hold circuit is integrated on-chip. This A/D Converter does not have the self-calibration feature. Thus, guaranteed Total Unadjusted Error is + 2 LSB. Refer to Section 20.3.1: A/D converter characteristics for detailled characteristics. The sample time (for loading the capacitors) and the conversion time is programmable and can be adjusted to the external circuitry. Convertion time is fully equivalent to the one of previous generation A/D self-calibrated Converter. To remove high frequency components from the analog input signal, a low-pass filter must be connected at the ADC input. Overrun error detection/protection is controlled by the ADDAT register. Either an interrupt request is generated when the result of a previous conversion has not been read from the result register at the time the next conversion is complete, or the next conversion is suspended until the previous result has been read. For applications which require less than 16 analog input channels, the remaining channel inputs can be used as digital input port pins. The A/D converter of the ST10F280 supports four different conversion modes: Single channel conversion mode the analog level on a specified channel is sampled once and converted to a digital result. Single channel continuous mode the analog level on a specified channel is repeatedly sampled and converted without software intervention. Auto scan mode the analog levels on a pre-specified number of channels are sequentially sampled and converted. Auto scan continuous mode the number of pre-specified channels is repeatedly sampled and converted. Channel Injection Mode injects a channel into a running sequence without disturbing this sequence. The peripheral event controller stores the conversion results in memory without entering and exiting interrupt routines for each data transfer. 13.2 Multiplexage of two blocks of 16 analog Inputs The ADC can manage 16 analog inputs, so to increase its capability, a new XADCMUX register is added to control the multiplexage between the first block of 16 channels on Port5 and the second block of 16 channels on XPort10. The conversion result register stays identical and only a software management can determine the block in use. 140/239 Doc ID 8673 Rev. 3 ST10F280 A/D converter Figure 52. Block diagram &38FORFN 5HDG3RUW3\ ,QSXW ODWFK ,QWHUQDO%XV &38FORFN 5HDG3RUW;3\ ,QSXW ODWFK ;%86 3\ $'& ;3\ &KDQQHO6HOHFW \ ;$'&08; ("1($'5 The XADCMUX register is enabled by setting XPEN bit 2 of the SYSCON register and bit 3 of the new XPERCON register XADCMUX 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0 - - - - - - - - - - - - - - - XADCMUX R/W Address: 0xC384h Reset: 0x0000h Type: R/W XADCMUX.0 0: Default configuration,analog inputs on port P5.y can be converted 1: Analog inputs on port XP10.y can be converted 13.3 XTIMER peripheral (trigger for ADC channel injection) This new peripheral is dedicated for the Channel Injection Mode of the A/D converter. This mode injects a channel into a running sequence without disturbing this sequence. The peripheral event controller stores the conversion results in memory without entering and exiting interrupt routines for each data transfer. A channel injection can be triggered by an event on Capture/Compare CC31 (Port P7.7) of the CAPCOM2 unit. The dedicated output XADCINJ of the XTIMER must be connected externally on the input P7.7/CC31. Doc ID 8673 Rev. 3 141/239 A/D converter ST10F280 Due to the multiplexed inputs, at a time, the ADC exclusively converts the Port5 inputs or the XPort10 inputs. If one "y" channel has to be used continuously in injection mode, it must be externally hardware connected to the Port5.y and XPort10.y inputs. The XTIMER peripheral is enabled by setting XPEN bit 2 of the SYSCON register and bit 3 of the new XPERCON register. 13.3.1 Main features The XTIMER features are : 16 bits linear timer / 4 bits exponential prescaler Counting between 16 bits "start value" and 16 bits "end value" Counting period between 4 cycles and 2**33 cycles (100 ns and 214s using 40MHz CPU clock) 1 trigger ouput (XADCINJ) Programmable functions : - Internal clock XCLK is derivated from the CPU clock and has the same period - Up counting / down counting - Reload enable - Continue / stop modes 4 memory mapped registers : - Control / prescaler - Start value - End value - Current value Table 26. The different counting Modes TLE TCS TCVR(n) = TEVR x x x TUD TEN x 0 TCVR(n+1) comments Timer disable TCVR(n) x 0 1 x x 0 x Stop Decrement 0 0 1 TCVR(n)-1 1 Decrement (Continue) 1 x x 0 Increment 1 142/239 0 1 1 1 1 1 TCVR(n)+1 Increment (Continue) x TSVR Doc ID 8673 Rev. 3 Load ST10F280 13.3.2 A/D converter Register description TCR: Timer Control Register XTCR 15 14 13 12 11 10 5 4 3 2 1 0 0 0 0 0 0 0 TFP[3:0] TCM TIE TCS TLE TUD TEN R R R R R R RW RW RW RW RW RW RW Address: 0xC000h Reset: 0x0000h Type: R, R/W 9 8 7 6 TEN Timer Enable When TEN = '0', the Timer is disabled (reset value). To avoid glitches, it is recommended to modify TCR in 2 steps, first with new values and and second by setting TEN. TUD Timer Up / Down Counting When TUD = '0', the Timer is counting "down" (reset value), ie the TCVR ('current value') register content is decremented. When TUD = '1', the Timer is counting "up", ie the TCVR ('current value') register content is incremented. TLE Timer Load Enable When the counter has reached its end value (TCVR = TEVR), TCVR is (re)loaded with TSVR ('start value') register content when TLE = '1'. When TLE = '0' (reset value), the next state of TCVR depends on TCS bit. TCS Timer Continue / Stop When TLE = '0' (no load) and when the counter has reached its end value (TCVR = TEVR), the TCVR content continues to increment / decrement according to TUD bit when TCS = '1' (continue mode). When TCS = '0' (stop mode reset value), TCVR is stopped and its content is frozen. TIE Timer Output Enable When the counter has reached its end value (TCVR = TEVR), the XADCINJ output is set when TIE = '1'. When TIE = '0' (reset value), XADCINJ output is disabled (= '0'). TCM Timer Clock Mode Must be Cleared TCM = '0' (reset value), the TCVR clock is derived from internal XCLK clock according to TFP bits. TFP[3:0] Timer Frequency Prescaler When TCM = '0' (internal clock), the TCVR register clock is derived from the XCLK clock input by dividing XCLK by 2**(2+ TFP). The coding is as follows : 0000 : prescaler by 2 (reset value), XCLK divided by 4 0001 : prescaler by 4, XCLK divided by 8 0010 : prescaler by 8, XCLK divided by 16 ... 1111 : prescaler by 2**16, XCLK divided by 2**17 Doc ID 8673 Rev. 3 143/239 A/D converter ST10F280 XTSVR : Timer Start Value Register 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0 TSVR RW Address: 0xC002h Reset: 0x0000h Type: R/W TSVR[15:0] Timer Start Value TSVR contains the data to be transferred to the TCVR 'Current Value' register when : - TEN = '1' (TIM enable), TLE = '1' (TIM Load enable), TCVR = TEVR (count period finished), TCS = '1' (stop mode disabled). - first counting clock rising edge after the timer start (the timer starts on TEN rising edge). XTEVR : Timer End Value Register 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0 TEVR RW Address: 0xC004h Reset: 0x0000h Type: R/W TEVR[15:0] Timer End Value TEVR contains the data to be compared to the TCVR 'Current Value' register. XTCVR : Timer Current Value Register 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0 TCVR R Address: 0xC006h Reset: 0x0000h Type: R TCVR[15:0] Timer Current Value TCVR contains the current counting value. When TCVR = TEVR, TCVR content is changed according to Table . The TCVR clock is derived from internal XCLK clock according to TFP bits when TCM = '0'. 144/239 Doc ID 8673 Rev. 3 ST10F280 A/D converter Registers mapping Table 27. Timer registers mapping Address (Hexa) 13.3.3 Register Name Reset Value (Hexa) Access C000h XTCR : Control 0000h RW C002h XTSVR : Start Value 0000h RW C004h XTEVR : End Value 0000h RW C006h XTCVR : Current Value 0000h R Block diagram Figure 53. XTIMER block diagram '$7$ ;&/. ;7&5 ;7695 FWO FWO 3UHVFDOLQJ FWO ;7&95 ;7(95 GLII FWO 7LPHURXWSXW ;$'&,1("1($'5 Clocks The XTCVR register clock is the prescaler output. The prescaler allows to divide the basic register frequency in order to offer a wide range of counting period, from 2**2 to 2**33 cycles (note that 1 cycle = 1 XCLK periods). Doc ID 8673 Rev. 3 145/239 A/D converter ST10F280 Registers The XTCVR register input is linked to several sources: XTSVR register (start value) for reload when the period is finished, or for load when the timer is starting. Incrementer output when the 'up' mode is selected, Decrementer output when the 'down' mode is selected. The selection between the sources is made through the XTCR control register. When starting the timer, by setting TEN bit of TCR to '1', XTCVR will be loaded with XTSVR value on the first rising edge of the counting clock. That's to say that for counting from 0000h to 0009h for example, 10 counting clock rising edges are required. The XTCVR register output is continuously compared to the XTEVR register to detect the end of the counting period. When the registers are equal, several actions are made depending on the XTCR control register content : The output XADCINJ is conditionally generated, XTCVR is loaded with XTSVR or stops or continues to count (see Table ). XTEVR, XTSVR and all TCR bits except TEN must not be modified while the timer is counting, ie while TEN bit of TCR = '1'. The timer behaviour is not guaranteed if this rule is not respected. It implies that the timer can be configured only when stopped (TEN = '0'). When programming the timer, XTEVR, XTSVR and XTCR bits except TEN can be modified, with TEN = '0'; then the timer is started by modifying only TEN bit of TCR. To stop the timer, only TEN bit should be modified, from '1' to '0'. Timer output (XADCINJ) The XADCINJ output is the result of the (XTCVR = XTEVR) flag after differentiation. The duration of the output lasts two cycles (50ns at 40MHz). Figure 54. XADCINJ timer output ;&/. ;$'&,1- 7&/ QV ("1($'5 146/239 Doc ID 8673 Rev. 3 ST10F280 A/D converter Figure 55. External connection for ADC channel injection &ORFN 3&& &$3&20 81,7 ,QSXW /DWFK 2XWSXW WULJJHU IRU$'& FKDQQHO LQMHFWLRQ ;7,0(5 ;$'&,1- ("1($'5 Doc ID 8673 Rev. 3 147/239 Serial channels 14 ST10F280 Serial channels Serial communication with other microcontrollers, microprocessors, terminals or external peripheral components is provided by two serial interfaces: the asynchronous / synchronous serial channel (ASCO) and the high-speed synchronous serial channel (SSC). Two dedicated Baud rate generators set up all standard Baud rates without the requirement of oscillator tuning. For transmission, reception and erroneous reception, 3 separate interrupt vectors are provided for each serial channel. 14.1 Asynchronous / Synchronous Serial Interface (ASCO) The asynchronous / synchronous serial interface (ASCO) provides serial communication between the ST10F280 and other microcontrollers, microprocessors or external peripherals. A set of registers is used to configure and to control the ASCO serial interface: 148/239 P3, DP3, ODP3 for pin configuration SOBG for Baud rate generator SOTBUF for transmit buffer SOTIC for transmit interrupt control SOTBIC for transmit buffer interrupt control SOCON for control SORBUF for receive buffer (read only) SORIC for receive interrupt control SOEIC for error interrupt control Doc ID 8673 Rev. 3 ST10F280 14.1.1 Serial channels ASCO in asynchronous mode In asynchronous mode, 8 or 9-bit data transfer, parity generation and the number of stop bit can be selected. Parity framing and overrun error detection is provided to increase the reliability of data transfers. Transmission and reception of data is double-buffered. Fullduplex communication up to 1.25M Bauds (at 40MHz of fCPU) is supported in this mode. Figure 56. Asynchronous mode of serial channel ASC0 5HORDG5HJLVWHU &38 &ORFN %DXG5DWH7LPHU 65 6)( 63( 62( 60 6673 &ORFN 65,5 5HFHLYH,QWHUUXSW 5HTXHVW 6HULDO3RUW&RQWURO 67,5 7UDQVPLW,QWHUUXSW 5HTXHVW 6KLIW&ORFN 6(,5 (UURU,QWHUUXSW 5HTXHVW 65(1 6)(1 63(1 62(1 ,QSXW 5['3 6/% 3LQ 08; 7UDQVPLW6KLIW 5HJLVWHU 5HFHLYH6KLIW 5HJLVWHU 6DPSOLQJ 3LQ 2XWSXW 7['3 5HFHLYH%XIIHU 5HJLVWHU65%8) 7UDQVPLW%XIIHU 5HJLVWHU67%8) ,QWHUQDO%XV ("1($'5 Asynchronous mode baud rates For asynchronous operation, the Baud rate generator provides a clock with 16 times the rate of the established Baud rate. Every received Bit is sampled at the 7th, 8th and 9th cycle of this clock. The Baud rate for asynchronous operation of serial channel ASC0 and the required reload value for a given Baud rate can be determined by the following formulas: fCPU BAsync = 16 x [2 + (S0BRS)] x [(S0BRL) + 1] fCPU S0BRL = ( 16 x [2 + (S0BRS)] x BAsync )1 (S0BRL) represents the content of the reload register, taken as unsigned 13 Bit integer, (S0BRS) represents the value of Bit S0BRS (`0' or `1'), taken as integer. Doc ID 8673 Rev. 3 149/239 Serial channels ST10F280 Using the above equation, the maximum Baud rate can be calculated for any given clock speed. Baud rate versus reload register value (SOBRS=0 and SOBRS=1) is described in Table 28. Table 28. Commonly used baud rates by reload value and deviation errors S0BRS = `0', fCPU = 40MHz Note: 150/239 S0BRS = `1', fCPU = 40MHz Baud rate (Baud) Deviation error Reload value (hexa) Baud rate (Baud) Deviation error Reload value (hexa) 1 250 000 0.0% / 0.0% 0000 / 0000 833 333 0.0% / 0.0% 0000 / 0000 112 000 +1.5% /7.0% 000A / 000B 112 000 +6.3% /7.0% 0006 / 0007 56 000 +1.5% /3.0% 0015 / 0016 56 000 +6.3% /0.8% 000D / 000E 38 400 +1.7% /1.4% 001F / 0020 38 400 +3.3% /1.4% 0014 / 0015 19 200 +0.2% /1.4% 0040 / 0041 19 200 +0.9% /1.4% 002A / 002B 9 600 +0.2% /0.6% 0081 / 0082 9 600 +0.9% /0.2% 0055 / 0056 4 800 +0.2% /0.2% 0103 / 0104 4 800 +0.4% /0.2% 00AC / 00AD 2 400 +0.2% /0.0% 0207 / 0208 2 400 +0.1% /0.2% 015A / 015B 1 200 0.1% / 0.0% 0410 / 0411 1 200 +0.1% /0.1% 02B5 / 02B6 600 0.0% / 0.0% 0822 / 0823 600 +0.1% /0.0% 056B / 056C 300 0.0% / 0.0% 1045 / 1046 300 0.0% / 0.0% 0AD8 / 0AD9 153 0.0% / 0.0% 1FE8 / 1FE9 102 0.0% / 0.0% 1FE8 / 1FE9 The deviation errors given in the Table 28 are rounded. To avoid deviation errors use a Baud rate crystal (providing a multiple of the ASC0/SSC sampling frequency). Doc ID 8673 Rev. 3 ST10F280 14.1.2 Serial channels ASCO in synchronous mode In synchronous mode, data are transmitted or received synchronously to a shift clock which is generated by the ST10F280. Half-duplex communication up to 5M Baud (at 40MHz of fCPU) is possible in this mode. Figure 57. Synchronous mode of serial channel ASC0 5HORDG5HJLVWHU &38 &ORFN 65 60 % 62( &ORFN 65(1 65,5 5HFHLYH,QWHUUXSW 5HTXHVW 67,5 7UDQVPLW,QWHUUXSW 5HTXHVW 6(,5 (UURU,QWHUUXSW 5HTXHVW 62(1 2XWSXW 7'[3 6HULDO3RUW&RQWURO 6/% 3LQ ,QSXW2XWSXW 5['3 %DXG5DWH7LPHU 6KLIW&ORFN 5HFHLYH 3LQ 08; 7UDQVPLW 5HFHLYH6KLIW 5HJLVWHU 7UDQVPLW6KLIW 5HJLVWHU 5HFHLYH%XIIHU 5HJLVWHU65%8) 7UDQVPLW%XIIHU 5HJLVWHU67%8) ,QWHUQDO%XV ("1($'5 Synchronous mode baud rates For synchronous operation, the Baud rate generator provides a clock with 4 times the rate of the established Baud rate. The Baud rate for synchronous operation of serial channel ASC0 can be determined by the following formula: BSync = fCPU 4 x [2 + (S0BRS)] x [(S0BRL) + 1] fCPU S0BRL = ( 4 x [2 + (S0BRS)] x BSync )1 (S0BRL) represents the content of the reload register, taken as unsigned 13 Bit integers, (S0BRS) represents the value of Bit S0BRS (`0' or `1'), taken as integer. Doc ID 8673 Rev. 3 151/239 Serial channels ST10F280 Using the above equation, the maximum Baud rate can be calculated for any clock speed as given in Table 29. Table 29. Commonly used baud rates by reload value and deviation errors S0BRS = `0', fCPU = 40MHz S0BRS = `1', fCPU = 40MHz Baud rate (Baud) Deviation error Reload value (hexa) Baud rate (Baud) Deviation error Reload value (hexa) 5 000 000 0.0% / 0.0% 0000 / 0000 3 333 333 0.0% / 0.0% 0000 / 0000 112 000 +1.5% /0.8% 002B / 002C 112 000 +2.6% /0.8% 001C / 001D 56 000 +0.3% /0.8% 0058 / 0059 56 000 +0.9% /0.8% 003A / 003B 38 400 +0.2% /0.6% 0081 / 0082 38 400 +0.9% /0.2% 0055 / 0056 19 200 +0.2% /0.2% 0103 / 0104 19 200 +0.4% /0.2% 00AC / 00AD 9 600 +0.2% /0.0% 0207 / 0208 9 600 +0.1% /0.2% 015A / 015B 4 800 +0.1% /0.0% 0410 / 0411 4 800 +0.1% /0.1% 02B5 / 02B6 2 400 0.0% / 0.0% 0822 / 0823 2 400 +0.1% /0.0% 056B / 056C 1 200 0.0% / 0.0% 1045 / 1046 1 200 0.0% / 0.0% 0AD8 / 0AD9 900 0.0% / 0.0% 15B2 / 15B3 600 0.0% / 0.0% 15B2 / 15B3 612 0.0% / 0.0% 1FE8 / 1FE9 407 0.0% / 0.0% 1FFD / 1FFE Note: The deviation errors given in the Table 29 are rounded. To avoid deviation errors use a Baud rate crystal (providing a multiple of the ASC0/SSC sampling frequency) 14.2 High speed synchronous serial channel (SSC) The High-Speed Synchronous Serial Interface SSC provides flexible high-speed serial communication between the ST10F280 and other microcontrollers, microprocessors or external peripherals. The SSC supports full-duplex and half-duplex synchronous communication. The serial clock signal can be generated by the SSC itself (master mode) or be received from an external master (slave mode). Data width, shift direction, clock polarity and phase are programmable. This allows communication with SPI-compatible devices. Transmission and reception of data is double-buffered. A 16-bit Baud rate generator provides the SSC with a separate serial clock signal. The serial channel SSC has its own dedicated 16-bit Baud rate generator with 16-bit reload capability, allowing Baud rate generation independent from the timers. 152/239 Doc ID 8673 Rev. 3 ST10F280 Serial channels Figure 58. Synchronous serial channel SSC block diagram &38 &ORFN 6ODYH&ORFN %DXG5DWH*HQHUDWRU 3LQ &ORFN&RQWURO 6KLIW &ORFN 6&/. 0DVWHU&ORFN 5HFHLYH,QWHUUXSW5HTXHVW 66&&RQWURO %ORFN 7UDQVPLW,QWHUUXSW5HTXHVW (UURU,QWHUUXSW5HTXHVW 6WDWXV &RQWURO 3LQ 0765 3LQ 0567 3LQ &RQWURO %LW6KLIW5HJLVWHU 5HFHLYH%XIIHU 5HJLVWHU66&5% 7UDQVPLW%XIIHU 5HJLVWHU66&7% ,QWHUQDO%XV ("1($'5 14.2.1 Baud rate generation The Baud rate generator is clocked by fCPU/2. The timer is counting downwards and can be started or stopped through the global enable Bit SSCEN in register SSCCON. Register SSCBR is the dual-function Baud Rate Generator/Reload register. Reading SSCBR, while the SSC is enabled, returns the content of the timer. Reading SSCBR, while the SSC is disabled, returns the programmed reload value. In this mode the desired reload value can be written to SSCBR. Note: Never write to SSCBR, while the SSC is enabled. The formulas below calculate the resulting Baud rate for a given reload value and the required reload value for a given Baud rate: fCPU Baud rateSSC = 2 x [(SSCBR) + 1] fCPU SSCBR = ( )1 2 x Baud rateSSC (SSCBR) represents the content of the reload register, taken as unsigned 16 Bit integer. Table 30 lists some possible Baud rates against the required reload values and the resulting bit times for a 40MHz CPU clock. Doc ID 8673 Rev. 3 153/239 Serial channels Table 30. ST10F280 Synchronous baud rate and reload values Baud rate Bit time Reload value --- --- 10M Baud 100ns 0001h 5M Baud 200ns 0003h 2.5M Baud 400ns 0007h 1M Baud 1s 0013h 100K Baud 10s 00C7h 10K Baud 100s 07CFh 1K Baud 1ms 4E1Fh 306 Baud 3.26ms FF4Eh Reserved use a reload value > 0. 154/239 Doc ID 8673 Rev. 3 ST10F280 15 CAN modules CAN modules The two integrated CAN modules (CAN1 and CAN2) are identical and handle the completely autonomous transmission and reception of CAN frames in accordance with the CAN specification V2.0 part B (active) i.e. the on-chip CAN module can receive and transmit standard frames with 11-bit identifiers as well as extended frames with 29-bit identifiers. Because of duplication of CAN controllers, the following adjustements are to be considered: The same internal register addresses both CAN controllers, but with the base addresses differing in address bit A8 and separate chip select for each CAN module. For address mapping, see Chapter 4. The CAN1 transmit line (CAN1_TxD) is the alternate function of the port P4.6 and the receive line (CAN1_RxD) is P4.5. The CAN2 transmit line (CAN2_TxD) is the alternate function of the port P4.7 and the receive line (CAN2_RxD) is the alternate function of the port P4.4. Interrupt of CAN2 is connected to the XBUS interrupt line XP1 (CAN1 is on XP0). Because of the new XPERCON register, both CAN modules have to be selected, before the bit XPEN is set in SYSCON register. After reset, the CAN1 is selected with the related control bit in the XPERCON register. The CAN2 is not selected. 15.1 Memory mapping 15.1.1 CAN1 Address range 00'EF00h 00'EFFFh is reserved for the CAN1 Module access. The CAN1 is enabled by setting bit 0 of the new XPERCON register before setting XPEN bit 2 of the SYSCON register. Accesses to the CAN Module use demultiplexed addresses and a 16-bit data bus (byte accesses are possible). Two waitstates give an access time of 100 ns at 40MHz CPU clock. No tristate waitstate is used. 15.1.2 CAN2 Address range 00'EE00h 00'EEFFh is reserved for the CAN2 Module access. The CAN2 is enabled by setting XPEN bit 2 of the SYSCON register and bit 1 of the new XPERCON register. Accesses to the CAN Module use demultiplexed addresses and a 16-bit data bus (byte accesses are possible). Two waitstates give an access time of 100 ns at 40MHz CPU clock. No tristate waitstate is used. Note: If one or the two CAN modules are used, Port 4 can not be programmed to output all 8 segment address lines. Thus, only 4 segment address lines can be used, reducing the external memory space to 5M Bytes (1M Byte per CS line). 15.2 CAN bus configurations Depending on application, CAN bus configuration may be one single bus with a single or multiple interfaces or a multiple bus with a single or multiple interfaces. The ST10F280 is able to support these 2 cases. Doc ID 8673 Rev. 3 155/239 CAN modules 15.2.1 ST10F280 Single CAN bus The single CAN Bus multiple interfaces configuration may be implemented using 2 CAN transceives as shown in Figure 55. Figure 59. Single CAN bus multiple interfaces - multiple transceivers &$1 5[' 7[' &$1 5[' 7[' &$1 7UDQVFHLYHU &$1 7UDQVFHLYHU &$1B+ &$1EXV &$1B+ ("1($'5 The ST10F280 also supports single CAN Bus multiple (dual) interfaces using the open drain option of the CANx_TxD output as shown in Figure 60. Thanks to the OR-Wired Connection, only one transceiver is required. In this case the design of the application must take in account the wire length and the noise environment. Figure 60. Single CAN bus dual interfaces - single transceiver &$1 5[' 7[' &$1 5[' 7[' 9 N: &$1 7UDQVFHLYHU &$1B+ &$1B+ &$1EXV 2SHQGUDLQRXWSXW ("1($'5 15.2.2 Multiple CAN bus The ST10F280 provides 2 CAN interfaces to support the kind of bus configuration shown in Figure 57. 156/239 Doc ID 8673 Rev. 3 ST10F280 CAN modules Figure 61. Connection to two different CAN buses (e.g. for gateway application) &$1 5[' 7[' &$1 5[' 7[' &$1 7UDQVFHLYHU &$1 7UDQVFHLYHU &$1B+ &$1B+ &$1 EXV &$1 EXV ("1($'5 15.3 Register and message object organization All registers and message objects of the CAN controller are located in the special CAN address area of 256 bytes, which is mapped into segment 0 and uses addresses 00'EE00h through 00'EFFFh. All registers are organized as 16 bit registers, located on word addresses. However, all registers may be accessed byte wise in order to select special actions without effecting other mechanisms. Note: The address map shown in Figure 58 lists the registers which are part of the CAN controller. There are also ST10F280 specific registers that are associated with the CAN Module. These registers, however, control the access to the CAN Module rather than its function. Doc ID 8673 Rev. 3 157/239 CAN modules ST10F280 Figure 62. CAN module address map (()K ())K 0HVVDJH2EMHFW (((K ()(K 0HVVDJH2EMHFW (('K ()'K 0HVVDJH2EMHFW ((&K ()&K 0HVVDJH2EMHFW ((%K ()%K 0HVVDJH2EMHFW (($K ()$K 0HVVDJH2EMHFW ((K ()K 0HVVDJH2EMHFW ((K ()K 0HVVDJH2EMHFW ((K ()K 0HVVDJH2EMHFW ((K ()K 0HVVDJH2EMHFW ((K ()K 0HVVDJH2EMHFW ((K ()K 0HVVDJH2EMHFW ((K ()K 0HVVDJH2EMHFW ((K ()K 0HVVDJH2EMHFW ((K ()K 0HVVDJH2EMHFW ((K ()K *HQHUDO5HJLVWHUV &$1 &$1 &$1$GGUHVV$UHD 0DVNRI /DVW0HVVDJH ()&K((&K *OREDO0DVN /RQJ ()K((K *OREDO0DVN 6KRUW %LW7LPLQJ 5HJLVWHU ,QWHUUXSW 5HJLVWHU &RQWURO6WDWXV 5HJLVWHU ()K((K ()K((K ()K((K ()K((K *HQHUDO5HJLVWHUV ("1($'5 158/239 Doc ID 8673 Rev. 3 ST10F280 CAN modules Control / Status Register 15 14 13 BOFF EWRN - R R 12 11 10 RXOK TXOK R/W R/W Address: 0xEF00h / 0xEE00h XReg Reset: 0xXX01h Type: R, R/W 7 6 5 4 3 2 1 0 LEC 9 8 TST CCE 0 0 EIE SIE IE INIT R/W R/W R/W R R R/W R/W R/W R/W INIT Initialization 1: Software initialization of the CAN controller. While init is set, all message transfers are stopped. Setting init does not change the configuration registers and does not stop transmission or reception of a message in progress. The INIT bit is also set by hardware, following a busoff condition; the CPU then needs to reset INIT to start the bus recovery sequence. 0: Disable software initialization of the CAN controller; on INI completion, the CAN waits for 11 consecutive recessive bit before taking part in bus activities. IE Interrupt Enable Does not affect status updates. 1: Global interrupt enable from CAN module. 0: Global interrupt disable from CAN module. SIE Status Change Interrupt Enable 1: Enables interrupt generation when a message transfer (reception or transmision is successfully completed) or CAN bus error is detected and registered in LEC is the status partition. 0: Disable status change interrupt. EIE Error Interrupt Enable 1: Enables interrupt generation on a change of bit BOFF or EWARN in the status partition. 0: Disable error interrupt. CCE Configuration Change Enable 1: Allows CPU access to the bit timing register 0: Disables CPU access to the bit timing register TST Test Mode (Bit 7) Make sure that bit 7 is cleared when writing to the Control Register. Writing a 1 during normal operation may lead erroneous device behaviour. Doc ID 8673 Rev. 3 159/239 CAN modules ST10F280 LEC Last Error Code This field holds a code which indicates the type of the last error occurred on the CAN bus. If a message has been transferred (reception or transmission) without error, this field will be cleared. Code "7" is unused and may be written by the CPU to check for updates. 0: No Error 1: Stuff Error: More than 5 equal bit in a sequence have occurred in a part of a received message where this is not allowed. 2: Form Error: A fixed format part of a received frame has the wrong format. 3: AckError: The message this CAN controller transmitted was not acknowledged by another node 4: Bit1Error: During the transmission of a message (with the exception of the arbitration field), the device wanted to send a recessive level ("1"), but the monitored bus value was dominant 5: Bit0Error: During the transmission of a message (or acknowledge bit, active error flag, or overload flag), the device wanted to send a dominant level ("0"), but the monitored bus value was recessive. During busoff recovery this status is set each time a sequence of 11 recessive bit has been monitored. This enables the CPU to monitor the proceeding of the busoff recovery sequence (indicating the bus is not stuck at dominant or continuously disturbed). 6: CRCError: The CRC check sum was incorrect in the message received. TXOK Transmitted Message Successfully Indicates that a message has been transmitted successfully (error free and acknowledged by at least one other node), since this bit was last reset by the CPU (the CAN controller does not reset this bit!). RXOK Received Message Successfully Indicates that a message has been received successfully, since this bit was last reset by the CPU (the CAN controller does not reset this bit!). EWRN Error Warning Status Indicates that at least one of the error counters in the EML has reached the error warning limit of 96. BOFF Busoff Status Indicates when the CAN controller is in busoff state (see EML). Note: Reading the upper half of the Control Register (status partition) will clear the Status Change Interrupt value in the Interrupt Register, if it is pending. Use byte accesses to the lower half to avoid this. 15.4 CAN interrupt handling The on-chip CAN Module has one interrupt output, which is connected (through a synchronization stage) to a standard interrupt node in the ST10F280 in the same manner as all other interrupts of the standard on-chip peripherals. The control register for this interrupt is XP0IC (located at address F186h/C3h for CAN1 and F18Eh/C7h for CAN2 in the ESFR range). The associated interrupt vector is called XP0INT at location 100h (trap number 40h) and XP1INT at location 104h (trap number 41h). With this configuration, the user has all control options available for this interrupt, such as enabling/disabling, level and group priority, and interrupt or PEC service (see note below). 160/239 Doc ID 8673 Rev. 3 ST10F280 CAN modules As for all other interrupts, the interrupt request flag XP0IR/XP1IR in register XP0IC/XP1IC is cleared automatically by hardware when this interrupt is serviced (either by standard interrupt or PEC service). Note: As a rule, CAN interrupt requests can be serviced by a PEC channel. However, because PEC channels only can execute single predefined data transfers (there are no conditional PEC transfers), PEC service can only be used, if the respective request is known to be generated by one specific source, and that no other interrupt request will be generated in between. In practice this seems to be a rare case. Since an interrupt request of the CAN Module can be generated due to different conditions, the appropriate CAN interrupt status register must be read in the service routine to determine the cause of the interrupt request. The Interrupt Identifier INTID (a number) in the Interrupt Register indicates the cause of an interrupt. When no interrupt is pending, the identifier will have the value 00h. If the value in INTID is not 00h, then there is an interrupt pending. If bit IE in the Control Register is set, also the interrupt line to the CPU is activated. The interrupt line remains active until either INTID gets 00h (after the interrupt requester has been serviced) or until IE is reset (if interrupts are disabled). The interrupt with the lowest number has the highest priority. If a higher priority interrupt (lower number) occurs before the current interrupt is processed, INTID is updated and the new interrupt overrides the last one. The Table 31 lists the valid values for INTID and their corresponding interrupt sources. Interrupt Register 15 14 13 12 11 10 9 8 7 6 5 Reserved 4 3 2 1 0 INTID R Address: 0xEF02h / 0xEE02h XReg Reset: 0x--XXh Type: R INTID Interrupt Identifier This number indicates the cause of the interrupt. When no interrupt is pending, the value will be "00". Table 31. INTID INTID values and corresponding interrupt sources Cause of the Interrupt 00 Interrupt Idle: There is no interrupt request pending. 01 Status Change Interrupt: The CAN controller has updated (not necessarily changed) the status in the Control Register. This can refer to a change of the error status of the CAN controller (EIE is set and BOFF or EWRN change) or to a CAN transfer incident (SIE must be set), like reception or transmission of a message (RXOK or TXOK is set) or the occurrence of a CAN bus error (LEC is updated). The CPU may clear RXOK, TXOK, and LEC, however, writing to the status partition of the Control Register can never generate or reset an interrupt. To update the INTID value the status partition of the Control Register must be read. Doc ID 8673 Rev. 3 161/239 CAN modules ST10F280 Table 31. INTID values and corresponding interrupt sources (continued) INTID Cause of the Interrupt 02 Message 15 Interrupt: Bit INTPND in the Message Control Register of message object 15 (last message) has been set. The last message object has the highest interrupt priority of all message objects. 1) (1) (2+N) Message N Interrupt: Bit INTPND in the Message Control Register of message object `N' has been set (N = 1...14). (1)(2) 1. Bit INTPND of the corresponding message object has to be cleared to give messages with a lower priority the possibility to update INTID or to reset INTID to 00h (idle state). 2. A message interrupt code is only displayed, if there is no other interrupt request with a higher priority. 15.4.1 Bit timing configuration According to the CAN protocol specification, a bit time is subdivided into four segments: Sync segment, propagation time segment, phase buffer segment 1 and phase buffer segment 2. Each segment is a multiple of the time quantum tq with tq = ( BRP + 1 ) x 2 x tXCLK The Synchronization Segment (Sync seg) is always 1 tq long. The Propagation Time Segment and the Phase Buffer Segment1 (combined to Tseg1) defines the time before the sample point, while Phase Buffer Segment2 (Tseg2) defines the time after the sample point. The length of these segments is programmable (except Sync-Seg). Note: For exact definition of these segments please refer to the CAN Specification. Figure 63. Bit timing definition ELWWLPH 6\QF 6HJ 76HJ WLPHTXDQWXP 76HJ VDPSOHSRLQW 6\QF 6HJ WUDQVPLWSRLQW ("1($'5 162/239 Doc ID 8673 Rev. 3 ST10F280 CAN modules Bit Timing Register 15 14 13 12 11 10 9 8 7 6 5 4 3 2 0 TSEG2 TSEG1 SJW BRP R R/W R/W R/W R/W Address: 0xEF04h / EE04h XReg Reset: 0xUUUUh Type: R, R/W 1 0 BRP Baud Rate Prescaler For generating the bit time quanta the CPU frequency is divided by 2 x (BRP+1). SJW (Re)Synchronization Jump Width Adjust the bit time by maximum (SJW+1) time quanta for re-synchronization. TSEG1 Time Segment before sample point There are (TSEG1+1) time quanta before the sample point. Valid values for TSEG1 are "2...15". TSEG2 Time Segment after sample point There are (TSEG2+1) time quanta after the sample point. Valid values for TSEG2 are "1...7". Note: This register can only be written, if the configuration change enable bit (CCE) is set. 15.4.2 Mask registers Messages can use standard or extended identifiers. Incoming frames are masked with their appropriate global masks. Bit IDE of the incoming message determines whether the standard 11 bit mask in Global Mask Short or the 29 bit extended mask in Global Mask Long is to be used. Bit holding a "0" mean "don't care", so do not compare the message's identifier in the respective bit position. The last message object (15) has an additional individually programmable acceptance mask (Mask of Last Message) for the complete arbitration field. This allows classes of messages to be received in this object by masking some bits of the identifier. Note: The Mask of Last Message is ANDed with the Global Mask that corresponds to the incoming message. Doc ID 8673 Rev. 3 163/239 CAN modules ST10F280 Global Mask Short 15 12 11 10 9 8 ID20...18 14 13 1 1 1 1 1 ID28...21 R/W R R R R R R/W Address: 0xEF06h / EE06h XReg Reset: 0xUFUUh Type: R, R/W 7 6 5 4 3 2 1 0 2 1 0 2 1 0 ID28...18 Identifier (11 Bit) Mask to filter incoming messages with standard identifier. Upper Global Mask Long 15 14 13 12 11 10 9 8 7 6 5 4 3 ID20...13 ID28...21 R/W R/W Address: 0xEF08h / EE08h XReg Reset: 0xUUUUh Type: R/W Lower Global Mask Long 15 14 10 9 8 ID4...0 13 12 11 0 0 0 ID12...5 R/W R R R R/W Address: 0xEF0Ah / EE0Ah XReg Reset: 0xUUUUh Type: R, R/W 7 6 5 4 ID28...0 Identifier (29 bit) Mask to filter incoming messages with extended identifier. 164/239 Doc ID 8673 Rev. 3 3 ST10F280 CAN modules Upper Mask of Last Message 15 14 13 12 11 10 9 8 7 6 5 4 3 ID20...18 ID17...13 ID28...21 R/W R/W R/W Address: 0xEF0Ch / EE0Ch XReg Reset: 0xUUUUh Type: R/W 2 1 0 2 1 0 Lower Mask of Last Message 15 14 10 9 8 ID4...0 13 12 11 0 0 0 ID12...5 R/W R R R R/W Address: 0xEF0Eh / EE0Eh XReg Reset: 0xUUUUh Type: R, R/W 7 6 5 4 3 ID28...0 Identifier (29 bit) Mask to filter the last incoming message (Nr. 15) with standard or extended identifier (as configured). 15.5 The message object The message object is the primary means of communication between CPU and CAN controller. Each of the 15 message objects uses 15 consecutive bytes (see Figure 60) and starts at an address that is a multiple of 16. Note: All message objects must be initialized by the CPU, even those which are not going to be used, before clearing the INIT bit. Each element of the Message Control Register is made of two complementary bits. This special mechanism allows the selective setting or resetting of specific elements (leaving others unchanged) without requiring read-modify-write cycles. None of these elements will be affected by reset. The Table 32 shows how to use and to interpret these 2 bit-fields. Doc ID 8673 Rev. 3 165/239 CAN modules ST10F280 Figure 64. Message object address map 2EMHFW6WDUW$GGUHVV 0HVVDJH&RQWURO $UELWUDWLRQ 'DWD 0HVVDJH&RQILJ 'DWD 'DWD 'DWD 'DWD 'DWD 'DWD 5HVHUYHG 'DWD ("1($'5 Table 32. Functions of complementary bit of message control register Value 166/239 Function on write Meaning on read 00 Reserved Reserved 01 Reset element Element is reset 10 Set element Element is set 11 Leave element unchanged Reserved Doc ID 8673 Rev. 3 ST10F280 CAN modules Message Control Register 15 14 13 12 11 10 RMTPND TXRQ MSGLST CPUUPD R/W R/W R/W Address: 0xEFn0h / EEn0h XReg Reset: 0xUUUUh Type: R/W 9 8 7 6 5 4 3 2 1 0 NEWDAT MSGVAL TXIE RXIE INTPND R/W R/W R/W R/W R/W INTPND Interrupt Pending Indicates, if this message object has generated an interrupt request (see TXIE and RXIE), since this bit was last reset by the CPU, or not. RXIE Receive Interrupt Enable Defines, if bit INTPND is set after successful reception of a frame. TXIE Transmit Interrupt Enable Defines, if bit INTPND is set after successful transmission of a frame.(1) MSGVAL Message Valid Indicates, if the corresponding message object is valid or not. The CAN controller only operates on valid objects. Message objects can be tagged invalid, while they are changed, or if they are not used at all. NEWDAT New Data Indicates, if new data has been written into the data portion of this message object by CPU (transmit-objects) or CAN controller (receive-objects) since this bit was last reset, or not.(2) MSGLST Message Lost (This bit applies to receive-objects only) (Receive) Indicates that the CAN controller has stored a new message into this object, while NEWDAT was still set, i.e. the previously stored message is lost. CPUUPD CPU Update (This bit applies to transmit-objects only) (Transmit) Indicates that the corresponding message object may not be transmitted now. The CPU sets this bit in order to inhibit the transmission of a message that is currently updated, or to control the automatic response to remote requests. TXRQ Transmit Request Indicates that the transmission of this message object is requested by the CPU or via a remote frame and is not yet done. TXRQ can be disabled by CPUUPD. (1) (3) RMTPND Remote Pending (Used for transmit-objects) Indicates that the transmission of this message object has been requested by a remote node, but the data has not yet been transmitted. When RMTPND is set, the CAN controller also sets TXRQ. RMTPND and TXRQ are cleared, when the message object has been successfully transmitted. 1. In message object 15 (last message) these bits are hardwired to "0" (inactive) in order to prevent transmission of message 15. 2. When the CAN controller writes new data into the message object, unused message bytes will be overwritten by non specified values. Usually the CPU will clear this bit before working on the data, and verify that the bit is still cleared once it has finished working to ensure that it has worked on a consistent set of data and not part of an old message and part of the new message. For transmit-objects the CPU will set this bit along with clearing bit CPUUPD. This will ensure that, if the message is actually being transmitted during the time the message was being updated by the CPU, the CAN controller will not reset bit TXRQ. In this way bit TXRQ is only reset once the actual data has been transferred. Doc ID 8673 Rev. 3 167/239 CAN modules ST10F280 3. When the CPU requests the transmission of a receive-object, a remote frame will be sent instead of a data frame to request a remote node to send the corresponding data frame. This bit will be cleared by the CAN controller along with bit RMTPND when the message has been successfully transmitted, if bit NEWDAT has not been set. If there are several valid message objects with pending transmission request, the message with the lowest message number is transmitted first. 15.6 Arbitration Registers The arbitration Registers are used for acceptance filtering of incoming messages and to define the identifier of outgoing messages. Upper Arbitration Reg 15 14 13 12 11 10 9 8 7 6 5 4 3 ID20...18 ID17...13 ID28...21 R/W R/W R/W Address: 0xEFn2h / EEn2h XReg Reset: 0xUUUUh Type: R/W 2 1 0 2 1 0 Lower Arbitration Reg 15 14 10 9 8 ID4...0 13 12 11 0 0 0 ID12...5 R/W R R R R/W Address: 0xEFn4h / EEn4h XReg Reset: 0xUUUUh Type: R, R/W 7 6 5 4 3 ID28...0 Identifier (29 bit) Identifier of a standard message (ID28...18) or an extended message (ID28...0). For standard identifiers bit ID17...0 are "don't care". 168/239 Doc ID 8673 Rev. 3 ST10F280 16 Watchdog timer Watchdog timer The Watchdog Timer is a fail-safe mechanism which prevents the microcontroller from malfunctioning for long periods of time. The Watchdog Timer is always enabled after a reset of the chip and can only be disabled in the time interval until the EINIT (end of initialization) instruction has been executed. Therefore, the chip start-up procedure is always monitored. The software must be designed to service the watchdog timer before it overflows. If, due to hardware or software related failures, the software fails to do so, the watchdog timer overflows and generates an internal hardware reset. It pulls the RSTOUT pin low in order to allow external hardware components to be reset. Each of the different reset sources is indicated in the WDTCON register. The indicated bit are cleared with the EINIT instruction. The origine of the reset can be identified during the initialization phase. WDTCON 15 14 13 12 11 10 WDTREL 9 8 7 6 5 4 3 2 1 0 - - PONR LHWR SHWR SWR WDTR WDTIN R R R R R R/W R/W Address: 0xFFAEh / D7h SFR Reset: 0x00XXh Type: R, R/W WDTIN Watchdog Timer Input Frequency Selection 0: Input Frequency is fCPU/2. 1: Input Frequency is fCPU/128. WDTR(1) Watchdog Timer Reset Indication Flag Set by the watchdog timer on an overflow. Cleared by a hardware reset or by the SRVWDT instruction. SWR(1) Software Reset Indication Flag Set by the SRST execution. Cleared by the EINIT instruction. SHWR(1) Short Hardware Reset Indication Flag Set by the input RSTIN. Cleared by the EINIT instruction. LHWR(1) Long Hardware Reset Indication Flag Set by the input RSTIN. Cleared by the EINIT instruction. PONR(1)(2) Power-On (Asynchronous) Reset Indication Flag Set by the input RSTIN if a power-on condition has been detected. Cleared by the EINIT instruction. 1. More than one reset indication flag may be set. After EINIT, all flags are cleared. 2. Power-on is detected when a rising edge from Vcc = 0 V to Vcc > 2.0 V is recognized. Doc ID 8673 Rev. 3 169/239 Watchdog timer ST10F280 The PONR flag of WDTCON register is set if the output voltage of the internal 3.3V supply falls below the threshold (typically 2V) of the power-on detection circuit. This circuit is efficient to detect major failures of the external 5V supply but if the internal 3.3V supply does not drop under 2 volts, the PONR flag is not set. This could be the case on fast switch-off / switch-on of the 5V supply. The time needed for such a sequence to activate the PONR flag depends on the value of the capacitors connected to the supply and on the exact value of the internal threshold of the detection circuit. Table 33. WDTCON bits value on different resets Reset source PONR LHWR SHWR SWR Power On Reset X X X X Power on after partial supply failure 1 X X X X X X X X Long Hardware Reset Short Hardware Reset Software Reset X Watchdog Reset X WDTR X Note: 1. PONR bit may not be set for short supply failure. Note: 2. For power-on reset and reset after supply partial failure, asynchronous reset must be used. In case of bi-directional reset is enabled, and if the RSTIN pin is latched low after the end of the internal reset sequence, then a Short hardware reset, a software reset or a watchdog reset will trigger a Long hardware reset. Thus, Reset Indications flags will be set to indicate a Long Hardware Reset. The Watchdog Timer is 16-bit, clocked with the system clock divided by 2 or 128. The high Byte of the watchdog timer register can be set to a pre-specified reload value (stored in WDTREL). Each time it is serviced by the application software, the high byte of the watchdog timer is reloaded. For security, rewrite WDTCON each time before the watchdog timer is serviced The Table 34 shows the watchdog time range for 40MHz CPU clock. Table 34. WDTREL reload value Prescaler for fCPU = 40MHz Reload value in WDTREL 2 (WDTIN = `0') 128 (WDTIN = `1') FFh 12.8s 819.2ms 00h 3.276ms 209.7ms The watchdog timer period is calculated with the following formula: P 170/239 WDT 1 = --------------- x 512 x ( 1 + [ WDTIN ] x 63 ) x ( 256 - [ WDTREL ] ) f CPU Doc ID 8673 Rev. 3 ST10F280 17 System reset System reset Table 35. Reset event definition Reset source Short-cut Conditions Power-on reset PONR Power-on Long Hardware reset (synchronous & asynchronous) LHWR t RSTIN > 1032 TCL Short Hardware reset (synchronous reset) SHWR 4 TCL < t RSTIN < 1032 TCL Watchdog Timer reset WDTR WDT overflow Software reset SWR SRST execution System reset initializes the MCU in a predefined state. There are five ways to activate a reset state. The system start-up configuration is different for each case as shown in Table 35. 17.1 Asynchronous reset (long hardware reset) An asynchronous reset is triggered when RSTIN pin is pulled low while RPD pin is at low level. Then the MCU is immediately forced in reset default state. It pulls low RSTOUT pin, it cancels pending internal hold states if any, it waits for any internal access cycles to finish, it aborts external bus cycle, it switches buses (data, address and control signals) and I/O pin drivers to high-impedance, it pulls high PORT0 pins and the reset sequence starts. 17.1.1 Power-on reset The asynchronous reset must be used during the power-on of the MCU. Depending on crystal frequency, the on-chip oscillator needs about 10ms to 50ms to stabilize. The logic of the MCU does not need a stabilized clock signal to detect an asynchronous reset, so it is suitable for power-on conditions. To ensure a proper reset sequence, the RSTIN pin and the RPD pin must be held at low level until the MCU clock signal is stabilized and the system configuration value on PORT0 is settled. 17.1.2 Hardware reset The asynchronous reset must be used to recover from catastrophic situations of the application. It may be triggerred by the hardware of the application. Internal hardware logic and application circuitry are described in Reset circuitry chapter and Figure 68, Figure 69 and Figure 66. 17.1.3 Exit of asynchronous reset state When the RSTIN pin is pulled high, the MCU restarts. The system configuration is latched from PORT0 and ALE, RD and R/W pins are driven to their inactive level. The MCU starts program execution from memory location 00'0000h in code segment 0. This starting location will typically point to the general initialization routine. Timing of asynchronous reset sequence are summarized in Figure 61. Doc ID 8673 Rev. 3 171/239 System reset ST10F280 Figure 65. Asynchronous reset timing 7&/RU7&/ &38&ORFN 567,1 $V\QFKURQRXV 5HVHW&RQGLWLRQ 53' 567287 $/( 3257 ,167 5HVHW&RQILJXUDWLRQ /DWFKLQJSRLQWRI3257 IRUV\VWHPVWDUWXS FRQILJXUDWLRQ ,QWHUQDO 5HVHW 6LJQDO ("1($'5 Note: 1. RSTIN rising edge to internal latch of PORT0 is 3 CPU clock cycles (6 TCL) if the PLL is bypassed and the prescaler is on (fCPU = fXTAL / 2), else it is 4 CPU clock cycles (8 TCL) . 17.2 Synchronous reset (warm reset) A synchronous reset is triggered when RSTIN pin is pulled low while RPD pin is at high level. In order to properly activate the internal reset logic of the MCU, the RSTIN pin must be held low, at least, during 4 TCL (2 periods of CPU clock). The I/O pins are set to high impedance and RSTOUT pin is driven low. After RSTIN level is detected, a short duration of 12 TCL (approximately 6 periods of CPU clock) elapes, during which pending internal hold states are cancelled and the current internal access cycle if any is completed. External bus cycle is aborted. The internal pull-down of RSTIN pin is activated if bit BDRSTEN of SYSCON register was previously set by software. This bit is always cleared on power-on or after a reset sequence. 17.2.1 Exit of synchronous reset state The internal reset sequence starts for 1024 TCL (512 periods of CPU clock) and RSTIN pin level is sampled. The reset sequence is extended until RSTIN level becomes high. Then, the MCU restarts. The system configuration is latched from PORT0 and ALE, RD and R/W pins are driven to their inactive level. The MCU starts program execution from memory location 00'0000h in code segment 0. This starting location will typically point to the general initialization routine. Timing of synchronous reset sequence are summarized in Figure 66 and Figure 67. 172/239 Doc ID 8673 Rev. 3 ST10F280 System reset Figure 66. Synchronous warm reset (short low pulse on RSTIN) 7&/ PLQ 7&/ PD[ 7&/ RU7&/ &38&ORFN 567,1 ,QWHUQDOO\SXOOHGORZ 53' P$'LVFKDUJH 953'!9$V\QFKURQRXV5HVHWQRWHQWHUHG 567287 $/( 3257 5HVHW&RQILJXUDWLRQ ,167 /DWFKLQJSRLQWRI3257 IRUV\VWHPVWDUWXSFRQILJXUDWLRQ ,QWHUQDO 5HVHW 6LJQDO ("1($'5 1. RSTIN assertion can be released there. 2. If during the reset condition (RSTIN low), VRPD voltage drops below the threshold voltage (about 2.5V for 5V operation), the asynchronous reset is then immediately entered. 3. RSTIN rising edge to internal latch of PORT0 is 3 CPU clock cycles (6 TCL) if the PLL is bypassed and the prescaler is on (fCPU = fXTAL / 2), else it is 4 CPU clock cycles (8 TCL). 4. RSTIN pin is pulled low if bit BDRSTEN (bit 5 of SYSCON register) was previously set by software. Bit BDRSTEN is cleared after reset. Doc ID 8673 Rev. 3 173/239 System reset ST10F280 Figure 67. Synchronous warm reset (long low pulse on RSTIN) 7&/ 7&/ RU7&/ 7&/ &38&ORFN ,QWHUQDOO\SXOOHGORZ 567,1 53' P$'LVFKDUJH 953'!9$V\QFKURQRXV5HVHWQRWHQWHUHG 567287 $/( 3257 5HVHW&RQILJXUDWLRQ /DWFKLQJSRLQWRI3257 IRUV\VWHPVWDUWXSFRQILJXUDWLRQ ,QWHUQDO 5HVHW 6LJQDO ("1($'5 1. RSTIN rising edge to internal latch of PORT0 is 3 CPU (6 TCL) clock cycles if the PLL is bypassed and the prescaler is on (fCPU = fXTAL / 2), else it is 4 CPU clock cycles (8 TCL). 2. If during the reset condition (RSTIN low), VRPD voltage drops below the threshold voltage (about 2.5V for 5V operation), the asynchronous reset is then immediately entered. 3. RSTIN pin is pulled low if bit BDRSTEN (bit 5 of SYSCON register) was previously set by soft-ware. Bit BDRSTEN is cleared after reset. 17.3 Software reset The reset sequence can be triggered at any time using the protected instruction SRST (software reset). This instruction can be executed deliberately within a program, for example to leave bootstrap loader mode, or upon a hardware trap that reveals a system failure. Upon execution of the SRST instruction, the internal reset sequence (1024 TCL) is started. The microcontroller behaviour is the same as for a Short Hardware reset, except that only P0.12...P0.6 bit are latched at the end of the reset sequence, while P0.5...P0.2 bit are cleared. 17.4 Watchdog timer reset When the watchdog timer is not disabled during the initialization or when it is not regularly serviced during program execution it will overflow and it will trigger the reset sequence. Unlike hardware and software resets, the watchdog reset completes a running external bus cycle if this bus cycle either does not use READY, or if READY is sampled active (low) after the programmed wait states. When READY is sampled inactive (high) after the programmed wait states the running external bus cycle is aborted. Then the internal reset sequence is started. At the end of the internal reset sequence (1024 TCL), only P0.12...P0.6 bit are latched, while previously latched values of P0.5...P0.2 are cleared. 174/239 Doc ID 8673 Rev. 3 ST10F280 17.5 System reset RSTOUT pin and bidirectional reset The RSTOUT pin is driven active (low level) at the beginning of any reset sequence (synchronous/asynchronous hardware, software and watchdog timer resets). RSTOUT pin stays active low beyond the end of the initialization routine, until the protected EINIT instruction (End of Initialization) is completed. The Bidirectional Reset function is useful when external devices require a reset signal but cannot be connected to RSTOUT pin, because RSTOUT signal lasts during initialisation. It is, for instance, the case of external memory running initialization routine before the execution of EINIT instruction. Bidirectional reset function is enabled by setting bit 3 (BDRSTEN) in SYSCON register. It only can be enabled during the initialization routine, before EINIT instruction is completed. When enabled, the open drain of the RSTIN pin is activated, pulling down the reset signal, for the duration of the internal reset sequence (synchronous/asynchronous hardware, software and watchdog timer resets). At the end of the internal reset sequence the pull down is released and the RSTIN pin is sampled 8 TCL periods later. If signal is sampled low, a hardware reset is triggered again. If it is sampled high, the chip exits reset state according to the running reset way (synchronous/asynchronous hardware, software and watchdog timer resets ). Note: The bidirectional reset function is disabled by any reset sequence (Bit BDRSTEN of SYSCON is cleared). To be activated again it must be enabled during the initialization routine. 17.6 Reset circuitry The internal reset circuitry is described in Figure 68. An internal pull-up resistor is implemented on RSTIN pin. (50k minimum, to 250k maximum). The minimum reset time must be calculated using the lowest value. In addition, a programmable pull-down (bit BDRSTEN of SYSCON register) drives the RSTIN pin according to the internal reset state as explained in Section 17.5: RSTOUT pin and bidirectional reset. The RSTOUT pin provides a signals to the application as described in Section 17.5: RSTOUT pin and bidirectional reset. A weak internal pull-down is connected to the RPD pin to discharge external capacitor to Vss at a rate of 100A to 200A. This Pull-down is turned on when RSTIN pin is low If bit PWDCFG of SYSCON register is set, an internal pull-up resistor is activated at the end of the reset sequence. This pull-up charges the capacitor connected to RPD pin. If Bidirectional Reset function is not used, the simplest way to reset ST10F280 is to connect external components as shown in Figure 69. It works with reset from application (hardware or manual) and with power-on. The value of C1 capacitor, connected on RSTIN pin with internal pull-up resistor (50k to 250k), must lead to a charging time long enough to let the internal or external oscillator and / or the on-chip PLL to stabilize. The R0-C0 components on RPD pin are mainly implemented to provide a time delay to exit Power down mode (see Chapter 18: Power reduction modes). Nervertheless, they drive RPD pin level during resets and they lead to different reset modes as explained hereafter. On power-on, C0 is totaly discharged, a low level on RPD pin forces an asynchronous Doc ID 8673 Rev. 3 175/239 System reset ST10F280 hardware reset. C0 capacitor starts to charge throught R0 and at the end of reset sequence ST10F280 restarts. RPD pin threshold is typically 2.5V. Depending on the delay of the next applied reset, the MCU can enter a synchronous reset or an asynchronous reset. If RPD pin is below 2.5V an asynchronous reset starts, if RPD pin is above 2.5V a synchronous reset starts. (see Section 17.1: Asynchronous reset (long hardware reset) and Section 17.2: Synchronous reset (warm reset)). Note that an internal pull-down is connected to RPD pin and can drive a 100A to 200A current. This Pull-down is turned on when RSTIN pin is low. In order to properly use the Bidirectional reset features, the schematic (or equivalent) of Figure 66 must be implemented. R1-C1 only work for power-on or manual reset in the same way as explained previously. D1 diode brings a faster discharge of C1 capacitor at power-off during repetitive switch-on / switch-off sequences. D2 diode performs an OR-wired connection, it can be replaced with an open drain buffer. R2 resistor may be added to increase the pull-up current to the open drain in order to get a faster rise time on RSTIN pin when bidirectional function is activated. The start-up configurations and some system features are selected on reset sequences as described in Table and Table 37. Table 36 describes what is the system configuration latched on PORT0 in the five different reset ways. Table 37 summarizes the bit state of PORT0 latched in RP0H, SYSCON, BUSCON0 registers. RPOH register is described in Section 19.2: System configuration registers. 176/239 Doc ID 8673 Rev. 3 ST10F280 System reset Figure 68. Internal (simplified) reset circuitry (,1,7,QVWUXFWLRQ &OU 4 567287 6HW 5HVHW6WDWH 0DFKLQH &ORFN 9&& 6567LQVWUXFWLRQ ZDWFKGRJRYHUIORZ 7ULJJHU ,QWHUQDO 5HVHW 6LJQDO 567,1 &OU %'567(1 5HVHW6HTXHQFH &38&ORFN&\FOHV 9&& $V\QFKURQRXV 5HVHW 53' )URPWR([LW 3RZHUGRZQ &LUFXLW :HDNSXOOGRZQ aP$ ("1($'5 Figure 69. Minimum external reset circuitry 567287 ([WHUQDO +DUGZDUH 567,1 67) & D 0DQXDO+DUGZDUH5HVHW E )RU$XWRPDWLF3RZHUXS5HVHWDQGLQWHUUXSWLEOHSRZHUGRZQPRGH 9'' 5 53' & ("1($'5 Doc ID 8673 Rev. 3 177/239 System reset ST10F280 Figure 70. External reset hardware circuitry 9'' 5 567287 ([WHUQDO +DUGZDUH 9'' ' 5 ' 567,1 67) 9'' 2SHQ'UDLQ,QYHUWHU 5 53' & ([WHUQDO 5HVHW6RXUFH & ("1($'5 Table 36. PORT0 latched configuration for the different resets Reserved BSL Reserved Reserved Adapt Mode Emu Mode P0H.4 P0H.3 P0H.2 P0H.1 P0H.0 P0L.7 P0L.6 P0L.5 P0L.4 P0L.3 P0L.2 P0L.1 P0L.0 - - - X X X X X X X - - - - - - Watchdog Reset - - - X X X X X X X - - - - - - Short Hardware Reset - - - X X X X X X X X X X X X X Long Hardware Reset X X X X X X X X X X X X X X X X Power-On Reset X X X X X X X X X X X X X X X X Sample event Doc ID 8673 Rev. 3 Bus Type - : Pin is not sampled WR config. P0H.5 Chip Selects P0H.6 Clock Options P0H.7 Software Reset X : Pin is sampled 178/239 Segm. Addr. Lines PORT0 ST10F280 System reset X(2) X(2) Internal logic To clock generator - To Port 4 logic To Port 6 logic - R EMU BUSCON0 X(2) X(2) X(2) R WRC X(2) X(2) X(2) I1 I0 X(2) X(2) X(2) X(2) X(2) X(2) X(2) X(2) X(2) X(2) X(2) X(2) X(2) X(2) X(2) X(2) X(2) X(2) X(2) Internal X(2) R ADP WRC SYSCON X(2) X(2) I2 CSSEL CSSEL X(2) X(2) X(2) I3 Internal CSSEL X(2) BUS ACT0 (4) X(2) X(2) I4 CSSEL SALSEL (1) I5 SALSEL SALSEL X(2) RP0H I6 BSL CLKCFG X(2) PORT0 bit Name I7 SALSEL h0 Internal h1 CLKCFG h2 CLKCFG BUSTYP h3 BTYP h4 WRCFG (3) CLKCFG BUSTYP h5 BTYP h6 ALE CTL0 (4) BYTDIS (3) PORT0 bit h7 nber CLKCFG PORT0 bit latched into the different registers after reset CLKCFG Table 37. 1. Only RP0H low byte is used and the bit-fields are latched from PORT0 high byte to RP0H low byte. 2. Not latched from PORT0. 3. Indirectly depend on PORT0. 4. Bits set if EA pin is 1. Doc ID 8673 Rev. 3 179/239 Power reduction modes 18 ST10F280 Power reduction modes Two different power reduction modes with different levels of power reduction have been implemented in the ST10F280, which may be entered under software control. In Idle mode the CPU is stopped, while the peripherals continue their operation. Idle mode can be terminated by any reset or interrupt request. In Power Down mode both the CPU and the peripherals are stopped. Power Down mode can now be configured by software in order to be terminated only by a hardware reset or by a transition on enabled fast external interrupt pins. Note: All external bus actions are completed before Idle or Power Down mode is entered. However, Idle or Power Down mode is not entered if READY is enabled, but has not been activated (driven low for negative polarity, or driven high for positive polarity) during the last bus access. 18.1 Idle mode Idle mode is entered by running IDLE protected instruction. The CPU operation is stopped and the peripherals still run. Idle mode is terminate by any interrupt request. Whatever the interrupt is serviced or not, the instruction following the IDLE instruction will be executed after return from interrupt (RETI) instruction, then the CPU resumes the normal program. Note that a PEC transfer keeps the CPU in Idle mode. If the PEC transfer does not succeed, the Idle mode is terminated. Watchdog timer must be properly programmed to avoid any disturbance during Idle mode. 18.2 Power down mode Power Down mode starts by running PWRDN protected instruction. Internal clock is stopped, all MCU parts are on hold including the watchdog timer. There are two different operating Power Down modes: protected mode and interruptible mode. The internal RAM contents can be preserved through the voltage supplied via the VDD pins. To verify RAM integrity, some dedicated patterns may be written before entering the Power Down mode and have to be checked after Power Down is resumed. It is mandatory to keep VDD = +5V 10% during power-down mode, because the on-chip voltage regulator is turned in power saving mode and it delivers 2.5V to the core logic, but it must be supplied at nominal VDD = +5V. 180/239 Doc ID 8673 Rev. 3 ST10F280 Power reduction modes 12 11 10 9 8 7 6 5 4 3 2 STKSZ SGTDIS ROMEN BYTDIS CLKEN WRCFG CSCFG PWDCFG OWDDIS BDRSTEN XPEN VISIBLE XPER-SHARE 15 ROMS1 SYSCON 14 13 R/W R/W R/W R/W R/W R/W R/W R/W R/W R/W R/W R/W R/W R/W Address: 0xFF12H / 89h SFR Reset: 0x0XX0h Type: R/W 1 0 PWDCFG Power Down Mode Configuration Control 0: Power Down Mode can only be entered during PWRDN instruction execution if NMI pin is low, otherwise the instruction has no effect. To exit Power Down Mode, an external reset must occurs by asserting the RSTIN pin. 1: Power Down Mode can only be entered during PWRDN instruction execution if all enabled FastExternal Interrupt (EXxIN) pins are in their inactive level. Exiting this mode can be done by asserting one enabled EXxIN pin. Note: Register SYSCON cannot be changed after execution of the EINIT instruction. 18.2.1 Protected power down mode This mode is selected by clearing the bit PWDCFG in register SYSCON to `0'. In this mode, the Power Down mode can only be entered if the NMI (Non Maskable Interrupt) pin is externally pulled low while the PWRDN instruction is executed. This feature can be used in conjunction with an external power failure signal which pulls the NMI pin low when a power failure is imminent. The microcontroller will enter the NMI trap routine which can save the internal state into RAM. After the internal state has been saved, the trap routine may set a flag or write a certain bit pattern into specific RAM locations, and then execute the PWRDN instruction. If the NMI pin is still low at this time, Power Down mode will be entered, otherwise program execution continues. During power down the voltage delivered by the on-chip voltage regulator automatically lowers the internal logic supply down to 2.5 V, saving the power while the contents of the internal RAM and all registers will still be preserved. Exiting power down mode In this mode, the only way to exit Power Down mode is with an external hardware reset. The initialization routine (executed upon reset) can check the identification flag or bit pattern within RAM to determine whether the controller was initially switched on, or whether it was properly restarted from Power Down mode. 18.2.2 Interruptable power down mode This mode is selected by setting the bit PWDCFG in register SYSCON to `1'. Doc ID 8673 Rev. 3 181/239 Power reduction modes ST10F280 In this mode, the Power Down mode can be entered if enabled Fast External Interrupt pins (EXxIN pins, alternate functions of Port 2 pins, with x = 7...0) are in their inactive level. This inactive level is configured with the EXIxES bit field in the EXICON register, as follow: EXICON (F1C0h / E0h) 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0 EXI7ES EXI6ES EXI5ES EXI4ES EXI3ES EXI2ES EXI1ES EXI0ES R/W R/W R/W R/W R/W R/W R/W R/W Address: 0xF1C0H / E0h ESFR Reset: 0x000h Type: R/W EXIxES (x=7...0) External Interrupt x Edge Selection Field (x=7...0) 00: Fast external interrupts disabled: standard mode EXxIN pin not taken in account for entering/exiting Power Down mode. Interrupt on positive edge (rising) 01: Enter Power Down mode if EXiIN = `0', exit if EXxIN = `1' (referred as `high' active level) 10: Interrupt on negative edge (falling) Enter Power Down mode if EXiIN = `1', exit if EXxIN = `0' (referred as `low' active level) 11: Interrupt on any edge (rising or falling) Always enter Power Down mode, exit if EXxIN level changed. Exiting power down mode When Power Down mode is entered, the CPU and peripheral clocks are frozen, and the oscillator and PLL are stopped. Power Down mode can be exited by either asserting RSTIN or one of the enabled EXxIN pin (Fast External Interrupt). RSTIN must be held low until the oscillator and PLL have stabilized. EXxIN inputs are normally sampled interrupt inputs. However, the Power Down mode circuitry uses them as level-sensitive inputs. An EXxIN (x = 7...0) Interrupt Enable bit (bit CCxIE in respective CCxIC register) need not to be set to bring the device out of Power Down mode. An external RC circuit must be connected, as shown in the following figure: 182/239 Doc ID 8673 Rev. 3 ST10F280 Power reduction modes Figure 71. External RC circuit on RPD pin for exiting power down mode with external interrupt 9'' 67) 5 N:0:7\SLFDO 53' & P)7\SLFDO ("1($'5 To exit Power Down mode with external interrupt, an EXxIN pin has to be asserted for at least 40 ns (x = 7...0). This signal enables the internal oscillator and PLL circuitry, and also turns on the weak pull-down (see following figure). The discharging of the external capacitor provides a delay that allows the oscillator and PLL circuits to stabilize before the internal CPU and Peripheral clocks are enabled. When the Vpp voltage drops below the threshold voltage (about 2.5 V), the Schmitt trigger clears Q2 flip-flop, thus enabling the CPU and Peripheral clocks, and the device resumes code execution. If the Interrupt was enabled (bit CCxIE='1' in the respective CCxIC register) before entering Power Down mode, the device executes the interrupt service routine, and then resumes execution after the PWRDN instruction (see note below). If the interrupt was disabled, the device executes the instruction following PWRDN instruction, and the Interrupt Request Flag (bit CCxIR in the respective CCxIC register) remains set until it is cleared by software. Note: Due to internal pipeline, the instruction that follows the PWRDN instruction is executed before the CPU performs a call of the interrupt service routine when exiting power-down mode. Doc ID 8673 Rev. 3 183/239 Power reduction modes ST10F280 Figure 72. Simplified power down exit circuitry 9'' ' 4 4 FG4 (QWHU 3RZHU'RZQ 6WRSSOO VWRSRVFLOODWRU 9'' 3XOOXS 53' :HDN3XOOGRZQ aP$ ([WHUQDO LQWHUUXSW UHVHW 9'' &38DQG3HULSKHUDOVFORFNV ' 4 4 FG4 6\VWHPFORFN ("1($'5 Figure 73. Power down exit sequence when using an external interrupt (PLL x 2) ;7$/ &38FON LQWHUQDO 3RZHUGRZQ VLJQDO ([WHUQDO ,QWHUUXSW 53' ([LW3ZUG LQWHUQDO a9 GHOD\IRURVFLOODWRUSOO VWDELOL]DWLRQ ("1($'5 184/239 Doc ID 8673 Rev. 3 ST10F280 19 Special function register overview Special function register overview The following table lists all SFRs which are implemented in the ST10F280 in alphabetical order. Bit-addressable SFRs are marked with the letter "b" in column "Name". SFRs within the Extended SFR-Space (ESFRs) are marked with the letter "E" in column "Physical Address". An SFR can be specified by its individual mnemonic name. Depending on the selected addressing mode, an SFR can be accessed via its physical address (using the Data Page Pointers), or via its short 8-bit address (without using the Data Page Pointers). The reset value is defined as following: X: Means the full nibble is not defined at reset. x: Means some bit of the nibble are not defined at reset. Table 38. Name Special function registers listed by name Physical address 8-bit address Description Reset value ADCIC b FF98h CCh A/D Converter end of Conversion Interrupt Control Register - - 00h ADCON b FFA0h D0h A/D Converter Control Register 0000h ADDAT FEA0h 50h A/D Converter Result Register 0000h ADDAT2 F0A0h E 50h A/D Converter 2 Result Register 0000h ADDRSEL1 FE18h 0Ch Address Select Register 1 0000h ADDRSEL2 FE1Ah 0Dh Address Select Register 2 0000h ADDRSEL3 FE1Ch 0Eh Address Select Register 3 0000h ADDRSEL4 FE1Eh 0Fh Address Select Register 4 0000h ADEIC b FF9Ah CDh A/D Converter Overrun Error Interrupt Control Register - - 00h BUSCON0 b FF0Ch 86h Bus Configuration Register 0 0xx0h BUSCON1 b FF14h 8Ah Bus Configuration Register 1 0000h BUSCON2 b FF16h 8Bh Bus Configuration Register 2 0000h BUSCON3 b FF18h 8Ch Bus Configuration Register 3 0000h BUSCON4 b FF1Ah 8Dh Bus Configuration Register 4 0000h CAPREL FE4Ah 25h GPT2 Capture/Reload Register 0000h CC0 FE80h 40h CAPCOM Register 0 0000h b FF78h BCh CAPCOM Register 0 Interrupt Control Register - - 00h FE82h 41h CAPCOM Register 1 0000h b FF7Ah BDh CAPCOM Register 1 Interrupt Control Register - - 00h FE84h 42h CAPCOM Register 2 0000h b FF7Ch BEh CAPCOM Register 2 Interrupt Control Register - - 00h CC0IC CC1 CC1IC CC2 CC2IC Doc ID 8673 Rev. 3 185/239 Special function register overview Table 38. Name CC3 CC3IC CC4 CC4IC CC5 CC5IC CC6 CC6IC CC7 CC7IC CC8 CC8IC CC9 CC9IC CC10 CC10IC CC11 CC11IC CC12 CC12IC CC13 CC13IC CC14 CC14IC CC15 CC15IC CC16 CC16IC CC17 CC17IC CC18 CC18IC CC19 CC19IC 186/239 ST10F280 Special function registers listed by name (continued) Physical address 8-bit address Description Reset value FE86h 43h CAPCOM Register 3 0000h b FF7Eh BFh CAPCOM Register 3 Interrupt Control Register - - 00h FE88h 44h CAPCOM Register 4 0000h b FF80h C0h CAPCOM Register 4 Interrupt Control Register - - 00h FE8Ah 45h CAPCOM Register 5 0000h b FF82h C1h CAPCOM Register 5 Interrupt Control Register - - 00h FE8Ch 46h CAPCOM Register 6 0000h b FF84h C2h CAPCOM Register 6 Interrupt Control Register - - 00h FE8Eh 47h CAPCOM Register 7 0000h b FF86h C3h CAPCOM Register 7 Interrupt Control Register - - 00h FE90h 48h CAPCOM Register 8 0000h b FF88h C4h CAPCOM Register 8 Interrupt Control Register - - 00h FE92h 49h CAPCOM Register 9 0000h b FF8Ah C5h CAPCOM Register 9 Interrupt Control Register - - 00h FE94h 4Ah CAPCOM Register 10 0000h b FF8Ch C6h CAPCOM Register 10 Interrupt Control Register - - 00h FE96h 4Bh CAPCOM Register 11 0000h b FF8Eh C7h CAPCOM Register 11 Interrupt Control Register - - 00h FE98h 4Ch CAPCOM Register 12 0000h b FF90h C8h CAPCOM Register 12 Interrupt Control Register - - 00h FE9Ah 4Dh CAPCOM Register 13 0000h b FF92h C9h CAPCOM Register 13 Interrupt Control Register - - 00h FE9Ch 4Eh CAPCOM Register 14 0000h b FF94h CAh CAPCOM Register 14 Interrupt Control Register - - 00h FE9Eh 4Fh CAPCOM Register 15 0000h b FF96h CBh CAPCOM Register 15 Interrupt Control Register - - 00h FE60h 30h CAPCOM Register 16 0000h b F160h E B0h CAPCOM Register 16 Interrupt Control Register - - 00h FE62h 31h CAPCOM Register 17 0000h b F162h E B1h CAPCOM Register 17 Interrupt Control Register - - 00h FE64h 32h CAPCOM Register 18 0000h b F164h E B2h CAPCOM Register 18 Interrupt Control Register - - 00h FE66h 33h CAPCOM Register 19 0000h b F166h E B3h CAPCOM Register 19 Interrupt Control Register - - 00h Doc ID 8673 Rev. 3 ST10F280 Special function register overview Table 38. Name CC20 Special function registers listed by name (continued) Physical address 8-bit address Description Reset value FE68h 34h CAPCOM Register 20 0000h b F168h E B4h CAPCOM Register 20 Interrupt Control Register - - 00h FE6Ah 35h CAPCOM Register 21 0000h b F16Ah E B5h CAPCOM Register 21 Interrupt Control Register - - 00h FE6Ch 36h CAPCOM Register 22 0000h b F16Ch E B6h CAPCOM Register 22 Interrupt Control Register - - 00h FE6Eh 37h CAPCOM Register 23 0000h b F16Eh E B7h CAPCOM Register 23 Interrupt Control Register - - 00h FE70h 38h CAPCOM Register 24 0000h b F170h E B8h CAPCOM Register 24 Interrupt Control Register - - 00h FE72h 39h CAPCOM Register 25 0000h b F172h E B9h CAPCOM Register 25 Interrupt Control Register - - 00h FE74h 3Ah CAPCOM Register 26 0000h b F174h E BAh CAPCOM Register 26 Interrupt Control Register - - 00h FE76h 3Bh CAPCOM Register 27 0000h b F176h E BBh CAPCOM Register 27 Interrupt Control Register - - 00h FE78h 3Ch CAPCOM Register 28 0000h b F178h E BCh CAPCOM Register 28 Interrupt Control Register - - 00h FE7Ah 3Dh CAPCOM Register 29 0000h b F184h E C2h CAPCOM Register 29 Interrupt Control Register - - 00h FE7Ch 3Eh CAPCOM Register 30 0000h b F18Ch E C6h CAPCOM Register 30 Interrupt Control Register - - 00h FE7Eh 3Fh CAPCOM Register 31 0000h CC31IC b F194h E CAh CAPCOM Register 31 Interrupt Control Register - - 00h CCM0 b FF52h A9h CAPCOM Mode Control Register 0 0000h CCM1 b FF54h AAh CAPCOM Mode Control Register 1 0000h CCM2 b FF56h ABh CAPCOM Mode Control Register 2 0000h CCM3 b FF58h ACh CAPCOM Mode Control Register 3 0000h CCM4 b FF22h 91h CAPCOM Mode Control Register 4 0000h CCM5 b FF24h 92h CAPCOM Mode Control Register 5 0000h CCM6 b FF26h 93h CAPCOM Mode Control Register 6 0000h CCM7 b FF28h 94h CAPCOM Mode Control Register 7 0000h FE10h 08h CPU Context Pointer Register FC00h b FF6Ah B5h GPT2 CAPREL Interrupt Control Register - - 00h CC20IC CC21 CC21IC CC22 CC22IC CC23 CC23IC CC24 CC24IC CC25 CC25IC CC26 CC26IC CC27 CC27IC CC28 CC28IC CC29 CC29IC CC30 CC30IC CC31 CP CRIC Doc ID 8673 Rev. 3 187/239 Special function register overview Table 38. Name 188/239 ST10F280 Special function registers listed by name (continued) Physical address 8-bit address Description Reset value CSP FE08h 04h CPU Code Segment Pointer Register (read only) 0000h DP0L b F100h E 80h P0L Direction Control Register - - 00h DP0H b F102h E 81h P0h Direction Control Register - - 00h DP1L b F104h E 82h P1L Direction Control Register - - 00h DP1H b F106h E 83h P1h Direction Control Register - - 00h DP2 b FFC2h E1h Port 2 Direction Control Register 0000h DP3 b FFC6h E3h Port 3 Direction Control Register 0000h DP4 b FFCAh E5h Port 4 Direction Control Register - - 00h DP6 b FFCEh E7h Port 6 Direction Control Register - - 00h DP7 b FFD2h E9h Port 7 Direction Control Register - - 00h DP8 b FFD6h EBh Port 8 Direction Control Register - - 00h DPP0 FE00h 00h CPU Data Page Pointer 0 Register (10-bit) 0000h DPP1 FE02h 01h CPU Data Page Pointer 1 Register (10-bit) 0001h DPP2 FE04h 02h CPU Data Page Pointer 2 Register (10-bit) 0002h DPP3 FE06h 03h CPU Data Page Pointer 3 Register (10-bit) 0003h EXICON b F1C0h E E0h External Interrupt Control Register 0000h EXISEL b F1DAh E EDh External Interrupt Source Selection Register 0000h IDCHIP F07Ch E 3Eh Device Identifier Register (n is the device revision) 118nh IDMANUF F07Eh E 3Fh Manufacturer Identifier Register 0401h IDMEM F07Ah E 3Dh On-chip Memory Identifier Register 3080h IDPROG F078h E 3Ch Programming Voltage Identifier Register 0040h IDX0 b FF08h 84h MAC Unit Address Pointer 0 0000h IDX1 b FF0Ah 85h MAC Unit Address Pointer 1 0000h MAH FE5Eh 2Fh MAC Unit Accumulator - High Word 0000h MAL FE5Ch 2Eh MAC Unit Accumulator - Low Word 0000h MCW b FFDCh EEh MAC Unit Control Word 0000h MDC b FF0Eh 87h CPU Multiply Divide Control Register 0000h MDH FE0Ch 06h CPU Multiply Divide Register - High Word 0000h MDL FE0Eh 07h CPU Multiply Divide Register - Low Word 0000h MRW b FFDAh EDh MAC Unit Repeat Word 0000h MSW b FFDEh EFh MAC Unit Status Word 0200h ODP2 b F1C2h E E1h Port 2 Open Drain Control Register 0000h ODP3 b F1C6h E E3h Port 3 Open Drain Control Register 0000h Doc ID 8673 Rev. 3 ST10F280 Special function register overview Table 38. Name Special function registers listed by name (continued) Physical address 8-bit address Description Reset value ODP4 b F1CAh E E5h Port 4 Open Drain Control Register - - 00h ODP6 b F1CEh E E7h Port 6 Open Drain Control Register - - 00h ODP7 b F1D2h E E9h Port 7 Open Drain Control Register - - 00h ODP8 b F1D6h E EBh Port 8 Open Drain Control Register - - 00h ONES b FF1Eh 8Fh Constant Value 1's Register (read only) FFFFh P0L b FF00h 80h PORT0 Low Register (Lower half of PORT0) - - 00h P0H b FF02h 81h PORT0 High Register (Upper half of PORT0) - - 00h P1L b FF04h 82h PORT1 Low Register (Lower half of PORT1) - - 00h P1H b FF06h 83h PORT1 High Register (Upper half of PORT1) - - 00h P2 b FFC0h E0h Port 2 Register 0000h P3 b FFC4h E2h Port 3 Register 0000h P4 b FFC8h E4h Port 4 Register (8-bit) - - 00h P5 b FFA2h D1h Port 5 Register (read only) P6 b FFCCh E6h Port 6 Register (8-bit) - - 00h P7 b FFD0h E8h Port 7 Register (8-bit) - - 00h P8 b FFD4h EAh Port 8 Register (8-bit) - - 00h P5DIDIS b FFA4h D2h Port 5 Digital Disable Register 0000h XXXXh POCON0L F080h E 40h PORT0 Low Output Control Register (8-bit) - - 00h POCON0H F082h E 41h PORT0 High Output Control Register (8-bit) - - 00h POCON1L F084h E 42h PORT1 Low Output Control Register (8-bit) - - 00h POCON1H F086h E 43h PORT1 High Output Control Register (8-bit) - - 00h POCON2 F088h E 44h Port2 Output Control Register 0000h POCON3 F08Ah E 45h Port3 Output Control Register 0000h POCON4 F08Ch E 46h Port4 Output Control Register (8-bit) - - 00h POCON6 F08Eh E 47h Port6 Output Control Register (8-bit) - - 00h POCON7 F090h E 48h Port7 Output Control Register (8-bit) - - 00h POCON8 F092h E 49h Port8 Output Control Register (8-bit) - - 00h POCON20 F0AAh E 55h ALE, RD, WR Output Control Register (8-bit) - - 00h PECC0 FEC0h 60h PEC Channel 0 Control Register 0000h PECC1 FEC2h 61h PEC Channel 1 Control Register 0000h PECC2 FEC4h 62h PEC Channel 2 Control Register 0000h PECC3 FEC6h 63h PEC Channel 3 Control Register 0000h PECC4 FEC8h 64h PEC Channel 4 Control Register 0000h PECC5 FECAh 65h PEC Channel 5 Control Register 0000h Doc ID 8673 Rev. 3 189/239 Special function register overview Table 38. Name Special function registers listed by name (continued) Physical address 8-bit address Description Reset value PECC6 FECCh 66h PEC Channel 6 Control Register 0000h PECC7 FECEh 67h PEC Channel 7 Control Register 0000h PICON b F1C4h E E2h Port Input Threshold Control Register - - 00h PP0 F038h E 1Ch PWM Module Period Register 0 0000h PP1 F03Ah E 1Dh PWM Module Period Register 1 0000h PP2 F03Ch E 1Eh PWM Module Period Register 2 0000h PP3 F03Eh E 1Fh PWM Module Period Register 3 0000h 88h CPU Program Status Word 0000h PSW b FF10h PT0 F030h E 18h PWM Module Up/Down Counter 0 0000h PT1 F032h E 19h PWM Module Up/Down Counter 1 0000h PT2 F034h E 1Ah PWM Module Up/Down Counter 2 0000h PT3 F036h E 1Bh PWM Module Up/Down Counter 3 0000h PW0 FE30h 18h PWM Module Pulse Width Register 0 0000h PW1 FE32h 19h PWM Module Pulse Width Register 1 0000h PW2 FE34h 1Ah PWM Module Pulse Width Register 2 0000h PW3 FE36h 1Bh PWM Module Pulse Width Register 3 0000h PWMCON0 b FF30h 98h PWM Module Control Register 0 0000h PWMCON1 b FF32h 99h PWM Module Control Register 1 0000h PWMIC b F17Eh E BFh PWM Module Interrupt Control Register - - 00h QR0 F004h E 02h MAC Unit Offset Register QR0 0000h QR1 F006h E 03h MAC Unit Offset Register QR1 0000h QX0 F000h E 00h MAC Unit Offset Register QX0 0000h QX1 F002h E 01h MAC Unit Offset Register QX1 0000h RP0H b F108h E 84h System Start-up Configuration Register (read only) - - XXh S0BG FEB4h 5Ah Serial Channel 0 Baud Rate Generator Reload Register 0000h S0CON b FFB0h D8h Serial Channel 0 Control Register 0000h S0EIC b FF70h B8h Serial Channel 0 Error Interrupt Control Register - - 00h FEB2h 59h Serial Channel 0 Receive Buffer Register (read only) - - XXh S0RIC b FF6Eh B7h Serial Channel 0 Receive Interrupt Control Register - - 00h S0TBIC b F19Ch E CEh Serial Channel 0 Transmit Buffer Interrupt Control Register - - 00h S0RBUF 190/239 ST10F280 Doc ID 8673 Rev. 3 ST10F280 Special function register overview Table 38. Special function registers listed by name (continued) 8-bit address Description FEB0h 58h Serial Channel 0 Transmit Buffer Register (write only) 0000h b FF6Ch B6h Serial Channel 0 Transmit Interrupt Control Register - - 00h SP FE12h 09h CPU System Stack Pointer Register FC00h SSCBR F0B4h E 5Ah SSC Baud Rate Register 0000h Name S0TBUF S0TIC Physical address Reset value SSCCON b FFB2h D9h SSC Control Register 0000h SSCEIC b FF76h BBh SSC Error Interrupt Control Register - - 00h 59h SSC Receive Buffer (read only) BAh SSC Receive Interrupt Control Register - - 00h 58h SSC Transmit Buffer (write only) 0000h b FF72h B9h SSC Transmit Interrupt Control Register - - 00h STKOV FE14h 0Ah CPU Stack Overflow Pointer Register FA00h STKUN FE16h 0Bh CPU Stack Underflow Pointer Register FC00h b FF12h 89h CPU System Configuration Register FE50h 28h CAPCOM Timer 0 Register 0000h T01CON b FF50h A8h CAPCOM Timer 0 and Timer 1 Control Register 0000h T0IC b FF9Ch CEh CAPCOM Timer 0 Interrupt Control Register - - 00h T0REL FE54h 2Ah CAPCOM Timer 0 Reload Register 0000h T1 FE52h 29h CAPCOM Timer 1 Register 0000h b FF9Eh CFh CAPCOM Timer 1 Interrupt Control Register - - 00h T1REL FE56h 2Bh CAPCOM Timer 1 Reload Register 0000h T2 FE40h 20h GPT1 Timer 2 Register 0000h T2CON b FF40h A0h GPT1 Timer 2 Control Register 0000h T2IC b FF60h B0h GPT1 Timer 2 Interrupt Control Register - - 00h FE42h 21h GPT1 Timer 3 Register 0000h T3CON b FF42h A1h GPT1 Timer 3 Control Register 0000h T3IC b FF62h B1h GPT1 Timer 3 Interrupt Control Register - - 00h FE44h 22h GPT1 Timer 4 Register 0000h T4CON b FF44h A2h GPT1 Timer 4 Control Register 0000h T4IC b FF64h B2h GPT1 Timer 4 Interrupt Control Register - - 00h FE46h 23h GPT2 Timer 5 Register 0000h T5CON b FF46h A3h GPT2 Timer 5 Control Register 0000h T5IC b FF66h B3h GPT2 Timer 5 Interrupt Control Register - - 00h FE48h 24h GPT2 Timer 6 Register 0000h SSCRB SSCRIC SSCTB SSCTIC SYSCON T0 T1IC T3 T4 T5 T6 F0B2h E b FF74h F0B0h E Doc ID 8673 Rev. 3 XXXXh 0xx0h(1) 191/239 Special function register overview Table 38. ST10F280 Special function registers listed by name (continued) Physical address Name 8-bit address Description Reset value T6CON b FF48h A4h GPT2 Timer 6 Control Register 0000h T6IC b FF68h B4h GPT2 Timer 6 Interrupt Control Register - - 00h 28h CAPCOM Timer 7 Register 0000h T7 F050h E T78CON b FF20h 90h CAPCOM Timer 7 and 8 Control Register 0000h T7IC b F17Ah E BEh CAPCOM Timer 7 Interrupt Control Register - - 00h T7REL F054h E 2Ah CAPCOM Timer 7 Reload Register 0000h T8 F052h E 29h CAPCOM Timer 8 Register 0000h b F17Ch E BFh CAPCOM Timer 8 Interrupt Control Register - - 00h F056h E 2Bh CAPCOM Timer 8 Reload Register 0000h b FFACh D6h Trap Flag Register 0000h FEAEh 57h Watchdog Timer Register (read only) 0000h WDTCON b FFAEh D7h Watchdog Timer Control Register 00xxh(2) XP0IC b F186h E C3h CAN1 Module Interrupt Control Register - - 00h(3) XP1IC b F18Eh E C7h CAN2 Module Interrupt Control Register - - 00h(3) XP2IC b F196h E CBh XPWM Interrupt Control Register - - 00h(3) XP3IC b F19Eh E CFh PLL unlock Interrupt Control Register - - 00h(3) F024h E 12h XPER Configuration Register - - 05h 8Eh Constant Value 0's Register (read only) 0000h T8IC T8REL TFR WDT XPERCON ZEROS b FF1Ch 1. The system configuration is selected during reset. 2. Bit WDTR indicates a watchdog timer triggered reset. 3. The XPnIC Interrupt Control Registers control interrupt requests from integrated X-Bus peripherals. Some software controlled interrupt requests may be generated by setting the XPnIR bits (of XPnIC register) of the unused X-peripheral nodes. Table 39. X registers listed by name Name Physical address CAN1BTR EF04h CAN1 Bit Timing Register XXXXh CAN1CSR EF00h CAN1 Control/Status Register XX01h CAN1GMS EF06h CAN1 Global Mask Short XFXXh CAN1IR EF02h CAN1 Interrupt Register - - XXh EF14--EFF4h CAN1 Lower Arbitration register 1 to 15 XXXXh CAN1LAR1--15 Description CAN1LGML EF0Ah CAN1 Lower Global Mask Long XXXXh CAN1LMLM EF0Eh CAN1 Lower Mask Last Message XXXXh CAN1MCR1--15 EF10--EFF0h CAN1 Message Control Register 1 to 15 CAN1MO1--15 192/239 Reset value EF1x--EFFxh CAN1 Message Object 1 to 15 Doc ID 8673 Rev. 3 XXXXh XXXXh ST10F280 Special function register overview Table 39. X registers listed by name (continued) Name CAN1UAR1--15 Physical address Description EF12--EFF2h CAN1 Upper Arbitration Register 1 to 15 Reset value XXXXh CAN1UGML EF08h CAN1 Upper Global Mask Long XXXXh CAN1UMLM EF0Ch CAN1 Upper Mask Last Message XXXXh CAN2BTR EE04h CAN2 Bit Timing Register XXXXh CAN2CSR EE00h CAN2 Control/Status Register XX01h CAN2GMS EE06h CAN2 Global Mask Short XFXXh CAN2IR EE02h CAN2 Interrupt Register - - XXh EE14--EEF4h CAN2 Lower Arbitration register 1 to 15 XXXXh CAN2LAR1--15 CAN2LGML EE0Ah CAN2 Lower Global Mask Long XXXXh CAN2LMLM EE0Eh CAN2 Lower Mask Last Message XXXXh CAN2MCR1--15 EE10--EEF0h CAN2 Message Control Register 1 to 15 XXXXh CAN2MO1--15 EE1x--EEFxh CAN2 Message Object 1 to 15 XXXXh CAN2UAR1--15 EE12--EEF2h CAN2 Upper Arbitration Register 1 to 15 XXXXh CAN2UGML EE08h CAN2 Upper Global Mask Long XXXXh CAN2UMLM EE0Ch CAN2 Upper Mask Last Message XXXXh XADCMUX C384h Port5 or PortX10 ADC Input Selection (Read / Write) 0000h XDP9 C200h Direction Register Xport9 (Read / Write) 0000h XDP9CLR C204h Bit Clear Direction Register Xport9 (Write only) 0000h XDP9SET C202h Bit Set Direction Register Xport9 (Write only) 0000h XODP9 C300H Open Drain Control Register Xport9 (Read / Write) 0000h XODP9CLR C304H Bit clear Open drain Control register Xport9 (Write only) 0000h XODP9SET C302H Bit Set Open Drain Control Register Xport9 (Write only) 0000h XP10 C380h Read only Data register Xport10 (Read only) 0000h XP10DIDIS C382h Xport10 Schmitt Trigger Input Selection (Read / Write) 0000h XP9 C100h Data Register Xport9 (Read / Write) 0000h XP9CLR C104h Bit Clear Data Register Xport9 (Write only) 0000h XP9SET C102h Bit Set Data Register Xport9 (Write only) 0000h XPOLAR EC04h XPWM Channel Polarity Control Register 0000h XPP0 EC20h XPWM Period Register 0 0000h XPP1 EC22h XPWM Period Register 1 0000h XPP2 EC24H XPWM Period Register 2 0000h XPP3 EC26h XPWM Period Register 3 0000h Doc ID 8673 Rev. 3 193/239 Special function register overview Table 39. 19.1 ST10F280 X registers listed by name (continued) Name Physical address Reset value XPT0 EC10h XPWM Timer Counter Register 0 0000h XPT1 EC12h XPWM Timer Counter Register 1 0000h XPT2 EC14h XPWM Timer Counter Register 2 0000h XPT3 EC16h XPWM Timer Counter Register 3 0000h XPW0 EC30h XPWM Pulse Width Register 0 0000h XPW1 EC32h XPWM Pulse Width Register 1 0000h XPW2 EC34h XPWM Pulse Width Register 2 0000h XPW3 EC36h XPWM Pulse Width Register 3 0000h XPWMCON0 EC00h XPWM Control Register 0 0000h XPWMCON1 EC02h XPWM Control Register 1 0000h XTCR C000h Xtimer Control Register (Read / Write) 0000h XTCVR C006h Xtimer Current Value Register (Read / Write) 0000h XTEVR C004h Xtimer End Value Register (Read / Write) 0000h XTSVR C002h Xtimer Start Value Register (Read / Write) 0000h Description Identification registers The ST10F280 has four Identification registers, mapped in ESFR space. These register contain: A manufacturer identifier, A chip identifier, with its revision, A internal memory and size identifier and programming voltage description. IDMANUF 15 14 13 12 11 10 9 8 MANUF 7 6 5 4 3 2 1 0 0 0 0 0 1 R Address: F07Eh / 3Fh ESFR Reset: 0x0401h Type: R MANUF Manufacturer Identifier 020h: STMicroelectronics Manufacturer (JTAG worldwide normalization). 194/239 Doc ID 8673 Rev. 3 ST10F280 Special function register overview IDCHIP 15 14 13 12 11 Address: F07Ch / 3Eh ESFR Reset: 0x118Xh Type: R 10 9 8 7 6 5 4 3 2 1 0 2 1 0 2 1 0 CHIPID REVID R R REVID Device Revision Identifier CHIPID Device Identifier 118h: ST10F280 identifier. IDMEM 15 14 13 12 11 10 9 8 7 6 5 MEMTYP MEMSIZE R R Address: 0xF07Ah / 3Dh ESFR Reset: 0x3080h Type: R 4 3 MEMSIZE Internal Memory Size is calculated using the following formula: Size = 4 x [MEMSIZE] (in K Byte) 080h for ST10F280 (512K Byte) MEMTYP Internal Memory Type 3h for ST10F280 (Flash memory). IDPROG 15 14 13 12 11 10 9 8 7 6 5 4 3 PROGVPP PROGVDD R R Address: F078h / 3Ch ESFR Reset: 0x0040h Type: R PROGVDD Programming VDD Voltage VDD voltage when programming EPROM or FLASH devices is calculated using the following formula: VDD = 20 x [PROGVDD] / 256 (volts) 40h for ST10F280 (5V). PROGVPP Programming VPP Voltage (no need of external VPP) 00h Note: 1. All identification words are read only registers. Doc ID 8673 Rev. 3 195/239 Special function register overview 19.2 ST10F280 System configuration registers The ST10F280 has registers used for different configuration of the overall system. These registers are described below. 12 11 10 9 8 7 6 5 4 3 2 STKSZ SGTDIS ROMEN BYTDIS CLKEN WRCFG CSCFG PWD CFG OWD DIS BDR STEN XPEN VISIBLE XPER-SHARE 15 ROMS1 SYSCON 14 13 R/W R/W R/W R/W R/W(1) R/W R/W R/W R/W R/W R/W R/W R/W(1) R/W(1) 1 0 1. These bit are set directly or indirectly according to PORT0 and EA pin configuration during reset sequence. Address: 0xFF12h / 89h SFR Reset: 0x0XX0h Type: R/W Note: Register SYSCON cannot be changed after execution of the EINIT instruction. XPER-SHARE XBUS Peripheral Share Mode Control 0: External accesses to XBUS peripherals are disabled 1: XBUS peripherals are accessible via the external bus during hold mode VISIBLE Visible Mode Control 0: Accesses to XBUS peripherals are done internally 1: XBUS peripheral accesses are made visible on the external pins XPEN XBUS Peripheral Enable bit 0: Accesses to the on-chip X-Peripherals and XRAM are disabled 1: The on-chip X-Peripherals are enabled. BDRSTEN Bidirectional Reset Enable 0: RSTIN pin is an input pin only. (SW Reset or WDT Reset have no effect on this pin) 1: RSTIN pin is a bidirectional pin. This pin is pulled low during 1024 TCL during reset sequence. OWDDIS Oscillator Watchdog Disable Control 0: Oscillator Watchdog (OWD) is enabled. If PLL is bypassed, the OWD monitors XTAL1 activity. If there is no activity on XTAL1 for at least 1 s, the CPU clock is switched automatically to PLL's base frequency (2 to 10MHz). 1: OWD is disabled. If the PLL is bypassed, the CPU clock is always driven by XTAL1 signal. The PLL is turned off to reduce power supply current. PWDCFG Power Down Mode Configuration Control 0: Power Down Mode can only be entered during PWRDN instruction execution if NMI pin is low, otherwise the instruction has no effect. Exit power down only with reset. 1: Power Down Mode can only be entered during PWRDN instruction execution if all enabled fast external interrupt EXxIN pins are in their inactive level. Exiting this mode can be done by asserting one enabled EXxIN pin or with external reset. 196/239 Doc ID 8673 Rev. 3 ST10F280 Special function register overview CSCFG Chip Select Configuration Control 0: Latched Chip Select lines: CSx change 1 TCL after rising edge of ALE 1: Unlatched Chip Select lines: CSx change with rising edge of ALE. WRCFG Write Configuration Control (Inverted copy of bit WRC of RP0H) 0: Pins WR and BHE retain their normal function 1: Pin WR acts as WRL, pin BHE acts as WRH. CLKEN System Clock Output Enable (CLKOUT) 0: CLKOUT disabled: pin may be used for general purpose I/O 1: CLKOUT enabled: pin outputs the system clock signal. BYTDIS Disable/Enable Control for Pin BHE (Set according to data bus width) 0: Pin BHE enabled 1: Pin BHE disabled, pin may be used for general purpose I/O. ROMEN Internal Memory Enable (Set according to pin EA during reset) 0: Internal Memory disabled: accesses to the Memory area use the external bus 1: Internal Memory enabled. SGTDIS Segmentation Disable/Enable Control 0: Segmentation enabled (CSP is saved/restored during interrupt entry/exit) 1: Segmentation disabled (Only IP is saved/restored). ROMS1 Internal Flash Memory Mapping 0: Internal Flash Memory area mapped to segment 0 (00'0000H...00'7FFFH) 1: Internal Flash Memory area mapped to segment 1 (01'0000H...01'7FFFH). STKSZ System Stack Size Selects the size of the system stack (in the internal RAM) from 32 to 1024 words. Table 40. Stack size selection <STKSZ> Stack size (words) 000b 256 00'FBFEh...00'FA00h (Default after Reset) SP.8...SP.0 001b 128 00'FBFEh...00'FB00h SP.7...SP.0 010b 64 00'FBFEh...00'FB80h SP.6...SP.0 011b 32 00'FBFEh...00'FBC0h SP.5...SP.0 100b 512 00'FBFEh...00'F800h (not for 1K Byte IRAM) SP.9...SP.0 101b - Reserved. Do not use this combination - 110b - Reserved. Do not use this combination - 111b 1024 Internal RAM addresses (words) of physical stack 00'FDFEh...00'FX00h (Note: No circular stack) 00'FX00h represents the lower IRAM limit, i.e. 1K Byte: 00'FA00h, 2K Byte: 00'F600h, 3K Byte: 00'F200h Doc ID 8673 Rev. 3 Significant bits of stack pointer SP SP.11...SP.0 197/239 Special function register overview ST10F280 13 12 11 10 9 8 CSREN0 RDYPOL0 RDYEN0 - BUS ACT0 ALE CTL0 - R/W R/W R/W R/W 7 R/W(1) R/W(1) 5 4 BTYP RWDC0 14 MTTC0 15 CSWEN0 BUSCON0 6 3 2 1 MCTC R/W(2) R/W R/W R/W 0 1. BUSCON0 is initialized with 0000h, if EA pin is high during reset. If EA pin is low during reset, bit BUSACT0 and ALECTRL0 are set ('1') and bit field BTYP is loaded with the bus configuration selected via PORT0. 2. BTYP (bit 6 and 7) are set according to the configuration of the bit l1 and l2 of PORT0 latched at the end of the reset sequence. Address: 0xFF0Ch / 86h SFR Reset: 0x0XX0h Type: R/W 9 8 CSREN1 RDYPOL1 RDYEN1 - - R/W R/W R/W R/W Address: 0xFF14h / 8Ah SFR Reset: 0x0000h Type: R/W R/W R/W 5 4 BTYP RWDC1 10 MCTC R/W R/W R/W R/W 5 4 BTYP RWDC2 11 MTTC1 12 MTTC2 13 ALECTL1 14 BUSACT1 15 CSWEN1 BUSCON1 7 6 3 2 MCTC R/W R/W R/W R/W 1 0 1 0 15 14 13 12 11 10 9 8 CSWEN2 CSREN2 RDYPOL2 RDYEN2 - BUSACT2 ALECTL2 BUSCON2 - R/W R/W R/W R/W R/W R/W Address: 0xFF16h / 8Bh SFR Reset: 0x0000h Type: R/W 198/239 Doc ID 8673 Rev. 3 7 6 3 2 ST10F280 Special function register overview 9 8 CSREN3 RDYPOL3 RDYEN3 - - R/W R/W R/W R/W Address: 0xFF18h / 8Ch SFR Reset: 0x0000h Type: R/W R/W R/W 5 4 BTYP RWDC3 10 MCTC R/W R/W R/W R/W 5 4 BTYP RWDC4 11 MTTC3 12 MTTC4 13 ALECTL3 14 BUSACT3 15 CSWEN3 BUSCON3 7 6 3 2 MCTC R/W R/W R/W R/W 1 0 1 0 15 14 13 12 11 10 9 8 CSWEN4 CSREN4 RDYPOL4 RDYEN4 - BUSACT4 ALECTL4 BUSCON4 - R/W R/W R/W R/W R/W R/W Address: 0xFF14h / 8Dh SFR Reset: 0x0000h Type: R/W MCTC RWDCx MTTCx BTYP 7 6 3 2 Memory Cycle Time Control (Number of memory cycle time wait states) 0000: 15 wait states (Nber = 15 [MCTC]) ... 1111: No wait states Read/Write Delay Control for BUSCONx 0: With read/write delay: activate command 1 TCL after falling edge of ALE 1: No read/write delay: activate command with falling edge of ALE Memory Tristate Time Control 0: 1 wait state 1: No wait state External Bus Configuration 00: 8-bit Demultiplexed Bus 01: 8-bit Multiplexed Bus 10: 16-bit Demultiplexed Bus 11: 16-bit Multiplexed Bus Note: For BUSCON0, BTYP bit-field is defined via PORT0 during reset. ALECTLx ALE Lengthening Control 0: Normal ALE signal 1: Lengthened ALE signal BUSACTx Bus Active Control 0: External bus disabled 1: External bus enabled (within the respective address window, see ADDRSEL) Doc ID 8673 Rev. 3 199/239 Special function register overview RDYENx RDYPOLx ST10F280 READY Input Enable 0: External bus cycle is controlled by bit field MCTC only 1: External bus cycle is controlled by the READY input signal Ready Active Level Control 0: Active level on the READY pin is low, bus cycle terminates with a `0' on READY pin, 1: Active level on the READY pin is high, bus cycle terminates with a `1' on READY pin. CSRENx Read Chip Select Enable 0: The CS signal is independent of the read command (RD) 1: The CS signal is generated for the duration of the read command CSWENx Write Chip Select Enable 0: The CS signal is independent of the write command (WR,WRL,WRH) 1: The CS signal is generated for the duration of the write command RP0H 15 14 13 12 11 10 9 8 - - - - - - - - 7 6 5 4 3 2 1 SALSEL CSSEL WRC R (1)(2) R (2) R (2) R(2) 1. RP0H.7 to RP0H.5 bits are loaded only during a long hardware reset. As pull-up resistors are active on each Port P0H pins during reset, RP0H default value is "FFh" 2. These bits are set according to Port 0 configuration during any reset sequence. Address: 0xF108h / 84h ESFR Reset: 0x--XXh Type: R WRC CSSEL SALSEL 200/239 Write Configuration Control 0: Pin WR acts as WRL, pin BHE acts as WRH 1: Pins WR and BHE retain their normal function Chip Select Line Selection (Number of active CS outputs) 00: 3 CS lines: CS2...CS0 01: 2 CS lines: CS1...CS0 10: No CS lines at all 11: 5 CS lines: CS4...CS0 (Default without pull-downs) Segment Address Line Selection (Number of active segment address outputs) 00: 4-bit segment address: A19...A16 01: No segment address lines at all 10: 8-bit segment address: A23...A16 11: 2-bit segment address: A17...A16 (Default without pull-downs) Doc ID 8673 Rev. 3 0 CLKSEL ST10F280 Special function register overview CLKSEL System Clock Selection 000: fCPU = 2.5 x fOSC 001: fCPU = 0.5 x fOSC 010: fCPU = 10 x fOSC 011: fCPU = fOSC 100: fCPU = 5 x fOSC 101: fCPU = 2 x fOSC 110: fCPU = 3 x fOSC 111: fCPU = 4 x fOSC EXICON 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0 EXI7ES EXI6ES EXI5ES EXI4ES EXI3ES EXI2ES EXI1ES EXI0ES R/W R/W R/W R/W R/W R/W R/W R/W Address: 0xF1C0h / E0h ESFR Reset: 0x0000h Type: R/W EXIxES(x=7...0) External Interrupt x Edge Selection Field (x=7...0) 00: Fast external interrupts disabled: standard mode EXxIN pin not taken in account for entering/exiting Power Down mode. 01: Interrupt on positive edge (rising) Enter Power Down mode if EXiIN = `0', exit if EXxIN = `1' (referred as `high' active level) 10: Interrupt on negative edge (falling) Enter Power Down mode if EXiIN = `1', exit if EXxIN = `0' (referred as `low' active level) 11: Interrupt on any edge (rising or falling) Always enter Power Down mode, exit if EXxIN level changed. EXISEL 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0 EXI7SS EXI6SS EXI5SS EXI4SS EXI3SS EXI2SS EXI1SS EXI0SS R/W R/W R/W R/W R/W R/W R/W R/W Address: 0xF1DAh / EDh ESFR Reset: 0x0000h Type: R/W EXIxSS External Interrupt x Source Selection (x=7...0) 00: Input from associated Port 2 pin. 01: Input from "alternate source". 10: Input from Port 2 pin ORed with "alternate source". 11: Input from Port 2 pin ANDed with "alternate source". Doc ID 8673 Rev. 3 201/239 Special function register overview ST10F280 EXIxSS Port 2 pin Alternate source 0 P2.8 CAN1_RxD 1 P2.9 CAN2_RxD 2...7 P2.10...15 Not used (zero) XP3IC 15 14 13 12 11 10 9 8 - - - - - - - - 7 R/W Address: 0xF19Eh / CFh ESFR Reset: 0x--00h Type: R/W Note: 6 5 XP3IR XP3IE 4 3 2 1 0 XP3ILVL GLVL R/W R/W R/W XP3IC register has the same bit field as xxIC interrupt registers xxIC 15 14 13 12 11 10 9 8 7 6 - - - - - - - - xxIR xxIE ILVL GLVL R/W R/W R/W R/W Address: 0xyyyyh / zzh SFR Reset: 0x--00h Type: R/W 5 4 3 2 GLVL Group Level Defines the internal order for simultaneous requests of the same priority. 11: Highest group priority 00: Lowest group priority ILVL Interrupt Priority Level Defines the priority level for the arbitration of requests. 1111: Highest priority level 0000: Lowest priority level xxIE Interrupt Enable Control Bit (individually enables/disables a specific source) 0: Interrupt Request is disabled 1: Interrupt Request is enabled xxIR Interrupt Request Flag 0: No request pending 1: This source has raised an interrupt request 202/239 Doc ID 8673 Rev. 3 1 0 ST10F280 Special function register overview XPERCON 10 9 8 7 6 5 - - - - - - - - - - - Address: 0xF024h / 12h ESFR Reset: 0x--05h Type: R/W 4 3 2 1 0 CAN1EN 11 CAN2EN 12 XRAMEN 13 XPERCONEN3 14 XPWMEN 15 R/W R/W R/W R/W R/W CAN1EN CAN1 Enable Bit 0: Accesses to the on-chip CAN1 XPeripheral and its functions are disabled. P4.5 and P4.6 pins can be used as general purpose I/Os. Address range 00'EF00h00'EFFFh is only directed to external memory if CAN2EN and XPWM bits are cleared also. 1: The on-chip CAN1 XPeripheral is enabled and can be accessed. CAN2EN CAN2 Enable Bit 0: Accesses to the on-chip CAN2 XPeripheral and its functions are disabled. P4.4 and P4.7 pins can be used as general purpose I/Os. Address range 00'EE00h00'EEFFh is only directed to external memory if CAN1EN and XPWM bits are cleared also. T1: he on-chip CAN2 XPeripheral is enabled and can be accessed. XRAMEN XRAM Enable Bit 0: Accesses to the on-chip 16K Byte XRAM are disabled, external access performed. 1: The on-chip 16K Byte XRAM is enabled and can be accessed. XPERCONEN3 XPORT9,XTIMER, XPORT10, XADCMUX Enable Bit 0: Accesses to the XPORT9, XTIMER, XPORT10, XADCMUX peripherals are disabled, external access performed. 1: The on-chip XPORT9, XTIMER, XPORT10, XADCMUX peripherals are enabled and can be accessed. XPWMEN XPWM Enable Bit 0: Accesses to the on-chip XPWM are disabled, external access performed. Address range 00'EC00h-00'ECFFh is only directed to external memory if CAN1EN and CAN2EN are `0' also 1: The on-chip XPWM is enabled and can be accessed. Note: When both CAN and XPWM are disabled via XPERCON setting, then any access in the address range 00'EC00h 00'EFFFh will be directed to external memory interface, using the BUSCONx register corresponding to address matching ADDRSELx register. P4.4 and P4.7 Doc ID 8673 Rev. 3 203/239 Special function register overview ST10F280 can be used as General Purpose I/O when CAN2 is not enabled, and P4.5 and P4.6 can be used as General Purpose I/O when CAN1 is not enabled. The default XPER selection after Reset is: XCAN1 is enabled, XCAN2 is disabled, XRAM is enabled, XPORT9, XTIMER, XPORT10, XPWM are disabled. Register XPERCON cannot be changed after the global enabling of XPeripherals, i.e. after setting of bit XPEN in SYSCON register. 204/239 Doc ID 8673 Rev. 3 ST10F280 Electrical characteristics 20 Electrical characteristics 20.1 Absolute maximum ratings Stresses the device above the rating listed in the Table 41: Absolute maximum ratings may cause permanent damage to the device. This is a stress rating only and functional operation of the device at these or any other conditions above those indicated in the operational sections of this specification is not implied. Exposure to absolute maximum rating conditions for extended periods may affect device reliability. During overload conditions (VIN > VDD or VIN < VSS) the voltage on pins with respect to ground (VSS) must not exceed the values defined Table 41. Table 41. Absolute maximum ratings Symbol Parameter Unit -0.5, +6.5 V VDD Voltage on VDD pins with respect to ground VIO Voltage on any pin with respect to ground -0.5, (VDD +0.5) V Voltage on VAREF pin with respect to ground -0.3, (VDD +0.3) V VAREF IOV Input Current on any pin during overload condition -10, +10 mA ITOV Absolute Sum of all input currents during overload condition |100 mA| mA Ptot Power Dissipation 1.5 W TA Ambient Temperature under bias -40, +125 C Storage Temperature -65, +150 C Tstg 20.2 Value Parameter interpretation The parameters listed in the following tables represent the characteristics of the ST10F280 and its demands on the system. Where the ST10F280 logic provides signals with their respective timing characteristics, the symbol "CC" for Controller Characteristics, is included in the "Symbol" column. Where the external system must provide signals with their respective timing characteristics to the ST10F280, the symbol "SR" for System Requirement, is included in the "Symbol" column. 20.3 DC characteristics VDD = 5 V 10%, VSS = 0 V, fCPU = 40 MHz, Reset active, TA = -40C to 125C Table 42. DC characteristics Symbol Parameter Test conditions Min. Max. Unit VIL SR Input low voltage - -0.5 0.2 VDD - 0.1 V VILS SR Input low voltage (special threshold) - -0.5 2.0 V Doc ID 8673 Rev. 3 205/239 Electrical characteristics Table 42. ST10F280 DC characteristics (continued) Symbol Parameter Test conditions Min. Max. Unit - 0.2 VDD + 0.9 VDD + 0.5 V Input high voltage (all except RSTIN and XTAL1) VIH SR VIH1 SR Input high voltage RSTIN - 0.6 VDD VDD + 0.5 V VIH2 SR Input high voltage XTAL1 - 0.7 VDD VDD + 0.5 V VIHS SR Input high voltage (special threshold) - 0.8 VDD 0.2 VDD + 0.5 V HYS Input Hysteresis (special threshold)(1) - 400 - mV IOL = 2.4mA - 0.45 V IOL1 = 1.6mA - 0.45 V IOH = -500A 0.9 VDD - V IOH = -2.4mA 2.4 - V IOH = - 250A 0.9 VDD - V IOH = - 1.6mA 2.4 - V Output low voltage (PORT0, PORT1, Port 4, ALE, RD, WR, BHE, CLKOUT, RSTOUT)(2) VOL CC VOL1 CC Output low voltage (all other outputs)(2) VOH CC VOH1 CC Output high voltage (all other outputs)(2)(3) Output high voltage (PORT0, PORT1, Port4, ALE, RD, WR, BHE, CLKOUT, RSTOUT)(2) IOZ1 CC Input leakage current (Port 5, XPort 10) 0V < VIN < VDD - 0.2 A IOZ2 CC Input leakage current (all other) 0V < VIN < VDD - 1 A IOV SR Overload current(1) (4) - 5 mA - 50 250 k VOUT = 2.4V - -40 A VOUT = VOLmax -500 - A VOUT = VOLmax 40 - A VOUT = 2.4V - 500 A VOUT = 2.4V - -40 A VOUT = VOL1max -500 - A VIN = VIHmin(6) - -10 A VIN = VILmax(7) -100 - A 0V < VIN < VDD - 20 A f = 1MHz, TA = 25C - 10 pF RRST IRWH CC RSTIN pull-up resistor(1) Read / Write inactive current(5)(6) IRWL Read / Write active current IALEL ALE inactive current(5)(6) IALEH ALE active current(5)(7) current(5)(6) IP6H Port 6 inactive IP6L Port 6 active current(5)(7) IP0H (5)(7) PORT0 configuration current(5) IP0L IIL CC XTAL1 input current CIO CC Pin capacitance (digital inputs / outputs)(1)(5) ICC Power supply current(8) RSTIN = VIH1 fCPU in [MHz] - 30 + 3.3 x fCPU mA IID Idle mode supply current(9) RSTIN = VIH1 fCPU in [MHz] - 20 + fCPU mA IPD Power-down mode supply current(10) VDD = 5.5V TA = 55C - 200 A 1. Partially tested, guaranteed by design characterization. 206/239 Doc ID 8673 Rev. 3 ST10F280 Electrical characteristics 2. ST10F280 pins are equipped with low-noise output drivers which significantly improve the device's EMI performance. These low-noise drivers deliver their maximum current only until the respective target output level is reached. After this, the output current is reduced. This results in increased impedance of the driver, which attenuates electrical noise from the connected PCB tracks. The current specified in column "Test Conditions" is delivered in any cases. 3. This specification is not valid for outputs which are switched to open drain mode. In this case the respective output will float and the voltage results from the external circuitry. 4. Overload conditions occur if the standard operating conditions are exceeded, i.e. the voltage on any pin exceeds the specified range (i.e. VOV > VDD+0.5V or VOV <0.5V). The absolute sum of input overload currents on all port pins may not exceed 50mA. The supply voltage must remain within the specified limits. 5. This specification is only valid during Reset, or during Hold-mode or Adapt-mode. Port 6 pins are only affected if they are used for CS output and if their open drain function is not enabled. 6. The maximum current may be drawn while the respective signal line remains inactive 7. The minimum current must be drawn in order to drive the respective signal line active. 8. The power supply current is a function of the operating frequency. This dependency is illustrated in the Figure 70. These parameters are tested at VDDmax and 40MHz CPU clock with all outputs disconnected and all inputs at VIL or VIH. The chip is configured with a demultiplexed 16-bit bus, direct clock drive, 5 chip select lines and 2 segment address lines, EA pin is low during reset. After reset, PORT 0 is driven with the value `00CCh' that produces infinite execution of NOP instruction with 15 wait-state, R/W delay, memory tristate wait state, normal ALE. Peripherals are not activated 9. Idle mode supply current is a function of the operating frequency. This dependency is illustrated in the Figure 70. These parameters are tested at VDDmax and 40MHz CPU clock with all outputs disconnected and all inputs at VIL or VIH. 10. This parameter value includes leakage currents. With all inputs (including pins configured as inputs) at 0 V to 0.1V or at VDD - 0.1V to VDD, VREF = 0V, all outputs (including pins configured as outputs) disconnected. ,>P$@ Figure 74. Supply / idle current as a function of operating frequency P$ ,&&PD[ ,&&W\S ,,'PD[ P$ ,,'W\S I&38>0+]@ ("1($'5 Doc ID 8673 Rev. 3 207/239 Electrical characteristics 20.3.1 ST10F280 A/D converter characteristics VDD = 5 V 10%, VSS = 0 V, TA = -40C to 125C, 4.0 V VAREF VDD + 0.1 V; VSS0.1 V VAGND VSS + 0.2 V Table 43. Symbol A/D converter characteristics Test Condition Parameter VAREF SR Analog Reference voltage VAIN SR Analog input voltage IAREF CC Min. Max Unit 4.0 VDD + 0.1 V (1)(2) VAGND VAREF V Reference supply current running mode power-down mode (3) - - 500 1 A A pF pF CAIN CC ADC input capacitance Not sampling Sampling (3) - - 10 15 tS CC Sample time (4)(5) 48 TCL 1 536 TCL tC CC Conversion time (6)(5) 388 TCL 2 884 TCL Differential Nonlinearity (7) -0.5 +0.5 LSB Integral Nonlinearity (7) -1.5 +1.5 LSB -1.0 +1.0 LSB LSB DNL INL CC CC OFS CC Offset Error (7) TUE CC Total unadjusted error (7) -2.0 +2.0 RASRC SR Internal resistance of analog source tS in [ns] (4)(3) - (tS / 150) 0.25 K CC Coupling Factor between inputs (8)(3) - 1/500 k 1. VAIN may exceed VAGND or VAREF up to the absolute maximum ratings. However, the conversion result in these cases will be X000h or X3FFh, respectively. 2. To remove noise and undesirable high frequency components from the analog input signal, a low-pass filter must be connected at the ADC input. The cut-off frequency of this filter should avoid 2 opposite transitions during the ts sampling time of the ST10 ADC: - fcut-off 1 / 5 ts to 1/10 ts where ts is the sampling time of the ST10 ADC and is not related to the Nyquist frequency determined by the tc conversion time. 3. Partially tested, guaranteed by design characterization. 4. During the tS sample time the input capacitance Cain can be charged/discharged by the external source. The internal resistance of the analog source must allow the capacitance to reach its final voltage level within the tS sample time. After the end of the tS sample time, changes of the analog input voltage have no effect on the conversion result. Values for the tSC sample clock depend on the programming. Referring to the tC conversion time formula of section 20.3.2 and to the table 39 of page 156: - tS min = 2 tSC min = 2 tCC min = 2 x 24 x TCL = 48 TCL - tS max = 2 tSC max = 2 x 8 tCC max = 2 x 8 x 96 TCL = 1536 TCL TCL is defined in section 20.4.5 at page 159. 5. This parameter is fixed by ADC control logic. 6. The conversion time formula is: - tC = 14 tCC + tS + 4 TCL (= 14 tCC + 2 tSC + 4 TCL) The tC parameter includes the tS sample time, the time for determining the digital result and the time to load the result register with the result of the conversion. Values for the tCC conversion clock depend on the programming. Referring to the table 39 of page 156: - tC min = 14 tCC min + tS min + 4 TCL = 14 x 24 x TCL + 48 TCL + 4 TCL = 388 TCL - tC max = 14 tCC max + tS max + 4 TCL = 14 x 96 TCL + 1536 TCL + 4 TCL = 2884 TCL 208/239 Doc ID 8673 Rev. 3 ST10F280 Electrical characteristics 7. DNL, INL, TUE are tested at VAREF = 5.0V, VAGND = 0V, VCC = 4.9V. It is guaranteed by design characterization for all other voltages within the defined voltage range. `LSB' has a value of VAREF / 1024. The specified TUE is guaranteed only if an overload condition (see IOV specification) occurs on maximum 2 not selected analog input pins and the absolute sum of input overload currents on all analog input pins does not exceed 10mA. 8. The coupling factor is measured on a channel while an overload condition occurs on the adjacent not selected channel with an absolute overload current less than 10mA. 20.3.2 Conversion timing control When a conversion is started, first the capacitances of the converter are loaded via the respective analog input pin to the current analog input voltage. The time to load the capacitances is referred to as the sample time ts. Next the sampled voltage is converted to a digital value in 10 successive steps, which correspond to the 10-bit resolution of the ADC. The next 4 steps are used for equalizing internal levels (and are keep for exact timing matching with the 10-bit A/D converter module implemented in ST10F168). The current that has to be drawn from the sources for sampling and changing charges depends on the time that each respective step takes, because the capacitors must reach their final voltage level within the given time, at least with a certain approximation. The maximum current, however, that a source can deliver, depends on its internal resistance. The sample time tS (= 2 tSC) and the conversion time tC (= 14 tCC + 2 tSC + 4 TCL) can be programmed relatively to the ST10F280 CPU clock. This allows adjusting the A/D converter of the ST10F280 to the properties of the system: Fast Conversion can be achieved by programming the respective times to their absolute possible minimum. This is preferable for scanning high frequency signals. The internal resistance of analog source and analog supply must be sufficiently low, however. High Internal Resistance can be achieved by programming the respective times to a higher value, or the possible maximum. This is preferable when using analog sources and supply with a high internal resistance in order to keep the current as low as possible. However, the conversion rate in this case may be considerably lower. The conversion times are programmed via the upper four bit of register ADCON. Bit field ADCTC (conversion time control) selects the basic conversion clock tCC, used for the 14 steps of converting. The sample time tS is a multiple of this conversion time and is selected by bit field ADSTC (sample time control). The table below lists the possible combinations. The timings refer to the unit TCL, where fCPU = 1/2 TCL. Table 44. ADC sampling and conversion timing Conversion clock tCC ADCTC Sample clock tSC ADSTC tSC = At fCPU = 40MHz and ADCTC = 00 00 tCC 0.3s Reserved 01 tCC x 2 0.6s TCL x 96 1.2 s 10 tCC x 4 1.2s TCL x 48 0.6 s 11 tCC x 8 2.4s TCL = 1/2 x fXTAL At fCPU = 40MHz 00 TCL x 24 0.3s 01 Reserved, do not use 10 11 Doc ID 8673 Rev. 3 209/239 Electrical characteristics ST10F280 A complete conversion will take 14 tCC + 2 tSC + 4 TCL (fastest conversion rate = 4.85s at 40MHz). This time includes the conversion itself, the sample time and the time required to transfer the digital value to the result register. 20.4 AC characteristics 20.4.1 Test waveforms Figure 75. Input / output waveforms 9 9'' 9'' 7H VW3RLQWV 9'' 9'' 9 $&LQSXWVGXULQJWHVWLQJDUHGULYHQDW9IRUDORJLFDQG9IRUDORJLF 7LPLQJPHDVXUHPHQWVDUHPDGHDW9 ,+PLQIRUDORJLFDQG9,/PD[IRUDORJLF ("1($'5 Figure 76. Float waveforms 92+ 92+9 9/RDG 9 7LPLQJ 5HIHUHQFH 3RLQWV 9/RDG 9/RDG9 92/9 92/ )RUWLPLQJSXUSRVHVDSRUWSLQLVQRORQJHUIORDWLQJZKHQ9 /2$'FKDQJHVRIP9 ,WEHJLQVWRIORDWZKHQDP9FKDQJHIURPWKHORDGHG92+92/OHYHORFFXUV ,2+,2/ P$ ("1($'5 20.4.2 Definition of internal timing The internal operation of the ST10F280 is controlled by the internal CPU clock fCPU. Both edges of the CPU clock can trigger internal (for example pipeline) or external (for example bus cycles) operations. The specification of the external timing (AC Characteristics) therefore depends on the time between two consecutive edges of the CPU clock, called "TCL". The CPU clock signal can be generated by different mechanisms. The duration of TCL and its variation (and also the derived external timing) depends on the mechanism used to generate fCPU. This influence must be regarded when calculating the timings for the ST10F280. The example for PLL operation shown in Figure 73 refers to a PLL factor of 4. 210/239 Doc ID 8673 Rev. 3 ST10F280 Electrical characteristics The mechanism used to generate the CPU clock is selected during reset by the logic levels on pins P0.15-13 (P0H.7-5). Figure 77. Generation mechanisms for the CPU clock 3KDVHORFNHGORRSRSHUDWLRQ I;7$/ I&38 7&/ 7&/ 'LUHFW&ORFN'ULYH I;7$/ I&38 7&/ 7&/ 3UHVFDOHU2SHUDWLRQ I;7$/ I&38 7&/ 7&/ ("1($'5 20.4.3 Clock generation modes The Table 45 associates the combinations of these three bit with the respective clock generation mode. Table 45. CPU frequency generation P0H.7 P0H.6 P0H.5 CPU frequency fCPU = fXTAL x F External clock input range(1) 1 1 1 fXTAL x 4 2.5 to 10MHz 1 1 0 fXTAL x 3 3.33 to 13.33MHz 1 0 1 fXTAL x 2 5 to 20MHz 1 0 0 fXTAL x 5 2 to 8MHz 0 1 1 fXTAL x 1 1 to 40MHz 0 1 0 fXTAL x 10 1 to 4MHz 0 0 1 fXTAL x 0.5 2 to 80MHz 0 0 0 fXTAL x 2.5 4 to 16MHz Notes Default configuration Direct drive(2)(3) CPU clock via prescaler(4) 1. The external clock input range refers to a CPU clock range of 1...40MHz. 2. The maximum depends on the duty cycle of the external clock signal. 3. The PLL free-running frequency is from 2 to 10MHz. Doc ID 8673 Rev. 3 211/239 Electrical characteristics ST10F280 4. The maximum input frequency is 25MHz when using an external crystal with the internal oscillator; providing that internal serial resistance of the crystal is less than 40. However, higher frequencies can be applied with an external clock source on pin XTAL1, but in this case, the input clock signal must reach the defined levels VIL and VIH2.. 20.4.4 Prescaler operation When pins P0.15-13 (P0H.7-5) equal '001' during reset, the CPU clock is derived from the internal oscillator (input clock signal) by a 2:1 prescaler. The frequency of fCPU is half the frequency of fXTAL and the high and low time of fCPU (i.e. the duration of an individual TCL) is defined by the period of the input clock fXTAL. The timings listed in the AC Characteristics that refer to TCL therefore can be calculated using the period of fXTAL for any TCL. Note that if the bit OWDDIS in SYSCON register is cleared, the PLL runs on its free-running frequency and delivers the clock signal for the Oscillator Watchdog. If bit OWDDIS is set, then the PLL is switched off. 20.4.5 Direct drive When pins P0.15-13 (P0H.7-5) equal '011' during reset the on-chip phase locked loop is disabled and the CPU clock is directly driven from the internal oscillator with the input clock signal. The frequency of fCPU directly follows the frequency of fXTAL so the high and low time of fCPU (i.e. the duration of an individual TCL) is defined by the duty cycle of the input clock fXTAL. Therefor, the timings given in this chapter refer to the minimum TCL. This minimum value can be calculated by the following formula: TCL min = 1f XT ALl xl DCmin DC = duty cycle For two consecutive TCLs, the deviation caused by the duty cycle of fXTAL is compensated, so the duration of 2 TCL is always 1/fXTAL. The minimum value TCLmin has to be used only once for timings that require an odd number of TCLs (1,3,...). Timings that require an even number of TCLs (2,4,...) may use the formula: 2TCL = 1 f XTAL Note: 212/239 The address float timings in Multiplexed bus mode (t11 and t45) use the maximum duration of TCL (TCLmax = 1/fXTAL x DCmax) instead of TCLmin. If the bit OWDDIS in SYSCON register is cleared, the PLL runs on its free-running frequency and delivers the clock signal for the Oscillator Watchdog. If bit OWDDIS is set, then the PLL is switched off. Doc ID 8673 Rev. 3 ST10F280 20.4.6 Electrical characteristics Oscillator Watchdog (OWD) An on-chip watchdog oscillator is implemented in the ST10F280. This feature is used for safety operation with external crystal oscillator (using direct drive mode with or without prescaler). This watchdog oscillator operates as following: The reset default configuration enables the watchdog oscillator. It can be disabled by setting the OWDDIS (bit 4) of SYSCON register. When the OWD is enabled, the PLL runs at its free-running frequency, and it increments the watchdog counter. The PLL free-running frequency is from 2 to 10MHz. On each transition of external clock, the watchdog counter is cleared. If an external clock failure occurs, then the watchdog counter overflows (after 16 PLL clock cycles). The CPU clock signal will be switched to the PLL free-running clock signal, and the oscillator watchdog Interrupt Request (XP3INT) is flagged. The CPU clock will not switch back to the external clock even if a valid external clock exits on XTAL1 pin. Only a hardware reset can switch the CPU clock source back to direct clock input. When the OWD is disabled, the CPU clock is always external oscillator clock and the PLL is switched off to decrease consumption supply current. 20.4.7 Phase locked loop For all other combinations of pins P0.15-13 (P0H.7-5) during reset the on-chip phase locked loop is enabled and it provides the CPU clock (see Table 45). The PLL multiplies the input frequency by the factor F which is selected via the combination of pins P0.15-13 (fCPU = fXTAL x F). With every F'th transition of fXTAL the PLL circuit synchronizes the CPU clock to the input clock. This synchronization is done smoothly, so the CPU clock frequency does not change abruptly. Due to this adaptation to the input clock the frequency of fCPU is constantly adjusted so it is locked to fXTAL. The slight variation causes a jitter of fCPU which also effects the duration of individual TCLs. The timings listed in the AC Characteristics that refer to TCLs therefore must be calculated using the minimum TCL that is possible under the respective circumstances. The real minimum value for TCL depends on the jitter of the PLL. The PLL tunes fCPU to keep it locked on fXTAL. The relative deviation of TCL is the maximum when it is referred to one TCL period. It decreases according to the formula and to the Figure 74 given below. For N periods of TCL the minimum value is computed using the corresponding deviation DN: TCL MIN = TCL NOM D N x 1 - ------------- 100 D = ( 4 - N 15 ) [ % ] N where N = number of consecutive TCL periods and 1 N 40. So for a period of 3 TCL periods (N = 3): D3 = 4 - 3/15 = 3.8% 3 TCLmin = 3 TCLNOM x (1 - 3.8/100) = 3 TCLNOM x 0.962 3 TCLmin = (36.075ns at fCPU = 40MHz) Doc ID 8673 Rev. 3 213/239 Electrical characteristics ST10F280 This is especially important for bus cycles using wait states and e.g. for the operation of timers, serial interfaces, etc. For all slower operations and longer periods (e.g. pulse train generation or measurement, lower Baud rates, etc.) the deviation caused by the PLL jitter is negligible. Figure 78. Approximated maximum PLL Jitter 0D[MLWWHU>@ 7KLVDSSUR[LPDWHGIRUPXODLVYDOLGIRU d1dDQG0+]dI&38 d0+] 1 ("1($'5 20.4.8 External clock drive XTAL1 VDD = 5 V 10%, VSS = 0 V, TA = -40C to 125 C Table 46. External clock drive XTAL1 fCPU = fXTAL x F fCPU = fXTAL Parameter fCPU = fXTAL / 2 Symbol F = 2 / 2.5 / 3 / 4 / 5 / 10 Min. Max. Min. Max. Min. Max. Unit Oscillator period tOSC SR 25 (1) - 12.5 - 40 x N 100 x N ns High time t1 SR 10 (2) - 5 (2) - 10 (2) - ns Low time t2 SR 10 (2) - 5 (2) - 10 (2) - ns 3 (2) ns 3 (2) ns Rise time Fall time t3 t4 SR SR - - 3 (2) 3 (2) - - 3 (2) 3 (2) - - 1. Theoretical minimum. The real minimum value depends on the duty cycle of the input clock signal. 25MHz is the maximum input frequency when using an external crystal oscillator. However, 40MHz can be applied with an external clock source. 2. The input clock signal must reach the defined levels VIL and VIH2 214/239 Doc ID 8673 Rev. 3 ST10F280 Electrical characteristics Figure 79. External clock drive XTAL1 W W W 9,+ 9,/ W W26& ("1($'5 20.4.9 Memory cycle variables The tables below use three variables which are derived from the BUSCONx registers and represent the special characteristics of the programmed memory cycle. The following table describes, how these variables are to be computed. Table 47. Memory cycle variables Description Values ALE Extension tA TCL x [ALECTL] Memory Cycle Time wait states tC 2 TCL x (15 - [MCTC]) Memory Tri-state Time tF 2 TCL x (1 - [MTTC]) Multiplexed bus VDD = 5 V 10%, VSS = 0 V, TA = -40C to +125C, CL = 50 pF, ALE cycle time = 6 TCL + 2 tA + tC + tF (75 ns at 40 MHz CPU clock without wait states). Table 48. Symbol Multiplexed bus characteristics Max. CPU Clock = 40MHz Parameter t5 CC ALE high time t6 CC Address setup to ALE (1) Variable CPU Clock 1/2 TCL = 1 to 40MHz Unit 20.4.10 Symbol Min. Max. Min. Max. 4 + tA - TCL - 8.5 + tA - ns 2 + tA - TCL - 10.5 + tA - ns 4 + tA - TCL - 8.5 + tA - ns t7 CC Address hold after ALE t8 CC ALE falling edge to RD, WR (with R/W-delay) 4 + tA - TCL - 8.5 + tA - ns t9 CC ALE falling edge to RD, WR (no R/W-delay) -8.5 + tA - -8.5 + tA - ns t10 CC Address float after RD, WR (with R/W-delay) (1) - 6 - 6 ns t11 CC Address float after RD, WR (no R/W-delay)(1) - 18.5 - TCL + 6 ns t12 CC RD, WR low time (with R/Wdelay) 15.5 + tC - 2 TCL -9.5 + tC - ns Doc ID 8673 Rev. 3 215/239 Electrical characteristics Symbol Multiplexed bus characteristics (continued) Max. CPU Clock = 40MHz Parameter Min. Max. Min. Max. 28 + tC - 3 TCL -9.5 + tC - t13 CC RD, WR low time (no R/Wdelay) t14 SR RD to valid data in (with R/W-delay) - 6 + tC - 2 TCL - 19 + tC ns t15 SR RD to valid data in (no R/Wdelay) - 18.5 + tC - 3 TCL - 19 + tC ns - 18.5 + tA + tC - 3 TCL - 19 + tA + tC ns t16 SR ALE low to valid data in ns t17 SR Address/Unlatched CS to valid data in - 22 + 2tA + tC - 4 TCL - 28 + 2tA + tC ns t18 SR Data hold after RD rising edge 0 - 0 - ns - 16.5 + tF - 2 TCL - 8.5 + tF ns 10 + tC - 2 TCL -15 + tC - ns 4 + tF - 2 TCL - 8.5 + tF - ns t19 SR Data float after RD (1) t22 CC Data valid to WR t23 CC Data hold after WR 216/239 Variable CPU Clock 1/2 TCL = 1 to 40MHz Unit Table 48. ST10F280 t25 CC ALE rising edge after RD, WR 15 + tF - 2 TCL -10 + tF - ns t27 CC Address/Unlatched CS hold after RD, WR 10 + tF - 2 TCL -15 + tF - ns t38 CC ALE falling edge to Latched CS -4 - tA 10 - tA -4 - tA 10 - tA ns t39 SR Latched CS low to Valid Data In - 18.5 + tC + 2tA - 3 TCL - 19 + tC + 2tA ns t40 CC Latched CS hold after RD, WR 27 + tF - 3 TCL - 10.5 + tF - ns t42 CC ALE fall. edge to RdCS, WrCS (with R/W delay) 7 + tA - TCL - 5.5+ tA - ns t43 CC ALE fall. edge to RdCS, WrCS (no R/W delay) -5.5 + tA - -5.5 + tA - ns t44 CC Address float after RdCS, WrCS (with R/W delay)(1) - 0 - 0 ns t45 CC Address float after RdCS, WrCS (no R/W delay)(1) - 12.5 - TCL ns t46 SR RdCS to Valid Data In (with R/W delay) - 4 + tC - 2 TCL - 21 + tC ns t47 SR RdCS to Valid Data In (no R/W delay) - 16.5 + tC - 3 TCL - 21 + tC ns t48 CC RdCS, WrCS Low Time (with R/W delay) 15.5 + tC - 2 TCL - 9.5 + tC Doc ID 8673 Rev. 3 - ns ST10F280 Electrical characteristics Symbol t49 CC Multiplexed bus characteristics (continued) Max. CPU Clock = 40MHz Parameter RdCS, WrCS Low Time (no R/W delay) t50 CC Data valid to WrCS t51 SR Data hold after RdCS t52 SR Data float after RdCS t54 CC Address hold after RdCS, WrCS t56 CC Data hold after WrCS (1) Variable CPU Clock 1/2 TCL = 1 to 40MHz Unit Table 48. Min. Max. Min. Max. 28 + tC - 3 TCL - 9.5 + tC - ns 10 + tC - 2 TCL - 15+ tC - ns 0 - 0 - ns - 16.5 + tF - 2 TCL - 8.5+tF ns 6 + tF - 2 TCL - 19 + tF - ns 6 + tF - 2 TCL - 19 + tF - ns 1. Partially tested, guaranteed by design characterization. Doc ID 8673 Rev. 3 217/239 Electrical characteristics ST10F280 Figure 80. External memory cycle: multiplexed bus, with / without read / write delay, normal ALE CLKOUT t5 t25 t16 ALE t6 t38 t17 t40 t27 t39 CSx t6 t27 t17 A23-A16 (A15-A8) BHE Address t16 Read Cycle Address/Data Bus (P0) t6m t7 t18 Data In Address t10 t8 Address t19 t14 RD t13 t9 t11 t15 Write Cycle Address/Data Bus (P0) t12 t23 Data Out Address t8 WR WRL WRH t22 t9 t12 t13 GAPGCFT00934 218/239 Doc ID 8673 Rev. 3 ST10F280 Electrical characteristics Figure 81. External memory cycle: multiplexed bus, with / without read / write delay, extended ALE CLKOUT t16 t5 t25 ALE t6 t38 t40 t17 t39 t27 CSx t6 t17 A23-A16 (A15-A8) BHE Address t27 Read Cycle Address/Data Bus (P0) t6 t7 Data In Address t8 t9 t18 t10 t19 t11 t14 RD t15 t12 t13 Write Cycle Address/Data Bus (P0) Address Data Out t23 t8 t9 t10 t11 WR WRL WRH t13 t22 t12 GAPGCFT00935 Doc ID 8673 Rev. 3 219/239 Electrical characteristics ST10F280 Figure 82. External memory cycle: multiplexed bus, with / without read / write delay, normal ALE, read / write chip select CLKOUT t5 t25 t16 ALE t6 t27 t17 A23-A16 (A15-A8) BHE Address t16 Read Cycle Address/Data Bus (P0) t6 t7 t51 Address Address Data In t44 t42 t52 t46 RdCSx t49 t43 t45 t47 Write Cycle Address/Data Bus (P0) t48 t56 Address Data Out t42 WrCSx t50 t43 t48 t49 GAPGCFT00936 220/239 Doc ID 8673 Rev. 3 ST10F280 Electrical characteristics Figure 83. External memory cycle: multiplexed bus, with / without read / write delay, extended ALE, read / write chip select CLKOUT t16 t5 t25 ALE t6 t17 A23-A16 (A15-A8) BHE Address t54 Read Cycle Address/Data Bus (P0) t6 t7 Data In Address t42 t43 t18 t44 t19 t45 t46 RdCSx t48 t47 t49 Write Cycle Address/Data Bus (P0) Address Data Out t42 t43 t56 t44 t45 t50 WrCSx t48 t49 GAPGCFT00937 Doc ID 8673 Rev. 3 221/239 Electrical characteristics 20.4.11 ST10F280 Demultiplexed bus VDD = 5 V 10%, VSS = 0 V, TA = -40C to 125C, CL = 50 pF, ALE cycle time = 4 TCL + 2tA + tC + tF (50 ns at 40 MHz CPU clock without wait states). Symbol Demultiplexed bus characteristics Maximum CPU Clock = 40MHz Parameter Min. Max. Min. Max. t5 CC ALE high time 4 + tA - TCL - 8.5 + tA - ns t6 CC Address setup to ALE 2 + tA - TCL - 10.5 + tA - ns 16.5 + 2tA - 2 TCL - 8.5 + 2tA - ns 4 + 2tA - TCL - 8.5 + 2tA - ns 15.5 + tC - 2 TCL - 9.5 + tC - ns 28 + tC - 3 TCL - 9.5 + tC - ns Address/Unlatched CS t80 CC setup to RD, WR (with R/W-delay) Address/Unlatched CS t81 CC setup to RD, WR (no R/Wdelay) t12 CC RD, WR low time (with R/W-delay) t13 CC RD, WR low time (no R/Wdelay) t14 SR RD to valid data in (with R/W-delay) - 6 + tC - 2 TCL - 19 + tC ns t15 SR RD to valid data in (no R/W-delay) - 18.5 + tC - 3 TCL - 19 + tC ns - 18.5 + tA + tC - 3 TCL - 19 + tA + tC ns t16 SR ALE low to valid data in t17 SR Address/Unlatched CS to valid data in - 22 + 2tA + tC - 4 TCL - 28 + 2tA + tC ns t18 SR Data hold after RD rising edge 0 - 0 - ns t20 SR Data float after RD rising edge (with R/W-delay) (1)(2) - 16.5 + tF - 2 TCL - 8.5 + tF + 2tA 1 ns t21 SR Data float after RD rising edge (no R/W-delay) (1)(2) - 4 + tF - TCL - 8.5 + tF + 2tA 1 ns 10 + tC - 2 TCL - 15 + tC - ns 4 + tF - TCL - 8.5 + tF - ns t22 CC Data valid to WR t24 CC Data hold after WR 222/239 Variable CPU Clock 1/2 TCL = 1 to 40MHz Unit Table 49. t26 CC ALE rising edge after RD, WR -10 + tF - -10 + tF - ns t28 CC Address/Unlatched CS hold after RD, WR (3) 0 (no tF) -5 + tF (tF > 0) - 0 (no tF) -5 + tF (tF > 0) - ns t28h CC Address/Unlatched CS hold after WRH -5 + tF - -5 + tF - ns Doc ID 8673 Rev. 3 ST10F280 Electrical characteristics Symbol Demultiplexed bus characteristics (continued) Maximum CPU Clock = 40MHz Parameter Variable CPU Clock 1/2 TCL = 1 to 40MHz Unit Table 49. Min. Max. Min. Max. -4 - tA 6 - tA -4 - tA 6 - tA ns - 18.5 + tC + 2tA - 3 TCL - 19 + tC + 2tA ns 2 + tF - TCL - 10.5 + tF - ns t38 CC ALE falling edge to Latched CS t39 SR Latched CS low to Valid Data In t41 CC Latched CS hold after RD, WR t82 CC Address setup to RdCS, WrCS (with R/W-delay) 14.5 + 2tA - 2 TCL - 10.5 + 2tA - ns t83 CC Address setup to RdCS, WrCS (no R/W-delay) 2 + 2tA - TCL - 10.5 + 2tA - ns t46 SR RdCS to Valid Data In (with R/W-delay) - 4 + tC - 2 TCL - 21 + tC ns t47 SR RdCS to Valid Data In (no R/W-delay) - 16.5 + tC - 3 TCL - 21 + tC ns t48 CC RdCS, WrCS Low Time (with R/W-delay) 15.5 + tC - 2 TCL - 9.5 + tC - ns t49 CC RdCS, WrCS Low Time (no R/W-delay) 28 + tC - 3 TCL - 9.5 + tC - ns 10 + tC - 2 TCL - 15 + tC - ns t51 SR Data hold after RdCS 0 - 0 - ns t53 SR Data float after RdCS (with R/W-delay) (2) - 16.5 + tF - 2 TCL - 8.5 + tF ns t68 SR Data float after RdCS (no R/W-delay) (2) - 4 + tF - TCL - 8.5 + tF ns t55 CC Address hold after RdCS, WrCS -8.5 + tF - -8.5 + tF - ns 2 + tF - TCL - 10.5 + tF - ns t50 CC Data valid to WrCS t57 CC Data hold after WrCS 1. R/W-delay and tA refer to the next following bus cycle. 2. Partially tested, guaranteed by design characterization. 3. Read data are latched with the same clock edge that triggers the address change and the rising RD edge. Therefore address changes before the end of RD have no impact on read cycles. Doc ID 8673 Rev. 3 223/239 Electrical characteristics ST10F280 Figure 84. External memory cycle: demultiplexed bus, with / without read / write delay, normal ALE CLKOUT t5 t26 t16 ALE t6 t38 t41 t17 t41u 1) t39 CSx t6 t28 (or t28h) t17 A23-A16 A15-A0 (P1) BHE Address t18 Read Cycle Data Bus (P0) (D15-D8) D7-D0 Data In t80 t81 t20 t14 t21 t15 RD t12 t13 Write Cycle Data Bus (P0) (D15-D8) D7-D0 Data Out t80 t22 t81 WR WRL WRH t24 t12 t13 GAPGCFT00938 1. Un-latched CSx = t41u = t41 TCL =10.5 + tF. 224/239 Doc ID 8673 Rev. 3 ST10F280 Electrical characteristics Figure 85. External memory cycle: demultiplexed bus, with / without read / write delay, extended ALE CLKOUT t5 t26 t16 ALE t6 t38 t41 t17 t28 t39 CSx t6 t28 t17 A23-A16 A15-A0 (P1) BHE Address t18 Read Cycle Data Bus (P0) (D15-D8) D7-D0 Data In t20 t14 t80 t15 t81 t21 RD t12 t13 Write Cycle Data Bus (P0) (D15-D8) D7-D0 Data Out t80 t81 t22 WR WRL WRH t24 t12 t13 GAPGCFT00939 Doc ID 8673 Rev. 3 225/239 Electrical characteristics ST10F280 Figure 86. External memory cycle: demultiplexed bus, with / without read / write delay, normal ALE, read / write chip select CLKOUT t5 t26 t16 ALE t6 A23-A16 A15-A0 (P1) BHE t17 t55 Address t51 Read Cycle Data Bus (P0) (D15-D8) D7-D0 Data In t82 t83 t53 t46 t68 t47 RdCSx t48 t49 Write Cycle Data Bus (P0) (D15-D8) D7-D0 Data Out t82 t50 t83 t57 WrCSx t48 t49 GAPGCFT00940 226/239 Doc ID 8673 Rev. 3 ST10F280 Electrical characteristics Figure 87. External memory cycle: demultiplexed bus, no read / write delay, extended ALE, read /write chip select CLKOUT t5 t26 t16 ALE t6 t55 t17 A23-A16 A15-A0 (P1) BHE Address t51 Read Cycle Data Bus (P0) (D15-D8) D7-D0 Data In t53 t46 t82 t47 t83 t68 RdCSx t48 t49 Write Cycle Data Bus (P0) (D15-D8) D7-D0 Data Out t82 t83 t50 t57 WrCSx t48 t49 GAPGCFT00941 CLKOUT and READY VDD = 5 V 10%, VSS = 0 V, TA = -40C to 125C, CL = 50 pF Table 50. Symbol CLKOUT and READY characteristics Parameter Maximum CPU Clock = 40MHz Variable CPU Clock 1/2 TCL = 1 to 40MHz Min. Max. Min. Max. Unit 20.4.12 t29 CC CLKOUT cycle time 25 25 2 TCL 2TCL ns t30 CC CLKOUT high time 4 - TCL - 8.5 - ns t31 CC CLKOUT low time 3 - TCL - 9.5 - ns t32 CC CLKOUT rise time - 4 - 4 ns t33 CC CLKOUT fall time - 4 - 4 ns Doc ID 8673 Rev. 3 227/239 Electrical characteristics Symbol CLKOUT and READY characteristics (continued) Maximum CPU Clock = 40MHz Parameter Variable CPU Clock 1/2 TCL = 1 to 40MHz Min. Max. Min. Max. t34 CC CLKOUT rising edge to ALE falling edge -2 + tA 8 + tA -2 + tA 8 + tA ns t35 SR Synchronous READY setup time to CLKOUT 12.5 - 12.5 - ns t36 SR Synchronous READY hold time after CLKOUT 2 - 2 - ns t37 SR Asynchronous READY low time 35 - 2 TCL + 10 - ns t58 SR Asynchronous READY setup time (1) 12.5 - 12.5 - ns t59 SR Asynchronous READY hold time (1) 2 - 2 - ns t60 Asynchronous READY hold time after RD, WR SR high (Demultiplexed Bus)(2) 0 0 + 2tA + tC + tF (2) 0 TCL - 12.5 + 2tA + tC + tF ns (2) 1. These timings are given for test purposes only, in order to assure recognition at a specific clock edge. 2. Demultiplexed bus is the worst case. For multiplexed bus 2 TCL are to be added to the maximum values. This adds even more time for deactivating READY. The 2tA and tC refer to the next following bus cycle, tF refers to the current bus cycle. 228/239 Unit Table 50. ST10F280 Doc ID 8673 Rev. 3 ST10F280 Electrical characteristics Figure 88. CLKOUT and READY READY wait state Running cycle 1) CLKOUT t32 MUX / Tri-state 6) t33 t30 t29 t31 t34 ALE 7) RD, WR 2) t35 Synchronous READY Asynchronous READY t36 t35 3) 3) t58 t59 t36 t58 t59 t60 4) 3) 3) t37 6) 5) GAPGCFT00942 1. Cycle as programmed, including MCTC wait states (Example shows 0 MCTC WS). 2. The leading edge of the respective command depends on R/W-delay. 3. READY sampled HIGH at this sampling point generates a READY controlled wait state, READY sampled LOW at this sampling point terminates the currently running bus cycle. 4. READY may be deactivated in response to the trailing (rising) edge of the corresponding command (RD or WR). 5. If the Asynchronous READY signal does not fulfill the indicated setup and hold times with respect to CLKOUT (e.g. because CLKOUT is not enabled), it must fulfill t37 in order to be safely synchronized. This is guaranteed, if READY is removed in response to the command (see Note 4)). 6. Multiplexed bus modes have a MUX wait state added after a bus cycle, and an additional MTTC wait state may be inserted here. For a multiplexed bus with MTTC wait state this delay is 2 CLKOUT cycles, for a demultiplexed bus without MTTC wait state this delay is zero. 7. The next external bus cycle may start here. External bus arbitration VDD = 5 V 10%, VSS = 0 V, TA = -40C to 125C, CL = 50 pF Table 51. Symbol External bus arbitration Maximum CPU Clock = 40MHz Parameter Variable CPU Clock 1/2 TCL = 1 to 40MHz Min. Max. Min. Max. Unit 20.4.13 t61 SR HOLD input setup time to CLKOUT 15 - 15 - ns t62 CC CLKOUT to HLDA high or BREQ low delay - 12.5 - 12.5 ns t63 CC CLKOUT to HLDA low or BREQ high delay - 12.5 - 12.5 ns Doc ID 8673 Rev. 3 229/239 Electrical characteristics External bus arbitration (continued) Symbol Maximum CPU Clock = 40MHz Parameter t64 CC CSx release t65 CC CSx drive (1) t66 CC Other signals release t67 CC Other signals drive (1) Variable CPU Clock 1/2 TCL = 1 to 40MHz Min. Max. Min. Max. - 15 - 15 ns -4 15 -4 15 ns - 15 - 15 ns -4 15 -4 15 ns 1. Partially tested, guaranteed by design characterization Figure 89. External bus arbitration, releasing the bus CLKOUT t61 HOLD t63 HLDA 1) t62 BREQ 2) t64 3) CSx (P6.x) 1) t66 Others GAPGCFT00943 1. The ST10F280 will complete the currently running bus cycle before granting bus access. 2. This is the first possibility for BREQ to become active. 3. The CS outputs will be resistive high (pull-up) after t64. 230/239 Unit Table 51. ST10F280 Doc ID 8673 Rev. 3 ST10F280 Electrical characteristics Figure 90. External bus arbitration, (regaining the bus) 2) CLKOUT t61 HOLD t62 HLDA t62 t62 BREQ t63 1) t65 CSx (On P6.x) t67 Other Signals GAPGCFT00944 1. 1. This is the last chance for BREQ to trigger the indicated regain-sequence. Even if BREQ is activated earlier, the regain-sequence is initiated by HOLD going high. Please note that HOLD may also be deactivated without the ST10F280 requesting the bus 2. The next ST10F280 driven bus cycle may start here. High-speed synchronous serial interface (SSC) timing Master mode VCC = 5 V 10%, VSS = 0 V, CPU clock = 40 MHz, TA = -40C to 125C, CL = 50 pF Table 52. Symbol SSC master timing Maximum Baud rate = 10M Baud (<SSCBR> = 0001h) Parameter Variable Baud rate (<SSCBR>=0001hFFFFh) Min. Max. Min. Max. Unit 20.4.14 t300 CC SSC clock cycle time 100 100 8 TCL 262144 TCL ns t301 CC SSC clock high time 40 - t300/2 - 10 - ns t302 CC SSC clock low time 40 - t300/2 - 10 - ns t303 CC SSC clock rise time - 10 - 10 ns t304 CC SSC clock fall time - 10 - 10 ns t305 CC Write data valid after shift edge - 15 - 15 ns t306 CC Write data hold after shift edge(1) -2 - -2 - ns Doc ID 8673 Rev. 3 231/239 Electrical characteristics SSC master timing (continued) Symbol Maximum Baud rate = 10M Baud (<SSCBR> = 0001h) Parameter Variable Baud rate (<SSCBR>=0001hFFFFh) Unit Table 52. ST10F280 Min. Max. Min. Max. 37.5 - 2 TCL + 12.5 - ns t307p Read data setup time before latch edge, phase SR error detection on (SSCPEN = 1) t308p Read data hold time after SR latch edge, phase error detection on (SSCPEN = 1) 50 - 4 TCL - ns t307 Read data setup time before latch edge, phase SR error detection off (SSCPEN = 0) 25 - 2 TCL - ns t308 Read data hold time after SR latch edge, phase error detection off (SSCPEN = 0) 0 - 0 - ns 1. Timing guaranteed by design. The formula for SSC Clock Cycle time is: t300 = 4 TCL * (<SSCBR> + 1) Where <SSCBR> represents the content of the SSC Baud rate register, taken as unsigned 16-bit integer. Figure 91. SSC master timing t300 1) t301 t302 2) SCLK t304 t305 t305 MTSR 1st Out Bit t303 t306 2nd Out Bit 1st.In Bit Last Out Bit t307 t308 t307 t308 MRST t305 2nd.In Bit Last.In Bit GAPGCFT00946 1. The phase and polarity of shift and latch edge of SCLK is programmable. This figure uses the leading clock edge as shift edge (drawn in bold), with latch on trailing edge (SSCPH = 0b), Idle clock line is low, leading clock edge is low-to-high transition (SSCPO = 0b). 2. The bit timing is repeated for all bits to be transmitted or received. 232/239 Doc ID 8673 Rev. 3 ST10F280 Electrical characteristics Slave mode VCC = 5 V 10%, VSS = 0 V, CPU clock = 40 MHz, TA = -40C to 125C, CL = 50 pF Symbol SSC slave timing Parameter Maximum Baud rate=10MBd (<SSCBR> = 0001h) Variable Baud rate (<SSCBR>=0001hFFFFh) Min. Max. Min. Max. Unit Table 53. t310 SR SSC clock cycle time 100 100 8 TCL 262144 TCL ns t311 SR SSC clock high time 40 - t310/2 - 10 - ns t312 SR SSC clock low time 40 - t310/2 - 10 - ns t313 SR SSC clock rise time - 10 - 10 ns t314 SR SSC clock fall time - 10 - 10 ns t315 CC Write data valid after shift edge - 39 - 2 TCL + 14 ns t316 CC Write data hold after shift edge 0 - 0 - ns t317p Read data setup time before SR latch edge, phase error detection on (SSCPEN = 1) 62 - 4 TCL + 12 - ns t318p(1) Read data hold time after SR latch edge, phase error detection on (SSCPEN = 1) 87 - 6 TCL + 12 - ns t317 Read data setup time before SR latch edge, phase error detection off (SSCPEN = 0) 6 - 6 - ns t318 Read data hold time after SR latch edge, phase error detection off (SSCPEN = 0) 31 - 2 TCL + 6 - ns 1. Timing guaranteed by design. The formula for SSC Clock Cycle time is: t310 = 4 TCL * (<SSCBR> + 1) Where <SSCBR> represents the content of the SSC Baud rate register, taken as unsigned 16-bit integer. Doc ID 8673 Rev. 3 233/239 Electrical characteristics ST10F280 Figure 92. SSC slave timing t310 1) t311 t312 2) SCLK t314 t315 MRST t313 t315 1st Out Bit t316 2nd Out Bit t317 t318 MTSR 1st.In Bit t315 Last Out Bit t317 t318 2nd.In Bit Last.In Bit GAPGCFT00947 1. The phase and polarity of shift and latch edge of SCLK is programmable. This figure uses the leading clock edge as shift edge (drawn in bold), with latch on trailing edge (SSCPH = 0b), Idle clock line is low, leading clock edge is low-to-high transition (SSCPO = 0b). 2. The bit timing is repeated for all bits to be transmitted or received. 234/239 Doc ID 8673 Rev. 3 ST10F280 Package information 21 Package information 21.1 ECOPACK(R) In order to meet environmental requirements, ST offers these devices in different grades of ECOPACK(R) packages, depending on their level of environmental compliance. ECOPACK(R) specifications, grade definitions and product status are available at: www.st.com. ECOPACK(R) is an ST trademark. PBGA 208 (23 x 23 x 1.96 mm) mechanical data Figure 93. Package outline PBGA 208 (23 x 23 x 1.96 mm) 000 C 21.2 SEATING PLANE C A2 A3 A1 A D D1 e f f U T R P N M L K E1 E J H G F E D C B A e 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 A1 BALL PAD CORNER 2 b (208 + 25 BALLS) 1. PBGA stands for Plastic Ball Grid Array. 2. The terminal A1 corner must be identified on the top surface of the package by using a corner chamfer, ink or metallized markings, identation or other feature of package body or integral heastslug. A distinguishing feature is allowable on the bottom of the package to identify the terminal A1 corner. Exact shape and size of this feature is optional. Doc ID 8673 Rev. 3 235/239 Package information Table 54. ST10F280 PBGA 208 (23 x 23 x 1.96 mm) mechanical data Millimeters Inches (approx) Dimensions Min. A A1 Max. Min. 1.960 0.500 0.600 Typ. Max. 0.077 0.700 0.019 0.024 A2 1.360 0.054 A3 0.560 0.022 0.028 b 0.600 0.760 0.900 0.024 0.030 0.035 D 22.900 23.000 23.100 0.902 0.906 0.909 D1 E 20.320 22.900 23.000 0.800 23.100 0.902 0.906 E1 20.320 0.800 e 1.270 0.50 f aaa 236/239 Typ. 1.240 1.340 1.440 0.150 Doc ID 8673 Rev. 3 0.049 0.053 0.909 0.057 0.006 ST10F280 22 Ordering information Ordering information Table 55. Device summary Order codes Package ST10F280 Packing Temperature range Tray PBGA 208 (23 x 23 x 1.96 mm) ST10F280-Q3TR -40C to +125C Tape and reel Doc ID 8673 Rev. 3 237/239 Revision history 23 ST10F280 Revision history Table 56. 238/239 Document revision history Date Revision Changes 13-Mar-2003 1 Initial release. 29-May-2008 2 Changed document template. 20-Aug-2012 3 Changed document template. Updated Table 55: Device summary Doc ID 8673 Rev. 3 ST10F280 Please Read Carefully: Information in this document is provided solely in connection with ST products. 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