MC33411A/B
900 MHz ANALOG
CORDLESS PHONE
BASEBAND
WITH COMPANDER
FTA SUFFIX
PLASTIC PACKAGE
CASE 932
(LQFP–48)
Device Operating
Temperature Package
ORDERING INFORMATION
MC33411AFTA TA = –20 to 70°C LQFP–48
SEMICONDUCTOR
TECHNICAL DATA
Order this document by MC33411A/D
MC33411BFTA
1
MOTOROLA RF/IF DEVICE DATA
Advance Information
900 MHz Analog Cordless
Phone Baseband with
Compander
The MC33411 900 MHz Analog Cordless Phone Baseband system is
designed to fit the requirements of a 900 MHz analog cordless telephone
system. Included are three PLLs (Phase–Locked Loops). Two are intended
for use with external VCOs and 64/65 or 128/129 dual modulus prescalers,
and can control the transmit and receive (LO1) frequencies for 900 MHz
communication. The third PLL is configured as the 2nd local oscillator (LO2),
and is functional to 80 MHz. Also included are muting, audio gain adjust
(internal and external), low battery/carrier detect, and a wide range for the
PLL reference frequency. The power supply range is 2.7 to 5.5 V . ”A” version
devices have programmable MCU clock out and reference oscillator disable
functions, whereas these functions are always enabled for ”B” version
devices.
•Complete Expander/Compressor for Superior Noise Rejection
•Two PLLs and a LO Suitable for a 900 MHz System
•Minimal External Components
•Transmit Path Includes Adjustable Gain Amplifier , Filters, Mute,
Compressor with Bypass and Limiter
•Receive Path Contains Data Slicer, Adjustable Gain Amplifier, Sidetone
Attenuator, Filters, Expander with Bypass, Mute, Volume Control and
Power Amplifier
•Dual A/Ds are Provided to Monitor RSSI and VCC
•Independent Power Amplifier with Differential Outputs and Mute
•Selectable Frequency for Switched Capacitor Filters, PLLs and the LO
•Reference Frequency Source can be a Crystal or System Clock
•Serial µP Port to Control Gain, Mute, Frequency Selection, Phase
Detector Gain, Power Down Modes, Low Battery Detect and Others
•Power Supply Range: 2.7 to 5.5 V
•Power Down Modes for Power Conservation
Simplified Block Diagram
VCC
DS In
RSSI
Tx In
Rx Out
DS Out
Tx Out
Audio In
MCU Clock
Clock
Enable
Data
LO2 Out
Amp/Mute
Compressor
Filter Gain Adj
Filter Sidetone Attn
Mute Expander
Power Amp
Programmable
Counters
2nd
LO
PLL
#1 PLL
#2
Data
Slicer
Dual
A/D
MCU
Interface
LPF+ VCO +
Prescaler LPF
Tank
This device contains 11,108 active transistors. LPF+ VCO +
Prescaler
This document contains information on a new product. Specifications and information herein
are subject to change without notice. Motorola, Inc. 1998 Rev 1
MC33411A/B
2MOTOROLA RF/IF DEVICE DATA
Mod CtlMod Ctl
Figure 1. Test Circuit
VCC VCC
VCC
VCC
VCC VCC
VCC
Audio
VB
SCF Clk
SPI
SPI
SPI
SPI
RSSI In
Rx Audio In
DS In
Gnd Audio
LO2 Out
LO2 VCC
LO2+
LO2–
LO2 Ctl
LO2 Gnd
LO2PD
LO2 Gnd
MCO
VCC
Audio
C In
Ccap
C Out
Lim In
Tx Out
DS Out
Fref Out
Fref In
Gnd Digital
MCU Clk Out
FRx MC FRx PLL
VCC Rx PD PLL
Gnd Tx PD PLL
VCC FTx FTx MC EN CLK Data
Rx
Out E In Ecap E Out PAI Gnd PA PAO+ VCC
PA VB VAG MCIPAO–
Tx Audio
ALC
LPF
AALPF Attn
LPF
RSSI 6b A/D
Converter
VCC 6b A/D
Converter
2nd LO
VCO
14b Ctr
LO2 Phase
Detect
7b A’
Rx Phase
Detect
13b N’
Tx Phase
Detect
12b Ref Ctr
MCU
Interface
Divide
By 2 6b SCF
Clk Ctr
MCU
Clk Ctr
1 1023456789 1112
48
47
46
45
44
43
42
41
40
39
38
37
BG Vref
Rx Gain Adj
Rx Mute
Data Slicer
Inverter
36 35 34
Exp PT
Expander
33 32 31 30 29
Power
Amp Mute
Power Amp
28 27 26
Mic Amp
25
24
23
22
21
20
19
Comp PT
Compressor
Limiter
Tx Gain Adj
Tx Mute
18
17
16
15
14
13
Side Tone
Attn
7b A13b N
0.47 µ
0.47 µ
SPI
SPI
Low Max
Gain
Vol
Ctl
VCC
1.0 k
1.0 µ
100 p
5.6 p
5.62 k
0.1 µ
1.0 µ
0.001 µ
1.0 µ
1.0 µ1.0 µ1.0 µ
4.99 k
4.99 k 130
1.0 µ0.1 µ
4.7 0.1 µ
1.0 µ
47.5 k
47.5 k
1.0 µ
1.0 µ
1.0 µ
10 k
1.0 µ
0.1 µ
1.0 µ
0.001 µ0.001 µ0.01 µ
1.0 µ
0.01 µ
VCC
49.9
0.1 µ10 µ
49.9
49.9
RF In RF In
MC33411A/B
3
MOTOROLA RF/IF DEVICE DATA
MAXIMUM RATINGS
Rating Symbol Value Unit
Power Supply Voltage VCC –0.5 to 6.0 V
Junction Temperature TJ–6.5 to 150 °C
Maximum Power Dissipation PD150 mW
NOTES: 1.Meets Human Body Model (HBM) ≤2000 V and Machine Model (MM) ≤200 V.
2.ESD data available upon request.
RECOMMENDED OPERATING CONDITIONS
Characteristic Symbol Min Typ Max Unit
Supply Voltage VCC 2.7 3.6 5.5 Vdc
Operating Ambient Temperature TA–20 – 70 °C
Input Voltage Low (Data, CLK, EN) Vil – – 0.3 V
Input Voltage High (Data, CLK, EN) Vih Tx PLL
VCC – 0.3 – – V
Frequency Range (Fref in) Frange 4.0 – 18.25 MHz
Bandgap Reference Voltage VB– 1.5 – V
DC ELECTRICAL CHARACTERISTICS (VCC = 3.6 V, TA = 25°C, unless otherwise noted.)
Characteristic Symbol Min Typ Max Unit
Static Current
Active Mode (R5/8 to 0 = 0; R6/7 = 0) ACT ICC – 15 20 mA
Receive Mode (R5/8, 7, 3, 2, 0 = 0; R6/7 = 0; R5/6,5,4,1 = 1) Rx ICC – 10 13 mA
Standby Mode (R5/0 = 0; R6/7 = 0; R5/8 to 1 = 1) STD ICC – 500 1500 µA
Inactive Mode, A only (R5/8 to 0 =1; R6/7 = 1) INA ICC – 10 15 µA
Data Slicer Only DS ICC – 100 – µA
RSSI/Batt A/D Only AD ICC – 70 – µA
Tx Audio Only TxA ICC – 1.4 – mA
Rx Audio Only RxA ICC – 1.4 – mA
PA Only PA ICC – 1.0 – mA
2nd LO/Fref Only 2LO ICC – 6.0 – mA
Rx PLL/Fref Only RxPLL ICC – 1.0 – mA
Tx PLL/Fref Only TxPLL ICC – 1.0 – mA
Ref Osc Only, ”A” version only ROSC ICC – 500 – µA
Reference Voltage, Unadjusted VB1.38 1.5 1.62 V
ELECTRICAL CHARACTERISTICS (VCC = 3.6 V, VB = 1.5 V, TA = 25°C, Active Mode, Rx Gain = 01111,
Vol Adj = 0111, fin = 1.0 kHz, unless otherwise noted.)
Characteristics Input
Pin Measure
Pin Symbol Min Typ Max Unit
Rx AUDIO PATH
Absolute Gain (Vin = –20 dBV) Rx Audio In E Out G –4.0 0 4.0 dB
Gain T racking (Referenced to Eout for
Vin = –20 dBV) E In E Out GtdB
Vin = –30 dBV –21 –20 –19
Vin = –40 dBV –42 –40 –38
Total Harmonic Distortion (Vin = –20 dBV) Rx Audio In PAO– THD – 0.7 1.0 %
Maximum Input Voltage (VCC = 2.7 V) Rx Audio In – –11.5 – dBV
Maximum Output Voltage (Increase input voltage
until output voltage THD = 5%, then measure
output voltage)
E In E Out VOmax –2.0 0 – dBV
NOTES: 1.Values specified are pure numbers to the base 10.
2.T ypical performance parameters indicate the potential of the device under ideal operating conditions.
MC33411A/B
4MOTOROLA RF/IF DEVICE DATA
ELECTRICAL CHARACTERISTICS (continued) (VCC = 3.6 V, VB = 1.5 V, TA = 25°C, Active Mode, Rx Gain = 01111,
Vol Adj = 0111, fin = 1.0 kHz, unless otherwise noted.)
Characteristics UnitMaxTypMinSymbol
Measure
Pin
Input
Pin
Rx AUDIO PATH (continued)
Input Impedance Zin kΩ
RxAudio In – 600 –
E In – 7.5 –
Attack T ime Ecap = 0.5 µF, Rfilt = 40 k E In E Out ta– 3.0 – mS
Release T ime Ecap = 0.5 µF, Rfilt = 40 k E In E Out tr– 13.5 – mS
Compressor to Expander Crosstalk (Vin = –10 dBV,
VE In = AC Gnd) MCI E Out CT– –90 –60 dB
Rx Muting (Vin = –20 dBV, Rx Gain Adj = 01111) Rx Audio In E Out Me– –84 –60 dB
Rx High Frequency Corner (Vin = –20 dBV) SCF
Counter = 31dRx Audio In Rx Out Rx fch 3.6 3.8 4.0 kHz
Low Pass Filter Passband Ripple (Vin = –20 dBV) Rx Audio In Rx Out Ripple – 0.4 0.6 dB
Rx Gain Adjust Range Rx Audio In Rx Out Rx Range ––9.0 to 10 – dB
Rx Gain Adjust Steps Rx Audio In Rx Out Rx n – 20 –
Audio Path Noise, C–Message Weighting
(Vin = AC Gnd) Rx Audio In EN dBV
Rx Out – –85 –
E Out – <–95 –
PA Out – <–95 –
Volume Control Adjust Range Rx Audio In E Out VCtl
Range ––14 to 16 – dB
Volume Control Levels E In E Out Vcn – 16 –
Side Tone Attenuate Selections Rx Audio In Rx Out STAn– 4 –
Side Tone Attenuate (Referenced to E In) E Out STA dB
Selection = 00 – 0.0 –
Selection = 01 – 1.5 –
Selection = 10 – 3.0 –
Selection = 11 – 5.2 –
Side Tone Attenuate Threshold (C Out/E In) STAthr – –3.0 – dB
POWER AMP/MUTE (VCC = 3.6 V, VB = 1.5 V, TA = 25°C, Active Mode, fin = 1.0 kHz)
Output Swing, ±5.0 mA load PAI PAO+ VOmax 1.3 2.4 – Vpp
(VPAO+ @ –5.0 mA – VPAO+@ 5.0 mA)
Output Swing, ±5.0 mA load PAI PAO– VOmax 1.3 2.4 – Vpp
(VPAO– @ –5.0 mA – VPAO–@ 5.0 mA)
Output Swing, No Load PAI PAO+ VOmax – 2.7 – Vpp
Output Swing, No Load PAI PAO– VOmax – 2.7 – Vpp
Maximum Output Current PAO–,
PAO+ IOmax –±5.0 – mA
Power Amp Mute (Vin = –20 dBV, RL = 130 Ω)PAI PAO– Msp – –92 –60 dB
MIC AMP (VCC = 3.6 V, TA = 25°C, Active Mode, fin = 1.0 kHz)
Open Loop Gain MCI MCO AVOL – 100.000 – V/V
Gain Bandwidth MCI MCO GBW – 100 – kHz
Maximum Output Swing (RL = 10 kΩ) MCI MCO VOmax – 3.2 – Vpp
NOTES: 1.Values specified are pure numbers to the base 10.
2.T ypical performance parameters indicate the potential of the device under ideal operating conditions.
MC33411A/B
5
MOTOROLA RF/IF DEVICE DATA
ELECTRICAL CHARACTERISTICS (continued) (VCC = 3.6 V, VB = 1.5 V, TA = 25°C, Active Mode, Rx Gain = 01111,
Vol Adj = 0111, fin = 1.0 kHz, unless otherwise noted.)
Characteristics UnitMaxTypMinSymbol
Measure
Pin
Input
Pin
Tx AUDIO PATH (VCC = 3.6 V, Limiter , Mutes, ALC disabled, TA = 25°C, Gain = 1, Active Mode, fin = 1.0 kHz)
Absolute Gain (Vin = –10 dBV) MCI TX Out G –4.0 0 4.0 dB
Gain T racking (Referenced to Tx Out for
Vin = –10 dBV) MCI Tx Out GtdB
Vin = –30 dBV –11 –10 –9.0
Vin = –40 dBV –17 –15 –13
Total Harmonic Distortion (Vin = –10 dBV) MCI Tx Out THD – 0.5 1.2 %
Maximum Output Voltage (Increase input voltage
until output voltage THD = 5%, then measure
output voltage. Tx Gain Adj = 8.0 dB)
MCI Tx Out VOmax –8.0 –5.0 – dBV
Input Impedance C In Zin – 10 – kΩ
Attack T ime Ccap = 0.5 µF, Rfilt = 40 k C In Tx Out ta– 3.0 – mS
Release T ime Ccap = 0.5 µF, Rfilt = 40 k C In Tx Out tr– 13.5 – mS
Expander to Compressor Crosstalk (Vin = –20 dBV,
PA no load, VCin = AC Gnd) E In Tx Out CT– –60 –40 dB
Tx Muting (Vin = –10 dBV) MCI Tx Out Mc– –88 –60 dB
ALC Output Level (When Enabled) MCI Tx Out ALCout dBV
Vin = –10 dBV –15 –13 –8.0
Vin = –2.5 dBV –13 –11 –6.0
ALC Slope (When Enabled) MCI Tx Out Slope 0.1 0.25 0.4 dB/dB
Vin = –10 dBV
Vin = –2.5 dBV
ALC Input Dynamic Range C In Tx Out DR ––16 to
–2.5 – dBV
Limiter Output Level (When Enabled, Vin = –2.5
dBV) Lim In Tx Out Vlim –10 –7.0 – dBV
Tx High Frequency Corner (Vin = –10 dBV,
Unity Gain) SCF Counter = 31dLim In Tx Out Tx fch 3.45 3.65 3.85 kHz
Low Pass Filter Passband Ripple (Vin = –10 dBV) Lim In Tx Out Ripple – 0.4 1.0 dB
MCU Clock or SCF Spurs (Vin = –10 dBv, relative to
SCF or MCU Fundamental) Lim In Tx Out – – –25 – dBc
Maximum Compressor Gain (Vin = –70 dBV) MCI Tx Out AVmax dB
R6/8 = 0 – 21 –
R6/8 = 1 – 12 –
Tx Gain Adjust Range Lim In Tx Out Tx Range ––9.0 to 10 – dB
Tx Gain Adjust Steps Lim In Tx Out Tx N – 20 –
DATA AMP COMPARATOR (VCC = 3.6 V, VB = 1.5 V, TA = 25°C, Active or Receive Mode)
Hysteresis DS In DS Out Hys 20 42 60 mV
Threshold Voltage DS In DS Out VT– VCC – 0.7 – V
Input Impedance DS In Zin 200 250 280 kΩ
Output Impedance DS Out Zout – 100 – kΩ
Output High Voltage (Vin = VCC – 1.0 V, Ioh = 0 mA) DS In DS Out Voh VCC
Audio
– 0.1
VCC
Audio – V
Output Low Voltage (Vin = VCC – 0.4 V, Iol = 0 mA) DS In DS Out Vol – 0.1 0.4 V
Maximum Frequency DS In DS Out Fmax – 10 – kHz
NOTES: 1.Values specified are pure numbers to the base 10.
2.T ypical performance parameters indicate the potential of the device under ideal operating conditions.
MC33411A/B
6MOTOROLA RF/IF DEVICE DATA
ELECTRICAL CHARACTERISTICS (continued) (VCC = 3.6 V, VB = 1.5 V, TA = 25°C, Active Mode, Rx Gain = 01111,
Vol Adj = 0111, fin = 1.0 kHz, unless otherwise noted.)
Characteristics UnitMaxTypMinSymbol
Measure
Pin
Input
Pin
RSSI/LOW BATTERY A/D (VCC = 3.6 V, VB = 1.5 V, TA = 25°C, Active or Receive Mode)
RSSI Voltage Range RSSI In SPI RSSI
Range V
Minimum (R5/17–12 = 0) – 0 –
Interim (R5/17–12 = 100000) .744 – .792
Maximum (R5/17–12 = 1) – 1.6 –
Low Battery Detect Operating Range VCC Audio SPI LOWB
Range V
Minimum – 2.7 –
Interim (R5/23–18 = 101111) 2.7 – 3.1
Maximum (R5/23–18 = 1) – 3.75 –
Differential Non–linearity RSSI In/
VCC Audio SPI A/D DNL –1.0 ±0.5 1.0 LSB
Resolution RSSI In/
VCC Audio SPI Resolution – 6 – Bits
Input Current RSSI In Iin –80 20 80 nA
REFERENCE FREQUENCY (VCC = 3.6 V, VB = 1.5 V, TA = 25°C, Active Mode)
Input Current High (Vin = VCC) Fref in Iih 2.0 5.0 15 µA
Input Current Low (Vin = 0 V) Fref in Iil –15 –5.0 –2.0 µA
Minimum Input Voltage Fref In Fref in Fref out Vin 300 – – mVpp
Input Impedance Fref in Zin –2.9 pF||11.6
kΩ–
Output Impedance Fref out Zout –2.5 pF||4.5
kΩ–
MICROPROCESSOR INTERFACE (VCC = 3.6 V, VB = 1.5 V, TA = 25°C, Active or Receive Mode)
Input Low Voltage Data/EN
/CLK Vil 0 – 0.3 V
Input High Voltage Data/EN
/CLK Vih Tx PLL
VCC –
0.3
–Tx PLL
VCC V
Input Current Low (Vin = 0.3 V, Standby Mode)
Data, EN, CLK Data, EN,
CLK Iil –5.0 0.4 – µA
Input Current High (Vin = 3.3 V, Standby Mode)
Data, EN, CLK Data, EN,
CLK Iih – 1.6 5.0 µA
Hysteresis Voltage Data, EN, CLK Data, EN,
CLK Vhys – 1.0 – V
Maximum Clock Frequency CLK Fmax 2.0 – – MHz
Input Capacitance Data, EN, CLK Data, CLK,
EN Cin – 8.0 – pF
EN to CLK Setup T ime EN, CLK tsuEC – 200 – nS
Data to CLK Setup T ime Data, CLK tsuDC – 100 – nS
Hold T ime Data, CLK th– 90 – nS
Recovery Time EN, CLK trec – 90 – nS
Input Pulse Width EN, CLK tw– 100 – nS
MCU Interface Power–Up Delay tpuMCU – 100 – µS
Output High Voltage (Ioh = 0 mA) MCU Clk
Out Voh Tx PLL
VCC –
0.3
3.5 – V
NOTES: 1.Values specified are pure numbers to the base 10.
2.T ypical performance parameters indicate the potential of the device under ideal operating conditions.
MC33411A/B
7
MOTOROLA RF/IF DEVICE DATA
ELECTRICAL CHARACTERISTICS (continued) (VCC = 3.6 V, VB = 1.5 V, TA = 25°C, Active Mode, Rx Gain = 01111,
Vol Adj = 0111, fin = 1.0 kHz, unless otherwise noted.)
Characteristics UnitMaxTypMinSymbol
Measure
Pin
Input
Pin
MICROPROCESSOR INTERFACE (VCC = 3.6 V, VB = 1.5 V, TA = 25°C, Active or Receive Mode)
Output Low Voltage (Iol = 0 mA) MCU Clk
Out Vol – 0.1 0.3 V
Output High Voltage (Ioh = 0 mA) Data Voh Tx PLL
VCC –
0.3
3.5 – V
Output Low Voltage (Iol = 0 mA) Data Vol – 0.1 0.3 V
Rx/Tx PLL CHARACTERISTICS (VCC = 3.6 V, VB = 1.5 V, TA = 25°C, Active or Receive Mode)
Output Source Current (VPD = 0.5 V or
VCC – 0.5 V) Ioh µA
±100 µA mode Rx PD & –130 –100 –70
±400 µA mode Tx PD –520 –400 –280
Output Sink Current (VPD = 0.5 V or VCC – 0.5 V) Iol µA
±100 µA mode Rx PD & 70 100 130
±400 µA mode Tx PD 280 400 520
Current Match, ±100 µA mode or ±400 µA mode,
VPD = VCC / 2 (i.e., 100 x (ABS (Ioh / Iol ))) Rx PD
Tx PD Match 80 100 125 %
Output Off Current (VPD = VCC /2),±100 µA mode
or ±400 µA mode Rx PD
Tx PD Ioz –80 5.0 80 nA
Input Current Low (Vin = 0 V) FRx FTx Iil –10 –7.5 – µA
Input Current High (Vin = VCC)FRx FTx Iih – 10 14 µA
Input Bias Voltage FRx FTx Vbias – 1.5 – V
Output Voltage High (Ioh = 0 mA, Voltage Mode) FRxMC Voh –Rx PLL
VCC – 0.1 – V
Output Voltage High (Ioh = 0 mA, Voltage Mode) FTxMC Voh –Tx PLL
VCC – 0.1 – V
Output Voltage Low (Iol = 0 mA, Voltage Mode) FRxMC
FTxMC Vol – 0.1 – V
Output Current High (Voh = 0.8 V, Current Mode) FRxMC
FTxMC Ioh –130 –100 –70 µA
Output Current Low (Vol = 0.8 V, Current Mode) FRxMC
FTxMC Iol 70 100 130 µA
Maximum Input Frequency FRx
FTx Fmax 20 – – MHz
Input Voltage Swing FRx
FTx Vin 200 – 1200 mVpp
Modulus Control Prop Delay FRx
FTx FRxMC
FTxMC – – 20 – nS
LO2 PLL CHARACTERISTICS (VCC = 3.6 V, VB = 1.5 V, TA = 25°C, Active Mode)
Output Source Current (VPD = 0.5 V or
VCC – 0.5 V) LO2PD Ioh µA
±100 µA mode –130 –100 –70
±400 µA mode –520 –400 –280
Output Sink Current (VPD = 0.5 V or VCC – 0.5 V) LO2PD Iol µA
±100 µA mode 70 100 130
±400 µA mode 280 400 520
Current Match, ±100 µA mode or ±400 µA mode,
VPD = VCC / 2 (i.e., 100 x (ABS (Ioh / Iol ))) LO2PD Match 80 100 125 %
NOTES: 1.Values specified are pure numbers to the base 10.
2.T ypical performance parameters indicate the potential of the device under ideal operating conditions.
MC33411A/B
8MOTOROLA RF/IF DEVICE DATA
ELECTRICAL CHARACTERISTICS (continued) (VCC = 3.6 V, VB = 1.5 V, TA = 25°C, Active Mode, Rx Gain = 01111,
Vol Adj = 0111, fin = 1.0 kHz, unless otherwise noted.)
Characteristics UnitMaxTypMinSymbol
Measure
Pin
Input
Pin
LO2 PLL CHARACTERISTICS (VCC = 3.6 V, VB = 1.5 V, TA = 25°C, Active Mode)
Output Off Current (VPD = VCC /2) LO2PD Ioz –80 5.0 80 nA
Input Current Low (Vin = 0.5 V) LO2Ctl Iil –1.0 –0.02 – µA
Input Current High (Vin = VCC – 0.5 V) LO2Ctl Iih – 0.02 1.0 µA
Input Voltage Range LO2Ctl Vrange 0.4 – VCC V
Maximum 2nd LO Frequency 65 80 – MHz
LO2 Out Drive (25 Ω load) Vout 112 180 245 mVpp
COUNTERS (VCC = 3.6 V, VB = 1.5 V, TA = 25°C, Active Mode)
12–Bit Reference Counter Range [Note 1] –3 to 4095 –
13–Bit N Counter Range [Note 1] –3 to 8191 –
7–Bit A Counter Range [Note 1]
64/65 Modulus Prescaler –0 to 63 –
128/129 Modulus Prescaler –0 to 127 –
14–Bit LO2 Counter Range [Note 1] –12 to
16383 –
6–Bit Counters (for SCF) [Note 1] –3 to 63 –
NOTES: 1.Values specified are pure numbers to the base 10.
2.T ypical performance parameters indicate the potential of the device under ideal operating conditions.
ÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁ
ÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁ
PIN FUNCTION DESCRIPTION
ÁÁÁÁ
ÁÁÁÁ
Pin
ÁÁÁÁÁÁ
ÁÁÁÁÁÁ
Symbol/Type
ÁÁÁÁÁÁÁÁÁÁÁÁÁ
ÁÁÁÁÁÁÁÁÁÁÁÁÁ
Description
ÁÁÁÁÁÁÁÁÁÁÁÁÁÁ
ÁÁÁÁÁÁÁÁÁÁÁÁÁÁ
Description
1FRx MC
(Output)
FRx MC
1
Rx PLL VCC
Current Mode
Rx PLL VCC
V oltage Mode
100 µA
100 µA
Modulus Control Output for the Rx PLL section.
Can be set to output in current mode or voltage
mode, selectable with bit 3/16.
2 FRx
(Input)
FRx
2
PLL
VCC
Bias
80 µA
200 k
Receives the signal from the external 64/65 or
128/129 prescaler. DC bias is at 1.3 V.
NOTE: 1. All VCC pins must be within ±0.5 V of each other.
MC33411A/B
9
MOTOROLA RF/IF DEVICE DATA
ÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁ
ÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁ
PIN FUNCTION DESCRIPTION (continued)
ÁÁÁÁÁÁÁÁÁÁÁÁÁÁ
ÁÁÁÁÁÁÁÁÁÁÁÁÁÁ
Description
ÁÁÁÁÁÁÁÁÁÁÁÁÁ
ÁÁÁÁÁÁÁÁÁÁÁÁÁ
Description
ÁÁÁÁÁÁ
ÁÁÁÁÁÁ
Symbol/Type
ÁÁÁÁ
ÁÁÁÁ
Pin
3Rx PLL VCC
(Input) 3
Rx PLL
Section
VCC
100.0110
Supply pin for the Rx PLL section. Allowable range
is 2.7 to 5.5 V and must be within 0.5 V of all other
VCC pins. Good bypassing is required and isolation
with a 10 Ω resistor is recommended.
4Rx PD
(Output)
Rx PD
4
100/
400 µA
Rx PLL VCC
100/
400 µA
Rx
PLL
VCC
125
125
to Filter
Rx Phase Detector Output. The output either
sources or sinks current, or neither, depending on
the phase difference of the phase detector input
signals. During lock, very narrow pulses with a
frequency equal to the PLL reference frequency are
present. Output current is either ±100 µA or
±400 µA, selectable with bit 2/20.
5PLL Gnd Ground pin for the PLL section. A direct connection
to a ground plane is strongly recommended.
6 Tx PD
(Output) Same as Pin 4, except powered from Tx PLL VCC.Tx Phase Detector Output. Description same as for
Pin 4, except bit 1/20 controls the current level.
7Tx PLL VCC
(Input) 7
Tx PLL
Section,
MCU Serial
Interface,
Reference
Oscillator
VCC
100.0110
Supply pin for the Tx PLL section, MCU Serial
Interface, MCU Clock Counter, and the Reference
Oscillator. Allowable range is 2.7 to 5.5 V and must
be within 0.5 V of all other VCC pins. Good
bypassing is required and isolation with a 10 Ω
resistor is recommended.
8 FTx
(Input) Same as Pin 2. Receives the signal from the external 64/65 or
128/129 prescaler. DC bias is at 1.5 V.
9FTx MC
(Output)
FTx MC
9
Tx PLL VCC
Current Mode
Tx PLL VCC
V oltage Mode
100 µA
100 µA
Modulus Control Output for the Tx PLL section. Can
be set to output in a current mode or a voltage
mode, selectable with bit 3/16.
NOTE: 1. All VCC pins must be within ±0.5 V of each other.
MC33411A/B
10 MOTOROLA RF/IF DEVICE DATA
ÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁ
ÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁ
PIN FUNCTION DESCRIPTION (continued)
ÁÁÁÁÁÁÁÁÁÁÁÁÁÁ
ÁÁÁÁÁÁÁÁÁÁÁÁÁÁ
Description
ÁÁÁÁÁÁÁÁÁÁÁÁÁ
ÁÁÁÁÁÁÁÁÁÁÁÁÁ
Description
ÁÁÁÁÁÁ
ÁÁÁÁÁÁ
Symbol/Type
ÁÁÁÁ
ÁÁÁÁ
Pin
10 EN
(Input)
Enable
10
Tx PLL
VCC
240
≈1.0 µA
Enable Input for the MCU Interface section.
Hysteresis threshold is within 0.5 V of ground and
VCC. See text for proper waveform required at this
pin.
11 CLK
(Input) Same as Pin 10. Clock Input for the MCU Interface section.
Hysteresis threshold is within 0.5 V of ground and
VCC. Data is written or read out on clock’s rising
edge. Maximum clock rate is 2.0 MHz.
12 Data
(I/O)
Data
12
Tx PLL
VCC
240
1.0 µA
Tx PLL
VCC
Disable
Data
Data I/O line for the MCU Interface section. Both
address and data are provided to/from this pin.
Input threshold is within 0.5 V of ground and VCC.
Data is written or read out on clock’s rising edge.
13 MCU Clk Out
(Output)
Clk Out
13
Tx PLL
VCC
1.0 k
Tx PLL
VCC
The microprocessor clock output is derived from the
reference oscillator and a programmable divider
with divide ratios of 2 to 312.5. It can be used to
drive a microprocessor and thereby reduce the
number of crystals required in the system design.
The driver has an internal resistor in series with the
output which can be combined with an external
capacitor to form a low–pass filter to reduce
radiated noise on the PCB. This output also
functions as the output for the counter test modes.
1) For the MC33411A the Clk Out can be disabled
via the MCU interface.
2) For the MC33411B this output is always active
(on).
14 Gnd Digital Ground for the Data, MCU Clk Out, and Fref Out
digital Outputs. A direct connection to the ground
plane is strongly recommended.
NOTE: 1. All VCC pins must be within ±0.5 V of each other.
MC33411A/B
11
MOTOROLA RF/IF DEVICE DATA
ÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁ
ÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁ
PIN FUNCTION DESCRIPTION (continued)
ÁÁÁÁÁÁÁÁÁÁÁÁÁÁ
ÁÁÁÁÁÁÁÁÁÁÁÁÁÁ
Description
ÁÁÁÁÁÁÁÁÁÁÁÁÁ
ÁÁÁÁÁÁÁÁÁÁÁÁÁ
Description
ÁÁÁÁÁÁ
ÁÁÁÁÁÁ
Symbol/Type
ÁÁÁÁ
ÁÁÁÁ
Pin
15, 16 Fref In,
Fref Out
16
Fref Out
Fref In
15
100
100
Tx PLL
VCC
Tx PLL
VCC
Disable
Reference Frequency Input for various portions of
the circuit, including the PLLs, SCF clock, etc.
A crystal (4 to 18.25 MHz) may be connected as
shown, or an external frequency source may be
capacitor coupled to Pin 15. See text for crystal
requirements.
1) For the MC33411A the Fref Out can be disabled
via the MCU interface.
2) For the MC33411B this output is always active
(on).
17 DS Out
(Output)
DS Out
17
VCC
Audio
VCC
Audio
100 k
Data Slicer Output (open collector with internal
100 kΩ pull–up resistor).
18 Tx Out
(Output)
,
18, 20
VCC
Audio
Tx Out is the Tx path audio output. Internally this
pin has a low–pass filter circuitry with –3.0 dB
bandwidth of 4.0 kHz. Tx gain and mute are
programmable through the MCU interface. This pin
is sensitive to load capacitance.
20 C Out
(Output)
Tx Out
,
C Out
VB
C Out is the compressor output.
19 Lim In
(Input)
Lim In
19
VCC
Audio
400 k
VB
Lim In is the limiter input. This pin is internally
biased and has an input impedance of 400 kΩ.
Lim In must be ac–coupled.
21 Ccap
Ccap
21
VCC
Audio VCC
Audio
40 k
Ccap is the compressor rectifier filter capacitor pin. It
is recommended that an external filter capacitor to
VCC audio be used. A practical capacitor range is
0.1 to 1.0 µF. The recommended value is 0.47 µF.
NOTE: 1. All VCC pins must be within ±0.5 V of each other.
MC33411A/B
12 MOTOROLA RF/IF DEVICE DATA
ÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁ
ÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁ
PIN FUNCTION DESCRIPTION (continued)
ÁÁÁÁÁÁÁÁÁÁÁÁÁÁ
ÁÁÁÁÁÁÁÁÁÁÁÁÁÁ
Description
ÁÁÁÁÁÁÁÁÁÁÁÁÁ
ÁÁÁÁÁÁÁÁÁÁÁÁÁ
Description
ÁÁÁÁÁÁ
ÁÁÁÁÁÁ
Symbol/Type
ÁÁÁÁ
ÁÁÁÁ
Pin
22 C In
(Input)
C In
22
VCC
Audio
12.5 k
VB
C In is the compressor input. This pin is internally
biased and has an input impedance of 12.5 kΩ.
C In must be ac–coupled.
23 VCC Audio
(Input) 23
Audio
Section,
Filters, A/D
Converters,
Data Slicer
VCC
0.0110
Supply input for the audio section, filters, A/D
Converters, and Data Slicer. Allowable range is 2.7
to 5.5 V. Good bypassing is required.
24 MCO
(Output)
MCO
24
Audio
VCC Output of the Microphone amplifier. Maximum
output swing is ≈3.0 Vpp for VCC ≥ 3.0 V.
Maximum output current is >1.0 mA peak.
25 MCI
(Input)
MCI
25
VCC
Audio
2.5 µA
VB
Inverting input of the microphone amplifier. Gain
and frequency response are set with external
resistors and capacitors from this pin to the audio
source and to MCO.
26 VAG
(Output)
VAG
26 0.1
µF
30 k
Audio
VCC Analog ground for the audio section filters. VAG is
equal to VB and is buffered from VB. Maximum
current which can be sourced from this pin is
500 µA.
27 VB
(Output)
VB
27 4.7
µF
30 k
Audio
VCC
240
An internal 1.5 V reference for several sections.
This voltage is adjustable with bits 3/20–17.
Maximum source current is 100 µA. PSRR, noise
and crosstalk depends on the external capacitor.
28 VCC PA
(Input) 28
Audio
Power
VCC
0.0110
Supply pin for the power amplifier outputs.
Allowable range is 2.7 to 5.5 V. Good bypassing is
required.
NOTE: 1. All VCC pins must be within ±0.5 V of each other.
MC33411A/B
13
MOTOROLA RF/IF DEVICE DATA
ÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁ
ÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁ
PIN FUNCTION DESCRIPTION (continued)
ÁÁÁÁÁÁÁÁÁÁÁÁÁÁ
ÁÁÁÁÁÁÁÁÁÁÁÁÁÁ
Description
ÁÁÁÁÁÁÁÁÁÁÁÁÁ
ÁÁÁÁÁÁÁÁÁÁÁÁÁ
Description
ÁÁÁÁÁÁ
ÁÁÁÁÁÁ
Symbol/Type
ÁÁÁÁ
ÁÁÁÁ
Pin
29 PAO+
(Output)
PAO+
29
Audio
VCC Output of the second power amplifier. This amplifier
is set for unity inverting gain and is driven by PAO–.
Maximum swing is 2.9 Vpp and maximum output
current is >5.0 mA peak. DC level is ≈1.5 V.
30 PAO–
(Output) Same as Pin 29. Output of the first power amplifier. Its gain is set
with external resistors and capacitors from this pin
to PAI. Output capability is the same as Pin 28.
31 Gnd PA Ground pin for the power amplifier outputs. A direct
connection to a ground plane is strongly
recommended.
32 PAI
(Input)
PAI
32
VCC
Audio
2.5 µA
VB
Inverting input of the power amplifier. Gain and
frequency response are set with external resistors
and capacitors from this pin to the audio source and
to PAO–.
33 E Out
(Output)
Rx Audio
Output
33
Audio
VCC
VB
Expander output. This output is sensitive to load
capacitance. Maximum output signal level is
≈2.5 Vpp. Maximum output current is >1.0 mA.
34 Ecap
Ecap
34
VCC
Audio
VCC
Audio
40 k
Ecap is the expander rectifier filter capacitor pin.
Connect an external filter capacitor between VCC
audio and Ecap. The recommended capacitance
range is 0.1 to 1.0 µF. The suggested value is
0.47 µF.
35 E In
(Input)
E In
35
VCC
Audio
VB
30 k
The expander input pin is internally biased and has
input impedance of 30 kΩ.
36 Rx Out
(Output)
Rx Out
36
VCC
Audio
VB
Rx Out is the Rx audio output. An internal low–pass
filter has a –3.0 dB bandwidth of 4.0 kHz.
NOTE: 1. All VCC pins must be within ±0.5 V of each other.
MC33411A/B
14 MOTOROLA RF/IF DEVICE DATA
ÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁ
ÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁ
PIN FUNCTION DESCRIPTION (continued)
ÁÁÁÁÁÁÁÁÁÁÁÁÁÁ
ÁÁÁÁÁÁÁÁÁÁÁÁÁÁ
Description
ÁÁÁÁÁÁÁÁÁÁÁÁÁ
ÁÁÁÁÁÁÁÁÁÁÁÁÁ
Description
ÁÁÁÁÁÁ
ÁÁÁÁÁÁ
Symbol/Type
ÁÁÁÁ
ÁÁÁÁ
Pin
37 RSSI In
(Input)
RSSI In
37
VCC
Audio Voltage input to RSSI A/D converter. Full scale is 0
to 1.6 V.
38 Rx Audio In
(Input)
Rx Audio
In
38
VCC
Audio
600 k
VB
RC
Network
Input to the Rx Audio Path. Input impedance is
600 kΩ. Input signal must be capacitor coupled
39 DS In
(Input)
DS In
39
VCC
Audio
250 k250 k
Input for the digital data from the RF Receiver
section. Input impedance is 250 kΩ. Hysteresis is
internally provided. Input signal level must be
between 50 and 700 mVpp.
40 Gnd Audio Ground pin for the audio section. A direct
connection to a ground plan is strongly
recommended.
41 LO2 Out
(Output)
LO2 Out
41
LO2
VCC LO2
VCC
LO2
VCC 50
2.5 mA
Buffered output of the 2nd LO. This high frequency
output is a current, requiring an external pullup
resistor.
42 LO2 VCC
(Input) 42
LO2
Section
VCC
100.0110
Supply pin for the LO2 section. Allowable range is
2.7 to 5.5 V and must be within 0.5 V of all other
VCC pins. Good bypassing is required and isolation
with a 10 Ω resistor is recommended.
NOTE: 1. All VCC pins must be within ±0.5 V of each other.
MC33411A/B
15
MOTOROLA RF/IF DEVICE DATA
ÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁ
ÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁ
PIN FUNCTION DESCRIPTION (continued)
ÁÁÁÁÁÁÁÁÁÁÁÁÁÁ
ÁÁÁÁÁÁÁÁÁÁÁÁÁÁ
Description
ÁÁÁÁÁÁÁÁÁÁÁÁÁ
ÁÁÁÁÁÁÁÁÁÁÁÁÁ
Description
ÁÁÁÁÁÁ
ÁÁÁÁÁÁ
Symbol/Type
ÁÁÁÁ
ÁÁÁÁ
Pin
43, 45 LO2+, LO2–
LO2+
43
LO2
VCC
LO2
VCC
The 2nd LO. External tank components are
required. The internal capacitance across the pins
is adjustable from 0 to 7.6 pF for fine tuning
performance with bits 7/20–18.
44 LO2 Ctl
(Input) LO2–
45
LO2 Ctl
44
LO2
VCC
55 k
LO2 Control is the dc control input for this VCO.
Typically it is the output of the low–pass filter fed
from the phase detector output.
46 LO2 Gnd Ground pin for the LO2 section. A direct connection
to a ground plane is strongly recommended.
47 LO2PD
(Output)
LO2 PD
47
100/
400 µA
LO2 PLL VCC
100/
400 µA
LO2
PLL
VCC
125
125
to Filter
LO2 Phase Detector Output. The output either
sources or sinks current, or neither, depending on
the phase difference of the phase detector input
signals. During lock, very narrow pulses with a
frequency equal to the PLL reference frequency are
present. Output current is either ±100 µA or
±400 µA, selectable with bit 3/14.
48 LO2 Gnd Ground pin for the LO2 section. A direct connection
to a ground plane is strongly recommended.
NOTE: 1. All VCC pins must be within ±0.5 V of each other.
MC33411A/B
16 MOTOROLA RF/IF DEVICE DATA
FUNCTIONAL DESCRIPTION
The following text, graphics, tables and schematics are
provided to the user as a source of valuable technical
information about the MC33411. This information originates
from thorough evaluation of the device performance. This
data was obtained by using units from typical wafer lots. It is
important to note that the forgoing data and information was
from a limited number of units. By no means is the user to
assume that the data following is a guaranteed parametric.
Only the minimum and maximum limits identified in the
electrical characteristics tables found earlier in the spec are
guaranteed.
Note: In the following descriptions, control bits in the MCU
Serial Interface for the various functions will be identified by
register number and bit number. For example, bit 3/19
indicates bit 19 of register 3. Bits 5/14–1 1 indicates register 5,
bits 14 through 11. Please refer to Figure 1.
General Circuit Description
The MC3341 1A/B is a low power baseband IC designed to
interface with the MC13145 UHF Wideband Receiver and
MC13146 Transmitter for applications up to 2.0 GHz. The
devices are primarily designated to be used for 900 MHz ISM
band in a CT–900, low power, dual conversion cordless
phone, but other applications such as data links with analog
processing could be developed. This device contains
complete baseband transmit and receive processing
sections, a transmit and receive PLL section, a
programmable PLL second local oscillator usable to 80 MHz,
RSSI and low battery detect circuitry and serial interface for a
microprocessor.
”A” versions of the device have the ability to disable either
the reference oscillator or MCU clock outputs. This feature is
useful for systems where the MCU has an internal clock,
allowing the user to place the MC33411 into Inactive (lowest
power consumption) mode. The ”A” version is also useful for
systems where the MCU has a dedicated clock source,
allowing for lower power consumption from the MC33411 by
disabling the MCU clock output.
”B” versions of the device are intended for systems where
the MCU clock will always be driven from the MC33411.
These bits are purposefully ”hard–wired” to the enable state
to ensure proper operation of the reference oscillator and
MCU clock output even during battery discharge/recharge
cycles.
All internal registers are completely static – no refreshing
is required under normal operation conditions.
DC Current
Figures 2 through 5 are the current consumption for
Inactive (MC33411 ”A” version only), Standby, Receive, and
Active modes versus supply voltages. Figures 6 and 7 show
the typical behavior of current consumption in relation to
temperature.
Figure 8 illustrates the effect of the MCU clock output
frequency to supply current during Active mode.
0
SUPPLY CURRENT (mA)
1.8
2.7
6.0
2.7 SUPPLY VOLTAGE (V)
S
UPPL
Y
C
U
RREN
T ( A)
Figure 2. Supply Current versus
Supply Voltage (Inactive Mode)
SUPPLY VOLTAGE (V)
Figure 3. Supply Current versus
Supply Voltage (Standby Mode)
5.0
4.0
3.0
2.0
1.0
3.1 3.5 3.9 4.3 4.7 5.5
1.6
1.4
1.2
1.0
0.8
0.6
0.4
0.0 3.1 3.5 3.9 4.3 5.1 5.5
TA = 25°CTA = 25°C
5.1
µ
4.7
MCU Clock Off
MC33411A/B
17
MOTOROLA RF/IF DEVICE DATA
S
UPPL
Y
C
U
RREN
T (
m
A)
10
2.7 SUPPLY VOLTAGE (V)
TA = 25°C
Figure 4. Supply Current versus
Supply Voltage (Receive Mode)
9.5
9.0
8.5
8.0
7.5 3.1 3.5 3.9 4.3 4.7 5.1 5.5 11
14
2.7
SUPPLY CURRENT (mA)
Figure 5. Supply Current versus
Supply Voltage (Active Mode)
SUPPLY VOLTAGE (V)
TA = 25°C
13
12
3.5 5.5
Figure 6. Supply Current versus Temperature
Normalized to 25°C (Standby Mode)
VCC = 3.6 V
Figure 7. Supply Current versus Temperature
Normalized to 25°C (Receive & Active Mode)
VCC = 3.6 V
12.5
30
SUPPLY CURRENT (mA)
MCU CLK OUT (kHz)
Figure 8. Supply Current versus
MCU Clock Output Frequency (Active Mode)
VCC = 3.6 V
TA = 25°C
2030 5030
12.3
12.1
11.9
11.7
11.5
MCU Clock Out Off
MCU Clock Out On
3.1 3.9 4.3 4.7 5.1
MCU Clock Out On
MCU Clock Out Off
1030 3030 4030
20
–20
740
–20
ICC, (mA)
DEGREES (°C)
ICC, ( A)
DEGREES (°C)
0257085
720
700
680
660
640
620
600
µ
19
18
17
16
15
14
13
12
11
10 –5.0 10 25 40 55 70 85
Active
Receive
MC33411A/B
18 MOTOROLA RF/IF DEVICE DATA
ÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁ
ÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁ
Table 1. Tx Gain Adjust Programming (Register 7)
Gain Control
Bit #9 Gain Control
Bit #8 Gain Control
Bit #7 Gain Control
Bit #6 Gain Control
Bit #5 Gain
Ctl # Gain/Attenuation
Amount
<6 –9.0 dB
0 0 1 1 0 6 –9.0 dB
0 0 1 1 1 7 –8.0 dB
0 1 0 0 0 8 –7.0 dB
0 1 0 0 1 9 –6.0 dB
0 1 0 1 0 10 –5.0 dB
0 1 0 1 1 11 –4.0 dB
0 1 1 0 0 12 –3.0 dB
0 1 1 0 1 13 –2.0 dB
0 1 1 1 0 14 –1.0 dB
0 1 1 1 1 15 0 dB
1 0 0 0 0 16 1.0 dB
1 0 0 0 1 17 2.0 dB
1 0 0 1 0 18 3.0 dB
1 0 0 1 1 19 4.0 dB
1 0 1 0 0 20 5.0 dB
1 0 1 0 1 21 6.0 dB
1 0 1 1 0 22 7.0 dB
1 0 1 1 1 23 8.0 dB
1 1 0 0 0 24 9.0 dB
1 1 0 0 1 25 10 dB
– – – – – >25 10 dB
Transmit Speech Processing System
This portion of the audio path goes from ”Tx Audio” to ”Tx
Out”. The gain of the microphone amplifier is set with external
resistors to receive the audio from the microphone hybrid or
any other audio source. The MCO output has rail–to–rail
capability. The ”Tx Audio” pin will be ac–coupled. The audio
transmit signal path includes automatic level control (ALC)
(also referred to as the Compressor), Tx mute, limiter, filters,
and Tx gain adjust. The ALC provides ”soft” limiting to the
output signal swing as the input voltage slowly increases.
With this technique the gain is slightly lowered to help reduce
distortion of the audio signal. The limiter section provides
hard limiting due to rapidly changing singal levels, or
transients. The ALC, TX mute, and limiter functions can be
enabled or disabled vis the MCU serial interface. The Tx gain
adjust can also be remotely controlled to set different desired
signal levels.
The adjustable gain stage provides 20 levels of gain in
1.0 dB increments. It is controlled with bits 7/9–5 as shown in
Table 1. The effect of the gain setting under various
ALC/Limiter On/Off settings is shown in Figure 9.
The Low–Pass Filter before the gain stage is a switched
capacitor filter with a corner frequency at 3.7 kHz. This
frequency is dependent upon the SCF clock, nominaly set to
165 kHz and is directly proportional to the SCF clock. The
filter response for inband, ripple, wideband, as well as phase
and group delay, are shown in Figures 10 through 14.
The mute switch at Pin 18 will mute a minimum of 60 dB.
Bit 6/2 controls the mute. The limiter can be disabled by
programming a logic 1 into 6/5.
The compressor with ALC transfer characteristic is shown
in Figure 15. The ALC gain is controlled by bits 6/11–12. If
both bits are programmed to a logic 0, the ALC gain is set to
5.0 dB. If bit 6/11 is set to a logic 1, the ALC gain will be set to
10 dB, whereas if bit 6/12 is set to a logic 1 the ALC gain will be
25 dB . The ALC function may be disabled by programming a
logic 1 into bit 6/6.
The compressor low maximum gain can be set with bit 6/8.
Programming this bit to a logic 0 sets the maximum gain to
23 dB. A lower maximum gain, nominally 13.5 dB, is
achieved by programming the bit to a logic 1. The entire
compressor can be bypassed (i.e., 0 dB) by programming bit
6/4 to a logic 1.
Figures 16 through 22 describe the characteristics of the
compressor, ALC, and limiter.
MC33411A/B
19
MOTOROLA RF/IF DEVICE DATA
–10
–12
–9.0 Tx GAIN SETTING (dB)
MAX Tx OUT
V
OLTAG
E
(d
BV
)
2.0
0
–2.0
–4.0
–6.0
–8.0
–14
–16
–18
–20 1.0 11
Figure 9. Tx Audio Output Voltage
versus Gain Control Setting 5.0
100 f, FREQUENCY (Hz)
Figure 10. Lim In to Tx Out
Gain versus Frequency (Inband)
VCC = 3.6 V
TA = 25°C
Vin = –10 dBV
VOLT AGE GAIN (dB)
0
–5.0
–10
–15
–20
–25
–30
–35
–40
–45
–50
–55 1000 10000
–100–1.5
0
100 f, FREQUENCY (Hz)
V
OLTAG
E
GAI
N
(d
B
)
Figure 11. Lim In to Tx Out
Gain versus Frequency (Ripple)
f, FREQUENCY (Hz)
Figure 12. Lim In to Tx Out
Gain versus Frequency (Wideband)
VCC = 3.6 V
TA = 25°C
Vin = –10 dBV
–0.5
–0.6
–0.7
–0.8
–0.9
–1.0
–1.1
–1.2
–1.3
–1.4
1000 10000
VCC = 3.6 V
TA = 25°C
Vin = –10 dBV
100 1000 1000000
VOLT AGE GAIN (dB)
–10
–20
–30
–40
–50
–60
–70
–80
–90
10
10000 100000
10
100
180
100
GROUP DELAY (ms)
f, FREQUENCY (Hz)f, FREQUENCY (Hz)
Figure 13. Lim In to Tx Out
Phase versus Frequency Figure 14. Lim In to Tx Out
Group Delay versus Frequency
VCC = 3.6 V
TA = 25°C
Vin = –10 dBV
PHA
SE
(d
egrees
)
135
90
45
0
–45
–90
–135
–180 1000 10000
VCC = 3.6 V
TA = 25°C
Vin = –10 dBV
1000 10000
1.0
0.1
0
–3.0 7.0
ALC On, Limiter On/Off
ALC Off, Limiter Off
ALC Off, Limiter On
–7.0 –5.0 –1.0 3.0 5.0 9.0
VCC = 3.6 V
TA = 25°C
Vin = –10 dBV
MC33411A/B
20 MOTOROLA RF/IF DEVICE DATA
0
–60 –50 –40 –30 –20 –10 0 10
–5.0
–10
–15
–20
–25
–30
–35
–40
4.0
3.0
2.0
1.0
0
DISTOR TION (%)
Tx OUT VOLTAGE (dBV)
C IN (dBV)
–30
–20
–33
–23.5
Vin > = –4.0 dBV, Vout = 1.26 Vpp
(rapidly changing limited signals)
Vin = –16 dBV,
Vout = –13 dBV
(slowly changing ALC signals)
Vin = –2.5 dBV,
Vout = –10 dBV
“Comp Low Max Gain En” = 1.0
Maximum Gain = 12
“Comp Low Max Gain En” = 0
Maximum Gain = 21
–60 –50 –40 –30 –20 –10 0
–50
–40
–30
–20
–10
0
C OUT (dBV)
0
–60
0
–60
MCI VOLT AGE (dBV)
Tx OUT VOLTAGE (dBV)
MCI VOLT AGE (dBV)
MCI VOLT AGE (dBV)
C OUT VOLTAGE (dBV)
C IN VOLT AGE (dBV)
Figure 15. Compressor Characteristic with
Programmable Compressor Maximum Gain Figure 16. Tx Audio Compressor Response
(Distortion & Amplitude, ALC off, Lim off)
Figure 17. Tx Audio Compressor Response
(Distortion & Amplitude, ALC off, Lim off) Figure 18. Tx Output Audio Response
(Lim & ALC off)
Figure 19. Tx Output Audio Response
(Lim on, ALC off) Figure 20. Tx Output Audio Response
(Lim off, ALC on)
–50 –40 –30 –20 –10 0 10
–5.0
–10
–15
–20
–25
–30
–35
–40
4.0
3.0
2.0
1.0
0
DISTOR TION (%)
–50 –40 –30 –20 –10 0 10
–5.0
–10
–15
–20
–25
–30
–35
–40
–45
14
10
6.0
2.0
0
4.0
8.0
12
DISTOR TION (%)
Compressor Transfer
Distortion
VCC = 3.6 V
TA = 25°C
R6/8 = 0
VCC = 3.6 V
TA = 25°CVCC = 3.6 V
TA = 25°C
VCC = 3.6 V
TA = 25°C
Distortion
Distortion
Tx Out
Tx Out
VCC = 3.6 V
TA = 25°C
R6/8 = 1
0
–60
C OUT VOLTAGE (dBV)
C IN VOLT AGE (dBV)
–50 –40 –30 –20 –10 0 10
–5.0
–10
–15
–20
–25
–30
–35
–40
–45
14
10
6.0
2.0
0
4.0
8.0
12
Compressor Transfer
Distortion
Tx OUT VOLTAGE (dBV)
DISTOR TION (%)
0
–60 –50 –40 –30 –20 –10 0 10
–5.0
–10
–15
–20
–25
–30
–35
–40
4.0
3.0
2.0
1.0
0
DISTOR TION (%)
Distortion
Tx Out
MC33411A/B
21
MOTOROLA RF/IF DEVICE DATA
0
–60 –50 –40 –30 –20 –10 0 10
–5.0
–10
–15
–20
–25
–30
–35
–40
4.0
3.0
2.0
1.0
0
DISTOR TION (%)
Tx OUT VOLTAGE (dBV)
MCI VOLTAGE (dBV)MCI VOLT AGE (dBV)
Figure 21. Tx Output Audio Response
(Lim off, R6/11 = 1) Figure 22. Tx Output Audio Response
(Lim off, R6/12 = 1)
VCC = 3.6 V
TA = 25°CVCC = 3.6 V
TA = 25°C
Distortion
Tx Out
Tx OUT VOLTAGE (dBV)
0
–60 –50 –40 –30 –20 –10 0 10
–5.0
–10
–15
–20
–25
–30
–35
–40
4.0
3.0
2.0
1.0
0
DISTOR TION (%)
Distortion
Tx Out
Data Slicer
The data slicer will receive the low level digital signal from
the RF receiver section at Pin 39. The input signal to the data
slicer must be >200 mVpp. Hysteresis of 40 mV is internally
provided. The output of the data slicer will be same
waveform, but with an amplitude of 0 to VCC, and can be
observed at Pin 17 if bits 5/9–8 are set to 00. The output can
be inverted by setting bit 5/9 = 1. The data slicer can be
disabled by setting bit 5/8 = 1.
Receive Audio Path
The Receive Audio Path (Pins 38, 36–33) consists of an
anti–aliasing filter , a low–pass filter , side tone attenuator , gain
adjust stage, a mute switch, expander and volume control.
The switched capacitor low–pass filter is an 8 pole filter,
with a corner frequency at 3.8 kHz. This is designed to
provide bandwidth limiting in the audio range.
The gain stage provides 20 dB of gain adjustment in
1.0 dB steps, measured from Pin 38 to 36. Bits 7/4–0 are
used to set the gain according to Table 3. The mute switch,
controlled by bit 6/1, will mute a minimum of 60 dB.
When the compressor output is within 3.0 dB of the
expander input level, the Rx output (Pin 36) can be attenuated
(referenced to the expander output) by bits 6/10–9. For
6/10–9 = 00, the attenuation is 0 dB. For the other
combinations, 6/10–9 = 01, attenuation = 3.0 dB; 6/10–9 =
10, attenuation = 6.0 dB; and 6/10–9 = 11, attenuation = 10.4
dB (See Table 2).
The expander can be bypassed by setting bit 6/3 = 1.
Table 3 shows the various gain control settings which can
be accessed in Register 7. Table 4 is the volume control
settings, also located in Register 7.
Figures 23 through 31 illustrate the various characteristics
of the reveive audio path.
ÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁ
ÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁ
Table 2. Side Tone Attenuate Programming
Side Tone
Attenuate Bit #1 Side Tone
Attenuate Bit #0 Select # Side Tone Attenuate
Amount at Expander Input Side Tone Attenuate
Amount at Expander Output
0 0 0 0 dB 0 dB
0 1 1 1.5 dB 3.0 dB
1 0 2 3.0 dB 6.0 dB
1 1 3 5.2 dB 10.4 dB
ÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁ
ÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁ
Table 3. Rx Gain Adjust Programming (Register 7)
Gain Control
Bit #4 Gain Control
Bit #3 Gain Control
Bit #2 Gain Control
Bit #1 Gain Control
Bit #0 Gain
Ctl # Gain/Attenuation
Amount
– – – – – <6 –9.0 dB
0 0 1 1 0 6 –9.0 dB
0 0 1 1 1 7 –8.0 dB
0 1 0 0 0 8 –7.0 dB
0 1 0 0 1 9 –6.0 dB
0 1 0 1 0 10 –5.0 dB
0 1 0 1 1 11 –4.0 dB
0 1 1 0 0 12 –3.0 dB
0 1 1 0 1 13 –2.0 dB
MC33411A/B
22 MOTOROLA RF/IF DEVICE DATA
ÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁ
ÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁ
Table 3. Rx Gain Adjust Programming (Register 7) (continued)
Gain Control
Bit #4 Gain/Attenuation
Amount
Gain
Ctl #
Gain Control
Bit #0
Gain Control
Bit #1
Gain Control
Bit #2
Gain Control
Bit #3
0 1 1 1 0 14 –1.0 dB
0 1 1 1 1 15 0 dB
1 0 0 0 0 16 1.0 dB
1 0 0 0 1 17 2.0 dB
1 0 0 1 0 18 3.0 dB
1 0 0 1 1 19 4.0 dB
1 0 1 0 0 20 5.0 dB
1 0 1 0 1 21 6.0 dB
1 0 1 1 0 22 7.0 dB
1 0 1 1 1 23 8.0 dB
1 1 0 0 0 24 9.0 dB
1 1 0 0 1 25 10 dB
– – – – – >25 10 dB
ÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁ
ÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁ
Table 4. Volume Control Programming
Volume Control
Bit #13 Volume Control
Bit #12 Volume Control
Bit #11 Volume Control
Bit #10 Volume
Ctl # Gain/Attenuation
Amount
0 0 0 0 0 –14 dB
0 0 0 1 1 –12 dB
0 0 1 0 2 –10 dB
0 0 1 1 3 –8.0 dB
0 1 0 0 4 –6.0 dB
0 1 0 1 5 –4.0 dB
0 1 1 0 6 –2.0 dB
0 1 1 1 7 0 dB
1 0 0 0 8 2.0 dB
1 0 0 1 9 4.0 dB
1 0 1 0 10 6.0 dB
1 0 1 1 11 8.0 dB
1 1 0 0 12 10 dB
1 1 0 1 13 12 dB
1 1 1 0 14 14 dB
1 1 1 1 15 16 dB
MC33411A/B
23
MOTOROLA RF/IF DEVICE DATA
180
100
PHASE (degrees)
f, FREQUENCY (Hz)
VCC = 3.6 V
TA = 25°C
Vin = –20 dBV
1000 100
0
135
90
45
0
–45
–90
–135
–180
10
100 f, FREQUENCY (Hz)
VCC = 3.6 V
TA = 25°C
Vin = –20 dBV
V
OLTAG
E
GAI
N
(d
B
)
0
–10
–20
–30
–40
–50
–60
–70
–80
–90
–100 1000 10000 100000 1000000
–0.7
0.3
f, FREQUENCY (Hz)
VCC = 3.6 V
TA = 25°C
Vin = –20 dBV
100 1000 100
0
VOLT AGE GAIN (dB)
0.2
0.1
0
–0.1
–0.2
–0.3
–0.4
–0.5
–0.6
–55
5.0
100
V
OLTAG
E
GAI
N
(d
B
)
f, FREQUENCY (Hz)
VCC = 3.6 V
TA = 25°C
Vin = –20 dBV
0
–5.0
–10
–15
–20
–25
–30
–35
–40
–45
–50
1000 10000
1.4
–14
2.0
–9.0
MAX E OUT VOLTAGE (dBV)
VOLUME SETTING (dB)
MAX
R
x OUT
V
OLTAG
E
(d
BV
)
Figure 23. Rx Out Maximum Output Voltage
versus Gain Control Setting
Rx GAIN SETTING (dB)
Figure 24. E Out Maximum Output Voltage
versus Volume Control Setting
Figure 25. Rx Audio In to Rx Out Gain
versus Frequency (Inband) Figure 26. Rx Audio In to Rx Out Gain
versus Frequency (Ripple)
Figure 27. Rx Audio In to Rx Out Gain
versus Frequency (Wideband) Figure 28. Rx Audio In to Rx Out Phase
versus Frequency
–10 –6.0 –2.0 2.0 6.0 10 14
1.2
1.0
0.8
0.6
0.4
–7.0 –5.0 –3.0 –1.0 1.0 3.0 5.0 7.0 9.0 11
0
–2.0
–4.0
–6.0
–8.0
–10
–12
–14
–16
–18
–20
VCC = 3.6 V
TA = 25°CVCC = 3.6 V
TA = 25°C
MC33411A/B
24 MOTOROLA RF/IF DEVICE DATA
10
100 f, FREQUENCY (Hz)
VCC = 3.6 V
TA = 25°C
Vin = –20 dBV
1.0
0.1
01000 10000
GROUP DELAY (ms)
10
100
5.0
–40
VOLT AGE GAIN (dB)
f, FREQUENCY (Hz)
E OUT VOLTAGE (dBv)
E IN VOLTAGE (dBV)
Figure 29. Rx Audio In to Rx Out
Group Delay versus Frequency Figure 30. AALPF Response
Gain versus Frequency
Figure 31. E In to E Out
Transfer Curve
1000 10000 100000 1000000
0
–10
–20
–30
–40
–50
–60
–70
–80
–90
–100
VCC = 3.6 V
TA = 25°C
Vin = –20 dBV
SCF Clk = 2.5 MHz
SCF Corner = 57 kHz
–35 –30 –25 –20 –15 –10 –5.0 0
–5.0
–15
–25
–35
–45
–55
–65
Expander Transfer
Distortion
28
24
20
16
12
8.0
4.0
0
DISTOR TION (%)
VCC = 3.6 V
TA = 25°C
MC33411A/B
25
MOTOROLA RF/IF DEVICE DATA
Power Amplifiers
The power amplifiers (Pins 29, 30, 32) are designed to
drive the earpiece in a handset, or the telephone line via a
hybrid circuit in the base unit. Each output (PAO+ and P AO–)
can source and sink 5.0 mA, and can swing 1.3 Vpp each. For
high impedance loads, each output can swing 2.7 Vpp (5.4
Vpp differential). The gain of the amplifiers is set with a
feedback resistor from Pin 30 to 32, and an input resistor at
Pin 32. The differential gain is 2x the resistor ratio. Capacitors
can be used for frequency shaping. The pins’ dc level is VB
(≅1.5 V).
The Mute switch, controlled with bit 6/0, will provide 60 dB
of muting with a 50 kΩ feedback resistor. The amount of
muting will depend on the value of the feedback resistor.
Figures 32 and 33 show the power amplifier
swing/distortion for VCC = 3.6 V, and Figure 34 illustrates the
maximum swing capability for various value of VCC.
0
3.2
0PAI (Vpp)
2.0
1.2
02.4 4.4
PAO
–
(
V
)
20
3.5
2.5
PAO– (DISTORTION %)
PAI (Vpp)
V
CC
(V)
Figure 32. Power Amplifier
Maximum Output Swing Figure 33. Power Amplifier
Distortion
Figure 34. Power Amplifier
Maximum Output Swing versus VCC
0.4 0.8 1.2 1.6 2.0 2.8 3.2 3.6 4.0
0.4
0.8
1.6
2.4
2.8
pp
Open
130 Ω
Open
2.4 4.40.4 0.8 1.2 1.6 2.0 2.8 3.2 3.6 4.0
15
10
5.0
0
130 Ω
VCC = 3.6 V
TA = 25°C
VCC = 3.6 V
TA = 25°C
PAO
–
(
V
)
pp
3.0
2.5
2.0
1.5
1.0
0.5
03.0 3.5 4.0 4.5 5.0 5.5
Open
130 Ω
TA = 25°C
MC33411A/B
26 MOTOROLA RF/IF DEVICE DATA
Reference Oscillator/MCU Clk Out
The reference oscillator provides the frequency basis for
the three PLLs, the switched capacitor filters, and the MCU
clock output. The source for the reference clock can be a
crystal in the range of 4.0 to 18.25 MHz connected to Pins
15 & 16, or it can be an external source connected to Fref In
(Pin 15). The referenc e frequency is directed to:
a. A programmable 12–bit counter (register bits 4/11–0) to
provide the reference frequency for the three PLLs. The
12–bit counter is to be set such that, in conjunction with the
programmable counters within each PLL, the proper
frequencies can be produced by each VCO.
b. A programmable 6–bit counter (register bits 4/17–12),
followed by a ÷2 stage, to set the frequency for the switched
capacitor filters to 165 kHz, or as close to that as possible.
c. A programmable 3–bit counter (register bits 7/16–14)
which provides the MCU clock output (see Tables 5 and 6).
A representation of the reference oscillator is given by
Figures 35 and 36.
Figure 35. Reference Oscillator Schematic
Reference Oscillator
RPI CPI RPO
CPO
Gm
Fref In Fref Out
Xtal
C2
C1
ÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁ
Á
ÁÁÁÁÁÁÁÁÁÁÁÁÁÁ
Á
ÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁ
Figure 36. Reference Oscillator
Input and Output Impedance
ÁÁÁÁÁÁÁÁÁ
ÁÁÁÁÁÁÁÁÁ
Input Impedance (RPI // CPI)
ÁÁÁÁÁÁÁÁ
ÁÁÁÁÁÁÁÁ
11.6 kΩ // 2.9 pF
ÁÁÁÁÁÁÁÁÁ
ÁÁÁÁÁÁÁÁÁ
Output Impedance (RPO // CPO)
ÁÁÁÁÁÁÁÁ
ÁÁÁÁÁÁÁÁ
4.5 kΩ // 2.5 pF
Figures 37 and 38 show a typical gain/phase response of
the oscillator. Load capacitance (CL), equivalent series
resistance (ESR), and even supply voltage will have an effect
on the oscillator response as shown in Figures 39 and 40. It
should be noted that optimum performance is achieved when
C1 equals C2 (C1/C2 = 1).
Figure 41 represents the ESR versus crystal load
capacitance for the reference oscillator . This relationship was
defined by using a 6.0 dB minimum loop gain margin at 3.6 V.
This is considered the minimum gain margin to guarantee
oscillator start–up.
Oscillator start–up is also significantly affected by the
crystal load capacitance selection. In Figure 39, the
relationship between crystal load capacitance and ESR can
be seen. The lower the load capacitance the better the
performance.
Given the desired crystal load capacitance, C1 and C2
can be determined from Figure 42. It should also be pointed
out that current consumption increases when C1 ≠ C2.
Be careful not to overdrive the crystal. This could cause a
noise problem. An external series resistor on the crystal
output can be added to reduce the drive level, if necessary.
MC33411A/B
27
MOTOROLA RF/IF DEVICE DATA
100
10.237
16
10.237 f, FREQUENCY (MHz)f, FREQUENCY (MHz)
PHASE (degrees)
V
OLTAG
E
GAI
N
(d
B
)
14
12
10
8.0
6.0
4.0
2.0
0
–2.0
–4.0 10.238 10.239 10.240 10.241 10.242 10.243 10.238 10.239 10.240 10.241 10.242 10.24
80
60
40
20
0
–20
–40
–60
–80
–100
VCC = 3.6 V
TA = 25°C
10.24 MHz, 10 pF
Load Capacitance
Crystal
VCC = 3.6 V
TA = 25°C
10.24 MHz, 10 pF
Load Capacitance
Crystal
Fref out
16 Fref in
15
13 pF13 pF
Fref out
16 Fref in
15
13 pF13 pF
20
0
1000
10
5.0
0
GAIN (dB)
TOTAL ESR (Ω)
MAXIMUM
ESR
( )
CRYSTAL LOAD CAPACITANCE (pF)
S
TA
R
T UP TIM
E
(
ms
)
TOTAL ESR (Ω)
VCC = 3.6 V
TA = 25°C
Figure 37. Reference Oscillator
Open Loop Gain versus Frequency Figure 38. Reference Oscillator
Open Loop Phase versus Frequency
Figure 39. Reference Oscillator Startup Time
versus Total ESR – Inactive to Rx Mode Figure 40. Reference Oscillator
Open Loop Gain versus ESR
Figure 41. Maximum ESR versus
Crystal Load Capacitance (C1 = C2)
VCC = 3.6 V
TA = 25°C
4.0
3.0
2.0
1.0
050 100 150 200 250 300 350
2.048 MHz
5.12 MHz
16
12
8.0
4.0
050 100 150 200 250 300 350
100
10 12 14 16 18 20 22 24 26 28 30 32
Ω
70
5.0
C1 AND C2 (pF)
CRYSTAL LOAD CAPACITANCE (pF)
Figure 42. Optimum Values for C1, C2 versus
Equivalent Required Parallel Capacitance
60
50
40
30
20
10
010 15 20 25 30 35
MC33411A/B
28 MOTOROLA RF/IF DEVICE DATA
ÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁ
ÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁ
Table 5. MCU Clock Divider Programming
MCU Clk Bit #16 MCU Clk Bit #15 MCU Clk Bit #14 Clk Out Divider Value
0 0 0 2.0
0 0 1 3.0
0 1 0 4.0
0 1 1 5.0
1 0 0 2.5
1 0 1 20
1 1 0 80
1 1 1 312.5
ÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁ
ÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁ
Table 6. MCU Clock Divider Frequencies
Crystal
Clock Output Divider
Crystal
Frequency 2.0 2.5 3.0 4.0 5.0 20 80 312.5
10.24 MHz 5.12 MHz 4.096 MHz 3.413 MHz 2.56 MHz 2.048 MHz 512 kHz 128 kHz 32.768 kHz
11.15 MHz 5.575 MHz 4.46 MHz 3.717 MHz 2.788 MHz 2.23 MHz 557 kHz 139 kHz 35.68 kHz
12 MHz 6.0 MHz 4.8 MHz 4.0 MHz 3.0 MHz 2.4 MHz 600 kHz 150 kHz 38.4 kHz
Transmit and Receive (LO1) PLL Sections
The transmit and receive PLLs (Pins 6–9 and 1–4,
respectively) are designed to be part of a 900 MHz system. In
a typical application the T ransmit PLL section will be set up to
generate the transmit frequency, and the Receive PLL
section will be set up to generate the LO1 frequency. The two
sections are identical, and function independently. External
requirements for each include a low–pass filter, a 900 MHz
VCO, and a 64/65 or 128/129 dual modulus prescaler.
The frequency output of the VCO is to be reduced by the
dual modulus prescaler, and then input to the MC33411 (at
Pin 8 or 2). That frequency is then further reduced by the
programmable 13–bit counter (bits 1/19–7 or 2/19–7), and
provided to one side of the Phase Detector, where it is
compared with the PLL reference frequency. The output of
the phase detector (at Pin 6 or 4) is a Three–State charge
pump which drives the VCO through the low–pass filter. Bits
1/20 and 2/20 set the gain of each of the two charge pumps
to either 100/2π µA/radian or 400/2π µA/radian. The polarity
of the two phase detector outputs is set with bits 1/21 and
2/21. If the bit = 0, the appropriate PLL is configured to
operate with a non–inverting low–pass filter/VCO
combination. If the low–pass filter/VCO combination is
inverting, the polarity bit should be set to 1.
The 7–bit A and A’ counters (bits 1/6–0 and 2/6–0) are to
be set to drive the Modulus Control input of the 64/65 or
128/129 dual modulus prescalers. The Modulus Control
outputs (Pins 9 and 1) can be set to either a voltage mode
(logic 1) or a current mode (logic 0) with bit 3/16.
To calculate the settings of the N and A registers, the
following procedure is used:
fVCO
fPLL
+
Nt (Nt must be an integer)
Nt
P
+
N
(1)
(2)
A = Remainder of Equation 2
(decimal part of N x P) (3)
where: fVCO = the VCO frequency
fPLL = the PLL Reference Frequency set within
the MC33411
P = the smaller divisor of the dual modulus
prescaler (64 for a 64/65 prescaler)
N = the whole number portion is the setting for the
N (or N’) counter within the MC33411
A = the setting for the A (or A’) counter within the
MC33411
For example, if the VCO is to provide 910 MHz, and the
internal PLL reference frequency is 50 kHz, then the
equations yield:
Nt
+
910 x 106
50 x 103
+
18,200
N
+
18,200
64
+
284.375
A
+
0.375 x 64
+
24
The N register setting is 284 (0 0001 0001 1100), and the
A register setting is 24 (001 1000).
MC33411A/B
29
MOTOROLA RF/IF DEVICE DATA
2nd LO (LO2)
This PLL is designed to be the 2nd Local Oscillator in a
typical 900 MHz system, and is designed for frequencies up
to 80 MHz. The VCO and varactor diodes are included, and
are to be used with an external tank circuit (Pins 43–45).
Bits 4/20–18 are used to select an internal capacitor, with
a value in the range of 0 to 7.6 pF, to parallel the varactor
diodes and the tank’s external capacitor. This permits a
certain amount of fine tuning of the oscillator’s performance.
See Table 7.
A buffered output is provided to drive, e.g., a mixer. The
frequency is set with the programmable 14–bit counter
(bits 3/13–0) in conjunction with the PLL reference
frequency. For example, if the reference frequency is 50 kHz,
and the 2nd LO frequency is to be 63.3 MHz, the 14–bit
counter needs to be set to 1266d (00 0100 1111 0010). The
output level is dependent on the value of the impedance at
Pin 41, partly determined by the external pull–up resistor.
The output of the phase detector is a Three–State charge
pump which drives the varactor diodes through an external
low–pass filter. Bit 3/14 sets the gain of the charge pump to
either 100/2π µA/radian (logic 0) or 400/2π µA/radian
(logic 1). Bit 3/15 sets its polarity – if 0, the PLL is configured
to operate with a non–inverting low–pass filter/VCO
combination. If the low–pass filter/VCO combination is
inverting, the polarity bit should be set to 1. Please note that
the 2nd LO VCO on the MC33411 is of the non–inverting
type. Figures 43 through 45 describe the response of the 2nd
LO.
ÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁ
ÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁ
Table 7. LO2 Capacitor Select Programming
LO2 Capacitor Select
Bit #20 LO2 Capacitor Select
Bit #19 LO2 Capacitor Select
Bit #18 Select # LO2 Capacitor Select
Value
0 0 0 0 0 pF
0 0 1 1 1.1 pF
0 1 0 2 2.2 pF
0 1 1 3 3.3 pF
1 0 0 4 4.3 pF
1 0 1 5 5.4 pF
1 1 0 6 6.5 pF
1 1 1 7 7.6 pF
MC33411A/B
30 MOTOROLA RF/IF DEVICE DATA
Figure 43. Varicap Capacitance
versus Control Voltage
MINIMUM OVERALL Q
80
0COIL INDUCTANCE (nH)
70
60
50
40
30
20
10
0200 400 600 800 1000 120
0
30 MHz
80 MHz
60 MHz
VCC = 3.6 V
TA = 25°C
Figure 44. Minimum Overall Q
versus Coil Inductance for LO2
LO AMPLITUDE (dBmV)
35
0TANK RESISTANCE (Ω)
VCC = 3.6 V
TA = 25°C
FLO = 63.3 MHz
30
25
20
15
10
5
0500 1000 1500 2000 2500 3000 3500
6.0
16
0
C
APA
C
ITA
NCE
(
p
F)
CONTROL VOLT AGE (V)
15
14
13
12
11
10
9.0
8.0
7.0
123456
VCC = 3.6 V
TA = 25°C
Figure 45. LO2 Amplitude versus Overall Tank
Parallel Resistance
MC33411A/B
31
MOTOROLA RF/IF DEVICE DATA
Loop Filter Characteristics
Let’s consider the following discussion on loop filters. The
fundamental loop characteristics, such as capture range,
loop bandwidth, lock–up time, and transient response are
controlled externally by loop filtering.
Figure 46 is the general model for a Phase Lock Loop
(PLL).
Phase
Detector (Kpd)Filter
(Kf)VCO
(Ko)fo
Divider
(Kn)
fi
Figure 46. PLL Model
Where: Kpd = Phase Detector Gain Constant
Kf = Loop Filter Transfer Function
Ko = VCO Gain Constant
Kn = Divide Ratio (N)
fi = Input frequency
fo = Output frequency
fo/N = Feedback frequency divided by N
From control theory the loop transfer function can be
represented as follows:
A
+
Kpd KfKo
KnOpen loop gain
Kpd can be either expressed as being 200 µA/4π or
800 µA/4π. More details about performance of different type
PLL loops, refer to Motorola application note AN535.
The loop filter can take the form of a simple low pass filter.
A current output, type 2 filter will be used in this discussion
since it has the advantage of improved step response,
velocity, and acceleration.
The type 2 low pass filter discussed here is represented as
follows:
From
Phase
Detector To VCO
R2
C2C1
Figure 47. Loop Filter
with Additional Integrating Element
From Figure 47, capacitor C1 forms an additional
integrator, providing the type 2 response, and filters the
discrete current steps from the phase detector output. The
function of the additional components R2 and C2 is to create
a pole and a zero (together with C1) around the 0 dB point of
the open loop gain. This will create sufficient phase margin
for stable loop operation.
In Figure 48, the open loop gain and the phase is
displayed in the form of a Bode plot. Since there are two
integrating functions in the loop, originating from the loopfilter
and the VCO gain, the open loop gain response follows a
second order slope (–40 dB/dec) creating a phase of –180
degrees at the lower and higher frequencies. The filter
characteristic needs to be determined such that it is adding a
pole and a zero around the 0 dB point to guarantee sufficient
phase margin in this design (Qp in Figure 48).
Phase
Figure 48. Bode Plot of Gain and
Phase in Open Loop Condition
A
,
O
pe
n Loo
p
G
a
in
ω
p
Open Loop Gain
Qp
–180
–90
0
0
The open loop gain including the filter response can be
expressed as:
Aopenloop
+
KpdKo(1
)
j
w
(R2C2))
j
w
Kn
ǒ
j
w
ǒ
1
)
j
w
ǒ
R2C1C2
C1
)
C2
ǓǓǓ
(4)
The two time constants creating the pole and the zero in
the Bode plot can now be defined as:
T1
+
R2C1C2
C1
)
C2 T2
+
R2C2 (5)
By substituting equation (5) into (4), it follows:
Aopenloop
+ǒ
KpdKoT1
w
2C1KnT2
Ǔǒ
1
)
j
w
T2
1
)
j
w
T1
Ǔ
(6)
The phase margin (phase + 180) is thus determined by:
Qp
+
arctan(
w
T2)–arctan(
w
T1)(7)
At ω=ωp, the derivative of the phase margin may be set to
zero in order to assure maximum phase margin occurs at ωp
(see also Figure 48). This provides an expression for ωp:
dQp
d
w
+
0
+
T2
1
)
(
w
T2)2–T1
1
)
(
w
T1)2(8)
w
+
w
p
+
1
T2T1
Ǹ
(9)
Or rewritten:
T1
+
1
w
p2T2 (10)
By substituting into equation (7), solve for T2:
T2
+
tan
ǒ
Qp
2
)
p
4
Ǔ
w
p(11)
MC33411A/B
32 MOTOROLA RF/IF DEVICE DATA
By choosing a value for ωp and Qp, T1 and T2 can be
calculated. The choice of Qp determines the stability of the
loop. In general, choosing a phase margin of 45 degrees is a
good choice to start calculations. Choosing lower phase
margins will provide somewhat faster lock–times, but also
generate higher overshoots on the control line to the VCO.
This will present a less stable system. Larger values of phase
margin provide a more stable system, but also increase
lock–times. The practical range for phase margin is 30
degrees up to 70 degrees.
The selection of ωp is strongly related to the desired
lock–time. Since it is quite complicated to accurately
calculate lock time, a good first order approach is:
T_lock
[
3
w
p(12)
Equation (12) only provides an order of magnitude for lock
time. It does not clearly define what the exact frequency
difference is from the desired frequency and it does not show
the effect of phase margin. It assumes, however, that the
phase detector steps up to the desired control voltage
without hesitation. In practice, such step response approach
is not really valid. If the two input frequencies are not locked,
their phase maybe momentarily zero and force the phase
detector into a high impedance mode. Hence, the lock times
may be found to be somewhat higher.
In general, ωp should be chosen far below the reference
frequency in order for the filter to provide sufficient
attenuation at that frequency. In some applications, the
reference frequency might represent the spacing between
channels. Any feedthrough to the VCO that shows up as a
spur might affect adjacent channel rejection. In theory, with
the loop in lock, there is no signal coming from the phase
detector. But in practice small current pulses and leakage
currents will be supplied to both the VCO and the phase
detector. The external capacitors may show some leakage,
too. Hence, the lower ωp, the better the reference frequency
is filtered, but the longer it takes for the loop to lock.
As shown in Figure 48, the open loop gain at ωp is 1 (or
0 dB), and thus the absolute value of the complex open loop
gain as shown in equation (6) solves C1:
C1
+ǒ
KpdKoT1
w
2KnT2
Ǔǒ
1
)
w
pT2
Ǔ
2
ǒ
1
)
w
pT1
Ǔ
2
Ǹ
(13)
With C1 known, and equation (5) solve C2 and R2:
C2
+
C1
ǒ
T2
T1
*
1
Ǔ
(14)
R2
+
T2
C2 (15)
The VCO gain is dependent on the selection of the
external inductor and the frequency required. The free
running frequency of the VCO is determined by:
f
+
1
2
p
LCT
Ǹ
(16)
In which L represents the external inductor value and CT
represents the total capacitance (including internal
capacitance) in parallel with the inductor. The VCO gain can
be easily calculated via the internal varicap transfer curve
shown in Figure 43.
As can be derived from Figure 43, the varicap capacitance
changes 2.0 pF over the voltage range from 1.0 V to 3.0 V:
D
Cvar
+
2.0 pF
2.0 V (17)
Combining (16) with (17) the VCO gain can be determined
by:
Ko
+
1
j2.0V
ȧ
ȧ
ȥ
ȡ
Ȣ
1
2
p
LCT
Ǹ*
1
2
p
L
ǒ
CT
)
D
Cvar
2
Ǔ
Ǹȧ
ȧ
Ȧ
ȣ
Ȥ
(18)
Although the basic loopfilter previously described provides
adequate performance for most applications, an extra pole
may be added for additional reference frequency filtering.
Given that the channel spacing is based on the reference
frequency, and any feedthrough to the first LO may effect
parameters like adjacent channel rejection and
intermodulation. Figure 49 shows a loopfilter architecture
incorporating an additional pole.
From
Phase
Detector To VCO
R2
C2C1
Figure 49. Loop Filter
with Additional Integrating Element
C3
R3
For the additional pole formed by R3 and C3 to be efficient,
the cut–off frequency must be much lower than the reference
frequency. However, it must also be higher than ωp in order
not to compromise phase margin too much. The following
equations were derived in a similar manner as for the basic
filter previously described.
MC33411A/B
33
MOTOROLA RF/IF DEVICE DATA
Similarly, it can be shown:
Aopenloop
+
–KpdKo
Kn
w
2
ǒ
(C1
)
C2
)
C3)–
w
2C1C2C3R2R3
Ǔ)
1
)
j
w
T2
1
)
j
w
T1 (19)
In which:
T1
+
(C1
)
C2)T2
)
(C1C2)T3
C1
)
C2
)
C3
*
w
2C1T2T3 (20)
T2
+
R2C2 T3
+
R3C3 (22)(21)
From T1 it can be derived that:
C2
+
(T1
)
T2)C3
*
C1
ǒ
T2
)
T3
*
T1
)
w
2T1T2T3
Ǔ
T3
*
T1 (23)
In analogy with (13), by forcing the loopgain to 1 (0 dB) at
ωp, we obtain:
C1(T1
)
T2)
)
C2T3
)
C3T2
+ǒ
KpdKo
Kn
w
p2
Ǔ
1
)ǒ
w
pT2
Ǔ
2
1
)ǒ
w
pT1
Ǔ
2
Ǹ
(24)
Solving for C1:
C1
+
(T2
*
T1)T3C3
*
(T3
*
T1)T2C3
)
(T3
*
T1)
ǒ
KpdKoT1
w
p2Kn
Ǔ
1
)ǒ
w
pT2
Ǔ
2
1
)ǒ
w
pT1
Ǔ
2
Ǹ
(T3
*
T1)T2
)
(T3
*
T1)T3
*ǒ
T2
)
T3
*
T1
)
w
p2T1T2T3
Ǔ
T3 (25)
By selecting ωp via (12), the additional time constant
expressed as T3, can be set to:
T3
+
1
K
w
p(26)
The K–factor shown determines how far the additional
pole frequency will be separated from ωp. Selecting too small
of a K–factor, the equations may provide negative
capacitance or resistor values. Too large of a K–factor may
not provide the maximum attenuation.
By selecting R3 to be 100 kΩ, C3 becomes known and C1
and C2 can be solved from the equations. By using equations
(11) and (10), time constants T2 and T1 can be derived by
selecting a phase margin. Finally , R2 follows from T2 and C2.
A test circuit with the following components and conditions
was constructed with these results:
Loop Filter (See Figure 49):
C1 = 470 pF
R2 = 68 kΩ
C2 = 3.9 nF
R3 = 270 kΩ
C3 = 82 pF
LO2 Tank:
Ctotal = 39.3 pF
Lext = 150 nH, Q = 50 @ 250 MHz
Reference Frequency = 10.24 MHz (unadjusted)
R Counter = 205
LO2 Counter = 1266
AC Load = 25 Ω
Frequency of LO2 = 63.258 MHz
Phase Noise @ 50 kHz offset = –107 dBc
Sidebands @ 50 kHz & 100 kHz offsets = –69 dBc
Low Battery/ RSSI Voltage Measurement
Both the Low Battery (bits 5/23–18) and RSSI (bits
5/17–12) measurement circuits have a 6–bit A/D converter
whose value may be read back via the SPI. The A/D’s sample
their voltages at a frequency equal to the internal SCF clock
frequency divided by 128. The Low Battery Measurement A/D
senses and divides by 2.5 the supply voltage (at Pin 23).
Please note that the minimum Low Battery Detect (LBD)
voltage is 2.7 V, since there is no guarantee that the device will
operate below this value. The RSSI Measurement senses the
voltage at Pin 37.
MC33411A/B
34 MOTOROLA RF/IF DEVICE DATA
These values are compared to the internal reference VB
(≈1.5 V) which is available at Pin 37. The value read back
from the LBD A/D will therefor be approximately:
N(for LBD)
[
63 (VCC)
2.5(VB)(1.07) (27)
and for the RSSI
N(for RSSI)
[
63 (RSSIVoltage)
(VB)(1.07) (28)
VB Voltage Adjust and Characteristics
VB has a production tolerance of ±8%, and can be
adjusted over a ±9% range using bits 3/20–17. The
adjustment steps will be ≈1.2% each (See Table 8). If
desired, VB can be used to bias external circuitry, as long as
the load current on this pin does not exceed 10 µA. VB varies
by less than ±0.5% over supply voltage, referenced to VCC =
3.6 V.
The value of the de–coupling capacitor connected from VB
to ground affects both the noise and crosstalk from the
receive and transmit audio paths, so the value should be
chosen with caution. Figures 50 and 51 show this
relationship.
ÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁ
Á
ÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁ
Á
Table 8. VB Voltage Reference Programming
Vref
Adjust Bit #20 Vref
Adjust Bit #19 Vref
Adjust Bit #18 Vref
Adjust Bit #17 Vref
Adjust # Voltage Reference
Adjustment Amount
0 0 0 0 0 –9.0%
0 0 0 1 1 –7.8%
0 0 1 0 2 –6.6%
0 0 1 1 3 –5.4%
0 1 0 0 4 –4.2%
0 1 0 1 5 –3.0%
0 1 1 0 6 –1.8%
0 1 1 1 7 –0.6%
1 0 0 0 8 0.6%
1 0 0 1 9 1.8%
1 0 1 0 10 3.0%
1 0 1 1 11 4.2%
1 1 0 0 12 5.4%
1 1 0 1 13 6.6%
1 1 1 0 14 7.8%
1 1 1 1 15 9.0%
0.01
–125
–105
0.01
CROSSTALK (dB)
VB CAPACITOR (µF)
–110
–115
–120
0.1 1.0 10
–50
VB CAPACITOR (µF)
Noise
Figure 50. Crosstalk/Noise from
C In to E Out versus VB Capacitor Figure 51. Crosstalk/Noise from
E In to Tx Out versus VB Capacitor
–107
–87
–92
–97
–102
NOISE LEVEL @ E OUT (dBV)
Crosstalk, 130 Ω load
Crosstalk, no load
0.1 1.0 10
CROSSTALK (dB)
–55
–60
–65
–70
–75
–80
–85
–90
–95 –75
–63
–67
–71
–73
–69
–65
–61
NOISE LEVEL @ Tx OUT (dBV)
Noise
Crosstalk
VCC = 3.6 V
TA = 25°CVCC = 3.6 V
TA = 25°C
MC33411A/B
35
MOTOROLA RF/IF DEVICE DATA
MCU Serial Interface
The MCU Serial Interface is a 3–wire interface, consisting
of a Clock line, an Enable line, and a bi–directional Data line.
The interface is always active, i.e., it cannot be powered
down as all other sections of the MC33411 are disabled and
enabled through this interface.
After the device power–up (or whenever a reset condition
is required), the MCU should perform the following steps:
1. Initialize the Data line to a high impedance state.
2. Initialize the Clock line to a logic low.
3. Initialize the Enable line to a logic low.
4. Pulse the Clock line a minimum of once (RZ format)
while leaving the Enable line continuously low. This
places the SPI port into a known condition.
5. Load all registers with their desired initial values.
The clock (Return–to–Zero format) must be supplied to the
MC33411 at Pin 11 to write or read data, and can be any
frequency up to 2.0 MHz. The clock need not be present
when data is not being transferred. The Enable line must be
low when data is not being transferred.
Internally there are 7 data registers, 24–bits each, addressed
with 4–bits ranging from $h1 to $h7 (see Tables 9 and 10).
Register 5, bits 23–12 are read–only bits, while all other register
bits are Read/Write. All unused/unimplemented bits are
reserved for Motorola use only. The contents of the 7 registers
can be read out at any time. All bits are written in, or read out,
on the clock’s positive transition. The write and read operations
are as follows:
Figure 52. Writing Data to the MC33411
Clock
Data
Enable
123 24
4–Bit Address 24–Bit Data from MCU
MSB LSB
Latch Address Latch Data
a. Write Operation:
– To write data to the MC3341 1, the following sequence is
required (see Figure 52):
6. The Enable line is taken high.
7. Five bits are entered:
– The first bit must be a 0 to indicate a Write operation.
– The next four bits identify the register address
(0001–0111). The MSB is entered first.
8. The Enable line is taken low . At this transition, the address
is latched in and decoded.
9. The Enable line is maintained low while the data bits are
clocked in. The MSB is entered first, and the LSB last. If
24–bits are written to a register which has less than 24 active
bits (e.g., register 6), the unassigned bits are to be 0.
10. After the last bit is entered, the Enable line is to be taken
high and then low. The falling edge of this pulse latches in
the just entered data. The clock line must be at a logic low
and must not transition in either direction during this Enable
pulse.
11.The Enable line must then be kept low until the next
communication.
Note: If less than 24 bits are to be written to a data register ,
it is not necessary to enter the full 24 bits, as long as they are
all lower order bits. For example, if bits 0–6 of a register are to
be updated, they can be entered as 7 bits with 7 clock cycles
in step 4 above. However , if this procedure is used, a minimum
of 4 bits, with 4 clock pulses, must be entered.
MC33411A/B
36 MOTOROLA RF/IF DEVICE DATA
Figure 53. Reading Data from the MC33411
Clock
Data
Enable
123 24
Sets Data Pin
to Output
4–Bit Address 24–Bit Data from MC33411
MSB LSB
Latch Address and Load
Data into Shift Register
Sets Data Pin
to Input
b. Read Operation:
– To read the output bits (bits 5/23–12), or the contents of
any register, the following sequence is required (see
Figure 53):
1. The Enable line is taken high.
2. Five bits are entered:
– The first bit must be a 1 to indicate a Read operation.
– The next four bits identify the register address
(0001–0111). The MSB is entered first.
3. The Enable line is taken low . At this transition, the address
is latched in and decoded, and the contents of the selected
register is loaded into the 24–bit output shift register. At this
point, the Data line (Pin 12) is still an input.
4. While maintaining the Enable line low , the data is read out.
The first clock rising edge will change the Data line to an
output, and the MSB will be present on this line.
5. The full contents of the register are then read out (MSB first,
LSB last) with a total of 24 clock rising edges, including the
one in step 4 above. It is recommended that the MCU read
the bits after the clock’s falling edge.
6. After the last clock pulse, the Enable line is to be taken high
and then low. The falling edge of this pulse returns the Data
Pin to be an input. The clock line must be at a logic low and
must not transition in either direction during this Enable
pulse.
7. The Enable line must then be kept low until the next
communication.
Power Supply/Power Saving Modes
The power supply voltage, applied to all VCC pins, can
range from 2.7 to 5.5 V. All VCC pins must be within ±0.5 V of
each other, and each must be bypassed. It is recommended
a ground plane be used, and all leads to the MC33411 be as
short and direct as possible. To reduce the possibility of
device latch–up, it is highly recommended that the Audio,
Synthesizer and RF VCC portions of the chip be isolated from
the main supply through 10 to 25 Ω resistors (see the
Evaluation PCB Schematic, Figure 54). This also provides
RF–to–Audio noise isolation. The supply and ground pins are
distributed as follows:
1. Pin 23 provides power to the audio section. Pin 40 is the
ground pin.
2. Pin 28 provides power to the speaker amplifier section.
Pin 31 is the ground pin.
3. Pin 3 provides power to the Rx PLL section. Pin 5 is the
ground pin.
4. Pin 7 provides power to the Tx PLL section, and the MCU
interface. Pin 5 is the ground pin.
5. Pin 42 provides power to the 2nd LO section. Pins 46 and 48
are the ground pins.
6. Pin 14 is the ground pin for the digital circuitry. Power for the
digital circuitry is derived from Pin 23.
To conserve power, various sections can be individually
disabled by using bits 5/7–0 and 6/7 (setting a bit to 1
disables the section).
1. Reference Oscillator Disable (bit 5/0) – The reference
oscillator at Pins 15 and 16 is disabled, thereby denying a
clock to the three PLLs and the switched capacitor filters.
This function is not available on the “B” version.
2. Tx PLL Disable (bit 5/1) – The 13–bit and 7–bit counters,
input buffer, phase detector, and modulus control blocks
are disabled. The charge pump output at Pin 6 will be in a
Hi–Z state.
3. Rx PLL Disable (bit 5/2) – The 13–bit and 7–bit counters,
input buffer, phase detector, and modulus control blocks
are disabled. The charge pump output at Pin 4 will be in a
Hi–Z state.
4. LO2 PLL Disable (bit 5/3) – The VCO, 14–bit counter,
output buffer , and phase detector are disabled. The charge
pump output at Pin 47 will be in a Hi–Z state.
5. Power Amplifier Disable (bit 5/4) – The two speaker
amplifiers are disabled. Their outputs will go to a high
impedance state.
6. Rx Audio Path Disable (bit 5/5) – The anti–aliasing filter,
low–pass filter, and variable gain stage are disabled.
7. Tx Audio Path Disable (bit 5/6) – Disables the microphone
amplifier and low–pass filter.
8. Low Battery/RSSI Measurement Disable (bit 5/7) – Both
6–bit A/Ds are disabled.
9. Data Slicer Disable (bit 5/8) – The data slicer is disabled
and DS Out goes to high impedance.
10. MCU Clock Disable (bit 6/7) – The MCU clock counter
is disabled and the MCU Clock Output will be in a Hi–Z
state. This function is not available on the “B” version.
Note: The 12–bit reference counter is disabled if the three
PLLs are disabled (bits 5/1–3 = 1).
MC33411A/B
37
MOTOROLA RF/IF DEVICE DATA
Table 9. Register
Map
Table 10. Register
Map: Power–Up
Defaults
0111 7 Volume Control Tx Gain Adjust Rx Gain Adjust
RSSI &
Batt. A/D
Disable
0001
0010
0011
0100
0101
0110
0111
Reg
Add Reg
Num MSB
Bit 23 LSB
Bit 0
Bit 22 Bit 21 Bit 20 Bit 19 Bit 18 Bit 17 Bit 16 Bit 15 Bit 14 Bit 13 Bit 12 Bit 11 Bit 10 Bit 9 Bit 8 Bit 7 Bit 6 Bit 5 Bit 4 Bit 3 Bit 2 Bit 1
1
2
3
4
5
6
7
Tx
Polarity
Select
Rx
Polarity
Select
Tx PD
Cur Sel
Rx PD
Cur Sel
MSB
MSB
LSB
LSB
LSB
LSB
13–Bit Tx N Counter Divide Value
13–Bit Rx N’ Counter Divide Value
MSB
MSB
VB V oltage Reference Adjust FTxMC/
FRxMC
Mode
LO2
Polarity
Select
2nd LO
PD Cur
Sel LSB14–Bit 2nd LO Counter Divide ValueMSB
Test Modes LO2 Capacitor Select 6–Bit Switched Capacitor Filter Counter Divide Value MSB LSB12–Bit Reference Counter Divide Value
6–Bit Battery V oltage A/D Output 6–Bit RSSI A/D Output
MCU Clock Divide Select V olume Control Tx Gain Adjust Rx Gain Adjust
Side Tone
Attenuate Select
Unused Register
Bits Data
Slicer
Invert
Data
Slicer
Disable Tx Audio
Disable Rx Audio
Disable Power
Amp
Disable
2nd LO
PLL
Disable Rx PLL
Disable Tx PLL
Disable Ref Osc
Disable*
ALC Gain
= 25 ALC Gain
= 10 Comp.
Low Max.
Gain En. MCU Clk
Disable* ALC
Disable Limiter
Disable Compres–
ser Pass–
through
Expander
Pass–
through Tx Mute Rx Mute Power
Amp
Mute
7–Bit Tx A Counter Divide Value
7–Bit Rx A’ Counter Divide Value
RSSI &
Batt. A/D
Disable
0001
0010
0011
0100
0101
0110
Reg
Add Reg
Num MSB
Bit 23 LSB
Bit 0
Bit 22 Bit 21 Bit 20 Bit 19 Bit 18 Bit 17 Bit 16 Bit 15 Bit 14 Bit 13 Bit 12 Bit 11 Bit 10 Bit 9 Bit 8 Bit 7 Bit 6 Bit 5 Bit 4 Bit 3 Bit 2 Bit 1
1
2
3
4
5
6
Tx
Polarity
Select
Rx
Polarity
Select
Tx PD
Cur Sel
Rx PD
Cur Sel
MSB
MSB
LSB
LSB
LSB
LSB
13–Bit Tx N Counter Divide Value
13–Bit Rx N’ Counter Divide Value
MSB
MSB
VB V oltage Reference Adjust FTxMC/
FRxMC
Mode
LO2
Polarity
Select
2nd LO
PD Cur
Sel LSB14–Bit 2nd LO Counter Divide ValueMSB
Test Modes LO2 Capacitor Select 6–Bit Switched Capacitor Filter Counter Divide Value MSB LSB12–Bit Reference Counter Divide Value
6–Bit Battery V oltage A/D Output 6–Bit RSSI A/D Output
Side Tone
Attenuate Select
Unused Register
Bits Data
Slicer
Invert
Data
Slicer
Disable Tx Audio
Disable Rx Audio
Disable Power
Amp
Disable
2nd LO
PLL
Disable Rx PLL
Disable Tx PLL
Disable Ref Osc
Disable*
ALC Gain
= 25 ALC Gain
= 10 Comp.
Low Max.
Gain En. MCU Clk
Disable* ALC
Disable Limiter
Disable Compres–
ser Pass–
through
Expander
Pass–
through Tx Mute Rx Mute Power
Amp
Mute
7–Bit Tx A Counter Divide Value
7–Bit Rx A’ Counter Divide Value
0010000000000001000000
0010000000000001000000
01110 00100000000 00000
0000100000100000000000
000000000000
0000000000000
01101110111101111
00
Table 9. Register Map
Table 10. Register Map: Power–Up Defaults
* These bits not included in ”B” version.
* These bits not included in ”B” version.
MCU Clock Divide Select
MC33411A/B
38 MOTOROLA RF/IF DEVICE DATA
Figure 54. MC33411A/B Evaluation PCB Schematic
Figure 54. MC33411A/B Evaluation PCB Schematic
0.01
Á
Á
Á
Á
ÁÁ
Á
Á
ÁÁ
Á
Á
Á
ÁÁ
Á
Á
ÁÁ
Á
Á
ÁÁ
Á
Á
VCCA
VCCR
VCCL
PA In
E In
LO2 Ctl
LO2 Out
AUD In
JP3
H5X2
PA Out+
PA Out–
Tx AUD
C In
Lim In
VCCD
Gnd
TP7
TP6
F In
VCCD
R
x
O
u
t
RSSI In
E
I
n
E
c
a
p
E
O
u
t
P
A
IG
n
d
P
A
P
A
O
–
P
A
O
+
V
C
C
P
A
V
BV
A
GM
C
I
F
R
x
M
CF
R
x
P
L
L
V
C
C
R
x
P
D
P
L
L
G
n
d
T
x
P
D
P
L
L
V
C
CF
T
x
F
T
x
M
CE
NC
L
K
D
a
t
a
Rx Audio In
DS In
Gnd Audio
LO2 Out
LO2 VCC
LO2+
LO2 Ctl
LO2–
LO2 Gnd
LO2 PD
LO2 Gnd
Mic Amp
VCC Audio
C In
Ccap
C Out
Lim In
Tx Out
DS Out
MCU Clk Out
Gnd Digital
Fref Out
Fref In
37
38
39
40
41
42
43
44
45
46
47
48
24
23
22
21
20
19
18
17
16
15
14
13
3
63
53
43
33
23
13
02
92
82
72
62
5
123456789 1
01
11
21
2
3
4
5
6
7
8
9
10
1
2
3
4
5
6
7
8
9
10
1
2
3
4
5
6
7
8
9
10
Det In
RSSI
RX EN
Rx PD
Rx MC
FRx
JP1
JP2
H5X2
H5X2
FTx
Tx MC
Tx PD
Tx EN
Tx Out
Tx DAT
Tx DAT
Tx EN
Rx EN
EN
CLK
Data
CK Out
DS Out
R6
47.5 k
J27 N/O
J25 N/C
J26 N/C
R5
47.5 k
C13 220 p
R7
130
J8 N/O
C12 1.0
C10 1.0
VCCA
J6 N/C
VCCA C38 4.7
0.1
C39 R19
U/D U/D
R20
VCCA
1.0
C1
R1 47.5 k
J23
N/C J24
N/O
C2
220 p
R2
47.5 k
J2 N/C
J3 N/C
C3
C4
C5
1.0
1.0
0.47
J11 N/C
J12 N/C
J13 N/O Y1
10.24 M
C15 15 p
C16 15 p
R8 49.9
C17
0.01
C30
10
C31
0.01
D1
C32
10
C34
10
C36
10
C33
0.01
C35
0.01
C37
0.01
J5 N/O
R3
U/D C7
U/D R4
U/D
C8 U/D
C14
C6
C9
C40
1.0
1.0
0.01
VCCL
VCCL
R18
49.9
L1
U/D
C21
U/D
R10 U/D
R9 U/D
C19 U/D
C18 U/D
C20 U/D J15 N/C
VCCR
C26 U/D
C27 U/D
C28 U/D
R13 U/D
R14 U/D R12 U/D
R11 U/D
C22 U/D
C23 U/D
C24 U/D
C25
0.01
C29
0.01
VCCA
J7 N/C
C12
1.0
R15 10
R16 10
R17 10
1N4001
J14
TP2
TP1
J1
J10
J9
J17
J18
TP4
TP3
J4
J16
TP5
U1
MC33411
MC33411A/B
39
MOTOROLA RF/IF DEVICE DATA
Figure 55. MC33411A/B Evaluation PCB Component Side
C1,C3,C5,C6,C9,C10,C12 1.0
C13,C2 220 p
C4,C11 0.47
L1,R3,R4,C7,C8,R9,R10, User defined
R11,R12,R13,R14,C18,R19,
C19,R20,C20,C21,C22,C23,
C24,C26,C27,C28
C14,C17,C25,C29,C31,C33, 0.01
C35,C37,C40
C15,C16 15 p
R15,R16,R17,C30,C32,C34, 10
C36
C38 4.7
C39 0.1
D1 1N4001
H1,H2,H3,H4 None
JP1,JP2,JP3 H5X2
J1 Tx Aud
J2,J3,J6,J7,J11,J12,J15, N.C.
J23,J25,J26
J4 Aud In
J5,J8,J13,J24,J27 N/O
J9 PAOUT+
J10 PAOUT–
J14 F In
J16 LO2 Out
J17,TP6 VCCD
J18,TP7 Gnd
J19,J20,J21,J22 TP
R1,R2,R5,R6 47.5 k
R7 130
R8,R18 49.9
TP1 C In
TP2 Lim In
TP3 E In
TP4 PA In
TP5 LO2 Ctl
U1 MC33411
Y1 10.24 M
4.5″
4.5″
MC33411A/B
40 MOTOROLA RF/IF DEVICE DATA
Figure 56. MC33411A/B Evaluation PCB Solder Side
4.5″
4.5″
MC33411A/B
41
MOTOROLA RF/IF DEVICE DATA
FTA SUFFIX
PLASTIC PACKAGE
CASE 932–02
(LQFP–48)
ISSUE D
OUTLINE DIMENSIONS
ÇÇÇÇ
ÇÇÇÇ
ÇÇÇÇ
ÉÉÉ
ÉÉÉ
ÉÉÉ
A
A1
–T–
Z
0.200 (0.008) AB T–U
–U–
4X
Z0.200 (0.008) AC T–U
4X
B
B1
1
12
13 24
25
36
37
48
–Z–
S1
S
V
V1
P
AE AE
–T–, –U–, –Z–
DETAIL Y
DETAIL Y
BASE METAL
NJ
F
D
S
T–U
M
0.080 (0.003) Z S
AC
SECTION AE–AE
–AB–
–AC– AD
G0.080 (0.003) AC
M
_
TOP & BOTTOM
Q
_
W
K
X
E
C
H
0.250 (0.010)
GAUGE PLANE
R
9
DETAIL AD
DIM
AMIN MAX MIN MAX
INCHES
7.000 BSC 0.276 BSC
MILLIMETERS
A1 3.500 BSC 0.138 BSC
B7.000 BSC 0.276 BSC
B1 3.500 BSC 0.138 BSC
C1.400 1.600 0.055 0.063
D0.170 0.270 0.007 0.011
E1.350 1.450 0.053 0.057
F0.170 0.230 0.007 0.009
G0.500 BASIC 0.020 BASIC
H0.050 0.150 0.002 0.006
J0.090 0.200 0.004 0.008
K0.500 0.700 0.020 0.028
M12 REF 12 REF
N0.090 0.160 0.004 0.006
P0.250 BASIC 0.010 BASIC
Q1 5 1 5
R0.150 0.250 0.006 0.010
S9.000 BSC 0.354 BSC
S1 4.500 BSC 0.177 BSC
V9.000 BSC 0.354 BSC
V1 4.500 BSC 0.177 BSC
W0.200 REF 0.008 REF
X1.000 REF 0.039 REF
NOTES:
1 DIMENSIONING AND TOLERANCING PER ANSI
Y14.5M, 1982.
2 CONTROLLING DIMENSION: MILLIMETER.
3 DATUM PLANE –AB– IS LOCATED AT BOTTOM OF
LEAD AND IS COINCIDENT WITH THE LEAD
WHERE THE LEAD EXITS THE PLASTIC BODY AT
THE BOTTOM OF THE PARTING LINE.
4 DATUMS –T–, –U–, AND –Z– TO BE DETERMINED
AT DATUM PLANE –AB–.
5 DIMENSIONS S AND V TO BE DETERMINED AT
SEATING PLANE –AC–.
6 DIMENSIONS A AND B DO NOT INCLUDE MOLD
PROTRUSION. ALLOWABLE PROTRUSION IS
0.250 (0.010) PER SIDE. DIMENSIONS A AND B DO
INCLUDE MOLD MISMATCH AND ARE
DETERMINED AT DATUM PLANE –AB–.
7 DIMENSION D DOES NOT INCLUDE DAMBAR
PROTRUSION. DAMBAR PROTRUSION SHALL
NOT CAUSE THE D DIMENSION TO EXCEED
0.350 (0.014).
8 MINIMUM SOLDER PLATE THICKNESS SHALL BE
0.0076 (0.0003).
9 EXACT SHAPE OF EACH CORNER IS OPTIONAL.
__
____
MC33411A/B
44 MOTOROLA RF/IF DEVICE DATA
Motorola reserves the right to make changes without further notice to any products herein. Motorola makes no warranty, representation or guarantee regarding
the suitability of its products for any particular purpose, nor does Motorola assume any liability arising out of the application or use of any product or circuit, and
specifically disclaims any and all liability, including without limitation consequential or incidental damages. “Typical” parameters which may be provided in Motorola
data sheets and/or specifications can and do vary in different applications and actual performance may vary over time. All operating parameters, including “Typicals”
must be validated for each customer application by customer’s technical experts. Motorola does not convey any license under its patent rights nor the rights of
others. Motorola products are not designed, intended, or authorized for use as components in systems intended for surgical implant into the body, or other
applications intended to support or sustain life, or for any other application in which the failure of the Motorola product could create a situation where personal injury
or death may occur. Should Buyer purchase or use Motorola products for any such unintended or unauthorized application, Buyer shall indemnify and hold Motorola
and its officers, employees, subsidiaries, affiliates, and distributors harmless against all claims, costs, damages, and expenses, and reasonable attorney fees
arising out of, directly or indirectly, any claim of personal injury or death associated with such unintended or unauthorized use, even if such claim alleges that
Motorola was negligent regarding the design or manufacture of the part. Motorola and are registered trademarks of Motorola, Inc. Motorola, Inc. is an Equal
Opportunity/Af firmative Action Employer.
Mfax is a trademark of Motorola, Inc.
How to reach us:
USA/EUROPE/Locations Not Listed: Motorola Literature Distribution; JAPAN: Nippon Motorola Ltd.; SPD, Strategic Planning Office, 141,
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MC33411A/D
◊
