© Semiconductor Components Industries, LLC, 2013
November, 2018 − Rev. 16
1Publication Order Number:
NCV4274/D
NCV4274, NCV4274A
Regulator Family,
400 mA, 2% and 4% Voltage
Description
The NCV4274 and NCV4274A is a precision micro−power voltage
regulator with an output current capability of 400 mA available in the
DPAK, D2PAK and SOT−223 packages.
The output voltage is accurate within ±2.0% or ±4.0% depending on
the version with a maximum dropout voltage of 0.5 V with an input up
to 40 V. Low quiescent current is a feature drawing only 150 mA with a
1 mA load. This part is ideal for automotive and all battery operated
microprocessor equipment.
The regulator is protected against reverse battery, short circuit, and
thermal overload conditions. The device can withstand load dump
transients making it suitable for use in automotive environments.
Features
•2.5, 3.3 V, 5.0 V, 8.5 V, ±2.0% Output Options
•2.5, 3.3 V, 5.0 V, ±4.0% Output Options
•Low 150 mA Quiescent Current at 1 mA load current
•400 mA Output Current Capability
•Fault Protection
•+60 V Peak Transient Voltage with Respect to GND
S −42 V Reverse Voltage
S Short Circuit
S Thermal Overload
•Very Low Dropout Voltage
•NCV Prefix for Automotive and Other Applications Requiring
Unique Site and Control Change Requirements; AEC−Q100
Qualified and PPAP Capable
•These are Pb−Free Devices
MARKING DIAGRAMS
DPAK
DT SUFFIX
CASE 369C
D2PAK
DS SUFFIX
CASE 418AF
See detailed ordering and shipping information in the package
dimensions section on page 15 of this data sheet.
ORDERING INFORMATION
www.onsemi.com
74X−xxG
ALYWW
x
X = A or blank
xx = Voltage Ratings
A = Assembly Location
L, WL = Wafer Lot
Y = Year
WW, W = Work Week
G, G= Pb−Free Package
4
1
2
3
4
123
1 Input
2, 4 Ground
3 Output
1 Input
2, 4 Ground
3 Output
SOT−223
ST SUFFIX
CASE 318E 1
AYW
74X−xxG
G
1 Input
2, 4 Ground
3 Output
23
4
NC
V4274X−xx
AWLYWWG
(Note: Microdot may be in either location)
NCV4274, NCV4274A
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2
Figure 1. Block Diagram
−
+
Bandgap
Refernece
Thermal
Shutdown
Current Limit and
Saturation Sense
GND
QI
Pin Definitions and Functions
Pin No. Symbol Function
1 I Input; Bypass directly at the IC a ceramic capacitor to GND.
2,4 GND Ground
3 Q Output; Bypass with a capacitor to GND.
1. DPAK 3LD package code 6025
2. D2PAK 3LD package code 6083
ABSOLUTE MAXIMUM RATINGS
Pin Symbol, Parameter Symbol Condition Min Max Unit
I, Input−to−Regulator Voltage VI−42 45 V
Current IIInternally
Limited
Internally
Limited
I, Input peak Transient Voltage to Regulator with Respect
to GND
VI60 V
Q, Regulated Output Voltage VQVQ = VI−1.0 40 V
Current IQInternally
Limited
Internally
Limited
GND, Ground Current IGND −100 mA
Junction Temperature
Storage Temperature
TJ
TStg
−
−50
150
150
°C
°C
ESD Capability, Human Body Model ESDHB 4 kV
ESD Capability, Machine Model ESDMM 200 V
ESD Capability, Charged Device Model ESDCDM 1 kV
Stresses exceeding those listed in the Maximum Ratings table may damage the device. If any of these limits are exceeded, device functionality
should not be assumed, damage may occur and reliability may be affected.
3. This device series incorporates ESD protection and is tested by the following methods:
ESD HBM tested per AEC−Q100−002 (EIA/JESD22−A114)
ESD MM tested per AEC−Q100−003 (EIA/JESD22−A115)
ESD CDM tested per EIA/JES D22/C101, Field Induced Charge Model
NCV4274, NCV4274A
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3
OPERATING RANGE
Parameter Symbol Condition Min Max Unit
Input Voltage (8.5 V Version) VI9.0 40 V
Input Voltage (5.0 V Version) VI5.5 40 V
Input Voltage (3.3 V, and 2.5 V Version) VI4.5 40 V
Junction Temperature TJ−40 150 °C
THERMAL RESISTANCE
Parameter Symbol Condition Min Max Unit
Junction−to−Ambient DPAK Rthja −70
(Note 4)
°C/W
Junction−to−Ambient D2PAK Rthja −60
(Note 4)
°C/W
Junction−to−Case DPAK Rthjc −4°C/W
Junction−to−Case D2PAK Rthjc −3°C/W
Junction−to−Tab SOT−223 Y−JLX,
YLX
−14.5
(Note 5)
°C/W
Junction−to−Ambient SOT−223 RqJA, qJA −169.7
(Note 5)
°C/W
4. Soldered in, minimal footprint, FR4
5. 1 oz copper, 5 mm2 copper area, FR4
LEAD FREE SOLDERING TEMPERATURE AND MSL
Parameter Symbol Condition Min Max Unit
Lead Free Soldering, (Note 6)
Reflow (SMD styles only), Pb−Free
Tsld 60s − 150s Above 217s
40s Max at Peak −265 pk
°C
Moisture Sensitivity Level MSL DPAK and D2PAK
SOT−223
1
3
−
−
6. Per IPC/JEDEC J−STD−020C
NCV4274, NCV4274A
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4
ELECTRICAL CHARACTERISTICS
−40°C < TJ < 150°C; VI = 13.5 V unless otherwise noted.
Parameter Symbol Test Conditions
Min Typ Max Min Typ Max
Unit
NCV4274A NCV4274
REGULATOR
Output Voltage (8.5 V Version) VQ5 mA < IQ < 200 mA
9.5 V < VI < 40 V
8.33 8.5 8.67 − − − V
Output Voltage (8.5 V Version) VQ5 mA < IQ < 400 mA
9.5 V < VI < 28 V
8.33 8.5 8.67 − − − V
Output Voltage (5.0 V Version) VQ5 mA < IQ < 400 mA
6 V < VI < 28 V
4.9 5.0 5.1 4.8 5.0 5.2 V
Output Voltage (5.0 V Version) VQ5 mA < IQ < 200 mA
6 V < VI < 40 V
4.9 5.0 5.1 4.8 5.0 5.2 V
Output Voltage (3.3 V Version) VQ5 mA < IQ < 400 mA
4.5 V < VI < 28 V
3.23 3.3 3.37 3.17 3.3 3.43 V
Output Voltage (3.3 V Version) VQ5 mA < IQ < 200 mA
4.5 V < VI < 40 V
3.23 3.3 3.37 3.17 3.3 3.43 V
Output Voltage (2.5 V Version) VQ5 mA < IQ < 400 mA
4.5 V < VI < 28 V
2.45 2.5 2.55 2.4 2.5 2.6 V
Output Voltage (2.5 V Version) VQ5 mA < IQ < 200 mA
4.5 V < VI < 40 V
2.45 2.5 2.55 2.4 2.5 2.6 V
Current Limit IQ−400 600 −400 600 −mA
Quiescent Current IqIQ = 1 mA
VQ = 8.5 V
VQ = 5.0 V
VQ = 3.3 V
VQ = 2.5 V
IQ = 250 mA
VQ = 8.5 V
VQ = 5.0 V
VQ = 3.3 V
VQ = 2.5 V
IQ = 400 mA
VQ = 8.5 V
VQ = 5.0 V
VQ = 3.3 V
VQ = 2.5 V
−
−
−
−
−
−
−
−
−
−
−
−
195
190
145
140
10
10
13
12
20
20
30
28
250
250
250
250
15
15
20
20
35
35
45
45
−
−
−
−
−
−
−
−
−
−
−
−
−
190
145
140
−
10
13
12
−
20
30
28
−
250
250
250
−
15
20
20
−
35
45
45
mA
mA
mA
mA
mA
mA
mA
mA
mA
mA
mA
mA
Dropout Voltage
8.5 V Version
5.0 V Version
3.3 V Version
2.5 V Version
VDR IQ = 250 mA,
VDR = VI − VQ
VI = 8.5 V
VI = 5.0 V
VI = 4.5 V
VI = 4.5 V
−
−
−
−
250
250
−
−
500
500
1.27
2.05
−
−
−
−
−
250
−
−
−
500
1.33
2.1
mV
mV
V
V
Load Regulation DVQIQ = 5 mA to 400 mA −7 20 −7 30 mV
Line Regulation DVQDVI = 12 V to 32 V
IQ = 5 mA
−10 25 −10 25 mV
Power Supply Ripple Rejection PSRR ƒr = 100 Hz,
Vr = 0.5 VPP
−60 − − 60 −dB
Temperature output voltage drift DVQ/DT−0.5 − − 0.5 −mV/K
Thermal Shutdown Temperature* TSD IQ = 5 mA 165 −210 165 −210 °C
*Guaranteed by design, not tested in production
NCV4274, NCV4274A
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5
Figure 2. Measuring Circuit
NCV4274
NCV4274A
Rload
VQ
CQ
10 mF
or
22 mF
C12
100 nF
C11
1.0 mF
VQ
IQ
QIII
VI
VI
IGND
GND
13
2,4
Figure 3. Application Circuit
Output
CQ*CI
100 nF
GND
NCV4274
NCV4274A
13
2,4
Input
VQ
VI
*CQ = 10 mF for VQ ≤ 3.3 V
CQ = 22 mF for VQ ≥ 5 V
TYPICAL CHARACTERISTIC CURVES
Figure 4. ESR Characterization − 3.3 V, 5 V and
8.5 V Versions
0.01
0.1
1
10
100
0 50 100 150 200 250
ESR (W)
LOAD CURRENT (mA)
Maximum ESR
COUT = 10 mF − 100 mF
300 350 400
Stable Region
VI = 13.5 V
Figure 5. ESR Characterization − 2.5 V Version
0.1
1.0
10
100
1000
0 5 20 60 100 140
ESR (W)
LOAD CURRENT (mA)
Maximum ESR
COUT = 1 mF − 100 mF
180 220 260 300 340 380 42
0
Minimum ESR
COUT = 1 mF
Stable Region
VI = 13.5 V
NCV4274, NCV4274A
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6
TYPICAL CHARACTERISTIC CURVES − 8.5 V Version
8.3
8.4
8.5
8.6
8.7
−40 0 40 80 120 160
VQ (V)
TJ (°C)
0
1
2
3
4
5
6
02 46 810
RL = 33 W
TJ = 25°C
VI = 13.5 V
RL = 1.7 kW
VQ (V)
VI (V)
Figure 6. Output Voltage vs. Junction Temperature
0
200
400
600
1000
0 1020304050
IQ (mA)
VI (V)
Figure 7. Output Voltage vs. Input Voltage
TJ = 25°C
VQ = 0 V
0
5
10
15
20
25
35
0 100 200 300 400 50
0
Iq (mA)
IQ (mA)
Figure 8. Output Current vs. Input Voltage
TJ = 25°C
VI = 13.5 V
0
0.2
0.4
0.6
0.8
1
1.2
1.4
1.6
0102030405060
Iq (mA)
IQ (mA)
TJ = 25°C
VI = 13.5 V
Figure 9. Current Consumption vs. Output
Current (High Load)
Figure 10. Current Consumption vs. Output
Current (Low Load)
Figure 11. Drop Voltage vs. Output Current
0
100
200
300
400
500
600
0 100 200 300 400
VDR (mV)
IQ (mA)
TJ = 25°C
TJ = 125°C
7
8
9
10
800
30
VI = 13.5 V
NCV4274, NCV4274A
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8
TYPICAL CHARACTERISTIC CURVES − 5.0 V Version
4.8
4.9
5.0
5.1
5.2
−40 0 40 80 120 160
VQ (V)
TJ (°C)
0
1
2
3
4
5
6
02 46 810
RL = 20 W
TJ = 25°C
VI = 13.5 V
RL = 1 kW
VQ (V)
VI (V)
Figure 14. Output Voltage vs. Junction
Temperature
0
200
400
600
800
0 1020304050
IQ (mA)
VI (V)
Figure 15. Output Voltage vs. Input Voltage
TJ = 25°C
VQ = 0 V
0
10
20
30
40
50
60
0 100 200 300 400 500 600
Iq (mA)
IQ (mA)
Figure 16. Output Current vs. Input Voltage
TJ = 25°C
VI = 13.5 V
0
0.2
0.4
0.6
0.8
1
1.2
1.4
1.6
0102030405060
Iq (mA)
IQ (mA)
TJ = 25°C
VI = 13.5 V
Figure 17. Current Consumption vs. Output
Current (High Load)
Figure 18. Current Consumption vs. Output
Current (Low Load)
Figure 19. Drop Voltage vs. Output Current
0
100
200
300
400
500
600
0 100 200 300 40
0
VDR (mV)
IQ (mA)
TJ = 25°C
TJ = 125°C
NCV4274, NCV4274A
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10
TYPICAL CHARACTERISTIC CURVES − 3.3 V Version
2.9
3.0
3.1
3.4
3.5
−40 0 40 80 120 160
VQ (V)
TJ (°C)
0
1
2
3
4
5
6
01 34 5 6
RL = 20 W
TJ = 25°C
VI = 6 V
RL = 1 kW
VQ (V)
VI (V)
Figure 22. Output Voltage vs. Junction
Temperature
0
200
400
600
800
0 1020304050
IQ (mA)
VI (V)
Figure 23. Output Voltage vs. Input Voltage
TJ = 25°C
VQ = 0 V
0
10
20
30
40
50
60
0 100 200 300 400 500 600
Iq (mA)
IQ (mA)
Figure 24. Output Current vs. Input Voltage
TJ = 25°C
VI = 13.5 V
0
0.2
0.4
0.6
0.8
1.0
1.2
1.4
1.6
0102030405060
Iq (mA)
IQ (mA)
TJ = 25°C
VI = 13.5 V
Figure 25. Current Consumption vs. Output
Current (High Load)
Figure 26. Current Consumption vs. Output
Current (Low Load)
Figure 27. Voltage Drop vs. Output Current
1.14
1.16
1.18
1.20
1.22
1.24
1.26
0 100 200 300 400
VDR (V)
IQ (mA)
TJ = 25°C
TJ = 125°C
3.2
3.3
2
VDR = VI(min) − VQ
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12
TYPICAL CHARACTERISTIC CURVES − 2.5 V Version
2.1
2.2
2.3
2.6
2.7
−40 0 40 80 120 160
VQ (V)
TJ (°C)
0
1.0
2.0
3.0
4.0
4.5
5.0
01 34 5 6
VI = 6 V
RL = 1 kW
VQ (V)
VI (V)
Figure 30. Output Voltage vs. Junction
Temperature
0
200
400
600
800
0 1020304050
IQ (mA)
VI (V)
Figure 31. Output Voltage vs. Input Voltage
TJ = 25°C
VQ = 0 V
0
10
20
30
40
50
60
0 100 200 300 400 500 600
Iq (mA)
IQ (mA)
Figure 32. Output Current vs. Input Voltage
TJ = 25°C
VI = 13.5 V
0
0.2
0.4
0.6
0.8
1.0
1.2
1.4
1.6
0102030405060
Iq (mA)
IQ (mA)
TJ = 25°C
VI = 13.5 V
Figure 33. Current Consumption vs. Output
Current (High Load)
Figure 34. Current Consumption vs. Output
Current (Low Load)
Figure 35. Voltage Drop vs. Output Current
1.95
1.96
1.97
2.00
2.02
2.03
2.05
0 100 200 300 400
VDR (V)
IQ (mA)
TJ = 25°C
TJ = 125°C
2.4
2.5
2
VDR = VI(min) − VQ
3.5
0.5
1.5
2.5
1.98
1.99
2.01
2.04
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TYPICAL CHARACTERISTIC CURVES − 2.5 V Version
0
0.5
2.5
3.0
4.5
01020304050
RL = 20 W
TJ = 25°C
Iq (mA)
VI (V)
−14
−12
−10
−8
−6
−4
−2
0
2
−50 −25 0 25 50
RL = 3.3 kW
TJ = 25°C
II (mA)
VI (V)
Figure 36. Current Consumption vs. Input Voltage Figure 37. Input Current vs. Input Voltage
1.0
1.5
4.0
2.0
3.5
NCV4274, NCV4274A
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14
APPLICATION DESCRIPTION
Output Regulator
The output is controlled by a precision trimmed reference
and error amplifier. The PNP output has saturation control
for regulation while the input voltage is low, preventing over
saturation. Current limit and voltage monitors complement
the regulator design to give safe operating signals to the
processor and control circuits.
Stability Considerations
The input capacitor CI1 in Figure 2 is necessary for
compensating input line reactance. Possible oscillations
caused by input inductance and input capacitance can be
damped by using a resistor of approximately 1 W in series
with CI2.
The output or compensation capacitor helps determine
three main characteristics of a linear regulator: startup delay,
load transient response and loop stability.
The capacitor value and type should be based on cost,
availability, size and temperature constraints. The
aluminum electrolytic capacitor is the least expensive
solution, but, if the circuit operates at low temperatures
(−25°C to −40°C), both the value and ESR of the capacitor
will vary considerably. The capacitor manufacturer’s data
sheet usually provides this information.
The value for the output capacitor CQ shown in Figure 2
should work for most applications; however, it is not
necessarily the optimized solution. Stability is guaranteed at
values CQ w 2.2 mF and an ESR v 2.5 W within the
operating temperature range. Actual limits are shown in a
graph in the Typical Performance Characteristics section.
Calculating Power Dissipation in a Single Output
Linear Regulator
The maximum power dissipation for a single output
regulator (Figure 3) is:
PD(max) +[VI(max) *VQ(min)]IQ(max) )VI(max)Iq(eq. 1)
Where:
VI(max) is the maximum input voltage,
VQ(min) is the minimum output voltage,
IQ(max) is the maximum output current for the application,
and
Iq is the quiescent current the regulator consumes at IQ(max).
Once the value of PD(max) is known, the maximum
permissible value of RqJA can be calculated:
PqJA +ǒ150 C *TAǓ
PD
(eq. 2)
The value of RqJA can then be compared with those in the
package section of the data sheet. Those packages with
RqJA
’s less than the calculated value in Equation 2 will keep
the die temperature below 150°C. In some cases, none of the
packages will be sufficient to dissipate the heat generated by
the IC, and an external heat sink will be required. The current
flow and voltages are shown in the Measurement Circuit
Diagram.
Heat Sinks
A heat sink effectively increases the surface area of the
package to improve the flow of heat away from the IC and
into the surrounding air.
Each material in the heat flow path between the IC and the
outside environment will have a thermal resistance. Like
series electrical resistances, these resistances are summed to
determine the value of RqJA:
RqJA +RqJC )RqCS )RqSA (eq. 3)
Where:
RqJC = the junction−to−case thermal resistance,
RqCS = the case−to−heat sink thermal resistance, and
RqSA = the heat sink−to−ambient thermal resistance.
RqJC appears in the package section of the data sheet.
Like RqJA, it too is a function of package type. RqCS and
RqSA are functions of the package type, heat sink and the
interface between them. These values appear in data sheets
of heat sink manufacturers. Thermal, mounting, and
heat sinking are discussed in the ON Semiconductor
application note AN1040/D, available on the
ON Semiconductor Website.
NCV4274, NCV4274A
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15
ORDERING INFORMATION4
Device* Output Voltage Accuracy Output Voltage Package Shipping†
NCV4274ADS85R4G 2% 8.5 V D2PAK
(Pb−Free)
800 / Tape & Reel
NCV4274DS50G 4% 5.0 V D2PAK
(Pb−Free)
50 Units / Rail
NCV4274DS50R4G 4% 5.0 V D2PAK
(Pb−Free)
800 / Tape & Reel
NCV4274DT50RKG 4% 5.0 V DPAK
(Pb−Free)
2500 / Tape & Reel
NCV4274ADS50G 2% 5.0 V D2PAK
(Pb−Free)
50 Units / Rail
NCV4274ADS50R4G 2% 5.0 V D2PAK
(Pb−Free)
800 / Tape & Reel
NCV4274ADT50RKG 2% 5.0 V DPAK
(Pb−Free)
2500 / Tape & Reel
NCV4274ST33T3G 4% 3.3 V SOT−223
(Pb−Free)
4000 / Tape & Reel
NCV4274DT33RKG 4% 3.3 V DPAK
(Pb−Free)
2500 / Tape & Reel
NCV4274AST33T3G 2% 3.3 V SOT−223
(Pb−Free)
4000 / Tape & Reel
NCV4274ADT33RKG 2% 3.3 V DPAK
(Pb−Free)
2500 / Tape & Reel
NCV4274ADS33R4G 2% 3.3 V D2PAK
(Pb−Free)
800 / Tape & Reel
NCV4274ST25T3G 4% 2.5 V SOT−223
(Pb−Free)
4000 / Tape & Reel
NCV4274AST25T3G 2% 2.5 V SOT−223
(Pb−Free)
4000 / Tape & Reel
†For information on tape and reel specifications, including part orientation and tape sizes, please refer to our Tape and Reel Packaging
Specifications Brochure, BRD8011/D.
*NCV Prefix for Automotive and Other Applications Requiring Unique Site and Control Change Requirements; AEC−Q100 Qualified and PPAP
Capable.
SOT−223 (TO−261)
CASE 318E−04
ISSUE R
DATE 02 OCT 2018
SCALE 1:1
q
q
MECHANICAL CASE OUTLINE
PACKAGE DIMENSIONS
ON Semiconductor and are trademarks of Semiconductor Components Industries, LLC dba ON Semiconductor or its subsidiaries in the United States and/or other countries.
ON Semiconductor reserves the right to make changes without further notice to any products herein. ON Semiconductor makes no warranty, representation or guarantee regarding
the suitability of its products for any particular purpose, nor does ON Semiconductor assume any liability arising out of the application or use of any product or circuit, and specifically
disclaims any and all liability, including without limitation special, consequential or incidental damages. ON Semiconductor does not convey any license under its patent rights nor the
rights of others.
98ASB42680B
DOCUMENT NUMBER:
DESCRIPTION:
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Printed versions are uncontrolled except when stamped “CONTROLLED COPY” in red.
PAGE 1 OF 2
SOT−223 (TO−261)
© Semiconductor Components Industries, LLC, 2018 www.onsemi.com
SOT−223 (TO−261)
CASE 318E−04
ISSUE R
DATE 02 OCT 2018
STYLE 4:
PIN 1. SOURCE
2. DRAIN
3. GATE
4. DRAIN
STYLE 6:
PIN 1. RETURN
2. INPUT
3. OUTPUT
4. INPUT
STYLE 8:
CANCELLED
STYLE 1:
PIN 1. BASE
2. COLLECTOR
3. EMITTER
4. COLLECTOR
STYLE 10:
PIN 1. CATHODE
2. ANODE
3. GATE
4. ANODE
STYLE 7:
PIN 1. ANODE 1
2. CATHODE
3. ANODE 2
4. CATHODE
STYLE 3:
PIN 1. GATE
2. DRAIN
3. SOURCE
4. DRAIN
STYLE 2:
PIN 1. ANODE
2. CATHODE
3. NC
4. CATHODE
STYLE 9:
PIN 1. INPUT
2. GROUND
3. LOGIC
4. GROUND
STYLE 5:
PIN 1. DRAIN
2. GATE
3. SOURCE
4. GATE
STYLE 11:
PIN 1. MT 1
2. MT 2
3. GATE
4. MT 2
STYLE 12:
PIN 1. INPUT
2. OUTPUT
3. NC
4. OUTPUT
STYLE 13:
PIN 1. GATE
2. COLLECTOR
3. EMITTER
4. COLLECTOR
1
A = Assembly Location
Y = Year
W = Work Week
XXXXX = Specific Device Code
G= Pb−Free Package
GENERIC
MARKING DIAGRAM*
AYW
XXXXXG
G
(Note: Microdot may be in either location)
*This information is generic. Please refer to
device data sheet for actual part marking.
Pb−Free indicator, “G” or microdot “G”, may
or may not be present. Some products may
not follow the Generic Marking.
ON Semiconductor and are trademarks of Semiconductor Components Industries, LLC dba ON Semiconductor or its subsidiaries in the United States and/or other countries.
ON Semiconductor reserves the right to make changes without further notice to any products herein. ON Semiconductor makes no warranty, representation or guarantee regarding
the suitability of its products for any particular purpose, nor does ON Semiconductor assume any liability arising out of the application or use of any product or circuit, and specifically
disclaims any and all liability, including without limitation special, consequential or incidental damages. ON Semiconductor does not convey any license under its patent rights nor the
rights of others.
98ASB42680B
DOCUMENT NUMBER:
DESCRIPTION:
Electronic versions are uncontrolled except when accessed directly from the Document Repository.
Printed versions are uncontrolled except when stamped “CONTROLLED COPY” in red.
PAGE 2 OF 2
SOT−223 (TO−261)
© Semiconductor Components Industries, LLC, 2018 www.onsemi.com
DPAK (SINGLE GAUGE)
CASE 369C
ISSUE F DATE 21 JUL 2015
SCALE 1:1
STYLE 1:
PIN 1. BASE
2. COLLECTOR
3. EMITTER
4. COLLECTOR
STYLE 2:
PIN 1. GATE
2. DRAIN
3. SOURCE
4. DRAIN
STYLE 3:
PIN 1. ANODE
2. CATHODE
3. ANODE
4. CATHODE
STYLE 4:
PIN 1. CATHODE
2. ANODE
3. GATE
4. ANODE
STYLE 5:
PIN 1. GATE
2. ANODE
3. CATHODE
4. ANODE
STYLE 6:
PIN 1. MT1
2. MT2
3. GATE
4. MT2
STYLE 7:
PIN 1. GATE
2. COLLECTOR
3. EMITTER
4. COLLECTOR
123
4
STYLE 8:
PIN 1. N/C
2. CATHODE
3. ANODE
4. CATHODE
STYLE 9:
PIN 1. ANODE
2. CATHODE
3. RESISTOR ADJUST
4. CATHODE
STYLE 10:
PIN 1. CATHODE
2. ANODE
3. CATHODE
4. ANODE
b
D
E
b3
L3
L4b2
M
0.005 (0.13) C
c2
A
c
C
Z
DIM MIN MAX MIN MAX
MILLIMETERSINCHES
D0.235 0.245 5.97 6.22
E0.250 0.265 6.35 6.73
A0.086 0.094 2.18 2.38
b0.025 0.035 0.63 0.89
c2 0.018 0.024 0.46 0.61
b2 0.028 0.045 0.72 1.14
c0.018 0.024 0.46 0.61
e0.090 BSC 2.29 BSC
b3 0.180 0.215 4.57 5.46
L4 −−− 0.040 −−− 1.01
L0.055 0.070 1.40 1.78
L3 0.035 0.050 0.89 1.27
Z0.155 −−− 3.93 −−−
NOTES:
1. DIMENSIONING AND TOLERANCING PER ASME
Y14.5M, 1994.
2. CONTROLLING DIMENSION: INCHES.
3. THERMAL PAD CONTOUR OPTIONAL WITHIN DI-
MENSIONS b3, L3 and Z.
4. DIMENSIONS D AND E DO NOT INCLUDE MOLD
FLASH, PROTRUSIONS, OR BURRS. MOLD
FLASH, PROTRUSIONS, OR GATE BURRS SHALL
NOT EXCEED 0.006 INCHES PER SIDE.
5. DIMENSIONS D AND E ARE DETERMINED AT THE
OUTERMOST EXTREMES OF THE PLASTIC BODY.
6. DATUMS A AND B ARE DETERMINED AT DATUM
PLANE H.
7. OPTIONAL MOLD FEATURE.
12 3
4
XXXXXX = Device Code
A = Assembly Location
L = Wafer Lot
Y = Year
WW = Work Week
G = Pb−Free Package
AYWW
XXX
XXXXXG
XXXXXXG
ALYWW
DiscreteIC
5.80
0.228
2.58
0.102
1.60
0.063
6.20
0.244
3.00
0.118
6.17
0.243
ǒmm
inchesǓ
SCALE 3:1
GENERIC
MARKING DIAGRAM*
*This information is generic. Please refer
to device data sheet for actual part
marking.
*For additional information on our Pb−Free strategy and soldering
details, please download the ON Semiconductor Soldering and
Mounting Techniques Reference Manual, SOLDERRM/D.
SOLDERING FOOTPRINT*
H0.370 0.410 9.40 10.41
A1 0.000 0.005 0.00 0.13
L1 0.114 REF 2.90 REF
L2 0.020 BSC 0.51 BSC
A1
H
DET AIL A
SEATING
PLANE
A
B
C
L1
L
H
L2 GAUGE
PLANE
DETAIL A
ROTATED 90 CW5
eBOTTOM VIEW
Z
BOTTOM VIEW
SIDE VIEW
TOP VIEW
ALTERNATE
CONSTRUCTIONS
NOTE 7
Z
MECHANICAL CASE OUTLINE
PACKAGE DIMENSIONS
http://onsemi.com
1
© Semiconductor Components Industries, LLC, 2002
October, 2002 − Rev. 0 Case Outline Number:
XXX
DOCUMENT NUMBER:
STATUS:
NEW STANDARD:
DESCRIPTION:
98AON10527D
ON SEMICONDUCTOR STANDARD
REF TO JEDEC TO−252
DPAK SINGLE GAUGE SURFACE MOUNT
Electronic versions are uncontrolled except when
accessed directly from the Document Repository. Printed
versions are uncontrolled except when stamped
“CONTROLLED COPY” in red.
PAGE 1 OF 2
DOCUMENT NUMBER:
98AON10527D
PAGE 2 OF 2
ISSUE REVISION DATE
ORELEASED FOR PRODUCTION. REQ. BY L. GAN 24 SEP 2001
AADDED STYLE 8. REQ. BY S. ALLEN. 06 AUG 2008
BADDED STYLE 9. REQ. BY D. WARNER. 16 JAN 2009
CADDED STYLE 10. REQ. BY S. ALLEN. 09 JUN 2009
DRELABELED DRAWING TO JEDEC STANDARDS. ADDED SIDE VIEW DETAIL A.
CORRECTED MARKING INFORMATION. REQ. BY D. TRUHITTE. 29 JUN 2010
EADDED ALTERNATE CONSTRUCTION BOTTOM VIEW. MODIFIED DIMENSIONS
b2 AND L1. CORRECTED MARKING DIAGRAM FOR DISCRETE. REQ. BY I. CAM-
BALIZA.
06 FEB 2014
FADDED SECOND ALTERNATE CONSTRUCTION BOTTOM VIEW. REQ. BY K.
MUSTAFA. 21 JUL 2015
© Semiconductor Components Industries, LLC, 2015
July, 2015 − Rev. F Case Outline Number
:
369C
ON Semiconductor and are registered trademarks of Semiconductor Components Industries, LLC (SCILLC). SCILLC reserves the right to make changes without further notice
to any products herein. SCILLC makes no warranty , representation or guarantee regarding the suitability of its products for any particular purpose, nor does SCILLC assume any liability
arising out of the application or use of any product or circuit, and specifically disclaims any and all liability, including without limitation special, consequential or incidental damages.
“Typical” parameters which may be provided in SCILLC data sheets and/or specifications can and do vary in different applications and actual performance may vary over time. All
operating parameters, including “Typicals” must be validated for each customer application by customer’s technical experts. SCILLC does not convey any license under its patent rights
nor the rights of others. SCILLC products are not designed, intended, or authorized for use as components in systems intended for surgical implant into the body, or other applications
intended to support or sustain life, or for any other application in which the failure of the SCILLC product could create a situation where personal injury or death may occur. Should
Buyer purchase or use SCILLC products for any such unintended or unauthorized application, Buyer shall indemnify and hold SCILLC and its officers, employees, subsidiaries, af filiates,
and distributors harmless against all claims, costs, damages, and expenses, and reasonable attorney fees arising out of, direct ly or indirectly, any claim of personal injury or death
associated with such unintended or unauthorized use, even if such claim alleges that SCILLC was negligent regarding the design or manufacture of the part. SCILLC is an Equal
Opportunity/Affirmative Action Employer. This literature is subject to all applicable copyright laws and is not for resale in any manner.
http://onsemi.com
1
D2PAK
CASE 418AF
ISSUE E DATE 15 SEP 2015
SCALE 1:1
XX
XXXXXXXXX
AWLYYWWG
XXXXX = Specific Device Code
A = Assembly Location
WL = Wafer Lot
YY = Year
WW = W ork Week
G = Pb−Free Package
GENERIC
MARKING DIAGRAM*
*This information is generic. Please refer
to device data sheet for actual part
marking. Pb−Free indicator, “G”, may
or not be present.
V
U
TERMINAL 4
NOTES:
1. DIMENSIONING AND TOLERANCING PER ANSI
Y14.5M, 1982.
2. CONTROLLING DIMENSION: INCHES.
3. TAB CONTOUR OPTIONAL WITHIN DIMENSIONS
A AND K.
4. DIMENSIONS U AND V ESTABLISH A MINIMUM
MOUNTING SURFACE FOR TERMINAL 4.
5. DIMENSIONS A AND B DO NOT INCLUDE MOLD
FLASH OR GATE PROTRUSIONS. MOLD FLASH
AND GATE PROTRUSIONS NOT TO EXCEED
0.025 (0.635) MAXIMUM.
6. SINGLE GAUGE DESIGN WILL BE SHIPPED
AFTER FPCN EXPIRATION IN OCTOBER 2011.
DIM
A
MIN MAX MIN MAX
MILLIMETERS
0.386 0.403 9.804 10.236
INCHES
B0.356 0.368 9.042 9.347
C0.170 0.180 4.318 4.572
D0.026 0.036 0.660 0.914
E0.045 0.055 1.143 1.397
F0.051 REF 1.295 REF
G0.100 BSC 2.540 BSC
H0.539 0.579 13.691 14.707
J0.125 MAX 3.175 MAX
K0.050 REF 1.270 REF
L0.000 0.010 0.000 0.254
M0.088 0.102 2.235 2.591
N0.018 0.026 0.457 0.660
P0.058 0.078 1.473 1.981
R
S0.116 REF 2.946 REF
U0.200 MIN 5.080 MIN
V0.250 MIN 6.350 MIN
A
12 3
K
F
B
J
S
H
D
M
0.010 (0.254) T
E
OPTIONAL
CHAMFER
BOTTOM VIEW
OPTIONAL CONSTRUCTIONS
T OP VIEW
SIDE VIEW
DUAL GAUGE BOTTOM VIEW
L
T
P
RDETAIL C
SEATING
PLANE
3X
G
NM
CONSTRUCTION
D
C
DETAIL C
E
OPTIONAL
CHAMFER
SIDE VIEW
SINGLE GAUGE
CONSTRUCTION
S
C
DETAIL C
TT
D
E0.018 0.026 0.457 0.660
S
*For additional information on our Pb−Free strategy and soldering
details, please download the ON Semiconductor Soldering and
Mounting Techniques Reference Manual, SOLDERRM/D.
SOLDERING FOOTPRINT*
8.380
2.540
DIMENSIONS: MILLIMETERS
PITCH
3X
16.155
1.016
3X
10.490
3.504
0_8_0_8_
MECHANICAL CASE OUTLINE
PACKAGE DIMENSIONS
http://onsemi.com
1
© Semiconductor Components Industries, LLC, 2002
October, 2002 − Rev. 0 Case Outline Number:
XXX
DOCUMENT NUMBER:
STATUS:
NEW STANDARD:
DESCRIPTION:
98AON21981D
ON SEMICONDUCTOR STANDARD
D2PAK, 3 LEAD, NON−CROPPED
Electronic versions are uncontrolled except when
acc essed d irectly f rom the Doc ument R epository. Printed
versions are uncontrolled except when stamped
“CONTROLLED COPY” in red.
PAGE 1 OF 2
http://onsemi.com
2
DOCUMENT NUMBER:
98AON21981D
PAGE 2 OF 2
ISSUE REVISION DATE
ORELEASED FOR PRODUCTION. REQ. BY A. NOAH. 13 FEB 2006
AADDED SOLDERING FOOTPRINT. REQ. BY M. FILLION. 18 JUN 2007
BADDED SINGLE AND DUAL GAUGE SIDE VIEWS AND BOTTOM VIEW. REQ. BY
J. KREMMER. 08 NOV 2011
CCORRECTED SOLDERING FOOTPRINT TO VERSION FROM ISSUE A. REQ. BY
J. KREMMER. 13 APR 2012
DCORRECTED SOLDERING FOOTPRINT BACK TO VERSION FROM ISSUE B.
REQ. BY J. KREMMER. 24 MAY 2012
EREVISED DIMENSION R FROM 5 DEGREES REFERENCE TO 0 & 8 DEGREES
MIN & MAX. REQ. BY K. MUSTAFA. 15 SEP 2015
© Semiconductor Components Industries, LLC, 2015
September, 2015 − Rev. E Case Outline Number
:
418AF
ON Semiconductor and are registered trademarks of Semiconductor Components Industries, LLC (SCILLC). SCILLC reserves the right to make changes without further notice
to any products herein. SCILLC makes no warranty, representation or guarantee regarding the suitability of its products for any particular purpose, nor does SCILLC assume any
liability arising out of the application or use of any product or circuit, and specifically disclaims any and all liability, including without limitation special, consequential or incidental
damages. “Typical” parameters which may be provided in SCILLC data sheets and/or specifications can and do vary in different applications and actual performance may vary over
time. All operating parameters, including “Typicals” must be validated for each customer application by customer ’s technical experts. SCILLC does not convey any license under
its patent rights nor the rights of others. SCILLC products are not designed, intended, or authorized for use as components in systems intended for surgical implant into the body,
or other applications intended to support or sustain life, or for any other application in which the failure of the SCILLC product could create a situation where personal injury or death
may occur. Should Buyer purchase or use SCILLC products for any such unintended or unauthorized application, Buyer shall indemnify and hold SCILLC and its officers, employees,
subsidiaries, affiliates, and distributors harmless against all claims, costs, damages, and expenses, and reasonable attorney fees arising out of, directly or indirectly, any claim of
personal injury or death associated with such unintended or unauthorized use, even if such claim alleges that SCILLC was negligent regarding the design or manufacture of the part.
SCILLC is an Equal Opportunity/Affirmative Action Employer. This literature is subject to all applicable copyright laws and is not for resale in any manner.
ON Semiconductor and are trademarks of Semiconductor Components Industries, LLC dba ON Semiconductor or its subsidiaries in the United States and/or other countries.
ON Semiconductor owns the rights to a number of patents, trademarks, copyrights, trade secrets, and other intellectual property. A listing of ON Semiconductor ’s product/patent
coverage may be accessed at www.onsemi.com/site/pdf/Patent−Marking.pdf. ON Semiconductor reserves the right to make changes without further notice to any products herein.
ON Semiconductor makes no warranty, representation or guarantee regarding the suitability of its products for any particular purpose, nor does ON Semiconductor assume any liability
arising out of the application or use of any product or circuit, and specifically disclaims any and all liability, including without limitation special, consequential or incidental damages.
Buyer is responsible for its products and applications using ON Semiconductor products, including compliance with all laws, regulations and safety requirements or standards,
regardless of any support or applications information provided by ON Semiconductor. “Typical” parameters which may be provided in ON Semiconductor data sheets and/or
specifications can and do vary in different applications and actual performance may vary over time. All operating parameters, including “Typicals” must be validated for each customer
application by customer ’s technical experts. ON Semiconductor does not convey any license under its patent rights nor the rights of others. ON Semiconductor products are not
designed, intended, or authorized for use as a critical component in life support systems or any FDA Class 3 medical devices or medical devices with a same or similar classification
in a foreign jurisdiction or any devices intended for implantation in the human body . Should Buyer purchase or use ON Semiconductor products for any such unintended or unauthorized
application, Buyer shall indemnify and hold ON Semiconductor and its officers, employees, subsidiaries, affiliates, and distributors harmless against all claims, costs, damages, and
expenses, and reasonable attorney fees arising out of, directly or indirectly, any claim of personal injury or death associated with such unintended or unauthorized use, even if such
claim alleges that ON Semiconductor was negligent regarding the design or manufacture of the part. ON Semiconductor is an Equal Opportunity/Affirmative Action Employer. This
literature is subject to all applicable copyright laws and is not for resale in any manner.
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