SP7516AN - Sipex Corporation - Datasheet.Directory

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DESCRIPTION…

The SP7516 and HS3160 are precision 16-bit multiplying DACs, that provide four-quadrant

multiplication. Both parts accept both AC and DC reference voltages. The SP7516 is available

for use in commercial and industrial temperature ranges, packaged in a 24-pin SOIC. The

HS3160 is available in commercial and military temperature ranges, packaged in a 22-pin

side-brazed DIP.

■Monolithic Construction

■16–Bit Resolution

■0.003% Non-Linearity

■Four-Quadrant Multiplication

■Latch-up Protected

■Low Power - 30mW

■ Single +15V Power Supply

IOUT1

RFEEDBACK

BIT16

(LSB)

BIT4BIT3BIT2BIT1

(MSB)

VDD

GND

VREF Force

Switches shown in high state.

SP7516

5 6 7 8 20 24

VREF Sense 22

3IOUT2 Force

IOUT2 Sense

IOUT1

IOUT2

RFEEDBACK

BIT16

(LSB)

BIT4BIT3BIT2BIT1

(MSB)

VDD

GND

VREF

Switches shown in high state.

HS3160

4 5 6 7 19 22

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SIGNAL PROCESSING EXCELLENCE

SP7516 and HS3160

16-Bit Multiplying DACs

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SPECIFICATIONS

(Typical @ 25 °C, nominal power supply, V REF = +10V, unipolar unless otherwise noted)

PARAMETER MIN. TYP. MAX. UNITS CONDITIONS

DIGITAL INPUT

Resolution 16 Bits

2–Quad, Unipolar Coding Binary

4–Quad, Bipolar Coding Offset Binary

Logic Compatibility CMOS, TTL Note 1

Input Current ±1µA

REFERENCE INPUT

Voltage Range ±25 V Note 2

Input Impedance 3.25 9.75 KOhms

ANALOG OUTPUT

Scale Factor 75 225 µA/VREF

Scale Factor Accuracy ±1 % Note 3

Output Leakage 10 nA Note 4

Output Capacitance

COUT 1, all inputs high 100 pF

COUT 1, all inputs low 50 pF

COUT 2, all inputs high 50 pF

COUT 2, all inputs low 100 pF

STATIC PERFORMANCE

Integral Linearity Note 5

SP7516KN/BN, HS3160–4 ±0.003 ±0.006 % FSR

SP7516JN/AN, HS3160–3 ±0.006 ±0.012 % FSR

Differential Linearity Note 6

SP7516KN/BN, HS3160–4 ±0.003 ±0.006 %FSR

SP7516JN/AN, HS3160–3 ±0.006 ±0.012 % FSR

Monotonicity

SP7516KN/BN, HS3160–4 Guaranteed to 14 bits

SP7516JN/AN, HS3160–3 Guaranteed to 13 bits

STABILITY (TMIN to TMAX)

Scale Factor 4 ppm FSR/°C Note 7 and 8

Integral Linearity 0.5 1.0 ppm FSR/°C

Differential Linearity 0.5 1.0 ppm FSR/°C

Monotonicity Temp. Range

SP7516JN/KN, HS3160C 0 +70 °C

SP7516AN/BN –40 +85 °C

HS3160B–_ –55 +125 °C

DYNAMIC PERFORMANCE

Digital Small Signal Settling 1.0 µS

Digital Full Scale Settling 2.0 µS

Reference Feedthrough Error (VREF = 20Vpp)

@ 1kHz 200 µV

@ 10kHz 2 mV

Reference Input Bandwidth 1 MHz

POWER SUPPLY (VDD)

Operating Voltage +15 ±5% V

Voltage Range +8 +18 V

Current 2.0 mA Note 9

Rejection Ratio 0.005 %/%

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0.048%

0.024%

0.012%

0.006%

0.003%

LINEARITY - %

6 8 10 12 14 16 18

VDD-VOLTS

Linearity vs. Supply Voltage

2.5

410

6 8 10 12 14 16 18

2.0

1.5

1.0

DD-mA

VDD-VOLTS

Power Supply Current vs. Voltage

0.048

0.024

0.012

0.006

0.003

0.01 0.1 1 10

INTEGRAL LINEARITY ERROR - %

VREF-VOLTS

Integral Linearity Error vs. Reference Voltage

CHARACTERISTIC CURVES

(Typical @ + 25°C, VDD = + 15VDC, VREF = + 10VDC, unless otherwise noted.)

Additional Linearity Error vs. Output-Amplifier

Offset-Voltage (VREF = + 10V)

0.01

GAIN CHANGE - %

6 8 10 12 14 16 18

0.004

0.002

VDD-VOLTS

0.008

0.006

Gain Change vs. Supply Voltage

001020304050

2 LSB

1 LSB

1/2 LSB @ 16 BITS

LINEARITY ERROR - PPM

VOS-mV

SPECIFICATIONS (continued)

(Typical @ 25°C, nominal power supply, VREF = +10V, unipolar unless otherwise noted)

PARAMETER MIN. TYP. MAX. UNITS CONDITIONS

ENVIRONMENTAL AND MECHANICAL

Operating Temperature

SP7516JN/KN 0 +70 °C

SP7516AN/BN –40 +85 °C

HS3160–C 0 +70 °C

HS3160–B –55 +125 °C

HS3160–B/883 –55 +125 °C

Storage Temperature –65 +150 °C

Package

SP7516_N 24-pin SOIC

HS3160 22–pin Side–Brazed DIP

Notes:

1. Digital input voltage must not exceed supply voltage or go below –0.5V ; “0” <0.8V; 2.4V < “1” ≤VDD.

2. AC or DC; use R6758–1 for fixed reference applications

3. Using the internal feedback resistor and an external op amp. The Scale Factor can be adjusted externally by variable resistors in series with the

reference input and/or in series to the internal feedback resistor. Please refer to the Applications Information section.

4. At 25°C; the output leakage current will create an offset voltage at the external op amps output. It doubles every 10 °C temperature increase.

5. Integral Linearity is measured as the arithmetic mean value of the magnitudes of the greatest positive deviation and the greatest negative deviation from

the theoretical value for any given input combination.

6. Differential Linearity is the deviation of an output step form the theoretical value of 1LSB for any two adjacent digital input codes.

7. At 25°C, the output leakage current will create an offset voltage output. It doubles every 10°C temperature increase.

8. Using the internal feedback resistor and an external op amp.

9. Use series 470ohm resistor to limit startup current.

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PIN ASSIGNMENTS

HS3160 22–PIN

Pin 1 – IO1 – Current Output 1.

Pin 2 – IO2 – Current Output 2.

Pin 3 – GND – Ground.

Pin 4 – DB15 – MSB, Data Bit 1.

Pin 5 – DB14 – Data Bit 2.

Pin 6 – DB13 – Data Bit 3.

Pin 7 – DB12 – Data Bit 4.

Pin 8 – DB11 – Data Bit 5.

Pin 9 – DB10 – Data Bit 6.

Pin 10 – DB9 – Data Bit 7.

Pin 11 – DB8 – Data Bit 8.

Pin 12 – DB7 – Data Bit 9.

Pin 13 – DB6 – Data Bit 10.

Pin 14 – DB5 – Data Bit 11.

Pin 15 – DB4 – Data Bit 12.

Pin 16 – DB3 – Data Bit 13.

Pin 17 – DB2 – Data Bit 14.

Pin 18 – DB1 – Data Bit 15.

Pin 19 – DB0 – LSB, Data Bit 16.

Pin 20 – VDD – Positive Supply Voltage.

Pin 21 – VREF – Reference Voltage Input.

Pin 22 – RFB – Feedback Resistor.

SP7516 24–PIN

Pin 1 – IO1 – Current Output 1.

Pin 2 – IO2 Sense – Current Output 2.

Pin 3 – IO3 Force – Current Output 3.

Pin 4 – GND – Ground.

Pin 5 – DB15 – MSB, Data Bit 1.

Pin 6 – DB14 – Data Bit 2.

Pin 7 – DB13 – Data Bit 3.

Pin 8 – DB12 – Data Bit 4.

Pin 9 – DB11 – Data Bit 5.

Pin 10 – DB10 – Data Bit 6.

Pin 11 – DB9 – Data Bit 7.

Pin 12 – DB8 – Data Bit 8.

Pin 13 – DB7 – Data Bit 9.

Pin 14 – DB6 – Data Bit 10.

Pin 15 – DB5 – Data Bit 11.

Pin 16 – DB4 – Data Bit 12.

Pin 17 – DB3 – Data Bit 13.

Pin 18 – DB2 – Data Bit 14.

Pin 19 – DB1 – Data Bit 15.

Pin 20 – DB0 – LSB, Data Bit 16.

Pin 21 – VDD – Positive Supply Voltage.

Pin 22 – VREF Sense – Reference Voltage Input.

Pin 23 – VREF Force – Reference Voltage Input.

Pin 24 – RFB – Feedback Resistor.

FEATURES…

The SP7516 and HS3160 are precision 16-bit multi-

plying DACs. The DACs are implemented as a one-

chip CMOS circuit with a resistor ladder network.

Three output lines are provided on the DACs to allow

unipolar and bipolar output connection with a mini-

mum of external components. The feedback resistor

is internal. The resistor ladder network termination is

externally available, thus eliminating an external re-

sistor for the 1 LSB offset in bipolar mode.

The SP7516 is available for use in commercial and

industrial temperature ranges, packaged in a 24-pin

SOIC. The HS3160 is available in commercial

and military temperature ranges, packaged in a

24–pin side–brazed DIP. For product processed

and screened to the requirements of MIL–M–

38510 and MIL–STD–883C, please consult the

factory (HS3160B only).

PRINCIPLES OF OPERATION

The SP7516/HS3160 achieve high accuracy by using

a decoded or segmented DAC scheme to implement

this function. The following is a brief description of

this approach.

Figure 1. SP7516/HS3160 Equivalent Output Circuit

–

VREF

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2 - 1(MSB) 2 - 2Output

00 0

0 1 1/4 Full-Scale

1 0 1/2 Full-Scale

1 1 3/4 Full-Scale

Table 1. Contribution of the two MSB's

VREF VDD

470Ω

DIGITAL

INPUTS

RFEEDBACK

IO1

IO2

GND

ROS

AVOUT

SP7516

HS3160

200Ω

400Ω

Figure 2. Unipolar Operation

The most common technique for building a D/A

converter of n bits is to use n switches to turn n current

or voltage sources on or off. The n switches and n

sources are designed so that each switch or bit contrib-

utes twice as much to the D/A converter’s output as the

preceding bit. This technique is commonly known as

binary weighting and allows an n-bit converter to

generate 2n output levels by turning on the proper

combination of bits.

In such a binary-weighted converter, the switch

with the smallest contribution (the LSB) accounts

for only 2 -n of the converter’s full-scale value.

Similarly, the switch with the largest contribution

(the MSB) accounts for 2 -1 or half of the converter’s

full-scale output. Thus it is easy to see that a given

percent change in the MSB will have a greater

effect on the converter’s output than would a

similar percent change in the LSB. For example, a

1% change in the LSB of a 10 bit converter would

only affect the output by 0.001% of full-scale. A

1% change in the MSB of the same converter

would affect the output by 0.5% of FSR.

In order to overcome the problem which results from

the large weighting of the MSB, the two MSB’s can

be decoded to three equally weighted sources. Table

1 shows that all combinations of the two MSB’s of a

converter result in four output levels. So by replacing

the two MSB’s with three bits equally weighted at 1/

4 full-scale and decoding the two MSB digital inputs

into three lines which drive the equally weighted bits,

the same functional performance can be obtained.

Thus by replacing the two MSB switches of a conven-

tional converter with three switches properly de-

coded, the contribution of any switch is reduced from

1/2 to 1/4. This reduction in sensitivity also reduces the

accuracy required of any switch for a given overall

converter accuracy.

With the decoded converter described above, a 1%

change in any of the converter’s switches will affect

the output by no more than 0.25% of full-scale as

compared to 0.5% for a conventional converter. In

other words the conventional D/A converter can be

made less sensitive to the quality of its individual bits

by decoding.

In the SP7516/HS3160 the first four MSB’s are

decoded into 16 levels which drive 15 equally weighted

current sources. The sensitivity of each switch on the

output is reduced by a factor of 8. Each of the 15

sources contributes 6.25% output change rather than

an MSB change of 50% for the common approach.

DIGITAL

INPUTS

RFEEDBACK

IO1

IO2

GND

ROS1

AVOUT

1



-A2

ROS2

VOUT1

A1, A2, OP-07

4KΩ

ROS2 R

200Ω

VREF VDD

470Ω

400Ω

SP7516

HS3160

Figure 3. Bipolar Operation

TRANSFER FUNCTION (N=16)

BINARY INPUT UNIPOLAR OUTPUT BIPOLAR OUTPUT

111...111 –VREF (1 - 2–N)–V

REF (1 – 2 –(N – 1))

100...001 –VREF (1/2 + 2–N)–V

REF (2 –(N – 1))

100...000 –VREF /2 0

011...111 –VREF (1/2 – 2–N)V

REF (2 –(N – 1))

000…001 –VREF (2(N – 1))V

REF (1 – 2 –(N – 1))

000...000 0 VREF

Table 2. Transfer Function

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Figure 4. Microprocessor Interface to SP7514

CLK

74273

VREF

(+ 25V MAX)

LSB

SP7514/

7516

74273

CLK MSB GND

LATCHESADDRESS DECODER

G2A

74LS138

G2B

–

200

470 3

400

BDSEL

VREF

VDD

I01

I02

UNIPOLAR MODE

(2-QUADRANT)

3A1

VOUT

0 TO - VREF

(1-2

- N

)

R0S

SP7516/

HS3160

HS3160, small values for Cf must be used. Resis-

tor Rp can be added, this will parallel Rj decreasing

the effective resistance. If Cf is reduced the band-

width will be increased and settling time decreased.

However a system penalty for lowering Cf is to

increase noise gain. The tradeoff is noise vs. set-

tling time. If Rp is added then a large value (1µF or

greater) non-polarized capacitor Cp should be added

in series with Rp to eliminate any DC drifts. If

settling time is not important, eliminate Rp and Cp,

and adjust Cf to prevent overshoot.

Output Offset

In most applications, the output of the DAC is fed

into an amplifier to convert the DAC’s current

output to voltage. A little known and not com-

monly discussed parameter is the linearity error

versus offset voltage of the output amplifier. All

CMOS DAC’s must operate into a virtual ground,

i.e., the summing junction of an op amp. Any

amplifier’s offset from the amplifier will appear as

an error at the output (which can be related to

LSB’s of error).

Most all CMOS DAC’s currently available are

implemented using an R-2R ladder network. The

formula for nonlinearity is typically 0.67mV/mVOS

(not derived here). However the SP7516 has a

coefficient of only 0.065mV/mVOS. This is due to

the decoding technique described earlier. CMOS

DAC applications notes (including this one) al-

ways show a potentiometer used to null out the

amplifier’s offset. If an amplifier is chosen having

‘pretrimmed’ offset it may be possible to eliminate

this component. Consider the following calcula-

tions:

1. Using LF441A amplifier (low power - 741 pinout)

2. Specified offset: 0.5mV max

3. Temperature coefficient of input offset: 10µV/°C max

VOS max (0°C to 70°C) = 0.5mV + (70µV)10

= 1.2mV

Add'l nonlinearity (max) = 1.2mV x 0.065mV/mV

= 78µV (1/2 LSB @ 16 Bits!)

Where: 78µV = 1/2 LSB @ 16 Bits (10V range)

Via the above configuration, the SP7516/HS3160

can be used to divide an analog signal by digital

code (i.e. for digitally controlled gain). The trans-

fer function is given in Table 2, where the value of

each bit is 0 or 1. Division by all “0”s is undefined

and causes the op amp to saturate.

Following the decoded section of the DAC a

standard binary weighted R-2R approach is used.

This divides each of the 16 levels (or 6.25% of

F.S.) into 4096 discrete levels (the 12 LSB’s).

Output Capacitance

The SP7516/HS3160 have very low output ca-

pacitance (CO). This is specified both with all

switches ON and all switches OFF. Output capaci-

tance varies from 50pF to 100pF over all input

codes. This low capacitance is due in part to the

decoding technique used. Smaller switches are

used with resulting less capacitance. Three impor-

tant system characteristics are affected by CO and

∆CO; namely digital feedthrough, settling time,

and bandwidth. The DAC output equivalent cir-

cuit can be represented as shown in Figure 1.

Digital feedthrough is the change in analog output

due to the toggling conditions on the converter

input data lines when the analog input VREF is at

0V. The SP7516/HS3160 very low CO and there-

fore will yield low digital feedthrough. Inputs to

the DAC can be buffered. This input latch with

microprocessor control is shown in Figure 4.

Settling time is directly affected by CO. In Figure

1, CO combines with Rf to add a pole to the open

loop response, reducing bandwidth and causing

excessive phase shift - which could result in

ringing and/or oscillation. A feedback capaci-

tor, Cf must be added to restore stability. Even with

Cf, there is still a zero-pole mismatch due to RiCO

which is code dependent. This code dependent

mismatch is minimized when C ORi = RfCf. How-

ever Cf must now be made larger to compensate for

worst case ∆RiCO - resulting in reduced bandwidth

and increased settling time. With the SP7516/

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Applications Information

Unipolar Operation

Figure 2 shows the interconnections for unipolar

operation. Connect IO1 and FB1 as shown in dia-

gram. Tie IO2 (Pin 7), FB3 (Pin 3), and FB4 (Pin 1)

to Ground (Pin 8). As shown, a series resistor is

recommended in the VDD supply line to limit

current during ‘turn-on.’ To maintain specified

linearity, external amplifiers must be zeroed. Apply

an ALL “ZEROES” digital input and adjust ROS

for VOUT = 0 ± 1mV. The SP7516 and HS3160

have been used successfully with OP-07, OP-27

and LF441A. For high speed applications the

SP2525 is recommended.

Bipolar Operation

Figure 3 shows the interconnections for bipolar

operation. Connect IO1, IO2, FB1, FB3, FB4 as

shown in diagram. Tie LDTR to IO2. As shown, a

series resistor is recommended in the VDD supply

line to limit current during ‘turn-on. To maintain

specified linearity, external amplifiers must be

zeroed. This is best done with VREF set to zero and,

the DAC register loaded with 10...0 (MSB = 1). Set

R0S1 for V01 = 0. Set R0S2 for VOUT = 0. Set VREF

to +10V and adjust RB for VOUT to be 0V.

Grounding

Connect all GND pins to system analog ground

and tie this to digital ground. All unused input

pins must be grounded.

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ORDERING INFORMATION

Model ................................................................ Monotonicity................................ Temperature Range ....................................Package

16-Bit Multiplying DAC

HS3160C-3Q............................................................ 13-Bit ............................................... 0°C to +70°C ................... 22-pin, 0.4" Side-Brazed DIP

HS3160B-3Q............................................................ 13-Bit ......................................... -55°C to +125°C ................... 22-pin, 0.4" Side-Brazed DIP

HS3160B-3/883 ....................................................... 13-Bit ......................................... -55°C to +125°C ................... 22-pin, 0.4" Side-Brazed DIP

HS3160C-4Q............................................................ 14-Bit ............................................... 0°C to +70°C ................... 22-pin, 0.4" Side-Brazed DIP

HS3160B-4Q............................................................ 14-Bit ......................................... -55°C to +125°C ................... 22-pin, 0.4" Side-Brazed DIP

HS3160B-4/883 ....................................................... 14-Bit ......................................... -55°C to +125°C .................. 22-pin , 0.4" Side-Brazed DIP

SP7516JN ................................................................ 13-Bit ...............................................0°C to +70°C ......................................24-pin, 0.3" SOIC

SP7516KN ............................................................... 14-Bit ...............................................0°C to +70°C ......................................24-pin, 0.3" SOIC

SP7516AN ............................................................... 13-Bit .......................................... –40°C to +85°C ......................................24-pin, 0.3" SOIC

SP7516BN ............................................................... 14-Bit .......................................... –40°C to +85°C ......................................24-pin, 0.3" SOIC