   
    
        
SDLS053B − O C TOBER 1976 − REVISED MAY 2004
1
POST OFFICE BOX 655303 • DALLAS, TEXAS 75265
’147, ’LS147
DEncode 10-Line Decimal to 4-Line BCD
DApplications Include:
− Keyboard Encoding
− Range Selection
’148, ’LS148
DEncode 8 Data Lines to 3-Line Binary
(Octal)
DApplications Include:
− n-Bit Encoding
− Code Converters and Generators
3212019
910111213
4
5
6
7
8
18
17
16
15
14
D
3
NC
2
1
6
7
NC
8
C
5
4
NC
A
9V
NC
B
GND
NC
SN54LS147 ...FK PACKAGE
(TOP VIEW)
CC
NC − No internal connection
1
2
3
4
5
6
7
8
16
15
14
13
12
11
10
9
4
5
6
7
8
C
B
GND
VCC
NC
D
3
2
1
9
A
SN54147, SN54LS147 ...J OR W PACKAGE
SN74147, SN74LS147 ...D OR N PACKAGE
(TOP VIEW)
1
2
3
4
5
6
7
8
16
15
14
13
12
11
10
9
4
5
6
7
EI
A2
A1
GND
VCC
E0
GS
3
2
1
0
A0
SN54148, SN54LS148 ...J OR W PACKAGE
SN74148, SN74LS148 . . . D, N, OR NS PACKAGE
(TOP VIEW)
3212019
910111213
4
5
6
7
8
18
17
16
15
14
GS
3
NC
2
1
6
7
NC
EI
A2
5
4
NC
A0
0V
E0
A1
GND
NC
SN54LS148 . . . FK PACKAGE
(TOP VIEW)
CC
TYPE TYPICAL
DATA
DELAY
TYPICAL
POWER
DISSIPATION
’147 10 ns 225 mW
’148 10 ns 190 mW
’LS147 15 ns 60 mW
’LS148 15 ns 60 mW
NOTE: The SN54147, SN54LS147, SN54148, SN74147, SN74LS147, and SN74148 are obsolete and are no longer supplied.
Please be aware that an important notice concerning availability, standard warranty, and use in critical applications o
f
Texas Instruments semiconductor products and disclaimers thereto appears at the end of this data sheet.
Copyright 2004, Texas Instruments Incorporated
  !"#$ % &'!!($ #%  )'*+&#$ ,#$(-
!,'&$% &!" $ %)(&&#$% )(! $.( $(!"%  (/#% %$!'"($%
%$#,#!, 0#!!#$1- !,'&$ )!&(%%2 ,(% $ (&(%%#!+1 &+',(
$(%$2  #++ )#!#"($(!%-
 )!,'&$% &")+#$ $ 3 #++ )#!#"($(!% #!( $(%$(,
'+(%% $.(!0%( $(,-  #++ $.(! )!,'&$% )!,'&$
)!&(%%2 ,(% $ (&(%%#!+1 &+',( $(%$2  #++ )#!#"($(!%-
   
    
        
SDLS053B − O C TOBER 1976 − REVISED MAY 2004
2POST OFFICE BOX 655303 • DALLAS, TEXAS 75265
description/ordering information
These TTL encoders feature priority decoding of the inputs to ensure that only the highest-order data line is
encoded. The ’147 and ’LS147 devices encode nine data lines to four-line (8-4-2-1) BCD. The implied decimal
zero condition requires no input condition, as zero is encoded when all nine data lines are at a high logic level.
The ’148 and ’LS148 devices encode eight data lines to three-line (4-2-1) binary (octal). Cascading circuitry
(enable input EI and enable output EO) has been provided to allow octal expansion without the need for external
circuitry. For all types, data inputs and outputs are active at the low logic level. All inputs are buffered to represent
one normalized Series 54/74 or 54/74LS load, respectively.
ORDERING INFORMATION
TAPACKAGE†ORDERABLE
PART NUMBER TOP-SIDE
MARKING
PDIP − N Tube SN74LS148N SN74LS148N
0°C to 70°C
SOIC − D
Tube SN74LS148D
LS148
0°C to 70°CSOIC − D Tape and reel SN74LS148DR LS148
SOP − NS Tape and reel SN74LS148NSR 74LS148
CDIP − J Tube SNJ54LS148J SNJ54LS148J
−55°C to 125°CCFP − W Tube SNJ54LS148W SNJ54LS148W
−55 C to 125 C
LCCC − FK Tube SNJ54LS148FK SNJ54LS148FK
†Package drawings, standard packing quantities, thermal data, symbolization, and PCB design guidelines are
available at www.ti.com/sc/package.
FUNCTION TABLE − ’147, ’LS147
INPUTS OUTPUTS
1 2 3 4 5 6 7 8 9 D C B A
H H H H H H H H H H H H H
XXXXXXXXLLHHL
XXXXXXXLHLHHH
XXXXXXLHHHLLL
XXXXXLHHHHLLH
XXXXLHHHHHLHL
XXXLHHHHHHLHH
XXLHHHHHHHHLL
XLHHHHHHHHHLH
L H H H H H H H H H H H L
H = high logic level, L = low logic level, X = irrelevant
   
    
        
SDLS053B − O C TOBER 1976 − REVISED MAY 2004
3
POST OFFICE BOX 655303 • DALLAS, TEXAS 75265
FUNCTION TABLE − ’148, ’LS148
INPUTS OUTPUTS
EI 0 1 2 3 4 5 6 7 A2 A1 A0 GS EO
H X X X X X X X X H H H H H
L H HHHHHHHHHHHL
L X XXXXXXLLLLLH
L X XXXXXLHLLHLH
L X XXXXLHHLHLLH
L X XXXLHHHLHHLH
L X XXLHHHHHLLLH
L X XLHHHHHHLHLH
L X LHHHHHHHHLLH
L L H H H H H H H H H H L H
H = high logic level, L = low logic level, X = irrelevant
   
    
        
SDLS053B − O C TOBER 1976 − REVISED MAY 2004
4POST OFFICE BOX 655303 • DALLAS, TEXAS 75265
’147, ’LS147 logic diagram (positive logic)
(11)
(12)
(13)
(1)
(2)
(3)
(4)
(5)
(10)
1
2
3
4
5
6
7
8
9D
B
C
A
(9)
(7)
(6)
(14)
Pin numbers shown are for D, J, N, and W packages.
   
    
        
SDLS053B − O C TOBER 1976 − REVISED MAY 2004
5
POST OFFICE BOX 655303 • DALLAS, TEXAS 75265
’148, ’LS148 logic diagram (positive logic)
(10)
(11)
(12)
(13)
(1)
(2)
(3)
(4)
1
2
3
4
5
6
7
EI
A1
A2
A0
(5)
0
(14)
EO
G5
(6)
(9)
(7)
(15)
Pin numbers shown are for D, J, N, NS, and W packages.
   
    
        
SDLS053B − O C TOBER 1976 − REVISED MAY 2004
6POST OFFICE BOX 655303 • DALLAS, TEXAS 75265
schematics of inputs and outputs
EQUIVALENT OF EACH INPUT
VCC
Input
Req
0 input (’148): Req = 2 kΩ NOM
All other inputs: Req = 4 kΩ NOM
TYPICAL OF ALL OUTPUTS
VCC
Output
’147, ’148
 Ω NOM
EQUIVALENT OF ALL INPUTS
VCC
Input
’LS147, ’LS148
TYPICAL OF ALL OUTPUTS
Output
VCC
120 Ω NOM
Req
’LS148 inputs 1–7: Req = 9 kΩ NOM
All other inputs: Req = 18 kΩ NOM
   
    
        
SDLS053B − O C TOBER 1976 − REVISED MAY 2004
7
POST OFFICE BOX 655303 • DALLAS, TEXAS 75265
absolute maximum ratings over operating free-air temperature (unless otherwise noted)†
Supply voltage, VCC (see Note 1) 7 V. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
Input voltage, VI: ’147, ’148 5.5 V. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
’LS147, ’LS148 7 V. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
Inter-emitter voltage: ’148 only (see Note 2) 5.5 V. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
Package thermal impedance θJA (see Note 3): D package 73°C/W. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
N package 67°C/W. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
NS package 64°C/W. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
Storage temperature range, Tstg −65°C to 150°C. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
†Stresses beyond those listed under “absolute maximum ratings” may cause permanent damage to the device. These are stress ratings only, and
functional operation of the device at these or any other conditions beyond those indicated under “recommended operating conditions” is not
implied. Exposure to absolute-maximum-rated conditions for extended periods may affect device reliability.
NOTES: 1. Voltage values, except inter-emitter voltage, are with respect to the network ground terminal.
2. This is the voltage between two emitters of a multiple-emitter transistor. For ’148 circuits, this rating applies between any two of the
eight data lines, 0 through 7.
3. The package thermal impedance is calculated in accordance with JESD 51-7.
recommended operating conditions (see Note 4)
SN54’ SN74’ SN54LS’ SN74LS’
UNIT
MIN NOM MAX MIN NOM MAX MIN NOM MAX MIN NOM MAX
UNIT
VCC Supply voltage 4.5 5 5.5 4.75 5 5.25 4.5 5 5.5 4.75 5 5.25 V
IOH High-level output current −800 −800 −400 −400 µA
IOL Low-level output current 16 16 4 8 mA
TAOperating free-air temperature −55 125 0 70 −55 125 0 70 °C
NOTE 4: All unused inputs of the device must be held at VCC or GND to ensure proper device operation. Refer to the TI application report,
Implications of Slow or Floating CMOS Inputs, literature number SCBA004.
   
    
        
SDLS053B − O C TOBER 1976 − REVISED MAY 2004
8POST OFFICE BOX 655303 • DALLAS, TEXAS 75265
electrical characteristics over recommended operating free-air temperature range (unless
otherwise noted)
PARAMETER
TEST CONDITIONS†
’147 ’148
UNIT
PARAMETER
TEST CONDITIONS†
MIN TYP‡MAX MIN TYP‡MAX
UNIT
VIH High-level input voltage 2 2 V
VIL Low-level input voltage 0.8 0.8 V
VIK Input clamp voltage VCC = MIN, II = −12 mA −1.5 −1.5 V
VOH High-level output voltage VCC = MIN,
VIL = 0.8 V, VIH = 2 V,
IOH = −800 µA2.4 3.3 2.4 3.3 V
VOL Low-level output voltage VCC = MIN,
VIL = 0.8 V, VIH = 2 V,
IOL = 16 mA 0.2 0.4 0.2 0.4 V
IIInput current at maximum input
voltage VCC = MIN, VI = 5.5 V 1 1 mA
High-level input
0 input
VCC = MAX,
VI = 2.4 V
40
A
IIH
High-level input
current Any input except 0 VCC = MAX, VI = 2.4 V 40 80 µA
Low-level input
0 input
VCC = MAX,
VI = 0.4 V
−1.6
mA
IIL
Low-level input
current Any input except 0 VCC = MAX, VI = 0.4 V −1.6 −3.2 mA
IOS Short-circuit output current§VCC = MAX −35 −85 −35 −85 mA
Supply current
VCC = MAX
Condition 1 50 70 40 60
mA
CC
Supply current
VCC = MAX
(See Note 5) Condition 2 42 62 35 55
mA
†For conditions shown as MIN or MAX, use the appropriate value specified under recommended operating conditions.
‡All typical values are at VCC = 5 V, TA = 25°C.
§Not more than one output should be shorted at a time.
NOTE 5: For ’147, ICC (Condition 1) is measured with input 7 grounded, other inputs and outputs open; ICC (Condition 2) is measured with all
inputs and outputs open. For ’148, ICC (Condition 1) is measured with inputs 7 and EI grounded, other inputs and outputs open; ICC
(Condition 2) is measured with all inputs and outputs open.
SN54147, SN74147 switching characteristics, VCC = 5 V, TA = 255C (see Figure 1)
PARAMETER FROM
(INPUT) TO
(OUTPUT) WAVEFORM TEST
CONDITIONS MIN TYP MAX UNIT
tPLH
Any
Any
In-phase output
9 14
ns
tPHL Any Any In-phase output
CL = 15 pF,
711 ns
tPLH
Any
Any
Out-of-phase output
CL = 15 pF,
RL = 400 Ω13 19
ns
tPHL
Any
Any
Out-of-phase output
RL = 400
12 19
ns
   
    
        
SDLS053B − O C TOBER 1976 − REVISED MAY 2004
9
POST OFFICE BOX 655303 • DALLAS, TEXAS 75265
SN54148, SN74148 switching characteristics, VCC = 5 V, TA = 255C (see Figure 1)
PARAMETER†FROM
(INPUT) TO
(OUTPUT) WAVEFORM TEST
CONDITIONS MIN TYP MAX UNIT
tPLH
1–7
A0, A1, or A2
In-phase output
10 15
ns
tPHL 1–7 A0, A1, or A2 In-phase output 9 14 ns
tPLH
1–7
A0, A1, or A2
Out-of-phase output
13 19
ns
tPHL 1–7 A0, A1, or A2 Out-of-phase output 12 19 ns
tPLH
0–7
EO
Out-of-phase output
6 10
ns
tPHL 0–7 EO Out-of-phase output 14 25 ns
tPLH
0–7
GS
In-phase output
CL = 15 pF,
18 30
ns
tPHL 0–7 GS In-phase output
CL = 15 pF,
RL = 400 Ω14 25 ns
tPLH
EI
A0, A1, or A2
In-phase output
RL = 400
10 15
ns
tPHL EI A0, A1, or A2 In-phase output 10 15 ns
tPLH
EI
GS
In-phase output
8 12
ns
tPHL EI GS In-phase output 10 15 ns
tPLH
EI
EO
In-phase output
10 15
ns
tPHL
EI
EO
In-phase output
17 30
ns
†tPLH = propagation delay time, low-to-high-level output.
tPHL = propagation delay time, high-to-low-level output.
electrical characteristics over recommended operating free-air temperature range (unless
otherwise noted)
PARAMETER
TEST CONDITIONS†
SN54LS’ SN74LS’
UNIT
PARAMETER
TEST CONDITIONS†
MIN TYP‡MAX MIN TYP‡MAX
UNIT
VIH High-level input voltage 2 2 V
VIL Low-level input voltage 0.7 0.8 V
VIK Input clamp voltage VCC = MIN, II = −18 mA −1.5 −1.5 V
VOH High-level output voltage VCC = MIN,
VIL = 0.8 V, VIH = 2 V,
IOH = −400 µA2.5 3.4 2.7 3.4 V
Low-level output voltage
VCC = MIN,
VIH = 2 V,
IOL = 4 mA 0.25 0.4 0.25 0.4
V
VOL Low-level output voltage
CC
V
IH
= 2 V,
VIL = VIL MAX IOL = 8 mA 0.35 0.5 V
Input current at
maximum input
’LS148 inputs 1–7
VCC = MAX,
VI = 7 V
0.2 0.2
mA
II
maximum input
voltage All other inputs VCC = MAX, VI = 7 V 0.1 0.1 mA
High-level input
’LS148 inputs 1–7
VCC = MAX,
VI = 2.7 V
40 40
A
IIH
High-level input
current All other inputs VCC = MAX, VI = 2.7 V 20 20 µA
Low-level input
’LS148 inputs 1–7
VCC = MAX,
VI = 0.4 V
−0.8 −0.8
mA
IIL
Low-level input
current All other inputs VCC = MAX, VI = 0.4 V −0.4 −0.4 mA
IOS Short-circuit output current§VCC = MAX −20 −100 −20 −100 mA
Supply current
VCC = MAX
Condition 1 12 20 12 20
mA
CC
Supply current
VCC = MAX
(See Note 6) Condition 2 10 17 10 17
mA
†For conditions shown as MIN or MAX, use the appropriate value specified under recommended operating conditions.
‡All typical values are at VCC = 5 V, TA = 25°C.
§Not more than one output should be shorted at a time.
NOTE 6: For ’LS147, ICC (Condition 1) is measured with input 7 grounded, other inputs and outputs open; ICC (Condition 2) is measured with
all inputs and outputs open. For ’LS148, ICC (Condition 1) is measured with inputs 7 and EI grounded, other inputs and outputs open;
ICC (Condition 2) is measured with all inputs and outputs open.
   
    
        
SDLS053B − O C TOBER 1976 − REVISED MAY 2004
10 POST OFFICE BOX 655303 • DALLAS, TEXAS 75265
SN54LS147, SN74LS147 switching characteristics, VCC = 5 V, TA = 255C (see Figure 2)
PARAMETER FROM
(INPUT) TO
(OUTPUT) WAVEFORM TEST
CONDITIONS MIN TYP MAX UNIT
tPLH
Any
Any
In-phase output
12 18
ns
tPHL Any Any In-phase output
CL = 15 pF,
12 18 ns
tPLH
Any
Any
Out-of-phase output
CL = 15 pF,
RL = 2 kΩ21 33
ns
tPHL
Any
Any
Out-of-phase output
RL = 2 k
15 23
ns
SN54LS148, SN74LS148 switching characteristics, VCC = 5 V, TA = 255C (see Figure 2)
PARAMETER†FROM
(INPUT) TO
(OUTPUT) WAVEFORM TEST
CONDITIONS MIN TYP MAX UNIT
tPLH
1–7
A0, A1, or A2
In-phase output
14 18
ns
tPHL 1–7 A0, A1, or A2 In-phase output 15 25 ns
tPLH
1–7
A0, A1, or A2
Out-of-phase output
20 36
ns
tPHL 1–7 A0, A1, or A2 Out-of-phase output 16 29 ns
tPLH
0–7
EO
Out-of-phase output
7 18
ns
tPHL 0–7 EO Out-of-phase output 25 40 ns
tPLH
0–7
GS
In-phase output
CL = 15 pF,
35 55
ns
tPHL 0–7 GS In-phase output
CL = 15 pF,
RL = 2 kΩ9 21 ns
tPLH
EI
A0, A1, or A2
In-phase output
RL = 2 k
16 25
ns
tPHL EI A0, A1, or A2 In-phase output 12 25 ns
tPLH
EI
GS
In-phase output
12 17
ns
tPHL EI GS In-phase output 14 36 ns
tPLH
EI
EO
In-phase output
12 21
ns
tPHL
EI
EO
In-phase output
23 35
ns
†tPLH = propagation delay time, low-to-high-level output
tPHL = propagation delay time, high-to-low-level output
   
    
        
SDLS053B − O C TOBER 1976 − REVISED MAY 2004
11
POST OFFICE BOX 655303 • DALLAS, TEXAS 75265
PARAMETER MEASUREMENT INFORMATION
SERIES 54/74 DEVICES
tPHL tPLH
tPLH tPHL
LOAD CIRCUIT
FOR 3-STATE OUTPUTS
High-Level
Pulse
Low-Level
Pulse
VOLTAGE WAVEFORMS
PULSE DURATIONS
Input
Out-of-Phase
Output
(see Note D)
3 V
0 V
VOL
VOH
VOH
VOL
In-Phase
Output
(see Note D)
VOLTAGE WAVEFORMS
PROPAGATION DELAY TIMES
VCC
RL
Test
Point
From Output
Under Test
CL
(see Note A)
LOAD CIRCUIT
FOR OPEN-COLLECTOR OUTPUTS
LOAD CIRCUIT
FOR 2-STATE TOTEM-POLE OUTPUTS
(see Note B)
VCC
RL
From Output
Under Test
CL
(see Note A)
Test
Point
(see Note B
)
V
CC RL
From Output
Under Test
CL
(see Note A)
Test
Point
1 kΩ
NOTES: A. CL includes probe and jig capacitance.
B. All diodes are 1N3064 or equivalent.
C. Waveform 1 is for an output with internal conditions such that the output is low, except when disabled by the output control.
Waveform 2 is for an output with internal conditions such that the output is high, except when disabled by the output control.
D. S1 and S2 are closed for tPLH, tPHL, tPHZ, and t PLZ; S1 is open, and S2 is closed for tPZH; S1 is closed, and S2 is open for tPZL
.
E. All input pulses are supplied by generators having the following characteristics: PRR ≤ 1 MHz, ZO ≈ 50 Ω; tr and tf ≤ 7 ns for Serie
s
54/74 devices and tr and tf ≤ 2.5 ns for Series 54S/74S devices.
F. The outputs are measured one at a time, with one input transition per measurement.
S1
S2
tPHZ
tPLZ
tPZL
tPZH
3 V
3 V
0 V
0 V
th
tsu
VOLTAGE WAVEFORMS
SETUP AND HOLD TIMES
Timing
Input
Data
Input
3 V
0 V
Output
Control
(low-level
enabling)
Waveform 1
(see Notes C
and D)
Waveform 2
(see Notes C
and D) ≈1.5 V
VOH − 0.5 V
VOL + 0.5 V
≈1.5 V
VOLTAGE WAVEFORMS
ENABLE AND DISABLE TIMES, 3-STATE OUTPUTS
1.5 V 1.5 V
1.5 V 1.5 V
1.5 V
1.5 V 1.5 V
1.5 V 1.5 V
1.5 V
1.5 V
tw
1.5 V 1.5 V
1.5 V 1.5 V
1.5 V 1.5 V
VOH
VOL
Figure 1. Load Circuits and Voltage Waveforms
   
    
        
SDLS053B − O C TOBER 1976 − REVISED MAY 2004
12 POST OFFICE BOX 655303 • DALLAS, TEXAS 75265
PARAMETER MEASUREMENT INFORMATION
SERIES 54LS/74LS DEVICES
tPHL tPLH
tPLH tPHL
LOAD CIRCUIT
FOR 3-STATE OUTPUTS
High-Level
Pulse
Low-Level
Pulse
VOLTAGE WAVEFORMS
PULSE DURATIONS
Input
Out-of-Phase
Output
(see Note D)
3 V
0 V
VOL
VOH
VOH
VOL
In-Phase
Output
(see Note D)
VOLTAGE WAVEFORMS
PROPAGATION DELAY TIMES
VCC
RL
Test
Point
From Output
Under Test
CL
(see Note A)
LOAD CIRCUIT
FOR OPEN-COLLECTOR OUTPUTS
LOAD CIRCUIT
FOR 2-STATE TOTEM-POLE OUTPUTS
(see Note B)
VCC
RL
From Output
Under Test
CL
(see Note A)
Test
Point
(see Note B
)
V
CC RL
From Output
Under Test
CL
(see Note A)
Test
Point
5 kΩ
NOTES: A. CL includes probe and jig capacitance.
B. All diodes are 1N3064 or equivalent.
C. Waveform 1 is for an output with internal conditions such that the output is low, except when disabled by the output control.
Waveform 2 is for an output with internal conditions such that the output is high, except when disabled by the output control.
D. S1 and S2 are closed for tPLH, tPHL, tPHZ, and t PLZ; S1 is open, and S2 is closed for tPZH; S1 is closed, and S2 is open for tPZL
.
E. Phase relationships between inputs and outputs have been chosen arbitrarily for these examples.
F. All input pulses are supplied by generators having the following characteristics: PRR ≤ 1 MHz, ZO ≈ 50 Ω, tr ≤ 1.5 ns, tf ≤ 2.6 ns
.
G. The outputs are measured one at a time, with one input transition per measurement.
S1
S2
tPHZ
tPLZ
tPZL
tPZH
3 V
3 V
0 V
0 V
th
tsu
VOLTAGE WAVEFORMS
SETUP AND HOLD TIMES
Timing
Input
Data
Input
3 V
0 V
Output
Control
(low-level
enabling)
Waveform 1
(see Notes C
and D)
Waveform 2
(see Notes C
and D) ≈1.5 V
VOH − 0.5 V
VOL + 0.5 V
≈1.5 V
VOLTAGE WAVEFORMS
ENABLE AND DISABLE TIMES, 3-STATE OUTPUTS
1.3 V 1.3 V
1.3 V 1.3 V
1.3 V
1.3 V 1.3 V
1.3 V 1.3 V
1.3 V
1.3 V
tw
1.3 V 1.3 V
1.3 V 1.3 V
1.3 V 1.3 V
VOL
VOH
Figure 2. Load Circuits and Voltage Waveforms
   
    
        
SDLS053B − O C TOBER 1976 − REVISED MAY 2004
13
POST OFFICE BOX 655303 • DALLAS, TEXAS 75265
APPLICATION INFORMATION
01234567EI
EO A0 A1 A2 GS
’148/’LS148
01234567EI
EO A0 A1 A2 GS
’148/LS148
’08/’LS08
01234567 9101112131415 Enable
(active low)
012 3
Encoded Data (active low)
Priority Flag
(active low)
16-Line Data (active low)
01234567EI
EO A0 A1 A2 GS
’148/’LS148
01234567EI
EO A0 A1 A2 GS
’148/’LS148
’HC00
0 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 Enable
(active low)
012 3
Encoded Data (active high)
Priority Flag
(active high)
16-Line Data (active low)
8
Figure 3. Priority Encoder for 16 Bits
Because the ’147/’LS147 and ’148/’LS148 devices are combinational logic circuits, wrong addresses can appear
during input transients. Moreover, for the ’148/’LS148 devices, a change from high to low at EI can cause a transient
low on GS when all inputs are high. This must be considered when strobing the outputs.
PACKAGING INFORMATION
Orderable Device Status (1) Package
Type Package
Drawing Pins Package
Qty Eco Plan (2) Lead/Ball Finish MSL Peak Temp (3)
78027012A ACTIVE LCCC FK 20 1 TBD Call TI Level-NC-NC-NC
7802701EA ACTIVE CDIP J 16 1 TBD Call TI Level-NC-NC-NC
7802701FA ACTIVE CFP W 16 1 TBD Call TI Level-NC-NC-NC
JM38510/36001B2A ACTIVE LCCC FK 20 1 TBD Call TI Level-NC-NC-NC
JM38510/36001BEA ACTIVE CDIP J 16 1 TBD Call TI Level-NC-NC-NC
JM38510/36001BFA ACTIVE CFP W 16 1 TBD Call TI Level-NC-NC-NC
SN54148J OBSOLETE CDIP J 16 TBD Call TI Call TI
SN54LS148J ACTIVE CDIP J 16 1 TBD Call TI Level-NC-NC-NC
SN74147N OBSOLETE PDIP N 16 TBD Call TI Call TI
SN74148J OBSOLETE CDIP J 16 TBD Call TI Call TI
SN74148N OBSOLETE PDIP N 16 TBD Call TI Call TI
SN74148N3 OBSOLETE PDIP N 16 TBD Call TI Call TI
SN74LS147DR OBSOLETE SOIC D 16 TBD Call TI Call TI
SN74LS147N OBSOLETE PDIP N 16 TBD Call TI Call TI
SN74LS148D ACTIVE SOIC D 16 40 Green (RoHS &
no Sb/Br) CU NIPDAU Level-1-260C-UNLIM
SN74LS148DE4 ACTIVE SOIC D 16 40 Green (RoHS &
no Sb/Br) CU NIPDAU Level-1-260C-UNLIM
SN74LS148DR ACTIVE SOIC D 16 2500 Green (RoHS &
no Sb/Br) CU NIPDAU Level-1-260C-UNLIM
SN74LS148DRE4 ACTIVE SOIC D 16 2500 Green (RoHS &
no Sb/Br) CU NIPDAU Level-1-260C-UNLIM
SN74LS148J OBSOLETE CDIP J 16 TBD Call TI Call TI
SN74LS148N ACTIVE PDIP N 16 25 Pb-Free
(RoHS) CU NIPDAU Level-NC-NC-NC
SN74LS148N3 OBSOLETE PDIP N 16 TBD Call TI Call TI
SN74LS148NE4 ACTIVE PDIP N 16 25 Pb-Free
(RoHS) CU NIPDAU Level-NC-NC-NC
SN74LS148NSR ACTIVE SO NS 16 2000 Green (RoHS &
no Sb/Br) CU NIPDAU Level-1-260C-UNLIM
SN74LS148NSRE4 ACTIVE SO NS 16 2000 Green (RoHS &
no Sb/Br) CU NIPDAU Level-1-260C-UNLIM
SNJ54148J OBSOLETE CDIP J 16 TBD Call TI Call TI
SNJ54148W OBSOLETE CFP W 16 TBD Call TI Call TI
SNJ54LS148FK ACTIVE LCCC FK 20 1 TBD Call TI Level-NC-NC-NC
SNJ54LS148J ACTIVE CDIP J 16 1 TBD Call TI Level-NC-NC-NC
SNJ54LS148W ACTIVE CFP W 16 1 TBD Call TI Level-NC-NC-NC
(1) The marketing status values are defined as follows:
ACTIVE: Product device recommended for new designs.
LIFEBUY: TI has announced that the device will be discontinued, and a lifetime-buy period is in effect.
NRND: Not recommended for new designs. Device is in production to support existing customers, but TI does not recommend using this part in
a new design.
PREVIEW: Device has been announced but is not in production. Samples may or may not be available.
OBSOLETE: TI has discontinued the production of the device.
(2) Eco Plan - The planned eco-friendly classification: Pb-Free (RoHS) or Green (RoHS & no Sb/Br) - please check
PACKAGE OPTION ADDENDUM
www.ti.com 26-Sep-2005
Addendum-Page 1
http://www.ti.com/productcontent for the latest availability information and additional product content details.
TBD: The Pb-Free/Green conversion plan has not been defined.
Pb-Free (RoHS): TI's terms "Lead-Free" or "Pb-Free" mean semiconductor products that are compatible with the current RoHS requirements
for all 6 substances, including the requirement that lead not exceed 0.1% by weight in homogeneous materials. Where designed to be soldered
at high temperatures, TI Pb-Free products are suitable for use in specified lead-free processes.
Green (RoHS & no Sb/Br): TI defines "Green" to mean Pb-Free (RoHS compatible), and free of Bromine (Br) and Antimony (Sb) based flame
retardants (Br or Sb do not exceed 0.1% by weight in homogeneous material)
(3) MSL, Peak Temp. -- The Moisture Sensitivity Level rating according to the JEDEC industry standard classifications, and peak solder
temperature.
Important Information and Disclaimer:The information provided on this page represents TI's knowledge and belief as of the date that it is
provided. TI bases its knowledge and belief on information provided by third parties, and makes no representation or warranty as to the
accuracy of such information. Efforts are underway to better integrate information from third parties. TI has taken and continues to take
reasonable steps to provide representative and accurate information but may not have conducted destructive testing or chemical analysis on
incoming materials and chemicals. TI and TI suppliers consider certain information to be proprietary, and thus CAS numbers and other limited
information may not be available for release.
In no event shall TI's liability arising out of such information exceed the total purchase price of the TI part(s) at issue in this document sold by TI
to Customer on an annual basis.
PACKAGE OPTION ADDENDUM
www.ti.com 26-Sep-2005
Addendum-Page 2
MECHANICAL DATA
MLCC006B – OCTOBER 1996
POST OFFICE BOX 655303 • DALLAS, TEXAS 75265
FK (S-CQCC-N**) LEADLESS CERAMIC CHIP CARRIER
4040140/D 10/96
28 TERMINAL SHOWN
B
0.358
(9,09)
MAX
(11,63)
0.560
(14,22)
0.560
0.458
0.858
(21,8)
1.063
(27,0)
(14,22)
A
NO. OF
MINMAX
0.358
0.660
0.761
0.458
0.342
(8,69)
MIN
(11,23)
(16,26)
0.640
0.739
0.442
(9,09)
(11,63)
(16,76)
0.962
1.165
(23,83)
0.938
(28,99)
1.141
(24,43)
(29,59)
(19,32)(18,78)
**
20
28
52
44
68
84
0.020 (0,51)
TERMINALS
0.080 (2,03)
0.064 (1,63)
(7,80)
0.307
(10,31)
0.406
(12,58)
0.495
(12,58)
0.495
(21,6)
0.850
(26,6)
1.047
0.045 (1,14)
0.045 (1,14)
0.035 (0,89)
0.035 (0,89)
0.010 (0,25)
12
1314151618 17
11
10
8
9
7
5
432
0.020 (0,51)
0.010 (0,25)
6
12826 27
19
21
B SQ
A SQ 22
23
24
25
20
0.055 (1,40)
0.045 (1,14)
0.028 (0,71)
0.022 (0,54)
0.050 (1,27)
NOTES: A. All linear dimensions are in inches (millimeters).
B. This drawing is subject to change without notice.
C. This package can be hermetically sealed with a metal lid.
D. The terminals are gold plated.
E. Falls within JEDEC MS-004
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