Decembe r 2003 i
© 20 03 Act el Corporat ion
ProASICPLUS Flash Fami ly FPGAs
Features and Benefits
High Capa city
• 75,000 to 1 m illion Sys tem Gates
• 27k to 198kbits of Two-Port SRAM
• 66 to 712 User I/ Os
Reprogrammable Flash Technology
•0.22µ 4L M F las h- bas ed CM OS Pro cess
• Live at Power-Up, Single-C hi p Solution
• No Co nf iguration De v ic e R equ i re d
• Retains Programmed Design during Power-Down/Power-Up Cycles
Performance
• 3.3V, 32-bit PCI (up to 50 MH z)
• Two In tegrate d PLLs
• Exter na l Sys tem Pe rf orma nc e u p to 150 MH z
Secure Programming
• The Industry’s Most Effective Security Key (FlashLock)
Preve nts R ead Ba ck of Pr og ra mming B its tream
Low Pow er
• Low Impedance Flash Switches
• Segm ent ed Hier arch ical R ou ting St r uct ur e
• Small, E ffic ient, Config urable (Com binatorial or Sequentia l)
Logic Cells
High Pe r f orm a nce Rout ing Hier a rchy
• Ultra-Fas t Local a nd Long-Line Network
• High Sp eed Very Lon g-Li ne Ne tw ork
• Hig h P e rfor m anc e, L ow Skew, S plit t able Global N et wo rk
• 100% Rou tability an d Utilizat io n
I/O
• Schmitt- Trigge r Opt ion on Ever y In put
• 2.5V/3.3V Support with Individually-Selectable Voltage and
Slew Rate
• Bidirect ional Glo bal I/Os
• Complia nce wit h PCI Sp ec ificatio n Revis ion 2.2
• Bou nd ary-Sc an Test IEE E St d. 1 149.1 (J TAG) Com plia nt
• Pin C ompat ible Pack age s a cross ProA SICPLUS Family
Unique Clock Conditi oning Circuitry
• PLL with Flexible Phase, Multiply/Divide and Delay
Capabilit ies
• Internal and/or External Dynamic PLL Configuration
• Two LVPECL Differential Pairs for Clock or Data Inputs
Standard FPGA and ASIC Design Flow
• Flexibili ty w ith Choice of Indust ry - S ta nd ard F r on ten d Tools
• Efficient Design through Frontend Timing and Gate Optimization
ISP Support
• In-System Programming (ISP) via JT AG Port
SRAM s and FI FO s
• ACTgen Netlist Generation Ensures Optimal Usage of
Emb edded Memo ry Block s
• 24 SRAM and FIFO Configurations with Synchronous and
Asynchrono us Operat ion u p to 150 MHz (typic al)
TM
Table 1 • ProASICPLUS Product Profile
Device APA075 APA150 APA300 APA450 APA600 APA750 APA1000
Maximum System Gates 75,000 150,000 300,000 450,000 600,000 750,000 1,000,000
Maximum Tiles (Registe rs) 3,072 6,144 8,192 12,288 21,504 32,768 56,320
Embedded RAM Bits (k=1,024
bits) 27k 36k 72k 108k 126k 144k 198k
Embedded RAM Blocks (256x9) 12 16 32 48 56 64 88
LVPECL 222 2 2 22
PLL 222 2 2 22
Global Networks 444 4 4 44
Max imum Clocks 24 32 32 48 56 64 88
Maximum User I/Os 158 242 290 344 454 562 712
JTAG ISP Yes Yes Yes Yes Yes Yes Yes
PCI Yes Yes Yes Yes Yes Yes Yes
Package (by pin coun t)
TQFP 100, 144 100 – – – – –
PQFP 208 208 208 208 208 208 208
PBGA – 456 456 456 456 456 456
FBGA 144 144, 256 144, 256 144, 256, 484 256, 484, 676 676, 896 896, 1152
v3.4
ProASICPLUS Flash Family FPGAs
i-ii v3.4
Ordering Information
Plas ti c D evice Resources
General Guideline
Maximum performance numbers in this datasheet are based on characterized data. Actel does not guarantee
perform anc e bey ond the limits specifi ed withi n the data she et .
User I/Os*
Device TQFP
100-Pin TQFP
144-Pin PQFP
208-Pin PBGA
456-Pin FBGA
144-Pin FBGA
256-Pin FBGA
484-Pin FBGA
676-Pin FBGA
896-Pin FBGA
1152-Pin
APA075 66 107 158 100
APA150 66 158 242 100 186
APA300 158 290 100 186
APA450 158 344 100 186 344
APA600 158 356 186 370 454
APA750 158 356 454 562
APA1000 158 356 642 712
Package Definitions
TQFP = Thin Quad Flat Pack, PQFP = Plastic Quad Flat Pack, PBGA = Plastic Ball Grid Array, FBGA = Fine Pitch Ball Grid Array
*Each pair of PEC L I/Os were counted as one user I/O.
APA1000 FG
_
Part Number
Speed Grade
Blank =Standard Speed
F
F
= 20% Slower than Standard
Package Type
PQ =Plastic Quad Flat Pack (0.5mm pitch)
TQ =Thin Quad Flat Pack (1.4mm pitch)
FG =Fine Pitch Ball Grid Array (1.0mm pitch)
BG =Plastic Ball Grid Array (1.27mm pitch)
1152 I
Package Lead Count
Application (Ambient Temperature Range)
Blank = Commercial (0 to +70˚ C)
I = Industrial (-40 to +85˚ C)
PP = Pre-production
ES = Engineering Silicon (Room Temperature Only)
150,000 Equivalent System GatesAPA150 = 75,000 Equivalent System GatesAPA075 =
APA450
APA600
APA750
APA1000
450,000 Equivalent System Gates
600,000 Equivalent System Gates
750,000 Equivalent System Gates
1,000,000 Equivalent System Gates
APA300 300,000 Equivalent System Gates=
=
=
=
=
ProASICPLUS Flash Family FP G As
v3.4 i-iii
Product Availability
Spe ed Gr ad e App l ica ti on
Std. –F* C I
APA075 Device
100-Pin Thin Quad Flat Pack (TQFP) ✔✔ ✔ ✔
144-Pin Thin Quad Flat Pack (TQFP) ✔✔ ✔ ✔
208-Pin Plastic Quad Flat Pack (PQFP) ✔✔ ✔ ✔
144-Pin Fine Pitch Ball Grid Array (FBGA) ✔✔ ✔ ✔
APA150 Device
100-Pin Thin Quad Flat Pack (TQFP) ✔✔ ✔ ✔
208-Pin Plastic Quad Flat Pack (PQFP) ✔✔ ✔ ✔
456-Pin Plastic Ball Grid Array (PBGA) ✔✔ ✔ ✔
144-Pin Fine Pitch Ball Grid Array (FBGA) ✔✔ ✔ ✔
256-Pin Fine Pitch Ball Grid Array (FBGA) ✔✔ ✔ ✔
APA300 Device
208-Pin Plastic Quad Flat Pack (PQFP) ✔✔ ✔ ✔
456-Pin Plastic Ball Grid Array (PBGA) ✔✔ ✔ ✔
144-Pin Fine Pitch Ball Grid Array (FBGA) ✔✔ ✔ ✔
256-Pin Fine Pitch Ball Grid Array (FBGA) ✔✔ ✔ ✔
APA450 Device
208-Pin Plastic Quad Flat Pack (PQFP) ✔✔ ✔ ✔
456-Pin Plastic Ball Grid Array (PBGA) ✔✔ ✔ ✔
144-Pin Fine Pitch Ball Grid Array (FBGA) ✔✔ ✔ ✔
256-Pin Fine Pitch Ball Grid Array (FBGA) ✔✔ ✔ ✔
484-Pin Fine Pitch Ball Grid Array (FBGA) ✔✔ ✔ ✔
APA600 Device
208-Pin Plastic Quad Flat Pack (PQFP) ✔✔ ✔ ✔
456-Pin Plastic Ball Grid Array (PBGA) ✔✔ ✔ ✔
256-Pin Fine Pitch Ball Grid Array (FBGA) ✔✔ ✔ ✔
484-Pin Fine Pitch Ball Grid Array (FBGA) ✔✔ ✔ ✔
676-Pin Fine Pitch Ball Grid Array (FBGA) ✔✔ ✔ ✔
APA750 Device
208-Pin Plastic Quad Flat Pack (PQFP) ✔✔ ✔ ✔
456-Pin Plastic Ball Grid Array (PBGA) ✔✔ ✔ ✔
676-Pin Fine Pitch Ball Grid Array (FBGA) ✔✔ ✔ ✔
896-Pin Plastic Ball Grid Array (FBGA) ✔✔ ✔ ✔
APA1000 Device
208-Pin Plastic Quad Flat Pack (PQFP) ✔✔ ✔ ✔
456-Pin Plastic Ball Grid Array (PBGA) ✔✔ ✔ ✔
896-Pin Fine Pitch Ball Grid Array (FBGA) ✔✔ ✔ ✔
1152-Pin Fine Pitch Ball Grid Array (FBGA) ✔✔ ✔ ✔
Notes:
*–F parts are only available as commercial temperature devices.
Applications: C = Commercial Availability: ✔=Available
I = Industrial PP=Product Planned
iv v3.4
Table of Co ntents
ProASICPLUS Flash Family FPGAs
General Guideline . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . ii
General Description
ProASICPLUS Architecture . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 2
Timing Control and Characteri stics . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 11
Sample Implementations . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 15
Adjust a b le Clock D e lay . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 15
Clock Skew Minimization . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 15
PLL Electrical Specifications . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 19
Design Environment . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 24
ISP . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 25
Related Documents . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 26
Pac k a g e T h e rmal Characteristics . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 27
Cal c u lating Typ ical Power Di ssipation . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 28
Operating Conditions . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 30
Tri st a te B u ff e r D e la y s . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 37
Input Buf fer Delays . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 39
Global Input Buffer Delays . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 40
Predi cted Global Routing Delay . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 40
Global Routing Skew . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 40
Module Delays . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 41
Sample Macrocell Lib rary Listin g . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 41
Emb e d d e d Me mory Spe cific a ti on s . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 43
Pin Des crip ti o n . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 63
Recommended Design Practice for VPN/VPP . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 64
Package Pin Assignments
100-Pin TQFP . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 1
14 4- P in TQ FP . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 3
45 6- P in PBG A . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 12
14 4- P in FB GA . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 27
25 6- P in FB GA . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 30
48 4- P in FB GA . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 35
67 6- P in FB GA . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 41
89 6- P in FB GA . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 49
1152-Pin FBGA . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 59
Lis t o f C han g e s . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 1
Data Sheet Categories . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 7
ProASICPLUS Flash Family FP G As
v3.4 1-1
General Descriptio n
The ProASICPLUS family of devices, Actel’s second
generation Flash FPGAs, offers enhanced performance
over Actel’s ProASIC family. It combines the advantages
of ASICs with the benefits of programmable devices
through nonvolatile Flash technology. This enables
engineers to create high-density systems using existing
ASIC or FPGA design flows and tools. In addition, the
ProASICPLUS family offers a unique clock conditioning
circuit based on two on-b oard phas e-locked lo ops (PLLs).
The fam i ly offers up to 1 m illi o n syste m gates, supp/
+;,llorted with up to 198kbits of two-port SRAM and up
to 712 user I/Os, all providing 5 0 MHz PCI performance.
Advantages to the designer extend beyond
performance. Unlike SRAM-based FPGAs, four levels of
routing hi era rc hy simplify r out in g, w hi le th e use of Fl as h
technology allows all functionality to be live at power-
up. No exte rna l Bo ot P ROM is required to s upport device
programming. While on-board security mechanisms
prevent all access to the program information,
reprogramming can be performed in-system to support
future design iterat ions and f ield upgrad es. The de vice’s
architecture mitigates the complexity of ASIC migration
at higher user volume. This makes ProASICPLUS a cost-
effective solution for applications in the networking,
communications, computing, and avionics markets.
The ProASICPLUS family achieves its nonvolatility and
reprogrammability through an advanced Flash-based
0.22µm LVCMOS process with four-layers of metal.
Standard CMOS design techniques are used to
implement logic and control functions, including the
PLLs and LVPECL inputs. This results in predictable
per forman ce fu ll y comp a ti b l e w ith gat e arrays.
The ProASICPLUS architecture provides granularity
comparable to gate arrays. The device core consists of a
Sea-of-Tiles. Each tile can be configured as a flip-flop,
latch, or three-input/one-output logic function by
programming the appropriate Flash switches. The
combination of fine granularity, flexible routing
resources, and abundant Flash switches allow 100%
utilization and over 95% routability for highly congested
designs. Tiles and larger functions are interconnected
through a four-level rou ting hi er archy.
Embedded two-port SRAM blocks with built-in FIFO/RAM
control logic can have user-defined depth and width.
Users can also select programming for synchronous or
asynch ronous o perat ion, as we ll as parity gene rations or
checking.
The unique clock conditioning circuitry in each device
includes two clock conditioning blocks. Each block
provides a PLL core, delay lines, phase shifts (0°, 90°,
180°, 270°), and clock multipliers/dividers, as well as the
circuitry needed to provide bidirectional access to the
PLL. The PLL block contains four programmable
frequency dividers, which allow the incoming clock
signal to be divid ed by a wide range of fact ors from 1 to
64. The clo ck conditioning circuit also del ays or advan ces
the incom ing refer ence clock up to 8 ns (in increments of
0.25 ns). The PLL can be configured internally or
externally during operation without redesigning or
reprogramming the part. In addition to the PLL, there
are two LVPEC L differential input pairs to accommodate
high speed cloc k and data inputs.
To support customer needs for more comprehensive,
lower cost board-level testing, Actel’s ProASICPLUS
devices are fully compatible with IEEE Standard 1149.1
for test access port and bound ary-scan test architecture.
For more information concerning the Flash FPGA
implementation, please refer to the "Boundary Scan
(JTAG)" on pa ge 1-10.
ProASICPLUS devices are available in a variety of high-
performance plastic packages. Those packages and the
performance features discussed above are described in
mo re detail in the foll o wing sect ions.
ProASICPLUS Flash Family FPGAs
1-2 v3.4
ProASICPLUS Archite cture
The proprietary ProASICPLUS architecture provides
gra n u l a r ity co mpara b l e to gate arrays.
The ProASICPLUS device core consists of a Sea-of-Tiles™
(Figure 1-1). Each tile can be configured as a three-i nput
logic function (e.g., NAND gate, D-Flip-Flop, etc.) by
programming the appropriate Flash switch
interconnections (Figure 1-2 on page 1-3 and Figure 1-3
on page 1-3). Tiles and larger functions are connected
with any of the four levels of routing hierarchy. Flash
switches are distributed throughout the device to
provide nonvolatile, reconfigurable interconnect
programming. Flash switches are programmed to
connect signal lines to the appropriate logic cell inputs
and outputs. Dedicated high-performance lines are
connected as needed for fast, low-skew global signal
distribution throughout the core. Maximum core
utilization is possible for virtually any design.
ProASICPLUS devices also contain embedded two-port
SRAM blocks with built-in FIFO/RAM control logic.
Programming options include synchronous or
asynchronous operation, two-port RAM configurations,
user defined depth and width, and parity generation or
checking. Please see the "Embedded Memory
Configur ations " on pa ge 1-20 for more inf o rmation.
Flash Switch
Unlik e SRAM FPGA s, Pr oA SI CPLUS uses a live o n pow er-up
ISP Flash sw itc h as its program m i ng el em ent .
In the ProASICPLUS Flash switch, two transistors share the
floating gate, which stores the programming
information. One is the sensing transistor, which is only
used for writing and verification of the floating gate
voltage. The other is the switching transistor. It can be
used in the architecture to connect/separate routing nets
or to con figure lo gic. It is also used to eras e the floatin g
gate (Figu re 1-2 o n page 1-3).
Logic Tile
The logic tile cell (Figure 1-3 on page 1-3) has three
inputs (any or all of which can be inverted) and one
output (which can connect to both ultra-fast local and
efficient long-line routing resources). Any three-input,
one-output logic function (except a three-input XOR) can
be confi gure d as one tile. The tile c an be configured as a
latch with clear or set or as a flip-flop with clear or set.
Thus, the tiles can flexibly map logic and sequential gates
of a design.
Figure 1-1 • The ProASICPLUS Device Architecture
256x9 Two-Port SRAM
or FIFO Block
Logic Tile
256x9 Two Port SRAM
or FIFO Block
RAM Block
RAM Block
I/Os
ProASICPLUS Flash Family FP G As
v3.4 1-3
Routing Resources
The routing structure of ProASICPLUS devices is designed
to provide high performance through a flexible four-
level hierarchy of routing resources: ultra-fast local
resources, efficient long-line resources, high speed very
long-line resources, and high performance global
networks.
The ultra-fast local resources are dedicated lines that
allow the output of each tile to con nect directly to ev ery
input of the eight surrounding tiles (Figure 1-4 on page
1-4).
The efficient long-line resources provide routing for
longer distances and higher fanout connections. These
resources vary in length (spanning 1, 2, or 4 tiles), run
both vertically and horizontally, and cover the entire
ProASICPLUS devi ce (Figure 1-5 on pa ge 1- 4). Each tile can
drive signals onto the efficient long-line resources, which
can in turn, access every input of every tile. Active buffers
are inserted automatically by routing software to limit
th e lo adi n g e ffects d u e to dis tance a nd fanout.
The high-speed very long-line resources, which span the
entire device with minimal delay, are used to route very
long or very hi gh fanout nets. (Figure 1-6 on pa g e 1- 5).
The high-performance global networks are low skew,
high fanout nets that are accessible from external pins or
from internal logic (Figure 1-7 on page 1-6). These nets
are typically used to distribute clocks, resets, and other
high fanout nets requiring a minimum skew. The global
networ ks are imple m ent ed as clock trees , and signals can
be introduced at any junction. These can be employed
hierarchically with signals accessing every input on all
tiles.
Figure 1-2 • Flash Switch
Figure 1-3 • Core Logic Tile
Sensing Switching
Switch In
Switch Out
Word
Floating Gate
Local Routing
In 1
In 2 (CLK)
In 3 (Reset)
Efficient Long-Line Routing
ProASICPLUS Flash Family FPGAs
1-4 v3.4
Figure 1-4 • Ultra-Fast Local Resources
Figure 1-5 • Efficient Long-Line Resources
L
LL
LL
L
Inputs
Output
Ultra-Fast
Local Lines
(connects a tile to the
adjacent tile, I/O buffer,
or memory block)
LLL
LL LLLL
LLLLLL
LL LLLL
LL LLLL
LL LLLL
Logic Cell
Spans 1 Tile
Spans 2 Tiles
Spans 4 Tiles
Spans 1 Tile
Spans 2 Tiles
Spans 4 Tiles
Logic Tile
ProASICPLUS Flash Family FP G As
v3.4 1-5
Clock Resources
The ProASICPLUS family offers powerful and flexible
control of circuit timing through the use of analog
circuitry. Each chip has two clock conditioning blocks
containing a phase-locked loop (PLL) core, delay lines,
phase shifter (0°, 90°, 180°, 270°), clock multiplier/
dividers and all the circuitry needed for the selection and
interconnection of inputs to the global network (thus
providing bidirectional access to the PLL). This permits
the PLL block to drive inputs and/or outputs via the two
global lines on each side of the chip (four total lines).
This circuitry is discussed in more detail in the
"ProASI CPLUS Clock Management System" on page 1-11.
Clock Trees
One of the main architectural benefits of ProASICPLUS is
the set of power and delay friendly global networks.
ProASICPLUS offers four global trees. Each of these trees
is based on a network of spines and ribs that reach all
the tiles in their regions (Figure 1-7 on page 1-6). This
flexib le clock tre e archit ectur e allows us ers to ma p up to
88 different internal/external clocks in an APA1000
device. Details on the clock spines and various numbers
of the fam ily ar e given in Table 1-1 on page 1-6.
The flexib l e use of th e ProASI CPLUS clock spine allows th e
designer to cope w ith sever al de sign r equi r ement s. Us ers
implementing clock-resource intensive applications can
easily route external or gated internal clocks using global
routing spines. Users can also drastically reduce delay
penalties and save buffering resources by mapping
critical high-fanout nets to spines. For design hints on
using these features, refer to Actel’s Efficient Use of
ProASIC Clock Trees ap plic ation note.
Figure 1-6 • High Speed Very Long-Line Resources
PAD RING
PAD RING
PAD RING
I/O RING
I/O RING
High Speed Very Long-Line Resouces
SRAM
SRAM
ProASICPLUS Flash Family FPGAs
1-6 v3.4
Array Coordinates
During many place-and-route operations in Actel’s
Designer software tool, it is possible to set constraints
tha t requi re arra y coordinates.
Table 1-2 on page 1- 7 is provided as a referenc e. The array
coordinates are measured from the lower left (0,0). They
can be used in region constraints for specific groups,
designated by a wildcard, and containing core cells, I/Os,
and memories.
I/O and cell coordinates are used for placement
constraint s. Two coordinate systems a re ne eded beca use
there is not a one-to-one correspondence between I/O
cells and co re cells. In addition, t he I/O coord in ate s ys te m
change s depe nding on the die/package combinatio n.
Core cell coordinates start at the lower left corner (1,1)
or (1,5) if memories are present at the bottom. Memory
coordinates use the same system and are indicated in
Table 1-2 on page 1-7. The memory coordinates for an
APA1000 are illustrated in Figure 1-8 on page 1-7. For
more information on how to use constraints, see the
Designer User’s Guide or online help for ProASICPLUS
software tools.
Note: This figure shows routing for only one global path.
Figure 1-7 • High Performance Global Network
Table 1-1 • Clock Spines
APA075 APA150 APA300 APA450 APA600 APA750 APA1000
Global Clock Networks (Trees) 4444444
Clock Spines/Tree 6 8 8 12 14 16 22
Total Spines 24 32 32 48 56 64 88
Top or Bottom Spine Height (Tiles) 16243232486480
Tiles in Each Top or Bottom Spine 512 768 1,024 1,024 1,536 2,048 2,560
Total Tiles 3,072 6,144 8,192 12,288 21,504 32,768 56,320
Top Spine
Bottom Spine
Global
Pads Global
Pads
Global Networks
Global Spine
Global Ribs
High Performace
Global Network
Scope of Spine
(Shaded area
plus local RAMs
and I/Os)
PAD RING
PAD RING
PAD RING
I/O RING
I/O RING
ProASICPLUS Flash Family FP G As
v3.4 1-7
Table 1-2 • Array Coordinates
Device
Logic Tile Memory Rows AllMin. Max. Bottom Top
x y x y y y Min. Max.
APA075 1 1 96 32 – (33,33) or (33, 35) 0,0 97, 37
APA150 1 1 12 8 48 – (49,49) or (49, 51) 0,0 129, 53
APA300 1 5 128 68 (1,1) or (1,3) (69,69) or (69, 71) 0,0 129, 73
APA450 1 5 192 68 (1,1) or (1,3) (69,69) or (69, 71) 0,0 193, 73
APA600 1 5 224 100 (1,1) or (1,3) (101,101) or (101, 103) 0,0 225, 105
APA750 1 5 256 132 (1,1) or (1,3) (133,133) or (133, 135) 0,0 257, 137
APA1000 1 5 352 164 (1,1) or (1,3) (165,165) or (165, 167) 0,0 353, 169
Figure 1-8 • Core Cell Coordinates for the APA1000
(353,169)
(352,167)
(352,165)
(352,164)
(352,5)
(352,3)
(353,0)
(352,1)
(1,5)
(1,1)
(1,164)
(1,165)
(1,3)
(1,167)
(1,169)
(0,0)
Core
Memory
Blocks
Memory
Blocks
ProASICPLUS Flash Family FPGAs
1-8 v3.4
Input/Output Blocks
To meet complex system demands, the ProASICPLUS
family offers devices with a large number of user I/O
pins, up to 712 on the APA1000. If the I/O pad power
supply (VDDP) is 3.3V, each I/O can be selectively
configured at the 2.5V and 3.3V threshold levels1.
Table 1-3 shows the available supply voltage
configurations (the PLL block uses an independent 2.5V
supply o n the AVDD and AGND pins). All I/Os include ESD
protection circuits. Each I /O has been tested to 2000V t o
the human body model (pe r JESD22 (HBM ) ).
Six or seven standard I/O pads are grouped with a GND
pad and either a VDD (core power) or VDDP (I/O power)
pad. Two reference bias signals circle the chip. One
protects the cascaded output drivers, while the other
creates a virtual VDD supply for the I/O ring.
I/O pads are fully configurable to provide the maximum
flexibility and speed. Each pad can be configured as an
input, an output, a tristate driver, or a bidirectional
buffer (Figure 1-9 and Table 1-4).
Table 1-3 • ProASICPLUS I/O Power Supply Voltages
VDDP
2.5V 3.3V
Input Compatibility 2.5V 3.3V, 2.5V
Output Driv e 2.5V 3.3V, 2.5V1
Note: VDD is always 2.5V.
1. Please refer to the mixed-mode interfacing section in the I/O
Features in ProASICPLUS Flash FPGAs application note for
details.
Figure 1-9 • I/O Block Schematic Representation
3.3V/2.5V
Signal Control
Pull-up
Control
Pad
Y
EN
A
3.3V/2.5V Signal Control Drive
Strength and Slew-Rate Control
Table 1-4 • I/O Features
Function Description
I/O pads configured as inputs • Individually selectable 2.5V or 3.3V threshold levels
• Optional pull-up resistor
• Optionally configurable as Schmitt trigger input. The Sc hmitt trigger input option can be
configured as an input only, not a bidirectional buffer. This input type may be slower than
a standard input under certain conditions and has a typical hysteresis of 0.35V. I/O macros
with an “S” in the standard I/O library have added Schmitt capabili ties.
• 3.3V PCI Compliant
I/O pads configured as outputs • Individually selectable 2.5V or 3.3V compliant output signals
• 2.5V – JEDEC JESD 8-5
• 3.3V – JEDEC JESD 8-A (LVTTL and LVCMOS)
• 3.3V PCI compliant
• Ability to drive LVTTL and LVCMOS levels
• Selectable drive strengths
• Selectable slew rates
• Tristate
I/O pads configured as bidirectional
buffers • Individually selectable 2.5V or 3.3V compliant output signals
• 2.5V – JEDEC JESD 8-5
• 3.3V – JEDEC JESD 8-A (LVTTL and LVCMOS)
• 3.3V PCI compliant
• Optional pull-up resistor
• Selectable drive strengths
• Selectable slew rates
• Tristate
ProASICPLUS Flash Family FP G As
v3.4 1-9
Power-Up Sequencing
While ProASICPLUS dev ic es ar e li ve at pow er - up , th e o rd er
of VDD and VDDP power-up is important during system
start-up. VDD should be powered up before (or
coincident with) VDDP on ProASICPLUS devices. Failure to
follow these guidelines may result in undesirable pin
behavior during system start-up. For more information,
refer to Actel’s ProASICPLUS Family Devices Power-Up
Behavior application note.
LVPECL Input Pads
In addition to standard I/O pads and power pads,
ProASICPLUS devices have a single LVPECL input pad on
both the east and west sides of the device, along with
AVDD and AGND pins to power the PLL block. The
LVPECL pad cell consists of an in put buffer (containing a
low voltage differential amplifier) and a signal and its
complement, PPECL (I/P) (PECLN) and NPECL (PECLREF).
The LVPECL input pad cell differs from the standard I/O
cell in that it is operated from VDD only.
Since it is exclusively an input, it requires no output
signal, output enable signal, or output configuration
bits. As a special high-speed differential input, it also
does not require pull ups. Recommended termination for
LVPECL inputs is shown in Figure 1-10. The LVPECL pad
cell compares voltages, as illustrated in Figure 1-11, on
the PPECL (I/P) pad and the NPECL pad and sends the
results to the global MUX (Figure 1-14 on page 1-13).
This high spe ed, l ow sk ew out put ess ent ial ly controls the
clock conditioning circuit.
LVPECLs are designed to meet LVPECL JEDEC receiver
standard levels (Table 1-5).
Figure 1-10 • Recommended Termination for LVPECL Inputs
Figure 1-11 • LVPECL High and Low Threshold Values
Table 1-5 • LVPECL Receiver Specifications
Symbol Parameter Min. Max Units
VIH Input High Voltage 1.49 2.72 V
VIL Input Low Voltage 0.86 2.125 V
VID Differential Input Voltage 0.3 VDD V
+
_
PPECL
NPECL
From LVPECL Driver Data
Z = 50Ω
0
Z = 50Ω
0
R = 100Ω
2.72
2.125
1.49
0.86
Voltage
ProASICPLUS Flash Family FPGAs
1-10 v3.4
Boundary Scan (JTAG)
ProASICPLUS devices are compatible with IEEE Standard
1149. 1, w h ich defines a set of har dw ar e architec ture and
mechanisms for cost-effective board-level testing. The
basic ProASICPLUS boundary-scan logic circuit is composed
of the TAP (test access port), TAP controller, test data
registers, and instruction register (Figure 1-12). This
circuit supports all mandatory IEEE 1149.1 instructions
(EXTEST, SAMPLE/PRELOAD and BYPASS) and the
optional IDCODE instruction (Table 1-6).
Each test section is accessed through the TAP, which has
five associated pins: TCK (test clock input), TDI an d TDO
(test data input and output), TMS (test mode selector)
and TRST (test reset input). TMS, TDI and TRST are
equipped with pull-up resistors to ensure proper
operation w hen no i nput data is supplied to them . Thes e
pins are dedicated for boundary-scan test usage. Actel
recommends that a nominal 20kΩ pull-up resistor is
added to TD O and TCK pins .
The TAP contr oller is a four-bit sta te machi ne (16 states)
that op erates as show n in Figure 1 -13 on page 1-11. Th e
’1’s and ‘0’s represe nt the value s that must be prese nt at
TMS at a rising edge of TCK for the given stat e trans itio n
to occur. IR and DR indicate that the instruction register
or the data regi ster is ope ra ting in that state .
ProASICPLUS devices have to be programmed at least
once for complete boundary-scan functionality to be
availab le . If boundary-sca n fu nct io nal i ty is re qui red prior
to part ial pr ogra mming, re fer to online technical support
on the Actel web site and se arch for Pro A SICPLUS BSDL .
The TAP controller receives t wo contro l input s (TMS an d
TCK) a nd gener ates con trol and clock sign als for the rest
of the test logic architecture. On power-up, the TAP
controller enters the Test-Logic-Reset state. To guarantee
a reset of the controller from any of the possible states,
TMS must remain high for five TCK cycles. The TRST pin
may also be used to asynchronously place the TAP
controller in the Test-Logic-Reset sta te.
ProASICPLUS devices support three types of test data
registers: bypass, device identification, and boundary
Figure 1-12 • ProASICPLUS JTAG Boundary Scan Test Logic Circuit
Device
Logic
TDI
TCK
TMS
TRST
TDO
I/OI/OI/O I/OI/O
I/OI/OI/O I/OI/O
I/O
I/O
I/O
I/O
Bypass Register
Instruction
Register
TAP
Controller
Test Data
Registers
Table 1-6 • Boundary-Scan O pcod es
Hex Opcode
EXTEST 00
SAMPLE/PRELOAD 01
IDCODE 0F
CLAMP 05
BYPASS FF
ProASICPLUS Flash Family FP G As
v3.4 1-11
scan. The bypass register is selected when no other
register needs to be accessed in a device. This speeds up
test data transfer to other devices in a test data path.
The 32-bit device identification register is a shift register
with four field s (lowe st signi ficant by te (LSB) , ID num ber,
part number and version). The boundary-scan register
observes and controls the state of eac h I/O pin .
Each I/O cell has three bou ndary-scan register cells, each
with a serial-in, serial-out, parallel-in, and parallel-out
pin. The serial pins are used to serially connect all the
boundar y-scan register cel ls in a device into a bou ndary-
scan register chain, which starts at the TDI pin and ends
at the TDO pin. The parallel ports are connected to the
internal core logic tile and the input, output, and control
ports of an I/O buffer to capture and load data into the
register to cont ro l or observe the logic state of each I /O.
Timing Con trol and Characte ristics
ProASICPLUS Clock Management System
Introduction
ProASICPLUS devices provide designers with very flexible
clock conditioning capabilities. Each member of the
ProASICPLUS family contains two phase-locked loop (PLL)
blocks which per fo rm the follow ing functions :
• Clock Phase Adjustment via Programmable Delay (250
ps steps from –8 ns to +8 ns)
• Clo ck Skew Mi n imizatio n
• Clock Frequency Synthesis
Each PLL has th e fo llowi ng key features:
• Input Fre quenc y Range (fIN) = 1.5 to 180 MH z
• Feedba ck Fr equency Rang e (fVCO) = 1.5 to 180 MHz
• Output Freq uenc y Range (fOUT) = 6 to 180 MHz
• Output Phas e Shi ft = 0 °, 90 ° , 180 °, and 270 °
• Output Duty Cy cle = 50 %
• Low Output Jitt er (ma x at 25°C)
–f
VCO <10 MH z. Jitt er ±1% or better
Figure 1-13 • TAP Controller State Diagram
Test-Logic
Reset
Run-Test/
Idle Select-DR-
Scan
Capture-DR
Shift-DR
Exit-DR
Pause-DR
Exit2-DR
Update-DR
Select-IR-
Scan
Capture-IR
Shift-IR
Exit-IR
Pause-IR
Exit2-IR
Update-IR
1
11
0
1
0
00
11 00
00
11
00
1
1
11
11
110
0
00
0
0
ProASICPLUS Flash Family FPGAs
1-12 v3.4
– 10 MHz < fVCO < 60 MHz. Jitter ±2% or better
–f
VCO > 60 MHz. Jitter ±1% or b etter
Note: Jit ter (p s) = Jitter (%)*(10/Frequency (MHz)
For Example:
Jitter in picoseconds at 1 MHz = 1(%)*(10/1 (MHz)) = 10ps
• Maxim um Acquis ition Time = 80µs
• Low Power Consumption – 6.9 mW (max – analog
supply) + 7.0µW/MHz (max – digital supply)
Physical Implementation
Each side of the ch ip conta in s a clock conditioning circuit
based upon a 18 0 M H z PLL block (Figure 1 -1 4 on page 1-
13) . Two global m ultiplexe d lines exten d along ea ch side
of the chip to p rovide b idirectional access to the PLL on
that side (neither MUX can be connected to the opposite
side's PLL). Each global line has optional LVPECL input
pads (described below). The global lines may be driven
by either the LVPECL global input pad or the outputs
from the PLL block or both. Each global line can be
driven by a different output from the PLL. Unused global
pins can be configured as regular I/Os or left
unconne cted. Th ey def ault to an i nput wi th pu ll-up. The
two signal s available to drive the glo bal networks are as
follows (Figure 1-15 on page 1-14, Table 1-7 on page 1-
14, and Table 1- 8 on page 1-15):
Global A (secondary clock)
• Output from Global MUX A
• Conditioned version of PL L out put (fOUT) – del ay ed or
advanced
• Divided version of eithe r of the above
• Further delayed version of either of the above (0.25
ns, 0.50 ns, or 4.00 ns dela y) 1
Global B
• Output from Global MUX B
• Delaye d or advanced ve rsio n of f OUT
• Divided version of eithe r of the above
• Further delayed version of either of the above (0.25
ns, 0.50 ns, or 4.00 ns dela y) 1
Functional Description
Each PLL block contains four programmable dividers as
shown in Figure 1-14 on page 1-13. These allow
frequency scaling of the input clock signal as follows :
• The n divider divides the input clock by integer
fac to rs fr om 1 to 32.
• The m divider in the feedback path allows
multiplication of the input clock by integer factors
ranging from 1 to 64 .
• The two dividers together can implement any
combination of multiplication and division resulting
in a clock fr equency betwe en 24 and 180 MHz ex itin g
the PLL core . Th is clo ck ha s a fixed 50% duty cyc le .
• The output frequency of the PLL core is given by the
following formula (fREF is the reference clock
frequency):
fOUT = fREF * m/n
• The third and fourth dividers (u and v) permit the
signals applied to the global network to each be
further divided by integer factors ranging from 1 to 4.
The implementations:
fGLB = m/(n*u)
fGLA = m/(n*v)
enable the user to define a wide range of frequency
multipliers and divisors. The clock conditioning circuit
can a dvance or delay the clock up to 8 ns (in inc reme nts
of 0.25 ns) relative to the positive edge of the incoming
reference clock. The system also allows for the selection
of output frequency clock phases of 0°, 90°, 180°, and
270°.
Prior to the app lication of signals to t he rib drivers, the y
pass through programmable delay units, one per global
network. These units permit the delaying of global
signals relative to other signals to assist in the control of
input set -up times. Not all possible combinations of input
and outp ut modes can be u sed. The de grees of freedom
available in the bidirectional global pad system and in
the clock conditioning circuit have been restricted. This
avoids unnecessary and unwieldy design kit and software
work.
Lock Signal
An active-high Lock signal (added via the ACTgen PLL
development tool) indicates that the PLL has locked to
the incoming clock signal. Users can employ the Lock
signal as a soft reset of the logic driven by GLB and/or
GLA.
PLL Configuration Options
The PLL can be configured during design (via Flash-
configuration bits set in the programming bitstream) or
dynamically during device operation, thus eliminating
the need for complete reprogramming. The dynamic
configur ation bits are lo aded into a seri al-in/parallel-out
shift register provided in the clock conditioning circuit of
1. This mode is available through the delay feature of the Global MUX driver.
ProASICPLUS Flash Family FP G As
v3.4 1-13
each PLL and then latched into the PLL block. The JTAG
ports can be used along with a built-in user JTAG
interface hardware to load the configuration shift
register externally. Another option is internal dynamic
configuration via user-designed hardware. Refer to
Actel’s ProASICPLUS PLL Dynamic Reconfiguration Using
JTAG appl icat i on not e for mo re info rm at i on.
For information on the clock conditioning circuit, refer
to Actel’s Using ProASICPLUS Clock Conditioning Circuits
application not e..
1. FBDLY is a programmable delay line from 0 to 4 ns in 250 ps increments.
2. DLYA, DLYB, DLYAFB are programmable delay lines, each with selectable values 0, 250 ps, 500 ps, and 4 ns.
3. OBDIV will also divide the phase-shift since it takes place after the PLL Core.
Figure 1-14 • PLL Block – Top-Level View and Detailed PLL Block Diagram
AVDD AGND GND
+
-
VDD
External Feedback Signal
GLA
GLB
Dynamic
Configuration Bits
Flash
Configuration Bits
8
27
4
Clock Conditioning
Circuitry
(Top level view)
Global MUX A OUT
Global MUX B OUT
See Figure 15
on page 15
Input Pins to the PLL
GLB
GLA
÷u
÷v
PLL Core
0˚
90˚
180˚
270˚ 0
1
7
6
5
4
2
Delay Line 0.0ns, 0.25ns,
0.50ns and 4.00ns
P+
P-
Clock from Core
(GLINT mode)
CLK
1
0
Deskew
Delay
2.95 ns
1
2
3
Delay Line
0.25ns to
4.00ns,
16 steps,
0.25ns
increments
3
1
2
Delay Line 0.0ns, 0.25ns,
0.50ns and 4.00ns
Clock from Core
(GLINT mode)
CLKA
EXTFB XDLYSEL
Bypass Secondary
Bypass Primary
FIVDIV[4:0]
FBDIV[5:0]
FBSEL[1:0]
OAMUX[1:0] DLYA[1:0]
DLYB[1:0]
OBDIV[1:0]
OBMUX[2:0]
OADIV[1:0]
FBDLY[3:0]
÷n
÷m
Clock Conditioning Circuitry Detailed Block Diagram
ProASICPLUS Flash Family FPGAs
1-14 v3.4
Note: When a signal from an I/O tile is connected to the core, it cannot be connected t o the Global MUX at the same time.
Figure 1-15 • In put Connectors to ProASICPLUS C loc k Co nd itio ni n g Cir c uit ry
Table 1-7 • Clock-Conditioning Circuitry MUX Settings
MUX Datapath Comments
FBSEL
1 Internal Feedback
2 Internal Feedback and Advance Clock Using FBDLY –0.25 to –4 ns in 0.25ns increments
3 Extern al Feedback (EXTFB)
XDLYSEL
0 Feedback Unchanged
1 Deskew feedback by advancing clock by system delay Fixed delay of -2.95 ns
OBMUX GLB
0 Primary bypass, no divider
1 Primary bypass, use divider
2 Delay Clock Using FBDLY +0.25 to +4 ns in 0.25ns increments
4 Phase Shift Clock by 0°
5 Phase Shift Clock by +90°
6 Phase Shift Clock by +180°
7 Phase Shift Clock by +270°
OAMUX GLA
0 Secondary bypass, no divider
1 Secondary bypass, use divider
2 Delay Clock Using FBDLY +0.25 to +4 ns in 0.25ns increments
3 Phase Shift Clock by 0°
Configuration T ile
Configuration T ile
PECL Pad Cell
GLMX
GL
Std. Pad Cell
Std. Pad Cell
Std. Pad Cell
GL
NPECL
PPECL
CORE
Package Pins Physical I/O
Buffers Global MUX
External
Feedback
Global MUX B
OUT
Global MUX A
OUT
Legend
Physical Pin
DATA Signals to the Core
DATA Signals to the PLL Block
DATA Signals to the Global MUX
Control Signals to the Global MUX
ProASICPLUS Flash Family FP G As
v3.4 1-15
Sam pl e Imp le m ent at i ons
Frequency Synthesis
Figure 1-16 on page 1-16 illustrates an example where
the PLL is us ed to multipl y a 33 MHz ext ernal clock up to
133 MHz. Figure 1-17 on page 1-16 uses two dividers to
synthesize a 50 MHz output clock from a 40 MHz input
reference clock. The input frequency of 40 MHz is
multiplie d by 5 a nd divided by 4, g iving a n output clock
(GLB) frequency of 50 MHz. When dividers are used, a
given ratio can be generated in multiple ways, allowing
the user to stay within the operating frequency ranges of
the PL L. Fo r exa mple, in this c ase t he inp ut di vider c ould
have been 2 and the output divider also 2, giving us a
division of the input frequency by 4 to go with the
feedback loop division (effective multiplication) by 5.
Adjustable Clock Delay
Figure 1-18 on page 1-17 illustrates the delay of the
input clock by employing one of the adjustable delay
lines. This is easily done in ProASICPLUS by bypassing the
PLL core en tirely and using th e output delay li ne. Notice
also that the output clock can be effectively advanced
relative to the input clock by using the delay line in the
feedbac k pat h. T h is is shown in Figure 1-19 on page 1-17.
Clock Ske w Minim i za tion
Figure 1-20 on page 1-18 indicates how feedback from
the clock network can be used to create minimal skew
between the distributed clock network and the "input"
clock. The input clock is fed to the reference clock input
of the PLL. The output clock (GLA) feeds a clock network.
The feed back input to th e PLL uses a clock input del ayed
by a rou ting network. The PLL then adjus ts the phase of
the input clock to match the delayed clock, thus
providing nearly zero effective skew between the two
clocks. Refer to Actel’s Using ProASICPLUS Clock
Conditioning Circuits application note for more
information.
Logic Tile Timing Characteristics
Timing characteristics for ProASICPLUS devices fall into
three categories: family dependent, device dependent,
and design dependent. The input and output buffer
characteristics are common to all ProASICPLUS family
members. Internal routing delays are device dependent.
Design dependency means that actual delays are not
determined until after placement and routing of the
user’s design are complete. Delay values may then be
determined by using the Timer utility or performing
simulation with post-layout delays.
Critical Nets and Typical Nets
Propagation delays are expressed only for typical nets,
which are used for initial design performance evaluation.
Critical net delays can then be applied to the most timi ng
critical paths. Critical nets are determined by net
property assignment prior to placement and routing.
Refer to the Actel Designer User’s Guide or online help
for details on using c ons trai nts.
Timing Derating
Since ProASICPLUS devices are manufactured with a
CMOS process, device performance will vary with
temperature, voltage, and process. Minimum timing
parameters reflect maximum operating voltage,
minimum operating temperature, and optimal process
var iati ons . Maxi mum ti ming para mete rs r efle ct min imum
operating voltage, maximum operating temperature,
and worst-case process variations (within process
specifications).
Table 1-8 • Clock-Conditioning Circuitry Delay-Line Settings
De lay Lin e De lay Va lue (ns)
DLYB
00
1 +0.25
2 +0.50
3+4.0
DLYA
00
1 +0.25
2 +0.50
3+4.0
ProASICPLUS Flash Family FPGAs
1-16 v3.4
Figure 1-16 • Using the PLL 33 MHz In, 133 MHz Out
Figure 1-17 • Using the PLL 40 MHz In, 50 MHz Out
÷n
÷m÷u
÷v
D
D
D
D
PLL Core
External Feedback
Global MUX B OUT
Global MUX A OUT
GLB
GLA
0
˚
90
180
˚
270
˚
˚
33 MHz 133 MHz
÷4
÷1
÷1
÷n
÷m÷u
÷v
D
D
D
D
PLL Core
External Feedback
Global MUX B OUT
Global MUX A OUT
GLB
GLA
0˚
90˚
180˚
270˚
40 MHz 50 MHz
÷5
÷4
÷1
ProASICPLUS Flash Family FP G As
v3.4 1-17
Figure 1-18 • Using the PLL to Delay the Input Clock
Figure 1-19 • Using the PLL to "Advance" the Input Clock
÷n
÷m÷u
÷v
D
D
D
D
PLL Core
External Feedback
Global MUX B OUT
Global MUX A OUT
GLB
GLA
0˚
90˚
180˚
270˚
133 MHz 133 MHz
÷1
÷1
÷1
÷n
÷m÷u
÷v
D
D
D
D
PLL Core
External Feedback
Global MUX B OUT
Global MUX A OUT
GLB
GLA
0˚
90˚
180˚
270˚
133 MHz 133 MHz
÷1
÷1
÷1
ProASICPLUS Flash Family FPGAs
1-18 v3.4
Figure 1-20 • Using the PLL for Clock De-Skewing
÷n
÷m÷u
÷v
D
D
D
D
PLL Core
External Feedback
Global MUX B OUT
Global MUX A OUT
GLB
GLA
0˚
90˚
180˚
270˚
133 MHz
133 MHz
÷1
÷1
÷1
D
Q
QSET
CLR
ProASICPLUS Flash Family FP G As
v3.4 1-19
PLL El ec tr ic al Specifications
User Security
ProASICPLUS devices have FlashLock protection bits that,
once programmed, block the entire programmed
contents from being read externally. If locked, the user
can only reprogram the device employing the user-
defined se curity key. This protects the dev ice from being
read back and duplicated. Since programmed data is
stored in nonvolatile memory cells (which are actually
very small cap acito rs), ra ther th an in the wiri ng, ph ysical
deconstr uction canno t be us ed to comprom ise dat a. Th is
approach is further hampered by the placement of the
memory cells beneath the four metal layers (whose
removal cannot be accomplished without disturbing the
charge in the capacitor). This is the highest security
provided in the industry. For more information, refer to
Actel’s Design Security in Nonvolatile Flash and Antifuse
FPGAs white paper.
Embedded Memory Floorplan
The embedded memory is located across the top and
bottom of the dev i ce in 256x 9 blo cks (Figur e 1-1 on page
1-2). Depending upon the device, up to 88 blocks are
availab le to support a vari ety o f memo ry con figurat ions.
Each block can be programmed as an independent
memory or combined (using dedicated memory routing
resources) to form larger, more complex memories. A
single memory configuration could include blocks from
both the top and bottom me m ory locat ion s.
Parameter Value Notes
Fr equency Ranges
Reference Frequency fIN (min.) 1.5 MHz Clock conditioning circuitry (min.) lowest input frequency
Reference Frequency fIN (max.) 180 MHz Clock conditioning circuitry (max.) highest input frequency
OSC Frequency fVCO (min.) 24 MHz Lowest output frequency voltage controlled oscillator
OSC Frequency fVCO (max.) 180 MHz Highest output frequency voltage controlled oscillator
Clock Conditioning Circuitry fOUT (min.) 6 MHz Lowest o utpu t f r equen cy cl ock con di tion ing c ir cui try
Clock Conditioning Circuitry fOUT (max.) 180 MHz Highest out put fr equency cloc k conditionin g circu itry
Long Term Jitter Peak-to-Peak Max.*
Temper ature Frequency MHz
fVCO<10 10<fVCO<60 fVCO>60
25°C (or higher) ±1% ±2% ±1% Jitter(ps) = Jitter(%)*(10/Frequency (MHz)
For Example:
Jitter in picoseconds at 1 MHz
= 1(%)*(10/1 (MHz)) = 10ps
0°C ±1.5% ±2.5% ±1%
–40°C ±2.5% ±3.5% ±1%
Acquisitio n Time fr om Cold Start
Acquisition Time (max.) 30 µsf
VCO ≤ 40 MHz
Acquisition Time (max.) 80 µsf
VCO > 40 MHz
Power Consumption
Analog Supply Power (max*)6.9 mW
Digital Supply Current (max) 7 µW/MHz
Duty Cycle 50% ±0.5%
Note: *High clock frequencies (>60 MHz)
TM
ProASICPLUS Flash Family FPGAs
1-20 v3.4
Embedded Memory Configurations
The embedded memory in the ProASICPLUS family
provides great configuration flexibility (Table 1-9 on
page 1-20). Unlike many other programmable vendors
each ProASICPLUS block is designed and optimized as a
two-port memory (1 read, 1 write). This provides
198kbits of total memory for two-port and single port
usage in the APA 1000 device.
Each memory can be configured as FIFO or SRAM, with
independent selection of synchronous or asynchronous
read and write ports (Table 1-10). Additional
characteristics include programmable flags as well as
parity checking and generation. Figure 1-21 on page 1-
21 and Figure 1-22 on page 1-22 show the block
diagrams of the basic SRAM and FIFO blocks. Table 1-11
on page 1-22 and Table 1-12 on page 1-23 describe
memory block SRAM and FIFO interface signals,
respectively. A single memory is designed to operate at
up to 150 MHz (standard speed grade typical conditions).
Each block contains a 256 word, 9-bit wide (1 read port, 1
write port) memory. The memory blocks may be
combined in para llel to form wider memories or stacked
to form deeper memories (Figure 1-23 on page 1-23).
This provides optimal bit widths of 9 (1 block), 18, 36,
and 72, and optimal depths of 256, 512, 768, and 1,024.
Refer to Actel’s A Guide to ACTgen Macros for more
information.
Figure 1-24 on page 1-24 gives an example of optimal
memory usage. Ten blocks with 23,040 bits have been
used to generate three memories of various widths and
depths. Figure 1-25 on page 1-24 shows how memory
can be used in p arallel to cre ate extra r ead ports. In th is
example, using only 10 of the 88 available blocks of the
APA1000 yields an effective 6,912 bits of multiple port
memories. The Actel ACTgen software facilitates
building wider and deeper memories for optimal
memory usage.
Table 1-9 • ProASICPLUS Memory Configurations by Device
Device Bottom Top
Maximum Width Maximum Depth
DWDW
APA075 0 12 256 108 1,536 9
APA150 0 16 256 144 2,048 9
APA300 16 16 256 144 2,048 9
APA450 24 24 256 216 3,072 9
APA600 28 28 256 252 3,584 9
APA750 32 32 256 288 4,096 9
APA1000 44 44 256 396 5,632 9
Table 1-10 • Basic Memory Configurations
Type Write Acce ss Read Access Parity Library Cell Name
RAM Asynchronous Asynchronous Checked RAM256x9AA
RAM Asynchronous Asynchronous Generated RAM256x9AAP
RAM Asynchronous Synchronous Transparent Checked RAM256x9AST
RAM Asynchronous Synchronous Transparent Generated RAM256x9ASTP
RAM Asynchronous Synchronous Pipelined Checked RAM256x9ASR
RAM Asynchronous Synchronous Pipelined Generated RAM256x9ASRP
RAM Synchronous Asynchronous Checked RAM256x9SA
RAM Synchronous Asynchronous Generated RAM256xSAP
RAM Synchronous Synchronous Transparent Checked RAM256x9SST
RAM Synchronous Synchronous Transparent Generated RAM256x9SSTP
RAM Synchronous Synchronous Pipelined Checked RAM256x9SSR
RAM Synchronous Synchronous Pipelined Generated RAM256x9SSRP
FIFO Asynchronous Asynchronous Checked FIFO256x9AA
ProASICPLUS Flash Family FP G As
v3.4 1-21
FIFO Asynchronous Asynchronous Generated FIFO256x9AAP
FIFO Asynchronous Synchronous Transparent Checked FIFO256x9AST
FIFO Asynchronous Synchronous Transparent Generated FIFO256x9ASTP
FIFO Asynchronous Synchronous Pipelined Checked FIFO256x9ASR
FIFO Asynchronous Synchronous Pipelined Generated FIFO256x9ASRP
FIFO Synchronous Asynchronous Checked FIFO256x9SA
FIFO Synchronous Asynchronous Generated FIFO256x9SAP
FIFO Synchronous Synchronous Transparent Checked FIFO256x9SST
FIFO Synchronous Synchronous Transparent Generated FIFO256x9SSTP
FIFO Synchronous Synchronous Pipelined Checked FIF O256x9SSR
FIFO Synchronous Synchronous Pipelined Generated FIFO256x9SSRP
Note: To save area while using embedded memories, the memory blocks contain multiplexers (called DMUX) for each output signal. These
DMUX cells do not consume any core logic tiles and connect directly to high speed routing resource s between the memory blocks.
They are used when memories are cascaded and are automatically inserted by the software tools.
Figure 1-21 • Example SRAM Block Diagrams
Table 1-10 • Basic M emory Configurations (Continu ed)
Type Write Acce ss Read Access Parity Library Cell Name
SRAM
(256 X 9)
Sync Write &
Sync Read
Ports
DI <0:8> DO <0:8>
RADDR <0:7>
WADDR <0:7>
WRB RDB
WBLKB RBLKB
WCLKS RCLKS
RPE
PARODD
SRAM
(256 X 9)
Async Write
&
Async Read
Ports
DI <0:8>
WADDR <0:7>
WRB
WBLKB
PARODD
WPE WPE
SRAM
(256 X 9)
Sync Write
&
Async Read
Ports
DI <0:8> DO <0:8>
WADDR <0:7>
WRB RDB
WBLKB RBLKB
WCLKS
RPE
PARODD
WPE
RADDR <0:7>
PARODD
SRAM
(256 X 9)
Async Write
&
Sync Read
Ports
DI <0:8> DO <0:8>
RADDR <0:7>WADDR <0:7>
WRB RDB
WBLKB RBLKB
RCLKS
RPE
WPE
DO <0:8>
RADDR <0:7>
RDB
RBLKB
RCLKS
RPE
ProASICPLUS Flash Family FPGAs
1-22 v3.4
Table 1-11 • Memory Block SRAM Interface Signals
SRAM Signal Bit s In/Out Description
WCLKS 1 IN Write clock used on s ynchronization on write side
RCLKS 1 IN Read clock used on synchronization on read side
RADDR<0:7> 8 IN Read address
RBLKB 1 IN Read block select (active LOW)
RDB 1 IN Read pulse (active LOW)
WADDR<0:7> 8 IN Write address
WBLKB 1 IN Write block select (active LOW)
DI<0:8> 9 IN Input data bits <0:8>, <8> can be used for parity in
WRB 1 IN Wr ite pulse (act ive LOW)
DO<0:8> 9 OUT Output data bits <0:8>, <8> can be used for parity out
RPE 1 OUT Read parity error (active HIGH)
WPE 1 OUT Write parity error (active HIGH)
PARODD 1 IN Selects odd parity generation/detect when high, even when low
Note: Not all signals shown are used in all modes.
Note: To save area while using embedded memories, the memory blocks contain multiplexers (called DMUX) for each output signal. These
DMUX cells do not consume any core logic tiles and connect directly to high speed routing resource s between the memory blocks.
They are used when memories are cascaded and are automatically inserted by the software tools.
Figure 1-22 • Basic FIFO Block Diagra ms
FIFO
(256 X 9)
Sync Write &
Sync Read
Ports
LEVEL<0:7> DO <0:8>
DI<0:8>
WRB
RDB
WBLKB
RBLKB
RPE
PARODD
WPE
LGDEP<0:2>
FULL
EMPTY
EQTH
GEQTH
WCLKS
RCLKS
RESET
RESET
FIFO
(256 X 9)
Sync Write &
Async Read
Ports
RPE
WPE
FULL
EMPTY
EQTH
GEQTH
FIFO
(256 X 9)
Async Write &
Async Read
Ports
DO <0:8>
RPE
WPE
FULL
EMPTY
EQTH
GEQTH
FIFO
(256 X 9)
Async Write &
Sync Read
Ports
DI <0:8> DO <0:8>
LEVEL <0:7>
WRB
RDB
WBLKB
RBLKB
RPE
PARODD
WPE
LGDEP<0:2>
DI <0:8>
LEVEL <0:7>
WRB
RDB
WBLKB
RBLKB
PARODD
LGDEP<0:2>
FULL
EMPTY
EQTH
GEQTH
RCLKS
RESET
RESET
LEVEL<0:7>
DI<0:8>
WRB
RDB
WBLKB
RBLKB
PARODD
LGDEP<0:2>
WCLKS
DO <0:8>
ProASICPLUS Flash Family FP G As
v3.4 1-23
Table 1-12 • Memory Block FIFO Interface Signals
FIFO Signal Bits In /Out Description
WCLKS 1 IN Write clock used for synchronization on write side
RCLKS 1 IN Read clock used for synchronization on read side
LEVEL <0:7> 8 IN Direct configuration implements static flag logic
RBLKB 1 IN Read block select (active LOW)
RDB 1 IN Read pulse (active LOW)
RESET 1 IN Reset for FIFO pointers (active LOW)
WBLKB 1 IN Write block select (active LOW)
DI<0:8> 9 IN Input data bits <0:8>, <8> will be generated if PARGEN is true
WRB 1 IN Write pulse (active LOW)
FULL, EMPTY 2 OUT FIFO flags. FULL prevents write and EMPTY prevents read
EQTH, GE QTH 2 OUT EQTH is true wh en the FIFO holds the n umber of wor d s specified by the LEVEL sign al.
GEQTH is true when the FIFO holds (LEVEL) words or more
DO<0:8> 9 OUT Output data bits <0:8>
RPE 1 OUT Read parity error (active HIGH)
WPE 1 OUT Write parity error (active HIGH)
LGDEP <0:2> 3 IN Configures DEPTH of the FIFO to 2 (LGDEP+1)
PARODD 1 IN Parity generation/detect – Even when low, odd when high
Figure 1-23 • APA1000 Memory Block Architecture
Word
Depth
Word Width
88 blocks
256
9
256
9
256
9
256
9
256
9
256
9
256
9
256
9
256
9
ProASICPLUS Flash Family FPGAs
1-24 v3.4
Design Environmen t
The ProASICPLUS family of FPGAs is fully supported by
both Actel’s Libero™ Integrated Design Environment
(IDE) and Actel’s Designer FPGA Development Software.
Actel's Designer software provides a comprehensive suite
of backend development tools for FPGA development.
The Design er software include s timing-driven pl ace-and-
route, a world-class integrated static timing analyzer and
constraints editor, a design netlist schematic viewer, and
SmartPower, a tool that allows the user to quickly
estimate the po w er consu mption in a design.
Libero IDE provides an integrated design manager that
seaml essl y int egr at es design tools w hi le gui di ng the u ser
through the design flow, managing all design and log
files, and passing necessary design data among tools
(Figure 1-26 on page 1-25). Libero IDE includes
Synplicity® Synplify AE for Actel, Mentor Graphics™
ViewDraw AE for Actel, Actel's own Designer software,
Model Technology™ ModelSim AE HDL Simulator, and
Synapt iC A D ™ WaveFormer Li te AE.
Figure 1-24 • E xampl e Showing Memories w ith Differe nt Widths and Depths
Figure 1-25 • Multiport Memory Usage
Word
Depth
Word Width
1,024 words x 9 bits, 1 read, 1 write
512 words x 18 bits, 1 read, 1 write
256 words x 18 bits, 1 read, 1 write
Total Memory Blocks Used = 10
Total Memory Bits = 23,040
256
256
256
256
9
256
256
99
256
99
256
256
256
256
256
999
256
9
512 words x 9 bits, 4 read, 1 write
256 words x 9 bits, 2 read, 1 write
Total Memory Blocks Used = 10
Total Memory Bits = 6,912
Word
Depth
Word Width Write Port Write Port
Read Ports
99
Read Ports
999 9
256
256
256
256
256
256
256
ProASICPLUS Flash Family FP G As
v3.4 1-25
ISP
The user can generate *.bit or *.stp programming files
from the Designer software and can use these files to
program a device.
ProASICPLUS devices can be programmed in system. For
more information on ISP of P roASICPLUS devices, refer to
the In-System Programming ProASICPLUS Devices and
Performing I nternal In-System Pro gramm ing Using A ctel’s
ProASICPLUS Devices application notes. Prior to being
programmed for the first time, the ProASICPLUS device I/
Os are inputs with pull-ups.
Figure 1-26 • Design Flow
Timing Simulation
Functional Simulation
ModelSimR
Simulator
ViewDrawR
Schematic Entry
Synthesis
Libraries
Fuse or Bitstream
Layout
Compile
Back-Annotate
SmartPower
Timer
NetlistViewer
I/O Attribute
Editor
PinEditor
MultiView Navigator
I/O Assignments
Select I/O Standards
ChipPlanner or
ChipEditor
Floorplanning
Design Synthesis and Optimization
Static Timing Analysis and
Constraints Editor
Power Analysis
Back-Annotation Timing
for Simulation
Design Schematic Viewer
Cross-Probing
WaveFormer
LiteTM
Testbench
Stimulus Generation
User
Testbench
Design Implementation Design Implementation
Design Creation/VerificationDesign Creation/Verification
Libero
TM
IDE Design Flow
HDL Editor
ACTgen
Macro Builder
Optimization and DRC
Timing Driven Place-and-Route
SynplifyR Synthesis
Silicon Sculptor
(Antifuse and Flash Families) Silicon Explorer II
(Antifuse Families)
FlashPro
(Flash Families)
FlashPro Lite
(ProASIC
PLUS
Family)
BP Microsystems
Programmers
Actel
Device
ProgrammingProgramming System VerificationSystem Verification
ProASICPLUS Flash Family FPGAs
1-26 v3.4
Related Documents
Application Notes
Efficient Use of Pro A SI C Clo ck Tree s
http://www.actel.com/documents/clocktree.pdf
I/O Features in ProASICPLUS Flash FPGAs
http://www.actel.com/documents/PAPLUSLVPECL.pdf
ProASICPLUS Family Devices Power-Up Behavi or
http://www.actel.com/documents/PAPLUS_PowerUp.pdf
ProASICPLUS PLL Dynamic Reconfigurat ion Using JTAG
http://www.actel.com/documents/
PAPLUSPLLdynamicAN.pdf
Using ProASICPLUS Clock Conditioni ng Ci rcuits
http://www.actel.com/documents/PAPLUSPLLan.pdf
In-System Programming ProASICPLUS Devices
http://www.actel.com/documents/External_ISP_AN.pdf
Perf ormi n g Inter nal In-S ys tem Pro gra mmin g Usi ng
Acte l ’s ProA SIC PLUS Devices
http://www.actel.com/documents/PAplusISPAN.pdf
White Paper
Design Security in Nonvol at ile Flas h and Ant ifus e FPGAs
http://www.actel.com/documents/DesignSecurity.pdf
User’s Guide
Designer User’s Guide
http://www.actel.com/documents/designerUG.pdf
Flash Macro Library Guide
http://www.actel.com/documents/PA_libguide.pdf
ProASICPLUS Flash Family FP G As
v3.4 1-27
Package Th er mal Characteri s ti cs
The ProASICPLUS family is available in several package
types with a range of pin counts. Actel has selected
packages based on high pin count, reliability factors, and
sup e rior therma l ch arac terist ics.
Thermal resistance defines the ability of a package to
conduct heat away from the silicon, through the
package to the surrounding air. Junction-to-ambient
thermal resistance is measured in degrees Celsius/Watt
and is represented as Theta ja (Θja). The lower the
thermal resistance, the more efficiently a package will
dissipate heat.
A packag e’s maxim um allowed power ( P) i s a fu nctio n of
maximum junction temperature (TJ), maximum ambient
operating temperature (TA), and junction-to-ambient
thermal resistance Θja. Maximum junction temperature is
the maximum allowable temperature on the active
surface of the IC and is 110° C. P is def ine d as:
Θja is a function of the rate (in linear feet per minute –
lfpm) of airflow in contact with the package. When the
estimated power consumption exceeds the maximum
allowed power, other means of cooling, such as
in creas ing the air fl o w ra te, must be u sed.
PTJTA
–
Θja
-
-
-----------------=
Table 1-13 • Package Thermal Characteristics
Package Type Pin Coun t Θjc Θja St ill Air Θja 300 ft./
min. Units
Thin Quad Flat Pack (TQFP) 100 12 37.5 30 °C/W
Thin Quad Flat Pack (TQFP) 144 11 32 24 °C/W
Plastic Quad Flat Pack (PQFP) 208 8 30 23 °C/W
PQFP with Heatspreader 2 08 3.8 20 17 °C/W
Plastic Ball Grid Array (PBGA) 456 3 15.6 12 °C/W
Fine Pitch Ball Grid Array (FBGA) 144 3.8 38.8 26.7 °C/W
Fine Pitch Ball Grid Array (FBGA) 256 3.8 25 22 °C/W
Fine Pitch Ball Grid Array (FBGA)1484 3.2 20 15 °C/W
Fine Pitch Ball Grid Array (FBGA)2484 3.2 20.5 16.6 °C/W
Fine Pitch Ball Grid Array (FBGA) 676 3.2 16.4 11.5 °C/W
Fine Pitch Ball Grid Array (FBGA) 896 2.4 13.6 10.3 °C/W
Fine Pitch Ball Grid Array (FBGA) 1152 1.8 12 8.9 °C/W
Notes:
1. Depopulated Array
2. Full Array
ProASICPLUS Flash Family FPGAs
1-28 v3.4
Calculating Typical Power
Dissipation
ProASICPLUS devi ce powe r is calculated w ith both a stat ic
and an active component. The active component is a
function of both the number of tiles utilized and the
system speed. Power dissipation can be calculated using
th e follo wing fo rmu la:
Ptotal = Pdc + Pac
wher e:
Pclock, the clock component of power dissipation, is given
by
Pclock = (P1 + P2 * R - P7*R2) * Fs
where:
Pstorage, the storage-tile (Register) component of AC
power diss ipation, is given by
Pstorage = P5 * ms * Fs
wher e:
Plogic, the logic-tile component of AC power dissipation,
is given by
Plogic = P3 * mc * Fs
where:
Poutputs, the I/O component of AC power dissipation, is
given by
Poutputs = (P4 + (Cload * VDDP2)) * p * Fp
where:
The inpu t’s component of AC power dissipation is given
by
Pinputs = P8 * q * Fq
wher e:
Ppll = P9 * Npll
wher e:
Finally, Pmemory, the memory component of AC power
consumption, is given by
Pmemory = P6 * Nmemory * Fmemory * Ememory
wher e:
•P
dc = 12. 5 mW (Typically 2.5V x 5mA)
Pdc includes the static com ponents of:
PVDDP + PVDD + PAVDD
•P
ac =P
clock + Pstorage + Plogic + Pinputs + Poutputs +
Pmemo ry + Ppll
• P1 = 100 µW/M H z is t he basic power co nsu mption
of the clo c k tre e per MH z of the cl o ck
•P2 =1.3 µW/MHz is the incremental power
consumption of the clock tree per storage
tile – also per MH z of the cl oc k
• P7 = 0.0 0003 µW/MHz is a correction factor for
highly loaded clock-trees
• R = the number of storage tiles clocked by this
clock
• Fs = the clock frequency
• P5 = 1.1 µW/MHz is the average power
consum ption of a storage-til e p er MHz of its
output toggling rate. The maximum output
toggling ra te is Fs /2
• ms = the number of storage tiles (Register)
switchi ng during each Fs cyc le
• Fs = the clock fre quen cy
• P3 = 1.4 µW/MHz, is the average power
consumption of a logic tile per MHz of its
output toggling rate. The maximum output
toggling rate is Fs/2
•mc = the number of logic tiles switching during
each Fs cycle
• Fs = the cloc k fr eque ncy
• P4 = 326 µW/MHz is the intrinsic power
consumption of an output pad normalized
pe r MHz o f the ou tput fr equ ency. T his is th e
total I/O current VDD + VDDP
•C
loa
d
= t he out put load
• p = the number of outputs
• Fp = t he average output frequency
•P8=29 µW/MHz is the intrinsic power consumption of an
input pad normalized per MHz of the input frequency
• q = t he num b er of inpu ts
• Fq = t he av era ge i nput fr eque ncy
• P9 = 7.5 mW. This value has been estimated at
max imum PLL clock frequency
•N
Pll= number of PLLs used
•P6 =175 µW/MHz is the average power
consumption of a memory block per
MHz of the clock
•N
memory = the numbe r of RA M/FI FO bl oc ks
(1 block = 256 w or ds * 9 bits )
ProASICPLUS Flash Family FP G As
v3.4 1-29
The following is an APA750 example using a shift
register design with 13,440 storage tiles (Register) and 0
logic tiles. This design has one clock at 10 MHz, and 24
outputs toggling at 5 MHz. We then calculate the various
components as follows:
Pclock
=> Pclock = (P1 + P2 * R - P7*R2) * Fs = 124. 2 m W
Pstorage
=> Pstorage = P5 * ms * Fs = 147 .8 mW
Plogic
=> Plogic = 0 mW
Poutputs
=> Poutputs = (P 4 + Cload * VDDP2) * p * Fp = 87.3 mW
Pinputs
=> Pinputs = P8 * q * Fq = 0.3 mW
Pmemory
=> Pmemory = 0 mW
Pac
=> 360 mW
Ptotal
Pdc + Pac = 372 mW (Typical )
•F
memory = the clock frequency of the memory
•E
memory = the average number of active blocks
divided by the total number of blocks
(N) of the memory.
• Typical values for Ememory would be
1/4 for a 1k x 8,9,16, 32 memory and
1/16 for a 4kx8, 9, 16, and 32
memory
• In addition, an application-
dependent component to Ememory
can be considered. For example, for
a 1kx8 memory using only 1 cycle
out of 3, Ememory = 1/4*1/3 = 1/12
•sF=10 MHz
• R = 13,440
• ms = 13,440 (in a shift register 100% of storage-
tiles are toggl ing at e ach clock cycle and Fs =
10 MHz)
•mc
= 0 (no logic tile in this shift-register)
•C
load =40 pF
•V
DDP = 3.3 V
• p =24
•Fp = 5 MHz
•q =1
•Fq =10 MHz
Nmemory = 0 (no RAM/F IFO in th is shift-register)
ProASICPLUS Flash Family FPGAs
1-30 v3.4
Operating Conditions
Standa rd an d –F parts are the sam e unl es s otherwise noted. –F parts are only available as commercial.
Table 1-14 • Absolute Maximum Ratings*
Parameter Condition Minimum Maximum Units
Supply Voltage Core (VDD)–0.33.0V
Supply Voltage I/O Ring (VDDP)–0.34.0V
DC Input Voltage –0.3 VDDP + 0.3 V
PCI DC Input Voltage –1.0 VDDP + 1.0 V
PCI DC Input Clamp Current (absolute) VIN < –1 or VIN = VDDP + 1V 10 mA
LVPECL Input Voltage –0.3 VDDP + 0.5 V
GND 00V
Note: *Stresses beyond those listed under “Absolute Maximum Ratings” may cause permanent damage to the device. Exposure to
absolute ma ximum rated condition s for exten ded periods may affect device reliability. Devices should not be operated outside the
Recommended Operating Conditions.
Table 1-15 • Programmin g, Stora ge and Opera ting Limit s
Product Grade Programming Cycles Program Retention
Sto rage Temperature Opera ting
Min. Max.
TJ Max
Junction
Temperature
Commercial 500 20 years –55°C 110°C 110°C
Industrial 500 20 years –55°C 110°C 110°C
Note: This is a stress rating only. Functional operation at these or any other condition above those indicated in the operational and
programming specific ation is not implied.
Table 1-16 • Supply Voltages
Mode VDD VDDP
Single Voltage 2.5V 2.5V
Mixed Voltage* 2.5V 3.3V
Note: *Please refer to the mixed-mode interfacing section in the I/O Features in ProASICPLUS Flash FPGAs application note for more
information.
Table 1-17 • Recommended Maximum Operating Conditions Programming and PLL Supplies
Parameter Condition
Commercial/Industrial
UnitsMinimum Maximum
VPP During Programming 15.8 16.5 V
Normal Operation10 16.5 V
VPN During Programming –13.8 –13.2 V
Normal Operation2–13.8 0 V
IPP During Programming 25 mA
IPN During Programming 10 mA
AVDD VDD VDD V
AGND GND GND V
Notes:
1. Please refer to the "VPP Programming Supply Pin" on page 1-64 for more information.
2. Please refer to the "VPN Programming Supply Pin" on page 1-64 for more information.
ProASICPLUS Flash Family FP G As
v3.4 1-31
Table 1-18 • Recommended Operating Conditions
Parameter Symbol
Limits
Commercial Industrial
DC Supply Voltage (2.5V I/Os) VDD & VDDP 2.5V ± 0.2V 2.5V ± 0.2V
DC Supply Voltage (2.5V, 3.3V I/Os*) VDDP
VDD
3.3V ± 0.3V
2.5V ± 0.2V 3.3V ± 0.3V
2.5V ± 0.2V
Operating Ambient Temperature Range TA0°C to 70°C –40°C to 85°C
Maximum Operating Junction Temperature TJ110°C 110°C
Note: *Please refer to the mixed-mode interfacing section in the I/O Features in ProASICPLUS Flash FPGAs application note for more
information.
Table 1-19 • DC Electrical Specifications (VDDP = 2.5V ±0.2V)1
Symbol Parameter Conditions
Commercia l / Industrial1,2
Min. Typ. Max. Units
VOH Output High Volt age
High Drive (OB25LPH)
Low Drive (OB25LPL)
IOH = –6 mA
IOH = –12 mA
IOH = –24 mA
IOH = –3 mA
IOH = –6 mA
IOH = –8 mA
2.1
2.0
1.7
2.1
1.9
1.7
V
VOL Output Low Voltage
High Drive (OB25LPH)
Low Drive (OB25LPL)
IOL = 8 mA
IOL = 15 mA
IOL = 24 mA
IOL = 4 mA
IOL = 8 mA
IOL = 15 mA
0.2
0.4
0.7
0.2
0.4
0.7
V
VIH Input High Voltage 1.7 VDDP +
0.3 V
VIL Input Low Voltage –0.3 0.7 V
RWEAKPULLUP Weak Pull-up Resistan ce
(OTB25LPU) VIN ≥ 1.25V 6 56 kΩ
HYST Input Hysteresis Schmitt See Table 1-4 on page 1-8 0.3 0.350.45V
IIN Input Current with pull up (VIN = GND) –240 – 20 µA
without pull up (VIN = GND or VDD) –10 10 µA
IDDQ Quiescent Supply Current
(standby)
Commercial
VIN = GND3 or VDD Std. 5.0 15 mA
–F 5.0 25 mA
IDDQ Quiescent Supply Current
(standby)
Industrial
VIN = GND3 or VDD Std. 5.0 20 mA
Notes:
1. All process conditions. Junction Temperature: –40 to +110°C.
2. –F parts are only available as commercial.
3. No pull-up resistor.
4. This will not exceed 2mA total per device.
ProASICPLUS Flash Family FPGAs
1-32 v3.4
IOZ 3-State Output Leakage C urr ent VOH = GND or VDD Std. –10 10 µA
–F4–10 100 µA
IOSH Outpu t Sho rt Cir cuit Curre nt Hi gh
High Drive (OB25LPH)
Low Drive (OB25LPL) VIN = VSS
VIN = VSS
–120
–100
mA
IOSL Output Short Circuit Current Low
High Drive (OB25LPH)
Low Drive (OB25LPL) VIN = VDDP
VIN = VDDP
100
30
mA
CI/O I/O Pad Capacitance 10 pF
CCLK Clock Input Pad Capacitance 10 pF
Table 1-19 • DC Electrical Specifications (VDDP = 2.5V ±0.2V)1 (Continued)
Symbol Parameter Conditions
Commercia l / Industrial1,2
Min. Typ. Max. Units
Notes:
1. All process conditions. Junction Temperature: –40 to +110°C.
2. –F parts are only available as commercial.
3. No pull-up resistor.
4. This will not exceed 2mA total per device.
ProASICPLUS Flash Family FP G As
v3.4 1-33
Table 1-20 • DC Electrical Specifications (VDDP = 3.3V ±0.3V and VDD 2.5V ±0.2V)1
Symbol Parameter Conditions
Commercial / Industrial1,2
UnitsMin. Typ. Max.
VOH Output High Volt age
3.3V I/O, High Drive (OB33P)
3.3V I/O, Low Drive (OB33L)
IOH = –14 mA
IOH = –24 mA
IOH = –6 mA
IOH = –12 mA
0.9∗VDDP
2.4
0.9∗VDDP
2.4
V
Output High Voltage
2.5V I/O, High Drive
(OB25H)3
2.5V I/O, Low Drive (OB 25L) 3
IOH = –0.1 mA
IOH = –0.5 mA
IOH = –3.0 mA
IOH = –0.1 mA
IOH = –0.5 mA
IOH = –1.0 mA
2.1
2.0
1.7
2.1
2.0
1.7
V
VOL Output Low Voltage
3.3V I/O, High Drive (OB33P)
3.3V I/O, Low Drive (OB33L)
IOL = 15 mA
IOL = 20 mA
IOL = 28 mA
IOL = 7 mA
IOL = 10 mA
IOL = 15 mA
0.1VDDP
0.4
0.7
0.1VDDP
0.4
0.7
V
Output Low Voltage
2.5V I/O, High Drive
(OB25H)3
2.5V I/O, Low Drive (OB 25L) 3
IOL = 7 mA
IOL = 14 mA
IOL = 28 mA
IOL = 5 mA
IOL = 10 mA
IOL = 15 mA
0.2
0.4
0.7
0.2
0.4
0.7
V
VIH Input High Voltage
3.3V LVTTL/LVCMOS
2.5V Mode 2
1.7 VDDP +
0.3
VDDP +
0.3
V
VIL Input Low Voltage
3.3V LVTTL/LVCMOS
2.5V Mode –0.3
–0.3 0.8
0.7 V
RWEAKPULLUP Weak Pull-up Resistance
(IOB33U) VIN ≥ 1.5V 7 43 kΩ
RWEAKPULLUP Weak Pull-up Resistance
(IOB25U) VIN ≥ 1.5V 7 43 kΩ
IIN Input Current with pull up (VIN = GND) –300 –40 µA
without pull up (VIN = GND or VDD) –10 10 µA
Notes:
1. All process conditions. Junction Temperature: –40 to +110°C.
2. –F parts are only available as commercial.
3. Plea se refe r to the mi xe d-m ode in ter fac ing s ecti on in th e I/O Features in ProASICPLUS Flash FPGAs application note for guidelines
and usage.
4. No pull-up resistor.
5. This will not exceed 2mA total per device.
ProASICPLUS Flash Family FPGAs
1-34 v3.4
IDDQ Quiescent Supply Current
(standby)
Commercial
VIN = GND4 or VDD Std. 5.0 15 mA
–F 5.0 25 mA
IDDQ Quiescent Supply Current
(standby)
Industrial
VIN = GND4 or VDD Std. 5.0 20 mA
IOZ 3-State Output Leakage
Current VOH = GND or VDD Std. –10 10 µA
–F4–10 100 µA
IOSH Output Short Circuit Current
High
3.3V High Drive (OB33P)
3.3V Low Drive (OB33L)
2.5V High Drive (OB25H)3
2.5V Low Drive (OB25L)3
VIN = GND
VIN = GND
VIN = GND
VIN = GND
–200
–100
–20
–10
mA
IOSL Output Short Circuit Current
Low
3.3V High Drive
3.3V Low Drive
2.5V High Drive3
2.5V Low Drive3
VIN = VDD
VIN = VDD
VIN = VDD
VIN = VDD
200
100
200
100
mA
CI/O I/O Pad Capacitance 10 pF
CCLK Clock Input Pad Capacitance 10 pF
Table 1-20 • DC Electrical Specifications (VDDP = 3.3V ±0.3V and VDD 2.5V ±0.2V)1 (Continued)
Symbol Parameter Conditions
Commercial / Industrial1,2
UnitsMin. Typ. Max.
Notes:
1. All process conditions. Junction Temperature: –40 to +110°C.
2. –F parts are only available as commercial.
3. Plea se refe r to the mi xe d-m ode in ter fac ing s ecti on in th e I/O Features in ProASICPLUS Flash FPGAs application note for guidelines
and usage.
4. No pull-up resistor.
5. This will not exceed 2mA total per device.
ProASICPLUS Flash Family FP G As
v3.4 1-35
Table 1-21 • DC Specifications (3.3V PCI Operation)1
Symbol Parameter Condition
Com m ercial / Indust rial2,3
UnitsMin. Max.
VDD Supply Voltage for Core 2.3 2.7 V
VDDP Supply Voltage for I/O Ring 3.0 3.6 V
VIH Input High Voltage 0.5VDDP VDDP + 0.5 V
VIL Input Low Voltage –0.5 0.3VDDP V
IIPU Input Pull-up Voltage40.7VDDP V
IIL Input Leakage Current50 < VIN < VCCI Std. –10 10 µA
–F6–10 100 µA
VOH Output High Volt age IOUT = –500 µA 0.9VDDP V
VOL Output Low Voltage IOUT = 1500 µA 0.1VDDP V
CIN Input Pin Capacitance (except CLK) 10 pF
CCLK CLK Pin Capacitance 5 12 pF
Notes:
1. For PCI operation, use OTB33PH , OB33PH, IOB33PH, IB33, or IB33S macro library cell only.
2. All process conditions. Junction Temperature: –40 to +110°C.
3. –F parts are available as commercial only.
4. This specification is guaranteed by design. It is the minimum voltage to which pull-up resistors are calculated to pull a floated
network. De si gners with applications se nsiti ve t o stat ic power ut ilizat ion s hou ld ens ur e th at t he in put buf fer is conduc t ing m inimum
current at this input voltage.
5. Input leakage currents include hi-Z output leakage for all bidirectional buffers with tristate outputs.
6. The sum of the leakage currents for all inputs shall not exceed 2mA per device.
ProASICPLUS Flash Family FPGAs
1-36 v3.4
Table 1-22 • AC Specifications (3.3V PCI Revision 2.2 Operation)
Symbol Parameter Condition
Commercial / I ndustrial
UnitsMin. Max.
IOH(AC) Switching Current High 0 < VOUT ≤ 0.3VCCI*–12VCCI mA
0.3VCCI ≤ VOUT < 0.9VCCI*(–17.1 + (VDDP – VOUT)) mA
0.7VCCI < VOUT < VCCI*See equation C – page 124 of
the PCI Specification
document rev. 2.2
(Test Point) VOUT = 0.7VCC*–32VCCI mA
IOL(AC) Switching Current Low VCCI > VOUT ≥ 0.6VCCI*16VDDP mA
0.6VCCI > VOUT > 0.1V CCI 1(26.7VOUT)mA
0.18VCCI > VOUT > 0*See equation D – page 124 of
the PCI Specification
document rev. 2.2
(Test Point) VOUT = 0.18VCC 38VCCI mA
ICL Low Clamp Current –3 < VIN ≤ –1 –25 + (VIN + 1)/0.015 mA
ICH High Clamp Current VCCI + 4 > VIN ≥ ςCCI + 1 25 + (VIN – VDDP – 1)/0.015 mA
slewROutput Rise Slew Rate 0.2VCCI to 0.6VCCI load*14V/ns
slewFOutput Fall Slew Rate 0.6VCCI to 0.2VCCI load*14V/ns
Note: * Refer to the PCI Specification document rev. 2.2.
pin
output
buffer
1/2 in. max
10 pF
1kΩ
pin
output
buffer 10 pF
1kΩ
Pad Loading Applicable to the Rising Edge PCI
Pad Loading Applicable to the Falling Edge PCI
ProASICPLUS Flash Family FP G As
v3.4 1-37
Tristate Buffer Delays
Figure 1-27 • Tristate Buffer Delays
Table 1-23 • Worst-Case Commercial Conditions
VDDP = 3.0V, VDD = 2.3V, 35 pF load, TJ = 70°C
Macro Type Description
Max
tDLH1Max
tDHL2Max
tENZH3Max
tENZL4
UnitsSTD –F STD –F STD –F ST D –F
OTB33PH 3.3V, PCI Output Current, High Slew Rate 2.0 2.4 2.2 2.6 2.2 2.6 2.0 2.4 ns
OTB33PN 3.3V, High Output Current, Nominal Slew Rate 2.2 2.6 2.9 3.5 2.4 2.9 2.1 2.5 ns
OTB33PL 3.3V, High Output Current, Low Slew Rate 2.5 3.0 3.2 3.9 2.7 3.3 2.8 3.4 ns
OTB33LH 3.3V, Low Output Current, High Slew Rate 2.6 3.1 4.0 4.8 2.8 3.4 3.0 3.6 ns
OTB33LN 3.3V, Low Output Current, Nominal Slew Rate 2.9 3.5 4.3 5.2 3.2 3.8 4.1 4.9 ns
OTB33LL 3.3V, Low Output Current, Low Slew Rate 3.0 3.6 5.6 6.7 3.3 3.9 5.5 6.6 ns
OTB25HH 2.5V, High Output Current, High Slew Rate53.1 3.8 1.8 2.2 2.8 3.4 1.7 2.0 ns
OTB25HN 2.5V, High Output Current, Nominal Slew Rate53.1 3.7 2.7 3.3 2.9 3.5 2.7 3.2 ns
OTB25HL 2.5V, High Output Current, Low Slew Rate53.1 3.7 3.9 4.7 2.9 3.5 3.8 4.6 ns
OTB25LH 2.5V, Low Output Current, High Slew Rate54.6 5.6 2.9 3.5 4.6 5.5 2.9 3.4 ns
OTB25LN 2.5V, Low Output Current, Nominal Slew Rate54.6 5.6 3.7 4.5 4.6 5.5 3.6 4.3 ns
OTB25LL 2.5V, Low Output Current, Low Slew Rate54.6 5.6 5.1 6.1 4.5 5.4 4.8 5.8 ns
OTB25LPHH 2.5V, Low Power, High Output Current, High Slew Rate62.0 2.4 2.1 2.5 2.3 2.7 2.0 2.4 ns
OTB25LPHN 2.5V, Low Power, High Output Current, Nominal Slew Rate62.4 2.9 3.0 3.6 2.7 3.2 2.1 2.5 ns
OTB25LPHL 2.5V, Low Power, High Output Current, Low Slew Rate62.9 3.5 3.2 3.8 3.1 3.8 2.7 3.2 ns
OTB25LPLH 2.5V, Low Power, Low Output Current, High Slew Rate62.7 3.3 4.6 5.5 3.0 3.6 2.6 3.1 ns
OTB25LPLN 2.5V, Low Power, Low Output Current, Nominal Slew Rate63.5 4.2 4.2 5.1 3.8 4.5 3.8 4.6 ns
OTB25LPLL 2.5V, Low Power, Low Output Current, Low Slew Rate64.0 4.8 5.3 6.4 4.2 5.1 5.1 6.1 ns
Notes:
1. tDLH=Data-to-Pad HIGH
2. tDHL=Data-to-Pad LOW
3. tENZH=Enable-to-Pad, Z to HIGH
4. tENZL = Enable-to-Pad, Z to LOW
5. Please refer to the mixed-mode interfacing section in the I/O Features in ProASICPLUS Flash FPGAs application note for guidelines
and usage.
6. Low power I/O work with VDDP=2.5V ±10% only. VDDP=2.3V for delays.
PAD
A
OTBx
A50%
PAD
VOL
VOH
50%
tDLH
50%
50%
tDHL
EN 50%
PAD VOL
50%
tENZL
50%
10%
EN 50%
PAD
GND
VOH
50%
tENZH
50%
90%
VCC
35pF
EN
ProASICPLUS Flash Family FPGAs
1-38 v3.4
Output Buffer Delays
Figure 1-28 • Output Buffer Delays
Table 1-24 • Worst-Case Commercial Conditions
VDDP = 3.0V, VDD = 2.3V, 35 pF load, TJ = 70°C
Macro Type Description
Max tDLH1Ma x tDHL2
UnitsSTD –F STD – F
OB33PH 3.3V, PCI Output Current, High Slew Rate 2.0 2.4 2.2 2.6 ns
OB33PN 3.3V, High Output Current, Nominal Slew Rate 2.2 2.6 2.9 3.5 ns
OB33PL 3.3V, High Output Current, Low Slew Rate 2.5 3.0 3.2 3.9 ns
OB33LH 3.3V, Low Output Current, High Slew Rate 2.6 3.1 4.0 4.8 ns
OB33LN 3.3V, Low Output Current, Nominal Slew Rate 2.9 3.5 4.3 5.2 ns
OB33LL 3.3V, Low Output Current, Low Slew Rate 3.0 3.6 5.6 6.7 ns
OB25HH 2.5V, High Output Current, High Slew Rate33.1 3.8 1.8 2.2 ns
OB25HN 2.5V, High Output Current, Nominal Slew Rate33.1 3.7 2.7 3.3 ns
OB25HL 2.5V, High Output Current, Low Slew Rate33.1 3.7 3.9 4.7 ns
OB25LH 2.5V, Low Output Current, High Slew Rate34.6 5.6 2.9 3.5 ns
OB25LN 2.5V, Low Output Current, Nominal Slew Rate34.6 5.6 3.7 4.5 ns
OB25LL 2.5V, Low Output Current, Low Slew Rate34.6 5.6 5.1 6.1 ns
OB25LPHH 2.5V, Low Power, High Output Current, High Slew Rate42.0 2.4 2.1 2.6 ns
OB25LPHN 2.5V, Low Power, High Output Current, Nominal Slew Rate42.4 2.9 3.0 3.6 ns
OB25LPHL 2.5V, Low Power, Hi gh Output Current, Low Slew Rate42.9 3.5 3.2 3.8 ns
OB25LPLH 2.5V, Low Power, Low Output Current, High Slew Rate42.7 3.3 4.6 5.5 ns
OB25LPLN 2.5V, Low Power, Low Output Current, Nominal Slew Rate43.5 4.2 4.2 5.1 ns
OB25LPLL 2.5V, Low Power, Low Output Current, Low Slew Rate44.0 4.8 5.3 6.4 ns
Notes:
1. tDLH = Data-to-Pad HIGH
2. tDHL = Data-to-Pad LOW
3. Please refer to the mixed-mode interfacing section in the I/O Features in ProASICPLUS Flash FPGAs application note for guidelines
and usage.
4. Low power I/O work with VDDP=2.5V ±10% only. VDDP=2.3V for delays.
PAD
A50%
PAD
VOL
VOH
50%
tDLH
50%
50%
tDHL
35pF
A
OBx
ProASICPLUS Flash Family FP G As
v3.4 1-39
Input Buffer Delays
Figure 1-29 • Input Buffer Delays
Table 1-25 • Worst-Case Commercial Conditions
VDDP = 3.0V, VDD = 2.3V, TJ = 70°C
Macro Type Description
Max. tINYH1 Max. tINYL2
UnitsStd. –F Std. –F
IB25 2.5V, CMOS Input Levels3, No Pull-up Resistor 0.7 0.9 0.8 1.0 ns
IB25S 2.5V, CMOS Input Levels3, No Pull-up Resistor, Schmitt Trigger 0.7 0.9 0.8 1.0 ns
IB25LP 2.5V, CMOS Input Levels3, Low Power 0.9 1.1 0.6 0.8 ns
IB25LPS 2.5V, CMOS Input Levels3, Low Power, Schmitt Trigger 0.7 0.9 0.9 1.1 ns
IB33 3.3V, CMOS Input Levels3, No Pull-up Resistor 0.4 0.5 0.6 0.7 ns
IB33S 3.3V, CMOS Input Levels3, No Pull-up Resistor, Schmitt Trigger 0.6 0.7 0.8 0.9 ns
Notes:
1. tINYH = Input Pad-to-Y HIGH
2. tINYL = Input Pad-to-Y LOW
3. LVTTL delays are the same as CMOS delays.
4. For LP Macros, VDDP=2.3V for delays.
PAD YPAD V
CC
0V
50%
Y
GND
V
CC
50%
t
INYH
50%
50%
INYL
IBx
t
ProASICPLUS Flash Family FPGAs
1-40 v3.4
Global Input Buffer Delays
Predicted Globa l Ro uting D elay
Global Routing Ske w
Table 1-26 • Worst-Case Commercial Conditions
VDDP = 3.0V, VDD = 2.3V, TJ = 70°
Macro Type De scription
Max. tINYH1 Max. tINYL2 Units
Std. –F Std. –F
GL25 2.5V, CMOS Input Levels3, No Pull-up Resistor 1.3 1.6 1.0 1.2 ns
GL25S 2.5V, CMOS Input Levels3, No Pull-up Resistor, Schmitt Trigger 1.3 1.6 1.0 1.2 ns
GL25LP 2.5V, CMOS Input Levels3, Low Power 1.1 1.2 1.0 1.3 ns
GL25LPS 2.5V, CMOS Input Levels3, Low Power, Schmitt Trigger 1.3 1.6 1.0 1.1 ns
GL33 3.3V, CMOS Input Levels3, No Pull-up Resistor 1.0 1.2 1.1 1.3 ns
GL33S 3.3V, CMOS Input Levels3, No Pull-up Resistor, Schmitt Trigger 1.0 1.2 1.1 1.3 ns
PECL PPECL Input Levels 1.0 1.2 1.1 1.3 ns
Notes:
1. tINYH = Input Pad-to-Y HIGH
2. tINYL = Input Pad-to-Y LOW
3. LVTTL delays are the same as CMOS delays.
4. For LP Macros, VDDP=2.3V for delays.
Table 1-27 • Worst-Case Commercial Conditions1
VDDP = 3.0V, VDD = 2.3V, TJ = 70°C
Parameter Description
Max.
UnitsStd. –F
tRCKH Input Low to High21.1 1.3 ns
tRCKL Input High to Low21.0 1.2 ns
tRCKH Input Low to High30.8 1.0 ns
tRCKL Input High to Low30.8 1.0 ns
Notes:
1. The timing delay difference between tile locations is less than 15ps.
2. Highly loaded row 50%.
3. Minimally loaded row.
Table 1-28 • Worst-Case Commercial Conditions
VDDP = 3.0V, VDD = 2.3V, TJ = 70°C
Parameter Description
Max.
UnitsStd. –F
tRCKSWH Maximum Skew Low to High 270 320 ps
tRCKSHH Maximum Skew High to Low 270 320 ps
ProASICPLUS Flash Family FP G As
v3.4 1-41
Module Delays
Sample Macro cell Library Listing
Figure 1-30 • Module Delays
Table 1-29 • Worst-Case Commercial Conditions1
VDD = 2.3V, TJ = 70º C
Cell Name Description
Standard –F
Max Min Max Min Units
NAND2 2-Input NAND 0.5 0.6 ns
AND2 2-Input AND 0.7 0.8 ns
NOR3 3-Input NOR 0.8 1.0 ns
MUX2L 2-1 MUX with Active Low Select 0.5 0.6 ns
OA21 2-Input OR into a 2-Input AND 0.8 1.0 ns
XOR2 2-Input Exclusive OR 0.6 0.8 ns
LDL Active Low Latch (LH/HL) LH20.9 1.1 ns
CLK-Q HL20.8 0.9
tsetup 0.7 0.8
thold 0.1 0.2
DFFL Negative Edge-Triggered D-type Flip-Flop (LH/HL)
CLK-Q LH20.9 1.1 ns
HL20.8 1.0
tsetup 0.6 0.7
thold 0.0 0.0
Notes:
1. Intrinsic delays have a variab l e compo nent , coupl ed to t he inp ut sl ope o f th e signal . These nu mber s assu me an input slo pe typica l of
local interconnect.
2. LH and HL refer to the Q transitions from Low to High and High to Low, respectively.
A
B
50%
Y
50%
50% 50%
50% 50%
DALH
C50% 50%
50%
50%
50%
DBLH
DAHL DBHL
DCHL
DCLH
50%
t
t
tt
t
t
A
B
CY
ProASICPLUS Flash Family FPGAs
1-42 v3.4
Table 1-30 • Recommended Operating Conditions
Parameter Symbol
Limits
Commercial/Industrial
Maximum Clo ck Frequency* fCLOCK 180 MHz
Maximum RAM Frequency* fRAM 150 MHz
Maximum Rise/Fall Time on Inputs*
• Schmitt Mode (10% to 90%)
• Non-schmitt Mode (10% to 90%) tR/tF
tR/tF
100 ns
10 ns
Maximum LVPECL Frequency* 180 MHz
Maximum tCK Frequency (JTAG) tCK 10 MHz
Note: *–F parts will be 20% slower than standard commercial devices.
Table 1-31 • Slew Rates Measured at C = 30pF, Nominal Power Supplies and 25°C
Type Tr ig. L evel R is ing Edge (nS) Slew R ate (V/nS) Falli ng Edge (nS) Slew Rate (V / nS) PCI Mode
OB33PH 10%-90% 1.60 1.65 1.65 1.60 Yes
OB33PN 10%-90% 1.57 1.68 3.32 0.80 No
OB33PL 10%-90% 1.57 1.68 1.99 1.32 No
OB33LH 10%-90% 3.80 0.70 4.84 0.55 No
OB33LN 10%-90% 4.19 0.63 3.37 0.78 No
OB33LL 10%-90% 5.49 0.48 2.98 0.89 No
OB25HH220%-60% 3.31 0.30 0.75 1.33 No
OB25HN220%-60% 3.20 0.32 0.77 1.30 No
OB25HL220%-60% 3.27 0.31 0.77 1.30 No
OB25LH220%-60% 8.41 0.12 1.38 0.72 No
OB25LN220%-60% 8.54 0.12 1.15 0.87 No
OB25LL220%-60% 8.50 0.12 1.19 0.84 No
OB25LPHH 10%-90% 1.55 1.29 1.56 1.28 No
OB25LPHN 10%-90% 1.70 1.18 2.08 0.96 No
OB25LPHL 10%-90% 1.97 1.02 2.09 0.96 No
OB25LPLH 10%-90% 3.57 0.56 3.93 0.51 No
OB25LPLN 10%-90% 4.65 0.43 3.28 0.61 No
OB25LPLL 10%-90% 5.52 0.36 3.44 0.58 No
Notes:
1. Standard and –F parts.
2. Please refer to the mixed-mode interfacing section in the I/O Features in ProASICPLUS Flash FPGAs application note for guidelines
and usage.
ProASICPLUS Flash Family FP G As
v3.4 1-43
Embe dde d M em or y Specifications
This section discusses ProASICPLUS SRAM/FIFO embedded
memory and its interface signals, including timing
diagrams that show the relationships of signals as they
pertain to single embedded memory blocks (Table 1-32).
Table 1-10 on page 1-20 shows basic SRAM and FIFO
configurations. Simultaneous Read and Write to the
same location m ust be done with care. On such access es
the DI bus is output to the DO bus.
Enclosed Timing Diagrams—SRAM Mode:
•"Synchronous SRAM Read, Access Timed Output
Strobe (Synch ronous Transp are nt)"
•"Synchronous SRAM Read, Pipeline Mode Outputs
(Synchronous Pipelined)"
•"Asynchronous SRAM Write"
•"Asynchronous SRAM Read, Address Controlled,
RDB=0"
•"Asynchro nous SRAM Read, RDB Controlled"
•"Synchrono us SRAM W r i te"
• Emb edd ed Memory Spec ifications
The difference between synchronous transparent and
pipeline modes is the timing of all the output signals
fro m th e mem ory. In tra nsp arent mod e, the out puts w ill
change within the same clock cycle to reflect the data
requested by the currently valid access to the memory. If
clock cycles are short (high clock speed), the data
require s mos t of the clock cycle t o change t o va lid values
(stable s ignals). Pro cessing of thi s data in th e same cl ock
cycle is nearly impossible. Most designers add registers at
all outputs of the memory to push the data processing
into the next clock cycle. An entire clock cycle can then
be used to process the data. To simplify use of this
memory setup, suitable registers have been
implemented as part of the memory primitive and are
available to the user in the synchronous pipeline mode.
In this mode, the output signals will change shortly af ter
the second rising edge, following the initiation of the
read ac ces s.
Table 1-32 • Memory Block SRAM Interface Signals
SRAM Signal Bit s In/Out Description
WCLKS 1 IN Write clock used on s ynchronization on write side
RCLKS 1 IN Read clock used on synchronization on read side
RADDR<0:7> 8 IN Read address
RBLKB 1 IN True read block select (active LOW)
RDB 1 IN True read pulse (active LOW)
WADDR<0:7> 8 IN Write address
WBLKB 1 IN Write block select (active LOW)
DI<0:8> 9 IN Input data bits <0:8>, <8> can be used for parity in
WRB 1 IN Ne gative true write puls e
DO<0:8> 9 OUT Output data bits <0:8>, <8> can be used for parity out
RPE 1 OUT Read parity error (active HIGH)
WPE 1 OUT Write parity error (active HIGH)
PARODD 1 IN Selects odd parity generation/detect when high, even when low
Note: Not all signals shown are used in all modes.
ProASICPLUS Flash Family FPGAs
1-44 v3.4
Synchronous SRAM Read, Access Timed Output Strobe (Synchronous Transparent)
Note: The plot shows the normal operation status.
Figure 1-31 • Synchronous SRAM Read, Access Timed Output Strobe (Synchronous Transparent)
Table 1-33 • TJ = 0°C to 110°C; VDD = 2.3V to 2.7V
Symbol txxx Description Min. Max. Units Notes
CCYC Cycle time 7.5 ns
CMH Clock high phase 3.0 ns
CML Clock low phase 3.0 ns
OCA New DO access from RCLKS ↑ 7.5 ns
OCH Old DO valid from RCLKS ↑ 3.0 ns
RACH RADDR hold from RCLKS ↑ 0.5 ns
RACS RADDR setup to RCLKS ↑ 1.0 ns
RDCH RDB hold from RCLKS ↑ 0.5 ns
RDCS RDB setup to RCLKS ↑ 1.0 ns
RPCA New RPE access from RCLKS ↑ 9.5 ns
RPCH Old RPE valid fr om RCLKS ↑ 3.0 ns
Note: – F speed grade devices are 20% slower than the standard numbers.
RADDR
RPE
DO
RCLKS
RBD, RBLKB
New Valid Data Out
Cycle Start
Old Data Out
New Valid
Address
tRACS
tRDCS
tRDCH
tRACH tOCH
tRPCH
tCMH
tOCA
tRPCA
tCCYC
tCML
ProASICPLUS Flash Family FP G As
v3.4 1-45
Synchronous SRAM Read, Pipeline Mode Outputs (Synchronous Pipelined)
Note: The plot shows the normal operation status.
Figure 1-32 • Synchronous SRAM Read, Pipeline Mode Outputs (Synchronous Pipelined)
Table 1-34 • TJ = 0°C to 110°C; VDD = 2.3V to 2.7V
Symbol txxx Description Min. Max. Units Notes
CCYC Cycle time 7.5 ns
CMH Clock high phase 3.0 ns
CML Clock low phase 3.0 ns
OCA New DO access from RCLKS ↑ 2.0 ns
OCH Old DO valid from RCLKS ↑ 0.75 ns
RACH RADDR hold from RCLKS ↑ 0.5 ns
RACS RADDR setup to RCLKS ↑ 1.0 ns
RDCH RDB hold from RCLKS ↑ 0.5 ns
RDCS RDB setup to RCLKS ↑ 1.0 ns
RPCA New RPE access from RCLKS ↑ 4.0 ns
RPCH Old RPE valid from RCLKS ↑ 1.0 ns
Note: – F speed grade devices are 20% slower than the standard numbers.
RCLKS
RPE
DO New Valid Data Out
Cycle Start
New RPE Out
RADDR New Valid
Address
RDB, RBLKB
tRACS tOCA
tRPCH
tOCH tRPCA
tCML
tCMH
tCCYC
tRACH
tRDCH
tRDCS
Old Data Out
Old RPE Out
ProASICPLUS Flash Family FPGAs
1-46 v3.4
Asynchronous SRAM Write
Note: The plot shows the normal operation status.
Figure 1-33 • Asynchronous SR AM Write
Table 1-35 • TJ = 0°C to 110°C; VDD = 2.3V to 2.7V
Symbol txxx Description Min. Max. Units Notes
AWRH WADDR hold from WB ↑ 1.0 ns
AWRS WADDR setup to WB ↓ 0.5 ns
DWRH DI hold from WB ↑ 1.5 ns
DWRS DI setup to WB ↑ 0.5 ns PARGEN is inactive
DWRS DI setup to WB ↑ 2.5 ns PARGEN is active
WPDA WPE access from DI 3.0 ns WPE is invalid while
PARGEN is active
WPDH WPE hold from DI 1.0 ns
WRCYC Cycle time 7.5 ns
WRMH WB high p hase 3.0 ns In activ e
WRML WB low phase 3.0 ns Active
Note: – F speed grade devices are 20% slower than the standard numbers.
WRB, WBLKB
WADDR
WPE
DI
tAWRS
tWPDA
tAWRH
tDWRS
tWRML tWRMH
tWRCYC
tWPDH
tDWRH
ProASICPLUS Flash Family FP G As
v3.4 1-47
Asynchronous SRAM Read, Address Controlled, RDB=0
Note: The plot shows the normal operation status.
Figure 1-34 • Asynch ronous SRAM Read , Addres s Controlle d, RDB=0
Table 1-36 • TJ = 0°C to 110°C; VDD = 2.3V to 2.7V
Symbol txxx Description Min. Max. Units Notes
ACYC Read cycle time 7.5 ns
OAA New DO access from RADDR stable 7.5 ns
OAH Old DO hold from RADDR stable 3.0 ns
RPAA New RPE access from RADDR stable 10.0 ns
RPAH Old RPE hold from RADDR stable 3.0 ns
Note: – F speed grade devices are 20% slower than the standard numbers.
RPE
DO
RADDR
tOAH
tRPAH tOAA
tRPAAtACYC
ProASICPLUS Flash Family FPGAs
1-48 v3.4
Asynchronous SRAM Read, RDB Controlled
Note: The plot shows the normal operation status.
Figure 1-35 • As ynchronous SRA M Read, RDB Controlled
Table 1-37 • TJ = 0°C to 110°C; VDD = 2.3V to 2.7V
Symbol txxx Description Min. Max. Units Notes
ORDA New DO access from RB ↓7.5 ns
ORDH Old DO valid from RB ↓3.0 ns
RDCYC Read cycle time 7.5 ns
RDMH RB high phase 3.0 ns Inactive setup to new cycle
RDML RB low phase 3.0 ns Active
RPRDA New RPE access from RB ↓9.5 ns
RPRDH Old RPE valid from RB ↓3.0 ns
Note: – F speed grade devices are 20% slower than the standard numbers.
RB=(RDB+RBLKB)
RPE
DO
tORDH
tORDA
tRPRDA
tRDMLtRDCYC
tRDMH
tRPRDH
ProASICPLUS Flash Family FP G As
v3.4 1-49
Synchronous SRAM Write
Note: The plot shows the normal operation status.
Figure 1-36 • Synchronous SRAM Write
Table 1-38 • TJ = 0°C to 110°C; VDD = 2.3V to 2.7V
Symbol txxx Description Min. Max. Units Notes
CCYC Cycle time 7.5 ns
CMH Clock high phase 3.0 ns
CML Clock low phase 3.0 ns
DCH DI hold from WCLKS ↑ 0.5 ns
DCS DI setup to WCLKS ↑ 1.0 ns
WACH WADDR hold from WCLKS ↑ 0.5 ns
WDCS WADDR setup to WCLKS ↑ 1.0 ns
WPCA New WPE access from WCLKS ↑ 3.0 ns WPE is invalid while
PARGEN is active
WPC H Old WP E va l i d fr om WCLKS ↑ 0.5 ns
WRCH, WBCH WRB & WBLKB hold from WCLKS ↑ 0.5 ns
WRCS, WBCS WRB & WBLKB setup to WCLKS ↑ 1.0 ns
Notes:
1. On simultaneous read and write accesses to the same location DI is output to DO.
2. –F speed grade devices are 20% slower than the standard numbers.
WCLKS
WPE
WADDR, DI
WRB, WBLKB
Cycle Start
tWRCH, tWBCH
tWRCS, tWBCS
tDCS, tWDCStWPCH
tDCH, tWACH tWPCA
tCMH tCML
tCCYC
ProASICPLUS Flash Family FPGAs
1-50 v3.4
Synchronous Write and Read to the Same Location
Note: The plot shows the normal operation status.
Figure 1-37 • Synchronous Write and Read to the Sam e Location
Table 1-39 • TJ = 0°C to 110°C; VDD = 2.3V to 2.7V
Symbol txxx Description Min. Max. Units Notes
CCYC Cycle time 7.5 ns
CMH Clock high phase 3.0 ns
CML Clock low phase 3.0 ns
WCLKRCLKS WCLKS ↑to RCLK S ↑setup time – 0.1 ns
WCLKRCLKH WCLKS ↑to RCLKS ↑hold time 7.0 ns
OCH Old DO valid from RCLKS ↑3.0 ns OCA/OCH displayed for
Access Timed Output
OCA New DO valid from RCLKS ↑7.5 ns
Note:
1. This beh avio r is valid fo r Acce ss Tim ed Outpu t and Pipel ine d Mode O utput. The ta ble shows th e timing s of a n Acces s Timed Ou tput.
2. During synchronous write and synchronous read access to the same location, the new write data will be read out if the active write
clock edge occurs before or at the same time as the active read clock edge. The negative setup time insures this behavior for WCLKS
and RCLKS driven by the same design signal.
3. I f WCLKS changes after the hold time, the data will be read.
4. A setup or hold time violation will result in unknown output data.
5. –F speed grade devices are 20% slower than the standard numbers.
* New data is read if WCLKS ↑occurs before se tup ti me.
The data stored is read if WCLKS ↑occurs after hold time.
RCLKS
DO
WCLKS
tWCLKRCLKH
New Data*
Last Cycle Data
tWCLKRCLKS
tOCH
tCCYC
tCMH tCML
tOCA
ProASICPLUS Flash Family FP G As
v3.4 1-51
Asynchronous Write and Synchronous Read to the Same Location
Note: The plot shows the normal operation status.
Figure 1-38 • Asynchronous Write and Synchronous Read to the Same Location
Table 1-40 • TJ = 0°C to 110°C; VDD = 2.3V to 2.7V
Symbol txxx Description Min. Max. Units Notes
CCYC Cycle time 7.5 ns
CMH Clock high phase 3.0 ns
CML Clock low phase 3.0 ns
WBRCLKS WB ↓to RCLKS ↑setup time –0.1 ns
WBRCLKH WB ↓to RCLKS ↑ hold time 7.0 n s
OCH Old DO valid from RCLKS ↑3.0 ns OCA/OCH displayed for
Access Timed Output
OCA New DO valid from RCLKS ↑7.5 ns
DWRRCLKS DI to RCLKS ↑ setup time 0 ns
DWRH DI to WB ↑ hold time 1.5 ns
Notes:
1. This beh avio r is valid fo r Acce ss Tim ed Outpu t and Pipel ine d Mode O utput. The ta ble shows th e timing s of a n Acces s Timed Ou tput.
2. In asynchronous write and synchronous read access to the same location, the new write data will be read out if the active write
signal edge occurs before or at the same time as the active read clock edge. If WB changes to low after hold time, the data will be
read.
3. A setup or hold time violation will result in unknown output data.
4. –F speed grade devices are 20% slower than the standard numbers.
* New data is read if WB ↓occurs before setup time.
The stored data is read if WB ↓occurs after hold time.
WB = {WRB + WBLKB}
RCLKS
DO
tBRCLKH
New Data*
Last Cycle Data
tWRCKS
tOCH
tOCA
DI
tDWRRCLKS tDWRH
tCCYC
tCMH tCML
ProASICPLUS Flash Family FPGAs
1-52 v3.4
Asynchronous Write and Read to the Same Location
Note: The plot shows the normal operation status.
Figure 1-39 • Asynchronous Write and Read to the Same Location
Table 1-41 • TJ = 0°C to 110°C; VDD = 2.3V to 2.7V
Symbol txxx Description Min. Max. Units Notes
ORDA New DO access from RB ↓7.5 ns
ORDH Old DO valid from RB ↓3.0 ns
OWRA New D O access from WB ↑3.0 ns
OWRH O ld DO valid from WB ↑0.5 ns
RAWRS RB ↓or RADDR from WB ↓5.0 ns
RAWRH RB ↑or RADDR fr om WB ↑5.0 ns
Notes:
1. During an asynchronous read cycle, each write operation (synchronous or asynchronous) to the same location will automatically
trigger a read operation which updates the read data.
2. Violation or RAWRS will disturb access to the OLD data.
3. Vio lation of RAWRH will disturb access to the NEWER data.
4. –F speed grade devices are 20% slower than the standard numbers.
RB, RADDR
OLD NEWERNEW
tORDA
tORDH
tOWRH
tRAWRH
WB = {WRB+WBL KB}
DO
tOWRA
tRAWRS
ProASICPLUS Flash Family FP G As
v3.4 1-53
Synchronous Write and Asynchronous Read to the Same Location
Note: The plot shows the normal operation status.
Figure 1-40 • Synchronous Write and Asynchronous Read to the Same Locat ion
Table 1-42 • TJ = 0°C to 110°C; VDD = 2.3V to 2.7V
Symbol txxx Description Min. Max. Units Notes
ORDA New DO access from RB ↓7.5 ns
ORDH Old DO valid from RB ↓3.0 ns
OWRA New DO access from WCLKS ↓3.0 ns
OWRH O ld DO valid from WCLKS ↓0.5 ns
RAWCLKS RB ↓or RADDR from WCLKS ↑5.0 ns
RAWCLKH RB ↑or RADDR from WCL KS ↓5.0 ns
Notes:
1. During an asynchronous read cycle, each write operation (synchronous or asynchronous) to the same location will automatically
trigger a read operation which updates the read data.
2. Vio lation of RAWCLKS will disturb access to OLD data.
3. Violation of RAWCLKH will disturb access to NEWER data.
4. –F speed grade devices are 20% slower than the standard numbers.
RB, RADDR
OLD NEW NEWER
tORDA
tORDH
tRAWCLKS
tRAWCLKH
WCLKS
DO
tOWRH
tOWRA
ProASICPLUS Flash Family FPGAs
1-54 v3.4
Asynchronous FIFO Full and Empty Transitions
The asynchronous FIFO accepts writes and reads while
not full or not empty. When the FIFO is full, all write s are
inhibited. Conversely, when the FIFO is empty, all reads
are inh ibited. A pr oblem is c reated if the FIFO is writte n
during the transition out of full to not full or read during
the tran sition out of em pty to not em pt y. Th e exact time
at which the write or read operation changes from
inhibited to accept ed after the re ad (write) signa l which
causes the transition from full or empty to not full or not
empty i s indeterminat e. This inde terminate per iod starts
1 ns after the RB (WB) transition, which deactivates full
or not empty and ends 3 ns after the RB (WB) transition
for slow cycles. For fast cycles, the indeterminate period
ends 3 ns (7.5 ns – RDL (WRL)) after the RB (WB)
tra n s ition , whichever is l a ter (Table 1-1 on pag e 1-6).
The timing diagram for write is shown in Figure 1-38 on
page 1-51. The timing diagram for read is shown in
Figure 1-39 on page 1-52. For basic SRAM configurations,
see Tabl e 1-1 1 on page 1-22.
Enclosed Timing Diagrams – FIFO Mode:
•"Asynchronous FIFO Read"
•"Asynchronous FIFO Write"
•"Synchronous FIFO Read, Access Timed Output
Strob e (Synchr onous Transparen t) "
•"Synchronous FIFO Read, Pipeline Mode Outputs
(Synchro nous Pip el ined) "
•"Synchr onous FIFO Write"
•"FIFO Reset"
Table 1-43 • Memory Block FIFO Interface Signals
FIFO Signal Bits In/Out Description
WCLKS 1 IN Write clock used for synchronization on write side
RCLKS 1 IN Read clock used for synchronization on read side
LEVEL <0:7>* 8 IN Direct configuration implements static flag logic
RBLKB 1 IN Read block select (active LOW)
RDB 1 IN Read pulse (active LOW)
RESET 1 IN Reset for FIFO pointers (active LOW)
WBLKB 1 IN Write block select (active LOW)
DI<0:8> 9 IN Input data bits <0:8>, <8> will be generated if PARGEN is true
WRB 1 IN Write pulse (active LOW)
FULL, EMPTY 2 OUT FIFO flags. FULL prevents write and EMPTY prevents read
EQTH, GE QTH* 2 OUT EQTH is true wh en th e FIFO holds the number of word s specified by the LEVEL signal.
GEQTH is true when the FIFO holds (LEVEL) words or more
DO<0:8> 9 OUT Output data bits <0:8>
RPE 1 OUT Read parity error (active HIGH)
WPE 1 OUT Write parity error (active HIGH)
LGDEP <0:2> 3 IN Configures DEPTH of the FIFO to 2 (LGDEP+1)
PARODD 1 IN Selects odd parity generation/detect when high, even when low
Note: *LEVEL is always eight bits (0000.0000, 0000.0001). That means for values of DEPTH greater than 256, not all values will be
possible, e.g. for DEPTH=512, the LEVEL can onl y have the values 2, 4, . . ., 512. The L EVEL signal circuit will generate signals that
indi cate whether the FIFO is exactly filled to the value of LEVEL (EQTH) or filled equal or higher (GEQTH) than the specified LEVEL.
Since counting starts at 0, EQTH will become true when the FIFO holds (LEVEL+1) words for 512-bit FIFOs.
ProASICPLUS Flash Family FP G As
v3.4 1-55
Note: –F speed grade devices are 20% slower than the standard numbers.
Figure 1-41 • Write Timing Diagram
Note: –F speed grade devices are 20% slower than the standard numbers.
Figure 1-42 • Read Timing Diagram
Write acceptedWrite inhibited
FULL
RB
Write
cycle
1 ns
3 ns
WB
Read acceptedRead inhibited
EMPTY
WB
Read
cycle
1 ns
3 ns
RB
ProASICPLUS Flash Family FPGAs
1-56 v3.4
Asynchronous FIFO Read
Note: The plot shows the normal operation status.
Figure 1-43 • As ynchronous FIFO Read
Table 1-44 • TJ = 0°C to 110°C; VDD = 2.3V to 2.7V
Symbol txxx Description Min. Max. Units Notes
ERDH, FRDH,
THRDH Old EMPTY, FULL, EQTH, & GETH valid hold
time from RB ↑0 .5 ns Emp ty/fu ll/thr esh ar e invali d fr om the end of
hold until the new access is complete
ERDA New EMPTY access from RB ↑3.01ns
FRDA FULL↓ access from RB ↑3.01ns
ORDA New DO access from RB ↓7.5 ns
ORDH Old DO valid from RB ↓3.0 ns
RDCYC Read cycle time 7.5 ns
RDWRS WB ↑, clearing EMPTY, setup to
RB ↓3.02ns Enabling the read operation
1.0 ns Inhibiting the read operation
RDH RB high phase 3.0 ns Inactive
RDL RB low phase 3.0 ns Active
RPRDA New RPE access from RB ↓9.5 ns
RPRDH Old RPE valid from RB ↓4.0 ns
THRDA EQTH or GETH access from RB↑4.5 ns
Notes:
1. At fast cycles, ERDA and FRDA = MAX (7.5 ns – RDL), 3.0 ns.
2. A t fast cycles, RDWRS (for enabling read) = MAX (7. 5 ns – WRL), 3.0 ns.
3. –F speed grade devices are 20% slower than the standard numbers.
RB = (RDB+RBLKB)
RPE
RDATA
EMPTY
EQTH, GETH
FULL
(Empty inhibits read)
Cycle Start
WB
tRDWRS tERDH, tFRDH
tERDA, tFRDA
tTHRDH
tORDH
tRPRDH tORDA
tRPRDA
tRDL tRDH
tRPRDA
tRDL tRDCYC
tRDH
tTHRDA
ProASICPLUS Flash Family FP G As
v3.4 1-57
Asynchronous FIFO Write
Note: The plot shows the normal operation status.
Figure 1-44 • Asynchronous FIFO Write
Table 1-45 • TJ = 0°C to 110°C; VDD = 2.3V to 2.7V
Symbol txxx Description Min. Max. Units Notes
DWRH DI hold from WB ↑ 1.5 ns
DWRS DI setup to WB ↑ 0.5 ns PARGEN is inactive
DWRS DI setup to WB ↑ 2.5 ns PARGEN is active
EWRH, FWRH,
THWRH Old EMPTY, FULL, EQTH, & GETH valid hold
time after WB ↑0.5 ns Empty/full/thresh are invalid from the end
of hold until the new access is complete
EWRA EMPTY ↓ access from WB ↑ 3.01ns
FWRA New FULL access from WB ↑3.01ns
THWRA EQTH or GETH access from WB ↑4.5 ns
WPDA WPE access from DI 3.0 ns WPE is invalid while PARGEN is active
WPDH WPE hold from DI 1.0 ns
WRCYC Cycle time 7.5 ns
WRRDS RB ↑, clearing FULL, setup to
WB ↓3.02ns Enabling the write operation
1.0 Inhibiting the write operation
WRH WB high p hase 3.0 ns I nactiv e
WRL WB lo w phase 3.0 ns Active
Notes:
1. At fast cycles, EWRA , FWRA = MAX (7.5 ns – WRL), 3.0 ns.
2. A t fast cycles, WRRDS (for enabling write) = MAX (7.5 ns – RDL), 3.0 ns.
3. –F speed grade devices are 20% slower than the standard numbers.
WPE
WDATA (Full inhibits write)
WB = (WRB+WBLKB)
EMPTY
EQTH, GETH
FULL
Cycle Start
RB
tWRRDS tDWRH
tWPDH
tWPDA
tDWRS
tEWRH, tFWRH
tEWRA, tFWRA tTHWRH
tTHWRA
tWRH
tWRL tWRCYC
ProASICPLUS Flash Family FPGAs
1-58 v3.4
Synchronous FIFO Read, Access Timed Output Strobe (Synchronous Transparent)
Note: The plot shows the normal operation status.
Figure 1-45 • Synchronous FIFO Read, Access Timed Output Strobe (Synchronous Transparent)
Table 1-46 • TJ = 0°C to 110°C; VDD = 2.3V to 2.7V
Symbol txxx Description Min. Max. Units Notes
CCYC Cycle time 7.5 ns
CMH Clock high phase 3.0 ns
CML Clock low phase 3.0 ns
ECBA New EMPTY access from RCLKS ↓3.01ns
FCBA FULL ↓ access from RCLKS ↓ 3.01ns
ECBH, FCBH,
THCBH Old EMPTY, FULL, EQTH, & GETH valid hold
time from RCLKS ↓1.0 ns Empty/full/thresh are invalid from the end
of hold until the new access is complete
OCA New DO access from RCLKS ↑7.5 ns
OCH Old DO valid from RCLKS ↑ 3.0 ns
RDCH RDB hold from RCLKS ↑ 0.5 ns
RDCS RDB setup to RCLKS ↑ 1.0 ns
RPCA New RPE access from RCLKS ↑ 9.5 ns
RPCH Old RPE valid from RCLKS ↑ 3.0 ns
HCBA EQTH or GETH access from RCLKS ↓ 4.5 ns
Notes:
1. At fast cycles, ECB A and FCBA = MAX (7.5 ns – CMH), 3.0 ns.
2. –F speed grade devices are 20% slower than the standard numbers.
RCLK
RPE
RDATA
EMPTY
EQTH, GETH
FULL
RDB
tRDCH
tOCH
tRPCH
tRDCS
Old Data Out New Valid Data Out (Empty Inhibits Read)
Cycle Start
tECBH, tFCBH
tECBA, tFCBA
tOCA
tRPCA
tCMH tCML
tCCYC
tTHCBH
tHCBA
ProASICPLUS Flash Family FP G As
v3.4 1-59
Synchronous FIFO Read, Pipeline Mode Outputs (Synchronous Pipelined)
Note: The plot shows the normal operation status.
Figure 1-46 • Synchronous FIFO Read, Pipeline Mode Outputs (Synchronous Pipelined)
Table 1-47 • TJ = 0°C to 110°C; VDD = 2.3V to 2.7V
Symbol txxx Description Min. Max. Units Notes
CCYC Cycle time 7.5 ns
CMH Clo ck high phase 3.0 ns
CML Clo ck low phase 3.0 ns
ECBA New EMPTY access from RCLKS ↓ 3.01ns
FCBA FULL ↓ access from RCLKS ↓ 3.01ns
ECBH, FCBH,
THCBH Old EMPTY, FULL, EQTH, & GETH valid hold
time fr om RCLKS ↓ 1.0 ns Empty/full/thresh are invalid from the end of
hold until the new access is complete
OCA New DO access from RCLKS ↑ 2.0 ns
OCH Old DO valid from RCLKS ↑ 0.75 ns
RDCH RDB hold from RCLKS ↑ 0.5 ns
RDCS RDB setup to RCLKS ↑ 1.0 ns
RPCA N ew RPE access from RCLKS ↑ 4.0 ns
RPCH Old RPE valid from RCLKS ↑ 1.0 ns
HCBA EQTH or GETH access from RCLKS ↓ 4.5 ns
Notes:
1. At fast cycles, ECBA and FCBA = MAX (7.5 ns – CMS) , 3.0 ns.
2. –F speed grade devices are 20% slower than the standard numbers.
RCLK
RPE
RDATA
EMPTY
EQTH, GETH
FULL
Old Data Out New Valid Data Out
RDB
Cycle Start
Old RPE Out New RPE Out
tECBH, tFCBH
tRDCH
tRDCS
tOCA
tECBA, tFCBA
tTHCBH
tHCBA
tCMH tCML
tCCYC
tRPCH
tOCH
tRPCA
ProASICPLUS Flash Family FPGAs
1-60 v3.4
Synchronous FIFO Write
Note: The plot shows the normal operation status.
Figure 1-47 • Synchronous FIFO Write
Table 1-48 • TJ = 0°C to 110°C; VDD = 2.3V to 2.7V
Symbol txxx Description Min. Max. Units Notes
CCYC Cycle time 7.5 ns
CMH Clock high phase 3.0 ns
CML Clock low phase 3.0 ns
DCH DI hold from WCLKS ↑ 0.5 ns
DCS DI setup to WCLKS ↑ 1.0 ns
FCBA New FULL access from WCLKS ↓3.01ns
ECBA EMPTY↓ access from WCLKS ↓ 3.01ns
ECBH,
FCBH,
HCBH
Old EMPTY, FULL, EQTH, & GETH valid hold
time from WCLKS ↓1.0 ns Empty/full/thresh are invalid from the end of
hold until the new access is complete
HCBA EQTH or GETH access from WCLKS ↓ 4.5 ns
WPCA New WPE access from WCLKS ↑ 3.0 ns WPE is invalid while
PARGEN is active
WPC H Old WP E va l i d fr om WCLKS ↑ 0.5 ns
WRCH, WBCH WRB & WBLKB hold from WCLKS ↑ 0.5 ns
WRCS, WBCS WRB & WBLKB setup to WCLKS ↑ 1.0 ns
Notes:
1. At fast cycles, ECB A and FCBA = MAX (7.5 ns – CMH), 3.0 ns.
2. –F speed grade devices are 20% slower than the standard numbers.
WCLKS
WPE
DI
EMPTY
EQTH, GETH
FULL
(Full Inhibits Write)
WRB, WBLKB
Cycle Start
tWRCH, tWBCH tECBH, tFCBH
tECBA, tFCBA
tHCBA
tWRCS, tWBCS
tDCS
tWPCA
tCMH tCML
tCCYC
tWPCH
tDCH
tHCBH
ProASICPLUS Flash Family FP G As
v3.4 1-61
FIFO Reset
Note: *The plot shows the normal operation status.
Figure 1-48 • FIFO Reset
Table 1-49 • TJ = 0°C to 110°C; VDD = 2.3V to 2.7V
Symbol txxx Description Min. Max. Units Notes
CBRSH WCLKS or RCLKS ↑ hold from RESETB ↑ 1.5 ns Synchr ono us mode only
CBRSS WCLKS or RCLKS ↓ setup to RESETB ↑ 1.5 ns Synch r ono us mode only
ERSA New EMPTY ↑ access from RESETB ↓ 3.0 ns
FRSA FULL ↓ access from RESETB ↓ 3.0 ns
RSL RESETB low phase 7.5 ns
THRSA EQTH or GETH access from RESETB ↓ 4.5 ns
WBRSH WB ↓ hold from RESETB ↑ 1.5 ns Asynchronous mode only
WBRSS WB ↑ setup to RESETB ↑ 1.5 ns Asynchronous mode only
Note: – F speed grade devices are 20% slower than the standard numbers.
RESETB
EMPTY
EQTH, GETH
FULL
WB* Cycle Start
Cycle Start
WCLKS, RCLKS
tERSA, tFRSA
tTHRSA
tCBRSS
tWBRSS
tCBRSH
tWBRSH
tRSL
ProASICPLUS Flash Family FPGAs
1-62 v3.4
Asynchronous FIFO Full and Empty Transitions
The asynchronous FIFO accepts writes and reads while
not full or not empty. When the FIFO is full, all write s are
inhibited. Conversely, when the FIFO is empty, all reads
are inh ibited. A pr oblem is c reated if the FIFO is writte n
during the transition out of full to not full or read during
the tran sition out of em pty to not em pt y. Th e exact time
at which the write or read operation changes from
inhibited to accept ed after the re ad (write) signa l which
causes the transition from full or empty to not full or not
empty i s indeterminat e. This inde terminate per iod starts
1 ns after the RB (WB) transition, which deactivates full
or not empty and ends 3 ns after the RB (WB) transition
for slow cycles. For fast cycles, the indeterminate period
ends 3 ns (7.5 ns – RDL (WRL)) after the RB (WB)
tra n s ition , whichever is l a ter (Table 1-43 on page 1-54).
The timing diagram for write is shown in Figure 1-41 on
page 1-55. The timing diagram for read is shown in
Figure 1-42 on page 1-55. For basic SRAM configurations,
see Tabl e 1-1 1 on page 1-22.
Enclosed Timing Diagrams – FIFO Mode:
• Asynchronous FIFO Read
• Asynchronous FIFO Write
• Synchronous FIFO Read, Access Timed Output
Strob e (Synchr onous Transparen t)
• Synchronous FIFO Read, Pipeline Mode Outputs
(Synchro nous Pip el ined)
• Synchr onous FIFO Wr it e
• FIFO Reset
ProASICPLUS Flash Family FP G As
v3.4 1-63
Pin Description
User Pins
I/O User Input/Output
The I/O pin functions as an input, output, tristate, or
bidirectional buffer. Input and output signal levels are
compatible with standard LVTTL and LVCMOS
specifications. Unused I/O pins are configured as inputs
with pull-up resistors.
NC No Connec t
To maintain compatibility with other Actel ProASICPLUS
products, it is recommended that this pin not be
co nnect e d to t h e circuitr y o n the boar d.
GL Global Pin
Low skew i nput pin for clock or other global signals. Th is
pin can be configured with an internal pull-up resistor.
When it is not connected to the global network or the
clock condi tioning circu it, it can be configured and used
as a normal I/O.
GLMX Global Multip lexing Pin
Low skew i nput pin for clock or other global signals. Th is
pin can be used in one of two special ways: (Please see
Actel’s ProASICPLUS Clock Conditioning Circuits
applica tion not e for det ails).
1. When the external feedback option is selected for the
PLL block , this pin is routed as the external feed back
source to the clock condit ion ing circu it.
2. In app lications whe re two different signa ls access the
same global net (but at different times) through the
use of GLMXx and GLMXLx macros, this pin will be
fixed as one of the source pins.
This pin can be configured with an internal pull-up
resistor. When it is not connected to the global network
or the clock condi tioning circuit, it can be configured and
used as any normal I/O. If not used, a global will be
configured as an input with pull-up.
Dedicated Pins
GND Ground
Common gr ound supply voltage .
VDD Logic Array Power Supply Pin
2.5V suppl y vol ta ge.
VDDP I/O Pad Po w er Supply Pin
2.5V or 3.3V supply voltage.
TMS Test Mo de Select
The TMS pin controls the use of boundary-scan circuitry.
This pin has an inte rna l pull-up resisto r.
TCK Test Clock
Clo ck in put pin f or bound ary s c an (max imu m 10 MHz ). Actel
recommends adding a nominal 20kΩ pull-up resistor to this
pin.
TDI Test Data In
Serial input for boundary scan. A dedicated pull-up
resistor is included to pull this pin high when not being
driven.
TDO Test Data Out
Serial output for boundary scan. Actel recommends
adding a nomin al 20k Ω pull-up resistor to this pin.
TRST Test Reset Input
Asynchronous, active low input pin for resetting
boundary-scan circuitry. This pin has an internal pull-up
resistor.
Special Function Pins
RCK Running Cl ock
A free running clock is needed during programming if
the programmer cannot guarantee that TCK will be
uninterrupted. If not used, this pin has an internal pull-
up and can be lef t floating.
NPECL User Negative Input
Provides high speed clock or data signals to the PLL
block. If unused, le ave the pin unc onnected.
PPECL User Positive Input
Provides high speed clock or data signals to the PLL
block. If unused, le ave the pin unc onnected.
AVD D PLL Power S uppl y
Analog VDD should be VDD (core vol tage) 2.5V (nomina l)
and be decoupled from GND with suitable decoupling
capacitors to reduce noise. For more information, refer
to Actel’s Using ProASICPLUS Clock Conditioning Circuits
application note. If the PLLs or clock conditioning
circuitry are not used in a design, AVDD should be tied
high (2.5V norma l).
AGND PLL Power Ground
Analog GND should be 0V and be decoupled from GND
with suitable decoupling capacitors to reduce noise. For
more information, refer to Actel’s ProASICPLUS Clock
Conditioning Circuits application note. If the PLLs or
clock conditioning circuitry are not used in a design,
AGND should be tied to GND.
ProASICPLUS Flash Family FPGAs
1-64 v3.4
VPP Programming Supply Pin
This pin may be co nnected to any voltage betwe en GND
and 16.5V during normal operation, or it can be left
unconnected.1 For information on using this pin during
programming, see the Performing Internal In-System
Programming Using Actel’s ProASICPLUS Devices
application note. Actel recommends floating the pin or
connecting it t o VDDP.
VPN Programming Supply Pin
This pin may be co nnected to any voltage be tween GND
and –13.8V during normal operation, or it can be left
unconnected.2 For information on using this pin during
programming, see the Performing Internal In-System
Programming Using Actel’s ProASICPLUS Devices
application note. Actel recommends floating the pin or
co nnecting it t o GND.
Recommended Design Practice for VPN/VPP
ProASICPLUS Devices – APA450, APA600,
APA750, APA1000
Byp ass cap acito rs are requ ired from V PP to GND and VPN
to GND for all ProASICPLUS devices during progr amming.
During the erase cycle, ProASICPLUS devices may have
current surges on the VPP and VPN power supplies. The
only way to maintain the integrity of the power
distribution to the ProASICPLUS device during these
current surges is to counteract the inductance of the
finite lengt h c onductors that dis tr ibute th e power to the
device. This can be accomplished by providing sufficient
bypass capacitance between the VPP and VPN pins and
GND (using the shortest paths possible). Without
sufficient bypass capacitance to counteract the
inductance, the VPP and VPN pins may incur a voltage
spike bey ond the volt age that the device ca n withstand.
This issue ap plies to al l progr am m ing configuration s.
The power supply voltage limits are defined in the
"Supply Voltages" on page 1-30. The solution prevents
spikes from damaging the ProASICPLUS devices. Bypass
capacitors are required for the VPP and VPN pads. Use a
0.01 µF to 0. 1 µF ceramic cap acito r with a 25 V or greater
rating. To filter low-frequency noise (decoupling), use a
4.7 µF (low ESR, <1 <Ω, tantalum, 25V or greater ra ting)
capacitor. The capacitors should be located as close to
the device pins as possible (within 2.5cm is desirable).
The smaller, high-frequency capacitor should be placed
closer to the device pins than the larger low-frequency
capacitor. The same dual capacit or circuit should be use d
on both the VPP and VPN pins (Figure 1-49 on pag e 1-64).
ProASICPLUS Devices – APA075, APA150,
APA300
These devices do not require bypass capacitors on the VPP
and VPN pins as long as the total combined distance of
the programming cable and the trace length on the
board is less than or equal to 30 inches. Note: For trace
lengths greater than 3 0 inches, u se the byp ass capacitor
recommendations in the previous section.
1. There is a nominal 40kΩ pull-up resistor on VPP.
2. There is a nominal 40kΩ pull-down resistor on VPN.
(See the "Recommended Design Practice for VPN/VPP" on page 1-64)
Figure 1-49 • ProASICPLUS VPP and VPN Capacitor Requirements
2.5cm
0.1µF
or
0.01µFProgramming
Header
or
Supplies
4.7µF
Actel
ProASIC
Device
+
+
+
_
VPP
VPN +
_
0.1µF
or
0.01µF4.7µF
PLUS
