MT5C2564 883C 54K x 4 SRAM 64K x 4 SRAM AVAILABLE AS MILITARY SPECIFICATIONS * SMD 5962-88545, SMD 5962-88681 * MIL-STD-883 FEATURES Ultra high speed: 12, 15ns High speed: 20, 25, 35 and 45ns Battery backup: 2V data retention Low power standby High-performance, low-power, CMOS double-metal process Single +5V (10%) power supply Easy memory expansion with CE All inputs and outputs are TTL compatible OPTIONS MARKING * Timing 12ns access (Contact factory) -12 15ns access -15 20ns access -20 25ns access -25 35ns access -35 45ns access -45 55ns access -55* 7Ons access -70* Packages Ceramic DIP (300 mil) C No. 106 Ceramic LCC EC No. 204 * 2V data retention, low power standby L Electrical characteristics identical to those provided for the 45ns access devices. GENERAL DESCRIPTION The Austin Semiconductor SRAM family employs high- speed, low-power CMOS designs using a four-transistor memory cell. Austin Semiconductor SRAMs are fabricated using double-layer metal, double-layer polysilicon tech- nology. For flexibility in high-speed memory applications, Aus- tin Semiconductor offers chip enable (CE) on all organiza- tions. This enhancementcan place the outputs in High-Z for additional flexibility insystem design. The x1 configuration features separate data input and output. PIN ASSIGNMENT (Top View) 24-Pin DIP 28-Pin LCC (D-9) (C-11) 22289 aod1-2allvec 32. one Aif2 23fAi15 ene A243 22a Aa Asa 2111A13 A13 A4U5 20/12 Al2 ase 19[lait Ato Asl7 18fA10 pas A7Us 1i7fpa4 bas agg tel/pa3 tne poe Agtio 15 pa2 13914151617 CEq11 140Da01 Qagws VssQ12 190WE S Writing to these devices is accomplished when write enable (WE) and CE inputs are both LOW. Reading is accomplished when WE remains HIGH and CE goes LOW. The device offers a reduced power standby mode when disabled. This allows system designs to achieve low standby power requirements. The L version provides an approximate 50 percent reduction in CMOS standby current (Isbc2) over the stan- dard version. All devices operate froma single +5V power supply and all inputs and outputs are fully TTL compatible. MTSC2564 363C REV 397 Dscod324 1-41 Austin Semiconductor inc reserves the nght to change products or specifications wihout notceAUSTIN SEMICONDUCTOR. INC Pines) Eke 64K x 4 SRAM FUNCTIONAL BLOCK DIAGRAM Vec GND Aro A _ DQ4 A -_ o 4 O 5 A) 8 262,144-BIT E O 144- Wd ) memory array J Aa _ = Oo ae) | Oo Q O Q Aa A L{ e r- CE O a, | (LSB) * LC WE COLUMN DECODER (LSB) POWER ttt tt t pt p Ce A A A A A A A A TRUTH TABLE MODE CE WE pa POWER STANDBY H x HIGH-Z STANDBY READ L H Q ACTIVE WRITE L L D ACTIVE MT5C 2564 663C 1 42 4ushn Semeconductcr Inc reserv2s ine nant to change products cr specitcet ons snthout nance REV 3/97 - Gsace2s\USTIN SEMICONDUCEOR, INC. MIT5C2564 883C 64K x 4 SRAM ABSOLUTE MAXIMUM RATINGS* Voltage on Any Input or DQ Relative to Vss.... -2V to +7V Voltage on Vcc Supply Relative to Vss.............. -1V to +7V Storage Temperature oo... cccscceseesssseesssesseees -65C to +150C Power Dissipation. 0.0.0... ccccsceesssesssectenessestenseeseentnsensese 1W Short Circuit Output Current .....0....0- 50mMA Lead Temperature (soldering 10 seconds)............. +260C Junction Temperatule ........cc cece eceeseeeneeeeneetentens +175C *Stresses greater than those listed under Absolute Maxi- mum Ratings may cause permanent damage to the device. This is a stress rating only and functional operation of the device at these or any other conditions above those indi- cated in the operational sections of this specification is not implied. Exposure to absolute maximum rating conditions for extended periods may affect reliability. ELECTRICAL CHARACTERISTICS AND RECOMMENDED DC OPERATING CONDITIONS (-55C < Tg < 125C; Veo = 5V + 10%) DESCRIPTION CONDITIONS SYMBOL MIN MAX UNITS NOTES Input High (Logic 1) Voltage Vin 2.2 Vcc+1.0 v 1 Input Low (Logic 0) Voltage VIL -0.5 0.8 Vv 1,2 Input Leakage Currert OV < Vin s Vcc Iu 5 5 HA Output Leakage Current Outputs Disabled ILo 5 5 HA OV < Vout < Vec Output High Voltage loH = -4.0MA Vou 2.4 Vv 1 Output Low Voltage lo. = 8.0MA VoL 0.4 Vv 1 MAX DESCRIPTION CONDITIONS SYMBOL | -15 | -20 | -25 | -35 | -45 UNITS NOTES Power Supply CE < Vit; Voc = MAX Current: Operating f = MAX = 1/"RC (MIN) Icc 165 | 150 | 140 | 130 | 120 mA 3 Output Open Power Supply CE = Vin; Vec = MAX Current: Standby f = MAX = 1/'RC (MIN) isBt1 50 45 ! 40 40 40 mA Output Open CE = Vin, All Other inputs < Vii or > Vin, Voc = MAX Ispt2 | 25 25 25 25 25 mA f=0Hz CE = Vcc -0.2V; Vcc = MAX Vit < Vss +0.2V Isac2 5 5 5 5 5 mA Vik 2 Vcc -0.2V; f = 0 Hz | L Version Only Isac2 4 4 4 4 4 mA CAPACITANCE DESCRIPTION CONDITIONS SYMBOL MIN MAX UNITS NOTES Input Capacitance T, = 25C, f = 1MHz Ci 8 pF 4 Output Capacitance Vcc = 5V Co 8 pF 4 Mrsczse4 gaIc 1 -43 Austin Semiconductor Inc reserves Ine igri to change products or specifications without noticeAUSTIN SEMICONDUCTOR, ING MT5C2564 883C 64K x 4d SRAM ELECTRICAL CHARACTERISTICS AND RECOMMENDED AC OPERATING CONDITIONS (Note 5) (-55C < Tg < 125C; Vec = 5V + 10%) 15 -20 25 -35 -45 DESCRIPTION SYM MIN MAX MIN MAX MIN MAX | MIN MAX MIN MAX | UNITS | NOTES READ Cycle READ cycle time RO | 15 20 25 35 45 ns Address access time AA 15 20 25 35 45 | ns Chip Enabie access time ACE 15 20 25 35 45 ns Output hold from address change OH 2 2 2 2 2 ns Chip Enable to output in Lew-Z LZCE|] 2 2 2 2 2 ns 7 Chip disable to output in High-Z 'HZCE 8 9 10 14 15 ns 6,7 Chip Enable to power-up time Pu 0 0 0 0 0 ns 4 Chip disable to power-down time 'PD 15 20 25 35 45 ns 4 WRITE Cycle WRITE cycle time wo 15 20 25 35 45 ns Chip Enable to end of write cw | 12 15 18 20 25 ns Address valid to end of write Aw | 12 15 18 20 25 ns Address setup time as 0 0 0 0 0 ns Address hold from end of write 'AH 2 2 2 2 2 ns WRITE pulse width we | 12 15 17 20 25 ns Data setup time 'Ds 7 10 12 15 20 ns Data hold time 'DH 0 0) 0 0 0 ns Write disable to output in Low-Z 'LZWE| 2 2 2 2 2 ns 7 Write Enable to output in High-Z 'HZWE| 0 7 0 10 0 "i 0 14 0 15 ns 6,7 MTsc2564 B83c 1 . A A Austin Semconaucior, inc. reserves the nghi tc change products or specitications without notice psoco024MAT5C2564 883C 64K x 4SRAM AC TEST CONDITIONS +8v +sv Input pulse levels oo... ec ceeeeteereeteeee Vss to 3V Q 480 oO 480 Input rise and fall times 20.00... ee eeeeeeees 5ns 255 30 pF 255 = 5 PF Input timing reference level oo... eee 1.5V 7 Output reference level 0.0... cere ereenes 1.5V . Output load See fi tand2 Fig. 1 OUTPUT LOAD Fig. 2 OUTPUT LOAD UTPUE LOA... eee eee ee eee eees ee Tigures 7 an EQUIVALENT EQUIVALENT NOTES 1. All voltages referenced to Vss (GND). 7. Atany given temperature and voltage condition, 2. -3V for pulse width < 20ns. 'HZCE is less than 'LZCE and HZWE is less than 3. Icc is dependent on output loading and cycle rates. 'LZWE. The specified value applies with the outputs 8. WE is HIGH for READ cycle. 1 9. Device is continuously selected. Chip enable is held in unloaded, and f = Re (MIN) Hz. its active state. 4. This parameter is guaranteed but not tested. 10. Address valid prior to or coincident with latest 5. Test conditions as specified with the output loading pccur ring chip enable. as shown in Fig. 1 unless otherwise noted. 11. "RC = READ cycle time. ___ 6. HZCE and HZWE are specified with CL =5 pF as in 12. Chip enable (CE) and write enable (WE) can initiate Fig. 2. Transition is measured + 500mV typical from and terminate a WRITE cycle. steady state voltage, allowing for actual tester RC time constant. DATA RETENTION ELECTRICAL CHARACTERISTICS (L Version Only) DESCRIPTION CONDITIONS SYMBOL MIN MAX UNITS NOTES Vcc for Retention Data VbR 2 _ Vv Data Retention Current CE 2 (Vcc - 0.2V)|Vcc = 2V|_ Iccor 500 LA Vin 2 (Vcc - 0.2V) or<0.2V Vcc = 3V 800 pA Chip Deselect to Data CDR 0. ns 4 Retention Time Operation Recovery Time 'R 'RC ns 4,11 LOW Vcc DATA RETENTION WAVEFORM DATA RETENTION MODE Y 4.5V 45V/ k Vor >2Vv j cor tr WEL DON'T CARE B84) UNDEFINED Vec MT5C2564 B83C 1-45 Austin Semiconductor. Inc reserves Ine ngnt to cr ange oreducts or specificaticns without nonce REY 3/97 - psoco024AUSTIN SEMICONDUCTOR. INC MT5C2564 883C Lea es Ty READ CYCLE NO. 189 ac \ ADDR VALID Y tA toH Q PREVIOUS DATA VALID DATA VALID READ CYCLE NO. 27.819 tac tace tHZCE tL2CE Da HIGH-Z DATA VALID tpu ________- icc | pb DONT CARE XY UNDEFINED 1-46 Austin Semaconductor, Inc . reserves the right to change products or specifications without notice MT5C2564 683C REV 1/97 bsooo024AUSTIN SEMICONDUCTOR. INC Ba eel 64K x 4 SRAM WRITE CYCLE NO. 1 "2 (Chip Enable Controlled) two ADDR \ t taw tas \ tow TAH _ f. CE \ j twe we LLL WLLL. tps 'DH D DATA VALID + Q HIGH-Z WRITE CYCLE NO. 27.12 (Write Enable Controlled) two ADDR taw | tcw AH GE TLL L, , tas twp <1___- tos DH D DATA VALID J tHZWE 1ZWE TR RERE SRR RRR EREREREERRRRRERERRERR KKK SY? HIGH-2 WG / //) DON'T CARE KXX] UNDEFINED MT5C2564 8830 1 -47 Austin Semiconductor, Inc , reserves th right to change products cr specificahons without notice REV 397 Dsoco024AUSTIN SFMICONDUC FOR ING eae 64K x 4 SRAM p ELECTRICAL TEST REQUIREMENTS SUBGROUPS MIL-STD-883 TEST REQUIREMENTS (per Method 5005, Tabte |) INTERIM ELECTRICAL (PRE-BURN-IN) TEST PARAMETERS 2, BA, 10 (Methad 5004) FINAL ELECTRICAL TEST PARAMETERS 1*, 2,3, 7*, 8,9, 10,11 (Method 5004) GROUP A TEST REQUIREMENTS 1,2, 3, 4**, 7, 8, 9, 10, 11 (Method 5005) GROUP C AND D END-POINT ELECTRICAL PARAMETERS 1, 2,3, 7, 8,9, 10, 11 (Method 5005) * PDA applies to subgroups 1 and 7. ** Subgroup 4 shall be measured only for initial qualification and after process or design changes, which may affect input or output capacitance. MT5C2564 883C 4 -48 Austin Semiconguciar Inc. raserves the nghl tc change products or specifications winout notice REV 397 Dsaqo024