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Si86xx 1 Mbps Data Sheet

1 Mbps, 2.5 kVRMS Digital Isolators

Silicon Lab's family of ultra-low-power digital isolators are CMOS devices offering sub-

stantial data rate, propagation delay, power, size, reliability, and external BOM advan-

tages over legacy isolation technologies. The operating parameters of these products

remain stable across wide temperature ranges and throughout device service life for

ease of design and highly uniform performance. All device versions have Schmitt trigger

inputs for high noise immunity and only require VDD bypass capacitors.

All products support Data rates up to 1 Mbps and Enable inputs which provide a single

point control for enabling and disabling output drive. All products are safety certified by

UL, CSA, VDE, and CQC and support withstand ratings up to 2.5 kVRMS.

Automotive Grade is available for certain part numbers. These products are built using

automotive-specific flows at all steps in the manufacturing process to ensure the robust-

ness and low defectivity required for automotive applications.

KEY FEATURES

• High-speed operation

• DC to 1 Mbps

•No start-up initialization required

• Wide Operating Supply Voltage

• 2.5 to 5.5 V

• Up to 2500 VRMS isolation

• 60-year life at rated working voltage

• High electromagnetic immunity

• Ultra low power (typical)

• 5 V Operation: 1.6 mA per channel at 1

Mbps

• 2.5 V Operation: 1.5 mA per channel at

1 Mbps

• Tri-state outputs with ENABLE

• Schmitt trigger inputs

• Transient Immunity 50 kV/µs

• AEC-Q100 qualification

• Wide temperature range

• –40 to 125 °C

• RoHS-compliant packages

• SOIC-16 wide body

• SOIC-16 narrow body

• SOIC-8 narrow body

• Automotive-grade OPNs available

• AIAG compliant PPAP documentation

support

• IMDS and CAMDS listing support

Industrial Applications

•Industrial automation systems

•Medical electronics

• Isolated switch mode supplies

• Isolated ADC, DAC

• Motor control

• Power inverters

• Communication systems

Safety Regulatory Approvals

• UL 1577 recognized

• Up to 5000 VRMS for 1 minute

• CSA component notice 5A approval

• IEC 60950-1, 61010-1

• VDE certification conformity

• IEC 60747-5-2 (VDE0884 Part 2)

• CQC certification approval

• GB4943.1

Automotive Applications

•On-board chargers

•Battery management systems

• Charging stations

• Traction inverters

• Hybrid Electric Vehicles

• Battery Electric Vehicles

silabs.com | Building a more connected world. Rev. 1.02

1. Ordering Guide

Table 1.1. Ordering Guide for Valid OPNs1,2

Ordering Part

Number (OPN)

Number of

Inputs

VDD1 Side

Number of

Inputs

VDD2 Side

Max Data

Rate (Mbps)

Default Out-

put State

Isolation

Rating (kV)

Temp (°C) Package

Si8610AB-B-IS 1 0 1 Low 2.5 –40 to 125 °C SOIC-8

Si8620AB-B-IS 2 0 1 Low 2.5 –40 to 125 °C SOIC-8

Si8621AB-B-IS 1 1 1 Low 2.5 –40 to 125 °C SOIC-8

Si8630AB-B-IS 3 0 1 Low 2.5 –40 to 125 °C WB SOIC-16

Si8630AB-B-IS1 3 0 1 Low 2.5 –40 to 125 °C NB SOIC-16

Si8631AB-B-IS 2 1 1 Low 2.5 –40 to 125 °C WB SOIC-16

Si8631AB-B-IS1 2 1 1 Low 2.5 –40 to 125 °C NB SOIC-16

Si8640AB-B-IS1 4 0 1 Low 2.5 –40 to 125 °C NB SOIC-16

Si8640AB-B-IS 4 0 1 Low 2.5 –40 to 125 °C WB SOIC-16

Si8641AB-B-IS1 3 1 1 Low 2.5 –40 to 125 °C NB SOIC-16

Si8641AB-B-IS 3 1 1 Low 2.5 –40 to 125 °C WB SOIC-16

Si8642AB-B-IS1 2 2 1 Low 2.5 –40 to 125 °C NB SOIC-16

Si8642AB-B-IS 2 2 1 Low 2.5 –40 to 125 °C WB SOIC-16

Si8650AB-B-IS1 5 0 1 Low 2.5 –40 to 125 °C NB SOIC-16

Si8651AB-B-IS1 4 1 1 Low 2.5 –40 to 125 °C NB SOIC-16

Si8652AB-B-IS1 3 2 1 Low 2.5 –40 to 125 °C NB SOIC-16

Si8660AB-B-IS1 6 0 1 Low 2.5 –40 to 125 °C NB SOIC-16

Si8661AB-B-IS1 5 1 1 Low 2.5 –40 to 125 °C NB SOIC-16

Si8662AB-B-IS1 4 2 1 Low 2.5 –40 to 125 °C NB SOIC-16

Si8663AB-B-IS1 3 3 1 Low 2.5 –40 to 125 °C NB SOIC-16

Notes:

1. All packages are RoHS-compliant with peak reflow temperatures of 260 °C according to the JEDEC industry standard classifica-

tions and peak solder temperatures.

2. “Si” and “SI” are used interchangeably.

Si86xx Data Sheet

Ordering Guide

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Automotive Grade OPNs

Automotive-grade devices are built using automotive-specific flows at all steps in the manufacturing process to ensure robustness and

low defectivity. These devices are supported with AIAG-compliant Production Part Approval Process (PPAP) documentation, and fea-

ture International Material Data System (IMDS) and China Automotive Material Data System (CAMDS) listing. Qualifications are compli-

ant with AEC-Q100, and a zero-defect methodology is maintained throughout definition, design, evaluation, qualification, and mass pro-

duction steps.

Table 1.2. Ordering Guide for Automotive Grade OPNs1, 2, 4, 5

Ordering Part Number

(OPN)

Number of

Inputs

VDD1 Side

Number of

Inputs

VDD2 Side

Max Data

Rate

(Mbps)

Default

Output

State

Isolation

Rating (kV)

Temp (°C) Package

Si8621AB-AS 1 1 1 Low 2.5 –40 to 125 °C SOIC-8

SI8641AB-AS1 3 1 1 Low 2.5 –40 to 125 °C NB SOIC-16

SI8642AB-AS1 2 2 1 Low 2.5 –40 to 125 °C NB SOIC-16

Si8663AB-AS1 3 3 1 Low 2.5 –40 to 125 °C SOIC-16

Note:

1. All packages are RoHS-compliant with peak reflow temperatures of 260 °C according to the JEDEC industry standard classifica-

tions.

2. “Si” and “SI” are used interchangeably.

3. An "R" at the end of the part number denotes tape and reel packaging option.

4. Automotive-Grade devices (with an "–A" suffix) are identical in construction materials, topside marking, and electrical parameters

to their Industrial-Grade (with a "–I" suffix) version counterparts. Automotive-Grade products are produced utilizing full automotive

process flows and additional statistical process controls throughout the manufacturing flow. The Automotive-Grade part number is

included on shipping labels.

5. Additional Ordering Part Numbers may be available in Automotive-Grade. Please contact your local Silicon Labs sales represen-

tative for further information.

Si86xx Data Sheet

Ordering Guide

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Table of Contents

1. Ordering Guide ..............................2

2. Functional Description............................5

2.1 Theory of Operation ............................5

3. Device Operation ..............................6

3.1 Device Startup ..............................8

3.2 Undervoltage Lockout ...........................8

3.3 Layout Recommendations ..........................8

3.3.1 Supply Bypass ............................8

3.3.2 Output Pin Termination..........................8

4. Electrical Specifications ...........................9

5. Pin Descriptions .............................30

5.1 Pin Descriptions (Si861x/2x Narrow Body SOIC-8) ..................30

5.2 Pin Descriptions (Si863x) ..........................31

5.3 Pin Descriptions (Si864x) ..........................32

5.4 Pin Descriptions (Si8650/51/52) ........................33

5.5 Pin Descriptions (Si866x) ..........................34

6. Package Outlines .............................35

6.1 Package Outline (16-Pin Wide Body SOIC) ....................35

6.2 Package Outline (16-Pin Narrow Body SOIC)....................37

6.3 Package Outline (8-Pin Narrow Body SOIC) ....................39

7. Land Patterns ..............................40

7.1 Land Pattern (16-Pin Wide-Body SOIC) .....................40

7.2 Land Pattern (16-Pin Narrow Body SOIC) .....................41

7.3 Land Pattern (8-Pin Narrow Body SOIC) .....................42

8. Top Markings ..............................43

8.1 Top Marking (16-Pin Wide Body SOIC) ......................43

8.2 Top Marking (16-Pin Narrow Body SOIC) .....................44

8.3 Top Marking (8-Pin Narrow Body SOIC) .....................45

9. Revision History .............................46

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2. Functional Description

2.1 Theory of Operation

The operation of an Si86xx channel is analogous to that of an opto coupler, except an RF carrier is modulated instead of light. This

simple architecture provides a robust isolated data path and requires no special considerations or initialization at start-up. A simplified

block diagram for a single Si86xx channel is shown in the figure below.

OSCILLATOR

MODULATOR DEMODULATOR

A B

Semiconductor-

Based Isolation

Barrier

Transmitter Receiver

Figure 2.1. Simplified Channel Diagram

A channel consists of an RF Transmitter and RF Receiver separated by a semiconductor-based isolation barrier. Referring to the

Transmitter, input A modulates the carrier provided by an RF oscillator using on/off keying. The Receiver contains a demodulator that

decodes the input state according to its RF energy content and applies the result to output B via the output driver. This RF on/off keying

scheme is superior to pulse code schemes as it provides best-in-class noise immunity, low power consumption, and better immunity to

magnetic fields. See the figure below for more details.

Input Signal

Output Signal

Modulation Signal

Figure 2.2. Modulation Scheme

Si86xx Data Sheet

Functional Description

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3. Device Operation

Device behavior during start-up, normal operation, and shutdown is shown in Figure 3.1 Device Behavior during Normal Operation on

page 8, where UVLO+ and UVLO- are the positive-going and negative-going thresholds respectively. Refer to the table below to

determine outputs when power supply (VDD) is not present. Additionally, refer to Table 3.2 Enable Input Truth1 on page 7 for logic

conditions when enable pins are used.

Table 3.1. Si86xx Logic Operation

Input1,2

Input1,2,3,4

VDDI

State1,5,6

VDDO

State1,5,6

VO Output1,2 Comments

H H or NC P P H Enabled, normal operation.

L H or NC P P L

X7L P P Hi-Z8Disabled.

X7H or NC UP P L Upon transition of VDDI from unpowered to powered, VO re-

turns to the same state as VI in less than 1 µs.

X7L UP P Hi-Z8Disabled.

X7X7P UP Undetermined Upon transition of VDDO from unpowered to powered, VO re-

turns to the same state as VI within 1 µs, if EN is in either the

H or NC state. Upon transition of VDDO from unpowered to

powered, VO returns to Hi-Z within 1 µs if EN is L.

Notes:

1. VDDI and VDDO are the input and output power supplies. VI and VO are the respective input and output terminals. EN is the

enable control input located on the same output side.

2. X = not applicable; H = Logic High; L = Logic Low; Hi-Z = High Impedance.

3. It is recommended that the enable inputs be connected to an external logic high or low level when the Si86xx is operating in noisy

environments.

4. No Connect (NC) replaces EN1 on some devices. No Connects are not internally connected and can be left floating, tied to VDD,

or tied to GND.

5. “Powered” state (P) is defined as 2.5 V < VDD < 5.5 V.

6. “Unpowered” state (UP) is defined as VDD = 0 V.

7. Note that an I/O can power the die for a given side through an internal diode if its source has adequate current.

8. When using the enable pin (EN) function, the output pin state is driven into a high-impedance state when the EN pin is disabled

(EN = 0).

Si86xx Data Sheet

Device Operation

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Table 3.2. Enable Input Truth1

P/N EN11,2 EN21,2 Operation

Si861x/2x — — Outputs are enabled and follow input state.

Si8630 — H Outputs B1, B2, B3 are enabled and follow input state.

— L Outputs B1, B2, B3 are disabled and in high impedance state.3

Si8631 H X Output A3 enabled and follows input state.

L X Output A3 disabled and in high impedance state.3

X H Outputs B1, B2 are enabled and follow input state.

X L Outputs B1, B2 are disabled and in high impedance state.3

Si8640 — H Outputs B1, B2, B3, B4 are enabled and follow the input state.

— L Outputs B1, B2, B3, B4 are disabled and in high impedance state.3

Si8641 H X Output A4 enabled and follows the input state.

L X Output A4 disabled and in high impedance state.3

X H Outputs B1, B2, B3 are enabled and follow the input state.

X L Outputs B1, B2, B3 are disabled and in high impedance state.3

Si8642 H X Outputs A3 and A4 are enabled and follow the input state.

L X Outputs A3 and A4 are disabled and in high impedance state.3

X H Outputs B1 and B2 are enabled and follow the input state.

X L Outputs B1 and B2 are disabled and in high impedance state.3

Si8650 — H Outputs B1, B2, B3, B4, B5 are enabled and follow input state.

— L Outputs B1, B2, B3, B4, B5 are disabled and Logic Low or in high impedance state.3

Si8651 H X Output A5 enabled and follow input state.

L X Output A5 disabled and in high impedance state.3

X H Outputs B1, B2, B3, B4 are enabled and follow input state.

X L Outputs B1, B2, B3, B4 are disabled and in high impedance state.3

Si8652 H X Outputs A4 and A5 are enabled and follow input state.

L X Outputs A4 and A5 are disabled and in high impedance state.3

X H Outputs B1, B2, B3 are enabled and follow input state.

X L Outputs B1, B2, B3 are disabled and in high impedance state.3

Si866x — — Outputs are enabled and follow input state.

Notes:

1. Enable inputs EN1 and EN2 can be used for multiplexing, for clock sync, or other output control. These inputs are internally

pulled-up to local VDD by a 2 µA current source allowing them to be connected to an external logic level (high or low) or left

floating. To minimize noise coupling, do not connect circuit traces to EN1 or EN2 if they are left floating. If EN1, EN2 are unused,

it is recommended they be connected to an external logic level, especially if the Si86xx is operating in a noisy environment.

2. X = not applicable; H = Logic High; L = Logic Low.

3. When using the enable pin (EN) function, the output pin state is driven into a high-impedance state when the EN pin is disabled

(EN = 0).

Si86xx Data Sheet

Device Operation

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3.1 Device Startup

Outputs are held low during powerup until VDD is above the UVLO threshold for time period tSTART. Following this, the outputs follow

the states of inputs.

3.2 Undervoltage Lockout

Undervoltage Lockout (UVLO) is provided to prevent erroneous operation during device startup and shutdown or when VDD is below its

specified operating circuits range. Both Side A and Side B each have their own undervoltage lockout monitors. Each side can enter or

exit UVLO independently. For example, Side A unconditionally enters UVLO when VDD1 falls below VDD1(UVLO–) and exits UVLO when

VDD1 rises above VDD1(UVLO+). Side B operates the same as Side A with respect to its VDD2 supply.

INPUT

VDD1

UVLO-

VDD2

UVLO+

UVLO-

UVLO+

OUTPUT

tSTART tSTART tSTART tPHL tPLH

tSD

Figure 3.1. Device Behavior during Normal Operation

3.3 Layout Recommendations

To ensure safety in the end user application, high voltage circuits (i.e., circuits with >30 VAC) must be physically separated from the

safety extra-low voltage circuits (SELV is a circuit with <30 VAC) by a certain distance (creepage/clearance). If a component, such as a

digital isolator, straddles this isolation barrier, it must meet those creepage/clearance requirements and also provide a sufficiently large

high-voltage breakdown protection rating (commonly referred to as working voltage protection). Table 4.5 Regulatory Information1 on

page 25 and Table 4.6 Insulation and Safety-Related Specifications on page 25 detail the working voltage and creepage/clearance

capabilities of the Si86xx. These tables also detail the component standards (UL1577, IEC60747, CSA 5A), which are readily accepted

by certification bodies to provide proof for end-system specifications requirements. Refer to the end-system specification (61010-1,

60950-1, 60601-1, etc.) requirements before starting any design that uses a digital isolator.

3.3.1 Supply Bypass

The Si86xx family requires a 0.1 µF bypass capacitor between VDD1 and GND1 and VDD2 and GND2. The capacitor should be placed

as close as possible to the package. To enhance the robustness of a design, the user may also include resistors (50–300 Ω ) in series

with the inputs and outputs if the system is excessively noisy.

3.3.2 Output Pin Termination

The nominal output impedance of an isolator driver channel is approximately 50 Ω, ±40%, which is a combination of the value of the on-

chip series termination resistor and channel resistance of the output driver FET. When driving loads where transmission line effects will

be a factor, output pins should be appropriately terminated with controlled impedance PCB traces.

Si86xx Data Sheet

Device Operation

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4. Electrical Specifications

Table 4.1. Recommended Operating Conditions

Parameter Symbol Min Typ Max Unit

Ambient Operating Temperature1TA–40 25 125 ºC

Supply Voltage

VDD1 2.5 — 5.5 V

VDD2 2.5 — 5.5 V

Note:

1. The maximum ambient temperature is dependent on data frequency, output loading, number of operating channels, and supply

voltage.

Table 4.2. Electrical Characteristics

(VDD1 = 5 V±10%, VDD2 = 5 V±10%, TA = –40 to 125 °C)

Parameter Symbol Test Condition Min Typ Max Unit

VDD Undervoltage Threshold VDDUV+ VDD1, VDD2 rising 1.95 2.24 2.375 V

VDD Undervoltage Threshold VDDUV– VDD1, VDD2 falling 1.88 2.16 2.325 V

VDD Undervoltage

Hysteresis

VDDHYS 50 70 95 mV

Positive-Going Input Threshold VT+ All inputs rising 1.4 1.67 1.9 V

Negative-Going

Input Threshold

VT– All inputs falling 1.0 1.23 1.4 V

Input Hysteresis VHYS 0.38 0.44 0.50 V

High Level Input Voltage VIH 2.0 — — V

Low Level input voltage VIL — — 0.8 V

High Level Output Voltage VOH loh = –4 mA VDD1,VDD2 –

0.4

4.8 — V

Low Level Output Voltage VOL lol = 4 mA — 0.2 0.4 V

Input Leakage Current IL— — ±10 µA

Output Impedance1ZO— 50 — Ω

Enable Input High Current ΙENH VENx = VIH — 2.0 — µA

Enable Input Low Current IENL VENx = VIL — 2.0 — µA

DC Supply Current (All inputs 0 V or at Supply)

Si8610Ax

VDD1

VDD2

VDD1

VDD2

VI = 0(Ax)

VI = 1(Ax)

—

0.6

0.8

1.8

0.8

1.2

1.5

2.9

1.5

Si86xx Data Sheet

Electrical Specifications

silabs.com | Building a more connected world. Rev. 1.02 | 9

Parameter Symbol Test Condition Min Typ Max Unit

Si8620Ax

VDD1

VDD2

VDD1

VDD2

VI = 0(Ax)

VI = 1(Ax)

—

0.8

1.4

3.3

1.4

2.2

5.3

2.2

Si8621Ax

VDD1

VDD2

VDD1

VDD2

VI = 0(Ax)

VI = 1(Ax)

—

1.2

2.4

1.9

3.8

Si8630Ax

VDD1

VDD2

VDD1

VDD2

VI = 0(Ax)

VI = 1(Ax)

—

0.9

1.9

4.6

1.9

1.6

3.0

7.4

3.0

Si8631Ax

VDD1

VDD2

VDD1

VDD2

VI = 0(Ax)

VI = 1(Ax)

—

1.3

1.7

3.9

3.0

2.1

2.7

5.9

4.5

Si8640Ax

VDD1

VDD2

VDD1

VDD2

VI = 0(Ax)

VI = 1(Ax)

—

1.0

2.4

6.1

2.5

1.6

3.8

9.2

4.0

Si8641Ax

VDD1

VDD2

VDD1

VDD2

VI = 0(Ax)

VI = 1(Ax)

—

1.4

2.3

5.2

3.6

2.2

3.7

7.8

5.4

Si8642Ax

VDD1

VDD2

VDD1

VDD2

VI = 0(Ax)

VI = 1(Ax)

—

1.8

4.4

2.9

6.6

Si86xx Data Sheet

Electrical Specifications

silabs.com | Building a more connected world. Rev. 1.02 | 10

Parameter Symbol Test Condition Min Typ Max Unit

Si8650Ax

VDD1

VDD2

VDD1

VDD2

VI = 0(Ax)

VI = 1(Ax)

—

1.1

3.1

7.0

3.3

1.8

4.7

9.8

5.0

Si8651Ax

VDD1

VDD2

VDD1

VDD2

VI = 0(Ax)

VI = 1(Ax)

—

1.5

2.7

6.6

4.0

2.4

4.1

9.2

6.0

Si8652Ax

VDD1

VDD2

VDD1

VDD2

VI = 0(Ax)

VI = 1(Ax)

—

2.0

2.4

5.6

5.0

3.0

3.6

7.8

7.5

Si8660Ax

VDD1

VDD2

VDD1

VDD2

VI = 0(Ax)

VI = 1(Ax)

—

1.2

3.5

8.8

3.7

1.9

5.3

12.3

5.6

Si8661Ax

VDD1

VDD2

VDD1

VDD2

VI = 0(Ax)

VI = 1(Ax)

—

1.7

3.4

7.9

4.8

2.7

5.1

11.1

7.2

Si8662Ax

VDD1

VDD2

VDD1

VDD2

VI = 0(Ax)

VI = 1(Ax)

—

2.2

3.0

7.5

5.6

3.3

4.5

10.5

8.4

Si8663Ax

VDD1

VDD2

VDD1

VDD2

VI = 0(Ax)

VI = 1(Ax)

—

2.6

6.5

3.9

9.1

Si86xx Data Sheet

Electrical Specifications

silabs.com | Building a more connected world. Rev. 1.02 | 11

Parameter Symbol Test Condition Min Typ Max Unit

1 Mbps Supply Current (All inputs = 500 kHz square wave, CI = 15 pF on all Outputs)

Si8610Ax

VDD1

VDD2

—

1.2

0.9

2.0

1.5

Si8620Ax

VDD1

VDD2

—

2.1

1.6

3.1

2.4

Si8621Ax

VDD1

VDD2

—

1.9

2.9

Si8630Ax

VDD1

VDD2

—

2.8

2.2

3.9

3.1

Si8631Ax

VDD1

VDD2

—

2.7

2.6

3.8

3.6

Si8640Ax

VDD1

VDD2

—

3.6

2.9

5.0

4.0

Si8641Ax

VDD1

VDD2

—

3.4

3.3

4.8

4.6

Si8642Ax

VDD1

VDD2

—

3.3

4.6

Si8650Ax

VDD1

VDD2

—

4.1

3.7

5.7

5.2

Si8651Ax

VDD1

VDD2

—

4.2

3.8

5.8

5.3

Si8652Ax

VDD1

VDD2

—

4.0

5.6

Si86xx Data Sheet

Electrical Specifications

silabs.com | Building a more connected world. Rev. 1.02 | 12

Parameter Symbol Test Condition Min Typ Max Unit

Si8660Ax

VDD1

VDD2

—

5.0

4.2

7.0

5.9

Si8661Ax

VDD1

VDD2

—

4.9

4.6

6.9

6.4

Si8662Ax

VDD1

VDD2

—

5.1

4.7

7.1

6.6

Si8663Ax

VDD1

VDD2

—

4.9

6.8

Timing Characteristics

All Models

Maximum Data Rate 0 — 1 Mbps

Minimum Pulse Width — — 250 ns

Propagation Delay tPHL, tPLH See Figure 4.2 Propagation

Delay Timing on page 14

— — 35 ns

Pulse Width Distortion

|tPLH – tPHL|

PWD See Figure 4.2 Propagation

Delay Timing on page 14

— — 25 ns

Propagation Delay Skew2tPSK(P-P) — — 40 ns

Channel-Channel Skew tPSK — — 35 ns

Output Rise Time trCL = 15 pF

See Figure 4.2 Propagation

Delay Timing on page 14

— 2.5 4.0 ns

Output Fall Time tfCL = 15 pF

See Figure 4.2 Propagation

Delay Timing on page 14

— 2.5 4.0 ns

Peak eye diagram jitter tJIT(PK) See Figure 2.2 Modulation

Scheme on page 5

— 350 — ps

Common Mode

Transient Immunity

CMTI VI = VDD or 0 V

VCM = 1500 V (See Figure

4.3 Common-Mode Transient

Immunity Test Circuit on page

15)

35 50 — kV/µs

Enable to Data Valid ten1 See Figure 4.1 ENABLE Tim-

ing Diagram on page 14

— 6.0 11 ns

Enable to Data Tri-State ten2 See Figure 4.1 ENABLE Tim-

ing Diagram on page 14

— 8.0 12 ns

Si86xx Data Sheet

Electrical Specifications

silabs.com | Building a more connected world. Rev. 1.02 | 13

Parameter Symbol Test Condition Min Typ Max Unit

Start-up Time3tSU — 15 40 µs

Notes:

1. The nominal output impedance of an isolator driver channel is approximately 50 Ω, ±40%, which is a combination of the value of

the on-chip series termination resistor and channel resistance of the output driver FET. When driving loads where transmission

line effects will be a factor, output pins should be appropriately terminated with controlled impedance PCB traces.

2. tPSK(P-P) is the magnitude of the difference in propagation delay times measured between different units operating at the same

supply voltages, load, and ambient temperature.

3. Start-up time is the time period from the application of power to valid data at the output.

ENABLE

OUTPUTS

ten1 ten2

Figure 4.1. ENABLE Timing Diagram

Typical

Input

tPLH tPHL

Typical

Output

trtf

90%

10%

90%

10%

1.4 V

Figure 4.2. Propagation Delay Timing

Si86xx Data Sheet

Electrical Specifications

silabs.com | Building a more connected world. Rev. 1.02 | 14

Oscilloscope

3 to 5 V

Isolated

Supply

Si86xx

VDD2

OUTPUT

3 to 5 V

Supply

High Voltage

Surge Generator

Vcm Surge

Output

High Voltage

Differential

Probe

GND2GND1

VDD1

INPUT

Input

Signal

Switch

Input

Output

Isolated

Ground

Figure 4.3. Common-Mode Transient Immunity Test Circuit

Table 4.3. Electrical Characteristics

(VDD1 = 3.3 V±10%, VDD2 = 3.3 V±10%, TA = –40 to 125 °C)

Parameter Symbol Test Condition Min Typ Max Unit

VDD Undervoltage Threshold VDDUV+ VDD1, VDD2 rising 1.95 2.24 2.375 V

VDD Undervoltage Threshold VDDUV– VDD1, VDD2 falling 1.88 2.16 2.325 V

VDD Undervoltage

Hysteresis

VDDHYS 50 70 95 mV

Positive-Going Input

Threshold

VT+ All inputs rising 1.4 1.67 1.9 V

Negative-Going Input

Threshold

VT– All inputs falling 1.0 1.23 1.4 V

Input Hysteresis VHYS 0.38 0.44 0.50 V

High Level Input Voltage VIH 2.0 — — V

Low Level Input Voltage VIL — — 0.8 V

High Level Output Voltage VOH loh = –4 mA VDD1, VDD2 – 0.4 3.1 — V

Low Level Output Voltage VOL lol = 4 mA — 0.2 0.4 V

Si86xx Data Sheet

Electrical Specifications

silabs.com | Building a more connected world. Rev. 1.02 | 15

Parameter Symbol Test Condition Min Typ Max Unit

Input Leakage Current IL— — ±10 µA

Output Impedance1ZO— 50 — Ω

Enable Input High Current IENH VENx = VIH — 2.0 — µA

Enable Input Low Current IENL VENx = VIL — 2.0 — µA

DC Supply Current (All inputs 0 V or at supply)

Si8610Ax

VDD1

VDD2

VDD1

VDD2

VI = 0(Ax)

VI = 1(Ax)

—

0.6

0.8

1.8

0.8

1.2

1.5

2.9

1.5

Si8620Ax

VDD1

VDD2

VDD1

VDD2

VI = 0(Ax)

VI = 1(Ax)

—

0.8

1.4

3.3

1.4

2.2

5.3

2.2

Si8621Ax

VDD1

VDD2

VDD1

VDD2

VI = 0(Ax)

VI = 1(Ax)

—

1.2

2.4

1.9

3.8

Si8630Ax

VDD1

VDD2

VDD1

VDD2

VI = 0(Ax)

VI = 1(Ax)

—

0.9

1.9

4.6

1.9

1.6

3.0

7.4

3.0

Si8631Ax

VDD1

VDD2

VDD1

VDD2

VI = 0(Ax)

VI = 1(Ax)

—

1.3

1.7

3.9

3.0

2.1

2.7

5.9

4.5

Si8640Ax

VDD1

VDD2

VDD1

VDD2

VI = 0(Ax)

VI = 1(Ax)

—

1.0

2.4

6.1

2.5

1.6

3.8

9.2

4.0

Si86xx Data Sheet

Electrical Specifications

silabs.com | Building a more connected world. Rev. 1.02 | 16

Parameter Symbol Test Condition Min Typ Max Unit

Si8641Ax

VDD1

VDD2

VDD1

VDD2

VI = 0(Ax)

VI = 1(Ax)

—

1.4

2.3

5.2

3.6

2.2

3.7

7.8

5.4

Si8642Ax

VDD1

VDD2

VDD1

VDD2

VI = 0(Ax)

VI = 1(Ax)

—

1.8

4.4

2.9

6.6

Si8650Ax

VDD1

VDD2

VDD1

VDD2

VI = 0(Ax)

VI = 1(Ax)

—

1.1

3.1

7.0

3.3

1.8

4.7

9.8

5.0

Si8651Ax

VDD1

VDD2

VDD1

VDD2

VI = 0(Ax)

VI = 1(Ax)

—

1.5

2.7

6.6

4.0

2.4

4.1

9.2