Rev 13.0 1
PD-97510
IR3842AMPbF
Features
•Wide Input Voltage Range 1.5V to 21V
•Wide Output Voltage Range 0.7V to 0.9*Vin
•Continuous 6A Load Capability
•Integrated Bootstrap-diode
•High Bandwidth E/A for excellent transient
performance
•Programmable Switching Frequency up to 1.2MHz
•Programmable Over Current Protection
•PGood output
•Hiccup Current Limit
•Precision Reference Voltage (0.7V, +/-1%)
•Programmable Soft-Start
•Enable Input with Voltage Monitoring Capability
•Enhanced Pre-Bias Start-up
•Seq input for Tracking applications
•-40oC to 125oC operating junction temperature
•Thermal Protection
•Multiple current ratings in pin compatible footprint
•5mm x 6mm Power QFN Package, 0.9 mm height
•Lead-free, halogen-free and RoHS compliant
Applications
•Server Applications
•Storage Applications
•Embedded Telecom Systems
•Distributed Point of Load Power Architectures
Fig. 1. Typical application diagram
Description
The IR3842A SupIRBuckTM is an easy-to-use,
fully integrated and highly efficient DC/DC
synchronous Buck regulator. The MOSFETs co-
packaged with the on-chip PWM controller make
IR3842A a space-efficient solution, providing
accurate power delivery for low output voltage
applications.
IR3842A is a versatile regulator which offers
programmability of start up time, switching
frequency and current limit while operating in
wide input and output voltage range.
The switching frequency is programmable from
250kHz to 1.2MHz for an optimum solution.
It also features important protection functions,
such as Pre-Bias startup, hiccup current limit and
thermal shutdown to give required system level
security in the event of fault conditions.
HIGHLY EFFICIENT
INTEGRATED 6A SYNCHRONOUS BUCK REGULATOR
SupIRBuckTM
Boot
Vcc
Fb
Comp
Gnd PGnd
SW
OCSet
SS/ SD
4.5V <Vcc<5.5V
Vo
PGood
PGood
Enable
Rt
1.5V <Vin<16V
Vin
Seq
•Netcom Applications
•Computing Peripheral Voltage Regulators
•General DC-DC Converters
Rev 13.0 2
PD-97510
IR3842AMPbF
14
13
ABSOLUTE MAXIMUM RATINGS
(Voltages referenced to GND unless otherwise specified)
•Vin ……………………………………………………. -0.3V to 25V
•Vcc ……………….….…………….……..……….…… -0.3V to 8V (Note2)
•Boot ……………………………………..……….…. -0.3V to 33V
•SW …………………………………………..……… -0.3V to 25V(DC), -4V to 25V(AC, 100ns)
•Boot to SW ……..…………………………….…..….. -0.3V to Vcc+0.3V (Note1)
•OCSet ………………………………………….……. -0.3V to 30V, 30mA
•Input / output Pins ……………………………….. ... -0.3V to Vcc+0.3V (Note1)
•PGND to GND ……………...………………………….. -0.3V to +0.3V
•Storage Temperature Range ................................... -55°C To 150°C
•Junction Temperature Range ................................... -40°C To 150°C (Note2)
•ESD Classification …………………………… ……… JEDEC Class 1C
•Moisture sensitivity level………………...………………JEDEC Level 2@260 °C (Note5)
Stresses beyond those listed under “Absolute Maximum Ratings” may cause permanent damage to the
device. These are stress ratings only and functional operation of the device at these or any other
conditions beyond those indicated in the operational sections of the specifications are not implied.
Note1: Must not exceed 8V
Note2: Vcc must not exceed 7.5V for Junction Temperature between -10oC and -40oC
W/C2θ
W/C35θ
o
PCBJ
o
JA
=
=
-
PACKAGE INFORMATION
5mm x 6mm POWER QFN
400015IR3842AMTRPbFM
750
PARTS PER
REEL
15
PIN COUNT
IR3842AMTR1PbF
PACKAGE
DESCRIPTION
M
PACKAGE
DESIGNATOR
ORDERING INFORMATION
12 11 10 PGnd
15
Gnd
1234567
8
9
Seq FB COMP Gnd Rt SS OCSet
PGood
VCC
Enable
Boot
VIN
SW
Rev 13.0 3
PD-97510
IR3842AMPbF
Block Diagram
Fig. 2. Simplified block diagram of the IR3842A
Rev 13.0 4
PD-97510
IR3842AMPbF
Pin Description
Pin Name Description
1 Seq
Sequence pin. Use two external resistors to set Simultaneous Power up
sequencing. If this pin is not used connect to Vcc.
2 Fb
Inverting input to the error amplifier. This pin is connected directly to the
output of the regulator via resistor divider to set the output voltage and
provide feedback to the error amplifier.
3 Comp
Output of error amplifier. An external resistor and capacitor network is
typically connected from this pin to Fb pin to provide loop
compensation.
4 Gnd Signal ground for internal reference and control circuitry.
5 Rt
Set the switching frequency. Connect an external resistor from this pin
to Gnd to set the switching frequency.
6 SS/SD¯¯
Soft start / shutdown. This pin provides user programmable soft-start
function. Connect an external capacitor from this pin to Gnd to set the
start up time of the output voltage. The converter can be shutdown by
pulling this pin below 0.3V.
7 OCSet
Current limit set point. A resistor from this pin to SW pin will set the
current limit threshold.
8
PGood
Power Good status pin. Output is open drain. Connect a pull up resistor
from this pin to Vcc. If unused, it can be left open.
9 V
CC
This pin powers the internal IC and the drivers. A minimum of 1uF high
frequency capacitor must be connected from this pin to the power
ground (PGnd).
10 PGnd Power Ground. This pin serves as a separated ground for the MOSFET
drivers and should be connected to the system’s power ground plane.
11
SW
Switch node. This pin is connected to the output inductor.
12
V
IN
Input voltage connection pin.
13 Boot Supply voltage for high side driver. A 0.1uF capacitor must be
connected from this pin to SW.
14 Enable
Enable pin to turn on and off the device. Use two external resistors to
set the turn on threshold (see Enable section). Connect this pin to Vcc if
it is not used.
15 Gnd Signal ground for internal reference and control circuitry.
Rev 13.0 5
PD-97510
IR3842AMPbF
Recommended Operating Conditions
Parameter Symbol Test Condition Min TYP MAX Units
Power Loss
Power Loss
P
loss
Vcc=5V, V
in
=12V, V
o
=1.8V, I
o
=6A,
Fs=600kHz, L=1.0uH, Note4
1.27 W
MOSFET R
ds(on)
Top Switch R
ds(on)_Top
V
Boot
-V
sw
=5V, I
D
=6A, Tj=
25
o
C
24.5 34
Bottom Switch
R
ds(on)_Bot
V
cc
=5V, I
D
=6A, Tj=
25
o
C
14.3 19
mΩ
Reference Voltage
Feedback Voltage V
FB
0.7 V
0
o
C<Tj<125
o
C -1.0 +1.0 Accuracy
-40
o
C<Tj<125
o
C,
Note3
-2.0 +2.0
%
Supply Current
V
CC
Supply Current (Standby)
I
CC(Standby)
SS=0V, No Switching, Enable low 500 μA
V
cc
Supply Current (Dyn) I
CC(Dyn)
SS=3V, Vcc=5V, Fs=500kHz
Enable high
10 mA
Under Voltage Lockout
V
CC
-Start-Threshold V
CC
_UVLO_Start
Vcc Rising Trip Level 3.95 4.15 4.35
V
CC
-Stop-Threshold V
CC
_UVLO_Stop Vcc Falling Trip Level 3.65 3.85 4.05
Enable-Start-Threshold Enable_UVLO_Start
Supply ramping up 1.14 1.2 1.36
Enable-Stop-Threshold Enable_UVLO_Stop Supply ramping down 0.9 1.0 1.06
V
Enable leakage current Ien Enable=3.3V 15 μA
* SW must not exceed the Abs Max Rating (25V)
Electrical Specifications
Unless otherwise specified, these specification apply over 4.5V< Vcc<5.5V, Vin=12V, 0oC<Tj< 125oC.
Typical values are specified at Ta= 25oC.
Symbol Definition Min Max Units
V
in
Input Voltage 1.5 21*
V
cc
Supply Voltage 4.5 5.5
Boot to SW Supply Voltage 4.5 5.5
V
o
Output Voltage 0.7 0.9*Vin
V
I
o
Output Current 0 6 A
Fs Switching Frequency 225 1320 kHz
T
j
Junction Temperature -40 125
o
C
Rev 13.0 6
PD-97510
IR3842AMPbF
Electrical Specifications (continued)
Unless otherwise specified, these specifications apply over 4.5V< Vcc<5.5V, Vin=12V, 0oC<Tj< 125oC.
Typical values are specified at Ta= 25oC.
Parameter Symbol Test Condition Min TYP MAX Units
Osc illator
Rt Voltage 0.665 0.7 0.735 V
Rt=59K 225 250 275
Rt=28.7K 450 500 550
Frequency FS
Rt=11.5K, Note4 1080 1200 1320
kHz
Ramp Amplitude Vramp Note4 1.8 Vp-p
Ramp Offset Ramp (os) Note4 0.6 V
Min Pulse Width Dmin(ctrl) Note4 50
Fixed Off Time Note4 130 200
ns
Max Duty Cycle Dmax Fs=250kHz 92 %
Error Amplifier
Input Offset Voltage Vos Vfb-Vseq,
Vseq=0.8V
-10 0 +10 mV
Input Bias Current IFb(E/A) -1 +1
Input Bias Current IVp(E/A) -1 +1
μA
Sink Current Isink(E/A) 0.40 0.85 1.2
Source Current Isource(E/A) 8 10 13
mA
Slew Rate SR Note4 7 12 20
V/μs
Gain-Bandwidth Product GBWP Note4 20 30 40 MHz
DC Gain Gain Note4 100 110 120 dB
Maximum Voltage Vmax(E/A) Vcc=4.5V 3.4 3.5 3.75 V
Minimum Voltage Vmin(E/A) 120 220 mV
Common Mode Voltage Note4 0 1 V
Soft Start/SD
Soft Start Current ISS Source 14 20 26 μA
Soft Start Clamp Voltage Vss(clamp) 2.7 3.0 3.3
Shutdown Output
Threshold
SD 0.3
V
Over Current Protection
Fs=250kHz 20.8 23.6 26.4
Fs=500kHz 43 48.8 54.6
OCSET Current IOCSET
Fs=1200kHz, Note4 121.7
μA
OC Comp Offset Voltage VOFFSET Note4 -10 0 +10 mV
SS off time SS_Hiccup 4096 Cycles
Bootstrap Diode
Forward Voltage I(Boot)=30mA 180 260 470 mV
Deadband
Deadband time Note4 5 10 30 ns
Rev 13.0 7
PD-97510
IR3842AMPbF
Note3: Cold temperature performance is guaranteed via correlation using statistical quality control. Not tested in production.
Note4: Guaranteed by Design but not tested in production.
Note5: Upgrade to industrial/MSL2 level applies from date codes 1227 (marking explained on application note AN1132 page 2).
Products with prior date code of 1227 are qualified with MSL3 for Consumer market.
Electrical Specifications (continued)
Unless otherwise specified, these specification apply over 4.5V< Vcc<5.5V, Vin=12V, 0oC<Tj< 125oC.
Typical values are specified at Ta= 25oC.
Parameter SYM Test Condition Min TYP MAX Units
Thermal Shutdown
Thermal Shutdown Note4 140
Hysteresis Note4 20
o
C
Power Good
Power Good upper
Threshold
VPG(upper) Fb Falling 0.770 0.805 0.840 V
Upper Threshold Delay VPG(upper)_Dly Fb Falling 256/Fs s
Power Good lower
Threshold
VPG(lower) Fb Rising 0.560 0.595 0.630 V
Lower Threshold Delay VPG(lower)_Dly Fb Rising 256/Fs s
Delay Comparator
Threshold
PG(Delay) Relative to charge voltage, SS rising 2 2.1 2.3 V
Delay Comparator
Hysteresis
Delay(hys) Note4 260 300 340 mV
PGood Voltage Low PG(voltage) I
PGood
=-5mA 0.5 V
Leakage Current I
leakage
0 10 μA
Switch Node
SW=0V, Enable=0V SW Bias Current
Isw
SW=0V,Enable=high,SS=3V,Vseq=0V, Note4
6
μA
Rev 8.0 8
IR3842WMPbF
PRELIMINARY DATA SHEET
ISS
14.0
16.0
18.0
20.0
22.0
24.0
26.0
-40-200 20406080100120
Temp[
o
C]
[uA]
Enable(UVLO) Stop
0.90
0.92
0.94
0.96
0.98
1.00
1.02
1.04
1.06
-40 -20 0 20 40 60 80 100 120
Temp[
ο
C]
[V]
Enable(UVLO) Start
1.14
1.16
1.18
1.20
1.22
1.24
1.26
1.28
1.30
1.32
1.34
1.36
-40 -20 0 20 40 60 80 100 120
Temp[
o
C]
[V]
Vcc(UVLO) Stop
3.76
3.81
3.86
3.91
3.96
4.01
4.06
4.11
4.16
-40-200 20406080100120
Temp[
o
C]
[V]
Vcc(UVLO) Start
4.06
4.11
4.16
4.21
4.26
4.31
4.36
4.41
4.46
-40-200 20406080100120
Temp[
o
C]
[V]
IOCSET(500kHz)
43.0
44.0
45.0
46.0
47.0
48.0
49.0
50.0
51.0
52.0
53.0
54.0
-40-200 20406080100120
Temp[
o
C]
[uA]
FREQUENCY
450
460
470
480
490
500
510
520
530
540
550
-40 -20 0 20 40 60 80 100 120
Temp[
o
C]
[kHz]
Icc(Standby)
150
170
190
210
230
250
270
290
-40 -20 0 20 40 60 80 100 120
Temp[
o
C]
[uA]
TYPICAL OPERATING CHARACTERISTICS (-40oC - 125oC) Fs=500 kHz
Vfb
686
691
696
701
706
711
-40-200 20406080100120
Temp[ oC]
[mV]
Ic(Dyn)
9.5
9.6
9.7
9.8
9.9
10.0
10.1
10.2
10.3
10.4
10.5
-40-20 0 20406080100120
Temp[
o
C]
[mA]
Rev 8.0 9
IR3842WMPbF
PRELIMINARY DATA SHEET
Rdson of MOSFETs Over Temperature at Vcc=5V
12
14
16
18
20
22
24
26
28
30
-40-200 20406080100120140
Temperature [°C]
Resistance [mΩ]
Sync-FET Ctrl-FET
Rev 8.0 10
IR3842WMPbF
PRELIMINARY DATA SHEET
Typical Efficiency and Power Loss Curves
Vin=12V, Vcc=5V, Io=1A-6A, Fs=600kHz, Room Temperature, No Air Flow
The table below shows the inductors used for each of the output voltages
in the efficiency measurement.
82
84
86
88
90
92
94
96
98
1.01.52.02.53.03.54.04.55.05.56.0
Load Current (A)
Efficiency (%)
0.9V 1.0V 1.1V 1.2V 1.5V 1.8V 2.5V 3.3V 5.0V
0.1
0.2
0.3
0.4
0.5
0.6
0.7
0.8
0.9
1.0
1.1
1.2
1.3
1.4
1.5
1.6
1.0 1.5 2.0 2.5 3.0 3.5 4.0 4.5 5.0 5.5 6.0
Load Current (A)
Power Loss (W)
0.9V 1.0V 1.1V 1.2V 1.5V 1.8V 2.5V 3.3V 5.0V
3.8
PIMC104T-1R5MN
1.53.3
3.8
PIMC104T-1R5MN
1.52.5
3
PIMC104T-1R0MN
11.8
2.45
MPO104-0R9IR
0.91.2
2.45
MPO104-0R9IR
0.91.5
6.7
PIMC104T-2R2MN
2.25
2.45
MPO104-0R9IR
0.9
1.1
1.5MPL104-0R60.6
1
1.5
MPL104-0R6
0.6
0.9
DCR
(mΩ)
P/NL (uH)
Vout (V)
3.8
PIMC104T-1R5MN
1.53.3
3.8
PIMC104T-1R5MN
1.52.5
3
PIMC104T-1R0MN
11.8
2.45
MPO104-0R9IR
0.91.2
2.45
MPO104-0R9IR
0.91.5
6.7
PIMC104T-2R2MN
2.25
2.45
MPO104-0R9IR
0.9
1.1
1.5MPL104-0R60.6
1
1.5
MPL104-0R6
0.6
0.9
DCR
(mΩ)
P/NL (uH)
Vout (V)
Rev 8.0 11
IR3842WMPbF
PRELIMINARY DATA SHEET
Typical Efficiency and Power Loss Curves
Vin=5V, Vcc=5V, Io=1A-6A, Fs=600kHz, Room Temperature, No Air Flow
The table below shows the inductors used for each of the output voltages
in the efficiency measurement.
81
83
85
87
89
91
93
95
97
1.0 1.5 2.0 2.5 3.0 3.5 4.0 4.5 5.0 5.5 6.0
Load Current (A)
Efficiency (%)
0.7V 0.75V 0.9V 1.0V 1.1V 1.2V 1.5V 1.8V 2.5V 3.3V
0.1
0.2
0.3
0.4
0.5
0.6
0.7
0.8
0.9
1
1.1
1.2
1.3
1.4
1.01.52.02.53.03.54.04.55.05.56.0
Load Current (A)
Power Loss (W)
0.7V 0.75V 0.9V 1.0V 1.1V 1.2V 1.5V 1.8V 2.5V 3.3V
2.45
MPO104-0R9IR0.9
3.3
2.45
MPO104-0R9IR0.9
2.5
2.45
MPO104-0R9IR0.9
1.8
1.5
MPL104-0R60.6
1.2
2.45
MPO104-0R9IR0.9
1.5
1.5
MPL104-0R60.6
1.1
1.5
MPL104-0R60.6
1
1.5
MPL104-0R60.6
0.9
0.29
59PR9875N0.4
0.75
0.29
59PR9875N0.4
0.7
DCR
(mΩ)
P/NL (uH)
Vout (V)
2.45
MPO104-0R9IR0.9
3.3
2.45
MPO104-0R9IR0.9
2.5
2.45
MPO104-0R9IR0.9
1.8
1.5
MPL104-0R60.6
1.2
2.45
MPO104-0R9IR0.9
1.5
1.5
MPL104-0R60.6
1.1
1.5
MPL104-0R60.6
1
1.5
MPL104-0R60.6
0.9
0.29
59PR9875N0.4
0.75
0.29
59PR9875N0.4
0.7
DCR
(mΩ)
P/NL (uH)
Vout (V)
Rev 13.0 12
PD-97510
IR3842AMPbF
Circuit Description
THEORY OF OPERATION
Introduction
The IR3842A uses a PWM voltage mode control
scheme with external compensation to provide
good noise immunity and maximum flexibility in
selecting inductor values and capacitor types.
The switching frequency is programmable from
250kHz to 1.2MHz and provides the capability of
optimizing the design in terms of size and
performance.
IR3842A provides precisely regulated output
voltage programmed via two external resistors
from 0.7V to 0.9*Vin.
The IR3842A operates with an external bias
supply from 4.5V to 5.5V, allowing an extended
operating input voltage range from 1.5V to 21V.
The device utilizes the on-resistance of the low
side MOSFET as current sense element, this
method enhances the converter’s efficiency and
reduces cost by eliminating the need for external
current sense resistor.
IR3842A includes two low Rds(on) MOSFETs
using IR’s HEXFET technology. These are
specifically designed for high efficiency
applications.
Under-Voltage Lockout and POR
The under-voltage lockout circuit monitors the
input supply Vcc and the Enable input. It assures
that the MOSFET driver outputs remain in the off
state whenever either of these two signals drop
below the set thresholds. Normal operation
resumes once Vcc and Enable rise above their
thresholds.
The POR (Power On Ready) signal is generated
when all these signals reach the valid logic level
(see system block diagram). When the POR is
asserted the soft start sequence starts (see soft
start section).
Enable
The Enable features another level of flexibility for
start up. The Enable has precise threshold which
is internally monitored by Under-Voltage Lockout
(UVLO) circuit. Therefore, the IR3842A will turn
on only when the voltage at the Enable pin
exceeds this threshold, typically, 1.2V.
If the input to the Enable pin is derived from the
bus voltage by a suitably programmed resistive
divider, it can be ensured that the IR3842A does
not turn on until the bus voltage reaches the
desired level. Only after the bus voltage reaches
or exceeds this level will the voltage at Enable
pin exceed its threshold, thus enabling the
IR3842A. Therefore, in addition to being a logic
input pin to enable the IR3842A, the Enable
feature, with its precise threshold, also allows the
user to implement an Under-Voltage Lockout for
the bus voltage Vin. This is desirable particularly
for high output voltage applications, where we
might want the IR3842A to be disabled at least
until Vin exceeds the desired output voltage level.
Figure 3b. shows the recommended start-up
sequence for the non-sequenced operation of
IR3842A.
Figure 3c. shows the recommended startup
sequence for sequenced operation of IR3842A
Fig. 3a. Normal Start up, Device turns on
when the Bus voltage reaches 10.2V
Fig. 3b. Recommended startup sequence,
Non-Sequenced operation
Rev 13.0 13
PD-97510
IR3842AMPbF
Soft-Start
The IR3842A has a programmable soft-start to
control the output voltage rise and to limit the
current surge at the start-up. To ensure correct
start-up, the soft-start sequence initiates when
the Enable and Vcc rise above their UVLO
thresholds and generate the Power On Ready
(POR) signal. The internal current source
(typically 20uA) charges the external capacitor
Css linearly from 0V to 3V. Figure 6 shows the
waveforms during the soft start.
The start up time can be estimated by:
During the soft start the OCP is enabled to
protect the device for any short circuit and over
current condition.
Pre-Bias Startup
IR3842A is able to start up into pre-charged
output, which prevents oscillation and
disturbances of the output voltage.
The output starts in asynchronous fashion and
keeps the synchronous MOSFET off until the first
gate signal for control MOSFET is generated.
Figure 4 shows a typical Pre-Bias condition at
start up.
The synchronous MOSFET always starts with a
narrow pulse width and gradually increases its
duty cycle with a step of 25%, 50%, 75% and
100% until it reaches the steady state value. The
number of these startup pulses for the
synchronous MOSFET is internally programmed.
Figure 5 shows a series of 32, 16, 8 startup
pulses.
Fig. 5. Pre-Bias startup pulses
Fig. 6. Theoretical operation waveforms
during soft-start
(
)
(1) --------------------
A20 *0.7-1.4
μ
SS
start C
T=
Fig. 4. Pre-Bias startup
Fig. 3c. Recommended startup sequence,
Sequenced operation
Rev 13.0 14
PD-97510
IR3842AMPbF
An internal current source sources current (IOCSet
) out of the OCSet pin. This current is a function
of the switching frequency and hence, of Rt.
Shutdown
The IR3842A can be shutdown by pulling the
Enable pin below its 1 V threshold. This will tri-
state both, the high side driver as well as the low
side driver. Alternatively, the output can be
shutdown by pulling the soft-start pin below 0.3V.
Normal operation is resumed by cycling the
voltage at the Soft Start pin.
Over-Current Protection
The over current protection is performed by
sensing current through the RDS(on) of low side
MOSFET. This method enhances the converter’s
efficiency and reduces cost by eliminating a
current sense resistor. As shown in figure 7, an
external resistor (ROCSet) is connected between
OCSet pin and the switch node (SW) which sets
the current limit set point.
Table 1. shows IOCSet at different switching
frequencies. The internal current source
develops a voltage across ROCSet. When the low
side MOSFET is turned on, the inductor current
flows through the Q2 and results in a voltage at
OCSet which is given by:
An over current is detected if the OCSet pin goes
below ground. Hence, at the current limit
threshold, VOCset=0. Then, for a current limit
setting ILimit,R
OCSet is calculated as follows:
Operating Frequency
The switching frequency can be programmed
between 250kHz – 1200kHz by connecting an
external resistor from Rtpin to Gnd. Table 1
tabulates the oscillator frequency versus Rt.
Fig. 7. Connection of over current sensing resistor
An overcurrent detection trips the OCP
comparator, latches OCP signal and cycles the
soft start function in hiccup mode.
The hiccup is performed by shorting the soft-start
capacitor to ground and counting the number of
switching cycles. The Soft Start pin is held low
until 4096 cycles have been completed. The
OCP signal resets and the converter recovers.
After every soft start cycle, the converter stays in
this mode until the overload or short circuit is
removed.
I
)
RRIV L
(onDS
OCSetOCSetOCSet .(3).......... ) () ( ∗−
∗
=
I
IR
R
OCSet
LimitonDS
OCSet (4) ........................
)( *
=
)2.....(..............................
)(k
)μA( Ω
=
t
OCSet R
I1400
Table 1. Switching Frequency and IOCSet vs.
External Resistor (Rt)
The OCP circuit starts sampling current typically
160 ns after the low gate drive rises to about 3V.
This delay functions to filter out switching noise.
110.2110012.7
97.9100014.3
121.7120011.5
88.690015.8
78.680017.8
68.270020.5
59.0760023.7
48.750028.7
39.240035.7
29.430047.5
I
ocset
(μA)F
s
(kHz)R
t
(kΩ)
110.2110012.7
97.9100014.3
121.7120011.5
88.690015.8
78.680017.8
68.270020.5
59.0760023.7
48.750028.7
39.240035.7
29.430047.5
I
ocset
(μA)F
s
(kHz)R
t
(kΩ)
Rev 13.0 15
PD-97510
IR3842AMPbF
Thermal Shutdown
Temperature sensing is provided inside
IR3842A. The trip threshold is typically set to
140oC. When trip threshold is exceeded, thermal
shutdown turns off both MOSFETs and
discharges the soft start capacitor.
Automatic restart is initiated when the sensed
temperature drops within the operating range.
There is a 20oC hysteresis in the thermal
shutdown threshold.
Fig. 8b. Application Circuit for Simultaneous
Sequencing
Simultaneous Powerup
Vo1
Vo2
Output Voltage Sequencing
The IR3842A can accommodate user
programmable sequencing using Seq, Enable
and Power Good pins.
Boot
Vcc
Fb
Comp
Gnd PGnd
SW
OCSet
SS/ SD
4.5V <Vcc<5.5V
Vo(master)
PGood
PGood
Enable
Rt
1.5V <Vin<16V
Vin
Seq
RA
RB
Boot
Vcc
Fb
Comp
Gnd PGnd
SW
OCSet
SS/ SD
4.5V <Vcc<5.5V
Vo(slave)
PGood
PGood
Enable
Rt
1.5V <Vin<16V
Vin
Seq
Vo(master)
RC
RD
RE
RF
Fig. 8a. Simultaneous Power-up of the slave
with respect to the master.
Power Good Output
The IC continually monitors the output voltage via
Feedback (Fb pin). The feedback voltage forms
an input to a window comparator whose upper
and lower thresholds are 0.805V and 0.595V
respectively. Hence, the Power Good signal is
flagged when the Fb pin voltage is within the
PGood window, i. e. between 0.595V to 0.805V,
as shown in Fig .9. The PGood pin is open drain
and it needs to be externally pulled high. High
state indicates that output is in regulation. Fig. 9a
shows the PGood timing diagram for non-
tracking operation. In this case, during startup,
PGood goes high after the SS voltage reaches
2.1V if the Fb voltage is within the PGood
comparator window. Fig. 9a. and Fig 9.b. also
show a 256 cycle delay between the Fb voltage
entering within the thresholds defined by the
PGood window and PGood going high.
Through these pins, voltage sequencing such as
simultaneous and sequential can be
implemented. Figure 8. shows simultaneous
sequencing configurations. In simultaneous
power-up, the voltage at the Seq pin of the slave
reaches 0.7V before the Fb pin of the master. For
RE/RF=RC/RD, therefore, the output voltage of
the slave follows that of the master until the
voltage at the Seq pin of the slave reaches 0.7 V.
After the voltage at the Seq pin of the slave
exceeds 0.85V, the internal 0.7V reference of
the slave dictates its output voltage.
It is recommended that irrespective of the
sequencing configuration used, the input voltage
should be allowed to come up to its nominal
value first, followed by Vcc and Enable, before the
sequencing signal is applied.
For non-sequenced operation, the Seq pin
should be tied to a voltage greater than 0.85V,
such as 3.3V or Vcc. Again, the input voltage
should be allowed to come up before Vcc and
Enable.
Rev 13.0 16
PD-97510
IR3842AMPbF
TIMING DIAGRAM OF PGOOD FUNCTION
Fig.9a IR3842A Non-Tracking Operation (Seq=Vcc)
Fig.9b IR3842A Tracking Operation
Rev 13.0 17
PD-97510
IR3842AMPbF
Minimum on time Considerations
The minimum ON time is the shortest amount of
time for which the Control FET may be reliably
turned on, and this depends on the internal
timing delays. For the IR3842A, the typical
minimum on-time is specified as 50 ns.
Any design or application using the IR3842A
must ensure operation with a pulse width that is
higher than this minimum on-time and preferably
higher than 100 ns. This is necessary for the
circuit to operate without jitter and pulse-
skipping, which can cause high inductor current
ripple and high output voltage ripple.
In any application that uses the IR3842A, the
following condition must be satisfied:
The minimum output voltage is limited by the
reference voltage and hence Vout(min) = 0.7 V.
Therefore, for Vout(min) = 0.7 V,
Therefore, at the maximum recommended input
voltage 21V and minimum output voltage, the
converter should be designed at a switching
frequency that does not exceed 330 kHz.
Conversely, for operation at the maximum
recommended operating frequency 1.2 MHz and
minimum output voltage, any voltage above
5.83V may not be stepped down reliably without
pulse-skipping.
V/s
ns 100
V0.7
V
V
in
(min)
(min)
in
6
107 ×=≤×∴
≤×∴
s
on
out
s
F
t
V
F
Maximum Duty Ratio Considerations
A fixed off-time of 200 ns maximum is specified
for the IR3842A. This provides an upper limit on
the operating duty ratio at any given switching
frequency. It is clear that, higher the switching
frequency, the lower is the maximum duty ratio at
which the IR3842A can operate. To allow a
margin of 50 ns, the maximum operating duty
ratio in any application using the IR3842A should
still accommodate about 250 ns off-time. Fig 10.
shows a plot of the maximum duty ratio v/s the
switching frequency, with 250 ns off-time.
s
out
s
on
F
V
F
D
t
V
in ×
=
=
(min)
(min)
(min)
on
out
sin
sin
out
on
onon
t
V
FV
FV
V
t
tt
≤×∴
×
≤∴
≤
Fig. 10. Maximum duty cycle v/s switching
frequency.
70
75
80
85
90
95
300 400 500 600 700 800 900 1000 1100 1200
Switching Frequency (kHz)
Max Duty Cycle (%)
Rev 13.0 18
PD-97510
IR3842AMPbF
when an external resistor divider is connected to
the output as shown in figure 11.
Equation (7) can be rewritten as:
For the calculated values of R8 and R9 see
feedback compensation section.
Soft-Start Programming
The soft-start timing can be programmed by
selecting the soft-start capacitance value. From
(1), for a desired start-up time of the converter,
the soft start capacitor can be calculated by
using:
Where Tstart is the desired start-up time (ms).
For a start-up time of 3.5ms, the soft-start
capacitor will be 0.099μF. Choose a 0.1μF
ceramic capacitor.
Bootstrap Capacitor Selection
To drive the Control FET, it is necessary to
supply a gate voltage at least 4V greater than
the voltage at the SW pin, which is connected
the source of the Control FET . This is achieved
by using a bootstrap configuration, which
comprises the internal bootstrap diode and an
external bootstrap capacitor (C6), as shown in
Fig. 12. The operation of the circuit is as follows:
When the lower MOSFET is turned on, the
capacitor node connected to SW is pulled down
to ground. The capacitor charges towards Vcc
through the internal bootstrap diode, which has a
forward voltage drop VD. The voltage Vcacross
the bootstrap capacitor C6 is approximately
given as
When the upper MOSFET turns on in the next
cycle, the capacitor node connected to SW rises
to the bus voltage Vin. However, if the value of
C6 is appropriately chosen,
Application Information
Design Example:
The following example is a typical application for
IR3842A. The application circuit is shown on
page 24.
Enabling the IR3842A
As explained earlier, the precise threshold of
the Enable lends itself well to implementation of
a UVLO for the Bus Voltage.
For a typical Enable threshold of VEN = 1.2 V
For a Vin (min)=10.2V, R1=49.9K and R2=7.5K is a
good choice.
Programming the frequency
For Fs= 600 kHz, select Rt= 23.7 kΩ, using
Table. 1.
Output Voltage Programming
Output voltage is programmed by reference
voltage and external voltage divider. The Fb pin
is the inverting input of the error amplifier, which
is internally referenced to 0.7V. The divider is
ratioed to provide 0.7V at the Fb pin when the
output is at its desired value. The output voltage
is defined by using the following equation:
kHz 600=
54mV
A6 =
V1.8=
max)13.2V ( V 12=
s
o
o
o
in
F
ΔV
I
V
V
≤
.....(7)..............................
⎟
⎟
⎠
⎞
⎜
⎜
⎝
⎛+∗=
9
8
1R
R
VV refo
Fig. 11. Typical application of the IR3842A for
programming the output voltage
(8) ..................................
VV
V
RR
refo
ref ⎟
⎟
⎠
⎞
⎜
⎜
⎝
⎛
−
∗= 89
VVV Dccc (10) ..........................
−
≅
Fb
IR3624
V
OUT
R
9
R
8
IR3842A
TC startSS (9) .......... 0.02857 ) ms ( )μF( ×
=
IR3842A
Enable
Vin
R2
R1
V
RR
R
VENin (5) .......... 1.2*
(min) ==
+21
2
VV
V
RR
EN)in(
EN (6) ..........
min −
=12
Rev 13.0 19
PD-97510
IR3842AMPbF
the voltage Vc across C6 remains approximately
unchanged and the voltage at the Boot pin
becomes
A bootstrap capacitor of value 0.1uF is suitable
for most applications.
For applications with 21V input voltage, the switch
node may ring above the 25V absolute maximum
voltage rating. To prevent this, in addition to
using best layout practices, it may be necessary
to provide a 10ohm resistor in series with the boot
capacitor.
Input Capacitor Selection
The ripple current generated during the on time of
the upper MOSFET should be provided by the
input capacitor. The RMS value of this ripple is
expressed by:
Where:
Dis the Duty Cycle
IRMS is the RMS value of the input capacitor
current.
Io is the output current.
For Io=6A and D = 0.15, the IRMS = 2.14 A.
Ceramic capacitors are recommended due to
their peak current capabilities. They also feature
low ESR and ESL at higher frequency which
enables better efficiency. For this application, it is
advisable to have 2x10uF 25V ceramic capacitors
C3216X5R1E106M from TDK. In addition to
these, although not mandatory, a 1X330uF, 25V
SMD capacitor EEV-FK1E331P may also be used
as a bulk capacitor and is recommended if the
input power supply is not located close to the
converter.
Inductor Selection
The inductor is selected based on output power,
operating frequency and efficiency requirements.
A low inductor value causes large ripple current,
resulting in the smaller size, faster response to a
load transient but poor efficiency and high output
noise. Generally, the selection of the inductor
value can be reduced to the desired maximum
ripple current in the inductor . The optimum
point is usually found between 20% and 50%
ripple of the output current.
For the buck converter, the inductor value for the
desired operating ripple current can be
determined using the following relation:
Where:
If Δi≈42%(Io), then the output inductor is
calculated to be 1.01μH. Select L=1 μH.
The MPL105-1R0 from Delta provides a compact,
low profile inductor suitable for this application
....(12)....................)( DDII oRMS −∗∗= 1
(13) ................................
in
o
V
V
D=
)( i
Δ
cycleDuty
time on Turn
frequency Switching
current ripple Inductor
VoltageOutput
voltag
e
input Maximum
=
=
=
=
=
=
D
Δt
F
Δi
V
V
s
o
in
()
(14) ...............................
*
;
sin
o
oin
s
oin
FiV
V
VVL
F
Dt
t
i
LVV
Δ∗
∗−=
∗=Δ
Δ
Δ
∗=− 1
Fig. 12. Bootstrap circuit to generate
Vc voltage
(11) ........................................
DccinBoot VVVV −+≅
Rev 13.0 20
PD-97510
IR3842AMPbF
Phase
00
FLC
-1800
Frequency
Gain
FLC
0 dB
Frequency
-40dB/decade
(15) .........................
current ripple Inductor
ripple voltage Output
**
*
*
)(
)(
)(
)()()(
=Δ
=Δ
Δ
=Δ
⎟
⎟
⎠
⎞
⎜
⎜
⎝
⎛−
=Δ
Δ=Δ
Δ
+Δ+Δ=Δ
L
o
so
L
Co
oin
ESLo
LESRo
CoESLoESRoo
I
V
FC
I
V
ESL
L
VV
V
ESRIV
VVVV
8
Since the output capacitor has a major role in the
overall performance of the converter and
determines the result of transient response,
selection of the capacitor is critical. The IR3842A
can perform well with all types of capacitors.
As a rule, the capacitor must have low enough
ESR to meet output ripple and load transient
requirements.
The goal for this design is to meet the voltage
ripple requirement in the smallest possible
capacitor size. Therefore it is advisable to select
ceramic capacitors due to their low ESR and ESL
and small size. Five of the Panasonic ECJ-
2FB0J226ML (22uF, 6.3V, 3mOhm) capacitors is
a good choice.
Feedback Compensation
The IR3842A is a voltage mode controller. The
control loop is a single voltage feedback path
including error amplifier and error comparator. To
achieve fast transient response and accurate
output regulation, a compensation circuit is
necessary. The goal of the compensation
network is to provide a closed-loop transfer
function with the highest 0 dB crossing frequency
and adequate phase margin (greater than 45o).
The output LC filter introduces a double pole,
–40dB/decade gain slope above its corner
resonant frequency, and a total phase lag of 180o
(see figure 13). The resonant frequency of the LC
filter is expressed as follows:
Figure 13 shows gain and phase of the LC filter.
Since we already have 180ophase shift from the
output filter alone, the system runs the risk of
being unstable.
The IR3842A uses a voltage-type error amplifier
with high-gain (110dB) and wide-bandwidth. The
output of the amplifier is available for DC gain
control and AC phase compensation.
The error amplifier can be compensated either in
type II or type III compensation.
Local feedback with Type II compensation is
shown in Fig. 14.
This method requires that the output capacitor
should have enough ESR to satisfy stability
requirements. In general the output capacitor’s
ESR generates a zero typically at 5kHz to 50kHz
which is essential for an acceptable phase
margin.
The ESR zero of the output capacitor is
expressed as follows:
(16) ................................
oo
LC CL
F∗∗
=
π
2
1
Fig. 13. Gain and Phase of LC filter
(17) ...........................
o
ESR *ESR*C
F
π
∗
=21
Output Capacitor Selection
The voltage ripple and transient requirements
determine the output capacitors type and values.
The criteria is normally based on the value of the
Effective Series Resistance (ESR). However the
actual capacitance value and the Equivalent Series
Inductance (ESL) are other contributing
components. These components can be described
as
Rev 13.0 21
PD-97510
IR3842AMPbF
The transfer function (Ve/Vo) is given by:
The (s) indicates that the transfer function varies
as a function of frequency. This configuration
introduces a gain and zero, expressed by:
First select the desired zero-crossover frequency
(Fo):
Use the following equation to calculate R3:
V
OUT
V
REF
R9
R8
CPOLE
C4
R3
Ve
FZFPOLE
E/A
Zf
Frequency
Gain(dB)
H(s) dB
Fb
Comp
ZIN
Fig. 14. Type II compensation network
and its asymptotic gain plot
(18) ..... )(
48
43
1
CsR
CsR
Z
Z
sH
V
V
IN
f
o
e+
−=−==
()
(20) ............................
**
(19) ............................. .........
43
8
3
21
CR
F
R
R
sH
z
π
=
=
()
sESRo FFF *1/10~1/5 F and
o
≤>
(21) ...........................
*
***
28
3
LCin
ESRoosc
FV
RFFV
R=
Where:
Vin = Maximum Input Voltage
Vosc = Oscillator Ramp Voltage
Fo= Crossover Frequency
FESR = Zero Frequency of the Output Capacitor
FLC = Resonant Frequency of the Output Filter
R8= Feedback Resistor
To cancel one of the LC filter poles, place the
zero before the LC filter resonant frequency pole:
Use equations (20), (21) and (22) to calculate
C4.
One more capacitor is sometimes added in
parallel with C4 and R3. This introduces one
more pole which is mainly used to suppress the
switching noise.
The additional pole is given by:
The pole sets to one half of the switching
frequency which results in the capacitor CPOLE:
For a general solution for unconditional stability
for any type of output capacitors, and a wide
range of ESR values, we should implement local
feedback with a type III compensation network.
The typically used compensation network for
voltage-mode controller is shown in figure 15.
Again, the transfer function is given by:
By replacing Zin and Zfaccording to figure 15,
the transfer function can be expressed as:
(22) .....................................
*
*.
%
oo
z
LCz
CL
F
FF
π
2
1
750
75
=
=
...(23)..............................
*
**
POLE
POLE
P
CC
CC
R
F
+
=
4
4
3
2
1
π
(24)......................
s
s
POLE *F*R
C
*F*R
C
3
4
3
1
1
1
π
π
≅
−
=
IN
f
o
e
Z
Z
sH
V
V−== )(
()
[
]
(25) ....
)(
*
)(
)(
)(
710
34
34
3348
108743
11
11
CsR
CC
CC
sRCCsR
RRsCCsR
sH
+
⎥
⎥
⎦
⎤
⎢
⎢
⎣
⎡
⎟
⎟
⎠
⎞
⎜
⎜
⎝
⎛
+
++
+++
−=
Rev 13.0 22
PD-97510
IR3842AMPbF
Tantalum
Ceramic
FLC<Fo<FESR
Type III
Electrolytic
Tantalum
FLC<FESR<Fo<Fs/2Type II
Output
Capacitor
FESR vs Fo
Compensator
Type
Tantalum
Ceramic
FLC<Fo<FESR
Type III
Electrolytic
Tantalum
FLC<FESR<Fo<Fs/2Type II
Output
Capacitor
FESR vs Fo
Compensator
Type
The compensation network has three poles and
two zeros and they are expressed as follows:
Cross over frequency is expressed as:
Fig.15. Type III Compensation network and
its asymptotic gain plot
(30)..........
**)(**
.....(29)........................................
**
(28) ...............
**
*
*
) .......(27........................................
**
......(26)............................................................
871087
2
43
1
33
34
34
3
3
710
2
1
21
21
21
21
2
1
21
0
RCRRC
F
CR
F
CR
CC
CC
R
F
CR
F
F
Z
Z
P
P
P
ππ
π
π
π
π
≅
+
=
=
≅
⎟
⎟
⎠
⎞
⎜
⎜
⎝
⎛
+
=
=
=
(31) ................................
**
***
ooosc
in
oCLV
V
CRF
π
21
73
=
The higher the crossover frequency, the
potentially faster the load transient response.
However, the crossover frequency should be low
enough to allow attenuation of switching noise.
Typically, the control loop bandwidth or crossover
frequency is selected such that
The DC gain should be large enough to provide
high DC-regulation accuracy. The phase margin
should be greater than 45ofor overall stability.
For this design we have:
Vin=12V
Vo=1.8V
Vosc=1.8V
Vref=0.7V
Lo=1 uH
Co=6x22uF, ESR=3mOhm each
It must be noted here that the value of the
capacitance used in the compensator design
must be the small signal value. For instance, the
small signal capacitance of the 22uF capacitor
used in this design is 12uF at 1.8 V DC bias and
600 kHz frequency. It is this value that must be
used for all computations related to the
compensation. The small signal value may be
obtained from the manufacturer’s datasheets,
design tools or SPICE models. Alternatively, they
may also be inferred from measuring the power
stage transfer function of the converter and
measuring the double pole frequency FLC and
using equation (16) to compute the small signal
Co.
These result to:
FLC=20.55 kHz
FESR=4.4 MHz
Fs/2=300 kHz
Select crossover frequency: Fo=100 kHz
Since FLC<Fo<Fs/2<FESR, TypeIII is selected to
place the pole and zeros.
(
)
so F F *1/10~1/5≤
V
OUT
V
REF
R9
R8
R10
C7
C3
C4
R3
Ve
F
Z
1F
Z
2F
P
2F
P
3
E/A
Zf
ZIN
Frequency
Gain(dB)
H(s) dB
Fb
Comp
Based on the frequency of the zero generated by
the output capacitor and its ESR, relative to
crossover frequency, the compensation type can
be different. The table below shows the
compensation types and location of the
crossover frequency.
Rev 13.0 23
PD-97510
IR3842AMPbF
Detailed calculation of compensation TypeIII
Ω=Ω==
Ω=
Ω==
Ω=Ω==
===
===
Ω=
Ω==
=
==
==
=
Θ−
Θ+
=
=
Θ+
Θ−
=
=Θ
k 2.55 :Select k 2.57 ;*
k 4.02:Select
,k 3.97 ;
**
130 :Select , 128 ;
**
: and , Calculate
pF 160 :Select
,pF 171.69 ;
**
nF 5.6 :Select nF, 84.5 ;
**2
1
k 3.09 :Select
k 3.08;
*
****
: and , Calculate
nF 2.2C :Select
kHz 300*0.5
and kHz 8.82 *. :Select
kHz 567.1
sin
sin
kHz 17.63
sin
sin
70 Margin Phase Desired
3
7
o
9989
8
810
27
8
1010
27
10
9810
33
33
3
44
1
4
3
3
7
3
433
3
21
2
2
-
-
21
21
21
2
50
1
1
1
1
RRR
VV
V
R
R
RR
FC
R
RR
FC
R
RRR
CC
RF
C
CC
RF
C
R
R
VC
VCLF
R
CCR
FF
FF
FF
FF
refo
ref
Z
P
P
Z
in
oscooo
sP
ZZ
oP
oZ
π
π
π
π
π
Programming the Current-Limit
The Current-Limit threshold can be set by
connecting a resistor (ROCSET) from the SW pin
to the OCSet pin. The resistor can be calculated
by using equation (4). This resistor ROCSET must
be placed close to the IC.
The RDS(on) has a positive temperature
coefficient and it should be considered for the
worst case operation.
Setting the Power Good Threshold
Power Good threshold is internally set at 88% of
Vref. When the voltage at the FB pin exceeds the
threshold, PGood is asserted.
The PGood is an open drain output. Hence, it is
necessary to use a pull up resistor RPG from
PGood pin to Vcc. The value of the pull-up
resistor must be chosen such as to limit the
current flowing into the PGood pin, when the
output voltage is not in regulation, to less than 5
mA. A typical value used is 10kΩ.
Ω=Ω=
==
==≅
Ω=Ω=
k 2.67 Select k 2.694R
kHz) 600 (atμA 59.07I
) current output nominal over (50%
A 91.5 A6
m 17.8751.25m 14.3
OCSet
OCSet
)(
)(
7
*
*
R
F
II
R
s
LIMoSET
onDS
(32) .......................
)(
)(
R
IR
II
onDS
OCSetOCSet
criticalLSET
∗
==
Rev 13.0 24
PD-97510
IR3842AMPbF
Application Diagram:
Fig. 16. Application circuit diagram for a 12V to 1.8 V, 6 A Point Of Load Converter
Suggested Bill of Materials for the application circuit:
Part Reference Quantity Value Description Manufacturer Part Number
1 330uF SMD Elecrolytic, Fsize, 25V, 20% Panasonic EEV-FK1E331P
2 10uF 1206, 16V, X5R, 20% TDK C3216X5R1E106M
1 0.1uF 0603, 25V, X7R, 10% Panasonic ECJ-1VB1E104K
Lo 1 1.0uH 11.5x10x5mm, 20%, 2.3mOhm Delta MPL105-1R0IR
Co 6 22uF 0805, 6.3V, X5R, 20% Panasonic ECJ-2FB0J226ML
R1 1 49.9k Thick Film, 0603,1/10 W,1% Rohm MCR03EZPFX4992
R2 1 7.5k Thick Film, 0603,1/10W,1% Rohm MCR03EZPFX7501
Rt1 23.7k Thick Film, 0603,1/10W,1% Rohm MCR03EZPFX2372
Rocset 1 2.67k Thick Film, 0603,1/10W,1% Rohm MCR03EZPFX2671
RPG 1 10k Thick Film, 0603,1/10W,1% Rohm MCR03EZPFX1002
Css C6 2 0.1uF 0603, 25V, X7R, 10% Panasonic ECJ-1VB1E104K
R3 1 3.09k Thick Film, 0603,1/10W,1% Rohm MCR03EZPFX3091
C3 1 160pF 50V, 0603, NPO, 5% Panasonic ECJ-1VC1H161J
C4 1 5.6nF 0603, 50V, X7R, 10% Panasonic ECJ-1VB1H562K
R8 1 4.02k Thick Film, 0603,1/10W,1% Rohm MCR03EZPFX4021
R9 1 2.55k Thick Film, 0603,1/10W,1% Rohm MCR03EZPFX2551
R10 1 130 Thick Film, 0603,1/10W,1% Rohm ERJ-3EKF1300V
C7 1 2200pF 0603, 50V, X7R, 10% Panasonic ECJ-1VB1H222K
CVcc 1 1.0uF 0603, 16V, X5R, 20% Panasonic ECJ-BVB1C105M
U1 1 IR3842A SupIRBuck, 6A, PQFN 5x6mm International Rectifier IR3842AMPbF
Cin
Rev 13.0 25
PD-97510
IR3842AMPbF
TYPICAL OPERATING WAVEFORMS
Vin=12.0V, Vcc=5V, Vo=1.8V, Io=0-6A, Room Temperature, No Air Flow
Fig. 20. Output Voltage Ripple, 6A
load Ch2: Vo
Fig. 21. Inductor node at 6A load
Ch1:LX
Fig. 22. Short (Hiccup) Recovery
Ch2:Vo , Ch3:VSS
Fig. 18. Start up at 6A Load,
Ch1:Vin, Ch2:Vo, Ch3:Vss, Ch4:VPGood
Fig. 17. Start up at 6A Load
Ch1:Vin, Ch2:Vo, Ch3:Vss, Ch4:Enable
Fig. 19. Start up with 1.62V Pre
Bias, 0A Load, Ch2:Vo, Ch3:VSS
Rev 13.0 26
PD-97510
IR3842AMPbF
TYPICAL OPERATING WAVEFORMS
Vin=12V, Vcc=5V, Vo=1.8V, Io=3A-6A, Room Temperature, No Air Flow
Fig. 23. Transient Response, 3A to 6A step
2.5A/μs
Ch2:Vo, Ch4:Io
Rev 13.0 27
PD-97510
IR3842AMPbF
TYPICAL OPERATING WAVEFORMS
Vin=12V, Vcc=5V, Vo=1.8V, Io=6A, Room Temperature, No Air Flow
Fig. 24. Bode Plot at 6A load shows a bandwidth of 103kHz and phase margin of 54
degrees
Rev 13.0 28
PD-97510
IR3842AMPbF
Simultaneous Tracking at Power Up and Power Down
Vin=12V, Vo=1.8V, Io=6A, Room Temperature, No Air Flow
Fig. 25: Simultaneous Tracking a 3.3V input at power-up and shut-down
Ch2: Vout (1.8V) Ch3:SS (1.8V) Ch4: Seq (3.3V)
Fb
IR3624
V
OUT
R
9
R
8
IR3842A
3.3V
Rs2
Rs1 Seq
4.02K
4.02K
2..55K 2.55K
Rev 13.0 29
PD-97510
IR3842AMPbF
Layout Considerations
The layout is very important when designing high
frequency switching converters. Layout will affect
noise pickup and can cause a good design to
perform with less than expected results.
Make all the connections for the power
components in the top layer with wide, copper
filled areas or polygons. In general, it is desirable
to make proper use of power planes and
polygons for power distribution and heat
dissipation.
The inductor, output capacitors and the IR3842A
should be as close to each other as possible.
This helps to reduce the EMI radiated by the
power traces due to the high switching currents
through them. Place the input capacitor directly at
the Vin pin of IR3842A.
The feedback part of the system should be kept
away from the inductor and other noise sources.
The critical bypass components such as
capacitors for Vcc should be close to their
respective pins. It is important to place the
feedback components including feedback
resistors and compensation components close to
Fb and Comp pins.
PGnd
Vin
AGnd Vout
PGnd
Vin
AGnd Vout
The connection between the OCSet resistor and
the Sw pin should not share any trace with the
connection between the bootstrap capacitor and
the Sw pin. Instead, it is recommended to use a
Kelvin connection of the trace from the OCSet
resistor and the trace from the bootstrap
capacitor at the Sw pin.
In a multilayer PCB use one layer as a power
ground plane and have a control circuit ground
(analog ground), to which all signals are
referenced. The goal is to localize the high
current path to a separate loop that does not
interfere with the more sensitive analog control
function. These two grounds must be connected
together on the PC board layout at a single point.
The Power QFN is a thermally enhanced
package. Based on thermal performance it is
recommended to use at least a 4-layers PCB. To
effectively remove heat from the device the
exposed pad should be connected to the ground
plane using vias. Figure 26 illustrates the
implementation of the layout guidelines outlined
above, on the IRDC3842A 4 layer demoboard.
PGnd
Vin
AGnd Vout
All bypass caps
should be placed as
close as possible to
their connecting
pins.
Resistors Rt and
Rocset should be
placed as close as
possible to their pins.
Enough copper &
minimum length
ground path between
Input and Output
PGnd
Vin
AGnd
Vout
Compensation parts
should be placed as close
as possible to
the Comp pin.
Fig. 26a. IRDC3842A demoboard layout
considerations – Top Layer
Rev 13.0 30
PD-97510
IR3842AMPbF
PGnd
Vin
AGnd
Power
Ground
Plane
Analog
Ground
plane
Single point
connection between
AGND & PGND,
should be close to
the SupIRBuck, kept
away from noise
sources.
Use separate traces
for connecting Boot
cap and Rocset to the
switch node and with
the minimum length
traces. Avoid big
loops.
Fig. 26c. IRDC3842A demoboard layout
considerations – Mid Layer 1
Fig. 26d. IRDC3842A demoboard layout
considerations – Mid Layer 2
Feedback
trace should
be kept
away form
noise
sources
Fig. 26b. IRDC3842A demoboard layout
considerations – Bottom Layer
Rev 13.0 31
PD-97510
IR3842AMPbF
PCB Metal and Components Placement
Lead lands (the 11 IC pins) width should be equal to nominal part lead width. The
minimum lead to lead spacing should be ≥0.2mm to minimize shorting.
Lead land length should be equal to maximum part lead length + 0.3 mm outboard
extension. The outboard extension ensures a large and inspectable toe fillet.
Pad lands (the 4 big pads other than the 11 IC pins) length and width should be equal to
maximum part pad length and width. However, the minimum metal to metal spacing
should be no less than 0.17mm for 2 oz. Copper; no less than 0.1mm for 1 oz. Copper
and no less than 0.23mm for 3 oz. Copper.
Rev 13.0 32
PD-97510
IR3842AMPbF
Solder Resist
It is recommended that the lead lands are Non Solder Mask Defined (NSMD). The solder
resist should be pulled away from the metal lead lands by a minimum of 0.025mm to ensure
NSMD pads.
The land pad should be Solder Mask Defined (SMD), with a minimum overlap of the solder
resist onto the copper of 0.05mm to accommodate solder resist mis-alignment.
Ensure that the solder resist in-between the lead lands and the pad land is ≥0.15mm due
to the high aspect ratio of the solder resist strip separating the lead lands from the pad land.
Rev 13.0 33
PD-97510
IR3842AMPbF
Stencil Design
• The Stencil apertures for the lead lands should be approximately 80% of the area of
the lead lads. Reducing the amount of solder deposited will minimize the
occurrences of lead shorts. If too much solder is deposited on the center pad the part
will float and the lead lands will be open.
• The maximum length and width of the land pad stencil aperture should be equal to
the solder resist opening minus an annular 0.2mm pull back to decrease the
incidence of shorting the center land to the lead lands when the part is pushed into
the solder paste.
Rev 13.0 34
PD-97510
IR3842AMPbF
IR WORLD HEADQUARTERS: 233 Kansas St., El Segundo, California 90245, USA Tel: (310) 252-7105
TAC Fax: (310) 252-7903
This product has been designed and qualified for the Industrial market (Note5)
Visit us at www.irf.com for sales contact information
Data and specifications subject to change without notice. 08/12
BOTTOM VIEW
