Rev 1.2 1/16 Copyright © 2016 by Silicon La boratories Si4356
Si4356
Si4356 STANDALONE SUB-GHZ RECEIVER
Features
Applications
Description
Silicon Laboratories' Si4356 is a pin-strap configurable, low current,
sub-GHz EZRadio® receiver. With no external MCU control needed, the
Si4356 provides a true plug-and-play receive option. Excellent sensitivity
up to –113 dBm allows for a longer operating range, while the low current
consumption of 12 mA active and 50 nA standby provides for superior
battery life. The Si4356 provides receive data as well as a system clock
output for use by an external microcontroller or decoder.
Pin configurable
Frequency range = 315–917 MHz
Supply Voltage = 1.8–3.6 V
Receive sensitivity =
Up to –113 dBm
Modulation
(G)FSK
OOK
Low RX Current = 12 mA
Low standby current = 50 nA
Max data rate = 120 kbps
Automatic gain control (AGC)
System clock output
Low BOM
20-pin 3x3 mm QFN package
Remote control
Home security and alarm
Garage and gate openers
Remote keyless entry
Home automation
Industrial control
Sensor networks
Health monitors
Patents pending
Pin Assignments
20-pin QFN
(Top View)
1
2
3
4
5
6 7 8 9 10
16
15
14
13
12
11
20 19 18 17GND
RST
RXp
RXn
NC
GND
GND
SEL1
RX_DATA / OUT1
STBY
MSTAT / OUT0
SEL0
VDD
VDD
GND
CLK_OUT
SEL3
SEL2
XIN
XOUT
GND
Si4356
2 Rev 1.2
Functional Block Diagram
Rx Modem
Synthesizer
LNA PGA ADC
Rx Chain
Configuration Decoder
30MHz XO
RXp
RXn
VDD SEL0
CLK_OUT
RX_DATA / OUT1
XOUTXIN
SEL1 SEL3
STBY
SEL2
MSTAT / OUT0
÷
RST
GND
Si4356
Rev 1.2 3
TABLE OF CONTENTS
Section Page
1. Electrical Specifications . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .4
1.1. Definition of Test Conditions . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .8
2. Typical Applications Circuit . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .9
3. Device Configuration . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .11
4. Functional Description . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .13
5. Modes and Timing . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .14
5.1. Power on Reset (POR) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .14
6. Additional Features . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .17
6.1. System Clock Output . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .17
7. Pin Descriptions . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .18
8. Ordering Information . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .20
9. Package Outline . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .21
10. PCB Land Pattern . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .23
11. Top Marking . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .24
11.1. Si4356 Top Marking . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .24
11.2. Top Marking Explanation . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .24
Document Change List . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .25
Contact Information . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .26
Si4356
4 Rev 1.2
1. Electrical Specifications
Table 1. Recommended Operating Conditions
Parameter Symbol Test Condition Min Typ Max Unit
Ambient Temperature TA— –40 25 85 C
Supply Voltage VDD —1.8—3.6V
I/O Drive Voltage VGPIO —1.8—3.6V
Table 2. DC Characteristics*
Parameter Symbol Test Condition Min Typ Max Unit
Standby Mode Current IStandby Configuration retained, all other functions OFF — 50 — nA
RX Mode Current IRX ——12—mA
*Note: All specifications guaranteed by production test unless otherwise noted. Production test conditions and max limits are
listed in the "Production Test Conditions" section of "1.1. Definition of Test Conditions" on page 8.
Table 3. Receiver Electrical Characteristics1
Parameter Symbol Test Condition Min Typ Max Unit
Frequency Range FRANGE Only frequencies listed in Table 9
supported
315 — 917 MHz
Sensitivity2PFSK BER < 0.1%, 2.4 kbps, (G)FSK,
Configuration = FSK1 (See Section 3.)
—–113—dBm
PFSK BER < 0.1%, 2.4 kbps, (G)FSK,
Configuration = FSK6 (See Section 3.)
–104 dBm
POOK BER < 0.1%, 2.4 kbps, OOK,
Configuration = OOK6 (See Section 3.)
—–111—dBm
RX Channel Bandwidth3BW — 100 — 535 kHz
BER Variation vs Power
Level3
PRX_RES Up to +5 dBm Input Level — 0 0.1 ppm
Notes:
1. Test conditions and max limits are listed in section “1.1. Definition of Test Conditions”.
2. Sensitivity measured at 434 MHz using a PN9 modulated input signal. Received signal is filtered, deglitched, and
retimed using an external RC filter (R = 1 k, C = 47 nF) and MCU.
3. Guaranteed by qualification. Qualification test conditions are listed in section “1.1. Definition of Test Conditions”.
Si4356
Rev 1.2 5
200 kHz Selectivity3C/I1-CH Desired Ref Signal 3 dB above sensitiv-
ity, BER < 0.1%. Interferer is CW and
desired modulated with
2.4 kbps F = 30 kHz (G)FSK,
BT = 0.5,
Rx BW = 155 kHz,
—–42—dB
400 kHz Selectivity3C/I2-CH —–50—dB
Blocking 1 MHz Offset3— Desired Ref Signal 3 dB above sensitiv-
ity, BER < 0.1% Interferer is CW and
desired modulated with 2.4 kbps
F = 30 kHz (G)FSK, BT = 0.5,
RX BW = 155 kHz
—–57—dB
Blocking 8 MHz Offset3——–68—dB
Image Rejection3ImREJ IF = 468 kHz — –35 — dB
Spurious Emissions3POB_RX1 Measured at RX pins — — –54 dBm
Table 4. Auxiliary Block Specifications1
Parameter Symbol Test Condition Min Typ Max Unit
XTAL Nominal Cap3———10—pF
XTAL Frequency — — — 30 — MHz
XTAL Series Resistance — — — — 50
XTAL Stability — — — ±50 — ppm
Reset to RX Time2tRST ———20ms
Notes:
1. Test conditions and max limits are listed in section in “1.1. Definition of Test Conditions”.
2. Guaranteed by qualification. Qualification test conditions are listed in the "Qualification Test Conditions" subsection of
section “1.1. Definition of Test Conditions”.
3. Targeted nominal capacitive load for both XIN and XOUT pins.
Table 3. Receiver Electrical Characteristics1 (Continued)
Parameter Symbol Test Condition Min Typ Max Unit
Notes:
1. Test conditions and max limits are listed in section “1.1. Definition of Test Conditions”.
2. Sensitivity measured at 434 MHz using a PN9 modulated input signal. Received signal is filtered, deglitched, and
retimed using an external RC filter (R = 1 k, C = 47 nF) and MCU.
3. Guaranteed by qualification. Qualification test conditions are listed in section “1.1. Definition of Test Conditions”.
Si4356
6 Rev 1.2
Table 5. Digital I/O Specifications (STBY, RX_DATA, MSTAT, CLK_OUT)1
Parameter Sym bo l Test Condition Min Typ Max Unit
Rise Time TRISE 0.1xVDD to 0.9xVDD,
CL=10pF, DRV<1:0≥HH
—2.3 — ns
Fall Time TFALL 0.9xVDD to 0.1xVDD,
CL=10pF, DRV<1:0≥HH
—2.0 — ns
Input Capacitance CIN —–2—pF
Logic High Level Input
Voltage
VIH —V
DDx0.7 – — V
Logic Low Level Input
Voltage
VIL ———V
DDx0.3 V
Input Current (STBY)2IIN 0<VIN<VDD –10 — 10 µA
Input Current (STBY)2IINP VIL = 0 V 1 — 10 µA
Drive Strength for Out-
put Low Level2, 3
IOL RX_DATA, MSTAT, CLK_OUT — 1.13 — mA
Drive Strength for Out-
put High Level2, 3
IOH RX_DATA, MSTAT — 0.96 — mA
Drive Strength for Out-
put High Level2, 3
IOH CLK_OUT — 0.80 — mA
Logic High Level Out-
put Voltage
VOH IOUT = 500 µA VDDx0.8 – — V
Logic Low Level Out-
put Voltage
VOL IOUT = 500 µA — — VDDx0.2 V
CLK_OUT Frequency FCLK Rx Freq = 315 MHZ — 10 — MHz
All other frequencies — 15 — MHz
CLK_OUT Duty Cycle — — — 50 — %
Notes:
1. Guaranteed by qualification. Qualification test conditions are listed in Section “1.1. Definition of Test Conditions”.
2. Currents listed are during normal operation after power up sequence is complete.
3. Output currents measured at 3.3 VDC VDD with VOH = 2.64 VDC and VOL = 0.66 VDC.
Table 6. Thermal Characteristics
Parameter Symbol Test Condition Value Unit
Thermal Resistance Junction to Ambient JA Still Air 30 C/W
Si4356
Rev 1.2 7
Table 7. Absolute Maximum Ratings
Parameter Value Unit
VDD to GND –0.3 to +3.6 V
Voltage on Digital Control Inputs –0.3 to VDD + 0.3 V
Voltage on Analog Inputs –0.3 to VDD + 0.3 V
RX Input Power +10 dBm
Operating Ambient Temperature Range TA–40 to +85 C
Storage Temperature Range TSTG –55 to +125 C
Note: Stresses beyond those listed under “Absolute Maximum Ratings” may cause permanent damage to the device. These
are stress ratings only and functional operation of the device at or beyond these ratings in the operational sections of
the specifications is not implied. Exposure to absolute maximum rating conditions for extended periods may affect
device reliability. Caution: ESD sensitive device.
Si4356
8 Rev 1.2
1.1. Definition of Test Conditions
Production Test Conditions:
TA=+25°C
VDD =+3.3VDC
External reference signal (XIN) = 1.0 VPP at 30 MHz, centered around 0.8 VDC
Production test schematic (unless noted otherwise)
All RF input levels referred to the pins of the Si4356 (not the RF module)
Qualification Test Conditions:
TA = –40 to +85 °C (typical = 25 °C)
VDD = +1.8 to +3.6 VDC (typical = 3.3 VDC)
Using reference design or production test schematic
All RF input levels are referred to the antenna port of Si4356 reference design or to the pins of the Si4356
when the production test setup is used.
Si4356
Rev 1.2 9
2. Typical Applications Circuit
Figure 1. Si4356 Applications Circuit
Table 8. Si4356 Recommended Matching Values
Frequency
(MHz) C1
(pF) C2
(pF) C3
(pF) L1
(nH) L2
(nH)
433.92 270 2.7 5.1 56 56
315.00 470 3.0 6.2 82 100
434.15 270 2.7 5.1 56 56
867.84 68 1.2 3.0 22 18
868.30 56 1.2 3.0 22 18
917.00 56 1.0 3.0 22 18
Note: Multi-layer inductors and ceramic chip capacitors with tolerance of ±5% are recommended.
100 pF 100 nF
C4 C5 C6
VDD
C1 C2
L2
L1
C3
1
2
3
4
5
6
7
8
9
10
11
12
13
14
15
16
17
18
19
20
Si4356
30 MHz
1 F
SEL1
RX_DATA/OUT1
STBY
MSTAT/OUT0
SEL0
CLK_OUT
GND
VDD
VDD
GND
NC
RXn
RXp
RST
GND
SEL3
SEL2
XIN
XOUT
GND
Si4356
10 Rev 1.2
Figure 2 shows the application circuit for a particular radio configuration (433.92 MHz, OOK, 2 kbps, 206 kHz
RxBW) with all optional connections. See Sections 5 and 7 for Si4356 pin functionality.
Figure 2. Si4356 Application Circuit Example
Note:
1. R1 is required to minimize power up current. R1 is only necessary for pin configurations where SEL2 or SEL3 is
mapped to GND.
2. An optional external low-pass RC filter may be connected to RX_DATA to filter the output and improve sensitivity.
R2 and C7 should be selected to realize a cut-off frequency that is ~40% larger than that targeted data rate
according to fc = 1/(2RC).
30 MHz
L1
GND
SEL0
19
18
17
16
1
2
3
4
15
14
13
7
8
9
10
SEL1
RX_DATA/OUT1
2
STBY
RXn
RST
RXp
XIN
SEL3
GND
XOUT
5
NC
620
SEL2
11
12
C2
Si4356
MSTAT/OUT0
VDD
100 nF
C5
100 pF
C4
1μF
L2
C3
C6
MCU
Data In
Rx STBY (Optional)
Clock In (Optional)
VDD
Reset (Optional)
Mode Status (Optional)
C1
270 pF 2.7 pF
5.1 pF
56 nH
56 nH
10 k:
R1
1
GND
VDD
VDD
GND
CLK_OUT
R2 C7
Optional RC Filter
2
Si4356
Rev 1.2 11
3. Device Configuration
The Si4356 is configured for operation using the four configuration selector pins (SEL0 – SEL3). These pins will be
connected to one of four possible inputs: GND, VDD, RX DATA/OUT1 (pin 14), or OUT0 (pin 12). Refer to the
tables below for how these pins should be connected for the desired configuration.
SEL0 and SEL1 may be connected to VDD, GND, or OUT1 to choose desired frequency. Note that a 10 k
resistor should be inserted between SEL1 and OUT1 when SEL1 is mapped to OUT1. See Table 9 for frequency
settings.
SEL2 and SEL3 may be connected to VDD, GND, or OUT1 to choose desired modem configuration. See Table 10
for basic configurations. Note that a 10 k resistor should inserted between SEL2 and/or SEL3 and GND when
SEL2 and/or SEL3 are mapped to GND.
Table 9. Frequency Selection
SEL0 SEL1 F requency (MHz)
GND VDD 433.92
VDD VDD 315.00
OUT1 VDD 434.15
GND OUT1 867.84
VDD OUT1 868.30
OUT1 OUT1 917.00
Table 10. Basic Configuration
Config.
Name SEL2 SEL3 Mod Data Rate
(kbps) RxBW (kHz) Squelch Recommended
FDEV (kHz)
OOK1 GND GND OOK 0.5–5 206 Disabled —
OOK2 VDD GND OOK 1–10 370 Disabled —
OOK3 OUT1 GND OOK 10–50 370 Disabled —
OOK4 OUT0 GND OOK 50–120 370 Disabled —
OOK5 GND VDD OOK 50–120 535 Disabled —
OOK6 VDD VDD OOK 0.5–2.4 100 Disabled —
FSK1 GND OUT1 (G)FSK 0.5–30 155 Disabled 30
FSK2 VDD OUT1 (G)FSK 0.5–30 185 Disabled 70
FSK3 OUT1 OUT1 (G)FSK 0.5–30 275 Disabled 30
FSK4 OUT0 OUT1 (G)FSK 10–120 275 Disabled 70
FSK5 GND OUT0 (G)FSK 10–120 535 Disabled 70
FSK6 VDD OUT0 (G)FSK 0.5–2.4 155 Enabled 30
FSK7 OUT1 OUT0 (G)FSK 0.5–2.4 275 Enabled 30
Si4356
12 Rev 1.2
To disable the system clock, connect CLK_OUT to OUT0. Otherwise, CLK_OUT is enabled. See Table 11 settings.
Table 11. System Clock
CLK_OUT (Pin 10) Clock Output
OUT0 OFF
XON
Si4356
Rev 1.2 13
4. Functional Description
Figure 3. Si4356 Functional Block Diagram
The Si4356 is an easy-to-use, size efficient, low current wireless receiver that covers the sub-GHz bands. The wide
operating voltage range of 1.8–3.6 V and low current consumption make the Si4356 an ideal solution for battery
powered applications. The Si4356 uses a single-conversion mixer to downconvert the (G)FSK or OOK modulated
receive signal to a low IF frequency. Following a programmable gain amplifier (PGA), the signal is converted to the
digital domain by a high performance  ADC, thus allowing filtering and demodulation to be performed in the
built-in DSP and increasing the receiver's performance and flexibility versus analog based architectures. The
receiver demodulates the incoming data asynchronously by oversampling the incoming transmission. The resulting
demodulated signal is output to the system MCU through data output pin RX_DATA.
Integrated configuration tables allow the Si4356 to be completely configured using the four selector pins. The state
of each of these pins is read internally at startup and used to determine which pre-loaded configuration should be
used. The Si4356 then loads this configuration without the need for any external MCU control.
The Si4356 includes an integrated crystal oscillator. The design is differential with the typical crystal load
capacitance integrated on-chip to accommodate a 30 MHz off-chip crystal.
Rx Modem
Synthesizer
LNA PGA ADC
Rx Chain
Configuration Decoder
30MHz XO
RXp
RXn
VDD SEL0
CLK_OUT
RX_DATA / OUT1
XOUTXIN
SEL1 SEL3
STBY
SEL2
MSTAT / OUT0
÷
RST
GND
Si4356
14 Rev 1.2
5. Modes and Timing
At initial startup, the Si4356 reads the selector pins and loads all registers with the appropriate values for the
selected configuration, as shown in the Figure 4.
Figure 4. Power Up Timing
5.1. Power on Reset (POR)
A Power On Reset (POR) sequence is used to boot the device up from a fully off or shutdown state. To execute this
process, VDD must ramp within 1ms and must remain applied to the device for at least 10 ms. If VDD is removed,
then it must stay below 0.15 V for at least 10 ms before being applied again. See Figure 5 and Table 12 for details.
2 mA
3 mA
9mA
10 ms 8.5 ms
12 mA
3 ms
Total
Current
MSTAT
(Pin12)
RX_ DATA
(Pin14)
CLK_ OUT
(Pin10)
2.9 Vp-p
2.5 mA
1ms
VDD
Si4356
Rev 1.2 15
Figure 5. POR Timing Diagram
The Si4356 provides two operating modes, a receive mode and a standby mode. The operating mode can be
changed by toggling STBY (pin 13) as described in Figure 6. Care should be taken to minimize the trace connected
to STBY to avoid external noise coupling that could result in unintended mode changes. The MSTAT signal (pin 12)
indicates the current operating mode of the device as defined in Table 13 and illustrated in Figure 6.
Table 12. POR Timing
Variable Description Min Typ Max Units
tPORH High time for VDD to fully settle POR circuit 10 ms
tPORL Low time for VDD to enable POR 10 ms
VRRH Voltage for successful POR 90% x Vdd V
VRRL Starting Voltage for successful POR 0150mV
tSR Slew rate of VDD for successful POR 1ms
Table 13. Operating Mode Status
Pin 12 (MSTAT) Mode
LOW Receive
HIGH Standby
VDD
Time
VRRH
tSR tPORH
VRRL
Si4356
16 Rev 1.2
Figure 6. Standby Control and Timing
Once in standby mode, the device shuts down most functions, allowing for very low current consumption, but it still
maintains all register settings for a fast transition back to the receive operating mode, as shown in Table 14.
It is also possible to reset the device by using RST (pin 2). This mode briefly cycles power on the device, before
retuning the device to the receive operating mode as shown in Figure 7. The device takes approximately 20 ms to
transition from reset to Receive mode.
Table 14. Operating State Response Time and Current Consumption
State / Mode Response Time to Rx Cu rrent in State /Mode
Standby 0.5 ms 50 nA
Receive N/A 12 mA
Si4356
Rev 1.2 17
Figure 7. Device Reset Control and Timing
6. Additional Features
6.1. System Clock Output
A clock output is available on CLK_OUT (pin 10) of the Si4356, which can be used to drive an external MCU and
avoid the need for additional oscillators in the application. The clock signal is valid when MSTAT is low. The clock
frequency is set to 10 MHz for 315 MHz RX frequency selection and 15 MHz for all other frequencies. If this clock
signal is not needed, then it can be turned off by connecting CLK_OUT (pin 10) to MSTAT/OUT0 (pin 12). The
clock signal is turned off during Standby and Device Reset modes.
2mA
3mA
9mA
10ms 8.5ms
1ms
12mA12mA
>1 ms
RST
(Pin2)
Total
Current
MSTAT
(Pin12)
RX_ DATA
(Pin14)
CLK_OUT
(Pin10)
2.9Vp-p
2.5mA
Si4356
18 Rev 1.2
7. Pin Descriptions
Pin Pin Name I/O Description
1GNDGND
Ground
2RSTI
Device reset
3RXpI
Differential RF receiver input pin
4RXnI
Differential RF receiver input pin
5NC No Connect
6GNDGND
Ground
7VDDV
DD Supply Voltage
8VDDV
DD Supply Voltage
9GNDGND
Ground
10 CLK_OUT O System reference clock output
11 SEL0 I Configuration selector pin
12 MSTAT
OUT0
O
O
Mode status (Rx = 0, STBY = 1)
Configuration output pin
13 STBY I Standby mode toggle
14 RX_DATA
OUT1
O
O
Receiver raw data output
Configuration output pin
15 SEL1 I Configuration selector pin
1
2
3
4
5
678910
16
15
14
13
12
11
20 19 18 17GND
RST
RXp
RXn
NC
GND
GND
SEL1
RX_DATA / OUT1
STBY
MSTAT / OUT0
SEL0
VDD
VDD
GND
CLK_OUT
SEL3
SEL2
XIN
XOUT
GND
Si4356
Rev 1.2 19
16 GND GND GND
17 XOUT O Crystal oscillator output
18 XIN I Crystal oscillator input
19 SEL2 I Configuration selector pin
20 SEL3 I Configuration selector pin
Pin Pin Name I/O Description
Si4356
20 Rev 1.2
8. Ordering Information
Part Number*Description Package Type Operating
Temperature
Si4356-B1A-FM Si4356 EZRadio Standalone Receiver 3x3 QFN-20
Pb-free
–40 to 85 °C
*Note: Add an “R” at the end of the device part number to denote tape and reel option.
Si4356
Rev 1.2 21
9. Package Outline
Figure 8. 20-pin QFN Package
Si4356
22 Rev 1.2
Table 15. Package Diagram Dimensions
Dimension Min Nom Max
A 0.80 0.85 0.90
A1 0.00 0.02 0.05
A3 0.20 REF
b 0.18 0.25 0.30
c 0.25 0.30 0.35
D3.00 BSC.
D2 1.55 1.70 1.85
e0.50 BSC.
E3.00 BSC.
E2 1.55 1.70 1.85
f2.40 BSC.
L 0.30 0.40 0.50
aaa 0.15
bbb 0.10
ccc 0.10
ddd 0.05
eee 0.08
fff 0.10
Note: All dimensions shown are in millimeters (mm) unless otherwise noted.
Si4356
Rev 1.2 23
10. PCB Land Pattern
Figure 9. 20-pin QFN PCB Land Pattern (Top View)
Table 16. PCB Land Pattern Dimensions
Dimension Min Max
C1 3.00
C2 3.00
E 0.50 REF
X1 0.25 0.35
X2 1.65 1.75
Y1 0.85 0.95
Y2 1.65 1.75
Y3 0.37 0.47
f 2.40 REF
c 0.25 0.35
Note: : All dimensions shown are in millimeters (mm) unless otherwise noted.
Si4356
24 Rev 1.2
11. Top Marking
11.1. Si4356 Top Marking
Figure 10. Si4356 Top Marking
11.2. Top Marking Explanation
Mark Method: Laser
Pin 1 Mark Circle = 0.5 mm Diameter
Font Size 0.6 mm Right Justified
Line 1 Marking: Product ID 356A
Line 2 Marking: TTTT = Trace Code Internal tracking number
Line 3 Marking: YWW = Date Code Corresponds to the last digit of the current year (Y) and the
work week (WW) of the assembly date.
Si4356
Rev 1.2 25
DOCUMENT CHANGE LIST
Revision 1.1 to Revision 1.2
January 18, 2016
Added POR Information to Section 5.
Si4356
26 Rev 1.2
CONTACT INFORMATION
Silicon Laboratories Inc.
400 West Cesar Chavez
Austin, TX 78701
Tel: 1+(512) 416-8500
Fax: 1+(512) 416-9669
Toll Free: 1+(877) 444-3032
Please visit the Silicon Labs Technical Support web page:
https://www.silabs.com/support/pages/contacttechnicalsupport.aspx
and register to submit a technical support request.
Patent Notice
Silicon Labs invests in research and development to help our customers differentiate in the market with innovative low-power, small size, ana-
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