71M6515H-IGTR/F - Maxim Integrated

71M6515H

Energy Meter IC

DATA SHEET

JULY 2011

A Maxim Integrated Products Brand

GENERAL DESCRIPTION

The 71M6515H is a high-accuracy analog front-end

(AFE) IC that provides measurements for 3-quadrant

3-phase metering. The combination of a 21-bit

sigma-delta A/D converter with a six-input analog

front-end, a thermally compensated high-precision

reference, and a compute engine results in high

accuracy and wide dynamic range. Our Single

Converter Technology® reduces cross talk and cost.

This IC also provides RTC and battery backup for

time-of-use (TOU) metering.

HOST

PRO-

CESSOR

CURRENT

VOLTAGE

SSI

UART, IRQZ

VOLTAGE

REFERENCE

COMPUTE

ENGINE

RTC

Battery

RAM

TERIDIAN 71M6515H DIO

CONTROL

Figure 1: Meter Block Diagra m

As shown in the block diagram (Figure 1), the host

processor communicates with the 71M6515H

through a UART interface using the programmable

IRQZ interrupt. The 71M6515H calculates and accu-

mulates meter me asurements fo r each ac cumulation

interval. A high-speed synchronous serial port (SSI)

is provided to facilitate high-end metering. Integrated

rectifying functions on the battery-backup circuit

enable minimal external component usage and

minimum back-up current. Also, eight multipurpose

pins are provided for control of peripherals.

FEATURES

High Accuracy

 < 0.1% Wh accuracy over 2000:1 range

 Exceeds IEC 62053/ANSIC 12.20 specifications

 Up to 10ppm/C precision ultra-stable voltage

reference

 Single Converter Technology reduces cross talk

and power consumption

 Six sensor inputs—referenced to V3P3

 Compatible with CTs, resistive shunts and

Rogowski Coil sensors

 Digital temperature compensation

 Sag detection

 Measures Wh, VARh, VAh, Vrms, Irms, V-to-V

phase and load angl e on each phase

 Four-quadrant metering.

 Four low-jitter pulse outputs from sele ctable

measurements

 Four pulse count registers

 Selectable default status for pulse pins

 Same calibration data for 46Hz to 64Hz line

frequency

 Broad CT phase compensation (±7deg)

Battery Backup

 Powers real-time clock d uring power supply

outage

 Compatible with Li-ion, NiCd, or super capacitor

 Battery backup current 2µA typical at 25°C

External Data Interface

 UART control interface, two sele ctable data rates

 8 general-purpose I/O pins with alarm capability

 5 or 10MHz selectable high-spee d synchronous

serial output for DSP interface

 IRQ output signal for alarms and end of

measurement intervals

 Alarms on voltage sag, overvoltage, overcurrent

Low System Cost

 Power consumption 30m W at 3.3V typical

 Real-time clock with temperature compensation

 Built-in power-fault detection

 Single 32kHz crystal time base

 Single-supply operation (3.3V)

 64-lead LQFP package

Single Converter Technology is a registered trademark of

Maxim Integrated Products, Inc.

19-5361; Rev 7/11

∆Σ ADC

CONVERTER

VREF

VB MUX

VREF

RESETZ

VFLT

64 PINS -- 64 TQFP

UART

VX FAULT DETECT

GNDD

V3P3A

V3P3D

VBAT

VOLT

REG

2.5V to logic

V2P5

TMUXOUT

TEST

GNDA

TEMP

March 3, 2008

CK_GEN

VREF

GNDA

GNDD

V3P3A

GNDD

V3P3

XIN

XOUT

OSC

(32KHz)

CKTEST

SYSTEM CLOCKS

RTC

DATA

RAM

BATTERY BACKUP

SSCLK

SSDATA

SFR

SRDY

SSI INTERFACE

MUXSYNC

CALCULATIONS

OUTPUT VALUES:

ALARMS:

Whr (A, B, C)

VARhr (A, B, C)

VAhr (A, B, C)

Vrms (A, B, C)

Irms (A, B, C)

Iphase (A, B, C)

Frequency (Selected Phase)

Temperature

Voltage Sag (A, B, C)

Zero Cross (Selected Phase)

Over-Voltage (All)

Over-Current (All)

D0-D7 State Change

CONTROL

PULSEW PULSER

VBIAS

(1.5V)

VBIAS

(1.5V)

RESERVED

IRQZ

I/O CONTROL

Change of State

(D0...D7)

GNDD

PULSE4

PULSE3

PULSE_INIT

BAUDRATE

MISC

Figure 2: IC Functional Block Diagram

ELECTRICAL SPECIFICAT IONS

71M6515H

Energy Meter IC

DATA SHEET

JULY 2011

A Maxi m In tegrated Produ cts Brand

A BSOLU TE MAXIMUM RA TING S

Supplies and G round Pins:

V3P3D, V3P3A

−0.5V to 4.6V

|V3P3D – V3P3A|

0V to 0. 5V

VBAT

-0.5V to 4.6V

GNDD

-0.5V to +0.5V

Analog Output Pins:

VREF

-1mA to 1mA,

-0.5V to V3P3A+0. 5V

V2P5

-1mA to 1mA,

-0.5 to 3.0V

Analog Input Pins:

IA, VA, I B, VB, IC, VC

-0.5V to V3P3A+1. 0V

VFLT, VX

-0.5V to V3P3A+0. 5V

XIN, XOUT

-0.5V to 3.0V

Digital Input Pins:

-0.5V to 3.6V

D0…D7

-0.5V to 6V

Al l other pi ns

-0.5V to V3P3D+0.5V

Operating junction temperature (peak, 100 ms)

140 °C

Operating junction temperature (continuous)

125 °C

Storage temperatur e

−

45 °C to 165 °C

Solder temperature – 10 second duration

250 °C

ESD Stress

Pins IA, VA, IB, VB, IC, VC, RX, TX

6kV

All other pi ns

2kV

Stresses beyond Absolute Maximum Ratings may cause permanent damage to the device. These are stress ratings only and functional

operation at these or any other conditions beyond those indicated under “recommended operating conditions” is not implied. Exposure to

absolute-maximum-rated cond iti ons for e xt end ed per i ods m ay affect d evice reli ab ility. Al l vol tag es are with r espec t to GND A .

RECOM M E NDE D OPERATING CONDIT IO NS

PARAMETER

CONDITION

MIN

TYP

MAX

UNIT

3.3V Suppl y Voltage ( V3P3A, V3P3D)+

Normal Ope ration

3.0

3.3

3.6

Battery Backup

3.8

VBAT

No Battery

Externall y Connect to V3P3D

Battery Backup

2.0

3.8

Operating Temperature

-40

ºC

+ V3P3A and V3P3D should be shorted together on the circuit board. GNDD and GNDA should also be shorted on the circuit board.

71M6515H

Energy Meter IC

DATA SHEET

JULY 2011

A Maxi m In tegrated Produ cts Brand

LOGIC LEVELS

PARAMETER

CONDITION

MIN

TYP

MAX

UNIT

Digital high-level i nput volta ge, VIH

V3P3D

Digital low-level input volt age, V

−0.3

0.8

Digital high-level output voltage VOH ILOAD = 1mA

V3P3D

–0.4

V3P3D V

ILOAD = 15mA

V3P3D-

0.6

Digital low-level output vol tage VOL

LOAD

= 1mA

0.4

ILOAD = 15mA

0.81

Input pull-up current, I

RESETZ

E_RXTX, E_ISYNC/ BRKRQ

E_RST

Other digital inputs

VIN=0V

-1

100

µA

Input pull down current, I

TEST

Other digital inputs

VIN=V3P3D

-1

100

µA

1 Guaranteed by design; not product ion tested.

SUPPLY CURRENT

PARAMETER

CONDITION

MIN

TYP

MAX

UNIT

V3P3A + V3P3D

Normal Ope ration,

V3P3A=V3P3D=3.3V

VBAT=3.6V

8.8

11.5

V3P3A current

3.7

4.7

V3P3D current

5.1

6.8

VBAT current

-300

300

VBAT current,

VBAT=3.6V

Battery backup, ≤25°C

V3P3A=V3P3D=0V

fOSC = 32kHz 85°C

µA

4 121 µA

1 Guaranteed by design; not product ion tested.

VREF

71M6515H

Energy Meter IC

DATA SHEET

JULY 2011

A Maxi m In tegrated Produ cts Brand

PARAMETER

CONDITION

MIN

TYP

MAX

UNIT

VREF output voltage, VNO M(25)

Ta = 25ºC

1.193

1.195

1.197

VREF output impe dance

LOAD

= 10µA , -10µA

2.5

kΩ

VNOM definition 2

VNOM( T) = VRE F (2 2 ) + ( T-22)TC1 + (T-22)2TC2

VREF(T) deviation from VNOM(T)

)40|,22max(| 10

)()( 6

−

TVNOM TVNOMTVREF

Ta = -40ºC to +85ºC, fo r

71M6515H-IGT/F -101 +101 PPM/ºC

Ta = -40ºC to +85ºC, for

71M6515H-IGTW/F -401 +401 PPM/ºC

VREF aging ±25 PPM/year

1 Guaranteed by design; not production teste d.

2 This r el ationshi p describes t he nomi nal behavior of VREF at different tem peratur es . The values of TC1 and TC2 are devi ce

specific in gene ral and are progra mmed into the device at manufac tu ring.

71M6515H

Energy Meter IC

DATA SHEET

JULY 2011

A Maxi m In tegrated Produ cts Brand

2.5V VOLTAGE REGULATOR

PARAMETER

CONDITION

MIN

TYP

MAX

UNIT

Voltage Overhead V3P3D-V2P5

Reduc e V3P3 until V2P5

drops 200m V

440 mV

PSRR ΔV2P5/ΔV3P3D

RESETZ=1, I

LOAD

-3

mV/V

RTC

PARAMETER

CONDITION

MIN

TYP

MAX

UNIT

Range f or date

2000

2255

year

RESETZ

PARAMETER

CONDITION

MIN

TYP

MAX

UNIT

Reset pulse widt h

µs

Reset pulse fall t ime

µs

1 Guaranteed by design; not product ion tested.

CRYSTAL OSCILLATOR

PARAMETER

CONDITION

MIN

TYP

MAX

UNIT

Maximum Output Power to Crystal4

µW

Xin to Xout Capacitance

Capacitance to DGND

Xin

Xout

Watchdog RTC_OK threshold

kHz

TEMPERATURE SENSOR

PARAMETER CONDITION MIN TYP MAX UNIT

Nomi na l Sens itivity (S n)4 TA=25ºC, TA=85ºC

No minal relationship:

N(T)= Sn*T+Nn

-900 LSB/ºC

Nominal Offset (Nn) 4 40000

0 LSB

Temperat ure Error , relative to 25ºC error

SNTN

TERR ))25()((

)25( −

−−=

TA = -40ºC t o +85 ºC -31 +31 ºC

1 Guaranteed by design; not production teste d.

71M6515H

Energy Meter IC

DATA SHEET

JULY 2011

A Maxi m In tegrated Produ cts Brand

PULS E GENE R ATOR TIMING SPECIFICATIONS

PARAMETER CONDITION MIN TYP MAX UNIT

PULSEW, PULSER maximum rate

APULSE=231-1,

WRATE=2

-1

7.56 kHz

PULSE3, PULSE 4 max i mu m rate

PULSE3=231-1,

WRATE=2

-1

0.15 kHz

Pulse count frequency all pulse outputs 0.15 kHz

THERMAL CHARACTERISTICS

PARAMETER CONDITION VALUE UNIT

The r mal resistance, j unct ion to am bien t (RθJA ) Air velocity 0 m / s. Par t sol dered to PC B . 63.7 °C/W

UART HOST INTERFACE

PARAMETER

CONDITION

MIN

TYP

MAX

UNIT

Baud Rat e

19.2

38.4

kBaud

Character set

binary

Data Form at

8N1

Byte-to-byte delay (6515H times out after

maximum delay)

Host sending data to

6515H

10 20 ms

Byte-to-byte delay

6515H sending dat a to

host 0 0.1 ms

Response time to read command

6515H has data ready

0.5

Response time to read command when

71M6515H is post-pr ocessing data

Data not ready

CE_ONLY = 1

CE_ONLY = 0 and

VAH_SELECT = 0

CE_ONLY = 0 and

VAH_SELECT = 1

350

ADC CONVERTE R, V3P3 REFERENCE D

PARAMETER

CONDITION

MIN

TYP

MAX

UNIT

Usable Input Range (Vin-V3P3A) -250 250

peak

Voltage to Current cross ta lk:

)cos(

*10

VcrosstalkVin

Vin

Vcrosstalk ∠−∠

Vin = 200m V peak, 65Hz,

on VA, VB, or VC

Vcrosstalk = largest

measure ment on IA, IB, or

-101 +101 µV/V

THD (First 10 harmonics)

250mV-pk

20mV-pk

Vin=65Hz,

64kpts FFT, Blackman-

Harris window

-75

-90

Input Impedance

Vin=65Hz

kΩ

71M6515H

Energy Meter IC

DATA SHEET

JULY 2011

A Maxi m In tegrated Produ cts Brand

Temperat ure Co efficien t of Input

Impedance

Vin=65Hz 1.7 Ω/°C

LSB size

355

nV/LSB

Dig ital Full Scal e

+884736

LSB

AD C Gai n Er ror v s.

%Power Supply Variatio n

3.3/33100 /357106

APV VnVNout INPK

∆

Vin=200mV pk, 65Hz

V3P3A=3.0V , 3.6V 50 PPM/

Inp ut Offs et (V in-V3P3A)

-10

+10

1 Guaranteed by design; not product ion tested.

RECOMMENDED EXTERNAL COMPONENTS

NAME

FROM

FUNCTION

VALUE

UNIT

V3P3A

AGND

Bypass capacitor for 3 .3V supp ly

≥0.1±20%

µF

V3P3D

DGND

Bypass capacitor for 3 .3V supp ly

≥0.1±20%

µF

XTAL XIN XOUT

32.768kHz cr ystal – e lectrically similar to

ECS .327-12.5-17X or Vishay XT26T, load

capacitance 12.5pF

32.768 kHz

CXS

XIN

AGND

Load capaci tor for crystal (depends on crystal

specs and board parasitics).

10%

CXL

XOUT

AGND

10%

C2P5

V2P5

DGND

Bypass capacitor for V2P5

≥0.1±20%

µF

FOOTNOTES:

1 This spec is guaranteed, has been verified in production samples, but is not measured in production.

2 This sp ec is gu aranteed, h as b een verified in produc t i on s am pl es , but is m eas ured in pr od uc tion onl y at DC.

3 This sp ec is m eas ured in pr od uc ti on at th e li mits of t h e sp ec ifi ed opera ting temperature.

4 This s pec d efin es a n omin al r el ations hi p r ather than a meas ured p ar amet er . C orr ec t cir cui t oper ati on is ver ifi ed with oth er s pecs that use

this n omi n al r el ati onshi p as a ref erenc e

71M6515H

Energy Meter IC

DATA SHEET

JULY 2011

A Maxi m In tegrated Produ cts Brand

PIN CONFIGURATION AND PIN FUNCTION

TERIDIAN

71M6515H-IGT

71M6515H-IGTW

GNDD

RESERVED

TMUXOUT

/RTMTX

SSCLK

CKTEST

V3P3D

SSDATA

SFR

RESERVED

PULSE3

PULSE4

GNDD

RESETZ

V2P5

VBAT

IRQZ

UARTCSZ

PULSER

PULSEW

BAUD_RATE

RESERVED

MUX_SYNC

SRDY

GNDD

RESERVED

VREF

XIN

GNDA

V3P3A

XOUT

GNDA

VFLT

PULSE_INIT

RESERVED

GNDD

Pins m ar ked RESERVED should be left unconnected during normal use.

71M6515H

Energy Meter IC

DATA SHEET

JULY 2011

A Maxi m In tegrated Produ cts Brand

Analog Pin Description

Name

No.

Type Circuit Description

IA,

IB,

I 6

Line Current Sens e Inputs: Voltage inputs to the inter nal A/D conv erter. Typically,

they are connected to the o utput of a curr ent transformer. The input is ref erenced

to V3P3A. Unused pins must be tied to V3P3A.

VA,

VB,

I 6

Line Vol t age Sense Inputs: Volt age input s to the internal A/D converter. Typically,

they are connected to the o utput of a resistor di vi der . The i nput is ref erenced to

V3P3A. Unused pins m ust be tied to V3P3A.

VFLT

Power Fault Input. This pin must be ti ed to V3P3A.

Aux iliary input (not used). Thi s pin should be tie d to VREF.

VREF

I/O

Voltag e Refer ence for t he A DC .

XIN,

XOUT 61

63 I 8

Crystal I nputs: A 32768Hz crystal shoul d be c onnected acr oss these pins.

Typically, a 15pF capaci tor is al s o connected from each pin to GNDA. See the

datashee t of the crystal manufac turer for details.

Pi n ty p es: P = Po wer, O = Output , I = I nput, I/O = I npu t/Outp ut

The circuit num ber denot es the equivalent circuit, as specified under “I/O Equivalent Circui t s”.

Digital Pin Description

Unless ot herwise indicated, all inputs and outputs ar e standard CMOS. Inputs do NOT have inter nal pull-up s or pull-downs.

Name

No. Type Circuit Description

CKTEST 6 I/O 4

Clock PLL output. Can be enabled and dis abl ed by CKOUT_DSB (see

St a tus Ma sk).

I/O 3, 4

Input/output pins 0 through 7. These pins must be terminated to

V3P3D or ground if configured as i nput pins.

D0 through D7 are high impedance after reset or power-up and are

configured as outputs and dri ven low 140m s after RESETZ goes

high.

PULSE4

The fourth pul s e generator output

PULSE3

The third pulse generator output

PULSE_INIT 40 I 3

The pulse output initial power-up volt age (0: 0V, 1: 3.3V), default is 1.

This pin m ust be term i nated to V3P3D or ground.

BAUD_RATE 16 I 3

The UART baud rate (1: 38.4kbd, 0: 19.2kbd). This pin must be

termi nated to V3P3D or ground.

IRQZ 41 O 4

Interrupt output , low active. A falling edge indicates the end of a

m easurem ent frame, as well as alarms. Rises when status word is

read.

MUXSYNC 25 O 4

Int ernal s ignal. MUXSYNC falls at t he beginning of each conversion

cycle (multiplexer frame).

RESETZ 47 I 1

Chip reset: Input pin with internal pull-up resistor, u sed t o r eset th e chi p

int o a know n state. For nor mal operat io n, t hi s pi n is set to 1. To reset

the chip, t his pin i s driven to 0 f or 5 m icr oseconds. N o ex ter nal r eset

circu itry is necessary for power-up reset.

71M6515H

Energy Meter IC

DATA SHEET

JULY 2011

A Maxi m In tegrated Produ cts Brand

Name

No.

Type Circuit Description

UARTCSZ 34 I 3

Enables t he UART when 0. The UART is di sabled when this pin is set

to 1. A posi tive pulse on t his pin wi ll reset t he U AR T. Thi s pin m ust be

termi nat ed t o groun d.

SRDY

SFR

SSCLK

SSDATA

High-Spe ed Synchronous Inte rface (SSI).

The SRDY i nput should be tied to ground.

SSI frame puls e output, o ne S SC LK wide.

SSI clock output (5MHz or 10MHz selectable).

SSI data output, changes on the rising edge of SSCLK.

RX 44 I 3

UA RT serial Int erf ace r eceiv er i nput. The vol tage at this p in m ust not

exceed 3.6V. This pin must be terminated to V3P3D or ground.

UA RT serial Int erf ace t rans mitter o utput .

TMUXOUT

Digital ou tput test mult ipl exer . Co ntr olled by TMUX[2:0].

PULSER

PULSEW

Selectable pulse out put (default: VARh pulse).

Selec table pul se output (default: Wh pulse) .

Power/Ground Pin Descripti on

Name P in No. Type Description

GNDA 49,60 P Analog ground: This pin should be connected dir ectly to the gr ound plane.

GNDD

1,27,

48,62

P Digital ground: These pi ns must be connect ed dir ectly to the ground plane.

V3P3A 50 P Analog power : A 3.3V anal og power supply should be c onnected to this pi n.

V3P3D 7 P Digital power supply: A 3.3V digital po wer supply s hould be c onnected to t his pin.

VBAT 45 P

Battery backup power supply. A battery or super -capacitor is to be connected bet ween

VBAT and GNDD. If no battery is used, connect VBAT to V3P3D.

V2P5 46 O Output of the 2.5V regulator. A 0.1µ F capacitor should be connected from this pin to GND.

Pi n ty p es: P = Po wer, O = Output , I = I nput, I/O = I npu t/Outp ut

The circuit num ber denotes the equivalent circuit, as specified under “I/O Equivalent Circuits”.

Reserved Pins

Pin s labeled RESERVED are not to be connected.

Name

Pin No.

Description

RESERVED

2,10,11,12,

13,17,18,19,

20,26,28,29,

30,31,32,43,

DO NOT CONNE CT T HESE PINS !

71M6515H

Energy Meter IC

DATA SHEET

JULY 2011

A Maxi m In tegrated Produ cts Brand

I/O E q uiv a le nt Ci rcu its

Digital Input Equivalent Circuit

Type 1:

Standard Digital Input or

pin configured as DIO Input

with Internal Pull-Up

GNDD

110K

V3P3D

CMOS

Input

V3P3D

Digital

Input

Digital Input

Type 2:

Pin configured as DIO Input

with Internal P ull-Down

GNDD

110K

GNDD

CMOS

Input

V3P3D

Digital

Input

Digital Input Type 3:

Standard Digital Input or

pin configured as DIO Input

GNDD

CMOS

Input

V3P3D

Digital

Input

CMOS

Output

GNDD

V3P3D

GNDD

V3P3D

Digital Output Equivalent Circuit

Type 4:

Standard Digital Output or

pin configured as DI O Out put

Digital

Output

MUX

GNDA

V3P3A

Analog Input Equivalent Circuit

Typ e 6:

ADC Input

Analog

Input

Comparator Input Equivalent

Circuit Type 7:

Comparator Input

GNDA

V3P3A

Comparator

Input

VREF Equivalent Circuit

Type 9:

VREF

from

internal

reference

GNDA

V3P3A

VREF

V2P5 Equi valent Circuit

Type 10:

V2P5

from

internal

reference

GNDD

V3P3D

V2P5

VBAT Equivalent Circuit

Type 12:

VBAT Power

GNDD

Power

Down

Circuits

VBAT

Oscillator Equivalent Circuit

Type 8:

Oscillator I/O

Oscillator

GNDD

V3P3D

Oscillator

71M6515H

Energy Meter IC

DATA SHEET

JULY 2011

A Maxi m In tegrated Produ cts Brand

TYPI CAL PERFORMANCE CHARACT ERISTICS

Figure 3: Wh Accuracy, 0.3A - 200A/240V

Figure 4: VARh Accuracy for 0.3A to 200A/240V Perform ance

200

100

0.3

-0.2

-0.15

-0.1

-0.05

0.05

0.1

0.15

0.2

0.1 110 100 1000

%Error

0 Deg

60 Deg

-60 Deg

180 Deg

200

100

0.3

-0.2

-0.15

-0.1

-0.05

0.05

0.1

0.15

0.2

0.1 110 100 1000

% Error

90 De g

150 De g

270 De g

71M6515H

Energy Meter IC

DATA SHEET

JULY 2011

A Maxi m In tegrated Produ cts Brand

Meas ured at cur r ent distor t ion am plit u d e of 40% and vol tage dist or t i on am pl i tu d e of 10% .

Figure 5: Mete r Accuracy over Harmonics at 240V, 30A

Figure 6: Typical VAh Accuracy for VAh Using Vector Method

-8

-7

-6

-5

-4

-3

-2

-1

1357911 13 15 17 19 21 23 25

Harmonic

Error [%]

50Hz Harmonic Data 60Hz Harmonic Data

-0.2

-0.15

-0.1

-0.05

0.05

0.1

0.15

0.2

0.1 110 100 1000

Error [%]

Current [A]

Performance for A pparent Energy (VA h)

71M6515H

Energy Meter IC

DATA SHEET

JULY 2011

A Maxi m In tegrated Produ cts Brand

FUNCTI ONAL DESCRIP TION

THEOR Y OF OPER ATION

The 71M 6515H integrates the primary functional blocks re qui re d to implement a solid-state ele c tr i c ity me ter fron t end. Inclu d ed

on-chip are an anal og front end ( AFE) , a di gital computation engi ne (CE), a voltage ref erence, a real tim e clock, and I /O pi ns.

Various current sensor technologies are supported including Current Transformers (CT), Resistive Shunts, and Rogowski

(di/dt) Coils.

In a typical application, the 71M6515H sequentially digitizes the voltage inputs on pins IA, VA, IB, VB, IC, VC and performs

calculations to measure active energy (Wh), reactive energy (VARh), and apparent energy (VAh). In addition to these

measurement functions, the real time clock function allows the device to record time of use (TOU) metering information for

multi-rate applications.

The 71M6515H contains a t em perat ure-trimmed ultra-prec i se v o l t a g e r eference, and the on-chip digital temperature compen-

sation mechanism includes a temperature sensor and associated controls for correction of unwanted temperature effects on

measurement. RTC accuracy can be greatly improved by supplying correction coefficients derived from crystal

characterization. The combination of both features enables designers to produce electricity meters with exceptional accuracy

over the indus t rial te mperature range .

Meter Equ at io ns

The 71M6515H implements the equations in Table 1. Regist er EQU specifies the equation to be used. In one sample time,

each of the six inputs is converted and the selected equation updated. In a typical application, IA, IB, IC are connected to

current transformers that sense the current on each phase of the line voltage. VA, VB, and VC are typically connected to

voltage sensors (resistor dividers) with respect to NEUTRAL. NEUTRAL is to be connected to V3P3A, the analog supply

voltage. NEUTRAL is t he zero reference for all analog measurements.

EQU Watt & VAR Formula Application Channels used from MUX

sequence

Mux State:

0 1 2 3 4 5

0 VA IA 1 element , 2W 1ø IA VA - - - -

1* VA(IA-IB)/2 1 element, 3W 1ø IA VA IB - - -

2 VA IA + VB IB 2 element, 3W 3 øDelta IA VA IB VB - -

3* VA (IA - IB)/2 + VC IC 2 element , 4W 3ø Delta IA VA IB - IC VC

4* VA(IA-IB)/2 + VB(IC-IB)/2) 2 element, 4W 3ø Wye IA VA IB VB IC -

5 VA IA + VB IB + VC IC 3 element, 4W 3ø Wye IA VA IB VB IC VC

Note: Equations 1*, 3*, 4* avai lable onl y when IMAGE = 00 (CT mode ).

Table 1: Meter Equations

Table 2 shows how the elements of the m eter are mapped for the six possible equations.

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EQU Watt & VAR Formul a

(WSUM/VARSUM)

Element Output Mapping

W0SUM/

VAR0SUM W1SUM/

VAR1SUM W2SUM/

VAR2SUM I0SQ

SUM I1SQ

SUM I2SQ

SUM

0 VA IA ( 1 element, 2W 1φ) VA*IA - - IA - -

1 VA*(IA-IB)/2

(1 element, 3W 1 φ) VA*(IA-IB)/2 VA*IB - IA-IB IB -

2 VA* IA + VB*I B

(2 element, 3W 3 φ Delta) VA*IA VB*IB - IA IB -

VA*(IA-IB )/2 + VC*IC

(2 element, 4W 3 φ Delta) VA*(IA-IB)/2 - VC*IC IA-IB IB IC

VA*(IA-IB)/2 + VB*(IC-IB)/2

(2 element, 4W 3 φ Wye) VA*(IA-IB)/2 VB*(IC-IB)/2 IA-IB IC-IB IC

VA*I A + VB*IB + VC* IC

(3 element, 4W 3 φ Wye) VA*IA VB*IB VC*IC IA IB IC

Table 2: Me ter Eleme nt Output Mapping

ANALOG FRONT END

A/D Converter (ADC)

A si ngle delta-sigma A/D converter (ADC) digitizes the inputs to the device. The resolution of the ADC is 21 bits. The ADC

operates at 5MHz oversampling rate and places the digital results in CE memory. Each analog input is sampled at 2520Hz.

O n ce ea c h ac c um ul at i on i nt er v al , i t ref r es h es t h e t em p er a tu re v a l u e t h at is pl a c ed i n the TEMP_RAW register. The analog re-

ference f or all input s is V3P3A, i.e. the ADC processes voltages bet ween the input pins and V 3P3A.

Voltage Refer ence

The device includes an on-chip precision bandgap voltage reference that incorporates auto-zero techniques as well as

production trims to m inimize error s caused by component mism atch and drift. The result is a voltage output wi th a predictable

temperatur e coeffici ent.

The CE compensates for temperature characteristics of the voltage reference by modifying the gain applied to the V and I

channels based on the coefficients PPMC and PPMC2. See the sectio n “TEMPERATURE COMPENSATIO N” for details.

DI GITAL COMPUTATION

The six ADC outputs are processed and accumulated digitally. The default product summation is based on 42*60 (if the

SUM_CYCLES register is set to 60) samples per accumulation interval. At the end of each accumulation interval, a ready

interr upt (IRQZ) is signaled (if enabled with the READY bit in STMASK), indi cating that fresh data is available to the host. For

instance, if SUM_CYCLES =30, the IRQ Z rate will be 2Hz (500ms).

A dedicated 32-bit Computation Engine (CE) performs the precision computations necessary to accurately measure energy.

Inter nal CE calcul ations include frequency-insensitive offset cancellation on all six channels and a frequency insensitive 90°

phase shifter for VAR calculations. The CE also includes LPF smoothing filters after each product and squaring circuit to

attenuate ripple and eliminate beat frequencies between the power line fundamental and the accumulation time. The CE

directly calculates Watts, VARs, V2, and I2 and ac cumulat es them for one interval.

At the end of each CE computation cycle, the accumulated data are post-processed to calculate RMS amplitudes, phase

angles, and VAh. W hen post-process ing is c ompl ete, the IRQZ signal is activated.

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The minimum combi ned cycle time for CE and post-processor is 400ms, which makes the m aximum frequency for the IRQZ

signal 2.5Hz.

If the 71M6515H is i nt erfacing to an ext ernal DSP (typically, but not necessarily through the SSI interface), the host may turn

off post-processing by setting the CE_ONLY bit in the CONFIG word. This will permit setting SUM_CYCLES below its

r ecom mended l ow er li mit of 24. SUM_CYCLES m ay then be reduced t o 1, creating an accumulation interval of only 4 2 sampl es.

The output s available in CE only mode are limit ed to tem perature, frequency, voltage phases, input signal zer o cr ossings, plus

W SUM and VARSUM f or each phase and VSQSUM, ISQSUM, and ISQ FRACT for each phase.

Pulse Generators

The chip contains four pulse generators connected to the pins PULSEW, PULSER, PULSE3, and PULSE4 that create low

jitter pulses from 32-bit data. The peak time jitter for PULSEW and PULSER is the 397µs MUX frame period, and is

independent of the rate of the generator or the length of time the generator is monitored. Thus, if the pulse generator is

monitored for 1 second, the peak jitter is 400PPM. After 10 seconds , the peak jitter is 40PPM .

PULSE3 and PULSE4 are updated at a slower rate and have four t imes higher jitter, i.e. 160PPM after 10 seconds.

Th e av era ge j itt er i s a lwa ys zer o. I f it is att em pt ed t o dr iv e ei th er p ul se g ener at or fast er t han it s m axim um r ate, it will sim ply

output at it s maximum rat e without exhibi ting any roll -o ver character isti cs .

Pulse generator inputs may be from three sources:

• Internal ( dir ectly from the CE ) , P U LSEW an d PU LSE R on ly

• Ext ernal (controlled by the host writing to registers APULSEW, APULSER, APULS E3, APULSE4)

• Post-p rocessed valu es

The source is selected individually for each pulse output with the PULSEW_SRC, PULSER_SRC, PULSE3_SRC, and PULSE4_SRC

registers. Figure 7 shows internal pulse generation for the PULSEW output selected by writing the value 35 into the

PULSEW_SRC register.

PULSEW_SRC

35: WSUM

0: WSUM

1: WASUM

2: WBSUM

3: WCSUM

4: VARSUM

34: VAR2SUM_E

36: APULSEW

HOST

PULSEW

OUTPUT

POST PROC ESSOR

34: VAR2SUM_E

Figure 7: Internal Pulse Generation Selected in the PULSEW_SRC Register

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Internal data is pulsed out during the accumulation interval immediately following its accumulation interval. Post-processed

values are pulsed out one accumulat ion i nter val a f ter t hat.

The pulse generator output rate depends on its input value, WRATE, PULSE_SLOW, and PULSE_FAST. Additionally, its

maximum pulse wi dth (negative going pulse) is controlled by PULSEWIDTH. High frequency pulses will have 50% duty cycle

until thei r rate slows enough that their pulse width is limited by PULSEWIDTH.

In inter nal and post-processed modes, t he pulse r ate, expressed as K h (Wh p er pulse) is given by t he formula:

PulseWh

XWRATECYCLESSUMIn IMAXVMAX

Kh /5757.1

_8_ ⋅⋅⋅

where

VMAX is the m eter voltage cor r esponding to an input voltage of 176mV (rms) at the VA, VB, and VC input pins ,

IMAX is the meter current corresponding to an input volt age of 176mV (r ms) at t he IA, IB, and I C input pin s,

In_8 is t he additional A DC gain ( 1 or 8) , as co nt rolled by the IA_X, IB_X and IC_X bits in the CONFIG register.

X i s t he pulse speed fact or d etermin ed f rom Table 3.

PULSE_SLOW

PULSE_FAST

1.5*22=6

1.5*26=96

1.5*2-4=0.09375

1 (default)

1.5

Table 3: Pul se Speed Factor X

In ext ernal pulse mode, the pulse rate i s given by the f ormula:

Rat e(Hz) = WRATE * X * input * 35.82*10-12,

where input i s t he val ue in r egisters APULSER, APULSEW. APULSE3 or APULSE4,

X i s t he pulse speed fact or d etermin ed f rom Table 3.

External pulse gen eration can be seen as providing the raw voltage and current readings equi valent to Vin*Iin / L S B di r ec t l y to

the pulse gener at or .

The maximum pulse rate is 7.56kHz for PULSEW and PULSER, and 150Hz for PULSE3 and PULSE4.

In ext ernal pulse m ode, the puls e generator s load their data at the begi nni ng of each CE accumulation int erval, preserving any

partially implemented pulses from the previous interval. The source of data is controlled by the entries in the PULSE_SRCS

The procedure for accur ate external pulse generation controlled by the host is:

1) Respond to a READY int errupt by r eading the accumulated val ues.

2) Process t he accumulated values.

3) Write the processed value(s) to APULSER, APULSEW, APULSE3, or APULSE4. The host must write to APULSER,

APULSEW, APULSE3, and APULSE4 before the next READY interrupt for the pulse generati on to be beginni ng in t he

following accumu lation in terval.

Figure 8 illust rates puls e generator timing.

Regardless of the source, the pulse generators should receive new data during each accumulation interval. If this does not

occur and if the corresponding bit in the STMASK regis ter is s et, an APULSE_ERR inter rupt wi ll be i ssued.

The PULSEW, PULSER, PULSE3 and PULSE4 pins are suitable for dri ving LEDs through a current limiti n g resi st or. The LED

should be connected so it is on when the pulse pin is l ow.

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The pin PULSE_INIT determines the logic level applied to the pulse pins on power-up, i.e. with PULSE_INIT low, the pulse

pin s wi l l be initializ ed to low ( d efau lt = 1 ).

The pulse width PW is contr ol led wi th t he PULSEWIDTH register for the PULSER and PULSEW output pins per the following

formula:

6.2520 12 +⋅

=PULSEWIDTH

The PULSE3 and PULSE4 output pins will always generat e pulses with 50% duty cycle.

Figure 8: Pulse Generator Timing

Accumulati on 1 Accumulati on 2 Ac c umulat i on 3

Post 1

Post 0 Post 2

READY

APULSE write

CE Operations

Post P rocessi ng

Pulse -1 Pulse 0 Pulse 1Pulse Generat or

READY READY

XFER XFER XFER

Accumulati on Interval

Post- Processed Da t a

APULSE write APULSE write

Accumulati on 1 Accumulati on 2 Ac c umulat i on 3

Post 1

Post 0 Post 2

READY

CE Operations

Post P rocessi ng

Pulse 0 Pulse 1 Pulse 2Pulse Generator

READY READY

XFER XFER XFER

Accumulati on Interval

Internal D ata (Directly by CE)

Accumulati on 1 Accumulati on 2 Ac c umulat i on 3

Post 1

Post 0 Post 2

Host 0

READY

CE Operations

Post P rocessi ng

Host Proc essing

Pulse -2 Pulse -1 Pulse 0Pulse Generator

Host 1

READY Hos t 2

READY

XFER XFER XFER

Accumulati on Interval

External (Host data is transferred to the pulse generator in the first accumulation interval after the

next READY)

APULSE write APULSE write APULSE write

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In t ernal Resources

Oscillator

The oscill ator drives a standard 32.768kHz watch crystal. Crystals of this type are accurate and do not require a high current

oscillator circuit. The 71M6515H oscillator has been designed specifi cally to handle watch crystals and is compatible wit h their

high impedance and limited power handling capability. The oscillator power dissipation is very low to maximize the lifetime of

any battery backup device attached to VBAT. Using PLL techniques, all internal clocks, such as the 4.915MHz clock for the

ADC and the post-processor , ar e deriv ed f rom t he watch cr ystal f requency.

Real-Ti me Clo ck (RTC)

The RTC is driven di r ectly by the crystal oscill ator. In the absence of V3P3, it is power ed by the battery-backed up supply. The

RTC consists of a count er chain and output r egisters. The counter chain consists of registers for seconds, minutes, hours, day

of week, day of month, month, and year. The nominal quadratic temperature coefficient of the crystal is automatically

c ompensated in th e RT C. The RTC is capable of processing leap years.

I/O Peripherals

The 71M6515H includes several I/O peripheral functions that improve the functionality of the device and reduce the

compone nt count for mos t meter applica tions. The I/O periphe rals include a UART and digi tal I/O.

Digital I/O

The device includes ei ght pins of general purpose digital I/O (D0…D7). Each pin can be configured independentl y as an input

or output with the D_DIR bits. Inputs are standard CMOS with no pull-ups or pull-downs. Outputs are standard CMOS. The

DIO pins are controlled by t he D_CONFIG register.

Immediately af ter reset or power-up, D0 through D7 are in tr i-stat e m ode. 140 ms after reset, D0 through D7 are con-

fi gured as out puts and driven low.

UART Host I nte rf a c e

The UART is a dedicat ed 2-wi r e serial interface, whi ch can comm unicate wit h the host processor. The oper ati on of each pi n is

as follows:

RX: Is the pin accepting the serial input dat a. It in put s da ta to i nter na l r egi ster s. T he b yt es ar e input LSB fi rst. Th e vol t age

applied to this pin must be restricted t o 0 to 3.6V.

TX: Is the pin used for serial output data. It outputs the contents of a block of i nternal regi sters. The bytes are output LSB

first.

BAUD_RATE: The baud rat e can be selec t ed wi t h the BAUD_RATE pin (38.4bps when high, 19.2bps when low).

UARTCSZ: This pin enables the UART wh en low. The UART can be reset by taking UARTCSZ briefly to the high st ate and

then low again.

The 71M6515H has several on-chip registers, which can be read and written. All transfers start with a stream of 8-bit bytes

(LSB first) from the host on the RX input, followed by a (possibly null) stream of 8-bi t bytes (LSB first) to the host on the TX

output (see Figure 9 and Figure 10). The UART is configured as 8N1 (8 bits, no parity, 1 st op bit).

If the READY bit in STMASK is enabled, the IRQZ pin can be used to signal data availability to the host. If data read cycles

exceedi ng 1 second are used, care should be taken to prevent data overflow.

UART Writ e Regist er Ope r atio n

The registers are written by sending a byte, consisting of a starting register address in the seven MSBs and ‘0’ in the LSB

indicating this is a write operation. It is followed by a one byte length of bytes to write. If more bytes arrive than fit in the

addressed register, subsequent registers will be written. The bytes are processed in “big-endian” order (i.e. most significant

byte fi rst) . S ee Figure 9 (read bits and bytes f rom l eft to rig ht).

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Figure 9: UART Write Oper ation

UART Read Regi ste r Operati o n

The registers are r ead by sendi ng a byte, consisting of a s t art register addr ess in the seven MSBs and ‘1’ in the LS B i ndic ati ng

this is a read operati on. It i s followed by a one byte length of bytes to read. If m ore bytes are asked for than the size of the

addressed r egister, subsequent registers will be read. The bytes are in “big-end i an” or d er ( i . e. mo st significant byte first). See

Figure 10.

Figure 10: UART Read Ope ration

Note: In both register read and write operations, the register address can be 0 through 127 (0x7F) . The regi ster address byte

is obtained by l eft-shifting the register address by one bit and setti ng bit 0 to 1 for read or setting bit 0 to 0 for wr ite.

Synchronous Ser ial Interface (SSI)

A high speed, handshake, serial interface is available to send a contiguous block of CE data to an external data logger or

DSP. The bl ock of data, configurable as to location and size, is sent at the beginning of each ADC m ultiplex cycle. The SSI

int erface is enabled by the SSI_EN bit and con si st s of the outputs SSCLK, SSDATA, and SFR and of t he SRDY i nput pin. The

inter face is compatib le with 16-bit and 32-bit processors. The operation of each pin is as follows:

SSCLK: This pin provides the serial clock. The clock can be 5MHz or 10MHz, as specified by the SSI_10M bit. The

SSI_CKGATE bit controls whether SSCLK runs continuously or is gated off when no SSI activity is occurring. If SSCLK is

gated, it will begin three cycles befor e SFR r ises and will persist t hr ee cycles after the last data bit is output.

SSDATA: Thi s pin provides the ser ial output data. SSDATA changes on the rising edge of SSCLK and outputs the content s

of a block of CE words starting wit h addr ess SSI_STRT and endi ng wi th SSI_END. The words are out put MSB first. SSDATA

is stable wi th the falling edge of SS CLK .

SFR: This pin provides the framing pulse. Although CE wor ds are always 32 bits, the SSI interface will fram e t he enti r e data

block as a single field, as mul tiple 16 bit fields, or as m ultiple 32 bit fields. The SFR pulse is one clock cycle wide, changes

state on the r ising edge of SSCLK and precedes the fir st bit of each fi eld. The fi eld size i s set with SSI_FSIZE: 0-ent i r e d at a

block, 1-8 bit fields, 2-16 bit fields, 3-32 bit fields. The polarity of the SFR pulse can be inverted with SSI_FPOL. The first

SFR pulse in a frame w ill rise on the third SSCLK clock period after MU X_SY NC (fourth SSCLK period, if SSCLK is 10MHz).

MUX_SYNC can be used to synchronize the fields arriving at the data logger or DSP.

SRDY: The SRDY input sh ould alw ays be t ied to G ND .

time

data byte least signi fi can t

data byte

time

most significant

data byte least signi fi can t

data byte

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The SSI timing is shown i n Figure 11.

Figure 11: SSI Tim in g (SSI_FPOL = SSI_RDYPOL = 0)

Fau lt and Reset Behavior

Reset Mode

When RESETZ is pulled low or when VFLT < V3P3/2, all activity (i.e. sampling of analog signals, CE, generation of digital

outputs) in the chip stops while the analog circuits are active. The exceptions are the oscillator and RTC module, which

continue to run. Additionally, all I/O Register bits are cleared. As long as VFLT > V3P3/2, the internal 2.5V regulator will

continue to provide power t o the di git al section.

O nce i niti at ed, th e res et m ode wi ll per sis t unti l t he r eset t imer ti m es out. Thi s wi ll occur in 41 00 cycl es of th e rea l t im e clock

after RE SET Z goes high, at which t ime t he 71M6515H will begin executing its pr eboot and boot sequences.

Power Fault Circuit

The power fault comparator compares the voltage at the VFLT pin to V3P3/2. The comparator output internally enables the

batt ery backup protecti on for os cillator, RTC and RAM during the powe r fail mode.

Temperatu re Comp ensation

Voltage Refer ence

The internal voltage reference of the 71M6515H is calibrated at 25°C during device manufacture. The 71M6515H is given

additional temperature-related calibrations which further compensate its ADC gain and allow it to achieve 10PPM/°C over

±60°C tempe rature range .

Temperature Sensor

The device includes an on-chip temperature sensor for determining the temperature of the bandgap reference. The primary

use of the tem perature data is to det ermine the magnitude of compensation requir ed t o offset therm al drift in t he system. The

temperatur e sensor is read once per accumul at io n i nter val.

Temperature measurement can be implemented with the following steps:

1) At a k nown t em perature TN, read the TEMP_RAW r egi ster and wr it e t he valu e int o TEMP_NOM register.

2) Read the DELTA_T r egister at t he know n t emperatur e. The obtai ned valu e should be <±0.1°C.

3) The temperature T (in °C) at any environment can be obtained by reading the DELTA_T register and applying the

following formula:

10 _TDELTA

TT N+=

SCLK (Output)

SSDATA (Output)

SFR (Output)

31 30 16 15 1 0 31

SSI_BEG

30 16 15 1 0 31

SSI_BEG+1

1 0

SSI_END

If 16bi t f ields If 32bi t f ields

If SSI_CKGATE =1 If SSI_CKGATE =1

MUX_STATE

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Tem perature Compensation f or Energy Measurements

TEMP_NOM is one of t he calibration paramet ers that must be loaded by the host in order to enable temperat ure measur em ent

and ther eby temper ature compensati on.

PPMC and PPMC2, the linear and quadratic compensation coefficients, compensate for temperature drift in the 71M6515H

r efer enc e th at aff ect s the m eter per f orm an ce. PPMC and PPMC2 describe how the 71M6515H calculations are to respond to

temperature. This means they should be the negative of the meter behavior before compensation. PPMC and PPMC2 are

scaled from PPM/°C and PPM/°C2 values. See the register description for details. Temperature compensation can be

s elected to operate in o ne of tw o m odes shown i n t he table below :

Temperature Compen sation Mode DEFAULT_PPM Bit in

CONFIG Register PPMC, PPMC2 Calculation

Internal (CE ) 1 By post-process or , based on

stor ed VREF characteristics

Ex ternal (host)

By host

When the part is first powered up, TEMP_NOM, PPMC, and PPMC2 are zero. When the host writes its calibration value into

TEMP_NOM (after setting the DEFAULT_PPM bit on the CONFIG register to 1), PPMC and PPMC2 will automatically be

initialized to the values that best compensate for the temperature drift of the internal reference. These parameters will be

individually custom ized f or 71M6515H parts. If, f or some reason, the host writes to TEMP_NOM again, PPMC and PPMC2 will

not be changed since they will no l onger be zero.

If TEMP_NOM is not l oaded by the host, PPMC and PPMC2 are ignored, and their values are permanent l y held at zero.

If TEMP_NOM is zer o, no temper ature compensation occurs, even if PPMC and PPMC2 are loaded.

If the host wishes to provide its own compensation, it should read PPMC and PPMC2 and modify them by merging the

additional com pensation i nto to them . In that case, the DEFAULT_PPM bi t in the CONFIG register must be zero.

Tem perature Compensation f or the Crystal and RTC

The crystal oscillator contributes negl igi ble error to energy cal culat ions. However, som etim es specifi cati ons for the real tim e

clock (RTC) require better accuracy than that provided by the untrimmed watch crystal. The 71M6515H therefore allows

calibration of the RTC clock. Calibration requires that frequency tolerance and frequency stability either be obtained f rom the

manufacturer or be independently measured (the RTC clock is available on the TMUX pin). Calibration does not change the

frequency of the RTC clock, but rather increments or decrements the clock by one second when sufficient error has

accumulated. Positive correction makes the clock run faster.

The formu la for the RTC correction facto r is as fol lows :

CORRECT ION [PPM] =

CALCY

CALCYCALCY∆

∆

1000 2_

100 1_

10 0_

Where Y_CALC0 = 10 * crys tal freque ncy deviat ion fro m ideal (measured)

Y_CALC1 = 10 0 * cry stal s kew (nominally z ero)

Y_CALC2 = 1000 * crystal frequency stability (specified)

∆T = T - C alibration Temperatur e in °C

Calibration

Cali bration Factors for CT and Resistive Shunt

Once installed in a meter, the TERIDIAN 71M6515H IC has to be calibrated for the tolerances of current sensors, voltage

dividers and signal conditioning com ponents. The r oom temperature reading of its tem perature sensor must also be entered.

These calibration factors must be stored by the host and, upon power up, loaded into the TERIDIAN 71M6515H. Typical

calibration constants are listed in Table 4.

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Name

Description

CAL_IA

Gain factors for curre nt and voltage of each phase .

CAL_VA

CAL_IB

CAL_VB

CAL_IC

CAL_VC

TEMP_NOM

The valu e of TEMP_RAW at nominal te mperature.

PHADJ_A

Phase compensati on for eac h current . If phase compensati on is 0 or if

current sens ors have predictable phase, PHADJ may not need to be

measured on every met er.

PHADJ_B

PHADJ_C

Table 4: Typ ical Cal ibrati on Parameters ( CT )

Gain adjustment (CAL_Xn parameters) is used to compensate for tolerances of components used for signal conditioning,

es pecially t he resisti ve components. A 1% increase in CAL_Xn will cause a 1% i ncrease in the channel gain.

The phase compensation circuit in the TERIDIAN 71M6515H is optimized for operation with current transformers (CT’s).

These devices have a l ow frequency pole and t herefore have a slight am ount of phase lead at 50 or 60Hz—more at 50Hz than

at 60Hz. The phase lead diminishes at higher harmonics. When PHADJ_n is calibrated as shown below at either 50Hz or

60Hz, the CT will be correctly compens ated fr om below 25Hz to beyond 1100Hz.

This phase compensator is m arkedl y super ior to the more common technique of pr o gr amm i ng a ti m e d el ay t o com p en s at e f or

CT phase. The time delay technique results in phase compensation that is correct at only one frequency, and actually

ampli f ies the phase err or at har monic s of the f requency.

Cali bration Factors for Rogowski Coi l Sensors

If IMAGE i s set to 0 1, i.e. the 71M6515H can be operated with Rogowski Coil sens or s. In this case, one more calibration factor

per phase is needed. The PHADJ parameters have non-zero defaults and do not obey the same formula used for CT

calibration. The feedthrough parameter has to be determined by a separate crosstalk measurement. Table 5 shows the

parameters involved in the calibration procedure for the Rogowski sensor.

Name

Description

CAL_IA

Gain constan ts for current and voltage of each phase.

CAL_VA

CAL_IB

CAL_VB

CAL_IC

CAL_VC

TEMP_NOM

The valu e of TEMP_RAW at nominal te mperature.

PHADJ_A

Phase compensati on for eac h current . If phase compensation is 0 or if

current sens ors have predictable phase, PHADJ may not need to be

measured on every met er.

PHADJ_B

PHADJ_C

VFEED_A

Feedthrough compensati on for each curr ent.

VFEED_B

VFEED_C

Table 5: Typical Calibrat ion P arameter s ( R ogow ski)

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General Notes on Cali bration

The calibration procedures described below should be followed after

int erfacing t he voltage and curr ent sensors to the 71M6515H chi p. When

properly interfaced, the V3P3 power supply is connected to the meter

neutral and i s the DC reference for each input. Eac h voltage and current

waveform, as seen by the 6515H, is scaled to be less than 250mV

(peak).

Each m eter phase must be calibrated individually. The procedures below

show how to calibrate a meter phase with either three or five

measurements. Note that there is no need to calibrate for VARh if the

Wh m easurement is calibrated correctly. Note that positive load angles

correspond to lagging current (se e Figure 12).

For a typical calibration, a meter calibration system is used to apply a

calibrated load, e.g. 240V at 30A, while interfacing the voltage and

current sensors to the 71M6515H. This load should result in an ob-

servable pulse rate at the PULSEW output depending on the selected

energy per pulse. For example, 7.2kW will result in an energy rate

corresponding to 7200Wh/3600s = 2Wh/s, i.e., when 7.2kW are applied

per phase (resul ti ng in a t ot al power of 21.6kW, equivalent to 6Wh/s) and

a Kh of 3.2 (Wh/pulse) has been conf igured, a pulse rate of 6Wh/3.2Whs

= 1.875Hz will be est ablished.

Figure 12: Definition of Load Angles

I t i s ent ir ely pos sibl e to calibrate piece-wi se, i .e. in segm ent s, to compensate for non-li nea r s ensor s. For exam pl e, o ne s et of

calibration factors can be appl ied by t he host when the current is bel ow 0. 5A, whil e another set is appli ed when t he current is

at or above 0.5A.

Cali bration Procedure for CT and Resisti ve Shunt

A typical m eter has phase and gai n errors as shown by φS, AXI, and AXV in Figure 13. Following the typical m eter convention of

current phase being in the lag direction, t he small amount of phase l ead in a typical current sensor is represent ed as -φS. The

errors shown in Figure 13 repr esent th e sum of all gai n a nd ph ase er ro rs. They include errors in voltage attenuat ors, current

sensors, si gnal conditioning circuits, and in ADC gains. In other words, no errors are made in the ‘input’ or ‘meter’ boxes.

INPUT

−φ

ERRORS

)

cos(

IDEAL

)

cos(

ACTUAL

−

≡

IDEAL

ACTUAL

IDEAL

ACTUAL

ERROR

RMS

METER

RMS

ACTUAL

IDEAL

ACTUAL

IDEAL

is phase lag

is phase lead

Figure 13: Watt Met er with Gain and Phase Errors.

During the calibration phase, we measure errors and then introduce correction factors to nullify their effect. With three

unknowns to determine, we must make at least three measurem ents. If we make more measurem ents, we can average the

results.

Voltage

Current

+60°

Using EnergyGenerating Energy

Current lags

voltage

(inductive

)

Current leads

voltage

(capacitive

)

-60°

Voltage

Positive

direction

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Calibration with Three Measurem ent s

The simplest calibration m ethod is to make three m easurements. Typically, a voltage m easurem ent and two Watt-hour (Wh)

measure ments are made.

I f t he vol tage measurement has the error EV and the two Wh measurements have errors E0 and E60, where E0 i s m easur ed

with φL = 0 and E60 is mea sur ed wi t h φL = 60. These values should be simple ratios—not percentage values. They should be

zero when the m et er is acc ur ate and negati ve when the meter runs slow. The fundamental frequency is f0. T i s equal to 1/fS,

where fS is the sample frequency (2520.62Hz). Set all calibration factors to nominal: CAL_IA = 16384, CAL_VA = 16384,

PHADJ_A = 0.

From the voltage measurement, we d etermin e that

1. 1+= VXV

We use the other t wo measurements to determine φS and AXI.

1)cos(1

)0cos( )0cos(

−=−

−

SXIXV

AAIV

2a.

)cos( 1

XIXV

)60cos( )60cos(

−

=−

−

XIXV

SXIXV

AAIV

φφ

3a.

[ ]

)60cos( )sin()60sin()cos()60cos(

60 −

=SSXIXV AA

φφ

1)sin()60tan()cos( −+

=SXIXVSXIXV AAAA

φφ

Combining 2a and 3a:

4. )tan()60tan()1( 0060 S

EEE

++=

)60tan()1(

)tan(

060

−

=EEE

6.













−

)60tan()1(

tan

060

EEE

and from 2a:

7.

)cos(

SXV

XI AE

Now that we know the AXV, AXI, and φS error s, w e calcula te t he new cali brat ion vol ta ge gain coeffic ient from the p rev ious ones:

NEW

AVCAL

VCAL _

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We calc u la t e PHADJ from φS, t he desir ed phase lag:

[ ]













−−−−

−−−+

=−−

−−

)2cos()21(1)tan()2sin()21(

)2cos()21(2)21(1)tan(

929

20 TfTf

PHADJ

πφπ

πφ

Finally, we cal culat e the new calibration current gain coef fi cient, including compensati on for a sli ght gain increase i n the phase

calibration ci r cuit.

92020

)21()2cos()21(21

))2cos()21(222(2

−−

−−−

−+−−

−−+

TfPHADJPHADJ

AICAL

ICAL

NEW

Calibration with Fi ve M easurements

The five measurement method provides more orthogonality between the gain and phase error derivations. This method

i nv olv es m ea sur ing E V, E0, E180, E60, and E300. Again, set all calibration factors to nominal, i.e. CAL_IA = 16384, CAL_VA =

16384, PHADJ_A = 0..

First, calculate AXV from EV:

1. 1+= VXV EA

Calculate A XI from E0 and E180:

1)cos(1

)0cos( )0cos(

0−=−

−

=SXIXV

SXIXV AA

AAIV

1)cos(1

)180cos( )180cos(

180

−=−

−

SXIXV

AAIV

2)cos(2

1800 −=+ SXIXV AAEE

)cos(22

1800

XIXV

6.

)cos( 12)( 1800

SXV

XI AEE

Use above results along with E60 and E300 to calculate φS.

)60cos( )60cos(

60 −

−

=IV

AAIV

ESXIXV

1)sin()60tan()cos( −+= SXIXVSXIXV AAAA

φφ

)60cos( )60cos(

300

−

−−

=IV

AAIV

SXIXV

1)sin()60tan()cos( −−= SXIXVSXIXV AAAA

φφ

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Subtract 8 from 7:

)sin()60tan(2

30060 SXIXV

AAEE

=−

use equation 5:

10.

)sin()60tan(

)

cos( 2

1800

30060 S

=−

11.

)tan()60tan()2( 180030060 S

EEEE

++=−

12.













−

)2)(60tan( )(

tan

1800

30060

EE EE

Now that we know the AXV, AXI, and φS error s, w e calcula te t he new cali brat ion vol ta ge gain coeffic ient from the p rev ious ones:

NEW AVCAL

VCAL _

We calc u la t e PHADJ from φS, t he desir ed phase lag:

[ ]













−−−−

−−−+

=−−

−−

)2cos()21(1)tan()2sin()21(

)2cos()21(2)21(1)tan(

929

20 TfTf

PHADJ

πφπ

πφ

Finally, we cal culat e the new calibration current gain coef fi cient, including compensation for a slight gain increase i n t he phase

calibration ci r cuit.

92020

)21()2cos()21(21

))2cos()21(222(2

−−

−−−

−+−−

−−+

TfPHADJPHADJ

AICAL

ICAL

NEW

Alternative Calibr ation Procedur es

It is possible to implement a fast calibration based on only one measurement with a zero-degree load angle. Details can be

found in the TERIDI AN Application Not e AN_651X_022 (Calibration Procedures).

Cali bration Procedure for Rogowski Sensor

Rogowski coils generat e an output signal that is the der ivative of the input current. The 6515H Rogowski m odule implemented

in the Rogowski CE image digitally compensates for this effect and has the usual gain and phase calibration adjustments.

Addi tional ly, cal ibration adjustments are pr ovid ed to el iminate voltage coupling from the sensor input .

Current sensors built from Rogowski coils have relatively high output impedances that are susceptible to capacitive coupling

from the large voltages present in the m et er. The m ost dominant coupling is usually capacitance between the prim ary of the

coil and the coil’s output. This coupli ng adds a component proportional to the deri vative of voltage to the sensor out put. This

effect is compensated by the voltage coupli ng calibration coefficients.

As with the CT procedure, the calibration procedure for Rogowski sensors uses the meter’s display to calibrate the voltage

path and the pulse outputs to per f orm the r em aining energy calibrations. The cali bration procedure m ust be performed t o each

phase sep ar at ely, m aki ng sur e th at t he pul se g ener at or i s dri ven by t he acc umu lat ed r eal en erg y f or ju st th at ph as e. In ot her

words, the pulse gener at or input shoul d be set to WhA, W hB, or W hC, depending on the phase being cal ibr ated. The I C has t o

be configured for Rogowski mode (IMAGE=01). In preparation of the calibration, all calibration parameters are set to their

default values. VMAX and IMAX a r e s et t o r ef l ec t th e s y st em des i g n p ar am et er s . WRATE and PULSE_SLOW, PULSE_FAST are

adjusted to obtain the desired Kh.

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For details on cali brating a meter for Rogowski coil sensors, see the TERIDIAN Application Not e AN_6515_036.

Meter Desi gn - Scaling o f Measu red Valu es

An actual meter will always use sensors that scale the voltages and cur r ents managed by t he meter to small voltages that can

be processed by the 71M6515H. This scaling is reflected in the system parameters VMAX and IMAX. Scaling is physically

implemented with resistor dividers for the voltage signals and current transformers, shunt resistors or Rogowski coils for the

current signals.

IMAX i s t he RMS met er curr ent that results i n 250mV peak signal (or 177mV RMS) at the ADC input (IA, IB, IC pins). VMAX is

the RMS met er vol tage that results in 250mV peak signal at the ADC input ( VA, VB, VC pins). In_8 is either 1 or 8, dependi ng

on In_8x, the A DC g ain c onf igurat ion bi t f or element n ( see IA_8, IB_8 , IC_8 ) in the CONFIG register.

Only the host is aware of the system parameters VMAX and IMAX, while the CE and the post-processor know signal

ampli tudes only as values r elative to their maximum peak l evel s ( 250mV). This makes the host itself responsible for translating

the m easured values from the 71M6515H registers into real-world values by applying the parameters VMAX, IMAX and In_8.

Equally, the host is responsible for non-volatil e storage of accumulated energy values, calibration fact ors, default setti ngs et

cetera.

Measured values and values determining the function of the 71M6515H, as controlled by the registers described in the

following section, are often stated as f rac t ions or multiples of the system paramet ers VMAX, IMAX and In_8.

Host In t erf ace - REGISTE R DESCRI PTIO N

Com muni cati on between the host and the 71M6515H is established by writing to and reading from the registers described in

thi s sect io n. The registers are accessible via the U A RT (see UA RT Wr i te and Rea d Op eration) .

The tables below contain the regi sters that can be accessed by the host to obtai n data from the 71M6515H or to control and

configure the IC.

Bits with a W (w ri te) direction are w ritten by the host. Bits with R (read) direction can only be re ad by the host. Write operations

attem pted to read-onl y r egi st er s wi ll r esult i n t he CMD_IGNORED bit set in the STATUS register. Unl ess stat ed otherwise, al l

r egis ter s are four bytes ( 32 bi ts) , 2’s compl em ent, and have a r ange of (231-1) to -(231-1).

Each register bel ongs to one of the following func tional groups:

• Pulse Ge neration

• Calibration

• Control of Basi c Functions

• Temperature

• Temp erat ure Compensat io n

• Output Signals

• Accumulated Energy and V/I Values

• Alarms and Thresholds

• Time (RTC)

• Test

• Digital I/O Cont r ol ( pin s D0…D7)

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Regi st ers in Alp habeti cal O rder

Name Address

(hex) R/W Default Group Comment

APULSEW

APULSER

APULSE3

APULSE4

0x30

0x31

0x32

0x33

R/W

Pulse Generation C ontr ol

CAL_IA

CAL_VA 0x24

0x25 R/W

R/W 214

214 Calibration

CAL_IB

CAL_VB 0x26

0x27 R/W

R/W 214

214 Calibration

CAL_IC

CAL_VC 0x28

0x29 R/W

R/W 214

214 Calibration

CE_DATA 0x63 R/W N/A Control of Basic Functions

CE_DATA_ADDR 0x61 R/W N/A Cont r ol of Basic Functions

CE_DATA_INC 0x65 R/W N/A Contr ol of Basic Functions

CE_PROG 0x62 R/W N/A Contr ol of Basic Functions

CE_PROG_ADDR 0x60 R/W N/A Control of Basic Functions

CE_PROG_INC 0x64 R/W N/A Contr ol of Basic Functions

CONFIG 0x16 R/W 0 Control of Basic Func tions

CREEP_THRSLD 0x1D R/W 6000 Alarms and Thresholds

DEG_SCALE 0x1C R/W 22721 Temperature

D_CONFIG 0x1A R/W 15 I /O C o n trol

FREQ_DELTA_T 0x11 R N/A Outputs, Temperature

GAIN_ADJ 0x4E R 16384 Temperature

Compensation

IASQFRACT

IBSQFRACT

ICSQFRACT

0x4A

0x4B

0x4C

N/A

N/A Outputs

IASQSUM

IBSQSUM

ICSQSUM

0x39

0x3A

0x3B

N/A

N/A Outputs

INSQFRACT 0x4D R N/A Outputs

INSQSUM 0x3C R N/A Outputs

IPHASE_ABC 0x0F R N/A Outputs Uses the post-

processor

IRMS_A

IRMS_B

IRMS_C

0x0C

0x0D

0x0E

N/A

N/A Outputs Uses the post-

processor

KVAR 0x2F R 6444 Calibration Do not change

MAIN_EDGE_ COUNT 0x35 R N/A Outputs

OP_TIME 0x1E R/W 0 Time

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Name Address

(hex) R/W Default Group Comment

PHADJ_A

PHADJ_B

PHADJ_C

0x2A

0x2B

0x2C

R/W

CT: 0

CT: 0 Calibration Defaults are –3973

for Rogowski

operation

PPMC1_2 0x1B R/W 0 Temperature

Compensation

PULSE3_4_ CNTS 0x42 R N/A Outputs

PULSE_SRCS 0x43 R/W Pulse Generation Control

PULSEW_R_ CNTS 0x41 R N/A Outputs

PULSE_WIDTH 0x34 R/W 50 Pulse Generation Control

QUANT_W

QUANT_VAR

QUANT_I

0x36

0x37

0x38

R/W

0 Calibration

RTC_DATE 0x20 R/W N/A Time

RTC_TIME_DAY 0x1F R/W N/A Time

RTM 0x21 R/W 0 Test

SAG 0x2E R/W 80,

26000 Alarms and Thresholds

SSI 0x22 R/W 0 Test

STATUS

0x14 R N/A Cont r ol of Basic Functions

STMASK 0x15 R/W 0 Control of Basi c Functions

TEMP_NOM 0x13 R/W 0 Outputs

TEMP_RAW 0x12 R N/A Outputs

VASQSUM

VBSQSUM

VCSQSUM

0x3D

0x3E

0x3F

N/A

N/A Outputs

VAH_A

VAH_B

VAH_C

0x06

0x07

0x08

N/A

N/A Outputs Uses the post-

processor

VARH_A

VARH_B

VARH_C

0x03

0x04

0x05

N/A

N/A Outputs

VFEED_A

VFEED_B

VFEED_C

0x44

0x45

0x46

R/W

0 Calibration

VI_PTHRESH 0x17 W 21000 Alarms and Thresholds

VI_THRESH 0x40 W 21000 Alarms and Thresholds

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Name Address

(hex) R/W Default Group Comment

VPHASE_ABC 0x10 R N/A Outputs

VRMS_A

VRMS_B

VRMS_C

0x09

0x0A

0x0B

N/A

N/A Outputs Uses the post-

processor

WH_A

WH_B

WH_C

0x00

0x01

0x02

N/A

N/A Outputs

WRATE 0x2D R/W 683 Pulse Generation Control

Y_DEG0 0x18 R/W 0 Temperature

Compensation Holds Y_CALC0

Y_DEG1_2 0x19 R/W 0 Temperature

Compensation Holds Y_CALC1 and

Y_CALC2

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Individual Register Descrip t ions

Registers for Pul se Generation Control

APULSEW (0x30), APULSER (0x31), APULSE3 (0x32), APULSE4 (0x33),

Figure 14 shows t he r egisters that control the PULSEW , PULSER, PULSE3 and PULSE4 output pins if t he c or respondi ng

PULSE_SRCS register contains the decimal value 36. This figure uses the PULSER_SRC 8-bit portion of the PULSE_SRCS

r egi st er as an exam pl e: T he i nter nal pulse generati on (CE) and the post-pr oces so r p uls e gen er at ion ar e des el ect ed, and

the APULSER register acts as the pulse generation source. In this setting (external pulse generation), the host is

responsible for updating the data in the APULSER register.

PULSER_SRC

35: WSUM

0: WSUM

1: WASUM

2: WBSUM

3: WCSUM

4: VARSUM

34: VAR2SUM_E

36: APULSER

HOST

PULSER

OUTPUT

POST PROC ESSOR

34: VAR2SUM_E

Figure 14: Pulse Generation via APULSER S elected in the PULSER_SRC Register

PULSE_SRCS (0x43)

This register contains the pulse source selectors for the pulses generated by the PULSEW, PULSER, PULSE3 and

PULSE4 output pins. Pulse sources can be selected individually for internal (CE), external (post-processor) or external

(supplied by the host). The internal selection is val id for the PULSER and PULSEW gener ators only. The allocation of the

bytes in PULSE_SRCS i s as fol low s:

31 24 23 16 15 8 7 0

PULSEW_SRC PULSER_SRC PULSE3_SRC PULSE4_SRC

Source selector register for

the PULSE W generator Source selector register for

the PULSER generator Source selector register for

the PULSE3 generator Source selector register for

the PULSE4 generator

Table 6 shows the codes used to sel ect pulse sourc es.

PULSE_WIDTH (0x34)

This register contains the numerical value controlling the pulse width for the PULSEW and PULSER output pins. The

defa ult v alu e i s 50, w hich amounts t o 40.07ms. T he puls e width PW follows the formula:

PW <= (2 * PULSE_WIDTH + 1)/2520.6

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At high pulse rates, duty cycle is 50%. At rates less than 1/(2*PWmax), the negative going pulse width is PWmax. The

allowed range i s 0 to 231-1.

The pulse wi dth f or the PULSE3 and PULSE4 outputs is al ways at a 50% duty c ycle.

The init ial vol tage lev el of the pulse pin s is def ined w ith th e P ULS E_INIT pin.

Value in Pulse

Source Register

(hex) (dec)

Name Description

0x00

WSUM

The signed sum: W0SUM + W1SU M + W 2SU M

0x01

WASUM

The sum of Wh samples f r om individual watt met er el ements.

LSB = 9.4045*10-13 VMAX I MAX / I n_8 Wh

0x02

WBSUM

0x03

WCSUM

0x04

VARSUM

The signed sum: VAR0SUM + VAR1SUM + VAR2SUM

0x05

VARASUM

The sum of VA Rh sampl es f rom individu al wat tmeter element s.

LSB = 9.4045*10-13 VMAX I MAX / I n_8 VARh

0x06

VARBSUM

0x07

VARCSUM

0x08

VASUM

The sum of VA h samples f rom individ ual sampl es.

0x09

VAASUM

The sum of VA h samples f rom i ndividual wat t meter elements.

LSB = 9.4045*10-13 VMAX IMAX / In_8 VAh

0x0A

VABSUM

0x0B

VACSUM

0x0C 12 INSQSUM

The sum of the square of the calculated neutr al current.

∑

++ .)( 2

210 III

LSB = 9.4045*10

-13

IMAX

/ In_8

0x0D

IASQSUM

The sum of squared cur rent s amples f rom each elem ent.

LSB = 9.4045*10-13 IMAX2 / In_82 A2h

0x0E

IBSQSUM

0x0F

ICSQSUM

Table 6: Pulse Sources Def i ned by t he PULSE_SRCS Register (1/2)

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Value in Pulse

Source Register

(hex) (dec)

Name Description

0x10

VASQSUM

The sum of squared voltage sampl es f rom each element.

LSB = 9.4045*10-13 VMAX2 V2h

0x11

VBSQSUM

0x12

VCSQSUM

0x13

WSUM_I

Imported Energy: W0SUM_I + W 1SU M_I + W2SU M _I

0x14

WASUM_I

Imported energy f rom individual watt meter elem ents. N ever negati ve.

LSB = 9.4045*10-13 VMAX I MAX / In_8 Wh

0x15

WBSUM_I

0x16

WCSUM_I

0x17 23 VARSUM_I

Imported VARh:

VAR0SUM_I + VAR1SUM_I + VAR2SUM_I

0x18

VARASUM_I

Export ed react iv e energy f rom i ndividual w at t meter elements. N ever negati ve.

LSB = 9.4045*10-13 VMAX I MAX / I n_8 VARh

0x19

VARBSUM_I

0x1A

VARCSUM_I

0x1B

WSUM_E

Export ed Ener gy: W 0SU M_E + W1SU M_E + W2SU M _E

0x1C

WASUM_E

Export ed energy f rom indivi dual wat t meter elements . Nev er negative.

LSB = 9.4045*10-13 VMAX IMAX / In_8 Wh

0x1D

WBSUM_E

0x1E

WCSUM_E

0x1F 31 VARSUM_E

Export ed VARh:

VAR0SUM_E + VAR1SUM_E + VAR2SUM_E

0x20

VARASUM_E

Export ed react iv e energy f rom i ndividual w at t meter elements. N ever negati ve.

LSB = 9.4045*10-13 VMAX IM AX / In_8 VARh

0x21

VARBSUM_E

0x22

VARCSUM_E

0x23 35 Inter nal (CE )

Connec t s the pul se generator to the WSUM or VARSUM values internally

c alculated by the C E. Not selec table f or PU LSE 3 and PU LSE4 puls e generators.

0x24 36 External

(host)

Indicates that the host w i ll pr ovide val ues in the AP ULS ER , APU LSEW,

APULSE3, and APULSE4 regist ers and that the pulse gener at or should be up-

dated on the next RE AD Y i nter rupt..

Table 6: Pul se Sources Def i ned by the PULSE_SRCS Register (2/ 2)

WRATE (0x2D)

This register controls the rate of the pulse generation for the PULSEW, PULSER, PUSE3 and PULSE4 output pins. The

inverse pulse rat e, exp ressed as Wh per pulse is:

PulseWh

XWRATECYCLESSUMIn IMAXVMAX

Kh /5757.1

_8_ ⋅⋅⋅

(X = value formed by PULSE_SLOW and

PULSE_FAST bits in the CONFIG register)

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Registers Used f or Calibration

CAL_IA (0x24), CAL_VA (0x25), CAL_IB (0x26), CAL_VB (0x27), CAL_IC (0x28), CAL_VC (0x29):

These regist ers adjust t he gain f or the current and volt age measurements of each phase for the purpose of calibration. The

calibration factors have to be stored by t he host and wri tten to the registers of t he 71M6515H af ter power-up. The allowed

range is (215 – 1) to –(215 – 1). The default value of 16384 equals unity gain.

If a vol t age m easurement of phase C is higher than expect ed, CAL_VC has to be adjusted to:

CAL_VC = 16384 / (1 + err or)

Error must be expressed as a fraction, not a per centage val ue.

If the percent error is +3.5% , the relative err or i s 0.035, and th e calibration factor becomes:

CAL_VC = 16384 / (1 + 0.035) = 15829. 952,

which is rounded up to15830.

KVAR (0x2F)

This register holds the relative gain of the VAR cal culation wi th respect to the W att calculation. The val ue should always be

6444.

PHADJ_A (0x2A), PHADJ_B (0x2B), PHAD_C (0x2C)

These registers hold the phase cor r ection factors for channels A, B, and C. The values are used by the CE to compensate

for phase errors induced by current transform ers. The allowed range is (215-1) to -(215-1). See the Calibration Procedure

section for applicable values.

If the CE is oper at ed in Rogowski Coil mode, no phase compensati on should be required. The default value i s not zero and

should need to be changed only slightly, if at al l. See t he Calibration section for det ail s.

QUANT_W (0x36), QUANT_ VAR (0x37), QUANT_ I (0x38)

These regi sters hold DC values that ar e added to each calculat ed product in order to com pensate f or i nter nal quant ization

(a very small amount) and external noise. These values are normally set to zero. The LSB values for these variabl e are

listed in Table 7.

Variable LSB Value Unit

QUANT_W (VMAX IMAX/ In_8)* 1.04173*10-9 W

QUANT_VAR (VMAX IMAX / In_8)* 1.04173*10-9 VAR

QUANT_I (IMAX

/ In_8

)* 5.08656*10-13 A (rms)

Table 7: LSB Values for QUANT Variables

Nonlinearity is most noticeable at low currents, and can result from input noise and truncation. Nonlinearities can be

eliminated using the QUANT_W register. The error can be seen as t he pr esence of a virtual constant noi se current that

bec omes domi nant at sm all load currents.

The valu e t o be used for QUANT_W can be determi ned by the f ollowing f ormula:

LSBIMAXVMAX

InIV

error

WQUANT ⋅⋅

⋅⋅

−= 8_

100

Where er ror = observ ed err or at a gi ven voltage (V) and cur rent (I),

VMAX = voltage scali ng factor , as des cribed in secti on Scali ng of Measured Val ues

IMAX = current scal ing factor, as described in secti on Scali ng of Measured Val ues

LSB = Q UANT LSB value = 1. 04173*10-9W

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Example: For a Wh measurement, an error of +1% was obser v ed at 1A. If VMAX is 600V and IMAX = 208A,

and if the measurement was tak en at 240V, we det ermine QUANT_W as follows:

18460

1004173.1208600

1240

100

−=

⋅⋅⋅

⋅

−=

−

WQUANT

The negative value obtained by the calculation will co mpe nsate for the positive e rror. It does not matter which current value

is chosen as long as the correspondi ng error value is significant (5% error at 0.2A used in the above equati on will produce

the same result for QUANT_W).

Input noise and truncation can cause similar errors i n the VAR calculation that can be eliminated using the QUANT_VAR

VFEED_A (0x44), VFEED_B (0x45), VFEED_C (0x46)

These regi sters hold the com pensat ion factors for feedthrough used for cali brating Rogowski coils. The allowed r ange is

(215-1 ) to -(215-1). See t he section on Rogowski Coil Calibration for details.

Registers Controlling Basic Function and Set tings of t he 71M6515H

CONFIG (0x16)

The four bytes written t o this register det erm i ne the basic operati on of the 71M6515H. The func tion of the 28 bit s used for

this register are explained below:

Bit 0: This bit (VAH_SELECT) determines the method used by the post-processor for determining the apparent energy

measured in V Ah. I f t he bit i s 0 (default), t he calc ulat ion i s based on V RMS, IRMS and the time (t) per the formula:

VAh = VRMS * IRMS * t

The accuracy of the result can be improved for low currents by set ting Bi t 0 to 1. The c al culation is then based on the Wh

and VA Rh values per t he formula :

VARhWhVAh +=

Using the calculation method above, high accuracy can be achi eved for low currents.

Bi t 3: T hi s bi t ( RTM_EN) en ables t he R ea l -Time Monitor function when set t o 1.W hen used, the RTM signal is available at

the T M UX pin .

Bi t 4 : This bit (CE_EN) enabl es the CE when set to 1. The CE has to be enabled for most meter ing functions.

Bits 7-5: Th ese three bits (EQU) def ine the equation (see table below) to be impl em ented by the CE.

EQU Watt & VAR Formula Application

0 VA IA 1 element, 2W 1ø

1* VA(IA-IB)/2 1 element, 3W 1ø

2 VA IA + VB IB 2 element , 3W 3 øD elt a

3* VA (IA - IB)/2 + VC IC 2 element , 4W 3ø D elt a

4* VA(IA-IB)/2 + VB(IC-IB)/2) 2 element, 4W 3ø Wye

5 VA IA + VB IB + VC IC 3 element, 4W 3ø Wye

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Bit s 13-8: These si x bits ( SUM_CYCLES) d efine t he length of th e accumulation interval τ per the for mula:

6.2520 42_ ⋅

=CYCLESSUM

All owed val ues are 24 (400ms ) through 60 (1000ms), unl ess the post-processor is disabled . Bit 8 i s the LSB.

It i s important to not e that the l ength of the ac cumulation interval, as det ermined by SUM_CYCLES, is not an exact multiple

of 1000ms. F or example, if SUM_CYCLES = 60, the resulting accumulation interval is:

Hz 75.999

62.2520

2520

32768

4260 ==

⋅

This means that accurate time measurements should be based on the RTC, not the accumulation int erval.

Bi t 1 4: Th is bit (CKOUT_DISB) disabl es the CKOUT pin when set. The CKOUT pin can be used for di agnostics. For EMC

compliance and power saving reasons, CKOUT_DISB should always be set.

Bit 15: Thi s bit (ADC_DIS) disabl es t he A DC wh en s et , e. g. to sa ve p ower . O f c our se, no m et er ing or measuring can be

perfo rmed with t he A DC disabled.

Bits 18-16: These three bits (TMUX) select the source for the TMUX diagnostic output pin. For EMC compliance and

power s aving reasons, TMUX should be zero (default) if unused.

Bi t 1 8

TMUX2

Bi t 1 7

TMUX1

Bi t 1 6

TMUX0

TMUX Signal Selected for the TMUX Pin

GND

MUX_SYNC

RTM

RTC Out p ut

CE_BUSY

XFER_BUSY

VX_OK (Compa rator Output )

V3P3/2 =1.5V i nternal analog voltage

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Bits 20-19: These two bits (F_SELECT) select t he phase that is t o be used for f r equency measur em ent. The frequency will

be shown in bits 31-16 of t he FREQ_DELTA_T register (and as bit 4 of the STATUS word – i n t hi s f orm as a di gi tized zero

crossing signal).

Bi t 2 0

F_SELECT1

Bi t 1 9

F_SELECT0

F_SELECT

Phase

Selected

Phase A

Phase B

Phase C

Not all owed

Since the signal at the input selected wit h F_SELECT i s used to synchronize f ilters and other processi ng stages in the CE,

accuracy for most measurements will be reduced if no voltage is present at the selected phase input. Accuracy can be

established by selecting the phase that carries a stable si gnal (A, B, or C).

Bit 21: This bit (CE_ONLY) disables the post-processor when set to 1. When the post-processor is disabled, the time-

intensive computations of IPHASE, IRMS, VAh and VRMS are not performed, and therefore smaller accumulation times

(SUM_CYCLES < 24) ar e per mit ted. In t his c ase, t he host i s responsible for calculating I PH AS E, I RM S , VAh and VRMS.

Bits 23-22: These two bits (IMAGE) select the code to be used by the CE. The CE can be operated in standard mode

when us ing CTs and/or shunt resistor s ens ors or i n Rogowski mode when using Rogowski coil sensor s. In order to switch

the operation mode , the CE has to be disabled first by clearing the CE_EN bit.

Bi t 2 3

IMAGE 1

Bi t 2 2

IMAGE 0

IMAGE CE Code Sel ected

Standard (CT /shunt)

Rogows k i c oil

Standard (CT /shunt)

Bit 24: This bit (RESET), when reset, forces all internal states of the 71M6515H to their powe r-up defaul t.

Bits 26-25: These two bits (PULSE_SLOW, PULSE_FAST) modify the speed of the pulse generator. PULSE_SLOW and

PULSE_FAST determi ne the factor X in the equat ion used f or Kh as shown i n the table below.

PULSE_SLOW

PULSE_FAST

1.5*22 = 6

1.5*26 = 96

1.5*2-4 = 0. 09375

1 (default)

1.5

PULSE_SLOW and PULSE_FAST will affect the operation of all four pulse outputs. See the Pulse Generation section for

details.

Bits 29-27: Th es e t h r ee bit s ( IA_8X, I B_8X, IC_8X) appl y an additional gain of 8 to t he IA, I B, and I C channels when set to

1. This is a useful tool when very small signals are encountered, as is the case when using current shunt resistors with

very low resistance whil e oper at ing at low currents. Care must be taken to avoid clipping. If the input to the meter exceeds

IMAX/8, cli pping will occur. These bits shoul d normally be zero, unless additional gai n following the ADC stage is needed.

Bit 30: This bit (DEFAULT_PPM) defines the source of temperature compensation. When DEFAULT_PPM is 1, the

71M6515H will automatically apply compensation coefficients der ived from the stored VREF temperature characteristics to

the PPMC and PPMC2 registers. When DEFAULT_PPM is zero, the host is allowed to write its own values to the PPMC and

PPMC2 registers.

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STATUS (0x14)

The four bytes in this register reflect the status of the various measurement functions of the 71M6515H. This register is

read only. When a bit in the STMASK register is set, an interr upt (IRQZ) is generated as soon as the correspondi ng bit in

the STATUS register is set.

Bi t 0 : This bit (BOOTUP) signals a r equest from the 71M6515H to the host to be i nitiali zed.

Bit 1: This bit (SAGA ), w hen set, i ndic ates th at the volt age appli ed to phase A has sagged below SAGTHR. See the for SAG

Bi t 2 : This bit (SAGB), when set, indicates that the voltage appl i ed to phase B has sagged below SAGTHR.

Bi t 3 : This bit (SAGC), when set , indicates that the voltage appli ed to phase C has sagged below SAGTHR.

Bit 4: This bit (F0) follows the polarity of the input voltage selected with the F_SELECT bits in the CONFIG register. It

r epres ents a smoothed, f ilt ered and squared copy of the f undamen tal waveform.

Bit 5: This bit (MAXV), when set, indicates that a voltage greater than the voltage limit defined in the VI_PTHRESHOLD

r egis ter h ad been detected in t he previo us accumulatio n i nterval .

Bit 6: This bit (MAXI), when set, indicates that a current greater than the current limit defined in the VI_PTHRESHOLD

r egis ter h ad been detected in t he previo us accumulatio n i nterval .

Bi t 7 : This bit (1SECI, t oggles ever y second. I t i s contr olled by the R TC.

Bit 8: This bi t (VXEDGE), when set , i ndicates a change i n state of VX com parator. Thi s bit is updated ev ery accumulati on

interval.

Bit 9: This bit (DEDGE), when set, indicates a change in state of any selected DIO pin. This bit is updated every

accumulation interval. Pins have to be configured to generate the DEDGE flag using the DIO_INT_CTRL bits in the

D_CONFIG register.

Bi t 10: Thi s b it ( XOVF), when set, i ndicates that the host failed to read at least one of the Wh values. Between interrupts

(i ndi cated by the READY bit in the STATUS wor d), the 71M6515H exp ects the host to read at least one of t he WATTHR_A,

WATTHR_B, o r WATTHR_C values.

Bit 11: This bit (READY), when set , indicates that the 71M6515H has f r esh output values ready for the host. Setting this bit

in STMASK will enable the hardware interrupt output pin IRQZ.

Bit 14-12: These bits (bit 12 for phase A, bit 13 for phase B, bit 14 for phase C), when set, indicate that the energy

r ec ei v ed f r om elemen t A, B, or C i s belo w t h e c r eep t h r es h ol d def in ed i n th e CREEP_THRSHLD register or t h at th e c ur r en t

in elements A, B, or C is below the threshold defined in bits 15-0 of th e START_THRESHLD register. The creep condition

flagged by bits 14-12 of the STATUS register indicates that Wh, VARh, and IRMS measurements of element A, B, or C

have been zer oed out. Consequently, accumulation di d not occur.

Bit 15: This bit (CMD_IGNORED), when set, indicates that the 71M6515H ignored the last command received from the

host. The reason can be any type of command incompatibility, e.g. attempts to write to a read-only register.

Bit 16: This bit (PULSEW_ERR), when set, indicates that the pulse generator PULSEW is configured for external (host)

input, b ut di d not r ecei ve an update duri ng t he previous accumul at io n i nter val.

Bi t 1 7: This bit (PULSER_ERR), when set, indicates t hat the pulse generat or PULSER is configured for external ( host) input,

but did not receive an updat e during the pr evious accumulation int erval.

Bit 18: This bit (PULSE3_ERR), when set, indicates that the puls e generator PULSE3 is conf igured for external ( host) input,

but did not receive an updat e during the pr evious accumulation int erval.

Bit 19: This bit (PULSE4_ERR), when set, indicates that the pulse generator PULSE4 is configured for external ( host) input,

but did not receive an updat e during the pr evious accumulation int erval.

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STMASK (0x15)

The four bytes in this register enabl e i nterrupts when the correspondi ng bit in the STATUS r eg i st er i s s et. Th e d ef a ul t v al u e

for STMASK is zero.

W hen a bit in the STMASK regist er is set, an interrupt (IRQZ) i s generat ed as soon as the cor respondi ng bit in the STATUS

register is set. Interrupts indicated by IRQZ do not necessarily have to be synchronized with accumulation intervals. For

example, the toggling of a signal applied to the DIO pins (D0…D7), when t he interrupt is enabled wit h the DIO_INT_CTRL

Registers Controlling Temperature M easurement and Compensation

DEG_SCALE (0x1C)

This register holds the scal e factor used to c alcul ate the internal tem perature value provided by the tem perat ur e sensor to

temperat ure in degrees Celsius (°C). The default value is 22721 and should not be changed.

FREQ_DELTA_T (0x11)

This regist er holds f requency and t emperatur e inf or mat io n i n tw o bytes each.

31 16 15 0

FREQUENCY (see Output R egis ter s) DELTA_T

Bits 15-0: These bits (DELTA_T) represent the temperature information relative to the value stored in the TEMP_NOM

r egis ter. O ne LSB is equivalen t to 0. 1°C . The f or mul a used for DELTA_T is:

DELTA_T = -DEGSCALE*2-22*(TEMP_RAW-TEMP_NOM)

TEMP_NOM (0x13)

This register holds the nominal (reference) temperature. During calibration, the host must write the value read from

TEMP_RAW to TEMP_NOM in order to enable tem perature com pensation. See the Meter Calibration sec tion for details. The

temperature available in register DELTA_T is based on the difference between the current temperature, as provided in

TEMP_RAW, and the ref erence temperatur e provid ed by TEMP_NOM.

TEMP_RAW (0x12)

This read-only register holds the raw temperature provided by the temperature sensor on the 71M6515H chip. During

calibration, the host must write the value read from TEMP_RAW to TEMP_NOM in order to enable temperature

compensation.

Example: A t cal ib r at io n t i me, t he raw temperat ure va lue of 853030 was re ad from the TEMP_RAW regis ter and

writte n to th e TEMP_NOM r egister. At a later tim e, the raw temperature register reads 844866. The 71M6515H

c alculates t he temperat ure di fference to:

DELTA_T = -DEGSCALE*2-22*(TEMP_RAW-TEMP_NOM) = 44

This v alue is i nter pret ed as +4. 4°C.

PPMC1_2 (0x1B)

This register holds the linear and squared compensation factors for the ADC temperature compensation. The allowed

range is (215 – 1) to – (215 – 1). Bot h w ords are r eset to zer o i f TEMP_NOM equals zero.

31 16 15 0

PPMC = ADC linear factor (PPMC = 26.84 * PPM/°C ) P PMC2 = ADC quadrati c factor (PPMC2 = 1374 * PPM/ °C

)

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The 71M6515H perf orms ADC tem perature com pensation by com puting a gain adjustment factor for both the volt age and

c urr ent sampl es per the follow ing equation:

GAIN_ADJ=16384+floor(1+DELTA_T*PPMC/214+DELTA_T2*PPMC2/223)

Changes to PPMC1_2 by the host are only allowed if the DEFAULT_PPM bit i n the CONFIG regi ster i s zero. If additi onal

temperatur e compensat io n by the host , e. g. for ex ter nal c omponents, is r equired , the procedure is as f ollow s:

1) The host sets the DEFAULT_PPM bit in the CONFIG register to 1 and then re ads PPMC and PPMC2.

2) The host then adds the compensation factors to PPMC and PPMC2, resets the DEFAULT_PPM bit in the CONFIG

r egis ter to 0 and then wri tes t he modi fied values t o PPMC and PPMC2.

Y_DEG0 (0x18)

This register holds the constant compensation factor for the RTC temperature compensation. One LSB is equivalent to

0.1PPM.

Bit s 31-16: These bits ( Y_CALC0) r epresent t he constant compensat ion factor.

Y_DEG1_2 (0x19)

This register holds the linear and quadratic compensation factors for the RT C t emperatur e compensat ion.

31 16 15 0

Y_CALC1 = linear compensation factor. One LSB is equi-

valent to 0.01PPM/° Y_CALC2

= quadratic compensation factor. One LSB is

equivalent to 0. 001PPM/°C

Both Y_DEG0 and Y_DEG1_2 can be used to compensate the RTC to be accurate over the whole temperature range by

characterizing the crystal.

Registers for Output Signals

PULSEW_R_CNTS (0x41)

This register contains the pulse count for the PULSEW and PULSER output pins for the past accumulation interval. The

counters will be cleared at the begi nning of each accumulation interval and then st art counting up with each generat ed pulse.

Bi t 1 5 -0: The counte r for the PULSER (VARh) generator.

Bi t 3 1 -16: The counter for the PULSEW (Wh) generator.

31 16 15 0

Counter for the PULSEW gene rator (Wh) Counte r for the PULSER generator (VARh)

At pulse rat es that do not r esult in generation of whole counts per accumulati on i nter val, e. g. 3 1/ 3 pulses, the count equiv alent

to the next lower natural number will be generated until the residue accumulates to a full count, i.e. the pulse sequence

generat ed will be 3, 3, 3, 4, 3, 3, 3, 4…

PULSE3_4_CNTS (0x42)

This register contains t he pulse count for the PULSE3 and PULSE4 output pins for the accum ulation interval. The counters

will b e cleared at the beginning of each accum ulation int erval and then start counti ng up with each generated pulse.

Bi t 1 5 -0: The counter for the PULSE4 generat or.

Bi t 3 1 -16: The counte r for the PULSE3 generator.

31 16 15 0

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Counter for the PULSE3 generator Counte r for the PULSE4 generator

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IASQSUM (0x39), IBSQSUM (0x3A), ICSQSUM (0x3B)

These registers hold the sum of the squared current samples collected during the previous accumulation interval. The

v alues for IASQSUM, IBSQSU M, and ICSQSUM are provided directly by the CE and are not post-processed. The magnitude

of the accumulat ed samples i s determined by:

IMAX

LSB 213

2104045.9

−

⋅=

IASQFRACT (0x4A), IBSQFRACT (0x4B), ICSQFRACT (0x4C)

These read-only registers hold the difference between the 10-bit residual squared current sum of the current accumulation

interval and the 10-bit residual squared current sum of the previous interval. If IASQSUM, IBSQSUM, or ICSQSUM are

used to calculate current, the value obtained over several accumulation intervals will be accurate due to averaging, but

the individual values wi ll have a higher unc ertainty than when using IASQFRACT, IBSQFRACT, and ICSQFRACT.

The most accur at e calculation of the squared current for a phase X ( IXSQ) uses t he formul a:

IXSQ = IXSQSUM + 2 -10 IXSQFRACT

INSQFRACT (0x4D)

This r egister holds the di ff erence between the 10-bit residual squared neutral currents of the current accumu lation interva l

and the 10-bit residual squared neutral c urr ent s of t he p rev io us in ter val. Th e val ue c an b e used t o i m pro ve th e ac cur ac y

of the squared neutral cur r ent reading by applying the formula:

IN SQ = INSQSUM + 2-10 INSQFRACT

INSQSUM (0x3C)

This register holds the sum of the square of the calculated neutral current collected during the previous accumulation

int erval. The calculation is impl ementing the f ollowing equation:

( )

∑++= 2

210 IIIINSQSUM

The magnitude of the accumulat ed sampl es is determi ned by:

IMAX

LSB 213

2104045.9

−

⋅=

IPHASE_ABC (0x0F)

This register holds voltage-to-current phase information for all three phases. Positive phase means lagging current

(inductive load). One LSB is equivalent to 1 degree. The range is from (28 – 1) t o –(28 – 1). Since the phase calcul ation

involves the post-processor, these regist ers will not be functional when t he CE_ONLY bit in the CONFIG register is set.

Bit s 8-0: These bits (IPHASE_C) represent t he voltage-to-current phase angle in phase C.

Bit s 17-9: These bits (IPHASE_B) r epresent t he vol tage-to-current phas e angle in p hase B.

Bit s 26-18: T hese bits (IPHASE_A) represent the voltage-to-current phase angle in phase A.

IRMS_A (0x0C), IRMS_B (0x0D), IRMS_C (0x0E)

These registers hold the post-processed RMS current for each phase. Only the 16 most significant bits are used. The

magnitude of the values is determined by:

rmsA

CYCLESSUMIn

IMAX

LSB _8_

108781.6 9−

⋅

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Since t he R M S calculati on i nvolv es the post-processor, these regist ers will not be functional when the CE_ONLY bit in the

CONFIG register is set. If higher precision is required, the host must calculate the RMS currents from the values in the

IASQSUM, IBSQSUM, and ICSQSUM registers. For even higher precision, the IASQFRACT, IBSQFRACT, ICSQFRACT

r egis ter s should be used.

Example: T he r egi st er IRMS_C reads the value 2,079,670. Assuming IMAX to be 208A, and using the f ormula

above, we determ ine the RMS curr ent of phase C to:

RMS

0385.0

208108781.6

2079670

⋅

⋅=

−

VASQSUM (0x3D), VBS QSUM (0x3E), VCSQSUM (0x3F)

These registers hold the sum of the squared voltage samples collected during the previous accumulation interval. The

values for VASQSUM, VBSQSUM, and VCSQSUM are provided directly by the CE and are not post-processed. The

magnitude of the accumulat ed s amples is determined by:

hVVMAXLSB

2132

104045.9

−

⋅=

VAH_A (0x06), VAH_B (0x07), VAH_ C (0x08)

These registers hold the apparent energy collected during the previous accumulation interval. The magnitude of the

accumulated samples is determined by:

VAh

In IMAXVMAX

LSB 8_

104045.9 13−

⋅=

Since the VAh calculation involves the post-processor, these registers will not be functional when the CE_ONLY bit in the

CONFIG r egister i s set .

VARH_A (0x03), VARH_B (0x04), VARH_ C (0x05)

These registers hold the reactive energy collected during the previous accumulation interval. The magnitude of the

accumulated samples is determined by:

VARh

In IMAXVMAX

LSB 8_

104045.9

13−

⋅=

VPHASE_ABC (0x10)

This register holds the phase angle between t he voltages of phases A/C and A/ B. The LSB is one degree.

Bit s 15-0: T hese bits (VPHASE_AC) hold the phase angl e between VA and VC.

Bit s 31-16: T hese bits ( VPHASE_AB) hold the phase angle between VA and VB.

VRMS_A (0x09), VRMS_B (0x0A), VRMS_C (0x0B)

These registers hold the post-processed RMS voltage for each phase. Only the 16 most significant bits are used. The

magnitude of the values is determined by:

rmsV

CYCLESSUM

VMAX

LSB _

108781.6

9−

⋅

Since t he R M S calculati on i nvolv es the post-processor, these regist ers will not be functional when the CE_ONLY bit in the

CONFIG r egister i s set .

71M6515H

Energy Meter IC

DATA SHEET

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A Maxi m In tegrated Produ cts Brand

If hi gher pr ecision is required, the host m ust calculate t he RMS vol tages f rom t he values in the VASQSUM, VBSQSUM, and

VCSQSUM registers.

Example: The register VRMS_B reads the value 425,778,000. Assuming VMAX to be 600V, and using the

formula above, we determi ne t he RMS voltage of phase B to:

RMS

85.226

600108781.6

425778000

⋅

⋅=

−

WH_A (0x00), WH_B (0x01), WH_C (0x02)

These registers hold the real energy collected during the previous accumulation interval. The magnitude of the values is

deter m ined by:

In IMAXVMAX

LSB 8_

104045.9

13−

⋅=

Example: The regist er WH_A reads the value 236,675 for one accumulation interval of one second. Assuming

600V for VMAX, 208A for IMAX, and unity gain, we determine t he real energy to be:

E = 236, 675*600*208* 9.4045*10-13 W h = 0.0277781Wh.

By multiplying with 3,600, we get 100Wh/h, which means the applied power i s 100W.

FREQ_DELTA_T (0x11)

This register holds frequency and t emperature inform ati on in two bytes eac h.

Bits 31-16: These bits (FREQUENCY) represent the frequency of the input signal selected with the F_SELECT bit of the

CONFIG register. One LSB is equivalent to 0. 1Hz.

MAIN_EDGE_CNT (0x35)

This register holds the num ber of zero crossings of the i nput phase selected by the F_SELECT bits in t he CONFIG register

detect ed in the prev ious accumulation inter val. The value in MAIN_EDGE_CNT can be used by t he host to correct its own

RTC or t o synchronize events to the l ine voltage.

Registers Controlling Al a rms and Thr esholds

CREEP_THRSLD (0x1D)

Th e f our bytes written to this regist er determine the creep threshold. Setting a creep t hreshold hel ps suppressing I2H, W h

and VARh readings when the val ues of WSUM and VARSUM are determined t o be below the creep t hr eshold.

Example: The creep t hr eshold of a m eter oper ati ng with an accumulation interval of 1000ms is to be configured

to be 15mA at 240V. The meter i s using a VMAX of 600V, an I MAX of 208A, and is not using the addi tional gain

of 8. T he numer ic al valu e for the CREEP_THRSLD register is to be determined.

W ith 15mA, the power per phase will be 3.6W , or 0.001W h per second. With the LSB of W SUM readings given

as 9.4045* 10-13*VM A X* IMAX [W h], we deter mine t he val ue to:

n = 0.001 Wh / (9.4045*10-13*VMAX*IMAX / I n_8 W h) = 8520. 2

The rounded down value of 8520 is written to th e CREEP_THRSLD register.

SAG (0x2E)

This register holds the vol tage and timing threshold for sag detecti on.

Bits 15-0: These bits (SAG_CNT) hold t he sag count. A sag condition must persist for at least SAG_CNT samples before a

sag alarm is generated. The allowed range is 1 to (215-1), and the default is 80 (31.7ms). The time period defined by

SAG_CNT is:

T = SAG_CNT*397µs

71M6515H

Energy Meter IC

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Bi t s 31 -16: T hes e b i ts ( SAGTHR) hold t he vol tage t hreshol d that is to be appl ied for sag detection. The peak voltage m ust

exceed SAGTHR once eac h SAG_CNT sampl es in ord er to prevent a SAG w ar ning. One LSB is defi ned as:

VMAXLSB

916

1028798.7

−

⋅⋅=

Example: A meter operating at 50Hz and 240V ( RMS) is supposed to apply a sag t hr eshold of 180V (RMS)

for at least four periods before a sag warning is issued. VMAX is 600V. Which values are to be selected for

SAG?

Four per i ods tr anslate to T = 4 * 20ms = 80m s. This means that

SAG_CNT = T/397µs = 202.

180V (RMS) trans late to 255V (peak) , so SAGTHR i s determined by

823

6001028798.7

255255

916

⋅⋅

−

LSB

SAGTHR

START_THRESHLD (0x40)

This register holds the voltage and current thresholds that apply to the calculation of frequency, zero crossings, voltage

phase and en ergy val ues. If the current is below the value stored in I_START, calculation of RMS current, and energy (Wh,

VARh and VAh) is suppre ssed.

Bits 15-0: These bits (I_START) hold the threshold to be applied for under-current. If ISQSUM< I_START, all post-

processed values are set to zero for that phase. This includes reported values for Wh, VARh, VAh, IRMS, VPHASE,

IPHASE, PULSER, PULSEW , PULSE3 and PULSE4. This applies only if CREEP_THRSLD is not set to zero. One LSB is

defined as:

IMAX

LSB

213

104045.9

−

⋅⋅=

Eleme n ts with ISQSUM< I_START wil l set the creep bits i n t he STATUS register.

Bits 31-16: These bits (V_START). hold the threshold to be applied for under-voltage. If VRMS<V_START, the values for

frequency (register FREQ_DELTA_T), zero crossings (register MAIN_EDGE_CNT), and voltage phase (register

V_PHASE_ABC) are set to zero. Additionally, if VRMS< V_START, the reported value of VRMS is set to zero. One LSB is

defined as:

hVVMAXLSB

213162

104045.92

−

⋅⋅⋅=

Elements with VRMS< V_START will not set the creep bits i n t he STATUS register.

VI_PTHRESHOLD (0x17)

This regist er holds t he thr eshold for over-v olta ge and over-current alarms.

Bi ts 15-0: T hese bi ts (I_PTHRESHOLD) hold t he threshold to applied for over-current alarm. The threshold comparison is

applied to t he upper 16 bits of the val ues in IRMS: One LSB is defi ned as :

rmsA

CYCLESSUMIn

IMAX

LSB _8_

1076.450

6−

⋅

Bits 31-16: T hes e b i t s ( V_PTHRESHOLD). hol d the threshold to applied for over-vol tage al arm. The threshold comparison

is appli ed to the upper 16 bits of the values in VRMS One LSB is defined as:

71M6515H

Energy Meter IC

DATA SHEET

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A Maxi m In tegrated Produ cts Brand

rmsV

CYCLESSUM

VMAX

LSB _

1076.450

6−

⋅

Example: A meter designed with VMAX=600V and IMAX=208A is supposed to apply an overvoltage

threshold of 520V (RMS) and an over-current threshold of 400A (RMS). Which values are to be selected for

V_PTH RESHOLD and I_PTHRESHOLD?

893,14

6001076.450 520520

⋅

−

CYCLESSUM

LSB

PTHRESHOLDV

046,33

2081076.450 400400

⋅

−

CYCLESSUM

LSB

PTHRESHOLDI

Registers Controlling Time and RTC Functions

OP_TIME (0x1E)

This register holds the operati ng tim e express ed in 1/100 hour s . The r egist er will be reset t o zero when ever the host writes

ti me or date t o t he R TC .

RTC_DATE (0x20)

This regist er holds t he date i nfor mation p rovided by th e RTC . The register c an be written to in order to set the date.

Bit s 15-8: These bits contain the y ear information ( 0 to 255) . The val ue 0 r epresent s the year 2000.

Bit s 23-16: These bits contain the month inf or mat ion ( 01 to 12). T he value 01 r epresents Januar y.

Bit s 31-24: These bits contain the day of m onth information (01 to 31).

RTC_TIME_DAY (0x1F)

This register holds the time and day information provided by the RTC. The register can be written to in order to set the

time.

Bit s 7-0: These bi ts contain the day of the week (01 to 07). The value 01 represents Sunday.

Bit s 15-8: These bits contain the hour informat ion ( 00 to 23) . The val ue 00 r epresent s midnight.

Bit s 23-16: The se bits contain the minute s informa tion (00 to 59).

Bit s 31-24: These bits contain the s econds inform ati on (00 to 59).

Example: The value 200835 is read from the OP_TIME register . This m eans that the meter has been running

s ince t he las t reset or power-up for

t = 800850/ 100h = 8008.50h or 8,008h and 30 minutes (333.6875 days or 333 days and 16.5h).

Registers Used for Test Functions

RTM (0x21)

This register controls the Real-Tim e Moni tor . W h en t he RTM_EN bit in the CONFIG r egi st er i s set , t he val ues of CE R AM

locations specified with the RTM register can be routed to the TMUX pin as a serial data stream. The TMUX bits in the

CONFIG r egister must be set to 3 i n or der to selec t t he R TM output for t he TM U X pin.

Bit s 7-0: These bits (RTM3) sel ect the C E address for RT M3 .

71M6515H

Energy Meter IC

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Bit s 15-8:. Th ese bit s (RTM2) selec t the CE address for RTM 2.

Bit s 23-16: These bits ( RTM1) select the CE address for RTM1.

Bit s 31-24: These bits ( RTM0) select the CE address for RTM0.

SSI (0x22)

This register controls the function of the Serial Synchronous Interface (SSI). The function of the SSI is described in the

Internal Resources section of this data sheet. If the SSI is enabled (bit 23, SSI_EN, in the SSI register), a block of CNT

words starting at the address BEG will be t ransmitted each 397µs.

Bit s 7-0: T hes e b i t s ( CNT) select the number of CE RAM address locations to be transmitted. The value in CNT must be

>= 0.

Bit s 15-8: These bits (BEG) def in e the star t address of the transfer regio n of t he C E data R AM addres s.

Bit 16: This bit m ust be set to zer o.

Bit 17: This bit must be set to zero.

Bit 18: This bit (SSI_FPOL) defines the polar it y of t he SFR pulse signal (0: positive, 1: negative).

Bit s 20-19: These bits ( SSI_FSIZE) defi ne t he frame pul s e f ormat as f oll ows:

Bi t 2 0 Bit 1 9 SSI_FSIZE S SI Frame Pulse Format

0 0 0 O nce at beginning of SSI s equence

0 1 1 Every 8 bits

1 0 2 E very 16 bits

1 1 3 E very 32 bits

Bit 21: This bit (SSI_CGATE) enab le s the clock to be gated. When low , the SSCLK signal is active continuously, when high,

the SSCLK s ignal i s held low wh en no data is being t ransfer r ed.

Bit 22: This bit (SSI_10M) defines the speed of the SSCLK si gnal: 0: 5MHz, 1: 10MHz.

Bit 23: This bit (SSI_EN), wh en set to 1, enables the SSI interfa ce.

Registers Used f or I/O Control

D_CONFIG (0x1A)

This register holds three bytes that ar e used to m anipulate the DIO pins of the 71M6515H.

Bits 7-0: These bits (DIO_VALUE) form the data register for the DIO pins D0 through D7. When a byte is written to

DIO_VALUE, the pins conf igured as out put s (using the D_DIR regist er) will change their state ac cordi ngly. Pi ns configured

as inputs will ignore t he byte written to DIO_VALUE.

Reading DIO_VALUE will return a byte that reflects the stat e of all pins regardless whether they are configured as i nputs or

outputs.

Bit s 15-8: T hese bits are not used

Bi t s 2 3 -16: T hes e b i t s ( D_DIR) defi ne the dat a direction. Bit 0 cont rols the D0 pin, bi t 7 controls the D7 pi n. Set t i n g t h e bit

corresponding to a pin to 1 makes the pi n an output, clearing it to 0 makes it an input.

Bi t s 3 1 -24: T hese bit s ( DIO_INT_CTRL) form a mask enabling the DEDGE i nt errupt (bit 9 of t he STATUS word register). Bit

8 controls the D0 pin, bit 15 controls the D7 pi n. Setting the bit cor responding to a pin to 1 enables the DEDG E i nt er r u pt ,

clearing the bit disables the interrupt. If the bit in DIO_INT_CTRL is set and a t r ansitio n f rom high to lo w or from low t o high

occurs, the DEDGE interrupt bit in t he STATUS word register will be set in the following accumulation interval.

71M6515H

Energy Meter IC

DATA SHEET

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A Maxi m In tegrated Produ cts Brand

Example: DIO pins D0 through D3 are to be configured as outputs, while D4 through D7 are to be inputs. DIO7

must generat e a DEDGE i nterrupt when t he input value changes, and D0 thr ough D3 m ust apply the hexadecim al

pattern 0x05. T his m akes the selec t ion for the D_CONFIG registe rs as follows:

DIO_INTCTRL = 0x80, D_DIR = 0x0F, DIO_VALUE = 0x05

The valu es are combi ned int o the 32-bit pat tern 0x800F0005.

Example: D0 through D5 are to be configured as outputs, while D6 and D7 are to be inputs. D6 and D7 must

generat e a DEDGE int errupt when their input value changes. This makes the selection f or the D_CONFIG registers

as follows:

DIO_INTCTRL = 0xC0, D_DIR = 0x3F

The valu es are combi ned int o the 32-bit pattern 0xC03F0000.

71M6515H

Energy Meter IC

DATA SHEET

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Regi st ers in Numeri cal Order

Address Name Address Name Address Name

0x00 WH_A 0x20 RTC_DATE 0x40 START_THRESHLD

0x01 WH_B 0x21 RTM 0x41 PULSEW_R_CNTS

0x02 WH_C 0x22 SSI 0x42 PULSE3_4_CNTS

0x03 VARH_A 0x23 RESERVED 0x43 PULSE_SRCS

0x04 VARH_B 0x24 CAL_IA 0x44 VFEED_A

0x05 VARH_C 0x25 CAL_VA 0x45 VFEED_B

0x06 VAH_A 0x26 CAL_IB 0x46 VFEED_C

0x07 VAH_B 0x27 CAL_VB 0x47

0x08 VAH_C 0x28 CAL_IC 0x48

0x09 VRMS_A 0x29 CAL_VC 0x49

0x0A VRMS_B 0x2A PHADJ_A 0x4A IASQFRACT

0x0B VRMS_C 0x2B PHADJ_B 0x4B IBSQFTACT

0x0C IRMS_A 0x2C PHADJ_C 0x4C ICSQFRACT

0x0D IRMS_B 0x2D WRATE 0x4D INSQFRACT

0x0E IRMS_C 0x2E SAG 0x4E GAIN_ADJ

0x0F IPHASE_ABC 0x2F KVAR

0x10 VPHASE_ABC 0x30 APULSEW

0x11 FREQ_DELTA_T 0x31 APULSER

0x12 TEMP_RAW 0x32 APULSE3

0x13 TEMP_NOM 0x33 APULSE4

0x14 STATUS 0x34 PULSE_WIDTH

0x15 STMASK 0x35 MAIN_EDGE_CNT 0x60 CE_PROG_ADDR

0x16 CONFIG 0x36 QUANT_W 0x61 CE_DATA_ADDR

0x17 VI_PTHRESH 0x37 QUANT_VAR 0x62 CE_PROG

0x18 Y_DEG0 0x38 QUANT_I 0x63 CE_DATA

0x19 Y_DEG1_2 0x39 IASQSUM 0x64 CE_PROG_INC

0x1A D_CONFIG 0x3A IBSQSUM 0x65 CE_DATA_INC

0x1B PPMC1_2 0x3B ICSQSUM

0x1C DEG_SCALE 0x3C INSQSUM

0x1D CREEP_THRSLD 0x3D VASQSUM

0x1E OP_TIME 0x3E VBSQSUM

0x1F RTC_TIME_DAY 0x3F VCSQSUM

71M6515H

Energy Meter IC

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APPLICATION INFORMATION

Meter Circuits

Bits 7 through 5 (EQU) of the CONFIG register all ow the selection of the metering equation that i s to be implemented by the

71M6515H. The equation to be used depends on t he meter configuration.

Figure 15 shows how the 71M6515H is connected for the most common configurati on, the three-phase, f our-wir e W YE. The

neutral wi r e connects to V3P3A. For this configuration, equation 5 mus t be sel ected.

LOAD A

71M6515H

V3P3A

Distribution

transformers

ANSI: Form 16S

EQU = 5

LOAD B

P=VA*IA+VB*IB+VC*IC

LOAD C

Figure 15: 4-Wire 3-Phase WYE Connecti on

In many three-phase three-wire confi gurations, one phase can be grounded, as shown in Figure 16. Again, the grounded wir e

is connected to V3P3A. For this configuration, equati on 2 m ust be selected.

The four-wire three-phase delta configuration is shown in Figure 19. In this case, the center tap of the transformer that

provides the A-C voltage is grounded. the grounded wire is connected to V3P3A. For this configuration, equation 2 must be

selected. For this configuration, equat ion 3 m ust be selected, i. e. P = VA*(IA-IB)/2 + VC*IC.

71M6515H

Energy Meter IC

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EQU = 2

P=VA*IA+VB*IB 71M6515H

V3P3A

LOAD A

LOAD B

Figure 16: 3-Wire 3-Phase Del t a Connection

71M6515H

V3P3A

LOAD B

LOAD A

LOAD C

NEUTRAL

Figure 17: 4-Wire 3-Phase Del t a Connection

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Com muni cation bet ween the 71M6515H and the Host Processor

General

To ensure proper transf er of energy and other values from the 71M6515H to t he host, the out put data of t he 71M6515H must

be read by the host each time they are ready, and no energy-r elat ed d atum can be mi ssed. Thi s requir es c los e synchroniza-

ti on between the 71M6515H and the host.

Control Signals

Figure 18 shows the control signals between t he 71M6515H and the host pr ocessor. These signals are:

1) TX: Serial transm it output pin of the 71M6515H

2) RX: Serial receive input pin of the 71M6515H

3) IRQZ: I nterrupt output, us ed as “Data Ready” hardware signal of the 71M6515H (low-active)

4) RESETZ: Reset input pin of the 71M6515H (low-active, should be pull ed up to V3P3)

5) UARTCSZ: UART r eset input pin of t he 71M6515H (low-active)

6) BAUD_RATE: Baud rat e select input pin of the 71M6515H (optional)

7) PULSE_INIT: Pulse pol arity select input pin of the 71M6515H (optional)

TX and RX are t he most essential signals for the communication between the 71M6515H and the host processor. The IRQZ

pin provides a useful output signal that can be used by the host to determine whether the 71M6515H has fresh data ready.

IR QZ can be connected to ei ther an interrupt inp ut or general I / O inp ut of th e host pr ocessor.

RESETZ can be used to force a hardware reset of the 71M6515H, and UARTCSZ can be used to reset (pur ge) the UART of

the 71M6515H communication buffers for reconfiguration. The additional pins BAUD_RATE and PULSE_INIT can be hard-

wired for configuring t he communication baud rate and the puls e status, or controlled on power up by the host processor.

Figure 18: Connections between 71M6515H and Host

Note that the DIO pins of the host processor used to control the 71M6515H are not lost, since the 71M6515H can provide

eight DIO pins ((DIO0…DI O7) to act as general-purpose D IO pins.

Since the communication between the 71M6515H and its host is based on a binary protocol, it is imperative for the host to

issue a clean character stream without added bytes (UART drivers of high-level oper ati ng system s often add extra bytes to the

charact er st r eam , rel y i ng o n er r o r-detecting protocol s). In c as e t he 71M6515H l oses synchr oni zation due to unexp ect ed byt es

sent by the host, i t times out after 10ms (maximum 20ms). The 71M6515H flags a tim e-out condition by setting the BOOTUP

71M6515H Host

IRQZ IRQ or DIO_1

RESETZ

UARTCSZ

DIO_2

DIO_3

BAUD_RATE

PULSE_INIT

DIO_4

DIO_5

DIO0...DIO7DIO

3.3V

71M6515H

Energy Meter IC

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flag in the STATUS register. This happens because the i nc omplete or garbled data could have included a write comm and to the

CONFIG register or other important registers.

Met hods of Control

Two different m ethods of control can be used by the host processor :

1) Synchronization using the I RQZ pin of the 71M 6515H (interrupt or DIO pin polli ng method, s ee Figure 19):

a. Interr upt Method: The IRQZ pin of the 71M6515H is connected t o a pin of the host processor that can gener ate an

int errupt f or the host processor. This is the easiest method for synchronization bet ween the 71M6515H and the host .

The CONFIG register of the 71M6515H is set up t o generate an int errupt on th e IRQZ pin whenever fr esh data are

ready, and the int errupt ser vice routine of the host processor r eads the f r esh data out of the 71M6515H.

b. DI O pi n polling meth od: The I RQZ pin of the 71M6515H i s connected t o a DIO pin of the host processor. The host

processor polls the st atus of the DIO pin as frequentl y as possi ble or through a timer-bas ed polling m ethod. The

CONFIG register of the 71M6515H i s set up to have the IRQ Z pin t o go low on ever y fresh data ready status, and the

timer-s erviced pol ling of the host processor will monitor the status of the DIO pin and initiate t he seri al communication

when IRQZ is detected. For t his met hod to be eff ective, the fi r mwa re of t he host p roc essor must m aintain the t i mer

inter rupt to be the highe st priority, followed by the serial communications priority.

2) Polling the READY bit in the STATUS word of the 71M6515H (status pol li ng method, see Figure 20).

This method requires t hat the hos t processor ut ili z es a timer wit h 1ms t o 5ms r esolut ion t ied i nto th e high est-priority

interrupt . The int err upt service rout in e must in itia te r eadin g t he STATUS register, pref erabl y at least every 10ms, i n

order to monitor the READY bit, but t he host pr ocessor must wait for the response of each st atus request. O t herwise,

the STATUS register read operations will be st ack ed in the 71M6515H resulting in multiple responses.

If a delay ed response is received upon a STATUS re gis te r read, the host proce ssor will know that the 71M6515H is

wit hin its post-processi ng peri od, whi ch m akes it necessary hat the hos t waits for the response. Every ti me t he

READY bit in the STATUS r egister is not set, ind icating that dat a is not available, the host s hould poll again

Figure 19: Timing D iagram (Using IRQZ, SUM_CYCLES = 12)

The communication between the 71M6515H and the host processor can always be reset without disturbing the metering

function by utilizing the UARTCSZ and BAUDRATE pins. Conf iguring t he BAUDRATE pin without resetting t he UART buff er s

is not recommended. The UART of the 71M6515H can be “reset ” by pulling the UARTCSZ pin low. This will f orc e th e UART

back into the default configuration while cl earing all buffer s (UART buffers, UART-relat ed buf fer s in the f irmwa re).

200ms 400ms

80ms

read

command

from host

read

command

from host

post-processor

active post-processor

active

6515H data 6515H data

time

80ms

IRQZ

300ms 500ms

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Energy Meter IC

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Figure 20: Timing D iagram (Host Polling)

Comm unication Steps f or Int err upt M ethod:

The following is a l i st of commands r equired from the host process or to establish communication with t he 71M6515H.

1) Establish host baud rate and data format as required by the 71M6515H.

2) Configure the DIO pins (D0…D7 ), if requ ired, using the D_CONFIG register

3) Configure the 71M6515H by selecti ng t he CE im age (bi t s 23-22), equation ( bits 7-5) , puls e rate ( bi ts 26-25), followed

by enabling the CE (bit 4 in the CONFIG register). The bit pattern sent to CONFIG should have all bits set to their

default state, as given in t he Register T able.

4) Write the TEMP_RAW value obtained at calibration into the TEM_NOM register to enabl e temper ature compensati on.

5) Write the calibration coefficients into registers CAL_IA, CAL_VA, CAL_IB, CAL_VB, CAL_C, CAL_VC, PHADJ_A,

PHADJ_B, PHADJ_ C. Write calibration values to t he VFEED_A/B/C regist ers if the Rogowsk i image is used.

6) Configure WRATE with the value r equired to generate the desired pulse r ate.

7) Establish creep, sag and over/under voltage/current thresholds, if necessary, by writing values to the

CREEP _THRSLD, SAG, VI_PTHRESH, and VI_THRSHLD registers.

8) Set the READY b it in the status mask STMASK i n order t o enable the generation of interrupts on the IR QZ p in.

9) Rea d at lea st one accumul ated val ue register (WATTH_X, or VAH_X, or VARH_X).

10) Wai t for th e IRQ Z pin t o go low.

11) Af t er rec ei v i n g th e i nt er r u pt, r ea d at lea s t o ne a c cum u l at ed va l ue r eg i ster ( WATTH_X, or VAH_X, o r VARH_X) in order

t o mai n t ai n i nt er r u pt g ener a t i on. Rea d t he b i t s i n t h e STATUS word to detect potenti al faults (overflow si gnaled by the

XOVF flag or uninitialized condition signaled by the BOOTUP flag) or warnings and events (sag, creep, excessive

voltage or current , DIO signal changes). I f necessary, take cor rective action.

12) After r eading the required data from t he 71M6515H, configurat ion changes should be m ade, if necessary. These con-

fi guration changes should be completed before the pr e-proce ssing pe riod be gins again.

1000ms 2000ms

330ms

read

commands

from host

read

commands

from host

6515H not

ready 6515H not

ready

post-processor

active post-processor

active

330ms

6515H data 6515H data

time

71M6515H

Energy Meter IC

DATA SHEET

JULY 2011

A Maxi m In tegrated Produ cts Brand

Timing

The fundamental factor for all timing considerations i s SUM_CYCLES, wh ic h d et erm i n es t h e l en gt h of t he a c c um ul at i on in t er va l

for the 71M6515H per the equation:

CYCLESSUM 6.2520 42_ ⋅

The default setting for SUM_CYCLES is 60, which yields an accumulation interval close to 1,000m s. A conservative minimum

number f or SUM_CYCLES is 24, which yields an accum ulation interval close to 400m s. Both calculations by the post-processor

in the 71M6515H and the communication between 71M6515H and the host have to be completed within the accumulation

inter val . If an accumulation int erval ha s passed, and the energy values have not been read by the host, t hey are los t forever.

In order to analyze the timi ng of the comm unication bet ween t he 71M6515H and the host, i t i s useful to know the basic timing

requirements of the post-pr ocessor of t he 71M 6515H . S ome timing p aramet ers ar e list ed in Table 8.

CE_ONLY VAh Calculation Resulting Calculation Time

Disabled Ve ctor me thod :

22 VARhWhVAh +=

350ms

Disabled Vrms*Irms method 80ms

Enabled X 40ms

Table 8: P ost-p rocesso r Timing

As can be seen in Table 8, the calculation tim e can be gr eatly reduced if the VAh values are calculated using the m et hod of

multiplying Vrms by Irms (by resetting bit 0 i n the CONFIG r egist er) , w hich is less accurat e at low curre nts.

Furt her improvement can be achieved by dis abl ing the post-processor using the CE_ONLY bit in the CONFIG register. This is

possible f or applicati ons wher e the registers IPHASE, IRMS, VAh and VRMS ar e not required.

It becomes clear now t hat the mini mu m value of 24 for SUM_CYCLES, equivalent to a 400ms accumulation interval, accom-

modates the worst-case scenario, using the vector method, which requires 350ms post-processing t ime. T his s ettin g l eaves

around 50ms f or the commu nic at io n t o take place between the 71M6515 and the host. If the simpl er Irms*Vrm s m ethod i s

c hosen for VAh, a low er value can be selected for SUM_CYCLES.

Lower values for SUM_CYCLES, f or example 12, yielding a 200ms acc umulation interval, are possible, leavin g st ill 1 20ms for

host communications, as long as the Vrms*Irms met hod for VAh is used.

Some ot her timin g parameters are list ed in Table 9.

Parameter Value Comment

Time from power-up to UART being funct i onal 370ms ±10%

Time fr om HW r eset to U AR T being f unctiona l 370ms ±10%

Time fr om s oft reset t o U AR T being f unc ti onal 245ms ±10% Soft reset = RESET bi t in CONFIG register

is set hig h.

Time from UARTCSZ pin low to UART being functional 20ms

UA RTC SZ is p ol led just b efore the

71M6515H checks its data buff er for a

command. This means that the command

latency specif ied in the E lec trical S pecifi-

cations section also applies to the

UARTCSZ pin.

Table 9: UART Timing Parameters

71M6515H

Energy Meter IC

DATA SHEET

JULY 2011

A Maxi m In tegrated Produ cts Brand

PACKAGE OUTLINE

11.7

12.3

0.60 Typ.

1.40

1.60

11.7

12.3

0.00

0.20

9.8

10.2

0.50 Typ. 0.14

0.28

PIN No. 1 Indicator

NOTE: Contr olling dim ensions are in mm

Ord erin g I nformatio n

PART DESCRI P TION ORDER NO. PACKAGING

MARK

71M6515H 64-Pin LQFP Lead-Free, 10PPM/°C VREF 71M6515H-IGT/F 71M6515H-IGT

71M6515H 64-Pin LQFP Lead-Free, 10PPM/°C VREF, T&R 71M6515H-IGTR/F 71M6515H-IGT

71M6515H 64-Pin LQFP Lead-Free, 40PPM/°C VREF 71M6515H-IGTW/F

71M6515H-IGTW

71M6515H 64-Pin LQFP Lead-Free, 40PPM/°C VREF, T&R 71M6515H-IGTWR/F

71M6515H-IGTW

1 71M6515H-IGTW requires program loading by the customer. Please contact factory for more infor mation.

71M6515H

Energy Meter IC

DATA SHEET

JULY 2011

A Maxi m In tegrated Produ cts Brand

REVISIO N HISTORY

Revision Date Description

Rev. 1.0 O ctober 26, 2005 Fi rst publication.

Rev. 1.1

Decemb er 11, 2006

Changed c apacitor values f or XIN/XOUT

Corr ected addresses for C E_D ATA and made a ddresses C E_D ATA etc. visible i n

table “Registers in Numerical Order”.

Changed freque ncy range to 46-64Hz and “Real-time cloc k fo r TOU” to “Real-time

c lock with temperatur e compensation” on title page.

Added complet e chapter on com munic at ion between host and 6515H.

Changed pin n ame V1 to VFLT in Electrical Specification.

Consolidated s pelling f or CREEP_THRSLD register. Added expl anation for X in

formula for WRATE.

Adde d information on processing time for registers invo lving post-processing.

Changed default value for WRATE to 683.

Delet ed note on low-pass filter in the C E in CONFIG register description.

Added note at CONFIG reg is ter d escript ion stating that phase with stable volt age

can be sel ected wit h F_SELECT to avoid inaccurate measurements and note

stating that PULSE_SLO W and PULSE_FAST affect all four pulse source s.

Added diagram “ Connections between 71M6515H and host ”.

Rev. 1.2 March 15, 2007 Added I/O Equivalent Circuit diagrams and c irc uit type numbers i n Pi n Descr ipt ion s.

Added note in Pin Descr iptions stating that the voltage at RX m ust not exceed 3.6V.

Added VREF aging data.

Clar ified polar ity of SS DA T and SSCLK pins.

Rev. 1.3 August 17, 2007 Changed r ecommended value for capaci t ors at XIN/XOUT to 22pF.

Changed r ecommended crystal to ECS ECX-3TA series .

Added note on exact l ength of default accumulation int erval.

Corr ected bit l ocatio ns for D_CONFIG register.

Added note in pin description f or D0-D7 and Digital I/O” section: D0 t hrough D7 are

high impedance after reset or pow er-up and are configured as outpu ts and driven

low 140ms af ter RE SE TZ goes high.

Updated default values for VIPTHRESH and VI_THRESH.

Rev. 1.4 March 5, 2008 Changed pin and r egister nam es to PULSEW and PULSER and updated block

diagram (Figure 2), up dated pin -out diagr am wi th corr ected pin n ames.

Removed COMPARATOR table in ELECTRICAL SPECIFICATIONS.

Changed not e for SRDY in pin descri ption t able t o “ SR DY should be tied to gr ound”,

deleted Figur e 13 (SRDY f unction) and removed all text desc ribing the functi on of

SR DY (exc ept t hat SRDY should be grounded), deleted Figure 13 (SSI Timing w/

SRDY) and removed refer ences to SRDY in Figure 12.

Consolidated spelling of Y_CALC etc. const ants in section “Temperature Com-

pensation f or the Cr ystal and RTC” and in the register tables .

Added reference t o f ast cali br ation procedure (AN_651X_022).

Added diagrams f or metering confi gurations.

Improv ed Tabl e 6 and explanation of PULSE_SRC register.

Changed c apacitor val ues for XIN/XO UT to 27pF and added recommended load

capacitance value (12.5pF).

Changed r egister name at location 0x38 from QUANT_V to QUANT_I.

Re moved non lead-fr ee packages from Orde ring Infor ma tion.

Updated T eridian str eet address.

Added text at explanation of bi t s 14-12 of the STATUS reg ister s t ating that these bi ts

are also set when the current is bel ow the threshold defi ned by bit s 15-0 of the

START_THRESHLD register. Added at explanation of START_THRESHLD : “Elements

with VRMS< V_START will not set the c reep bit s in t he STATUS register ” and

“Elements with ISQSUM< I_START wi ll set the creep bits i n the STATUS register”.

71M6515H

Energy Meter IC

DATA SHEET

JULY 2011

A Maxi m In tegrated Produ cts Brand

Adde d value for Rθ

in Electrical Specification.

Rev 1.5 January 18, 2011 Changes for transi tion to Maxim DC:

- Title page: D elet ed ref erence to tem perat ure ra nge in 0.1% Wh accur acy

s tat ement . Delet ed “Protects accumul ated data” u nder “ Bat tery Backup”.

- D eleted refer ence t o “ patented” technolo gy

- Deleted F igu re 6 ( Typical Meter Accuracy over Temperatur e)

Added Guaranteed By Design notes to Electrical Specifications.

Changed the Cr yst al O scillat or electrical speci ficat ion TY P f rom blank to 3 .

Changed t he Capacitance t o DGND Xin and Xout TYP from blank to 5. D eleted t he

MAX values.

Changed the AD C C onvert er, V 3P 3 Reference electr ical specification TH D 250mV-

pk TY P f rom blank t o -75. Changed the THD 20m V-pk TYP from blank to -90.

Delet ed the M AX valu es.

Rev 1.6 July 8, 2011 Added 71M6515H-IGTW to the data sheet.

Added footnotes to VREF and temperature sensor specifications.