SN54ALS273, SN74ALS273
OCTAL D-TYPE FLIP-FLOPS
WITH CLEAR
SDAS218A – APRIL 1982 – REVISED DECEMBER 1994
Copyright 1994, Texas Instruments Incorporated
1
POST OFFICE BOX 655303 • DALLAS, TEXAS 75265
•Contain Eight Flip-Flops With Single-Rail
Outputs
•Buffered Clock and Direct-Clear Inputs
•Individual Data Input to Each Flip-Flop
•Applications Include:
Buffer/Storage Registers
Shift Registers
Pattern Generators
•Package Options Include Plastic
Small-Outline (DW) Packages, Ceramic
Chip Carriers (FK), and Standard Plastic (N)
and Ceramic (J) 300-mil DIPs
description
These octal positive-edge-triggered flip-flops
utilize TTL circuitry to implement D-type flip-flop
logic with a direct-clear (CLR) input.
Information at the data (D) inputs meeting the
setup-time requirements is transferred to the
Q outputs on the positive-going edge of the clock
(CLK) pulse. Clock triggering occurs at a particular
voltage level and is not directly related to the
transition time of the positive-going pulse. When
CLK is at either the high or low level, the D input
signal has no effect at the output.
The SN54ALS273 is characterized for operation
over the full military temperature range of –55°C
to 125°C. The SN74ALS273 is characterized for
operation from 0°C to 70°C.
FUNCTION TABLE
(each flip-flop)
INPUTS OUTPUT
CLR CLK D
OUTPUT
Q
L X X L
H↑HH
H↑LL
HH or L X Q0
1
2
3
4
5
6
7
8
9
10
20
19
18
17
16
15
14
13
12
11
CLR
1Q
1D
2D
2Q
3Q
3D
4D
4Q
GND
VCC
8Q
8D
7D
7Q
6Q
6D
5D
5Q
CLK
SN54ALS273 ...J PACKAGE
SN74ALS273 . . . DW OR N PACKAGE
(TOP VIEW)
3212019
910111213
4
5
6
7
8
18
17
16
15
14
8D
7D
7Q
6Q
6D
2D
2Q
3Q
3D
4D
1D
1Q
CLR
5Q
5D 8Q
4Q
GND
CLK VCC
SN54ALS273 . . . FK PACKAGE
(TOP VIEW)
PRODUCTION DATA information is current as of publication date.
Products conform to specifications per the terms of Texas Instruments
standard warranty. Production processing does not necessarily include
testing of all parameters.
SN54ALS273, SN74ALS273
OCTAL D-TYPE FLIP-FLOPS
WITH CLEAR
SDAS218A – APRIL 1982 – REVISED DECEMBER 1994
2POST OFFICE BOX 655303 • DALLAS, TEXAS 75265
logic symbol†
1D
3
1D
11
CLK C1
R
1
1Q
2
4
2D 2Q
5
7
3D 3Q
6
8
4D 4Q
9
13
5D 5Q
12
14
6D 6Q
15
17
7D 7Q
16
18
8D 8Q
19
CLR
†This symbol is in accordance with ANSI/IEEE Std 91-1984 and IEC Publication 617-12.
logic diagram (positive logic)
CLK
1D
3
1D
C1
R
1Q2
2D
4
1D
C1
R
2Q5
3D
7
1D
C1
R
3Q6
4D
8
1D
C1
R
4Q9
5D
13
1D
C1
R
5Q12
6D
14
1D
C1
R
6Q15
7D
17
1D
C1
R
7Q16
8D
18
1D
C1
R
8Q19
CLR
11
1
absolute maximum ratings over operating free-air temperature range (unless otherwise noted)‡
Supply voltage, VCC 7 V. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
Input voltage, VI 7 V. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
Operating free-air temperature range, TA: SN54ALS273 –55°C to 125°C. . . . . . . . . . . . . . . . . . . . . . . . . . . . .
SN74ALS273 0°C to 70°C. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
Storage temperature range –65°C to 150°C. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
‡Stresses beyond those listed under “absolute maximum ratings” may cause permanent damage to the device. These are stress ratings only , and
functional operation of the device at these or any other conditions beyond those indicated under “recommended operating conditions” is not
implied. Exposure to absolute-maximum-rated conditions for extended periods may af fect device reliability.
SN54ALS273, SN74ALS273
OCTAL D-TYPE FLIP-FLOPS
WITH CLEAR
SDAS218A – APRIL 1982 – REVISED DECEMBER 1994
3
POST OFFICE BOX 655303 • DALLAS, TEXAS 75265
recommended operating conditions
SN54ALS273 SN74ALS273
UNIT
MIN NOM MAX MIN NOM MAX
UNIT
VCC Supply voltage 4.5 5 5.5 4.5 5 5.5 V
VIH High-level input voltage 2 2 V
VIL Low-level input voltage 0.7 0.8 V
IOH High-level output current –1 –2.6 mA
IOL Low-level output current 12 24 mA
fclock Clock frequency 0 30 0 35 MHz
CLR low 10 10
twPulse duration CLK high 16.5 14 ns
CLK low 16.5 14
t
Set p time before CLK↑
Data 10 10
ns
t
su
S
etup t
i
me
b
e
f
ore
CLK↑
CLR inactive state 15 15
ns
thHold time, data after CLK↑0 0 ns
TAOperating free-air temperature –55 125 0 70 °C
electrical characteristics over recommended operating free-air temperature range (unless
otherwise noted)
PARAMETER
TEST CONDITIONS
SN54ALS273 SN74ALS273
UNIT
PARAMETER
TEST
CONDITIONS
MIN TYP†MAX MIN TYP†MAX
UNIT
VIK VCC = 4.5 V, II = –18 mA –1.5 –1.5 V
VCC = 4.5 V to 5.5 V, IOH = –0.4 mA VCC –2 VCC –2
VOH
VCC =45V
IOH = –1 mA 2.4 3.3 V
V
CC =
4
.
5
V
IOH = –2.6 mA 2.4 3.2
VOL
VCC =45V
IOL = 12 mA 0.25 0.4 0.25 0.4
V
V
OL
V
CC =
4
.
5
V
IOL = 24 mA 0.35 0.5
V
IIVCC = 5.5 V, VI = 7 V 0.1 0.1 mA
IIH VCC = 5.5 V, VI = 2.7 V 20 20 µA
IIL VCC = 5.5 V, VI = 0.4 V –0.2 –0.2 mA
IO‡VCC = 5.5 V, VO = 2.25 V –20 –112 –30 –112 mA
ICCH VCC = 5.5 V 11 20 11 20 mA
ICCL VCC = 5.5 V 19 29 19 29 mA
†All typical values are at VCC = 5 V, TA = 25°C.
‡The output conditions have been chosen to produce a current that closely approximates one half of the true short-circuit output current, IOS.
SN54ALS273, SN74ALS273
OCTAL D-TYPE FLIP-FLOPS
WITH CLEAR
SDAS218A – APRIL 1982 – REVISED DECEMBER 1994
4POST OFFICE BOX 655303 • DALLAS, TEXAS 75265
switching characteristics (see Figure 1)
PARAMETER FROM
(
INPUT
)
TO
(
OUTPUT
)
VCC = 4.5 V to 5.5 V,
CL = 50 pF,
RL = 500 Ω,
TA = MIN to MAX†UNIT
(INPUT)
(OUTPUT)
SN54ALS273 SN74ALS273
MIN MAX MIN MAX
fmax 30 35 MHz
tPHL CLR Any Q 4 24 4 18 ns
tPLH
CLK
Any Q
220 2 12
ns
tPHL
CLK
An
y
Q
3 17 3 15
ns
†For conditions shown as MIN or MAX, use the appropriate value specified under recommended operating conditions.
SN54ALS273, SN74ALS273
OCTAL D-TYPE FLIP-FLOPS
WITH CLEAR
SDAS218A – APRIL 1982 – REVISED DECEMBER 1994
5
POST OFFICE BOX 655303 • DALLAS, TEXAS 75265
PARAMETER MEASUREMENT INFORMATION
SERIES 54ALS/74ALS AND 54AS/74AS DEVICES
tPHZ
tPLZ
tPHL tPLH
0.3 V
tPZL
tPZH
tPLH tPHL
LOAD CIRCUIT
FOR 3-STATE OUTPUTS
From Output
Under Test Test
Point
R1
S1
CL
(see Note A)
7 V
1.3 V
1.3 V1.3 V
3.5 V
3.5 V
0.3 V
0.3 V
th
tsu
VOLTAGE WAVEFORMS
SETUP AND HOLD TIMES
Timing
Input
Data
Input
1.3 V 1.3 V 3.5 V
3.5 V
0.3 V
0.3 V
High-Level
Pulse
Low-Level
Pulse
tw
VOLTAGE WAVEFORMS
PULSE DURATIONS
Input
Out-of-Phase
Output
(see Note C)
1.3 V 1.3 V
1.3 V1.3 V
1.3 V 1.3 V
1.3 V1.3 V
1.3 V
1.3 V
3.5 V
3.5 V
0.3 V
0.3 V
VOL
VOH
VOH
VOL
Output
Control
(low-level
enabling)
W aveform 1
S1 Closed
(see Note B)
W aveform 2
S1 Open
(see Note B)
[
0 V
VOH
VOL
[
3.5 V
In-Phase
Output
0.3 V
1.3 V 1.3 V
VOLTAGE WAVEFORMS
PROPAGATION DELAY TIMES
VOLTAGE WAVEFORMS
ENABLE AND DISABLE TIMES, 3-STATE OUTPUTS
R2
VCC
RL
Test
Point
From Output
Under Test
CL
(see Note A)
LOAD CIRCUIT
FOR OPEN-COLLECTOR OUTPUTS
LOAD CIRCUIT FOR
BI-STATE
TOTEM-POLE OUTPUTS
From Output
Under Test Test
Point
CL
(see Note A) RL
RL = R1 = R2
NOTES: A. CL includes probe and jig capacitance.
B. W aveform 1 is for an output with internal conditions such that the output is low except when disabled by the output control.
W aveform 2 is for an output with internal conditions such that the output is high except when disabled by the output control.
C. When measuring propagation delay items of 3-state outputs, switch S1 is open.
D. All input pulses have the following characteristics: PRR ≤ 1 MHz, tr = tf = 2 ns, duty cycle = 50%.
E. The outputs are measured one at a time with one transition per measurement.
Figure 1. Load Circuits and Voltage Waveforms
PACKAGE OPTION ADDENDUM
www.ti.com 5-Sep-2011
Addendum-Page 1
PACKAGING INFORMATION
Orderable Device Status (1) Package Type Package
Drawing Pins Package Qty Eco Plan (2) Lead/
Ball Finish MSL Peak Temp (3) Samples
(Requires Login)
84136012A ACTIVE LCCC FK 20 1 TBD Call TI Call TI
8413601RA ACTIVE CDIP J 20 1 TBD Call TI Call TI
8413601SA ACTIVE CFP W 20 1 TBD Call TI Call TI
SN54ALS273J ACTIVE CDIP J 20 1 TBD A42 N / A for Pkg Type
SN74ALS273DW ACTIVE SOIC DW 20 25 Green (RoHS
& no Sb/Br) CU NIPDAU Level-1-260C-UNLIM
SN74ALS273DWE4 ACTIVE SOIC DW 20 25 Green (RoHS
& no Sb/Br) CU NIPDAU Level-1-260C-UNLIM
SN74ALS273DWG4 ACTIVE SOIC DW 20 25 Green (RoHS
& no Sb/Br) CU NIPDAU Level-1-260C-UNLIM
SN74ALS273DWR ACTIVE SOIC DW 20 2000 Green (RoHS
& no Sb/Br) CU NIPDAU Level-1-260C-UNLIM
SN74ALS273DWRE4 ACTIVE SOIC DW 20 2000 Green (RoHS
& no Sb/Br) CU NIPDAU Level-1-260C-UNLIM
SN74ALS273DWRG4 ACTIVE SOIC DW 20 2000 Green (RoHS
& no Sb/Br) CU NIPDAU Level-1-260C-UNLIM
SN74ALS273N ACTIVE PDIP N 20 20 Pb-Free (RoHS) CU NIPDAU N / A for Pkg Type
SN74ALS273N3 OBSOLETE PDIP N 20 TBD Call TI Call TI
SN74ALS273NE4 ACTIVE PDIP N 20 20 Pb-Free (RoHS) CU NIPDAU N / A for Pkg Type
SN74ALS273NSR ACTIVE SO NS 20 2000 Green (RoHS
& no Sb/Br) CU NIPDAU Level-1-260C-UNLIM
SN74ALS273NSRE4 ACTIVE SO NS 20 2000 Green (RoHS
& no Sb/Br) CU NIPDAU Level-1-260C-UNLIM
SN74ALS273NSRG4 ACTIVE SO NS 20 2000 Green (RoHS
& no Sb/Br) CU NIPDAU Level-1-260C-UNLIM
SNJ54ALS273FK ACTIVE LCCC FK 20 1 TBD POST-PLATE N / A for Pkg Type
SNJ54ALS273J ACTIVE CDIP J 20 1 TBD A42 N / A for Pkg Type
SNJ54ALS273W ACTIVE CFP W 20 1 TBD Call TI N / A for Pkg Type
(1) The marketing status values are defined as follows:
ACTIVE: Product device recommended for new designs.
LIFEBUY: TI has announced that the device will be discontinued, and a lifetime-buy period is in effect.
NRND: Not recommended for new designs. Device is in production to support existing customers, but TI does not recommend using this part in a new design.
PACKAGE OPTION ADDENDUM
www.ti.com 5-Sep-2011
Addendum-Page 2
PREVIEW: Device has been announced but is not in production. Samples may or may not be available.
OBSOLETE: TI has discontinued the production of the device.
(2) Eco Plan - The planned eco-friendly classification: Pb-Free (RoHS), Pb-Free (RoHS Exempt), or Green (RoHS & no Sb/Br) - please check http://www.ti.com/productcontent for the latest availability
information and additional product content details.
TBD: The Pb-Free/Green conversion plan has not been defined.
Pb-Free (RoHS): TI's terms "Lead-Free" or "Pb-Free" mean semiconductor products that are compatible with the current RoHS requirements for all 6 substances, including the requirement that
lead not exceed 0.1% by weight in homogeneous materials. Where designed to be soldered at high temperatures, TI Pb-Free products are suitable for use in specified lead-free processes.
Pb-Free (RoHS Exempt): This component has a RoHS exemption for either 1) lead-based flip-chip solder bumps used between the die and package, or 2) lead-based die adhesive used between
the die and leadframe. The component is otherwise considered Pb-Free (RoHS compatible) as defined above.
Green (RoHS & no Sb/Br): TI defines "Green" to mean Pb-Free (RoHS compatible), and free of Bromine (Br) and Antimony (Sb) based flame retardants (Br or Sb do not exceed 0.1% by weight
in homogeneous material)
(3) MSL, Peak Temp. -- The Moisture Sensitivity Level rating according to the JEDEC industry standard classifications, and peak solder temperature.
Important Information and Disclaimer:The information provided on this page represents TI's knowledge and belief as of the date that it is provided. TI bases its knowledge and belief on information
provided by third parties, and makes no representation or warranty as to the accuracy of such information. Efforts are underway to better integrate information from third parties. TI has taken and
continues to take reasonable steps to provide representative and accurate information but may not have conducted destructive testing or chemical analysis on incoming materials and chemicals.
TI and TI suppliers consider certain information to be proprietary, and thus CAS numbers and other limited information may not be available for release.
In no event shall TI's liability arising out of such information exceed the total purchase price of the TI part(s) at issue in this document sold by TI to Customer on an annual basis.
OTHER QUALIFIED VERSIONS OF SN54ALS273, SN74ALS273 :
•Catalog: SN74ALS273
•Military: SN54ALS273
NOTE: Qualified Version Definitions:
•Catalog - TI's standard catalog product
•Military - QML certified for Military and Defense Applications
TAPE AND REEL INFORMATION
*All dimensions are nominal
Device Package
Type Package
Drawing Pins SPQ Reel
Diameter
(mm)
Reel
Width
W1 (mm)
A0
(mm) B0
(mm) K0
(mm) P1
(mm) W
(mm) Pin1
Quadrant
SN74ALS273DWR SOIC DW 20 2000 330.0 24.4 10.8 13.0 2.7 12.0 24.0 Q1
SN74ALS273NSR SO NS 20 2000 330.0 24.4 8.2 13.0 2.5 12.0 24.0 Q1
PACKAGE MATERIALS INFORMATION
www.ti.com 14-Jul-2012
Pack Materials-Page 1
*All dimensions are nominal
Device Package Type Package Drawing Pins SPQ Length (mm) Width (mm) Height (mm)
SN74ALS273DWR SOIC DW 20 2000 367.0 367.0 45.0
SN74ALS273NSR SO NS 20 2000 367.0 367.0 45.0
PACKAGE MATERIALS INFORMATION
www.ti.com 14-Jul-2012
Pack Materials-Page 2
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