DF2B7M2SL ESD Protection Diodes Silicon Epitaxial Planar DF2B7M2SL 1. Applications * ESD Protection Note: This product is designed for protection against electrostatic discharge (ESD) and is not intended for any other purpose, including, but not limited to, voltage regulation. 2. Packaging and Internal Circuit 1: Pin 1 2: Pin 2 SL2 ) 3. Absolute Maximum Ratings (Note) (Unless otherwise specified, Ta = 25 25 Characteristics Electrostatic discharge voltage (IEC61000-4-2)(Contact) Symbol Note Rating Unit VESD (Note 1) 12 kV 15 kV 40 W 2 A Electrostatic discharge voltage(IEC61000-4-2)(Air) Peak pulse power PPK Peak pulse current IPP (Note 2) Junction temperature Tj 150 Storage temperature Tstg -55 to 150 Note: Using continuously under heavy loads (e.g. the application of high temperature/current/voltage and the significant change in temperature, etc.) may cause this product to decrease in the reliability significantly even if the operating conditions (i.e. operating temperature/current/voltage, etc.) are within the absolute maximum ratings. Please design the appropriate reliability upon reviewing the Toshiba Semiconductor Reliability Handbook ("Handling Precautions"/"Derating Concept and Methods") and individual reliability data (i.e. reliability test report and estimated failure rate, etc). Note 1: According to IEC61000-4-2. Note 2: According to IEC61000-4-5. Start of commercial production 1 2014-10 2015-04-02 Rev.4.0 DF2B7M2SL ) 4. Electrical Characteristics (Unless otherwise specified, Ta = 25 25 VRWM: Working peak reverse voltage VBR: Reverse breakdown voltage IBR: Reverse breakdown current IR: Reverse current VC: Clamp voltage IPP: Peak pulse current RDYN: Dynamic resistance Fig. 4.1 Definitions of Electrical Characteristics Characteristics Working peak reverse voltage Reverse breakdown voltage Symbol Note Test Condition VRWM Min Typ. Max Unit 5 V VBR IBR = 1 mA 6 11 V Reverse current IR VRWM = 5 V 5 50 nA Clamp voltage VC (Note 1), (Note 3) IPP = 1 A 13 V IPP = 2 A 15 20 V Dynamic resistance Total capacitance RDYN (Note 2) 1 Ct (Note 3) VR = 0 V, f = 1 MHz 0.2 0.4 pF Note 1: Based on IEC61000-4-5 8/20 s pulse. Note 2: TLP parameter: Z0 = 50 , tp = 100 ns, tr = 300 ps, averaging window: t1 = 30 ns to t2 = 60 ns, extraction of dynamic resistance using a least-squares fit of TLP characteristics at IPP between 8 A to 16 A. Note 3: Guaranteed by design. 2 2015-04-02 Rev.4.0 DF2B7M2SL 5. Marking Fig. 5.1 Marking 6. Land Pattern Dimensions (for reference only) Fig. 6.1 Land Pattern Dimensions (Unit: mm) 3 2015-04-02 Rev.4.0 DF2B7M2SL 7. Characteristics Curves (Note) Note: Fig. 7.1 I - V Fig. 7.2 IR - VR Fig. 7.3 Ct - VR Fig. 7.4 Ct - f The above characteristics curves are presented for reference only and not guaranteed by production test, unless otherwise noted. 4 2015-04-02 Rev.4.0 DF2B7M2SL 8. Clamp Voltage VC - Peak Pulse Current (IPP) (Note) Fig. 8.1 VC - IPP Note: Fig. 8.2 Based on IEC61000-4-5 8/20 s pulse. (Ed.2) The above characteristics curves are presented for reference only and not guaranteed by production test, unless otherwise noted. 9. Insertion Loss (S21) (Note) Fig. 9.1 S21 - f Note: The above characteristics curves are presented for reference only and not guaranteed by production test, unless otherwise noted. 5 2015-04-02 Rev.4.0 DF2B7M2SL 10. ESD Clamp Waveform (Note) Fig. 10.1 +8 kV Fig. 10.2 -8 kV Fig. 10.3 IEC61000-4-2 (Contact) Note: The above characteristics curves are presented for reference only and not guaranteed by production test, unless otherwise noted. 6 2015-04-02 Rev.4.0 DF2B7M2SL Package Dimensions Unit: mm Weight: 0.2 mg (typ.) Package Name(s) TOSHIBA: 1-1AL1A Nickname: SL2 7 2015-04-02 Rev.4.0 DF2B7M2SL RESTRICTIONS ON PRODUCT USE * Toshiba Corporation, and its subsidiaries and affiliates (collectively "TOSHIBA"), reserve the right to make changes to the information in this document, and related hardware, software and systems (collectively "Product") without notice. * This document and any information herein may not be reproduced without prior written permission from TOSHIBA. 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