PRELIMINARY CY2DP818-2
1:8 Clock Fanout Buffer
Cypress Semiconductor Corporation • 198 Champion Court • San Jose,CA 95134-1709 • 408-943-2600
Document #: 38-07588 Rev. *A Revised October 22, 2008
Features
■Low voltage operation VDD = 3.3V
■1:8 fanout
■Single-input configurable for LVDS, LVPECL, or LVTTL
■8 pairs of LVPECL outputs with enable and disable
■Drives a 50 ohm load
■Low input capacitance
■Low output skew
■Low propagation delay typical (tpd < 4 ns)
■Industrial versions available
■Package available include: TSSOP
■Does not exceed Bellcore 802.3 standards
■Operation up to 350 MHz and 700 Mbps
Description
This Cypress series of network circuits is produced using
advanced 0.35 micron CMOS technology, achieving the
industry’s fastest logic.
The Cypress CY2DP818-2 fanout buffer features a single
LVDS or a single-ended LVTTL compatible input and eight
LVPECL output pairs.
Designed for data communications clock management appli-
cations, the large fanout from a single input reduces loading
on the input clock.
The CY2DP818-2 is ideal for both level translations from
single-ended to LVPECL and for the distribution of LVPECL
based clock signals.
The Cypress CY2DP818-2 has configurable input functions.
The input is user configurable through the Inconfig pin for
single ended or differential input.
Logic Block Diagram
INPUT
(LVPECL / LVDS / LVTTL)
OUTPUT
(LVPECL)
Q1A
Q1B
Q2A
Q2B
Q3A
Q3B
Q4A
Q4B
Q5A
Q5B
Q6A
Q6B
Q7A
Q7B
Q8A
Q8B
INPUT A
INPUT B
InConfig
EN1
EN2
EN3
EN4
EN5
EN6
EN7
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PRELIMINARY CY2DP818-2
Document #: 38-07588 Rev. *A Page 2 of 9
Pin Configuration
Figure 1. Pin Diagram - 38-Pin TSSOP
1
2
3
4
5
6
7
8
9
10
11
12
13
14
15
16
17
18
19
38
37
36
35
34
33
32
31
30
29
28
27
26
25
24
23
22
21
20
GND
VDD
Q1A
Q1B
Q2A
Q2B
Q3A
Q3B
Q4B
Q5A
Q5B
Q6A
Q6B
Q7A
Q7B
Q8A
Q8B
GND
Q4A
GND
VDD
GND
GND
VDD
InConfig
INPUT A
INPUT B
GND
GND
CY2DP818-2
VDD
EN1
EN2
EN3
EN5
EN6
EN7
VDD
EN4
Pin Description
Pin Number Pin Name Pin Standard Interface Description
1, 9,12,18,19,20,38 GND POWER Ground.
2,8,13,29,17 VDD POWER Power supply.
3,4,5,6,14,15,16 EN(1:7) LVTTL/LVCMOS The respective outputs are enabled when these
pins are pulled high. Outputs are disabled when
connected to GND. EN7 controls both Q7(A,B) and
Q8(A,B)
10,11 Input A, Input B Default: LVPECL/LDVS
Optional: LVTTL/LVCMOS
single pin
Differential input pair or single line. LVPECL/LVDS
default. See InConfig, below.
37, 36,35,34,
33,32,31, 30,
28,27,26,25,
24,23,22,21
Q1(A,B), Q2(A,B)
Q3(A,B), Q4(A,B)
Q5(A,B), Q6(A,B)
Q7(A,B), Q8(A,B)
LVPECL Differential outputs.
7 InConfig LVTTL/LVCMOS Converts inputs from the default
LVPECL/LVDS (logic = 0)
to LVTTL/LVCMOS (logic = 1)
See Input Receiver Configuration for Differential or
LVTTL/LVCMOS table, Figure 6 and Figure 7 for
additional information
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PRELIMINARY CY2DP818-2
Document #: 38-07588 Rev. *A Page 3 of 9
Power Supply Characteristics
Parameter Description Test Conditions Min Typ Max Unit
ICCD Dynamic Power Supply Current VDD = Max.
Input toggling 50% Duty Cycle, Outputs Open
1.5 2.0 mA/
MHz
IC Total Power Supply Current VDD = Max.
Input toggling 50% Duty Cycle, Outputs 50 ohms,
fL=100 MHz
350 mA
IC Core Core Current when Output Loads
are Disabled
VDD = Max.
Input toggling 50% Duty Cycle, Outputs Disabled,
not connected to VTT fL = 100 MHz
50 mA
Input Receiver Configuration for Differential or LVTTL/LVCMOS
INCONFIG Pin 7
Binary Value Input Receiver Family Input Receiver Type
1 LVTTL in LVCMOS Single ended, non inverting, inverting, void of bias resistors
0 LVDS Low voltage differential signaling
LVPECL Low voltage pseudo (positive) emitter coupled logic
Function Control of the TTL Input Logic used to Accept or Invert the Input Signal
LVTTL/LVCMOS Input Logic
Input Condition Input Logic Output Logic Q Pins, Q1A or Q1
Ground Input B (–) Pin 11
Input A (+) Pin 10 Input True
VDD Input B (–) Pin 11
Input A (+) Pin 10 Input Invert
Ground Input A (+) Pin 10
Input B (–) Pin 11 Input Invert
VDD Input A (+) Pin 10
Input B (–) Pin 11 Input True
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PRELIMINARY CY2DP818-2
Document #: 38-07588 Rev. *A Page 4 of 9
Absolute Maximum Conditions
Parameter Description Condition Min Max Unit
VDD DC Supply Voltage Inputs and VCC –0.3 4.6 V
VDD DC Operating Voltage Outputs –0.3 VDD + 0.3 V
VIN DC Input Voltage Relative to VSS, with or VDD applied –0.3 VDD + 0.3 V
VOUT DC Output Voltage Relative to VSS –0.3 VDD + 0.9 V
VTT Output Termination Voltage – VDD ÷ 2V
TSTemperature, Storage Non Functional –65 +150 °C
TATemperature, Operating
Ambient
Commercial Functional 0 70 °C
Industrial Functional –40 +85
Multiple Supplies: The voltage on any input or I/O pin cannot exceed the power pin during power up. Power supply sequencing is
NOT required.
DC Electrical Specifications
3.3V – LVDS Input at VDD = 3.3V ± 5%, TA = 0°C to 70°C or –40°C to 85°C
Parameter Description Conditions Min Typ Max Unit
VID Magnitude of Differential Input Voltage 100 600 mV
VIC Common Mode of Differential Input
VoltageIVIDI (minimum and maximum)
IVIDI/2 2.4–(IVIDI/2) V
IIH Input High Current VDD = Max. VIN = VDD – ±10 ± 20 μA
IIL Input Low Current VDD = Max. VIN = VSS – ±10 ± 20 μA
3.3V – LVPECL Input at VDD = 3.3V ± 5%, TA = 0°C to 70°C or –40°C to 85°C
Parameter Description Conditions Min Typ Max Unit
VID Differential Input Voltage p-p Guaranteed Logic High Level 400 – 2600 mV
VIH Input High Voltage Guaranteed Logic High Level 2.15 – 2.4 V
VIL Input Low Voltage Guaranteed Logic Low Level 1.5 – 1.8 V
IIH Input High Current VDD = Max. VIN = VDD –±10±20μA
IIL Input Low Current VDD = Max. VIN = VSS –±10±20μA
VCM Common-mode Voltage 1650 – 2250 mV
3.3V – LVTTL/LVCMOS Input at VDD = 3.3V ± 5%, TA = 0°C to 70°C or –40°C to 85°C
Parameter Description Conditions Min Typ Max Units
VIH Input High Voltage Guaranteed Logic High Level 2 – – V
VIL Input Low Voltage Guaranteed Logic Low Level – – 0.8 V
IIH Input High Current VDD = Max VIN = 2.7V – – 1 μA
IIL Input Low Current VDD = Max VIN = 0.5V – – –1 μA
IIInput High Current VDD = Max, VIN = VDD (Max)
VIK Clamp Diode Voltage VDD = Min, IIN = –18 mA – –0.7 –1.2 V
VHInput Hysteresis[1] –80 mV
Note
1. Guaranteed but not tested.
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PRELIMINARY CY2DP818-2
Document #: 38-07588 Rev. *A Page 5 of 9
Figure 2. Driver Design
3.3V – LVPECL Output at VDD = 3.3V ± 5%, TA = 0°C to 70°C or –40°C to 85°C
Parameter Description Conditions Min Typ Max Unit
VOD Driver Differential Output Voltage p-p VDD = Min, VIN = VIH or VIL RL = 50 ohm 1000 – 3600 mV
ΔVOC Driver common-Mode Variation p-p VDD = Min, VIN = VIH or VIL RL = 50 ohm – – 300 mV
Rise Time Differential 20% to 80% CL–10 pF RL and CL to
GND
RL = 50 ohm 300 1200 ps
Fall Time
VOH Output High Voltage VDD = Min, VIN = VIH or VIL IOH = –12 mA 2.1 – 3.0 V
VOL Output Low Voltage VDD = Min, VIN = VIH or VIL
User-defined by VTT RTT.
0.8 – 1.3 V
IOS Short Circuit Current VDD = Max, VOUT = GND – – –150 mA
AC Switching Characteristics
(at VDD = 3.3V ± 5%, TA = 0°C to 70°C or –40°C to 85°C)
Parameter Description Conditions Min Typ Max Unit
tPLH Propagation Delay – Low to High VOD = 100
mV
345ns
tPHL Propagation Delay – High to Low 3 4 5 ns
TPE Enable (EN) to Functional Operation – – 6 ns
TPD Functional Operation to Disable – – 5 ns
tSK(0) Output Skew: Skew between outputs of the same package (in phase) – – 0.2 ns
tSK(p) Pulse Skew: Skew between opposite transitions of the same output (tPHL–tPLH)–0.2 ns
tSK(t) Package Skew: Skew between outputs of different packages at the
same power supply voltage, temperature, and package type. Same
input signal level and output load.
VID = 100 mV – – 1 ns
High Frequency Parametrics
Parameter Description Conditions Min Typ Max Unit
Fmax Maximum Frequency
VDD = 3.3V
45% to 55% duty cycle
Standard load circuit
– – 350 MHz
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PRELIMINARY CY2DP818-2
Document #: 38-07588 Rev. *A Page 6 of 9
Figure 3. Differential Receiver to Driver Propagation Delay and Driver Transition Time[2,3,4,5]
Figure 4. Test Circuit and Voltage Definitions for the Driver Common-Mode Output Voltage[2,3,4,5]
80%
20%
0V Differential
QXA - QXB
tR tF
1.4 V
1.0 V
1.4 V
1.0 V
0V Differential
0V Differential
1.2 V CM
1.2 V C M
INA
INB
QXA
QXB
TPLH TPHL
TPA
TPC
TPB
50
50
GND
150
150
Standard Termination
Pulse
Generator
A
B
10pF VDD-2V
2.0V
1.6V
VI(A)
VI(B)
Next Device
VODVOC
TPA
TPC
TPB
50
50
GND
150
150
Standard Termination
Pulse
Generator
A
B
Notes
2. All input pulses are supplied by a frequency generator with the following characteristics: tR and tF ≤ 1 ns; pulse rerate = 50 Mpps; pulse width = 10 ± 0.2 ns.
3. RL = 50 ohm ± 1%; Zline = 50 ohm 6”.
4. CL includes instrumentation and fixture capacitance within 6” of the DUT.
5. TPA and B are used for prop delay and Rise/Fall measurements. TPC is used for VOC measurements only and is otherwise connected to VDD – 2.
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PRELIMINARY CY2DP818-2
Document #: 38-07588 Rev. *A Page 7 of 9
Figure 5. Test Circuit and Voltage Definitions for the Differential Output Signal[2,3,4,5]
Figure 6. LVTTL/LVCMOS[6] Figure 7. LVDS/LVPECL[6]
0.0V
100%
80%
20%
0%
tRtF
1.4V
1.0V
VI(A)
VI(B)
TPA
TPC
TPB
50
50
GND
150
150
Standard Termination
Pulse
Generator
A
B
10pF VDD-2V
1
InConfig
LVCMOS / LVTTL
LVTTL/LVCMOS
INPUT A
INPUT B
GND
InConfig
LVPECL &
LVDS
LVDS/LVPECL0
Ordering Information
Part Number Package Type Product Flow
CY2DP818ZI-2 38-Pin TSSOP Industrial, –40° to 85°C
CY2DP818ZI-2T 38-Pin TSSOP–Tape and Reel Industrial, –40° to 85°C
CY2DP818ZC-2 38-Pin TSSOP Commercial, 0°C to 70°C
CY2DP818ZC-2T 38-Pin TSSOP–Tape and Reel Commercial, 0°C to 70°C
Pb Free Devices
CY2DP818ZXI-2 38-Pin TSSOP Industrial, –40° to 85°C
CY2DP818ZXI-2T 38-Pin TSSOP–Tape and Reel Industrial, –40° to 85°C
CY2DP818ZXC-2 38-Pin TSSOP Commercial, 0°C to 70°C
CY2DP818ZXC-2T 38-Pin TSSOP–Tape and Reel Commercial, 0°C to 70°C
Note
6. LVPECL or LVDS differential input value.
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Document #: 38-07588 Rev. *A Revised October 22, 2008 Page 9 of 9
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PRELIMINARY CY2DP818-2
© Cypress Semiconductor Corporation, 2003-2008. The information contained herein is subject to change without notice. Cypress Semiconductor Corporation assumes no responsibility for the use of
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Disclaimer: CYPRESS MAKES NO WARRANTY OF ANY KIND, EXPRESS OR IMPLIED, WITH REGARD TO THIS MATERIAL, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED WARRANTIES
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assume any liability arising out of the application or use of any product or circuit described herein. Cypress does not authorize its products for use as critical components in life-support systems where
a malfunction or failure may reasonably be expected to result in significant injury to the user. The inclusion of Cypress’ product in a life-support systems application implies that the manufacturer
assumes all risk of such use and in doing so indemnifies Cypress against all charges.
Use may be limited by and subject to the applicable Cypress software license agreement.
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Document Title: CY2DP818-2 1:8 Clock Fanout Buffer
Document Number: 38-07588
Rev. ECN No. Submission
Date
Orig. of
Change Description of Change
** 129879 11/07/03 RGL New Data Sheet
*A 2595534 10/23/08 CXQ/PYRS Removed “Preliminary”, added Pb-free devices to Ordering Information
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