LMV641MFE/NOPB - Texas Instruments

180

100 10k 1M 100M

FREQUENCY (Hz)

-60

GAIN (dB)

10M100k

150

120

-30

180

-60

150

120

-30

PHASE (°)

GAIN

PHASE

V+ = +6V

V- = -6V

RL = 10 k:

CL = 20 pF

-400 -300 -200 -100 0 100 200 300 400

PERCENTAGE (%)

OFFSET VOLTAGE (PV)

18 V+ = +5V

V- = -5V

VCM = 0V

TA = 25°C

UNITS TESTED = 12,000

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An IMPORTANT NOTICE at the end of this data sheet addresses availability, warranty, changes, use in safety-critical applications,

intellectual property matters and other important disclaimers. PRODUCTION DATA.

LMV641

SNOSAW3D –SEPTEMBER 2007–REVISED AUGUST 2016

LMV641 10-MHz, 12-V, Low-Power Amplifier

1 Features

1• Specified for 2.7-V, and ±5-V Performance

• Low Power Supply Current: 138 µA

• High Unity Gain Bandwidth: 10 MHz

• Max Input Offset Voltage: 500 µV

• CMRR: 120 dB

• PSRR: 105 dB

• Input Referred Voltage Noise: 14 nV/√Hz

• 1/f Corner Frequency: 4 Hz

• Output Swing With 2-kΩLoad 40 mV from Rail

• Total Harmonic Distortion: 0.002% at 1 kHz, 2 kΩ

• Temperature Range −40°C to 125°C

2 Applications

• Portable Equipment

• Battery-Powered Systems

• Sensors and Instrumentation

3 Description

The LMV641 is a low-power, wide-bandwidth

operational amplifier with an extended power supply

voltage range of 2.7 V to 12 V.

The device features 10 MHz of gain bandwidth

product with unity gain stability on a typical supply

current of 138 µA. Other key specifications are a

PSRR of 105 dB, CMRR of 120 dB, VOS of 500 µV,

input referred voltage noise of 14 nV/√Hz, and a THD

of 0.002%. This amplifier has a rail-to-rail output

stage and a common mode input voltage, which

includes the negative supply.

The LMV641 device operates over a temperature

range of −40°C to +125°C and is offered in the board-

space-saving 5-Pin SC70, SOT-23, and 8-Pin SOIC

packages.

Device Information(1)

PART NUMBER PACKAGE BODY SIZE (NOM)

LMV641 SOIC (8) 4.90 mm × 3.91 mm

SOT-23 (5) 2.90 mm × 1.60 mm

SC70 (5) 2.00 mm × 1.25 mm

(1) For all available packages, see the orderable addendum at

the end of the data sheet.

Offset Voltage Distribution Open Loop Gain and Phase vs Frequency

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Table of Contents

1 Features.................................................................. 1

2 Applications ........................................................... 1

3 Description............................................................. 1

4 Revision History..................................................... 2

5 Pin Configuration and Functions......................... 3

6 Specifications......................................................... 4

6.1 Absolute Maximum Ratings ..................................... 4

6.2 ESD Ratings.............................................................. 4

6.3 Recommended Operating Conditions....................... 4

6.4 Thermal Information.................................................. 4

6.5 DC Electrical Characteristics: 2.7 V ......................... 5

6.6 DC Electrical Characteristics: 10 V........................... 6

6.7 Typical Characteristics.............................................. 8

7 Detailed Description............................................ 14

7.1 Overview................................................................. 14

7.2 Functional Block Diagram....................................... 14

7.3 Feature Description................................................. 14

7.4 Device Functional Modes........................................ 15

8 Application and Implementation ........................ 17

8.1 Application Information............................................ 17

8.2 Typical Applications ................................................ 17

9 Power Supply Recommendations...................... 23

10 Layout................................................................... 23

10.1 Layout Guidelines ................................................. 23

10.2 Layout Example .................................................... 23

11 Device and Documentation Support................. 24

11.1 Device Support .................................................... 24

11.2 Documentation Support ....................................... 24

11.3 Receiving Notification of Documentation Updates 24

11.4 Community Resource............................................ 24

11.5 Trademarks........................................................... 24

11.6 Electrostatic Discharge Caution............................ 24

11.7 Glossary................................................................ 24

12 Mechanical, Packaging, and Orderable

Information........................................................... 25

4 Revision History

NOTE: Page numbers for previous revisions may differ from page numbers in the current version.

Changes from Revision C (February 2013) to Revision D Page

• Added ESD Ratings table, Feature Description section, Device Functional Modes,Application and Implementation

section, Power Supply Recommendations section, Layout section, Device and Documentation Support section, and

Mechanical, Packaging, and Orderable Information section.................................................................................................. 1

• Moved Package thermal resistance (RθJA) rows from Recommended Operating Conditions to Thermal Information........... 4

Changes from Revision B (February 2013) to Revision C Page

• Changed layout of National Semiconductor Data Sheet to TI Format................................................................................... 1

V+

4 5

N/C

VIN-

VIN+

V-

N/C

VOUT

N/C

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5 Pin Configuration and Functions

DBV and DCK Packages

5-Pin SOT-23 and SC70

Top View D Package

8-Pin SOIC

Top View

(1) I = input; O = output; P = power

Pin Functions

PIN TYPE(1) DESCRIPTION

NAME SOT-23 SC70 SOIC

VIN+ 3 3 3 I Noninverting Input

VIN- 4 4 2 I Inverting Input

VOUT 1 1 6 O Output

V+5 5 7 P Positive supply input

V–2 2 4 P Supply negative input

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(1) Absolute Maximum Ratings indicate limits beyond which damage to the device may occur. Operating Ratings indicate conditions for

which the device is intended to be functional, but specific performance is not guaranteed. For ensured specifications and the test

conditions, see the Electrical Characteristics Tables.

(2) If Military/Aerospace specified devices are required, contact the Texas Instruments Sales Office / Distributors for availability and

specifications.

(3) The maximum power dissipation is a function of TJ(MAX, RθJA. The maximum allowable power dissipation at any ambient temperature is

PD= (TJ(MAX) - TA)/ RθJA. All numbers apply for packages soldered directly onto a PC board.

6 Specifications

6.1 Absolute Maximum Ratings

over operating free-air temperature range (unless otherwise noted)(1)(2)

MIN MAX UNIT

Differential input VID ±0.3 ±0.3 V

Supply voltage (VS= V+- V−) 13.2 V

Input and output pin voltage (V−−0.3) V++0.3 V

Junction temperature (3) 150 °C

Storage temperature, Tstg –65 150 °C

(1) Human Body Model, applicable std. MIL-STD-883, Method 3015.7.

6.2 ESD Ratings VALUE UNIT

V(ESD) Electrostatic discharge Human-body model (HBM), (1) ±2000 V

Machine model (MM) ±200

(1) The maximum power dissipation is a function of TJ(MAX, RθJA. The maximum allowable power dissipation at any ambient temperature is

PD= (TJ(MAX) - TA)/ RθJA. All numbers apply for packages soldered directly onto a PC board.

6.3 Recommended Operating Conditions

over operating free-air temperature range (unless otherwise noted) MIN NOM MAX UNIT

Temperature (1) –40 125 °C

Supply voltage (VS= V+– V−) 2.7 12 V

(1) For more information about traditional and new thermal metrics, see the Semiconductor and IC Package Thermal Metrics application

report.

(2) The maximum power dissipation is a function of TJ(MAX, RθJA. The maximum allowable power dissipation at any ambient temperature is

PD= (TJ(MAX) - TA)/ RθJA. All numbers apply for packages soldered directly onto a PC board.

6.4 Thermal Information

THERMAL METRIC(1) LMV641

UNITDBV (SOT-23) DCK (SC70) D (SOIC)

5 PINS 5 PINS 8 PINS

RθJA(2) Junction-to-ambient thermal resistance 325 456 166 °C/W

RθJC(top) Junction-to-case (top) thermal resistance 178.1 121.8 93.6 °C/W

RθJB Junction-to-board thermal resistance 60.8 68.9 90.9 °C/W

ψJT Junction-to-top characterization parameter 57.7 5.3 38.4 °C/W

ψJB Junction-to-board characterization parameter 60.2 68.1 90.4 °C/W

RθJC(bot) Junction-to-case (bottom) thermal resistance n/a n/a n/a °C/W

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(1) Limits are 100% production tested at 25°C. Limits over the operating temperature range are specified through correlations using

Statistical Quality Control (SQC) method.

(2) Typical values represent the most likely parametric norm as determined at the time of characterization. Actual typical values may vary

over time and also depend on the application and configuration. The typical values are not tested and are not specified on shipped

production material.

(3) Positive current corresponds to current flowing into the device.

(4) The part is not short-circuit protected and is not recommended for operation with low resistive loads. Typical sourcing and sinking output

current curves are provided in Typical Characteristics and should be consulted before designing for heavy loads.

6.5 DC Electrical Characteristics: 2.7 V

Unless otherwise specified, all limits are specified for TA= 25°C, V+= 2.7 V, V−= 0 V, VO= VCM = V+/2, and RL> 1 MΩ.

PARAMETER TEST CONDITIONS MIN

(1) TYP

(2) MAX

(1) UNIT

VOS Input offset voltage TA= 25°C 30 500 µV

Temperature extremes 750

TC VOS Input offset average drift 0.1 µV/°C

IBInput bias current TA= 25°C (3) 75 95 nA

Temperature extremes 110

IOS Input offset current 0.9 5 nA

CMRR Common-mode rejection

ratio 0 V ≤VCM ≤1.7 V TA= 25°C (3) 89 114 dB

Temperature extremes 84

PSRR Power supply rejection ratio

2.7 V ≤V+≤10 V, VCM =

0.5 TA= 25°C (3) 94.5 105

Temperature extremes 92.5

2.7 V ≤V+≤12 V, VCM =

0.5 TA= 25°C (3) 94 100

Temperature extremes 92

CMVR Input common-mode

voltage range CMRR ≥80 dB TA= 25°C (3) 0 1.8 V

CMRR ≥68 dB Temperature extremes 0 1.8

AVOL Large signal voltage gain

0.3 V ≤VO≤2.4 V, RL= 2 kΩto V+/2 82 88

0.4 V ≤VO≤2.3 V, RL= 2 kΩto V+/2 78

0.3 V ≤VO≤2.4 V, RL=

10 kΩto V+/2 TA= 25°C (3) 86 98

0.4 V ≤VO≤2.3 V, RL=

10 kΩto V+/2 Temperature extremes 82

Output swing high

RL= 2 kΩto V+/2, VIN =

100 mV TA= 25°C (3) 42 58

mV from

rail

Temperature extremes 68

RL= 10 kΩto V+/2, VIN =

100 mV TA= 25°C (3) 22 35

Temperature extremes 40

Output swing low

RL= 2 kΩto V+/2, VIN =

100 mV TA= 25°C (3) 38 48

Temperature extremes 58

RL= 10 kΩto V+/2, VIN =

100 mV 18 30

IOUT Sourcing and sinking output

current VIN_DIFF = 100 mV to VO

= V+/2 (4) Sourcing 22 mA

Sinking 25

ISSupply current TA= 25°C (3) 138 170 µA

Temperature extremes 220

SR Slew rate AV= 1, VO= 1 VPP Rising (10% to 90%) 2.3 V/µs

Falling (90% to 10%) 1.6

GBW Gain bandwidth product 10 MHz

enInput-referred voltage noise f = 1 kHz 14 nV/√Hz

inInput-referred current noise f = 1 kHz 0.15 pA/√Hz

THD Total harmonic distortion f = 1 kHz, AV= 2, RL= 2 kΩ0.014%

LMV641

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Product Folder Links: LMV641

(1) Limits are 100% production tested at 25°C. Limits over the operating temperature range are specified through correlations using

Statistical Quality Control (SQC) method.

(2) Typical values represent the most likely parametric norm as determined at the time of characterization. Actual typical values may vary

over time and also depend on the application and configuration. The typical values are not tested and are not specified on shipped

production material.

(3) Positive current corresponds to current flowing into the device.

(4) The part is not short-circuit protected and is not recommended for operation with low resistive loads. Typical sourcing and sinking output

current curves are provided in Typical Characteristics and should be consulted before designing for heavy loads.

6.6 DC Electrical Characteristics: 10 V

Unless otherwise specified, all limits are specified for TA= 25°C, V+= 10 V, V−= 0 V,VO= VCM = V+/2, and RL> 1 MΩ.

PARAMETER TEST CONDITIONS MIN

(1) TYP

(2) MAX

(1) UNIT

VOS Input offset voltage TA= 25°C (3) 5 500 µV

Temperature extremes 750

TC VOS Input offset average drift 0.1 µV/°C

IBInput bias current (3) TA= 25°C (3) 70 90 nA

Temperature

extremes 105

IOS Input offset current 0.7 5 nA

CMRR Common-mode rejection

ratio 0 V ≤VCM ≤9 V TA= 25°C (3) 94 120 dB

Temperature

extremes 90

PSRR Power supply rejection

ratio

2.7 V ≤V+≤10 V, VCM = 0.5

TA= 25°C (3) 94.5 105

Temperature

extremes 92.5

2.7 V ≤V+≤12 V, VCM = 0.5

TA= 25°C (3) 94 100

Temperature

extremes 92

CMVR Input common-mode

voltage range

CMRR ≥80 dB TA= 25°C (3) 0 9.1 V

CMRR ≥76 dB Temperature

extremes 0 9.1

AVOL Large signal voltage gain

0.3 V ≤VO≤9.7 V, RL= 2

kΩto V+/2

0.4 V ≤VO≤9.6 V, RL= 2

kΩto V+/2

TA= 25°C (3) 90 99

Temperature

extremes 85

0.3 V ≤VO≤9.7 V, RL= 10

kΩto V+/2

0.4 V ≤VO≤9.6 V, RL= 10

kΩto V+/2

TA= 25°C (3) 97 104

Temperature

extremes 92

Output Swing High

RL= 2 kΩto V+/2, VIN = 100

TA= 25°C (3) 68 95

mV from

rail

Temperature

extremes 125

RL= 10 kΩto V+/2, VIN = 100

TA= 25°C (3) 37 55

Temperature

extremes 65

Output Swing Low

RL= 2 kΩto V+/2, VIN = 100

TA= 25°C (3) 65 90

Temperature

extremes 110

RL= 10 kΩto V+/2, VIN = 100

TA= 25°C (3) 32 42

Temperature

extremes 52

IOUT Sourcing and sinking

output current VIN_DIFF = 100 mV

to VO= V+/2 (4) Sourcing 26 mA

Sinking 112

ISSupply current TA= 25°C (3) 158 190 µA

Temperature extremes 240

SR Slew rate AV= 1, VO= 2 V to 8 VPP Rising (10% to 90%) 2.6 V/µs

Falling (90% to 10%) 1.6

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DC Electrical Characteristics: 10 V (continued)

Unless otherwise specified, all limits are specified for TA= 25°C, V+= 10 V, V−= 0 V,VO= VCM = V+/2, and RL> 1 MΩ.

PARAMETER TEST CONDITIONS MIN

(1) TYP

(2) MAX

(1) UNIT

GBW Gain bandwidth product 10 MHz

enInput-referred voltage

noise f = 1 kHz 14 nV/√Hz

inInput-referred current

noise f = 1 kHz 0.15 pA/√Hz

THD Total harmonic distortion f = 1 kHz, AV= 2, RL= 2 kΩ0.002%

0 1 23 4 5 67 8 9

-50

-40

-30

-20

-10

OFFSET VOLTAGE (PV)

VCM (V)

-40°C

25°C

125°C

V+ = +10V

V- = 0V

-50

-40

-30

-20

-10

012 3 4 5 6 7 8 910 11

VCM (V)

OFFSET VOLTAGE (PV)

-40°C

25°C

125°C

V+ = +12V

V- = 0V

0 0.2 0.4 0.6 0.8 1 1.2 1.4 1.6 1.8

-100

-90

-80

-70

-60

-50

-40

-30

-20

-10

OFFSET VOLTAGE (PV)

VCM (V)

V+ = +2.7V

V- = 0V

-40°C

25°C

125°C

0 0.5 1 1.5 2 2.5 3 3.5 4

-50

OFFSET VOLTAGE (PV)

VCM (V)

-40

-30

-20

-10

-40°C

25°C

125°C

V+ = +5V

V- = 0V

2 3 4 5 6 7 8 9 10 11 12

-100

-80

-60

-40

-20

OFFSET VOLTAGE (PV)

SUPPLY VOLTAGE (V)

-40°C

25°C

125°C

2 3 4 5 6 7 8 9 10 11 12

100

120

140

160

180

200

220

SUPPLY CURRENT (PA)

SUPPLY VOLTAGE (V)

125°C

25°C

-40°C

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6.7 Typical Characteristics

Unless otherwise specified, TA= 25°C, V+= 10 V, V−= 0 V, VCM = VS/2.

Figure 1. Supply Current vs Supply Voltage Figure 2. Offset Voltage vs Supply Voltage

Figure 3. Offset Voltage vs VCM Figure 4. Offset Voltage vs VCM

Figure 5. Offset Voltage vs VCM Figure 6. Offset Voltage vs VCM

0 1 23 4 5 67 8 9

100

IBIAS (nA)

VCM (V)

-40°C

25°C

125°C

V+ = +10V

V- = 0V

0 0.2 0.4 0.6 0.8 1 1.2 1.4 1.6 1.8

100

IBIAS (nA)

VCM (V)

V+ = +2.7V

V- = 0V

125°C

25°C

-40°C

10 100 1k 10k 100k 1M 10M

FREQUENCY (Hz)

100

120

140

160

CMRR (dB)

V+ = 5V

V- = 5V

RL = 1 k:

130

10 1k 100k 10M

FREQUENCY (Hz)

-10

PSRR (dB)

1M10k

100

110

+PSRR

V+ = +5V

V- = -5V

+PSRR

V+ = +1.35V

V- = -1.35V

-PSRR

V+ = +1.35V

V- = -1.35V

-PSRR

V+ = +5V

V- = -5V

-400 -300 -200 -100 0 100 200 300 400

PERCENTAGE (%)

OFFSET VOLTAGE (PV)

18 V+ = +1.35V

V- = -1.35V

VCM = 0V

TA = 25°C

UNITS TESTED = 12,000

-400 -300 -200 -100 0 100 200 300 400

PERCENTAGE (%)

OFFSET VOLTAGE (PV)

18 V+ = +5V

V- = -5V

VCM = 0V

TA = 25°C

UNITS TESTED = 12,000

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Typical Characteristics (continued)

Unless otherwise specified, TA= 25°C, V+= 10 V, V−= 0 V, VCM = VS/2.

Figure 7. Offset Voltage Distribution Figure 8. Offset Voltage Distribution

Figure 9. CMRR vs Frequency Figure 10. PSRR vs Frequency

Figure 11. Input Bias Current vs VCM Figure 12. Input Bias Current vs VCM

10 1k 100k 10M

FREQUENCY (Hz)

0.01

1000

1M10k

100

0.1

ZOUT (:)

V+ = +5V

V- = -5V

AV = +1

0.10 10 1k 100k

FREQUENCY (Hz)

100

1000

10k100

VOLTAGE NOISE (nV/

Hz)

NOISE VOLTAGE

180

100 10k 1M 100M

FREQUENCY (Hz)

-60

GAIN (dB)

10M100k

150

120

-30

180

-60

150

120

-30

PHASE (°)

GAIN

PHASE

RL = 2 k:

RL = 10 k:

V+ = +6V

V- = -6V

CL = 20 pF RL = 2 k:

RL = 10 k:

180

100 10k 1M 100M

FREQUENCY (Hz)

-60

GAIN (dB)

10M100k

150

120

-30

180

-60

150

120

-30

PHASE (°)

GAIN

PHASE

RL = 2 k:

CL = 20 pF

V+ = +5V

V- = -5V

V+ = +1.35V

V- = -1.35V

180

100 10k 1M 100M

FREQUENCY (Hz)

-60

GAIN (dB)

10M100k

150

120

-30

180

-60

150

120

-30

PHASE (°)

GAIN

PHASE

CL = 20 pF

CL = 100 pF

CL = 50 pF

CL = 100 pF

CL = 50 pF

V+ = +1.35V

V- = -1.35V

RL = 2 k:

180

100 10k 1M 100M

FREQUENCY (Hz)

-60

GAIN (dB)

10M100k

150

120

-30

180

-60

150

120

-30

PHASE (°)

GAIN

PHASE

CL = 20 pF

CL = 100 pF

CL = 50 pF

CL = 100 pF

CL = 50 pF

V+ = +5V

V- = -5V

RL = 2 k:

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Typical Characteristics (continued)

Unless otherwise specified, TA= 25°C, V+= 10 V, V−= 0 V, VCM = VS/2.

Figure 13. Open-Loop Gain and Phase With Capacitive Load Figure 14. Open-Loop Gain and Phase With Capacitive Load

Figure 15. Open-Loop Gain and Phase With Resistive Load Figure 16. Open-Loop Gain and Phase With Supply Voltage

Figure 17. Input Referred Noise Voltage vs Frequency Figure 18. Close Loop Output Impedance vs Frequency

2 3 4 5 6 7 8 9 10 11 12

ISOURCE (mA)

SUPPLY VOLTAGE (V)

VOUT = V+/2

25°C

-40°C

125°C

23 4 5 6 7 8 9 10

SUPPLY VOLTAGE (V)

100

120

ISINK (mA)

125°C

25°C

-40°C

VOUT = V+/2

0.001 0.01 0.1 1 10

VOUT (V)

0.001

0.01

0.1

THD+N (%)

V+ = +1.35V

V- = -1.35V

VIN = 1 kHz SINE WAVE

AV = +2

RL = 2 k:

RL = 100 k:

0.001 0.01 0.1 1 10

VOUT (V)

0.001

0.01

0.1

THD+N (%)

V+ = +5V

V- = -5V

VIN = 1 kHz SINE WAVE

AV = +2

RL = 2 k:

RL = 10 k:

10 100 1k 10k 100k

FREQUENCY (Hz)

0.001

0.01

0.1

THD+N (%)

V+ = +1.35V

V- = -1.35V

VIN = 1 VPP

AV = +2

RL = 2 k:

RL = 10 k:

10 100 1k 10k 100k

FREQUENCY (Hz)

0.0001

0.001

0.01

0.1

THD+N (%)

V+ = +5V

V- = -5V

VIN = 1 VPP

AV = +2 RL = 2 k:

RL = 10 k:

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Typical Characteristics (continued)

Unless otherwise specified, TA= 25°C, V+= 10 V, V−= 0 V, VCM = VS/2.

Figure 19. THD+N vs Frequency Figure 20. THD+N vs Frequency

Figure 21. THD+N vs VOUT Figure 22. THD+N vs VOUT

Figure 23. Sourcing Current vs Supply Voltage Figure 24. Sinking Current vs Supply Voltage

-30

-25

-20

-15

-10

-5

VOUT (mV)

TIME (Ps)

020 40 60 70 80

CL = 125 pF, AV = +1

VIN = 20 mVPP, 20 kHz

V+ = +5V

V- = -5V

0 20 40 60 80 100

TIME (Ps)

-15

-10

-5

VOUT (mV)

-20

30 CL = 15 pF, AV = +1

VIN = 20 mVPP, 20 kHz

V+ = +5V

V- = -5V

0 1 2 3 4 5 6 7 8 9 10

ISOURCE (mA)

VOUT FROM RAIL (V)

V+ = +5V

V- = -5V 25°C

-40°C

125°C

0 20 40 60 80 100

-1.5

-1

-0.5

0.5

1.5

VOUT (mV)

TIME (Ps)

V+ = +5V

V- = -5V

CL = 15 pF, AV = +1

VIN = 2 VPP, 20 kHz

0 0.5 1 1.5 2 2.5

VOUT FROM RAIL (V)

ISOURCE (mA)

V+ = +1.35V

V- = -1.35V

125°C

25°C

-40°C

00.5 11.5 22.5

VOUT FROM RAIL (V)

ISINK (mA)

125°C

25°C

-40°C

V+ = +1.35V

V- = -1.35V

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Typical Characteristics (continued)

Unless otherwise specified, TA= 25°C, V+= 10 V, V−= 0 V, VCM = VS/2.

Figure 25. Sourcing Current vs VOUT Figure 26. Sinking Current vs VOUT

Figure 27. Sourcing Current vs VOUT Figure 28. Large-Signal Transient

Figure 29. Small-Signal Transient Response Figure 30. Small-Signal Transient Response

SUPPLY VOLTAGE (V)

23 4 5 6 7 8 9 10

0.5

1.5

2.5

SLEW RATE (V/Ps)

RL = 1 M:

CL = 20 pF

FALLING

RISING

2 3 4 5 6 7 8 9 10 11 12

VOUT FROM RAIL (mV)

SUPPLY VOLTAGE (V)

125°C 25°C

-40°C

RL = 10 k:

2 3 4 5 6 7 8 9 10 11 12

VOUT FROM RAIL (mV)

SUPPLY VOLTAGE (V)

125°C

25°C

-40°C

RL = 10 k:

2 3 4 5 6 7 8 9 10 11 12

100

VOUT FROM RAIL (mV)

SUPPLY VOLTAGE (V)

125°C

25°C

-40°C

RL = 2 k:

2 3 4 5 6 7 8 9 10 11 12

100

VOUT FROM RAIL (mV)

SUPPLY VOLTAGE (V)

125°C

25°C

-40°C

RL = 2 k:

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Typical Characteristics (continued)

Unless otherwise specified, TA= 25°C, V+= 10 V, V−= 0 V, VCM = VS/2.

Figure 31. Output Swing High vs Supply Voltage Figure 32. Output Swing Low vs Supply voltage

Figure 33. Output Swing High vs Supply Voltage Figure 34. Output Swing Low and Supply Voltage

Figure 35. Slew Rate vs Supply Voltage

IN ±

OUT

V+

V±

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7 Detailed Description

7.1 Overview

The LMV641 is a wide-bandwidth, low-power operational amplifier with an extended power supply voltage range

of 2.7 V to 12 V. The device is unity-gain stable with a 10 MHz of gain bandwidth product. Operating on a typical

supply current of 138 µA, it provides a PSRR of 105 dB, CMRR of 120 dB, VOS of 500 µV, input referred voltage

noise of 14 nV/√Hz, and a THD of 0.002%. This amplifier has a rail-to-rail output stage and a common mode

input voltage which includes the negative supply.

7.2 Functional Block Diagram

7.3 Feature Description

7.3.1 Low-Voltage and Low-Power Operation

The LMV641 has performance guaranteed at supply voltages of 2.7 V and 10 V. It is ensured to be operational

at all supply voltages between 2.7 V and 12 V. The LMV641 draws a low supply current of 138 µA. The LMV641

provides the low-voltage and low-power amplification, which is essential for portable applications.

7.3.2 Wide Bandwidth

Despite drawing the very low supply current of 138 µA, the LMV641 manages to provide a wide unity gain

bandwidth of 10 MHz. This is easily one of the best bandwidth to power ratios ever achieved, and allows this op

amp to provide wideband amplification while using the minimum amount of power. This makes the LMV641 ideal

for low power signal processing applications such as portable media players and other accessories.

7.3.3 Low Input Referred Noise

The LMV641 provides a flatband input referred voltage noise density of 14 nV/Hz, which is significantly better

than the noise performance expected from a low-power op amp. This op amp also feature exceptionally low 1/f

noise, with a very low 1/f noise corner frequency of 4 Hz. Because of this the LMV641 is ideal for low-power

applications which require decent noise performance, such as PDAs and portable sensors.

7.3.4 Ground Sensing and Rail-to-Rail Output

The LMV641 has a rail-to-rail output stage, which provides the maximum possible output dynamic range. This is

especially important for applications requiring a large output swing. The input common mode range of this part

includes the negative supply rail which allows direct sensing at ground in a single supply operation.

7.3.5 Small Size

The small footprint of the packages for the LMV641 saves space on printed-circuit boards, and enables the

design of smaller and more compact electronic products. Long traces between the signal source and the op amp

make the signal path susceptible to noise. By using a physically smaller package, these op amps can be placed

closer to the signal source, reducing noise pickup and enhancing signal integrity.

ROUT

VIN

RIN

UNSTABLE

ROC = 40 dB/decade

STABLE

ROC ± 20 dB/decade

FREQUENCY (Hz)

GAIN

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7.4 Device Functional Modes

7.4.1 Stability of Op Amp Circuits

If the phase margin of the LMV641 is plotted with respect to the capacitive load (CL) at its output, and if CLis

increased beyond 100 pF then the phase margin reduces significantly. This is because the op amp is designed

to provide the maximum bandwidth possible for a low supply current. Stabilizing the LMV641 for higher

capacitive loads would have required either a drastic increase in supply current, or a large internal compensation

capacitance, which would have reduced the bandwidth. Hence, if this device is to be used for driving higher

capacitive loads, it will have to be externally compensated.

Figure 36. Gain vs Frequency for an Op Amp

An op amp, ideally, has a dominant pole close to DC which causes its gain to decay at the rate of 20 dB/decade

with respect to frequency. If this rate of decay, also known as the rate of closure (ROC), remains the same until

the op amp's unity gain bandwidth, then the op amp is stable. If, however, a large capacitance is added to the

output of the op amp, it combines with the output impedance of the op amp to create another pole in its

frequency response before its unity gain frequency (Figure 36). This increases the ROC to 40 dB/decade and

causes instability.

In such a case, a number of techniques can be used to restore stability to the circuit. The idea behind all these

schemes is to modify the frequency response such that it can be restored to an ROC of 20 dB/decade, which

ensures stability.

7.4.1.1 In The Loop Compensation

Figure 37 illustrates a compensation technique, known as in the loop compensation, that employs an RC

feedback circuit within the feedback loop to stabilize a non-inverting amplifier configuration. A small series

resistance, RS, is used to isolate the amplifier output from the load capacitance, CL, and a small capacitance, CF,

is inserted across the feedback resistor to bypass CLat higher frequencies.

Figure 37. In the Loop Compensation

VIN

RSO VOUT

CF = ¨

§RF + 2RIN

RF2

CLROUT

RS = ROUTRIN

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Device Functional Modes (continued)

The values for RSand CFare decided by ensuring that the zero attributed to CFlies at the same frequency as the

pole attributed to CL. This ensures that the effect of the second pole on the transfer function is compensated for

by the presence of the zero, and that the ROC is maintained at 20 dB/ decade. For the circuit shown in Figure 37

the values of RSand CFare given by Equation 1. Values of RSand CFrequired for maintaining stability for

different values of CL, as well as the phase margins obtained, are shown in Table 1. RFand RIN are 10 kΩ, RLis

2 kΩ, while ROUT is 680Ω.

(1)

Table 1. Loop Compensation Stability

CL(nF) RS(Ω) CF(pF) PHASE MARGIN (°)

0.5 680 10 17.4

1 680 20 12.4

1.5 680 30 10.1

The LMV641 is capable of driving heavy capacitive loads of up to 1 nF without oscillating, however it is

recommended to use compensation should the load exceed 1 nF. Using this methodology will reduce any

excessive ringing and help maintain the phase margin for stability. The values of the compensation network

tabulated above illustrate the phase margin degradation as a function of the capacitive load.

Although this methodology provides circuit stability for any load capacitance, it does so at the price of bandwidth.

The closed loop bandwidth of the circuit is now limited by RFand CF.

7.4.1.2 Compensation by External Resistor

In some applications it is essential to drive a capacitive load without sacrificing bandwidth. In such a case, in the

loop compensation is not viable. A simpler scheme for compensation is shown in Figure 38. A resistor, RISO, is

placed in series between the load capacitance and the output. This introduces a zero in the circuit transfer

function, which counteracts the effect of the pole formed by the load capacitance, and ensures stability. The

value of RISO to be used should be decided depending on the size of CLand the level of performance desired.

Values ranging from 5Ωto 50Ωare usually sufficient to ensure stability. A larger value of RISO will result in a

system with less ringing and overshoot, but will also limit the output swing and the short circuit current of the

circuit.

Figure 38. Compensation by Isolation Resistor

CC1

+VOUT

VIN

RB1

V+

RB2

CC2

AV = -

100 k:

1 k:

= -100

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8 Application and Implementation

NOTE

Information in the following applications sections is not part of the TI component

specification, and TI does not warrant its accuracy or completeness. TI’s customers are

responsible for determining suitability of components for their purposes. Customers should

validate and test their design implementation to confirm system functionality.

8.1 Application Information

The LMV641 is a low-power, low noise, wide-bandwidth operational amplifier with an extended power supply

voltage range of 2.7 V to 12 V. With 10 MHz of gain bandwidth, 14 nV/√Hz input referred noise, and supply

current of 138 μA, the LMV641 is well suited for portable applications that require precision while amplifying at

high gains.

8.2 Typical Applications

8.2.1 High-Gain, Low-Power Inverting Amplifiers

Figure 39. High-Gain Inverting Amplifier

8.2.1.1 Design Requirements

The wide unity-gain bandwidth allows these parts to provide large gain over a wide frequency range, while

driving loads as low as 2 kΩwith less than 0.003% distortion.

8.2.1.2 Detailed Design Procedure

Figure 39 is an inverting amplifier, with a 100-kΩfeedback resistor, R2, and a 1-kΩinput resistor, R1, and

provides a gain of −100. With the LMV641, these circuits can provide gain of −100 with a −3-dB bandwidth of

120 kHz, for a quiescent current as low as 116 µA. Coupling capacitors CC1 and CC2 can be added to isolate the

circuit from DC voltages, while RB1 and RB2 provide DC biasing. A feedback capacitor CFcan also be added to

improve compensation.

BLMV641

LMV641

STANDOFF DISTANCE

20 k:

BRIDGE TEMPCO COMPENSATION NETWORK

V+

G = 23.2

BW-3 dB = 431 kHz

580:

24.5 k:

568 k:

HONEYWELL

HMC1051Z

or EQUIVALENT

CONDUCTOR TO BE

CURRENT MEASURED

I(AC or DC)

FROM mAs TO 20A V+

20 k:

5 k:

0.1 PF9V

ALKALINE

BATTERY

V+

VOUT

V+RTH

+TO ADC or

METER

CIRCUITRY

OFFSET TRIM

0 50 100 150 200

Signal Amplitudee

Time (us)

Vout (1V/div)

Vin (10mV/div)

C001

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Typical Applications (continued)

8.2.1.3 Application Curve

Figure 40. High Gain Inverting Amplifier Results

8.2.2 Anisotropic Magnetoresistive Sensor

Figure 41. A Battery-Operated System for Contact-Less Current Sensing Using an Anisotropic

Magnetoresistive Sensor

8.2.2.1 Design Requirements

The low operating current of the LMV641 makes it a good choice for battery-operated applications. Figure 41

shows two LMV641s in a portable application with a magnetic field sensor. The LMV641s condition the output

from an anisotropic magnetoresistive (AMR) sensor. The sensor is arranged in the form of a Wheatstone bridge.

This type of sensor can be used to accurately measure the current (either DC or AC) flowing in a wire by

measuring the magnetic flux density, B, emanating from the wire.

R/2

SIG +

SIG -

WITH 'R << R,

THEN RTH |R/2

THUS,

(b)

VTH± = VEXC ± VSIG

R + 'R R - 'R

SIG +

SIG -

R - 'RR + 'R

VEXC

(a)

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Typical Applications (continued)

8.2.2.2 Detailed Design Procedure

In this circuit, the use of a 9-V alkaline battery exploits the LMV641’s high voltage and low supply current for a

low-power, portable-current-sensing application. The sensor converts an incident magnetic field (through the

magnetic flux linkage) in the sensitive direction, to a balanced voltage output. The LMV641 can be used for

moderate to high current sensing applications (from a few milliamps and up to 20 A) using a nearby external

conductor providing the sensed magnetic field to the bridge. The circuit shows a Honeywell HMC1051Z used as

a current sensor. Note that the circuit must be calibrated based on the final displacement of the sensed

conductor relative to the measurement bridge. Typically, once the sensor has been oriented properly, with

respect to the conductor to be measured, the conductor can be placed about one centimeter away from the

bridge and have reasonable capability of measuring from tens of milliamperes to beyond 20 amperes.

In Figure 41, U1 is configured as a single differential input amplifier. Its input impedance is relatively low,

however, and requires that the source impedance of the sensor be considered in the gain calculations. Also, the

asymmetrical loading on the bridge will produce a small offset voltage that can be cancelled out with the offset

trim circuit shown in Figure 41.

Figure 42 shows a typical magnetoresistive Wheatstone bridge and the Thevenin equivalent of its resistive

elements. As we shall see, the Thevenin equivalent model of the sensor is useful in calculating the gain needed

in the differential amplifier.

Figure 42. Anisotropic Magnetoresistive Wheatstone Bridge Sensor, (a),

and Thevenin Equivalent Circuit, (b)

1012:988:

SIG + = 4.554V

988:1012:

SIG - = 4.446V

VSIG = 108 mV

SIG -

SIG + VO = [(SIG + ) ± (SIG -)] R4

R3R1 = R2 = R3 = R4

VSIG = VEXC x 'R

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Typical Applications (continued)

Using Thevenin’s Theorem, the bridge can be reduced to two voltage sources with series resistances. ΔR is

normally very small in comparison to R, thus the Thevenin equivalent resistance, commonly called the source

resistance, can be taken to be R. When a bias voltage is applied between VEXC and ground, in the absence of a

magnetic field, all of the resistances are considered equal. The voltage at Sig+ and Sig−is half VEXC, or 4.5 V,

and Sig+ - Sig−= 0. Bridges are designed such that, when immersed in a magnetic field, opposite resistances in

the bridge change by ±ΔR with an amount proportional to the strength of the magnetic field. This causes the

bridge's output differential voltage, to change from its half VEXC value. Thus Sig+ - Sig−= Vsig ≠0. With four

active elements, the output voltage is:

(2)

Because ΔR is proportional to the field strength, BS, the amount of output voltage from the sensor is a function of

sensor sensitivity, S. This expression can rewritten as , where

VSIG = VEXC · S · BS

where

• S = material constant (nominally 1 mV/V/gauss)

• BS= magnetic flux in gauss (3)

A simplified schematic of a single op amp, differential amplifier is shown in Figure 43. The Thevenin equivalent

circuit of the sensor can be used to calculate the gain of this amplifier.

Figure 43. Differential Input Amplifier

The Honeywell HMC1051Z AMR sensor has nominal 1-kΩelements and a sensitivity of 1 mV/V/gauss and is

being used with 9 V of excitation with a full scale magnetic field range of ±6 gauss. At full-scale, the resistors will

have ΔR≈12 Ωand 108 mV will be seen from Sig−to Sig+ (see Figure 44).

Figure 44. Sensor Output with No Load

+VO = 2.50V

580 k:

24.5 k:

LMV641

24.5 k:

580 k:

4.446V

4.554V

500:

SENSOR

BW-3 dB = GAIN-BANDWIDTH PRODUCT

AVCL =10 MHz

23.2 = 431 kHz

AVCL = R4

RTHEV + R2= 23.2

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Typical Applications (continued)

Referring to the simplified diagram in Figure 43, and assuming that required full scale at the output of the

amplifier is 2.5 V, a gain of 23.2 is needed for U1. It is clear from the Thevenin equivalent circuit in Figure 45 that

a sensor Thevenin equivalent source resistance, RTHEV, of 500 Ωwill be in series with both the inverting and

noninverting inputs of the LMV641. Therefore, the required gain is:

(4)

Choosing R1= R2= 24.5 kΩ, then R4will be approximately 580 kΩ. The actual values chosen will depend on the

full-scale needs of the succeeding circuitry as well as bandwidth requirements. The values shown here provide a

−3-dB bandwidth of approximately 431 kHz, and are found as follows.

Figure 45. Thevenin Equivalent Showing Required Gain

By choosing input resistor values for R1and R2that are four to ten times the bridge element resistance, the

bridge is minimally loaded and the offset errors induced by the op amp stages are minimized. These resistors

should have 1% tolerance, or better, for the best noise rejection and offset minimization.

Referring once again to Figure 41, U2 is an additional gain stage with a thermistor element, RTH, in the feedback

loop. It performs a temperature compensation function for the bridge so that it will have greater accuracy over a

wide range of operational temperatures. With mangetoresistive sensors, temperature drift of the bridge sensitivity

is negative and linear, and in the case of the sensor used here, is nominally −3000 PP/M. Thus the gain of U2

needs to increase proportionally with increasing temperature, suggesting a thermistor with a positive temperature

coefficient. Selection of the temperature compensation resistor, RTH, depends on the additional gain required, on

the thermistor chosen, and is dependent on the thermistor’s %/°C shift in resistance. For best op amp

compatibility, the thermistor resistance should be greater than 1000 Ω. RTH should also be much less than RA,

the feedback resistor. Because the temperature coefficient of the AMR bridge is largely linear, RTH also needs to

behave in a linear fashion with temperature, thus RAis placed in parallel with RTH, which acts to linearize the

thermistor.

8.2.2.2.1 Gain Error and Bandwidth Consideration if Using an Analog to Digital Converter

The bandwidth available from Figure 41 is dependent on the system closed loop gain required and the maximum

gain-error allowed if driving an analog to digital converter (ADC). If the output from the sensor is intended to drive

an ADC, the bandwidth will be considerably reduced from the closed-loop corner frequency. This is because the

gain error of the pre-amplifier stage needs to be taken into account when calculating total error budget. Good

practice dictates that the gain error of the amplifier be less than or equal to half LSB (preferably less in order to

allow for other system errors that will eat up a portion of the available error budget) of the ADC. However, at the

−3 dB corner frequency the gain error for any amplifier is 29.3%. In reality, the gain starts rolling off long before

the −3 dB corner is reached. For example, if the amplifier is driving an 8-bit ADC, the minimum gain error allowed

for half LSB would be approximately 0.2%. To achieve this gain error with the op amp, the maximum frequency

of interest can be no higher than

VS/2

LMV641

2.2 nF

5.23 k:

VOUT

VOICE IN

0.5 PFR1

5.23 k:

12.1 k:

15 nF

§1 - 1

2n+1

- 1 = 0.062 x f-3 dB

MAX FREQ =

= 0.062 x 380 kHz = 23.56 kHz

§1 - 1

2n+1

2- 1 x f-3 dB

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Typical Applications (continued)

where

• n is the bit resolution of the ADC

• f−3 dB is the closed loop corner frequency. (5)

Given that the LMV641 has a GBW of 10 MHz, and is operating with a closed loop gain of 26.3, its closed loop

bandwidth is 380 kHZ, therefore

(6)

which is the highest frequency that can be measured with required accuracy.

8.2.3 Voiceband Filter

The majority of the energy of recognizable speech is within a band of frequencies between 200 Hz and 4 kHz.

Therefore, it is beneficial to design circuits which transmit telephone signals that pass only certain frequencies

and eliminate unwanted signals (noise) that could interfere with conversations and introduce error into control

signals. The pass band of these circuits is defined as the ranges of frequencies that are passed. A telephone

system voice frequency (VF) channel has a pass band of 0 Hz to 4 kHz. Specifically for human voices most of

the energy content is found from 300 Hz to 3 kHz and any signal within this range is considered an in-band

signal. Alternatively, any signal outside this range but within the VF channel is considered an out-of-band signal.

To properly recover a voice signal in applications such as cellular phones, cordless phones, and voice pagers, a

low power bandpass filter that is matched to the human voice spectrum can be implemented using an LMV641

op amp. Figure 46 shows a multi-feedback, multi-pole filter (2nd order response) with a gain of −1. The lower 3

dB cutoff frequency which is set by the DC blocking capacitor C1and resistor R1is 60 Hz and the upper cutoff

frequency is 3.5 kHz.

The total current consumption is a mere 138 µA. The LV641 is operating with a gain of −1, but the circuit is easily

modified to add gain. The op amp is powered from a single supply, hence the need for offset (common-mode)

adjustment of its output, which is set to ½ VSvia its non-inverting input.

This filter is also useful in applications for battery operated talking toys and games.

Figure 46. Low Power Voice In-Band Receive Filter for Battery-Powered Portable Use

Rin

OUTPUT

Cbyp GND

V+

INPUT

GND

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9 Power Supply Recommendations

For proper operation, the power supplies must be properly decoupled. For decoupling the supply lines, TI

recommends that 10-nF capacitors be placed as close as possible to the op amp power supply pins. For single

supply, place a capacitor between V+ and V−supply leads. For dual supplies, place one capacitor between V+

and ground, and one capacitor between V– and ground.

10 Layout

10.1 Layout Guidelines

To properly bypass the power supply, several locations on a printed circuit board need to be considered. A 6.8

µF or greater tantalum capacitor should be placed at the point where the power supply for the amplifier is

introduced onto the board. Another 0.1-µF ceramic capacitor should be placed as close as possible to the power

supply pin of the amplifier. If the amplifier is operated in a single power supply, only the V+ pin needs to be

bypassed with a 0.1-µF capacitor. If the amplifier is operated in a dual power supply, both V+ and V−pins need

to be bypassed. It is good practice to use a ground plane on a printed-circuit board to provide all components

with a low-inductive ground connection.

10.2 Layout Example

Figure 47. LMV641 Layout Example

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11 Device and Documentation Support

11.1 Device Support

11.1.1 Development Support

For development support see the following:

•LMV641 PSPICE Model

•TINA-TI SPICE-Based Analog Simulation Program

•DIP Adapter Evaluation Module

•TI Universal Operational Amplifier Evaluation Module

•TI Filterpro Software

11.2 Documentation Support

11.2.1 Related Documentation

For related documentation see the following:

•Absolute Maximum Ratings for Soldering (SNOA549)

• AN-29 IC Op Amp Beats FETs on Input Current (SNOA624)

• AN-31 Op Amp Circuit Collection (SNLA140)

• AN-71 Micropower Circuits Using the LM4250 Programmable Op Amp (SNOA652)

• AN-127 LM143 Monolithic High Voltage Operational Amplifier Applications (SNVA516)

11.3 Receiving Notification of Documentation Updates

To receive notification of documentation updates, navigate to the device product folder on ti.com. In the upper

right corner, click on Alert me to register and receive a weekly digest of any product information that has

changed. For change details, review the revision history included in any revised document.

11.4 Community Resource

The following links connect to TI community resources. Linked contents are provided "AS IS" by the respective

contributors. They do not constitute TI specifications and do not necessarily reflect TI's views; see TI's Terms of

Use.

TI E2E™ Online Community TI's Engineer-to-Engineer (E2E) Community. Created to foster collaboration

among engineers. At e2e.ti.com, you can ask questions, share knowledge, explore ideas and help

solve problems with fellow engineers.

Design Support TI's Design Support Quickly find helpful E2E forums along with design support tools and

contact information for technical support.

11.5 Trademarks

E2E is a trademark of Texas Instruments.

All other trademarks are the property of their respective owners.

11.6 Electrostatic Discharge Caution

These devices have limited built-in ESD protection. The leads should be shorted together or the device placed in conductive foam

during storage or handling to prevent electrostatic damage to the MOS gates.

11.7 Glossary

SLYZ022 —TI Glossary.

This glossary lists and explains terms, acronyms, and definitions.

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12 Mechanical, Packaging, and Orderable Information

The following pages include mechanical, packaging, and orderable information. This information is the most

current data available for the designated devices. This data is subject to change without notice and revision of

this document. For browser-based versions of this data sheet, refer to the left-hand navigation.

PACKAGE OPTION ADDENDUM

www.ti.com 4-Feb-2016

Addendum-Page 1

PACKAGING INFORMATION

Orderable Device Status

(1)

Package Type Package

Drawing Pins Package

Qty Eco Plan

(2)

Lead/Ball Finish

(6)

MSL Peak Temp

(3)

Op Temp (°C) Device Marking

(4/5)

Samples

LMV641MA/NOPB ACTIVE SOIC D 8 95 Green (RoHS

& no Sb/Br) CU SN Level-1-260C-UNLIM -40 to 125 LMV64

1MA

LMV641MAE/NOPB ACTIVE SOIC D 8 250 Green (RoHS

& no Sb/Br) CU SN Level-1-260C-UNLIM -40 to 125 LMV64

1MA

LMV641MAX/NOPB ACTIVE SOIC D 8 2500 Green (RoHS

& no Sb/Br) CU SN Level-1-260C-UNLIM -40 to 125 LMV64

1MA

LMV641MF/NOPB ACTIVE SOT-23 DBV 5 1000 Green (RoHS

& no Sb/Br) CU SN Level-1-260C-UNLIM AB9A

LMV641MFE/NOPB ACTIVE SOT-23 DBV 5 250 Green (RoHS

& no Sb/Br) CU SN Level-1-260C-UNLIM AB9A

LMV641MFX/NOPB ACTIVE SOT-23 DBV 5 3000 Green (RoHS

& no Sb/Br) CU SN Level-1-260C-UNLIM AB9A

LMV641MG/NOPB ACTIVE SC70 DCK 5 1000 Green (RoHS

& no Sb/Br) CU SN Level-1-260C-UNLIM -40 to 125 A99

LMV641MGE/NOPB ACTIVE SC70 DCK 5 250 Green (RoHS

& no Sb/Br) CU SN Level-1-260C-UNLIM -40 to 125 A99

LMV641MGX/NOPB ACTIVE SC70 DCK 5 3000 Green (RoHS

& no Sb/Br) CU SN Level-1-260C-UNLIM -40 to 125 A99

(1) The marketing status values are defined as follows:

ACTIVE: Product device recommended for new designs.

LIFEBUY: TI has announced that the device will be discontinued, and a lifetime-buy period is in effect.

NRND: Not recommended for new designs. Device is in production to support existing customers, but TI does not recommend using this part in a new design.

PREVIEW: Device has been announced but is not in production. Samples may or may not be available.

OBSOLETE: TI has discontinued the production of the device.

(2) Eco Plan - The planned eco-friendly classification: Pb-Free (RoHS), Pb-Free (RoHS Exempt), or Green (RoHS & no Sb/Br) - please check http://www.ti.com/productcontent for the latest availability

information and additional product content details.

TBD: The Pb-Free/Green conversion plan has not been defined.

Pb-Free (RoHS): TI's terms "Lead-Free" or "Pb-Free" mean semiconductor products that are compatible with the current RoHS requirements for all 6 substances, including the requirement that

lead not exceed 0.1% by weight in homogeneous materials. Where designed to be soldered at high temperatures, TI Pb-Free products are suitable for use in specified lead-free processes.

Pb-Free (RoHS Exempt): This component has a RoHS exemption for either 1) lead-based flip-chip solder bumps used between the die and package, or 2) lead-based die adhesive used between

the die and leadframe. The component is otherwise considered Pb-Free (RoHS compatible) as defined above.

Green (RoHS & no Sb/Br): TI defines "Green" to mean Pb-Free (RoHS compatible), and free of Bromine (Br) and Antimony (Sb) based flame retardants (Br or Sb do not exceed 0.1% by weight

in homogeneous material)

PACKAGE OPTION ADDENDUM

www.ti.com 4-Feb-2016

Addendum-Page 2

(3) MSL, Peak Temp. - The Moisture Sensitivity Level rating according to the JEDEC industry standard classifications, and peak solder temperature.

(4) There may be additional marking, which relates to the logo, the lot trace code information, or the environmental category on the device.

(5) Multiple Device Markings will be inside parentheses. Only one Device Marking contained in parentheses and separated by a "~" will appear on a device. If a line is indented then it is a continuation

of the previous line and the two combined represent the entire Device Marking for that device.

(6) Lead/Ball Finish - Orderable Devices may have multiple material finish options. Finish options are separated by a vertical ruled line. Lead/Ball Finish values may wrap to two lines if the finish

value exceeds the maximum column width.

Important Information and Disclaimer:The information provided on this page represents TI's knowledge and belief as of the date that it is provided. TI bases its knowledge and belief on information

provided by third parties, and makes no representation or warranty as to the accuracy of such information. Efforts are underway to better integrate information from third parties. TI has taken and

continues to take reasonable steps to provide representative and accurate information but may not have conducted destructive testing or chemical analysis on incoming materials and chemicals.

TI and TI suppliers consider certain information to be proprietary, and thus CAS numbers and other limited information may not be available for release.

In no event shall TI's liability arising out of such information exceed the total purchase price of the TI part(s) at issue in this document sold by TI to Customer on an annual basis.

TAPE AND REEL INFORMATION

*All dimensions are nominal

Device Package

Type Package

Drawing Pins SPQ Reel

Diameter

(mm)

Reel

Width

W1 (mm)

(mm) B0

(mm) K0

(mm) P1

(mm) W

(mm) Pin1

Quadrant

LMV641MAE/NOPB SOIC D 8 250 178.0 12.4 6.5 5.4 2.0 8.0 12.0 Q1

LMV641MAX/NOPB SOIC D 8 2500 330.0 12.4 6.5 5.4 2.0 8.0 12.0 Q1

LMV641MF/NOPB SOT-23 DBV 5 1000 178.0 8.4 3.2 3.2 1.4 4.0 8.0 Q3

LMV641MFE/NOPB SOT-23 DBV 5 250 178.0 8.4 3.2 3.2 1.4 4.0 8.0 Q3

LMV641MFX/NOPB SOT-23 DBV 5 3000 178.0 8.4 3.2 3.2 1.4 4.0 8.0 Q3

LMV641MG/NOPB SC70 DCK 5 1000 178.0 8.4 2.25 2.45 1.2 4.0 8.0 Q3

LMV641MGE/NOPB SC70 DCK 5 250 178.0 8.4 2.25 2.45 1.2 4.0 8.0 Q3

LMV641MGX/NOPB SC70 DCK 5 3000 178.0 8.4 2.25 2.45 1.2 4.0 8.0 Q3

PACKAGE MATERIALS INFORMATION

www.ti.com 13-Jan-2018

Pack Materials-Page 1

*All dimensions are nominal

Device Package Type Package Drawing Pins SPQ Length (mm) Width (mm) Height (mm)

LMV641MAE/NOPB SOIC D 8 250 210.0 185.0 35.0

LMV641MAX/NOPB SOIC D 8 2500 367.0 367.0 35.0

LMV641MF/NOPB SOT-23 DBV 5 1000 210.0 185.0 35.0

LMV641MFE/NOPB SOT-23 DBV 5 250 210.0 185.0 35.0

LMV641MFX/NOPB SOT-23 DBV 5 3000 210.0 185.0 35.0

LMV641MG/NOPB SC70 DCK 5 1000 210.0 185.0 35.0

LMV641MGE/NOPB SC70 DCK 5 250 210.0 185.0 35.0

LMV641MGX/NOPB SC70 DCK 5 3000 210.0 185.0 35.0

PACKAGE MATERIALS INFORMATION

www.ti.com 13-Jan-2018

Pack Materials-Page 2

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