© Freescale Semiconductor, Inc. , 2004, 2007. All rights rese rved.
Freescale Semicondu ctor
Te chn ical Da ta
This document contains detaile d information about power
considerations, DC/AC electrical characteristics, and AC timing
specifications for .13µm (HiP7) members of the
PowerQUICC™ II family of integrated communications
processors—the MPC8280, the MPC8275, and the MPC8270
(collectively c alled the MPC8280 throughout this docum ent).
MPC8280EC
Rev. 1.8, 8/2007
Contents
1. Overview . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 2
2. Operating Conditions . . . . . . . . . . . . . . . . . . . . . . . . . 7
3. DC Electrical Characteristics . . . . . . . . . . . . . . . . . . . 8
4. Thermal Characteristics . . . . . . . . . . . . . . . . . . . . . . 11
5. Power Dissipation . . . . . . . . . . . . . . . . . . . . . . . . . . . 13
6. AC Electrical Characteristics . . . . . . . . . . . . . . . . . . 14
7. Clock Configuration Modes . . . . . . . . . . . . . . . . . . . 23
8. Pinout . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 42
9. Package Description . . . . . . . . . . . . . . . . . . . . . . . . . 72
10. Ordering Information . . . . . . . . . . . . . . . . . . . . . . . . 76
11. Document Revision History . . . . . . . . . . . . . . . . . . . 76
MPC8280
Pow e rQ UICC ™ II Fam i ly
Hardware Specifications
MPC8280 PowerQUI CC™ II Famil y Hardw are Sp ecif ications , Rev. 1.8
2Freescale Semiconductor
Overview
1Overview
Table 1 shows the functionality supported by each device in the MPC8280 family.
Device s in the MPC8280 family a re available in four packages—t he standard ZU a nd VV packages and the alternate
VR or ZQ packages—as shown in Table 2. No te that through out this document r eference s to the MPC8280 and the
MPC8270 ar e inclusive of VR and ZQ package devi ces unless otherwise specif ied. For more i nformation on VR and
ZQ packages, contact your Freescale sales of fic e. For package ordering infor mati on, refer t o Sect ion 10, “Ordering
Information.”
Table 1. MPC8280 Pow erQUICC II Family Functionality
Functionality
Devices
MPC8270 MPC8275 MPC8280
Package 1
1
Refer to Table 2.
480 TBGA 516 PBGA 516 PBGA 480 TBGA
Serial comm unicati ons controllers (SCCs) 4 4 4 4
QUICC multi -channel controller (QM C) — — — —
Fast communication controllers (FCCs) 3 3 3 3
I-Cache (Kbyte) 16 16 16 16
D-Cache (Kby te) 16 16 16 16
Ethernet (10/100) 3 3 3 3
UTOPIA II Ports 0 0 2 2
Multi -channel cont rollers (MCCs) 1 1 1 2
PCI bridge Yes Yes Yes Yes
Transmission convergence (TC) layer — — — Yes
Inverse multi plexing for ATM (IMA) — — — Yes
Univer sal s eri al bus (USB) 2.0 full/low rate 1 1 1 1
Security engine (SEC) — — — —
Table 2. HiP7 PowerQUICC II Device Packages
Code
(Package) ZU
(480 TBGA—Leaded) VV
(480 TBGA—Lead Free) VR
(516 PBGA—Lead free) ZQ
(516 PBGA —L ead spheres)
Device MPC8280 MPC8280 MPC8275VR MPC8275ZQ
MPC8270 MPC8270 MPC8270VR MPC8270ZQ
MPC8280 PowerQUI CC™ II Famil y Hardw are Sp ecif ications, Rev. 1.8
Freescale Semiconductor 3
Overview
Figure 1 shows the block diagram. Shaded po rtions are device-specific; refer to the notes below.
Figure 1. MPC8280 Block Diagram
1.1 Features
The major fea ture s of the MPC8280 are as follows:
• Dual-iss ue integer (G2_LE) core
— A core version of the EC603e microprocessor
— System core micr oprocessor support i ng f requencies of 166–450 MHz
— Separate 16-Kbyte data and instruction caches:
– Four-way set asso ciative
– Physically addres sed
– LRU rep lacem en t algo ri thm
— Architecture-c ompliant memory management unit (MMU)
— Common on-chip processor (COP) test interface
16 Kbytes
G2_LE Core
I-Cache
I-MMU
16 Kbytes
D-Cache
D-MMU
Communication Processor Module (CPM )
Timers
Parallel I/O
Baud Rate
Generators
32 KB
32-bit RI SC Mi crocontroller
and P rogram R O M
Serial
DMAs
4 Virtual
IDMAs
60x-to-PCI
Bridge
Bridge
Memory Controller
Clock Co unter
System Functions
Syste m Interface Unit
(SIU)
Loca l B us
32 bits, up to 100 MHz
PCI Bus
32 bi ts, up to 66 M H z
or
MCC1
1MCC2 FCC1 FCC2 FCC3 SCC1 SCC2 SCC3 SCC4/ SMC1 SMC2 SPI I2C
Serial Interface2
3 MII or RMII 2 UT OPIA
Ports3Ports
60x Bus
Microcode
IMA1
Data
Interrupt
Controller
Time Slot Assigner
TC Layer Hardware1
8 TDM Po rts 2 Non-Multiplexed
I/O
60x-to-Local
Bus Interface Unit
32 KB
Instruction
Notes:
1 MPC8280 only (not on MPC8270, the VR pac kage, nor the ZQ package)
2 MPC8280 has 2 seri al interface (SI) blocks and 8 TDM ports. MPC8270 and the VR and ZQ pack ages have
only 1 SI block and 4 TDM ports (TDM2[A–D]).
3 MPC8280, MPC8275VR, MPC8275ZQ only (not on MPC8270, MPC827 0VR, nor MPC827 0ZQ )
RAM RAM
USB
MPC8280 PowerQUI CC™ II Famil y Hardw are Sp ecif ications , Rev. 1.8
4Freescale Semiconductor
Overview
— High-performance (SP EC95 benchmark at 450 MHz; 855 Dhrystones MIP S at 450 MHz)
— Supports bus snooping for data cache coherency
— Floating-point unit (FPU)
• Separate power supply for internal logic and for I/O
• Separate PLLs for G2_LE core and for the CPM
— G2_LE core and CPM can run at different frequencies for power/ performance opti miza tion
— Internal core/bus cloc k multiplie r that provide s 2:1, 2.5:1, 3:1, 3.5:1, 4:1, 4.5:1, 5:1, 6:1, 7:1, 8:1 ratios
— Internal CPM/bus clock multiplier that provide s 2:1, 2.5:1, 3:1, 3.5:1, 4:1, 5:1, 6:1, 8:1 ratios
• 64-bit data and 32-bit address 60x bus
— Bus supports multiple master designs
— Supports single- and four-beat burst transfers
— 64-, 32-, 16-, and 8-bit port sizes controlled by on-chip memory controller
— Supports data parity or ECC and address parity
• 32-bit data and 18-bit address local bus
— Single-master bus, supports external slaves
— Eight-beat burst transfers
— 32-, 16-, and 8-bit port sizes controlled by on-chip memory contr oller
• 60x-to-PCI br idge
— Programmable host bridge and a gent
— 32-bit d ata bus, 66.67/83.3/ 100 MHz, 3.3 V
— Synchronous and asynchronous 60x a nd PCI clock modes
— Al l inter n al addre ss spa ce av ail ab le to ex t ernal PC I hos t
— DMA for memory block transfers
— PCI-to-60x address rema pping
• PCI bridge
— PCI Specification Revision 2. 2 complia nt and supports freque ncies up to 66 MHz
— On-chip arbitrat ion
— Support for PCI-to-60x- memory and 60x -memor y-to-PCI streaming
— PCI host bridge o r peripheral capabilities
— Includes 4 DMA channels for the following transfers:
– PCI-to-60x to 60x-to-PCI
– 60x-t o-PCI to PCI- to-60x
– PCI-to-60x to PCI-to-60 x
– 60x-to-PCI to 60x-to-PCI
— Includes all of the config uration registers (which are automatically loaded fro m the EPROM and u sed
to configure the MPC8280) requir ed by the PCI standard as well as message and doorbell registers
— Supports the I2O standard
— Hot-s wap friend ly (supports the hot swap specific ation as defined by PICMG 2.1 R1.0 August 3, 1998)
— Support for 66.67/83.33/100 MHz, 3 .3 V specif ic ation
— 60x-PCI bus core l ogic that us es a buffer pool to allocate buff ers for each port
MPC8280 PowerQUI CC™ II Famil y Hardw are Sp ecif ications, Rev. 1.8
Freescale Semiconductor 5
Overview
— Uses the local bus signals, removing ne ed for additional pins
• System interf ace unit (SIU)
— Clock synthesizer
— Reset controller
— Real-time clock (RTC) register
— Periodic interrupt timer
— Hardware bus monitor and softwa re watchdog timer
— IEEE 1149.1 JTAG test access port
• 12-bank memory contr oller
— Glueless interfa ce to SRAM, page mode SDRAM, DRAM, EPROM, Flash and other user- definable
peripherals
— Byte write en ables and selectable parity generat ion
— 32-bit addr ess decodes with programmable bank size
— Three user-programmable machines, general-purpos e chip-select machine, and page- mode pipeline
SDRAM machine
— Byte selects for 64-bus width (60x) and byte selects for 32-bus width ( loca l)
— Dedicated interface logic for SDRAM
• CPU co re can be disabled and the device can be used in slave mode to an externa l core
• Communications processor module (CPM)
— Embedded 32-bit communications proce ssor (CP) uses a RISC architecture for fle xible support for
communications protocols
— Interfaces to G2_LE core through a n on-chip 32- Kbyte dual-por t data RAM, an on-c hip 32-Kbyte
dual-port instr uction RAM and DMA controll er
— Serial DMA cha nnels for receive and transmit on all serial channels
— Parallel I/O regist ers with open-drain and interrupt capability
— Virtual DMA funct ionality execut ing memory- t o- memory and me mory-to-I/O transf ers
— Three fast communications contr oller s supporting the following protocols:
– 10/100-Mbit Ether net/IEEE 802 .3 CDMA/CS interface through media independe nt inter fac e (MII)
or reduced medi a indepe ndent interf ace (RMII)
– ATM—Full- duplex SAR protocols at 155 Mbps, thr ough UTOPIA interf ace, AAL5, AAL1, AAL0
protocols, TM 4.0 CBR, VBR, UBR, ABR traffic types, up to 64 K external connections (no ATM
support for the MPC8270)
– Transparent
– HDLC—Up to T3 rates (clear channel)
– FCC2 can also be connected to the TC layer (MPC8280 only)
— Two multicha nnel controlle rs (MCCs) (one MCC on the MPC8270)
– Each MCC h andles 128 seria l, f ull -duplex, 64-Kbps da ta c hannels. Each MCC c an be spli t in to four
subgroups of 32 ch annels each.
– Almost any combination of subgroups c an be multiplexed to single or multiple TDM inte rfa ces up
to four TDM interfaces per M CC
MPC8280 PowerQUI CC™ II Famil y Hardw are Sp ecif ications , Rev. 1.8
6Freescale Semiconductor
Overview
— Four se rial communi cati ons controllers (SCCs ) ide ntical to those o n the MPC860, supporting the digit al
portions of the followi ng protocols:
– Ethernet/IEEE 802.3 CDMA/CS
– HDLC/SDLC and HDLC bus
– Universal asynchro nous receiver transmitter (UART)
– Synchronous UART
– Binary synchronous (BISYNC) communications
– Transparent
— Universal ser ial bus (USB) controller
– Supports USB 2.0 f ull/low rate compat ible
– USB host mode
– Supports control, bulk, interrupt, and is ochronous data trans fer s
– CRC16 generation and checking
– NRZI encoding/de coding with bit stuffing
– Supports both 12- and 1.5-Mbps data rates (automatic generation of preamble token and data r ate
configuration ). Note that low-speed operation requires an exter nal h ub.
– Flexible data buf fers with multipl e buffers per frame
– Supports local loopback mode for diagnostics (12 Mbps only)
– Supports USB slave mod e
– Four independent endpoints support control, bulk, interrupt, and isochronous data transfers
– CRC16 generation and checking
– CR C5 checking
– NRZI encoding/de coding with bit stuffing
– 12- or 1.5- Mbps data ra te
– Flexible data buf fers with multipl e buffers per frame
– Automatic retransmi ssion upon transmit error
— Two seria l management controllers (SMCs) , identical to thos e of the MPC860
– Provide man agement f or BRI devi ces as general circuit inte rface (GCI) controllers in time-
division-multiplexed (TDM) channels
– Transparent
– UART (low-speed operation)
— One serial peripheral interface ident ical to the MPC860 SPI
— One inter-integrated circuit (I 2C) controller (identical to the MPC860 I2C controller)
– Microwire compatible
– Multiple-master, single-master, and slave modes
— Up to eight TDM interfaces (four on the MPC8270)
– Supports two groups of four TDM cha nnels for a total of eight TDMs (one group of four on the
MPC8270 and the MPC8275)
– 2,048 byte s of SI RAM
– Bit or byte resolution
– Independent trans mit and rec eive routing, frame synchronization
MPC8280 PowerQUI CC™ II Famil y Hardw are Sp ecif ications, Rev. 1.8
Freescale Semiconductor 7
Operati ng Conditions
– Supports T1, CEP T, T1/E1, T3/E3, pulse code modulation high way , ISDN basi c rate, ISDN pri mary
rate, Free sc ale int erc h ip digi t al lin k (IDL), gen era l circu it inte rfa ce (GCI), and user-defined T D M
serial interfaces
— Eight independent baud rat e generators and 20 input clock pins for supplying clocks to FCCs, SCCs,
SMCs, and seria l channels
— Four independent 16-bit timers that can be interconnected a s two 32-bit timers
• Inverse multiplexing for A TM capabilities (IMA) (MPC8280 only).Supported by eight transfer transmission
convergence (TC) layers between the TDMs and FCC2.
• Transmission convergence (TC) layer (MPC8280 only)
2 Operating Conditions
Table 3 shows the maximum electrical ratings.
Table 4 lists recommended operational voltage conditions.
Table 3. Absolute Maximum Rating s 1
1
Absolute maximum ratings are stress rati ngs only; func ti onal operation (see Table 4) at the maximums is not
guaranteed. Stress beyond those listed may affect device reliability or cause permanent damage.
Rating Symbol Value Unit
Core supply volt age 2
2
Caution: VDD/VCCSYN must n ot exc eed VDDH by more tha n 0.4 V during normal operati on. It i s reco mmended
that VDD/VCCSYN shou ld be raised bef ore or simult aneous with VDDH during power- on reset . VDD/VCCSYN may
exceed VDDH by more than 0.4 V during power-on reset for no more than 100 ms.
VDD -0.3 – 2.2 5 V
PLL supply voltage2VCCSYN -0.3 – 2.25 V
I/O supply volt age 3
3
Caution: VDDH can exceed VDD/VCCSYN by 3.3 V during power on reset by no more than 100 mSec. VDDH
should not exceed VDD/VCCSYN by more than 2.5 V during normal operation.
VDDH -0.3 – 4.0 V
Input voltage 4
4
Caution: VIN must not exceed VDDH by more than 2.5 V at any time, inc luding during power -on reset.
VIN GND(-0.3) – 3.6 V
Junction temperature Tj120 °C
Storage temperat ure range TSTG (-55 ) – (+150) °C
Table 4 . Recomm end ed Operati ng Conditions 1
1
Caution: These are the recommended and tested oper ating co nditions. Proper op eration o utside of these condi tions
is not guaranteed.
Rating Symbol Value Unit
Core suppl y voltage VDD 1.45 – 1 .60 V
PLL supply vol tage VCCSYN 1. 45 – 1.60 V
I/O suppl y voltage VDDH 3.135 – 3.465 V
Input voltage VIN GND (-0. 3) – 3.465 V
Juncti on temperature (m aximum) Tj105 2
2
Note that for extended temperature parts the range is (-40)TA– 105Tj.
°C
Ambient te mp erat ure TA0–702°C
MPC8280 PowerQUI CC™ II Famil y Hardw are Sp ecif ications , Rev. 1.8
8Freescale Semiconductor
DC Electrical Characteri sti cs
This de vice contains c irc uitry prote cting aga inst damage due to high st at ic volt age or e lectr ical fields; howe ver , it is
advised that normal precautions be taken to avoid a pplicati on of any voltages h igher than m aximum-rated voltages
to this high -impedance cir cuit. Reliabilit y of operation is enhan ced if unuse d inputs ar e tied to an appropriat e logic
voltage level (eit her GND or VCC).
Figure 2 shows the undershoot and overshoot voltage of the 60x and lo cal bus memory interface of t he MPC8280.
Note that in PCI mode the I/O interface is different.
Figure 2. Overshoot/Undershoot Voltage
3 DC E lectrical Ch aracteristi cs
Table 5 shows DC electrical characteristics.
Table 5. DC Electrical Characteris tics 1
Characteristic Symbol Min Max Unit
Input high voltage—
all input s except TCK, TRST and PORESET 2 VIH 2.0 3.465 V
Input low voltage VIL GND 0.8 V
CLKIN input high voltage VIHC 2.4 3.465 V
CLKIN input low vo lt age VILC GND 0.4 V
Input leakage current, VIN = VDDH 3 IIN —10µA
Hi-Z (o ff state) leakage current, VIN = VDDH3IOZ —10µA
Signal low input current, VIL = 0.8 V 4 IL—1µA
Signal high input current, VIH = 2.0 V IH—1µA
Output high voltage, IOH = –2 mA
except UT O P IA mode, and open drai n pins
In U TOP IA mo d e 5 (U T O PIA pins on ly): IOH = -8.0mA
PA[0-31]
PB[4-31]
PC[0-31]
PD[4-31]
VOH 2.4 — V
GND
GND – 0.3 V
GND – 1.0 V
Not to exceed 10%
GVDD
of tSDRAM_CLK
GVDD + 5%
4 V
VIH
VIL
MPC8280 PowerQUI CC™ II Famil y Hardw are Sp ecif ications, Rev. 1.8
Freescale Semiconductor 9
DC Electr ical Characteri stics
In U TOP IA mo d e 5 (UTOPIA pins only): IOL = 8.0 mA
PA[0-31]
PB[4-31]
PC[0-31]
PD[4-31]
VOL —0.5V
IOL = 6.0mA
BR BG
ABB/IRQ2
TS
A[0-31]
TT[0-4]
TBST
TSIZE[0–3]
AACK
ARTRY
DBG
DBB/IRQ3
D[0-63]
DP(0)/RSRV/EXT_BR2
DP(1)/IRQ1/EXT_BG2
DP(2)/TLBISYNC/IRQ2/EXT_DBG2
DP(3)/IRQ3/EXT_BR3/CKSTP_OUT
DP(4)/IRQ4/EXT_BG3/CORE_SREST
DP(5)/TBEN/EXT_DBG3/IRQ5/CINT
DP(6)/CSE(0)/IRQ6
DP(7)/CSE(1)/IRQ7
PSDVAL
TA
TEA
GBL/IRQ1
CI/BADDR29/IRQ2
WT/BADDR30/IRQ3
L2_HIT/IRQ4
CPU_BG/BADDR31/IRQ5/CINT
CPU_DBG
CPU_BR
IRQ0/NMI_OUT
IRQ7/INT_OUT/APE
PORESET
HRESET
SRESET
RSTCONF
VOL —0.4V
Table 5. DC Electrical Charac teristics 1 (c o ntin ued )
Characteristic Symbol Min Max Unit
MPC8280 PowerQUI CC™ II Famil y Hardw are Sp ecif ications , Rev. 1.8
10 Freescale Semiconductor
DC Electrical Characteri sti cs
IOL = 5.3mA
CS[0-9]
CS(10)/BCTL1
CS(11)/AP(0)
BADDR[27–28]
ALE
BCTL0
PWE[0–7]/PSDDQM[0–7]/PBS[0–7]
PSDA10/PGPL0
PSDWE/PGPL1
POE/PSDRAS/PGPL2
PSDCAS/PGPL3
PGTA/PUPMWAIT/PGPL4/PPBS
PSDAMUX/PGPL5
LWE[0–3]LSDDQM[0–3]/LBS[0–3]/PCI_CFG[0–3]
LSDA10/LGPL0/PCI_MODCKH0
LSDWE/LGPL1/PCI_MODCKH1
LOE/LSDRAS/LGPL2/PCI_MODCKH2
LSDCAS/LGPL3/PCI_MODCKH3
LGTA/LUPMWAIT/LGPL4/LPBS
LSDAMUX/LGPL5/PCI_MODCK
LWR
MODCK[1–3]/AP[1–3]/TC[0–2]/BNKSEL[0–2]
IOL = 3.2mA
L_A14/PAR
L_A15/FRAME/SMI
L_A16/TRDY
L_A17/IRDY/CKSTP_OUT
L_A18/STOP
L_A19/DEVSEL
L_A20/IDSEL
L_A21/PERR
L_A22/SERR
L_A23/REQ0
L_A24/REQ1/HSEJSW
L_A25/GNT0
L_A26/GNT1/HSLED
L_A27/GNT2/HSENUM
L_A28/RST/CORE_SRESET
L_A29/INTA
L_A30/REQ2
L_A31
LCL_D[0-31]/AD[0-31]
LCL_DP[0-3]/C/BE[0-3]
PA[0–31]
PB[4–31]
PC[0–31]
PD[4–31]
TDO
QREQ
VOL —0.4V
1
The defaul t configuration of the CPM pins (PA[0 –31], PB[4–31], PC[ 0–31], PD[4–31] ) is in put. To pre vent e xcessive DC
curr ent, either pul l un used pins to GND or VDDH or confi gure them as outputs.
2
TCK, TRST and PORESET have min VIH = 2.5V.
Table 5. DC Electrical Charac teristics 1 (c o ntin ued )
Characteristic Symbol Min Max Unit
MPC8280 PowerQUI CC™ II Famil y Hardw are Sp ecif ications, Rev. 1.8
Freescale Semiconductor 11
Thermal Characteristics
4 Thermal Characteristics
Table 6 describes thermal characteristics for both the packages. See Table 2 for inf ormation about a given device’s
packag e. For the disc ussi ons sections 4. 1 and 4.5, PD = (VDD × IDD) + PI/O, where PI/O is the power di ssipati on of
the I/O drivers.
4.1 Estimatio n with Junctio n-to-Amb ient Thermal Resistance
An estimation of the chip junction te mperature, TJ, in °C can be obtained from the fo llowing equation :
TJ = TA + (R θJA × PD)
where:
TA = amb ien t tem pe ratu re (ºC)
RθJA = package jun ction-to-a mbient thermal resi stance (ºC/W)
PD = power dissipation in package
The junction-to- ambient thermal r esi stance is an indust ry s tandard value that provides a quick and easy estimation
of thermal performance. However, the answer is only an estimate; test cases have demonstrated that errors of a factor
of two (in the quantity TJ – TA) are possibl e.
3
The leakage c urr ent is measured for nomi nal VDDH,V CCSYN, an d VDD.
4
VIL for II C interface does not match IIC standard, but does me et IIC stan dard for VOL and shoul d not cause any compatibility
issue.
5
MPC8280, MPC8275VR, MPC8275ZQ only.
Table 6. T herm al Characteristi cs
Characteristic Symbol Value Unit Air Flow
480 TBGA 516 PBGA
Junction to ambi ent—
single-layer board 1
1
Assum es no thermal vias .
RθJA
16 27
°C/W Natural convection
11 21 1 m/s
Junction to ambi ent—
four-lay er boar d RθJA
12 19
°C/W Natural convection
916 1 m/s
Junction to boar d 2
2
Thermal resi stance between the di e and the pri nted cir cuit board per JEDEC JESD51-8. Board t em perature is measured on
the top s urf ace of the board near the package .
RθJB 611°C/W —
Junction to cas e 3
3
Thermal re sista nce between the die and t he ca se top sur face as measur ed by the c old pl ate method (MI L SPEC-883 M ethod
1012.1).
RθJC 28°C/W —
Junction-t o-package top 4
4
Thermal char acteriza tion par ameter indica ting the tempera ture dif ference between pack age top and the juncti on temperature
per JEDEC JESD51-2. Wh en Greek letters are no t avai lable, the thermal characteriza ti on parameter is writ ten as Psi-JT.
ΨJT 22°C/W —
MPC8280 PowerQUI CC™ II Famil y Hardw are Sp ecif ications , Rev. 1.8
12 Freescale Semiconductor
Thermal Characteristics
4.2 Estimatio n with Junction- to-Case Thermal Resistance
Histor ically , the therm al r esistance has frequently be en expressed as the sum of a junction-to -case thermal resistance
and a case-to-ambient thermal resistance:
RθJA = RθJC + RθCA
where:
RθJA = ju n c t io n - t o -ambient th er mal re s i st a n c e (º C/ W)
RθJC = junction-to-case thermal resistance (ºC/W)
RθCA = case-to- am bien t therma l resi sta n ce (ºC /W )
RθJC is device rela ted and cannot be influenced by the use r. The user adjusts the the rmal environment to af fect the
case -t o-ambie nt the rmal resis t ance, RθCA. For instance, the user can change the air flow around the device, add a
heat sink, change the mounting arra ngement on t he printed circuit board, or change the thermal dissipation on the
print ed circuit boa rd surround ing the device. This thermal model i s most useful for ceramic p ackages with heat sin ks
where some 90% of the heat flows through the case and the heat sink to the ambient environment. For most
packages, a better model is required.
4.3 Estimatio n with Junction- to-Boa rd Thermal Resistance
A simple pa ckage the rmal model which ha s demonst rated reasona ble accur acy (about 20%) is a two- resistor model
consi sting of a junctio n-to- board and a junction -to-ca se thermal resi stanc e. The junction- to-case t hermal resista nce
cover s the situa tion where a heat sink is use d or where a substantia l amount of heat is dis sipate d from the top of the
package. The junction-to-board thermal resistance describes the thermal performance when most of the heat is
conducted to the printed cir cuit board. It has bee n observed tha t the the rmal performance of most plastic packages,
especially PBGA packages, is strongly depende nt on the board temperature.
If the board temperature is known, an estimate of the junction temperature in the environment can be made using
the following equatio n:
TJ = TB + ( RθJB × PD)
where:
RθJB = junction-to-board thermal resistance (ºC/W)
TB = board temp er at ure (ºC)
PD = power dissipation in package
If the board temperature is known and the heat loss fr om the pac kage case to the air can be ignored, acceptable
predictions of junction temperature can be made. For this method to work, the boa rd and board mounting must be
similar to the test board used to deter mine the ju nction-to-boa rd thermal resistanc e , namel y a 2s2p (board with a
power and a ground plane) and by attaching the thermal balls to the ground plane.
4.4 Estimation Using Simulation
When t he board t empera ture is not known, a thermal simulation of the application is needed. T he simple two-resist or
model can be used with the thermal simulation of the application, or a more accurate and complex model of the
package can be used in the thermal simulati on.
MPC8280 PowerQUI CC™ II Famil y Hardw are Sp ecif ications, Rev. 1.8
Freescale Semiconductor 13
Power Dissi pati on
4.5 Experimental Determination
To det erm i ne the jun c tio n tem p era tur e of th e device in the app l icat ion aft er p rot o types are av ail abl e, the ther mal
char act erization pa ram et er (ΨJT) can be used to dete rmine the junction temperatur e with a measurement of the
temperature at the top center of the package case using the following equation:
TJ = TT + (ΨJT × PD)
where:
ΨJT = thermal characterization pa rame te r
TT = th ermocouple tempera ture on top of package
PD = power dissipation in package
The thermal characterization parameter is measured per JEDEC JESD51-2 specification using a 40-gauge type T
thermocouple epoxied to the top cente r of the package case. The thermocou ple should be positioned so that the
thermo couple junctio n rest s on the package. A small amount of epoxy is pla ced over th e the rmocouple juncti on and
over 1 mm of wire extending from the junction. The thermocouple wire is placed flat against the case to avoid
measurement errors cause d by cooling effects of the thermocouple wire.
4.6 Layout Practi ces
Each VDD and VDDH pin should be provided with a low-impedance path to the board’s power supplies. Each
ground pin sho uld likewi se be p rovided with a lo w-impedance pa th to gr ound. The power su pply pins dr ive dist inct
groups of logic on chip. The VDD and VDDH power supplies should be bypassed to ground using by-pass
capacit ors located as close as possibl e to the four s ides of the p ackage. For filtering high freque ncy noise , a capac itor
of 0. 1uF on each VDD and VDDH pin is rec ommended. Further, for medium fr equency noise, a total of 2 capacitor s
of 47uF for VDD and 2 capa citors of 47uF for VDDH are also recommnded . The capacitor leads and associated
printed circuit tr aces connecting to chip VDD, VDDH and ground should be kept to le ss than half an inch per
capacitor lead. Boards should employ separat e inner layers for power and GND planes.
All output pins on the MPC8280 have fast rise and fall times. Printed circuit (PC) trace interconnection length should
be minim ized t o minimize ove rdampe d conditi ons and re flectio ns caus ed by the se fast output swit chi ng times. Th is
recommendation particularly applies to the address and data buses. Maximum PC trace lengths of six inches are
recommended. Capacitance calculations should consider all device loads as well as parasitic capacitances due to the
PC traces. Attention to proper PCB layout and bypassing becomes espec ially critical in systems with higher
capacitive loads because these loads create higher transient currents in the VDD and GND circuits. Pull up all
unused inp uts or signals that will be inputs dur ing reset. Special care should be t aken to minimize the noise levels
on the PLL supply pins.
5 Power Dissipation
Table 7 provides preliminary, estimated power dissipation for various configurations. Note that suitable thermal
management i s required to ensure the junc tion temperature does not e xceed the maximum spe cified value. Also note
that the I/O power should be included when determi ning whether to use a heat sink. For a complete list of possible
clock configurations, refer to Section 7, “Clock Configuration Mode s.”
MPC8280 PowerQUI CC™ II Famil y Hardw are Sp ecif ications , Rev. 1.8
14 Freescale Semiconductor
AC Electrical Characteri sti cs
6 AC E lectrical Ch aracteristi cs
The following sections include illustra tions and tables of clock diagrams, signals, and CPM outputs and inputs for
66.67/83.33/100 MHz device s. Note that AC timings are based on a 50-pf load for MAX Delay and 10-pf load for
MIN delay. Typical output buf fer impedances are shown in Table 8.
Ta bl e 7 . Esti m at ed P ower Dissi pation for Various Configu rat i on s 1
1
Test temperature = 105° C
Bus
(MHz)
CPM
Multiplication
Factor
CPM
(MHz)
CPU
Multiplication
Factor
CPU
(MHz)
PINT(W) 2, 3
2
PINT = IDD x VDD Watts
3
Values do not incl ude I/O. Add the foll owing estimat es for active I/O b ased on the following bus speeds:
66.7 MHz = 0.45 W (nominal), 0.5 W (m aximum )
83.3 MHz = 0.5W (nominal), 0.6 W (maximum)
100 MHz = 0.6 W (nominal), 0.7 W (maxi mum )
Vddl 1.5 Volts
Nominal Maximum
66.67 2.5 166 3.5 233 0.95 1.0
66.67 2.5 166 4 266 1.0 1.05
66.67 3 200 4 266 1.05 1.1
66.67 3.5 233 4.5 300 1.05 1.15
83.33 3 250 4 333 1.25 1.35
83.33 3 250 4.5 375 1.3 1.4
83.33 3.5 292 5 417 1.45 1.55
100 3 300 4 400 1.5 1.6
100 3 300 4.5 450 1.55 1.65
Table 8 . Output B uffe r Impedances 1
1
These are typical values at 65° C. Impedance may vary by ±25% with process and temperature.
Output Buff ers Typical Impedance (Ω)
60x bus 45 or 27 2
2
On sili con revisi on 0.0 (ma sk #: 0K49M), selectable impedance is not avai lable. Imp edance is set at 45 Ω.
On all ot her revisions, impedance value is selected throug h the SIUMCR[ 20,21]. Ref er to the MPC8280
PowerQUICC II Fam ily Reference Manual .
Local bus 45
Memory controlle r 45 or 272
Pa r al le l I/O 45
PCI 27
MPC8280 PowerQUI CC™ II Famil y Hardw are Sp ecif ications, Rev. 1.8
Freescale Semiconductor 15
AC Electr ical Characteri stics
6.1 CPM AC Characteristics
Table 9 lists CPM output characteristics.
Table 10 lists CPM input characteristics.
NOTE: Rise/Fall Time on CPM Input Pins
The rise/fa ll time on CPM input pins should not exceed 5 ns. This should be
enforced especially on cloc k signals. Rise time refers to signal transitions from
10% to 90% of VCC; fall time refers to transitio ns from 90% to 10% of VCC.
Table 9. AC Characteristics for CPM Outputs 1
1
Output specif icat ions ar e meas ure d from t he 50% level of t he ris ing edg e of CLKIN t o the 50 % lev el of the si gnal. T imi ngs a re
measured at the pin.
Spec Number Characterist ic Valu e (ns)
Max Min Maximum Delay Mini mum Delay
66 MHz 83 MHz 100 MHz 66 M Hz 83 MHz 100 MHz
sp36a sp37a FCC outputs—inter nal c lock (NMSI) 6 5.5 5.5 0.5 0.5 0.5
sp36b sp37b FCC outputs—external clock (NMSI) 8 8 8 2 2 2
sp38a sp39a SCC/SMC/SPI/I2C outputs— int ernal
clock (NMSI) 10 10 10 0 0 0
sp38b sp39b SCC/SMC/SPI/I2C outputs—external
clock (NMSI) 888222
sp40 sp41 TDM outputs/ SI 11 11 11 2.5 2.5 2.5
sp42 sp43 TIMER/IDMA outputs 11 11 11 0.5 0.5 0.5
sp42a sp43a PIO outputs 11 11 11 0.5 0.5 0.5
Table 10. AC Characteristics for CPM Inputs 1
1
Input specificatio ns are measured from the 50% level of the signal to the 50% level of the ris ing ed ge of CLKIN. Timings are
measured at the pin.
Spec Number
Characteristic
Value (ns)
Setup Hold Setup Hold
66 MHz 83 MHz 100 MHz 66 MHz 83 MHz 100 MHz
sp16a sp17a FCC inputs—inter nal c lock (NMSI) 666000
sp16b sp17b FCC inputs—external clock (NMSI) 2.5 2.5 2.5 2 2 2
sp18a sp19a SCC/SMC/SPI /I 2C inputs—internal clock
(NMSI) 666000
sp18b sp19b SCC/SMC/SPI/I2C inputs—external cloc k
(NMSI) 444222
sp20 sp21 TDM inputs/SI 5 5 5 2.5 2.5 2.5
sp22 sp23 PIO/TIMER/IDMA inputs 8 8 8 0.5 0.5 0.5
MPC8280 PowerQUI CC™ II Famil y Hardw are Sp ecif ications , Rev. 1.8
16 Freescale Semiconductor
AC Electrical Characteri sti cs
NOTE
Although the s pecifications gene rally reference the rising edge of the clock, the
following AC timing diagrams also apply when the fal ling edge is the active edge.
Figure 3 shows the FCC internal clock.
Figure 3. FCC Internal Clock Diagram
Figure 4 shows the FCC ext ernal clock.
Figure 4. FCC External Clock Diagram
BRG_OUT
FCC input signals
FCC output signals
FCC output signals
Note: Wh en GFM R.[T C I] = 1
Note: When GFMR[TCI] = 0 sp36a/sp37a
sp36a/sp37a
sp17a
sp16a
Serial ClKi n
FCC input signals
FCC output signals
FCC output signals
Note: When GFMR[TCI] = 1
Note: When GFMR[TCI] = 0
sp16b sp17b
sp36b/sp37b
sp36b/sp37b
MPC8280 PowerQUI CC™ II Famil y Hardw are Sp ecif ications, Rev. 1.8
Freescale Semiconductor 17
AC Electr ical Characteri stics
Figure 5 shows the SCC/SMC/SPI/I2C ext ernal clock.
Figu re 5. SCC/SMC/SPI /I2C External Clock Diagram
Figure 6 shows the SCC/SMC/SPI/I2C internal clock.
Figure 6. SCC/SMC/SPI/I2C Internal Clock Diagram
Serial CLKin
SCC/SMC/SPI/I2C input signals
SCC/SMC/SPI/I2C output signals
sp18b sp19b
sp38b/sp39b
(See note)
(See note)
Note: There are four possible timing conditions for SCC and SPI:
1. Input sampled on t he risin g edge and output driv en on the ris ing edge (shown).
2. Input sampled on the rising edge and output driven on the falling edge.
3. Input sampled on the falling edge and output driven on the falling edge.
4. Input sampled on the falling edge and output driven on the rising edge.
BRG_OUT
SCC/SMC/SPI /I 2C input signals
SCC/SMC/SPI /I 2C output signals
sp18a sp19a
sp38a/sp39a
(See note)
(See note)
Note: Ther e are four possible timing conditions for SCC and SPI:
1. Input sampled on the rising edge and output driven on the rising edge (shown).
2. Input sampled on the r ising edge and output dr iven on the falling edge.
3. Input sampled on the falling edge and output driven on the falling edge.
4. Input sampled on the f alling edge and output driven on the rising edge.
MPC8280 PowerQUI CC™ II Famil y Hardw are Sp ecif ications , Rev. 1.8
18 Freescale Semiconductor
AC Electrical Characteri sti cs
Figure 7 shows TDM input and output signals.
Figu re 7. TDM Signal Diagram
Figure 8 shows PIO and t imer si gna ls.
Figure 8. PIO and Ti mer Signal Diagram
Seria l CLKin
TDM input sig nals
TD M output s ignals
sp20 sp21
sp40/sp41
Note: Ther e are four possible TDM tim ing condit ions:
1. Input sampled on the ri sing edge and output driven o n the rising edge (shown).
2. Input sampled on the rising edge and output dr iven on the falling edge.
3. Input sampled on the falling edge and output driven on the falling edge.
4. Input sampled on the falling edge and output driven on the rising edge.
Sys clk
PIO/IDMA/TIMER[TGATE assertion] input signals
IDMA output s ignals
sp22
sp23
sp42/sp43
TIMER(sp42/43) / PIO(sp42a/s p43a)
sp42a/sp43a
output signals
sp42/sp43
TIMER input signal [TGATE deasserti on] sp22 sp23
Note: TGATE is asserted on the r ising edge of the clo ck; it is deassert ed on the falling ed ge.
(See note)
(See note)
MPC8280 PowerQUI CC™ II Famil y Hardw are Sp ecif ications, Rev. 1.8
Freescale Semiconductor 19
AC Electr ical Characteri stics
6.2 SIU AC Characteristics
Note the following points abou t the SIU AC characteristic s:
•CLKIN jitter and duty cycle. The CLKIN input to the MPC8280 should not exceed +/– 150 psec of jitter
(peak-to-peak) . This rep resents total input jitter—the combination of short term (cycle - to-cycle) and long
term (cumulative). The duty cycle of CLKIN should not exce ed the ratio of 40:60. The rise/file time of
CLKIN should adh ere to the t ypical SDRAM device AC clock re quire ment of 1 V/ns to meet SDRAM AC
specs.
•Spread spe ctrum clocking. Is allowed with 1% input frequency down-s pread at maximum 60 KHz
modulation rate regardless of input frequency.
•PCI AC timing. The MPC8280 meets the timing re quirements of PCI Specific ation Revisi on 2.2. Refer to
Sections 7.2 and 7.3 and “Note: Tval (Outp ut Hold)” to determine if a specific cloc k co nfiguration is
compliant.
• Activati ng data pipelining (s et ting BRx[DR] in the memory cont roller) improv es the AC timing.
Table 11 l ists SIU input characte ristics.
Table 12 lists SIU output characteristics.
Table 11. AC Characteristics for SIU In puts 1
1
Input specificati ons are meas ured from t he 50% leve l of the signal to t he 50% leve l of the rising edge of CLKIN. Tim ings are
measured at the pin.
Spec Number
Characteristic
Value (ns)
Setup Hold Setup Hold
66 MHz 83 MHz 100 MHz 66 MHz 83 MHz 100 MHz
sp11 sp10 AACK/TA/TS/DBG/BG/BR/ARTRY/
TEA 6 5 3.5 0.5 0.5 0.5
sp12 sp10 Data bus in norma l mode 5 4 3.5 0.5 0.5 0. 5
sp13 sp10 Data bus in ECC and PARITY modes 7 5 3.5 0.5 0.5 0.5
sp13a sp10 Pipe li ne m ode— Data bus (with or wit hout
ECC/PARITY) 5 4 2.5 0.5 0.5 0.5
sp14 sp10 DP pins 7 5 3.5 0.5 0.5 0. 5
sp14a sp10 Pipe li ne m ode— DP pins — 4 2.5 — 0.5 0.5
sp15 sp10 All other pins 5 4 3.5 0.5 0.5 0.5
Table 12. AC Ch aracteristi cs for SIU Outputs 1
Spec Number
Characteristic
Val ue (ns)
Max Min Maximu m Delay Minimum Delay
66 MHz 83 MHz 100 MHz 66 MHz 83 MHz 100 MHz
sp31 sp30 PSDVAL/TEA/TA 765.5111
sp32 sp30 ADD/ADD_atr./BADDR/CI/GBL/WT 8 6.5 5.5 1 1 1
sp33a sp30 Data bus 2 6.5 6.5 5.5 0.7 0.7 0.7
MPC8280 PowerQUI CC™ II Famil y Hardw are Sp ecif ications , Rev. 1.8
20 Freescale Semiconductor
AC Electrical Characteri sti cs
Figure 9 shows the interaction of several bus signals.
Figure 9. Bus Signals
sp33b sp30 DP 6 5.5 5.5 1 1 1
sp34 sp30 Memory controlle r signals/ALE 6 5.5 5.5 1 1 1
sp35 sp30 All other signals 6 5.5 5.5 1 1 1
sp35a sp30 AP 777111
1
Output s pecifica tions ar e meas ured f rom the 50% l eve l of the r ising edg e of CLKI N to t he 50% leve l of th e signa l. Timi ngs ar e
measured at the pin.
2
To achieve 1 ns of hold time at 66, 83, or 100 MHz, a minimum loading of 20 pF is required.
Table 12. AC Ch aracteristi cs for SIU Outputs 1
Spec Number
Characteristic
Val ue (ns)
Max Min Maximu m Delay Minimum Delay
66 MHz 83 MHz 100 MHz 66 MHz 83 MHz 100 MHz
MPC8280 PowerQUI CC™ II Famil y Hardw are Sp ecif ications, Rev. 1.8
Freescale Semiconductor 21
AC Electr ical Characteri stics
Figure 10 shows signal behavior for all parity modes (including ECC, RMW parity, and standard parity).
Figure 10. Parity Mode Diagram
Figure 11 shows signal beha vior in MEMC mode.
Figure 11. M EM C Mode Di a gram
NOTE
Generally, all MPC8280 bus and system output signals are driven from the rising
edge of the input clock (CLKin). Memory controller signals, however, trigger on
four points within a C LKin cycle. Each cycle is divi ded by four internal ticks : T1,
T2, T3, and T4. T1 always occurs a t the ris ing edge, and T3 at the falling edge, of
CLKin. However, the spacing of T2 and T4 depends on the PLL clock ratio
select ed , as shown in Table 13.
CLKin
DATA bus, ECC, and PARITY mode
Pipeline m ode—
DP mode output signal
sp13
sp10
sp14a
sp10
Pipeline m ode—
sp10
DP mode input signal
sp14
sp10
DATA bus, ECC, and PARITY mode
DP mode input signal
input signals
input signals
sp30
sp33b
sp13a
CLKin
V_CLK
Memory controller signals sp34/sp30
MPC8280 PowerQUI CC™ II Famil y Hardw are Sp ecif ications , Rev. 1.8
22 Freescale Semiconductor
AC Electrical Characteri sti cs
Figure 12 is a re presentation of the information in Table 13.
Figure 12. Internal Tick Spacing for Memo ry Con troller Signa ls
NOTE
The UPM machine outputs change on the i nternal tick determi ned by the me mory
controller programming; the AC specifications are relative to the internal tick. The
SDRAM and GPCM machine outputs change on CLKin’s rising edge.
6.3 JTAG Ti mings
Table 14 lists the JTAG timings.
Table 13. Tick Spacing for Memo ry Con troller Signa ls
PLL Clock Ratio Tick Spacing (T1 Occurs at the Rising Edge of CLKin)
T2 T3 T4
1:2, 1:3, 1:4, 1:5, 1:6 1/4 CLKin 1/2 CLKin 3/4 CLKin
1:2.5 3/10 CLKin 1/2 CLKin 8/10 CLKin
1:3.5 4/14 CLKin 1/2 CLKin 11/14 CLKin
Table 14. JTAG Timings1
Parameter Symbol2Min Max Unit Notes
JTAG external clock frequency of oper ation fJTG 0 33.3 MHz
JTAG external clock cy cle time tJTG 30 — ns
JTAG external clock pulse width mea sured at 1.4V tJTKHKL 15 — ns
JTAG external clock rise a nd fal l times tJTGR and
tJTGF
05ns6
TRST asse rt time tTRST 25 — ns 3, 6
Input setup times Boundary-scan data
TMS, TDI tJTDVKH
tJTIVKH
4
4—
—ns
ns
4, 7
4, 7
CLKin
T1 T2 T3 T4
CLKin
T1 T2 T3 T4
for 1:2 .5
for 1:3 .5
CLKin
T1 T2 T3 T4
for 1:2, 1:3, 1:4, 1:5, 1:6
MPC8280 PowerQUI CC™ II Famil y Hardw are Sp ecif ications, Rev. 1.8
Freescale Semiconductor 23
Clock Confi guration Modes
7 Clock Configuration Modes
The MPC8280 has thre e clocking modes: local, PCI host, and PCI age nt. The clocki ng mode is set according to three
input pins—PCI_MODE, PCI_CFG[0], PCI_MODCK—as shown in Table 15.
Input hold times Boundary-scan data
TMS, TDI tJTDXKH
tJTIXKH
10
10 —
—ns
ns
4, 7
4, 7
Output valid times Boundary-scan data
TDO tJTKLDV
tJTKLOV
—
—10
10 ns
ns
5, 7
5. 7
Output hol d times Boundary-scan data
TDO tJTKLDX
tJTKLOX
1
1—
—ns
ns
5, 7
5, 7
JTAG external clock to output high impedance
Boundary-scan data
TDO tJTKLDZ
tJTKLOZ
1
110
10 ns
ns
5, 6
5, 6
1All output s are measur ed from the midpoin t volta ge of the falling/risi ng edge of tTCLK to the mi dpoint o f the signa l in que stion.
The output timings are measured at the pins. All o utput timings assume a purely resistive 50-Ω load. Time- of-flight delays
must b e added for trace lengths, via s, and co nnectors in t he system.
2The symbols used for timing specificatio ns herein foll ow the pattern of t(first two letters o f functional b lock)(signal)(state) (refere nce)(state)
for in puts and t((first two letters of functi onal block)(reference)(state)(si gn al)(state) for outputs. For example, tJTDVKH symb oli zes J TAG
device timing (JT) with respect to the time data input signals (D) reaching the valid state (V) relative to the tJTG clock reference
(K) goi ng to the h igh (H) state or setup ti m e. Also, tJTDXKH symboli zes J TAG timi ng (JT) with respect to the time data input
signal s (D) went inval id (X) relati ve to t he tJTG cl ock refe rence (K) going to the high ( H) stat e. Note t hat, i n general , the cl ock
refer ence symbol representat ion is based on three letters representi ng the c lock of a particular functional. For ri se and fall
times, the latter conve nti on is used with the appropriate letter: R (rise) o r F (fall ).
3TRST is an asynchronous le vel s ensitive signal. The setup time is for test purposes only.
4Non-JTAG signal input timing with respect to tTCLK.
5Non-JTAG signal output timing with respect to tTCLK.
6Guaranteed by design.
7Guaranteed by design and device characterization.
T ab le 15. MPC8280 Clocking Modes
Pins Clocking Mode PCI Clock
Frequency Range
(MHZ) Reference
PCI_MODE PCI_CFG[0] PCI_MODCK 1
1
Determines PCI clock frequency range. Refer to Sections 7.2 and 7.3 .
1 — — Local bus — Table 16
0 0 0 PCI host 50–66 Table 17
0 0 1 25–50 Table 18
0 1 0 PCI agent 50–66 Table 19
0 1 1 25–50 Table 20
Table 14. JTAG Timi ngs1 (continued)
Parameter Symbol2Min Max Unit Notes
MPC8280 PowerQUI CC™ II Famil y Hardw are Sp ecif ications , Rev. 1.8
24 Freescale Semiconductor
Clock Configuration Modes
In each c locking mode, the c onfiguration of bus , core, PCI, a nd CPM frequencies is dete rmined by seven bit s during
the power- up reset—t hree hardware configura tion pins (MODCK[1–3]) and four bits from har dware configuration
word[28–31] (MODCK_H). Both the PLLs and the dividers are set according to the selecte d MPC8280 clock
operation mode as described in the following sections.
7.1 Local Bus Mode
Table 16 lists clock con figurations f or the MPC8280 in local b us mode. The frequencies list ed are for the purpose
of illustration only. Us ers must s elect a mode and input bus frequency so that the resulting configur ation does not
exceed the frequency rating of the use r’s devic e.
NOTE
Clock configurations change only after PORESET is assert ed.
Table 16. Clock Configurations for Local Bus Mode 1
Mode 2 Bus Clock 3
(MHz) CPM
Multiplication
Factor 4
CPM Clock
(MHz) CPU
Multiplication
Factor 5
CPU Clock
(MHz)
MODCK_H-MODCK[1:3] Low High Low High Low High
Defaul t Modes (MODCK_H= 0000)
0000_000 37.5 133.3 3 112.5 400.0 4 150.0 533.3
0000_001 33.3 133.3 3 100.0 400.0 5 166.7 666.7
0000_010 37.5 100.0 4 150.0 400.0 4 150.0 400.0
0000_011 30.0 100.0 4 120.0 400.0 5 150.0 500.0
0000_100 60.0 167.0 2 120.0 334.0 2.5 150.0 417.5
0000_101 50.0 167.0 2 100.0 334.0 3 150.0 501.0
0000_110 60.0 160.0 2.5 150.0 400.0 2.5 150.0 400.0
0000_111 50.0 160.0 2.5 125.0 400.0 3 150.0 480.0
Full Conf iguration Modes
0001_000 50.0 167.0 2 100.0 334.0 4 200.0 668.0
0001_001 50.0 167.0 2 100.0 334.0 5 250.0 835.0
0001_010 50.0 145.8 2 100.0 291.7 6 300.0 875.0
0001_011 Reserved
0001_100 Reserved
0001_101 37.5 133.3 3 112.5 400.0 4 150.0 533.3
0001_110 33.3 133.3 3 100.0 400.0 5 166.7 666.7
1000_111 33.3 133.3 3 100.0 400.0 5.5 183.3 733.3
0001_111 33.3 133.3 3 100.0 400.0 6 200.0 800.0
0010_000 Reserved
0010_001 Reserved
MPC8280 PowerQUI CC™ II Famil y Hardw are Sp ecif ications, Rev. 1.8
Freescale Semiconductor 25
Clock Confi guration Modes
0010_010 37.5 100.0 4 150.0 400.0 4 150.0 400.0
0010_011 30.0 100.0 4 120.0 400.0 5 150.0 500.0
0010_100 25.0 100.0 4 100.0 400.0 6 150.0 600.0
0010_101 25.0 100.0 4 100.0 400.0 7 175.0 700.0
0010_110 25.0 100.0 4 100.0 400.0 8 200.0 800.0
0010_111 Reserved
0011_000 30.0 80.0 5 150.0 400.0 5 150.0 400.0
0011_001 25.0 80.0 5 125.0 400.0 6 150.0 480.0
0011_010 25.0 80.0 5 125.0 400.0 7 175.0 560.0
0011_011 25.0 80.0 5 125.0 400.0 8 200.0 640.0
0011_100 Reserved
0011_101 Reserved
0011_110 25.0 66.7 6 150.0 400.0 6 150.0 400.0
0011_111 25.0 66.7 6 150.0 400.0 7 175.0 466.7
0100_000 25.0 66.7 6 150.0 400.0 8 200.0 533.3
0101_101 75.0 167.0 2 150.0 334.0 2 166.7 334.0
0101_110 60.0 167.0 2 120.0 334.0 2.5 166.7 417.5
0101_111 50.0 167.0 2 100.0 334.0 3 200.0 501.0
0110_000 50.0 167.0 2 100.0 334.0 3.5 250.0 584.5
0110_001 50.0 167.0 2 100.0 334.0 4 250.0 668.0
0110_010 50.0 167.0 2 100.0 334.0 4.5 250.0 751.5
0110_011 Reserved
0110_100 60.0 160.0 2.5 150.0 400.0 2.5 150.0 400.0
0110_101 50.0 160.0 2.5 125.0 400.0 3 150.0 480.0
0110_110 42.9 160.0 2.5 107.1 400.0 3.5 150.0 560.0
0110_111 40.0 160.0 2.5 100.0 400.0 4 160.0 640.0
0111_000 40.0 160.0 2.5 100.0 400.0 4.5 180.0 720.0
Table 16. Clock Configurations for Local Bus Mode 1 (co ntinued)
Mode 2 Bus Clock 3
(MHz) CPM
Multiplication
Factor 4
CPM Clock
(MHz) CPU
Multiplication
Factor 5
CPU Clock
(MHz)
MODCK_H-MODCK[1:3] Low High Low High Low High
MPC8280 PowerQUI CC™ II Famil y Hardw are Sp ecif ications , Rev. 1.8
26 Freescale Semiconductor
Clock Configuration Modes
0111_001 Reserved
0111_010 Reserved
0111_011 50.0 133.3 3 150.0 400.0 3 150.0 400.0
0111_100 42.9 133.3 3 128.6 400.0 3.5 150.0 466.7
0111_101 37.5 133.3 3 112.5 400.0 4 150.0 533.3
0111_110 33.3 133.3 3 100.0 400.0 4.5 150.0 600.0
0111_111 Reserved
1000_000 Reserved
1000_001 Reserved
1000_010 42.9 114.3 3.5 150.0 400.0 3.5 150.0 400.0
1000_011 37.5 114.3 3.5 131.3 400.0 4 150.0 457.1
1000_100 33.3 114.3 3.5 116.7 400.0 4.5 150.0 514.3
1000_101 30.0 114.3 3.5 105.0 400.0 5 150.0 571.4
1000_110 28.6 114.3 3.5 100.0 400.0 5.5 150.0 628.6
1100_000 Reserved
1100_001 Reserved
1100_010 Reserved
1101_000 Reserved
1
The “lo w” values are the minimum all owable frequencies for a give n clock mode. The minimum bus freque ncy in a table entry
guarantees only the required minimum CPU operat ing frequency. The “high” values ar e for the purpose of illustration only.
Users mu st sel ect a mode and i nput bus f req uency so th at the re sulti ng co nfigurat ion does no t vi olat e the fre quency rat ing of
the u ser’s d evi ce. The minimum CPM fr eque ncy i s 1 20 MHz. Mini mum CPU freque ncy is de term ined b y the cl ock m ode. For
modes with a CPU mul tiplication factor <= 3, the minimum CPU fr equency is 150 MHz for commercial temperature devices
and 175 M Hz for e xtended t emper ature d evices. For m odes wit h a CPU multi plic ation factor >= 3. 5: for Rev0 .1 the mi nimum
CPU frequency is 250 MHz; f or RevA or later the minimum CPU fr equency is 150 MHz for commercial temperatur e devices
and 175 MHz for extended temperature devices.
2
MODCK_H = hard reset conf iguration word [28–31]. MODCK[1-3] = three hardwar e configuration pins.
3
60x and local bus frequency. Identical to CLKIN.
4
CPM multiplication factor = CPM clock/bus clock
5
CPU multiplication factor = Core PLL multiplication factor
Table 16. Clock Configurations for Local Bus Mode 1 (co ntinued)
Mode 2 Bus Clock 3
(MHz) CPM
Multiplication
Factor 4
CPM Clock
(MHz) CPU
Multiplication
Factor 5
CPU Clock
(MHz)
MODCK_H-MODCK[1:3] Low High Low High Low High
MPC8280 PowerQUI CC™ II Famil y Hardw are Sp ecif ications, Rev. 1.8
Freescale Semiconductor 27
Clock Confi guration Modes
7.2 PCI Host Mode
Table 17 and Table 18 show clock con figurations fo r PCI host mode. The freq uencies listed are for the purpose of
illustration only. Users must select a mode and input bus frequency so that the resulting configuration does not
exceed the frequency rating of the use r’s device. In addition, note the following:
NOTE: PCI_ MO DCK
In PCI mode only, PCI_MODCK comes from the LGPL5 pin and
MODCK_H[0–3] comes fr om {LG PL0, LGPL1, LGPL2, LGP L3}.
NOTE: Tva l (Output Hold)
The mini mum Tval = 2 ns when PCI_MODCK = 1, and the minimum Tval = 1 ns
when PCI_M ODCK = 0. Therefore, designers sh ould use cl ock co nfigur ations that
fit thi s condition to achiev e PCI-comp liant AC timing.
Table 17. Clock Co nfigurations for PCI Ho st M ode (PCI_M ODCK=0) 1, 2
Mode 3 Bus Clock 4
(MHz) CPM
Multiplication
Factor 5
CPM Clock
(MHz) CPU
Multiplication
Factor 6
CPU Clock
(MHz) PCI
Division
Factor
PCI Clock
(MHz)
MODCK_H-
MODCK[1-3] Low High Low High Low High Low High
Defaul t Modes (MODCK_H=0000)
0000_000 60.0 66.7 2 120.0 133.3 2.5 150.0 166.7 2 60.0 66.7
0000_001 50.0 66.7 2 100.0 133.3 3 150.0 200.0 2 50.0 66.7
0000_010 60.0 80.0 2.5 150.0 200.0 3 180.0 240.0 3 50.0 66.7
0000_011 60.0 80.0 2.5 150.0 200.0 3.5 210.0 280.0 3 50.0 66.7
0000_100 60.0 80.0 2.5 150.0 200.0 4 240.0 320.0 3 50.0 66.7
0000_101 50.0 66.7 3 150.0 200.0 3 150.0 200.0 3 50.0 66.7
0000_110 50.0 66.7 3.5 150.0 200.0 3.5 175.0 233.3 3 50.0 66.7
0000_111 50.0 66.7 3 150.0 200.0 4 200.0 266.6 3 50.0 66.7
Full Conf iguration Modes
0001_000 50.0 66.7 3 150.0 200.0 5 250.0 333.3 3 50.0 66.7
0001_001 50.0 66.7 3 150.0 200.0 6 300.0 400.0 3 50.0 66.7
0001_010 50.0 66.7 3 150.0 200.0 7 350.0 466.6 3 50.0 66.7
0001_011 50.0 66.7 3 150.0 200.0 8 400.0 533.3 3 50.0 66.7
0010_000 50.0 66.7 4 200.0 266.6 5 250.0 333.3 4 50.0 66.7
0010_001 50.0 66.7 4 200.0 266.6 6 300.0 400.0 4 50.0 66.7
0010_010 50.0 66.7 4 200.0 266.6 7 350.0 466.6 4 50.0 66.7
0010_011 50.0 66.7 4 200.0 266.6 8 400.0 533.3 4 50.0 66.7
MPC8280 PowerQUI CC™ II Famil y Hardw are Sp ecif ications , Rev. 1.8
28 Freescale Semiconductor
Clock Configuration Modes
0010_100 75.0 100.0 4 300.0 400.0 5 375.0 500.0 6 50.0 66.7
0010_101 75.0 100.0 4 300.0 400.0 5.5 412.5 549.9 6 50.0 66.7
0010_110 75.0 100.0 4 300.0 400.0 6 450.0 599.9 6 50.0 66.7
0011_000 50.0 66.7 5 250.0 333.3 5 250.0 333.3 5 50.0 66.7
0011_001 50.0 66.7 5 250.0 333.3 6 300.0 400.0 5 50.0 66.7
0011_010 50.0 66.7 5 250.0 333.3 7 350.0 466.6 5 50.0 66.7
0011_011 50.0 66.7 5 250.0 333.3 8 400.0 533.3 5 50.0 66.7
0100_000 Reserved
0100_001 50.0 66.7 6 300.0 400.0 6 300.0 400.0 6 50.0 66.7
0100_010 50.0 66.7 6 300.0 400.0 7 350.0 466.6 6 50.0 66.7
0100_011 50.0 66.7 6 300.0 400.0 8 400.0 533.3 6 50.0 66.7
0101_000 60.0 66.7 2 120.0 133.3 2.5 150.0 166.7 2 60.0 66.7
0101_001 50.0 66.7 2 100.0 133.3 3 150.0 200.0 2 50.0 66.7
0101_010 50.0 66.7 2 100.0 133.3 3.5 175.0 233.3 2 50.0 66.7
0101_011 50.0 66.7 2 100.0 133.3 4 200.0 266.6 2 50.0 66.7
0101_100 50.0 66.7 2 100.0 133.3 4.5 225.0 300.0 2 50.0 66.7
0110_000 60.0 80.0 2.5 150.0 200.0 2.5 150.0 200.0 3 50.0 66.7
0110_001 60.0 80.0 2.5 150.0 200.0 3 180.0 240.0 3 50.0 66.7
0110_010 60.0 80.0 2.5 150.0 200.0 3.5 210.0 280.0 3 50.0 66.7
0110_011 60.0 80.0 2.5 150.0 200.0 4 240.0 320.0 3 50.0 66.7
0110_100 60.0 80.0 2.5 150.0 200.0 4.5 270.0 360.0 3 50.0 66.7
0110_101 60.0 80.0 2.5 150.0 200.0 5 300.0 400.0 3 50.0 66.7
0110_110 60.0 80.0 2.5 150.0 200.0 6 360.0 480.0 3 50.0 66.7
0111_000 Reserved
0111_001 50.0 66.7 3 150.0 200.0 3 150.0 200.0 3 50.0 66.7
0111_010 50.0 66.7 3 150.0 200.0 3.5 175.0 233.3 3 50.0 66.7
0111_011 50.0 66.7 3 150.0 200.0 4 200.0 266.6 3 50.0 66.7
Table 17. Clock Co nfigura tions for PCI Host Mo de (PCI_MODCK=0) 1, 2 (co ntinued)
Mode 3 Bus Clock 4
(MHz) CPM
Multiplication
Factor 5
CPM Clock
(MHz) CPU
Multiplication
Factor 6
CPU Clock
(MHz) PCI
Division
Factor
PCI Clock
(MHz)
MODCK_H-
MODCK[1-3] Low High Low High Low High Low High
MPC8280 PowerQUI CC™ II Famil y Hardw are Sp ecif ications, Rev. 1.8
Freescale Semiconductor 29
Clock Confi guration Modes
0111_100 50.0 66.7 3 150.0 200.0 4.5 225.0 300.0 3 50.0 66.7
1000_000 Reserved
1000_001 66.7 88.9 3 200.0 266.6 3 200.0 266.6 4 50.0 66.7
1000_010 66.7 88.9 3 200.0 266.6 3.5 233.3 311.1 4 50.0 66.7
1000_011 66.7 88.9 3 200.0 266.6 4 266.7 355.5 4 50.0 66.7
1000_100 66.7 88.9 3 200.0 266.6 4.5 300.0 400.0 4 50.0 66.7
1000_101 66.7 88.9 3 200.0 266.6 6 400.0 533.3 4 50.0 66.7
1000_110 66.7 88.9 3 200.0 266.6 6.5 433.3 577.7 4 50.0 66.7
1001_000 Reserved
1001_001 Reserved
1001_010 57.1 76.2 3.5 200.0 266.6 3.5 200.0 266.6 4 50.0 66.7
1001_011 57.1 76.2 3.5 200.0 266.6 4 228.6 304.7 4 50.0 66.7
1001_100 57.1 76.2 3.5 200.0 266.6 4.5 257.1 342.8 4 50.0 66.7
1001_101 85.7 114.3 3.5 300.0 400.0 5 428.6 571.4 6 50.0 66.7
1001_110 85.7 114.3 3.5 300.0 400.0 5.5 471.4 628.5 6 50.0 66.7
1001_111 85.7 114.3 3.5 300.0 400.0 6 514.3 685.6 6 50.0 66.7
1010_000 75.0 100.0 2 150.0 200.0 2 150.0 200.0 3 50.0 66.7
1010_001 75.0 100.0 2 150.0 200.0 2.5 187.5 250.0 3 50.0 66.7
1010_010 75.0 100.0 2 150.0 200.0 3 225.0 300.0 3 50.0 66.7
1010_011 75.0 100.0 2 150.0 200.0 3.5 262.5 350.0 3 50.0 66.7
1010_100 75.0 100.0 2 150.0 200.0 4 300.0 400.0 3 50.0 66.7
1011_000 Reserved
1011_001 80.0 106.7 2.5 200.0 266.6 2.5 200.0 266.6 4 50.0 66.7
1011_010 80.0 106.7 2.5 200.0 266.6 3 240.0 320.0 4 50.0 66.7
1011_011 80.0 106.7 2.5 200.0 266.6 3.5 280.0 373.3 4 50.0 66.7
1011_100 80.0 106.7 2.5 200.0 266.6 4 320.0 426.6 4 50.0 66.7
1011_101 80.0 106.7 2.5 200.0 266.6 4.5 360.0 480.0 4 50.0 66.7
Table 17. Clock Co nfigura tions for PCI Host Mo de (PCI_MODCK=0) 1, 2 (co ntinued)
Mode 3 Bus Clock 4
(MHz) CPM
Multiplication
Factor 5
CPM Clock
(MHz) CPU
Multiplication
Factor 6
CPU Clock
(MHz) PCI
Division
Factor
PCI Clock
(MHz)
MODCK_H-
MODCK[1-3] Low High Low High Low High Low High
MPC8280 PowerQUI CC™ II Famil y Hardw are Sp ecif ications , Rev. 1.8
30 Freescale Semiconductor
Clock Configuration Modes
1101_000 100.0 133.3 2.5 250.0 333.3 3 300.0 400.0 5 50.0 66.7
1101_001 100.0 133.3 2.5 250.0 333.3 3.5 350.0 466.6 5 50.0 66.7
1101_010 100.0 133.3 2.5 250.0 333.3 4 400.0 533.3 5 50.0 66.7
1101_011 100.0 133.3 2.5 250.0 333.3 4.5 450.0 599.9 5 50.0 66.7
1101_100 100.0 133.3 2.5 250.0 333.3 5 500.0 666.6 5 50.0 66.7
1101_101 125.0 166.7 2 250.0 333.3 3 375.0 500.0 5 50.0 66.7
1101_110 125.0 166.7 2 250.0 333.3 4 500.0 666.6 5 50.0 66.7
1110_000 100.0 133.3 3 300.0 400.0 3.5 350.0 466.6 6 50.0 66.7
1110_001 100.0 133.3 3 300.0 400.0 4 400.0 533.3 6 50.0 66.7
1110_010 100.0 133.3 3 300.0 400.0 4.5 450.0 599.9 6 50.0 66.7
1110_011 100.0 133.3 3 300.0 400.0 5 500.0 666.6 6 50.0 66.7
1110_100 100.0 133.3 3 300.0 400.0 5.5 550.0 733.3 6 50.0 66.7
1100_000 Reserved
1100_001 Reserved
1100_010 Reserved
1
The “lo w” valu es ar e the mi nim um allowa ble fr equenci es f or a gi ven cl ock mode. The mini mum bus freque ncy in a ta ble ent ry
guarantees only th e requi red minimum CPU operating frequency. The “high” values are for t he purpose of illustration on ly.
Users must select a mode and input bus frequency so that t he result ing configuration does not violat e the frequency rati ng of
the user’ s devi ce. The mini mum CPM f requency is 120 MHz. Minim um CPU frequ ency is det ermined by t he cl ock mod e. For
modes with a CPU multiplication factor <= 3, the minimum CPU frequency is 150 MHz for com m ercial temperature devices
and 175 MHz for ext ended tem peratu re devic es. For modes wi th a CPU mult ipli cati on facto r >= 3.5: for Rev0. 1 the m inimum
CPU frequency is 250 MHz; for RevA or later the minimum CPU frequency is 150 MHz for commercial temperature devices
and 175 MHz for extended temperature devices.
2
As Table 15 shows, PCI_MODCK determines the PCI clock frequency range. Refer to Table 18 for lower configurations.
3
MODCK_H = hard reset configuration word [28–31]. MODCK[1-3] = three hardw are configuration pins.
4
60x and local bus frequency. Identic al t o CLKIN.
5
CPM multiplication facto r = CPM clock/bus clock
6
CPU multi plication f actor = Core PLL multipl ication fact or
Table 17. Clock Co nfigura tions for PCI Host Mo de (PCI_MODCK=0) 1, 2 (co ntinued)
Mode 3 Bus Clock 4
(MHz) CPM
Multiplication
Factor 5
CPM Clock
(MHz) CPU
Multiplication
Factor 6
CPU Clock
(MHz) PCI
Division
Factor
PCI Clock
(MHz)
MODCK_H-
MODCK[1-3] Low High Low High Low High Low High
MPC8280 PowerQUI CC™ II Famil y Hardw are Sp ecif ications, Rev. 1.8
Freescale Semiconductor 31
Clock Confi guration Modes
Table 18. Clock Co nfigurations for PCI Ho st M ode (PCI_M ODCK=1) 1, 2
Mode 3 Bus Clock 4
(MHz) CPM
Multiplication
Factor 5
CPM Clock
(MHz) CPU
Multiplication
Factor 6
CPU Clock
(MHz) PCI
Division
Factor
PCI Clock
(MHz)
MODCK_H-
MODCK[1-3] Low High Low High Low High Low High
Defaul t Modes (MODCK_H=0000)
0000_000 60.0 100.0 2 120.0 200.0 2.5 150.0 250.0 4 30.0 50.0
0000_001 50.0 100.0 2 100.0 200.0 3 150.0 300.0 4 25.0 50.0
0000_010 60.0 120.0 2.5 150.0 300.0 3 180.0 360.0 6 25.0 50.0
0000_011 60.0 120.0 2.5 150.0 300.0 3.5 210.0 420.0 6 25.0 50.0
0000_100 60.0 120.0 2.5 150.0 300.0 4 240.0 480.0 6 25.0 50.0
0000_101 50.0 100.0 3 150.0 300.0 3 150.0 300.0 6 25.0 50.0
0000_110 50.0 100.0 3 150.0 300.0 3.5 175.0 350.0 6 25.0 50.0
0000_111 50.0 100.0 3 150.0 300.0 4 200.0 400.0 6 25.0 50.0
Full Conf iguration Modes
0001_000 50.0 100.0 3 150.0 300.0 5 250.0 500.0 6 25.0 50.0
0001_001 50.0 100.0 3 150.0 300.0 6 300.0 600.0 6 25.0 50.0
0001_010 50.0 100.0 3 150.0 300.0 7 350.0 700.0 6 25.0 50.0
0001_011 50.0 100.0 3 150.0 300.0 8 400.0 800.0 6 25.0 50.0
0010_000 50.0 100.0 4 200.0 400.0 5 250.0 500.0 8 25.0 50.0
0010_001 50.0 100.0 4 200.0 400.0 6 300.0 600.0 8 25.0 50.0
0010_010 50.0 100.0 4 200.0 400.0 7 350.0 700.0 8 25.0 50.0
0010_011 50.0 100.0 4 200.0 400.0 8 400.0 800.0 8 25.0 50.0
0010_100 37.5 75.0 4 150.0 300.0 5 187.5 375.0 6 25.0 50.0
0010_101 37.5 75.0 4 150.0 300.0 5.5 206.3 412.5 6 25.0 50.0
0010_110 37.5 75.0 4 150.0 300.0 6 225.0 450.0 6 25.0 50.0
0011_000 30.0 50.0 5 150.0 250.0 5 150.0 250.0 5 30.0 50.0
0011_001 25.0 50.0 5 125.0 250.0 6 150.0 300.0 5 25.0 50.0
0011_010 25.0 50.0 5 125.0 250.0 7 175.0 350.0 5 25.0 50.0
0011_011 25.0 50.0 5 125.0 250.0 8 200.0 400.0 5 25.0 50.0
0100_000 Reserved
0100_001 25.0 50.0 6 150.0 300.0 6 150.0 300.0 6 25.0 50.0
0100_010 25.0 50.0 6 150.0 300.0 7 175.0 350.0 6 25.0 50.0
MPC8280 PowerQUI CC™ II Famil y Hardw are Sp ecif ications , Rev. 1.8
32 Freescale Semiconductor
Clock Configuration Modes
0100_011 25.0 50.0 6 150.0 300.0 8 200.0 400.0 6 25.0 50.0
0101_000 60.0 100.0 2 120.0 200.0 2.5 150.0 250.0 4 30.0 50.0
0101_001 50.0 100.0 2 100.0 200.0 3 150.0 300.0 4 25.0 50.0
0101_010 50.0 100.0 2 100.0 200.0 3.5 175.0 350.0 4 25.0 50.0
0101_011 50.0 100.0 2 100.0 200.0 4 200.0 400.0 4 25.0 50.0
0101_100 50.0 100.0 2 100.0 200.0 4.5 225.0 450.0 4 25.0 50.0
0110_000 60.0 120.0 2.5 150.0 300.0 2.5 150.0 300.0 6 25.0 50.0
0110_001 60.0 120.0 2.5 150.0 300.0 3 180.0 360.0 6 25.0 50.0
0110_010 60.0 120.0 2.5 150.0 300.0 3.5 210.0 420.0 6 25.0 50.0
0110_011 60.0 120.0 2.5 150.0 300.0 4 240.0 480.0 6 25.0 50.0
0110_100 60.0 120.0 2.5 150.0 300.0 4.5 270.0 540.0 6 25.0 50.0
0110_101 60.0 120.0 2.5 150.0 300.0 5 300.0 600.0 6 25.0 50.0
0110_110 60.0 120.0 2.5 150.0 300.0 6 360.0 720.0 6 25.0 50.0
0111_000 Reserved
0111_001 50.0 100.0 3 150.0 300.0 3 150.0 300.0 6 25.0 50.0
0111_010 50.0 100.0 3 150.0 300.0 3.5 175.0 350.0 6 25.0 50.0
0111_011 50.0 100.0 3 150.0 300.0 4 200.0 400.0 6 25.0 50.0
0111_100 50.0 100.0 3 150.0 300.0 4.5 225.0 450.0 6 25.0 50.0
1000_000 Reserved
1000_001 66.7 133.3 3 200.0 400.0 3 200.0 400.0 8 25.0 50.0
1000_010 66.7 133.3 3 200.0 400.0 3.5 233.3 466.7 8 25.0 50.0
1000_011 66.7 133.3 3 200.0 400.0 4 266.7 533.3 8 25.0 50.0
1000_100 66.7 133.3 3 200.0 400.0 4.5 300.0 600.0 8 25.0 50.0
1000_101 66.7 133.3 3 200.0 400.0 6 400.0 800.0 8 25.0 50.0
1000_110 66.7 133.3 3 200.0 400.0 6.5 433.3 866.7 8 25.0 50.0
1001_000 Reserved
1001_001 Reserved
Table 18. Clock Co nfigura tions for PCI Host Mo de (PCI_MODCK=1) 1, 2 (co ntinued)
Mode 3 Bus Clock 4
(MHz) CPM
Multiplication
Factor 5
CPM Clock
(MHz) CPU
Multiplication
Factor 6
CPU Clock
(MHz) PCI
Division
Factor
PCI Clock
(MHz)
MODCK_H-
MODCK[1-3] Low High Low High Low High Low High
MPC8280 PowerQUI CC™ II Famil y Hardw are Sp ecif ications, Rev. 1.8
Freescale Semiconductor 33
Clock Confi guration Modes
1001_010 57.1 114.3 3.5 200.0 400.0 3.5 200.0 400.0 8 25.0 50.0
1001_011 57.1 114.3 3.5 200.0 400.0 4 228.6 457.1 8 25.0 50.0
1001_100 57.1 114.3 3.5 200.0 400.0 4.5 257.1 514.3 8 25.0 50.0
1001_101 42.9 85.7 3.5 150.0 300.0 5 214.3 428.6 6 25.0 50.0
1001_110 42.9 85.7 3.5 150.0 300.0 5.5 235.7 471.4 6 25.0 50.0
1001_111 42.9 85.7 3.5 150.0 300.0 6 257.1 514.3 6 25.0 50.0
1010_000 75.0 150.0 2 150.0 300.0 2 150.0 300.0 6 25.0 50.0
1010_001 75.0 150.0 2 150.0 300.0 2.5 187.5 375.0 6 25.0 50.0
1010_010 75.0 150.0 2 150.0 300.0 3 225.0 450.0 6 25.0 50.0
1010_011 75.0 150.0 2 150.0 300.0 3.5 262.5 525.0 6 25.0 50.0
1010_100 75.0 150.0 2 150.0 300.0 4 300.0 600.0 6 25.0 50.0
1011_000 Reserved
1011_001 80.0 160.0 2.5 200.0 400.0 2.5 200.0 400.0 8 25.0 50.0
1011_010 80.0 160.0 2.5 200.0 400.0 3 240.0 480.0 8 25.0 50.0
1011_011 80.0 160.0 2.5 200.0 400.0 3.5 280.0 560.0 8 25.0 50.0
1011_100 80.0 160.0 2.5 200.0 400.0 4 320.0 640.0 8 25.0 50.0
1011_101 80.0 160.0 2.5 200.0 400.0 4.5 360.0 720.0 8 25.0 50.0
1101_000 50.0 100.0 2.5 125.0 250.0 3 150.0 300.0 5 25.0 50.0
1101_001 50.0 100.0 2.5 125.0 250.0 3.5 175.0 350.0 5 25.0 50.0
1101_010 50.0 100.0 2.5 125.0 250.0 4 200.0 400.0 5 25.0 50.0
1101_011 50.0 100.0 2.5 125.0 250.0 4.5 225.0 450.0 5 25.0 50.0
1101_100 50.0 100.0 2.5 125.0 250.0 5 250.0 500.0 5 25.0 50.0
1101_101 62.5 125.0 2 125.0 250.0 3 187.5 375.0 5 25.0 50.0
1101_110 62.5 125.0 2 125.0 250.0 4 250.0 500.0 5 25.0 50.0
1110_000 50.0 100.0 3 150.0 300.0 3.5 175.0 350.0 6 25.0 50.0
1110_001 50.0 100.0 3 150.0 300.0 4 200.0 400.0 6 25.0 50.0
Table 18. Clock Co nfigura tions for PCI Host Mo de (PCI_MODCK=1) 1, 2 (co ntinued)
Mode 3 Bus Clock 4
(MHz) CPM
Multiplication
Factor 5
CPM Clock
(MHz) CPU
Multiplication
Factor 6
CPU Clock
(MHz) PCI
Division
Factor
PCI Clock
(MHz)
MODCK_H-
MODCK[1-3] Low High Low High Low High Low High
MPC8280 PowerQUI CC™ II Famil y Hardw are Sp ecif ications , Rev. 1.8
34 Freescale Semiconductor
Clock Configuration Modes
7.3 PCI Agent Mode
Table 19 and Table 20 show configur ations for PCI agent mode. The frequencies list ed are for the purpose of
illustration only. Users must select a mode and input bus frequency so that the resulting configuration does not
exceed the frequency rating of the use r’s device. In addition, note the following:
NOTE: PCI_ MO DCK
In PCI mode only, PCI_MODCK comes from the LGPL5 pin and
MODCK_H[0–3] comes fr om {LG PL0, LGPL1, LGPL2, LGP L3}.
NOTE: Tva l (Output Hold)
The mini mum Tval = 2 ns when PCI_MODCK = 1, and the minimum Tval = 1 ns
when PCI_M ODCK = 0. Therefore, designers sh ould use cl ock co nfigur ations that
fit thi s condition to achiev e PCI-comp liant AC timing.
1110_010 50.0 100.0 3 150.0 300.0 4.5 225.0 450.0 6 25.0 50.0
1110_011 50.0 100.0 3 150.0 300.0 5 250.0 500.0 6 25.0 50.0
1110_100 50.0 100.0 3 150.0 300.0 5.5 275.0 550.0 6 25.0 50.0
1100_000 Reserved
1100_001 Reserved
1100_010 Reserved
1
The “lo w” values ar e the minimum a llowable fr equ encies fo r a g iven clo ck mode. The minimum bus freque ncy in a tabl e e ntry
guarantees only t he required minimum CPU operating frequency. The “high” values are for the purpose of il lustration o nly.
Users mu st s elect a mode and input bus fr equency so that the result ing confi guration does not violate the frequency ra ti ng of
the user’s devi ce. The minimum CPM fr equency is 120 MHz. Minimum CPU freque ncy is de termin ed by the clock mode. For
modes with a CPU mult ipli cation factor <= 3, the minimum CPU fre quency is 150 MHz for commercial temper ature devices and
175 MHz fo r extend ed temperat ure devi ces. For modes with a CPU mult iplica tion f actor >= 3. 5: for Rev0.1 the minimum CPU
freque ncy is 250 MHz; for Re vA or l at er th e minimum CPU f requency i s 150 M Hz for co mmercial tem peratur e devi ces and 175
MHz for extended temperature devices.
2
As Table 15 shows, PCI_MODCK determines the PCI clock frequency range. Refer to Table 17 for higher confi guratio ns.
3
MODCK_H = hard reset configuration word [28–31 ]. MODCK[ 1-3] = three hardware confi guratio n pins.
4
60x and local bus frequency. Identical to CLKIN.
5
CPM multiplication fact or = CPM clock/bus clock
6
CP U multip li ca ti o n fa c to r = Cor e PL L mu lt ip lic a tion fa c to r
Table 18. Clock Co nfigura tions for PCI Host Mo de (PCI_MODCK=1) 1, 2 (co ntinued)
Mode 3 Bus Clock 4
(MHz) CPM
Multiplication
Factor 5
CPM Clock
(MHz) CPU
Multiplication
Factor 6
CPU Clock
(MHz) PCI
Division
Factor
PCI Clock
(MHz)
MODCK_H-
MODCK[1-3] Low High Low High Low High Low High
MPC8280 PowerQUI CC™ II Famil y Hardw are Sp ecif ications, Rev. 1.8
Freescale Semiconductor 35
Clock Confi guration Modes
Table 19 . Clock Configurations for PCI Agent M ode (PCI_MODCK=0) 1, 2
Mode 3 PCI Clock
(MHz) CPM
Multiplication
Factor 4
CPM Clock
(MHz) CPU
Multiplication
Factor 5
CPU Clock
(MHz) Bus
Division
Factor
Bus Clock
(MHz)
MODCK_H-
MODCK[1-3] Low High Low High Low High Low High
Default Mod es (MODCK_H=0000
0000_000 60.0 66.7 2 120.0 133.3 2.5 150.0 166.7 2 60.0 66.7
0000_001 50.0 66.7 2 100.0 133.3 3 150.0 200.0 2 50.0 66.7
0000_010 50.0 66.7 3 150.0 200.0 3 150.0 200.0 3 50.0 66.7
0000_011 50.0 66.7 3 150.0 200.0 4 200.0 266.6 3 50.0 66.7
0000_100 50.0 66.7 3 150.0 200.0 3 180.0 240.0 2.5 60.0 80.0
0000_101 50.0 66.7 3 150.0 200.0 3.5 210.0 280.0 2.5 60.0 80.0
0000_110 50.0 66.7 4 200.0 266.6 3.5 233.3 311.1 3 66.7 88.9
0000_111 50.0 66.7 4 200.0 266.6 3 240.0 320.0 2.5 80.0 106.7
Full Conf iguration Modes
0001_001 60.0 66.7 2 120.0 133.3 5 150.0 166.7 4 30.0 33.3
0001_010 50.0 66.7 2 100.0 133.3 6 150.0 200.0 4 25.0 33.3
0001_011 50.0 66.7 2 100.0 133.3 7 175.0 233.3 4 25.0 33.3
0001_100 50.0 66.7 2 100.0 133.3 8 200.0 266.6 4 25.0 33.3
0010_001 50.0 66.7 3 150.0 200.0 3 180.0 240.0 2.5 60.0 80.0
0010_010 50.0 66.7 3 150.0 200.0 3.5 210.0 280.0 2.5 60.0 80.0
0010_011 50.0 66.7 3 150.0 200.0 4 240.0 320.0 2.5 60.0 80.0
0010_100 50.0 66.7 3 150.0 200.0 4.5 270.0 360.0 2.5 60.0 80.0
0011_000 Reserved
0011_001 Reserved
0011_010 Reserved
0011_011 Reserved
0011_100 Reserved
0100_000 Reserved
0100_001 50.0 66.7 3 150.0 200.0 3 150.0 200.0 3 50.0 66.7
0100_010 50.0 66.7 3 150.0 200.0 3.5 175.0 200.0 3 50.0 66.7
0100_011 50.0 66.7 3 150.0 200.0 4 200.0 266.6 3 50.0 66.7
0100_100 50.0 66.7 3 150.0 200.0 4.5 225.0 300.0 3 50.0 66.7
MPC8280 PowerQUI CC™ II Famil y Hardw are Sp ecif ications , Rev. 1.8
36 Freescale Semiconductor
Clock Configuration Modes
0101_000 50.0 66.7 5 250.0 333.3 2.5 250.0 333.3 2.5 100.0 133.3
0101_001 50.0 66.7 5 250.0 333.3 3 300.0 400.0 2.5 100.0 133.3
0101_010 50.0 66.7 5 250.0 333.3 3.5 350.0 466.6 2.5 100.0 133.3
0101_011 50.0 66.7 5 250.0 333.3 4 400.0 533.3 2.5 100.0 133.3
0101_100 50.0 66.7 5 250.0 333.3 4.5 450.0 599.9 2.5 100.0 133.3
0101_101 50.0 66.7 5 250.0 333.3 5 500.0 666.6 2.5 100.0 133.3
0101_110 50.0 66.7 5 250.0 333.3 5.5 550.0 733.3 2.5 100.0 133.3
0110_000 Reserved
0110_001 50.0 66.7 4 200.0 266.6 3 200.0 266.6 3 66.7 88.9
0110_010 50.0 66.7 4 200.0 266.6 3.5 233.3 311.1 3 66.7 88.9
0110_011 50.0 66.7 4 200.0 266.6 4 266.7 355.5 3 66.7 88.9
0110_100 50.0 66.7 4 200.0 266.6 4.5 300.0 400.0 3 66.7 88.9
0111_000 50.0 66.7 3 150.0 200.0 2 150.0 200.0 2 75.0 100.0
0111_001 50.0 66.7 3 150.0 200.0 2.5 187.5 250.0 2 75.0 100.0
0111_010 50.0 66.7 3 150.0 200.0 3 225.0 300.0 2 75.0 100.0
0111_011 50.0 66.7 3 150.0 200.0 3.5 262.5 350.0 2 75.0 100.0
1000_000 Reserved
1000_001 50.0 66.7 3 150.0 200.0 2.5 150.0 166.7 2.5 60.0 80.0
1000_010 50.0 66.7 3 150.0 200.0 3 180.0 240.0 2.5 60.0 80.0
1000_011 50.0 66.7 3 150.0 200.0 3.5 210.0 280.0 2.5 60.0 80.0
1000_100 50.0 66.7 3 150.0 200.0 4 240.0 320.0 2.5 60.0 80.0
1000_101 50.0 66.7 3 150.0 200.0 4.5 270.0 360.0 2.5 60.0 80.0
1001_000 Reserved
1001_001 Reserved
1001_010 Reserved
1001_011 50.0 66.7 4 200.0 266.6 4 200.0 266.6 4 50.0 66.7
1001_100 50.0 66.7 4 200.0 266.6 4.5 225.0 300.0 4 50.0 66.7
Table 19. Clock Configuratio ns for PCI Agent Mod e (PCI_MODCK=0 ) 1, 2 (co ntinued)
Mode 3 PCI Clock
(MHz) CPM
Multiplication
Factor 4
CPM Clock
(MHz) CPU
Multiplication
Factor 5
CPU Clock
(MHz) Bus
Division
Factor
Bus Clock
(MHz)
MODCK_H-
MODCK[1-3] Low High Low High Low High Low High
MPC8280 PowerQUI CC™ II Famil y Hardw are Sp ecif ications, Rev. 1.8
Freescale Semiconductor 37
Clock Confi guration Modes
1010_000 Reserved
1010_001 50.0 66.7 4 200.0 266.6 3 200.0 266.6 3 66.7 88.9
1010_010 50.0 66.7 4 200.0 266.6 3.5 233.3 311.1 3 66.7 88.9
1010_011 50.0 66.7 4 200.0 266.6 4 266.7 355.5 3 66.7 88.9
1010_100 50.0 66.7 4 200.0 266.6 4.5 300.0 400.0 3 66.7 88.9
1011_000 Reserved
1011_001 50.0 66.7 4 200.0 266.6 2.5 200.0 266.6 2.5 80.0 106.7
1011_010 50.0 66.7 4 200.0 266.6 3 240.0 320.0 2.5 80.0 106.7
1011_011 50.0 66.7 4 200.0 266.6 3.5 280.0 373.3 2.5 80.0 106.7
1011_100 50.0 66.7 4 200.0 266.6 4 320.0 426.6 2.5 80.0 106.7
1100_101 50.0 66.7 6 300.0 400.0 4 400.0 533.3 3 100.0 133.3
1100_110 50.0 66.7 6 300.0 400.0 4.5 450.0 599.9 3 100.0 133.3
1100_111 50.0 66.7 6 300.0 400.0 5 500.0 666.6 3 100.0 133.3
1101_000 50.0 66.7 6 300.0 400.0 5.5 550.0 733.3 3 100.0 133.3
1101_001 50.0 66.7 6 300.0 400.0 3.5 420.0 559.9 2.5 120.0 160.0
1101_010 50.0 66.7 6 300.0 400.0 4 480.0 639.9 2.5 120.0 160.0
1101_011 50.0 66.7 6 300.0 400.0 4.5 540.0 719.9 2.5 120.0 160.0
1101_100 50.0 66.7 6 300.0 400.0 5 600.0 799.9 2.5 120.0 160.0
1110_000 50.0 66.7 5 250.0 333.3 2.5 312.5 416.6 2 125.0 166.7
1110_001 50.0 66.7 5 250.0 333.3 3 375.0 500.0 2 125.0 166.7
1110_010 50.0 66.7 5 250.0 333.3 3.5 437.5 583.3 2 125.0 166.7
1110_011 50.0 66.7 5 250.0 333.3 4 500.0 666.6 2 125.0 166.7
1110_100 50.0 66.7 5 250.0 333.3 4 333.3 444.4 3 83.3 111.1
1110_101 50.0 66.7 5 250.0 333.3 4.5 375.0 500.0 3 83.3 111.1
1110_110 50.0 66.7 5 250.0 333.3 5 416.7 555.5 3 83.3 111.1
1110_111 50.0 66.7 5 250.0 333.3 5.5 458.3 611.1 3 83.3 111.1
Table 19. Clock Configuratio ns for PCI Agent Mod e (PCI_MODCK=0 ) 1, 2 (co ntinued)
Mode 3 PCI Clock
(MHz) CPM
Multiplication
Factor 4
CPM Clock
(MHz) CPU
Multiplication
Factor 5
CPU Clock
(MHz) Bus
Division
Factor
Bus Clock
(MHz)
MODCK_H-
MODCK[1-3] Low High Low High Low High Low High
MPC8280 PowerQUI CC™ II Famil y Hardw are Sp ecif ications , Rev. 1.8
38 Freescale Semiconductor
Clock Configuration Modes
1100_000 Reserved
1100_001 Reserved
1100_010 Reserved
1
The “low” values ar e the minimum allowable f requencies for a given clock mode. The m inimum bus frequency in a tabl e entry
guarantees only th e requi red minimum CPU operating frequency. The “high” values are for the purpose of illustration o nly.
Users must select a mode and input bus frequency so that the resulting configuration does not violate the frequency rating of
the user’s device. The minimum CPM frequency is 120 MHz . Minimum CPU frequency is determined by the clock mode. For
modes with a CPU multiplicati on factor <= 3, the mini mum CPU freq uency is 150 MHz for commercia l tempera ture device s and
175 MHz for exte nded temperat ure devi ces. For modes with a CPU mu ltiplicat ion fac tor >= 3.5: for Rev0 .1 the minim um CPU
freque ncy is 250 MHz; for RevA or late r the mi nim um CPU freque ncy is 150 MH z for commer cial temperat ure dev ices an d 175
MHz for extended temperature devices.
2
As shown in Table 15, PCI_MODCK det ermines the PCI clock frequency range. Refer to Table 20 for lower confi guration s.
3
MODCK_H = hard reset configuration word [28–31]. MODCK[1-3] = three hardware configuration pins.
4
CPM multiplication factor = CPM clock /PCI clock
5
CP U multip li ca ti o n fa c to r = Cor e PL L mu lt ip lic a tion fa c to r
Table 20 . Clock Configurations for PCI Agent M ode (PCI_MODCK=1) 1, 2
Mode 3 PCI Clock
(MHz) CPM
Multiplication
Factor 4
CPM Clock
(MHz) CPU
Multiplication
Factor 5
CPU Clock
(MHz) Bus
Division
Factor
Bus Clock
(MHz)
MODCK_H-
MODCK[1-3] Low High Low High Low High Low High
Defaul t Modes (MODCK_H=0000)
0000_000 30.0 50.0 4 120.0 200.0 2.5 150.0 250.0 2 60.0 100.0
0000_001 25.0 50.0 4 100.0 200.0 3 150.0 300.0 2 50.0 100.0
0000_010 25.0 50.0 6 150.0 300.0 3 150.0 300.0 3 50.0 100.0
0000_011 25.0 50.0 6 150.0 300.0 4 200.0 400.0 3 50.0 100.0
0000_100 25.0 50.0 6 150.0 300.0 3 180.0 360.0 2.5 60.0 120.0
0000_101 25.0 50.0 6 150.0 300.0 3.5 210.0 420.0 2.5 60.0 120.0
0000_110 25.0 50.0 8 200.0 400.0 3.5 233.3 466.7 3 66.7 133.3
0000_111 25.0 50.0 8 200.0 400.0 3 240.0 480.0 2.5 80.0 160.0
Full Conf iguration Modes
0001_001 30.0 50.0 4 120.0 200.0 5 150.0 250.0 4 30.0 50.0
0001_010 25.0 50.0 4 100.0 200.0 6 150.0 300.0 4 25.0 50.0
0001_011 25.0 50.0 4 100.0 200.0 7 175.0 350.0 4 25.0 50.0
0001_100 25.0 50.0 4 100.0 200.0 8 200.0 400.0 4 25.0 50.0
Table 19. Clock Configuratio ns for PCI Agent Mod e (PCI_MODCK=0 ) 1, 2 (co ntinued)
Mode 3 PCI Clock
(MHz) CPM
Multiplication
Factor 4
CPM Clock
(MHz) CPU
Multiplication
Factor 5
CPU Clock
(MHz) Bus
Division
Factor
Bus Clock
(MHz)
MODCK_H-
MODCK[1-3] Low High Low High Low High Low High
MPC8280 PowerQUI CC™ II Famil y Hardw are Sp ecif ications, Rev. 1.8
Freescale Semiconductor 39
Clock Confi guration Modes
0010_001 25.0 50.0 6 150.0 300.0 3 180.0 360.0 2.5 60.0 120.0
0010_010 25.0 50.0 6 150.0 300.0 3.5 210.0 420.0 2.5 60.0 120.0
0010_011 25.0 50.0 6 150.0 300.0 4 240.0 480.0 2.5 60.0 120.0
0010_100 25.0 50.0 6 150.0 300.0 4.5 270.0 540.0 2.5 60.0 120.0
0011_000 Reserved
0011_001 37.5 50.0 4 150.0 200.0 3 150.0 200.0 3 50.0 66.7
0011_010 32.1 50.0 4 128.6 200.0 3.5 150.0 233.3 3 42.9 66.7
0011_011 28.1 50.0 4 112.5 200.0 4 150.0 266.7 3 37.5 66.7
0011_100 25.0 50.0 4 100.0 200.0 4.5 150.0 300.0 3 33.3 66.7
0100_000 Reserved
0100_001 25.0 50.0 6 150.0 300.0 3 150.0 300.0 3 50.0 100.0
0100_010 25.0 50.0 6 150.0 300.0 3.5 175.0 350.0 3 50.0 100.0
0100_011 25.0 50.0 6 150.0 300.0 4 200.0 400.0 3 50.0 100.0
0100_100 25.0 50.0 6 150.0 300.0 4.5 225.0 450.0 3 50.0 100.0
0101_000 30.0 50.0 5 150.0 250.0 2.5 150.0 250.0 2.5 60.0 100.0
0101_001 25.0 50.0 5 125.0 250.0 3 150.0 300.0 2.5 50.0 100.0
0101_010 25.0 50.0 5 125.0 250.0 3.5 175.0 350.0 2.5 50.0 100.0
0101_011 25.0 50.0 5 125.0 250.0 4 200.0 400.0 2.5 50.0 100.0
0101_100 25.0 50.0 5 125.0 250.0 4.5 225.0 450.0 2.5 50.0 100.0
0101_101 25.0 50.0 5 125.0 250.0 5 250.0 500.0 2.5 50.0 100.0
0101_110 25.0 50.0 5 125.0 250.0 5.5 275.0 550.0 2.5 50.0 100.0
0110_000 Reserved
0110_001 25.0 50.0 8 200.0 400.0 3 200.0 400.0 3 66.7 133.3
0110_010 25.0 50.0 8 200.0 400.0 3.5 233.3 466.7 3 66.7 133.3
0110_011 25.0 50.0 8 200.0 400.0 4 266.7 533.3 3 66.7 133.3
0110_100 25.0 50.0 8 200.0 400.0 4.5 300.0 600.0 3 66.7 133.3
Table 20. Clock Configuratio ns for PCI Agent Mod e (PCI_MODCK=1 ) 1, 2 (co ntinued)
Mode 3 PCI Clock
(MHz) CPM
Multiplication
Factor 4
CPM Clock
(MHz) CPU
Multiplication
Factor 5
CPU Clock
(MHz) Bus
Division
Factor
Bus Clock
(MHz)
MODCK_H-
MODCK[1-3] Low High Low High Low High Low High
MPC8280 PowerQUI CC™ II Famil y Hardw are Sp ecif ications , Rev. 1.8
40 Freescale Semiconductor
Clock Configuration Modes
0111_000 25.0 50.0 6 150.0 300.0 2 150.0 300.0 2 75.0 150.0
0111_001 25.0 50.0 6 150.0 300.0 2.5 187.5 375.0 2 75.0 150.0
0111_010 25.0 50.0 6 150.0 300.0 3 225.0 450.0 2 75.0 150.0
0111_011 25.0 50.0 6 150.0 300.0 3.5 262.5 525.0 2 75.0 150.0
1000_000 Reserved
1000_001 25.0 50.0 6 150.0 300.0 2.5 150.0 300.0 2.5 60.0 120.0
1000_010 25.0 50.0 6 150.0 300.0 3 180.0 360.0 2.5 60.0 120.0
1000_011 25.0 50.0 6 150.0 300.0 3.5 210.0 420.0 2.5 60.0 120.0
1000_100 25.0 50.0 6 150.0 300.0 4 240.0 480.0 2.5 60.0 120.0
1000_101 25.0 50.0 6 150.0 300.0 4.5 270.0 540.0 2.5 60.0 120.0
1001_000 Reserved
1001_001 Reserved
1001_010 Reserved
1001_011 25.0 50.0 8 200.0 400.0 4 200.0 400.0 4 50.0 100.0
1001_100 25.0 50.0 8 200.0 400.0 4.5 225.0 450.0 4 50.0 100.0
1010_000 Reserved
1010_001 25.0 50.0 8 200.0 400.0 3 200.0 400.0 3 66.7 133.3
1010_010 25.0 50.0 8 200.0 400.0 3.5 233.3 466.7 3 66.7 133.3
1010_011 25.0 50.0 8 200.0 400.0 4 266.7 533.3 3 66.7 133.3
1010_100 25.0 50.0 8 200.0 400.0 4.5 300.0 600.0 3 66.7 133.3
1011_000 Reserved
1011_001 25.0 50.0 8 200.0 400.0 2.5 200.0 400.0 2.5 80.0 160.0
1011_010 25.0 50.0 8 200.0 400.0 3 240.0 480.0 2.5 80.0 160.0
1011_011 25.0 50.0 8 200.0 400.0 3.5 280.0 560.0 2.5 80.0 160.0
1011_100 25.0 50.0 8 200.0 400.0 4 320.0 640.0 2.5 80.0 160.0
1100_101 25.0 50.0 6 150.0 300.0 4 200.0 400.0 3 50.0 100.0
1100_110 25.0 50.0 6 150.0 300.0 4.5 225.0 450.0 3 50.0 100.0
Table 20. Clock Configuratio ns for PCI Agent Mod e (PCI_MODCK=1 ) 1, 2 (co ntinued)
Mode 3 PCI Clock
(MHz) CPM
Multiplication
Factor 4
CPM Clock
(MHz) CPU
Multiplication
Factor 5
CPU Clock
(MHz) Bus
Division
Factor
Bus Clock
(MHz)
MODCK_H-
MODCK[1-3] Low High Low High Low High Low High
MPC8280 PowerQUI CC™ II Famil y Hardw are Sp ecif ications, Rev. 1.8
Freescale Semiconductor 41
Clock Confi guration Modes
1100_111 25.0 50.0 6 150.0 300.0 5 250.0 500.0 3 50.0 100.0
1101_000 25.0 50.0 6 150.0 300.0 5.5 275.0 550.0 3 50.0 100.0
1101_001 25.0 50.0 6 150.0 300.0 3.5 210.0 420.0 2.5 60.0 120.0
1101_010 25.0 50.0 6 150.0 300.0 4 240.0 480.0 2.5 60.0 120.0
1101_011 25.0 50.0 6 150.0 300.0 4.5 270.0 540.0 2.5 60.0 120.0
1101_100 25.0 50.0 6 150.0 300.0 5 300.0 600.0 2.5 60.0 120.0
1110_000 25.0 50.0 5 125.0 250.0 2.5 156.3 312.5 2 62.5 125.0
1110_001 25.0 50.0 5 125.0 250.0 3 187.5 375.0 2 62.5 125.0
1110_010 25.0 50.0 5 125.0 250.0 3.5 218.8 437.5 2 62.5 125.0
1110_011 25.0 50.0 5 125.0 250.0 4 250.0 500.0 2 62.5 125.0
1110_100 25.0 50.0 5 125.0 250.0 4 166.7 333.3 3 41.7 83.3
1110_101 25.0 50.0 5 125.0 250.0 4.5 187.5 375.0 3 41.7 83.3
1110_110 25.0 50.0 5 125.0 250.0 5 208.3 416.7 3 41.7 83.3
1110_111 25.0 50.0 5 125.0 250.0 5.5 229.2 458.3 3 41.7 83.3
1100_000 Reserved
1100_001 Reserved
1100_010 Reserved
1
The “ lo w” val ues are t he mini mum al lowabl e freq uenci es f or a gi ve n cloc k mode . The m ini mum bus frequ ency in a ta ble ent ry
guarantees onl y the required minimum CPU operating frequency. The “high” val ues are for the purpose o f illustration only.
Users m ust sel ect a mode and in put bu s fr equen cy so that t he resul ting con figur ation does not viol ate th e frequenc y rati ng of
the user’s d evi ce. The mi nimum CPM fre quenc y is 120 MHz . Mini mum CPU f requenc y is det ermined by the cl ock mode . For
mode s wit h a CPU multi plication factor <= 3, the minim um CPU frequ ency is 150 MHz for commercial temperature devic es
and 175 M Hz for ex tended t empera ture dev ices. For modes wit h a CPU multi plic ation fact or > = 3.5: fo r Rev0.1 the m inimum
CPU frequency is 250 MHz; for RevA or later the minimu m CPU frequency is 150 MHz for commercial temperature devices
and 175 MHz for extended temperature devices.
2
As shown in Table 15, PCI_ MO D C K d et e rmines th e P C I cl o ck ra n ge. Refe r to Table 19 for higher range configurations.
3
MODCK_H = hard reset configuration word [28–31]. MODCK[ 1-3] = three hardware configuration pins.
4
CPM multiplication factor = CPM clock/PCI clock
5
CPU multip li cation factor = Core PLL multiplication factor
Table 20. Clock Configuratio ns for PCI Agent Mod e (PCI_MODCK=1 ) 1, 2 (co ntinued)
Mode 3 PCI Clock
(MHz) CPM
Multiplication
Factor 4
CPM Clock
(MHz) CPU
Multiplication
Factor 5
CPU Clock
(MHz) Bus
Division
Factor
Bus Clock
(MHz)
MODCK_H-
MODCK[1-3] Low High Low High Low High Low High
MPC8280 PowerQUI CC™ II Famil y Hardw are Sp ecif ications , Rev. 1.8
42 Freescale Semiconductor
Pinout
8 Pinout
This section provides the pin assignments and pinout lists for both HiP7 PowerQUI CC II packages.
8.1 ZU and VV Packages—MPC8280 and MPC8270
The following figures and table represent the standard 480 TBGA package. For information on the alternate
package , refe r to Section 8.2, “VR and ZQ Packages—M PC8275 and MPC8270,” on page -57.
Figure 13 shows the pinout of the ZU and VV packages as viewed from the top surface.
Figure 13. Pinou t of the 480 TBGA Package (View from Top)
1 2 3 4 5 6 7 8 91011121314151617 18 19 20 21 22 23 24 25 26 27 28 29
Not to Scale
1 2 3 4 5 6 7 8 91011121314151617181920212223242526272829
A
B
C
D
E
F
G
H
J
K
L
M
N
P
R
T
U
V
W
Y
AA
AB
AC
AD
AE
AF
AG
AH
AJ
A
B
C
D
E
F
G
H
J
K
L
M
N
P
R
T
U
V
W
Y
AA
AB
AC
AD
AE
AF
AG
AH
AJ
MPC8280 PowerQUI CC™ II Famil y Hardw are Sp ecif ications, Rev. 1.8
Freescale Semiconductor 43
Pinout
Figure 14 shows the side profi le of the TBGA package to indica te th e direction of the top surface vi ew.
Figure 14. Side View of the TBGA Package
Table 21 shows the pinout list of the MPC8280 a nd MPC8270. Table 22 defines conv entions and acr onyms used in
Table 21.
Table 21. M PC8280 and MPC8270 (ZU and VV Packa ges) Pinout List
Pin Name Ball
MPC8280/MPC8270 MPC8280 only
BR W5
BG F4
ABB/IRQ2 E2
TS E3
A0 G1
A1 H5
A2 H2
A3 H1
A4 J5
A5 J4
A6 J3
A7 J2
A8 J1
A9 K4
A10 K3
A11 K2
A12 K1
A13 L5
A14 L4
A15 L3
A16 L2
Soldermask
Copper Traces
Die
Copper Heat Spreader
(Oxidized for Insulation)
1.27 mm Pitch Glob-Top Dam
Wire Bonds
Etched Pressure Sensitive
Die
Glob-Top Filled Area
Polymide Tape Cavity Adhesive
Attach
View
MPC8280 PowerQUI CC™ II Famil y Hardw are Sp ecif ications , Rev. 1.8
44 Freescale Semiconductor
Pinout
A17 L1
A18 M5
A19 N5
A20 N4
A21 N3
A22 N2
A23 N1
A24 P4
A25 P3
A26 P2
A27 P1
A28 R1
A29 R3
A30 R5
A31 R4
TT0 F1
TT1 G4
TT2 G3
TT3 G2
TT4 F2
TBST D3
TSIZ0 C1
TSIZ1 E4
TSIZ2 D2
TSIZ3 F5
AACK F3
ARTRY E1
DBG V1
DBB/IRQ3 V2
D0 B20
D1 A18
D2 A16
D3 A13
Tabl e 21. M PC8280 and MPC8270 (ZU and VV Packages) Pino ut List (continued)
Pin Name Ball
MPC8280/MPC8270 MPC8280 only
MPC8280 PowerQUI CC™ II Famil y Hardw are Sp ecif ications, Rev. 1.8
Freescale Semiconductor 45
Pinout
D4 E12
D5 D9
D6 A6
D7 B5
D8 A20
D9 E17
D10 B15
D11 B13
D12 A11
D13 E9
D14 B7
D15 B4
D16 D19
D17 D17
D18 D15
D19 C13
D20 B11
D21 A8
D22 A5
D23 C5
D24 C19
D25 C17
D26 C15
D27 D13
D28 C11
D29 B8
D30 A4
D31 E6
D32 E18
D33 B17
D34 A15
D35 A12
D36 D11
Tabl e 21. M PC8280 and MPC8270 (ZU and VV Packages) Pino ut List (continued)
Pin Name Ball
MPC8280/MPC8270 MPC8280 only
MPC8280 PowerQUI CC™ II Famil y Hardw are Sp ecif ications , Rev. 1.8
46 Freescale Semiconductor
Pinout
D37 C8
D38 E7
D39 A3
D40 D18
D41 A17
D42 A14
D43 B12
D44 A10
D45 D8
D46 B6
D47 C4
D48 C18
D49 E16
D50 B14
D51 C12
D52 B10
D53 A7
D54 C6
D55 D5
D56 B18
D57 B16
D58 E14
D59 D12
D60 C10
D61 E8
D62 D6
D63 C2
DP0/RSRV/EXT_BR2 B22
IRQ1/DP1/EXT_BG2 A22
IRQ2/DP2/TLBISYNC/EXT_DBG2 E21
IRQ3/DP3/CKSTP_OUT/EXT_BR3 D21
IRQ4/DP4/CORE_SRESET/EXT_BG3 C21
IRQ5/CINT/DP5/TBEN/EXT_DBG3 B21
Tabl e 21. M PC8280 and MPC8270 (ZU and VV Packages) Pino ut List (continued)
Pin Name Ball
MPC8280/MPC8270 MPC8280 only
MPC8280 PowerQUI CC™ II Famil y Hardw are Sp ecif ications, Rev. 1.8
Freescale Semiconductor 47
Pinout
IRQ6/DP6/CSE0 A21
IRQ7/DP7/CSE1 E20
PSDVAL V3
TA C22
TEA V5
GBL/IRQ1 W1
CI/BADDR29/IRQ2 U2
WT/BADDR30/IRQ3 U3
L2_HIT/IRQ4 Y4
CPU_BG/BADDR31/IRQ5/CINT U4
CPU_DBG R2
CPU_BR Y3
CS0 F25
CS1 C29
CS2 E27
CS3 E28
CS4 F26
CS5 F27
CS6 F28
CS7 G25
CS8 D29
CS9 E29
CS10/BCTL1 F29
CS11/AP0 G28
BADDR27 T5
BADDR28 U1
ALE T2
BCTL0 A27
PWE0/PSDDQM0/PBS0 C25
PWE1/PSDDQM1/PBS1 E24
PWE2/PSDDQM2/PBS2 D24
PWE3/PSDDQM3/PBS3 C24
PWE4/PSDDQM4/PBS4 B26
Tabl e 21. M PC8280 and MPC8270 (ZU and VV Packages) Pino ut List (continued)
Pin Name Ball
MPC8280/MPC8270 MPC8280 only
MPC8280 PowerQUI CC™ II Famil y Hardw are Sp ecif ications , Rev. 1.8
48 Freescale Semiconductor
Pinout
PWE5/PSDDQM5/PBS5 A26
PWE6/PSDDQM6/PBS6 B25
PWE7/PSDDQM7/PBS7 A25
PSDA10/PGPL0 E23
PSDWE/PGPL1 B24
POE/PSDRAS/PGPL2 A24
PSDCAS/PGPL3 B23
PGTA/PUPMWAIT/PGPL4/PPBS A23
PSDAMUX/PGPL5 D22
LWE0/LSDDQM0/LBS0/PCI_CFG0 H28
LWE1/LSDDQM1/LBS1/PCI_CFG1 H27
LWE2/LSDDQM2/LBS2/PCI_CFG2 H26
LWE3/LSDDQM3/LBS3/PCI_CFG3 G29
LSDA10/LGPL0/PCI_MODCKH0 D27
LSDWE/LGPL1/PCI_MODCKH1 C28
LOE/LSDRAS/LGPL2/PCI_MODCKH2 E26
LSDCAS/LGPL3/PCI_MODCKH3 D25
LGTA/LUPMWAIT/LGPL4/LPBS C26
LGPL5/LSDAMUX/PCI_MODCK B27
LWR D28
L_A14/PAR N27
L_A15/FRAME/SMI T29
L_A16/TRDY R27
L_A17/IRDY/CKSTP_OUT R26
L_A18/STOP R29
L_A19/DEVSEL R28
L_A20/IDSEL W29
L_A21/PERR P28
L_A22/SERR N26
L_A23/REQ0 AA27
L_A24/REQ1/HSEJSW P29
L_A25/GNT0 AA26
L_A26/GNT1/HSLED N25
Tabl e 21. M PC8280 and MPC8270 (ZU and VV Packages) Pino ut List (continued)
Pin Name Ball
MPC8280/MPC8270 MPC8280 only
MPC8280 PowerQUI CC™ II Famil y Hardw are Sp ecif ications, Rev. 1.8
Freescale Semiconductor 49
Pinout
L_A27/GNT2/HSENUM AA25
L_A28/RST/CORE_SRESET AB29
L_A29/INTA AB28
L_A30/REQ2 P25
L_A31/DLLOUT AB27
LCL_D0/AD0 H29
LCL_D1/AD1 J29
LCL_D2/AD2 J28
LCL_D3/AD3 J27
LCL_D4/AD4 J26
LCL_D5/AD5 J25
LCL_D6/AD6 K25
LCL_D7/AD7 L29
LCL_D8/AD8 L27
LCL_D9/AD9 L26
LCL_D10/AD10 L25
LCL_D11/AD11 M29
LCL_D12/AD12 M28
LCL_D13/AD13 M27
LCL_D14/AD14 M26
LCL_D15/AD15 N29
LCL_D16/AD16 T25
LCL_D17/AD17 U27
LCL_D18/AD18 U26
LCL_D19/AD19 U25
LCL_D20/AD20 V29
LCL_D21/AD21 V28
LCL_D22/AD22 V27
LCL_D23/AD23 V26
LCL_D24/AD24 W27
LCL_D25/AD25 W26
LCL_D26/AD26 W25
LCL_D27/AD27 Y29
Tabl e 21. M PC8280 and MPC8270 (ZU and VV Packages) Pino ut List (continued)
Pin Name Ball
MPC8280/MPC8270 MPC8280 only
MPC8280 PowerQUI CC™ II Famil y Hardw are Sp ecif ications , Rev. 1.8
50 Freescale Semiconductor
Pinout
LCL_D28/AD28 Y28
LCL_D29/AD29 Y25
LCL_D30/AD30 AA29
LCL_D31/AD31 AA28
LCL_DP0/C0/BE0 L28
LCL_DP1/C1/BE1 N28
LCL_DP2/C2/BE2 T28
LCL_DP3/C3/BE3 W28
IRQ0/NMI_OUT T1
IRQ7/INT_OUT/APE D1
TRST 1 AH3
TCK AG5
TMS AJ3
TDI AE6
TDO AF5
TRIS AB4
PORESET1AG6
HRESET AH5
SRESET AF6
QREQ AA3
RSTCONF AJ4
MODCK1/AP1/TC0/BNKSEL0 W2
MODCK2/AP2/TC1/BNKSEL1 W3
MODCK3/AP3/TC2/BNKSEL2 W4
CLKIN1 AH4
PA0/RESTART1/DREQ3 FCC2_UTM_TXADDR2 AC29 2
PA1/REJECT1/DONE3 FCC2_UTM_TXADDR1 AC252
PA2/CLK20/DACK3 FCC2_UTM_TXADDR0 AE282
PA3/CLK19/DACK4/L1RXD1A2 FCC2_UTM_RXADDR0 AG292
PA4/REJECT2/DONE4 FCC2_UTM_RXADDR1 AG282
PA5/RESTART2/DREQ4 FCC2_UTM_RXADDR2/FCC1_UT_RX
PRTY AG262
PA6/FCC2_RXADDR3 L1RSYNCA1 AE242
PA7/SMSYN2/FCC2_TXADDR3 L1TSYNCA1/L1GNTA1 AH252
Tabl e 21. M PC8280 and MPC8270 (ZU and VV Packages) Pino ut List (continued)
Pin Name Ball
MPC8280/MPC8270 MPC8280 only
MPC8280 PowerQUI CC™ II Famil y Hardw are Sp ecif ications, Rev. 1.8
Freescale Semiconductor 51
Pinout
PA8/SMRXD2/FCC2_TXADDR4 L1RXD0A1/L1RXDA1 AF232
PA9/SMTXD2 L1TXD0A1 AH232
PA10/MSNUM5 FCC1_UT8_RXD0/FCC1_UT16_RXD8 AE222
PA11/MSNUM4 FCC1_UT8_RXD1/FCC1_UT16_RXD9 AH222
PA12/MSNUM3 FCC1_UT8_RXD2/
FCC1_UT16_RXD10 AJ212
PA13/MSNUM2 FCC1_UT8_RXD3/
FCC1_UT16_RXD11 AH202
PA14/FCC1_MII_HDLC_RXD3 FCC1_UT8_RXD4/
FCC1_UT16_RXD12 AG192
PA15/FCC1_MII_HDLC_RXD2 FCC1_UT8_RXD5/
FCC1_UT16_RXD13 AF182
PA16/FCC1_MII_HDLC_RXD1/
FCCI_RMII_RXD1 FCC1_UT8_RXD6/
FCC1_UT16_RXD14 AF172
PA17/FCC1_MII_HDLC_RXD0/
FCC1_MII_TRAN_RXD/
FCCI_RMII_RXD0
FCC1_UT8_RXD7/
FCC1_UT16_RXD15 AE162
PA18/FCC1_MII_HDLC_TXD0/
FCC1_MII_TRAN_TXD/
FCC1_RMII_TXD0
FCC1_UT8_TXD7/FCC1_UT16_TXD15 AJ162
PA19/FCC1_MII_HDLC_TXD1/
FCC1_RMII_TXD1 FCC1_UT8_TXD6/FCC1_UT16_TXD14 AG152
PA20/FCC1_MII_HDLC_TXD2 FCC1_UT8_TXD5/FCC1_UT16_TXD13 AJ132
PA21/FCC1_MII_HDLC_TXD3 FCC1_UT8_TXD4/FCC1_UT16_TXD12 AE132
PA22 FCC1_UT8_TXD3/FCC1_UT16_TXD11 AF122
PA23 FCC1_UT8_TXD2/FCC1_UT16_TXD10 AG112
PA24/MSNUM1 FCC1_UT8_TXD1/FCC1_UT16_TXD9 AH92
PA25/MSNUM0 FCC1_UT8_TXD0/FCC1_UT16_TXD8 AJ82
PA26/FCC1_RMII_RX_ER FCC1_UTM_RXCLAV/
FCC1_UTS_RXCLAV AH72
PA27/FCC1_MII_RX_DV/
FCC1_RMII_CRS_DV FCC1_UT_RXSOC AF72
PA28/FCC1_MII_TX_EN/
FCC1_RMII_TX_EN FCC1_UTM_RXENB/
FCC1_UTS_RXENB AD52
PA29/FCC1_MII_TX_ER FCC1_UT_TXSOC AF12
PA30/FCC1_MII_CRS/FCC1_RTS FCC1_UTM_TXCLAV/
FCC1_UTS_TXCLAV AD32
PA31/FCC1_MII_COL FCC1_UTM_TXENB/
FCC1_UTS_TXENB AB52
Tabl e 21. M PC8280 and MPC8270 (ZU and VV Packages) Pino ut List (continued)
Pin Name Ball
MPC8280/MPC8270 MPC8280 only
MPC8280 PowerQUI CC™ II Famil y Hardw are Sp ecif ications , Rev. 1.8
52 Freescale Semiconductor
Pinout
PB4/FCC3_MII_HDLC_TXD3/
L1RSYNCA2/FCC3_RTS FCC2_UT8_RXD0 AD282
PB5/FCC3_MII_HDLC_TXD2/
L1TSYNCA2/L1GNTA2 FCC2_UT8_RXD1 AD262
PB6/FCC3_MII_HDLC_TXD1/
FCC3_RMII_TXD1/
L1RXDA2/L1RXD0A2
FCC2_UT8_RXD2 AD252
PB7/FCC3_MII_HDLC_TXD0/
FCC3_RMII_TXD0/
FCC3_TXD/L1TXDA2/L1TXD0A2
FCC2_UT8_RXD3 AE262
PB8/FCC3_MII_HDLC_RXD0/
FCC3_RMII_RXD0/
FCC3_RXD/TXD3
FCC2_UT8_TXD3/L1RSYNCD1 AH272
PB9/FCC3_MII_HDLC_RXD1/
FCC3_RMII_RXD1/L1TXD2A2 FCC2_UT8_TXD2/L1TSYNCD1/
L1GNTD1 AG242
PB10/FCC3_MII_HDLC_RXD2 FCC2_UT8_TXD1/L1RXDD1 AH242
PB11/FCC3_MII_HDLC_RXD3 FCC2_UT8_TXD0/L1TXDD1 AJ242
PB12/FCC3_MII_CRS/TXD2 L1CLKOB1/L1RSYNCC1 AG222
PB13/FCC3_MII_COL/L1TXD1A2 L1RQB1/L1TSYNCC1/L1GNTC1 AH212
PB14/FCC3_MII_RMII_TX_EN//RXD3 L1RXDC1 AG202
PB15/FCC3_MII_TX_ER/RXD2 L1TXDC1 AF192
PB16/FCC3_MII_RMII_RX_ER/CLK18 L1CLKOA1 AJ182
PB17/FCC3_MII_RX_DV/CLK17/
FCC3_RMII_CRS_DV L1RQA1 AJ172
PB18/FCC2_MII_HDLC_RXD3/
L1CLKOD2/L1RXD2A2 FCC2_UT8_RXD4 AE142
PB19FCC2_MII_HDLC_RXD2/
L1RQD2/L1RXD3A2 FCC2_UT8_RXD5 AF132
PB20/FCC2_MII_HDLC_RMII_RXD1/
L1RSYNCD2 FCC2_UT8_RXD6/L1TXD1A1 AG122
PB21//FCC2_MII_HDLC_RMII_RXD0/
FCC2_TRAN_RXD/L1TSYNCD2/
L1GNTD2
FCC2_UT8_RXD7/L1TXD2A1 AH112
PB22/FCC2_MII_HDLC_TXD0/
FCC2_TXD/FCC2_RMII_TXD0/
L1RXDD2
FCC2_UT8_TXD7/L1RXD1A1 AH162
PB23/FCC2_MII_HDLC_TXD1/
L1RXD2A1/L1TXDD2/
FCC2_RMII_TXD1
FCC2_UT8_TXD6/L1RXD2A1 AE152
PB24/FCC2_MII_HDLC_TXD2/
L1RSYNCC2 FCC2_UT8_TXD5/L1RXD3A1 AJ92
Tabl e 21. M PC8280 and MPC8270 (ZU and VV Packages) Pino ut List (continued)
Pin Name Ball
MPC8280/MPC8270 MPC8280 only
MPC8280 PowerQUI CC™ II Famil y Hardw are Sp ecif ications, Rev. 1.8
Freescale Semiconductor 53
Pinout
PB25/FCC2_MII_HDLC_TXD3/
L1TSYNCC2/L1GNTC2 FCC2_UT8_TXD4/L1TXD3A1 AE92
PB26/FCC2_MII_CRS/L1RXDC2 FCC2_UT8_TXD1 AJ72
PB27/FCC2_MII_COL/L1TXDC2 FCC2_UT8_TXD0 AH62
PB28/FCC2_MII_RX_ER/
FCC2_RMII_RX_ER/FCC2_RTS/
L1TSYNCB2/L1GNTB2/TXD1
AE32
PB29/L1RSYNCB2/FCC2_MII_TX_EN/
FCC2_RMII_TX_EN FCC2_UTM_RXCLAV/
FCC2_UTS_RXCLAV AE22
PB30/FCC2_MII_RX_DV/
FCC2_RMII_CRS_DV/L1RXDB2 FCC2_UT_TXSOC AC52
PB31/FCC2_MII_TX_ER/L1TXDB2 FCC2_UT_RXSOC AC42
PC0/DREQ1/BRGO7/SMSYN2/
L1CLKOA2 AB262
PC1/DREQ2/BRGO6/L1RQA2/ SPISEL AD292
PC2/FCC3_CD/DONE2 FCC2_UT8_TXD3 AE292
PC3/FCC3_CTS/DACK2/CTS4/
USB_RP FCC2_UT8_TXD2 AE272
PC4/SI2_L1ST4/FCC2_CD FCC2_UTM_RXENB/
FCC2_UTS_RXENB AF272
PC5/SI2_L1ST3/FCC2_CTS FCC2_UTM_TXCLAV/
FCC2_UTS_TXCLAV AF242
PC6/FCC1_CD L1CLKOC1/FCC1_UTM_RXADDR2/
FCC1_UTS_RXADDR2/
FCC1_UTM_RXCLAV1
AJ262
PC7/FCC1_CTS L1RQC1/FCC1_UTM_TXADDR2/
FCC1_UTS_TXADDR2/
FCC1_UTM_TXCLAV1
AJ252
PC8/CD4/RENA4/SI2_L1ST2/CTS3/
USBRN FCC1_UT16_TXD0 AF222
PC9/CTS4/CLSN4/SI2_L1ST1/
L1TSYNCA2/L1GNTA2/USB_RP FCC1_UT16_TXD1 AE212
PC10/CD3/RENA3 FCC1_UT16_TXD2/SI1_L1ST4/
FCC2_UT8_RXD3 AF202
PC11/CTS3/CLSN3/L1TXD3A2 L1CLKOD1/FCC2_UT8_RXD2 AE192
PC12/CD2/RENA2 SI1_L1ST3/FCC1_UTM_RXADDR1/
FCC1_UTS_RXADDR1 AE182
PC13/CTS2/CLSN2 L1RQD1/FCC1_UTM_TXADDR1/
FCC1_UTS_TXADDR1 AH182
Tabl e 21. M PC8280 and MPC8270 (ZU and VV Packages) Pino ut List (continued)
Pin Name Ball
MPC8280/MPC8270 MPC8280 only
MPC8280 PowerQUI CC™ II Famil y Hardw are Sp ecif ications , Rev. 1.8
54 Freescale Semiconductor
Pinout
PC14/CD1/RENA1 FCC1_UTM_RXADDR0/
FCC1_UTS_RXADDR0 AH172
PC15/CTS1/CLSN1/SMTXD2 FCC1_UTM_TXADDR0/
FCC1_UTS_TXADDR0 AG162
PC16/CLK16/TIN4 AF152
PC17/CLK15/TIN3/BRGO8 AJ152
PC18/CLK14/TGATE2 AH142
PC19/CLK13/BRGO7/SPICLK AG132
PC20/CLK12/TGATE1/USB_OE AH122
PC21/CLK11/BRGO6 AJ112
PC22/CLK10/DONE1/FCC1_UT_TXPRTY AG102
PC23/CLK9/BRGO5/DACK1 AE102
PC24/CLK8/TOUT4 FCC2_UT8_TXD3 AF92
PC25/CLK7/BRGO4 FCC2_UT8_TXD2 AE82
PC26/CLK6/TOUT3/TMCLK AJ62
PC27/FCC3_TXD/FCC3_MII_TXD0/
FCC3_RMII_TXD0/CLK5/BRGO3 AG22
PC28/CLK4/TIN1/TOUT2/CTS2/CLSN2/
FCC2_RXADDR4 AF32
PC29/CLK3/TIN2/BRGO2/CTS1/CLSN1 AF22
PC30/CLK2/TOUT1 FCC2_UT8_TXD3 AE12
PC31/CLK1/BRGO1 AD12
PD4/BRGO8/FCC3_RTS/SMRXD2 L1TSYNCD1/L1GNTD1 AC282
PD5/DONE1 FCC1_UT16_TXD3 AD272
PD6/DACK1 FCC1_UT16_TXD4 AF292
PD7/SMSYN1/FCC1_TXCLAV2 FCC1_UTM_TXADDR3/
FCC1_UTS_TXADDR3/
FCC2_UTM_TXADDR4
FCC2_UTS_TXADDR1
AF282
PD8/SMRXD1/BRGO5 FCC2_UT_TXPRTY AG252
PD9/SMTXD1/BRGO3 FCC2_UT_RXPRTY AH262
PD10/L1CLKOB2/BRGO4 FCC2_UT8_RXD1/L1RSYNCB1 AJ272
PD11/L1RQB2 FCC2_UT8_RXD0/L1TSYNCB1/
L1GNTB1 AJ232
PD12 SI1_L1ST2/L1RXDB1 AG232
PD13 SI1_L1ST1/L1TXDB1 AJ222
Tabl e 21. M PC8280 and MPC8270 (ZU and VV Packages) Pino ut List (continued)
Pin Name Ball
MPC8280/MPC8270 MPC8280 only
MPC8280 PowerQUI CC™ II Famil y Hardw are Sp ecif ications, Rev. 1.8
Freescale Semiconductor 55
Pinout
PD14/L1CLKOC2/I2CSCL FCC1_UT16_RXD0 AE202
PD15/L1RQC2/I2CSDA FCC1_UT16_RXD1 AJ202
PD16/SPIMISO FCC1_UT_TXPRTY/L1TSYNCC1/
L1GNTC1 AG182
PD17/BRGO2/SPIMOSI FCC1_UT_RXPRTY AG172
PD18/SPICLK FCC1_UTM_RXADDR4/
FCC1_UTS_RXADDR4/
FCC1_UTM_RXCLAV3/
FCC2_UTM_RXADDR3/
FCC2_UTS_RXADDR0
AF162
PD19/SPISEL/BRGO1 FCC1_UTM_TXADDR4/
FCC1_UTS_TXADDR4/
FCC1_UTM_TXCLAV3/
FCC2_UTM_TXADDR3/
FCC2_UTS_TXADDR0
AH152
PD20/RTS4/TENA4/L1RSYNCA2/
USB_TP FCC1_UT16_RXD2 AJ142
PD21/TXD4/L1RXD0A2/L1RXDA2/
USB_TN FCC1_UT16_RXD3 AH132
PD22/RXD4L1TXD0A2/L1TXDA2/
USB_RXD FCC1_UT16_TXD5 AJ122
PD23/RTS3/TENA3 FCC1_UT16_RXD4/L1RSYNCD1 AE122
PD24/TXD3 FCC1_UT16_RXD5/L1RXDD1 AF102
PD25/RXD3 FCC1_UT16_TXD6/L1TXDD1 AG92
PD26/RTS2/TENA2 FCC1_UT16_RXD6/L1RSYNCC1 AH82
PD27/TXD2 FCC1_UT16_RXD7/L1RXDC1 AG72
PD28/RXD2 FCC1_UT16_TXD7/L1TXDC1 AE42
PD29/RTS1/TENA1 FCC1_UTM_RXADDR3/
FCC1_UTS_RXADDR3/
FCC1_UTM_RXCLAV2/
FCC2_UTM_RXADDR4/
FCC2_UTS_RXADDR1
AG12
PD30/TXD1 FCC2_UTM_TXENB/
FCC2_UTS_TXENB AD42
PD31/RXD1 AD22
VCCSYN AB3
VCCSYN1 B9
CLKIN2 AE11
SPARE4 3 U5
Tabl e 21. M PC8280 and MPC8270 (ZU and VV Packages) Pino ut List (continued)
Pin Name Ball
MPC8280/MPC8270 MPC8280 only
MPC8280 PowerQUI CC™ II Famil y Hardw are Sp ecif ications , Rev. 1.8
56 Freescale Semiconductor
Pinout
Symbols used in Table 21 are described in Table 22.
PCI_MODE 4 AF25
SPARE63V4
No connect 5 AA1, AG4
I/O power AG21, AG14, AG8, AJ1, AJ2,
AH1, AH2, AG3, AF4, AE5, AC27 ,
Y27, T27, P27, K26, G27, AE 25,
AF26, AG27, AH28, AH29, AJ28,
AJ29, C7, C14, C16, C20, C23,
E10, A28, A29, B28, B29, C2 7,
D2 6 , E 2 5, H3, M 4 , T 3, AA4 , A 1 ,
A2, B1, B2, C3, D4, E5
Core power U28, U29, K28, K29, A9, A19,
B19, M1, M2, Y1, Y2, AC1, AC2,
AH19, AJ19, AH10, AJ10, AJ5
Ground AA5, AB1 6, AB2 7, AF21, AF14,
AF8, AE7, AF11 , AE17, AE23,
AC26, AB25, Y26, V25, T26, R25,
P26, M25, K27, H25, G26, D7,
D10, D14, D16, D20, D23, C9,
E11, E13, E15, E1 9, E22, B3, G5,
H4, K5, M3, P5, T4, Y5, AA2, AC3
1
Should be tied to VDDH via a 2K Ω external pull-up resis tor.
2
The default configuration of the CPM pins (PA[0–31], PB[4–31], PC[0–31], PD[4–31]) is i nput. To prevent excessive
DC current, it is recommended t o either pull unuse d pins to GND or VDDH, or to configure them as outputs.
3
Must be pulled down or left floating.
4
If PCI is not des ired, must be pulled u p or left floating.
5
Sphere is no t connected to die.
6
GNDSYN (AB1): This pi n ex ists as a s eparat e ground si gnal i n MPC826x( A) devic es; it does no t exist as a se parate
ground signal on the MPC8 280. Ne w designs must connect AB1 to GND and fol low the suggestions in Section 4.6,
“Layout Practices.” Ol d desi gns in wh ich t he MPC8280 is us ed a s a dr op- in re placement c an lea ve the pi n connec te d
to GND with the noise filtering c apacitors.
7
XFC (AB2) pin: This pin is used in MPC826x(A) devices; i t is not used in M PC8280 because there is no need for
exter nal cap acitor to oper ate the PLL . New design s shou ld connec t AB2 (XFC) pin t o GND. Old desi gns in whi ch the
MPC8280 is used as a drop-in replacem ent can leave t he pin co nnected to the cur rent capacitor.
T able 22. Symbol Legend
Symbol Meaning
OVERBAR Signals with overbars, such as TA, are activ e low.
UTM Indicates that a signal is pa rt o f the UTO P IA master interface.
UTS Indicates t hat a signal is part of the UTO PIA slave int erf ace.
Tabl e 21. M PC8280 and MPC8270 (ZU and VV Packages) Pino ut List (continued)
Pin Name Ball
MPC8280/MPC8270 MPC8280 only
MPC8280 PowerQUI CC™ II Famil y Hardw are Sp ecif ications, Rev. 1.8
Freescale Semiconductor 57
Pinout
8.2 VR and ZQ Packages—MP C8275 and MP C8270
The foll owing figures and ta ble represent the alternate 516 P BGA packa ge. F or informatio n on the standard package
for the MPC8280 and the MPC8270, refer to Sect ion 8.1, “ZU and VV Packages—MPC8280 and MPC8270,” on
page -42.
Figure 15 shows the pinout of the VR and ZQ packages as viewe d fr om the top surface.
UT8 Indi cates that a signal is pa rt o f the 8-bit UTOPIA in terface.
UT16 Indicates that a signal is part of the 16-bit UTOPIA interface.
MII Indicates t hat a signal is part of the media independent interface.
RMII Indicates that a signal is part of the reduced media independent interface.
Table 2 2. S ym bol Le ge n d ( continu e d)
Symbol Meaning
MPC8280 PowerQUI CC™ II Famil y Hardw are Sp ecif ications , Rev. 1.8
58 Freescale Semiconductor
Pinout
Figur e 15. Pinout of the 516 PBGA Package (View from To p)
Figure 16 sho ws the sid e prof ile of the PBGA pa ckag e t o indicate the d ir ecti o n of the top s urface view.
Figure 16. Side View of the PB GA Packag e Rem ove
1234567891011121314151617 18 19 20 21 22 23 24 25 26
Not to Scale
1234567891011121314151617181920212223242526
A
B
C
D
E
F
G
H
J
K
L
M
N
P
R
T
U
V
W
Y
AA
AB
AC
AD
AE
AF
A
B
C
D
E
F
G
H
J
K
L
M
N
P
R
T
U
V
W
Y
AA
AB
AC
AD
AE
AF
Die
Transfer molding compound
1 mm pitch
Wire bonds
attach
DIE
Ball bond Screen-printed
so ld er ma s k
Cu substrate traces
BT resin glass epoxy
Plated substrate via
MPC8280 PowerQUI CC™ II Famil y Hardw are Sp ecif ications, Rev. 1.8
Freescale Semiconductor 59
Pinout
NO T E: Tem p er ature R efl o w fo r the VR Pack ag e
In the VR package, sphere composition is lead-free (refer to Table 2). This requires
higher temperatur e reflow than what is required for other PowerQUICC II
packages. Users should consult “Freescale PowerQUICC II™ Pb-Free Packaging
Information” (MPC8250PBFREEPKG) available at www.freescale.com.
Table 23 shows the pinout list of the MPC8275 a nd MPC8270. Table 22 defines conv entions and acr onyms used in
Table 23.
Table 23. MPC8275 and MPC8270 (VR and ZQ Packages) Pinout List
Pin Name Ball
MPC827 5/MPC8270 MPC82 75 only
BR C16
BG D2
ABB/IRQ2 C1
TS D1
A0 D5
A1 E8
A2 C4
A3 B4
A4 A4
A5 D7
A6 D8
A7 C6
A8 B5
A9 B6
A10 C7
A11 C8
A12 A6
A13 D9
A14 F11
A15 B7
A16 B8
A17 C9
A18 A7
A19 B9
A20 E11
A21 A8
MPC8280 PowerQUI CC™ II Famil y Hardw are Sp ecif ications , Rev. 1.8
60 Freescale Semiconductor
Pinout
A22 D11
A23 B10
A24 C11
A25 A9
A26 B11
A27 C12
A28 D12
A29 A10
A30 B12
A31 B13
TT0 E7
TT1 B3
TT2 F8
TT3 A3
TT4 C3
TBST F5
TSIZ0 E3
TSIZ1 E2
TSIZ2 E1
TSIZ3 E4
AACK D3
ARTRY C2
DBG A14
DBB/IRQ3 C15
D0 W4
D1 Y1
D2 V1
D3 P4
D4 N3
D5 K5
D6 J4
D7 G1
D8 AB1
Tabl e 23. MPC8275 and MPC8270 (VR and ZQ Pack ages) Pinou t List (continued)
Pin Name Ball
MPC827 5/MPC8270 MPC82 75 only
MPC8280 PowerQUI CC™ II Famil y Hardw are Sp ecif ications, Rev. 1.8
Freescale Semiconductor 61
Pinout
D9 U4
D10 U2
D11 N6
D12 N1
D13 L1
D14 J5
D15 G3
D16 AA2
D17 W1
D18 T3
D19 T1
D20 M2
D21 K2
D22 J1
D23 G4
D24 U5
D25 T5
D26 P5
D27 P3
D28 M3
D29 K3
D30 H2
D31 G5
D32 AA1
D33 V2
D34 U1
D35 P2
D36 M4
D37 K4
D38 H3
D39 F2
D40 Y2
D41 U3
Tabl e 23. MPC8275 and MPC8270 (VR and ZQ Pack ages) Pinou t List (continued)
Pin Name Ball
MPC827 5/MPC8270 MPC82 75 only
MPC8280 PowerQUI CC™ II Famil y Hardw are Sp ecif ications , Rev. 1.8
62 Freescale Semiconductor
Pinout
D42 T2
D43 N2
D44 M5
D45 K1
D46 H4
D47 F1
D48 W2
D49 T4
D50 R3
D51 N4
D52 M1
D53 J2
D54 H5
D55 F3
D56 V3
D57 R5
D58 R2
D59 N5
D60 L2
D61 J3
D62 H1
D63 F4
DP0/RSRV/EXT_BR2 AB3
IRQ1/DP1/EXT_BG2 W5
IRQ2/DP2/TLBISYNC/EXT_DBG2 AC2
IRQ3/DP3/CKSTP_OUT/EXT_BR3 AA3
IRQ4/DP4/CORE_SRESET/EXT_BG3 AD1
IRQ5/CINT/DP5/TBEN/EXT_DBG3 AC1
IRQ6/DP6/CSE0 AB2
IRQ7/DP7/CSE1 Y3
PSDVAL D15
TA Y4
TEA D16
Tabl e 23. MPC8275 and MPC8270 (VR and ZQ Pack ages) Pinou t List (continued)
Pin Name Ball
MPC827 5/MPC8270 MPC82 75 only
MPC8280 PowerQUI CC™ II Famil y Hardw are Sp ecif ications, Rev. 1.8
Freescale Semiconductor 63
Pinout
GBL/IRQ1 E15
CI/BADDR29/IRQ2 D14
WT/BADDR30/IRQ3 E14
L2_HIT/IRQ4 A17
CPU_BG/BADDR31/IRQ5/CINT B14
CPU_DBG F13
CPU_BR B17
CS0 AC6
CS1 AD6
CS2 AE6
CS3 AB7
CS4 AF7
CS5 AC7
CS6 AD7
CS7 AF8
CS8 AE8
CS9 AD8
CS10/BCTL1 AC8
CS11/AP0 AB8
BADDR27 C13
BADDR28 A12
ALE D13
BCTL0 AF4
PWE0/PSDDQM0/PBS0 AA5
PWE1/PSDDQM1/PBS1 AE4
PWE2/PSDDQM2/PBS2 AD4
PWE3/PSDDQM3/PBS3 AF3
PWE4/PSDDQM4/PBS4 AB4
PWE5/PSDDQM5/PBS5 AE3
PWE6/PSDDQM6/PBS6 AF2
PWE7/PSDDQM7/PBS7 AD3
PSDA10/PGPL0 AE2
PSDWE/PGPL1 AD2
Tabl e 23. MPC8275 and MPC8270 (VR and ZQ Pack ages) Pinou t List (continued)
Pin Name Ball
MPC827 5/MPC8270 MPC82 75 only
MPC8280 PowerQUI CC™ II Famil y Hardw are Sp ecif ications , Rev. 1.8
64 Freescale Semiconductor
Pinout
POE/PSDRAS/PGPL2 AE1
PSDCAS/PGPL3 AC3
PGTA/PUPMWAIT/PGPL4/PPBS W6
PSDAMUX/PGPL5 AA4
LWE0/LSDDQM0/LBS0/PCI_CFG0 AC9
LWE1/LSDDQM1/LBS1/PCI_CFG1 AD9
LWE2/LSDDQM2/LBS2/PCI_CFG2 AE9
LWE3/LSDDQM3/LBS3/PCI_CFG3 AF9
LSDA10/LGPL0/PCI_MODCKH0 AB6
LSDWE/LGPL1/PCI_MODCKH1 AF5
LOE/LSDRAS/LGPL2/PCI_MODCKH2 AE5
LSDCAS/LGPL3/PCI_MODCKH3 AD5
LGTA/LUPMWAIT/LGPL4/LPBS AC5
LGPL5/LSDAMUX/PCI_MODCK AB5
LWR AF6
L_A14/PAR AE13
L_A15/FRAME/SMI AD15
L_A16/TRDY AF16
L_A17/IRDY/CKSTP_OUT AF15
L_A18/STOP AE15
L_A19/DEVSEL AE14
L_A20/IDSEL AC17
L_A21/PERR AD14
L_A22/SERR AF13
L_A23/REQ0 AE20
L_A24/REQ1/HSEJSW AC14
L_A25/GNT0 AC19
L_A26/GNT1/HSLED AD13
L_A27/GNT2/HSENUM AF21
L_A28/RST/CORE_SRESET AF22
L_A29/INTA AE21
L_A30/REQ2 AB14
L_A31/DLLOUT AD20
Tabl e 23. MPC8275 and MPC8270 (VR and ZQ Pack ages) Pinou t List (continued)
Pin Name Ball
MPC827 5/MPC8270 MPC82 75 only
MPC8280 PowerQUI CC™ II Famil y Hardw are Sp ecif ications, Rev. 1.8
Freescale Semiconductor 65
Pinout
LCL_D0/AD0 AB9
LCL_D1/AD1 AB10
LCL_D2/AD2 AC10
LCL_D3/AD3 AD10
LCL_D4/AD4 AE10
LCL_D5/AD5 AF10
LCL_D6/AD6 AF11
LCL_D7/AD7 AB12
LCL_D8/AD8 AB11
LCL_D9/AD9 AF12
LCL_D10/AD10 AE11
LCL_D11/AD11 AC13
LCL_D12/AD12 AC12
LCL_D13/AD13 AB13
LCL_D14/AD14 AD12
LCL_D15/AD15 AF14
LCL_D16/AD16 AF17
LCL_D17/AD17 AE16
LCL_D18/AD18 AD16
LCL_D19/AD19 AC16
LCL_D20/AD20 AB16
LCL_D21/AD21 AF18
LCL_D22/AD22 AE17
LCL_D23/AD23 AD17
LCL_D24/AD24 AB17
LCL_D25/AD25 AE18
LCL_D26/AD26 AD18
LCL_D27/AD27 AC18
LCL_D28/AD28 AE19
LCL_D29/AD29 AF20
LCL_D30/AD30 AD19
LCL_D31/AD31 AB18
LCL_DP0/C0/BE0 AE12
Tabl e 23. MPC8275 and MPC8270 (VR and ZQ Pack ages) Pinou t List (continued)
Pin Name Ball
MPC827 5/MPC8270 MPC82 75 only
MPC8280 PowerQUI CC™ II Famil y Hardw are Sp ecif ications , Rev. 1.8
66 Freescale Semiconductor
Pinout
LCL_DP1/C1/BE1 AA13
LCL_DP2/C2/BE2 AC15
LCL_DP3/C3/BE3 AF19
IRQ0/NMI_OUT A11
IRQ7/INT_OUT/APE E5
TRST 1 F22
TCK A24
TMS C24
TDI A25
TDO B24
TRIS C19
PORESET1B25
HRESET D24
SRESET E23
QREQ D18
RSTCONF E24
MODCK1/AP1/TC0/BNKSEL0 B16
MODCK2/AP2/TC1/BNKSEL1 F16
MODCK3/AP3/TC2/BNKSEL2 A15
CLKIN1 G22
PA0/RESTART1/DREQ3 FCC2_UTM_TXADDR2 AC20 2
PA1/REJECT1/DONE3 FCC2_UTM_TXADDR1 AC212
PA2/CLK20/DACK3 FCC2_UTM_TXADDR0 AF252
PA3/CLK19/DACK4/L1RXD1A2 FCC2_UTM_RXADDR0 AE242
PA4/REJECT2/DONE4 FCC2_UTM_RXADDR1 AA212
PA5/RESTART2/DREQ4 FCC2_UTM_RXADDR2 AD252
PA6 FCC2_UT_RXADDR3 AC242
PA7/SMSYN2 FCC2_UT_TXADDR3 AA222
PA8/SMRXD2 FCC2_UT_TXADDR4 AA232
PA9/SMTXD2 Y262
PA10/MSNUM5 FCC1_UT8_RXD0/FCC1_UT16_RXD8 W222
PA11/MSNUM4 FCC1_UT8_RXD1/FCC1_UT16_RXD9 W232
PA12/MSNUM3 FCC1_UT8_RXD2/
FCC1_UT16_RXD10 V262
Tabl e 23. MPC8275 and MPC8270 (VR and ZQ Pack ages) Pinou t List (continued)
Pin Name Ball
MPC827 5/MPC8270 MPC82 75 only
MPC8280 PowerQUI CC™ II Famil y Hardw are Sp ecif ications, Rev. 1.8
Freescale Semiconductor 67
Pinout
PA13/MSNUM2 FCC1_UT8_RXD3/
FCC1_UT16_RXD11 V252
PA14/FCC1_MII_HDLC_RXD3 FCC1_UT8_RXD4/
FCC1_UT16_RXD12 T222
PA15/FCC1_MII_HDLC_RXD2 /FCC1_UT8_RXD5/
FCC1_UT16_RXD13 T252
PA16/FCC1_MII_HDLC_RXD1/
FCC1_RMII_RXD1 FCC1_UT8_RXD6/
FCC1_UT16_RXD14 R242
PA17/FCC_MII_HDLC_RXD0/
FCC1_MII_TRAN_RXD/
FCCI_RMII_RXD0
FCC1_UT8_RXD7/
FCC1_UT16_RXD15 P222
PA18/FCC1_MII_HDLC_TXD0/
FCC1_MIITRAN_TXD/
FCC1_RMII_TXD0
FCC1_UT8_TXD7/FCC1_UT16_TXD15 N262
PA19/FCC1_MII_HDLC_TXD1/
FCC1_RMII_TXD1 FCC1_UT8_TXD6/FCC1_UT16_TXD14 N232
PA20/FCC1_MII_HDLC_TXD2 FCC1_UT8_TXD5/FCC1_UT16_TXD13 K262
PA21/FCC1_MII_HDLC_TXD3 FCC1_UT8_TXD4/FCC1_UT16_TXD12 L232
PA22 FCC1_UT8_TXD3/FCC1_UT16_TXD11 K232
PA23 FCC1_UT8_TXD2/FCC1_UT16_TXD10 H262
PA24/MSNUM1 FCC1_UT8_TXD1/FCC1_UT16_TXD9 F252
PA25/MSNUM0 FCC1_UT8_TXD0/FCC1_UT16_TXD8 D262
PA26/FCC1_MII_RMII_RX_ER/ FCC1_UTM_RXCLAV/
FCC1_UTS_RXCLAV D252
PA27/FCC1_MII_RX_DV/
FCC1_RMII_CRS_DV FCC1_UT_RXSOC C252
PA28/FCC1_MII_TX_EN/
FCC1_RMII_TX_EN FCC1_UTM_RXENB/
FCC1_UTS_RXENB C222
PA29/FCC1_MII_TX_ER FCC1_UT_TXSOC B212
PA30/FCC1_MII_CRS/FCC1_RTS FCC1_UTM_TXCLAV/
FCC1_UTS_TXCLAV A202
PA31/FCC1_MII_COL FCC1_UTM_TXENB/
FCC1_UTS_TXENB A192
PB4/FCC3_MII_HDLC_TXD3/
L1RSYNCA2/FCC3_RTS FCC2_UT8_RXD0 AD212
PB5/FCC3_MII_HDLC_TXD2/
L1TSYNCA2/L1GNTA2 FCC2_UT8_RXD1 AD222
PB6/FCC3_MII_HDLC_TXD1/
FCC3_RMII_TXD1/
L1RXDA2/L1RXD0A2
FCC2_UT8_RXD2 AC222
Tabl e 23. MPC8275 and MPC8270 (VR and ZQ Pack ages) Pinou t List (continued)
Pin Name Ball
MPC827 5/MPC8270 MPC82 75 only
MPC8280 PowerQUI CC™ II Famil y Hardw are Sp ecif ications , Rev. 1.8
68 Freescale Semiconductor
Pinout
PB7/FCC3_MII_HDLC_TXD0/
FCC3_RMII_TXD0/
FCC3_TXD/L1TXDA2/L1TXD0A2
FCC2_UT8_RXD3 AE262
PB8/FCC3_MII_HDLC_RXD0/
FCC3_RMII_RXD0/
FCC3_RXD/TXD3
FCC2_UT8_TXD3 AB232
PB9/FCC3_MII_HDLC_RXD1/
FCC3_RMII_RXD1/L1TXD2A2 FCC2_UT8_TXD2 AC262
PB10/FCC3_MII_HDLC_RXD2 FCC2_UT8_TXD1 AB262
PB11/FCC3_MII_HDLC_RXD3 FCC2_UT8_TXD0 AA252
PB12/FCC3_MII_CRS/TXD2 W262
PB13/FCC3_MII_COL/L1TXD1A2 W252
PB14/FCC3_MII_RMII_TX_EN/RXD3 V242
PB15/FCC3_MII_TX_ER/RXD2 U242
PB16/FCC3_MII_RMII_RX_ER/CLK18 R222
PB17/FCC3_MII_RX_DV/CLK17/
FCC3_RMII_CRS_DV R232
PB18/FCC2_MII_HDLC_RXD3/
L1CLKOD2/L1RXD2A2 FCC2_UT8_RXD4 M232
PB19FCC2_MII_HDLC_RXD2/
L1RQD2/L1RXD3A2 FCC2_UT8_RXD5 L242
PB20/FCC2_MII_HDLC_RMII_RXD1/
L1RSYNCD2 FCC2_UT8_RXD6 K242
PB21//FCC2_MII_HDLC_RMII_RXD0/
FCC2_TRAN_RXD/L1TSYNCD2/
L1GNTD2
FCC2_UT8_RXD7 L212
PB22/FCC2_MII_HDLC_RMII_TXD0/
FCC2_TXD/FCC2_RMII_TXD0/
L1RXDD2
FCC2_UT8_TXD7 P252
PB23/FCC2_MII_HDLC_TXD1/
L1RXD2A1/L1TXDD2/
FCC2_RMII_TXD1
FCC2_UT8_TXD6 N252
PB24/FCC2_MII_HDLC_TXD2/
L1RSYNCC2 FCC2_UT8_TXD5 E262
PB25/FCC2_MII_HDLC_TXD3/
L1TSYNCC2/L1GNTC2 FCC2_UT8_TXD4 H232
PB26/FCC2_MII_CRS/L1RXDC2 FCC2_UT8_TXD1 C262
PB27/FCC2_MII_COL/L1TXDC2 FCC2_UT8_TXD0 B262
PB28/FCC2_MII_RX_ER/FCC2_RMII_RX_ER/
FCC2_RTS/L1TSYNCB2/L1GNTB2/TXD1 A222
Tabl e 23. MPC8275 and MPC8270 (VR and ZQ Pack ages) Pinou t List (continued)
Pin Name Ball
MPC827 5/MPC8270 MPC82 75 only
MPC8280 PowerQUI CC™ II Famil y Hardw are Sp ecif ications, Rev. 1.8
Freescale Semiconductor 69
Pinout
PB29/L1RSYNCB2/
FCC2_MII_TX_EN/FCC2_RMII_TX_EN FCC2_UTM_RXCLAV/
FCC2_UTS_RXCLAV A212
PB30/FCC2_MII_RX_DV/L1RXDB2/
FCC2_RMII_CRS_DV FCC2_UT_TXSOC E202
PB31/FCC2_MII_TX_ER/L1TXDB2 FCC2_UT_RXSOC C202
PC0/DREQ1/BRGO7/SMSYN2/
L1CLKOA2 AE222
PC1/DREQ2/SPISEL/BRGO6/L1RQA2 AA192
PC2/FCC3_CD/DONE2 FCC2_UT8_TXD3 AF242
PC3/FCC3_CTS/DACK2/CTS4/
USB_RP FCC2_UT8_TXD2 AE252
PC4/SI2_L1ST4/FCC2_CD FCC2_UTM_RXENB/
FCC2_UTS_RXENB AB222
PC5/SI2_L1ST3/FCC2_CTS FCC2_UTM_TXCLAV/
FCC2_UTS_TXCLAV AC252
PC6/FCC1_CD FCC1_UTM_RXADDR2/
FCC1_UTS_RXADDR2/
FCC1_UTM_RXCLAV1
AB252
PC7/FCC1_CTS FCC1_UTM_TXADDR2/
FCC1_UTS_TXADDR2/
FCC1_UTM_TXCLAV1
AA242
PC8/CD4/RENA4/SI2_L1ST2/CTS3/
USB_RN FCC1_UT16_TXD0 Y242
PC9/CTS4/CLSN4/SI2_L1ST1/
L1TSYNCA2/L1GNTA2/USB_RP FCC1_UT16_TXD1 U222
PC10/CD3/RENA3 FCC1_UT16_TXD2/FCC2_UT8_RXD3 V232
PC11/CTS3/CLSN3/L1TXD3A2 FCC2_UT8_RXD2 U232
PC12/CD2/RENA2 FCC1_UTM_RXADDR1/
FCC1_UTS_RXADDR1 T262
PC13/CTS2/CLSN2 FCC1_UTM_TXADDR1/
FCC1_UTS_TXADDR1 R262
PC14/CD1/RENA1 FCC1_UTM_RXADDR0/
FCC1_UTS_RXADDR0 P262
PC15/CTS1/CLSN1/SMTXD2 FCC1_UTM_TXADDR0/
FCC1_UTS_TXADDR0 P242
PC16/CLK16/TIN4 M262
PC17/CLK15/TIN3/BRGO8 L262
PC18/CLK14/TGATE2 M242
PC19/CLK13/BRGO7/SPICLK L222
Tabl e 23. MPC8275 and MPC8270 (VR and ZQ Pack ages) Pinou t List (continued)
Pin Name Ball
MPC827 5/MPC8270 MPC82 75 only
MPC8280 PowerQUI CC™ II Famil y Hardw are Sp ecif ications , Rev. 1.8
70 Freescale Semiconductor
Pinout
PC20/CLK12/TGATE1/USB_OE K252
PC21/CLK11/BRGO6 J252
PC22/CLK10/DONE1 FCC1_UT_TXPRTY G262
PC23/CLK9/BRGO5/DACK1 F262
PC24/CLK8/TOUT4 FCC2_UT8_TXD3 G242
PC25/CLK7/BRGO4 FCC2_UT8_TXD2 E252
PC26/CLK6/TOUT3/TMCLK G232
PC27/FCC3_TXD/FCC3_MII_TXD0/
FCC3_RMII_TXD0/CLK5/BRGO3 B232
PC28/CLK4/TIN1/TOUT2/CTS2/CLSN2 FCC2_UT_RXADDR4 E222
PC29/CLK3/TIN2/BRGO2/CTS1/CLSN1 E212
PC30/CLK2/TOUT1 FCC2_UT8_TXD3 D212
PC31/CLK1/BRGO1 B202
PD4/BRGO8/FCC3_RTS/SMRXD2 AF232
PD5/DONE1 FCC1_UT16_TXD3 AE232
PD6/DACK1 FCC1_UT16_TXD4 AB212
PD7/SMSYN1/FCC1_TXCLAV2 FCC1_UTM_TXADDR3/
FCC1_UTS_TXADDR3/
FCC2_UTM_TXADDR4
FCC2_UTS_TXADDR1
AD232
PD8/SMRXD1/BRGO5 FCC2_UT_TXPRTY AD262
PD9/SMTXD1/BRGO3 FCC2_UT_RXPRTY Y222
PD10/L1CLKOB2/BRGO4 FCC2_UT8_RXD1 AB242
PD11/L1RQB2 FCC2_UT8_RXD0
L1GNTB1 Y232
PD12 AA262
PD13 W242
PD14/L1CLKOC2/I2CSCL FCC1_UT16_RXD0 V222
PD15/L1RQC2/I2CSDA FCC1_UT16_RXD1 U262
PD16/SPIMISO FCC1_UT_TXPRTY T232
PD17/BRGO2/SPIMOSI FCC1_UT_RXPRTY R252
PD18/SPICLK FCC1_UTM_RXADDR4/
FCC1_UTS_RXADDR4/
FCC1_UTM_RXCLAV3/
FCC2_UTM_RXADDR3/
FCC2_UTS_RXADDR0
P232
Tabl e 23. MPC8275 and MPC8270 (VR and ZQ Pack ages) Pinou t List (continued)
Pin Name Ball
MPC827 5/MPC8270 MPC82 75 only
MPC8280 PowerQUI CC™ II Famil y Hardw are Sp ecif ications, Rev. 1.8
Freescale Semiconductor 71
Pinout
PD19/SPISEL/BRGO1 FCC1_UTM_TXADDR4/
FCC1_UTS_TXADDR4/
FCC1_UTM_TXCLAV3/
FCC2_UTM_TXADDR3/
FCC2_UTS_TXADDR0
N222
PD20/RTS4/TENA4/L1RSYNCA2/
USB_TP FCC1_UT16_RXD2 M252
PD21/TXD4/L1RXD0A2/L1RXDA2/
USB_TN FCC1_UT16_RXD3 L252
PD22/RXD4L1TXD0A2/L1TXDA2/
USB_RXD FCC1_UT16_TXD5 J262
PD23/RTS3/TENA3 FCC1_UT16_RXD4 K222
PD24/TXD3 FCC1_UT16_RXD5 G252
PD25/RXD3 FCC1_UT16_TXD6 H242
PD26/RTS2/TENA2 FCC1_UT16_RXD6 F242
PD27/TXD2 FCC1_UT16_RXD7 H222
PD28/RXD2 FCC1_UT16_TXD7 B222
PD29/RTS1/TENA1 FCC1_UTM_RXADDR3/
FCC1_UTS_RXADDR3/
FCC1_UTM_RXCLAV2/
FCC2_UTM_RXADDR4/
FCC2_UTS_RXADDR1
D222
PD30/TXD1 FCC2_UTM_TXENB/
FCC2_UTS_TXENB C212
PD31/RXD1 E192
VCCSYN D19
VCCSYN1 K6
CLKIN2 K21
SPARE4 3 C14
PCI_MODE 4 AD24
SPARE63B15
No connect 5 E17, C23
I/O power E6, F6, H6 , L5, L 6 , P6, T 6 , U6, V 5 ,
Y5, AA6, AA8, AA10, AA11, AA14,
AA16, AA17, AB19, AB20, W21,
U21, T 21, P21, N21, M22, J 22, H21,
F21, F19, F17, E16, F14, E13, E12,
F10, E10, E9
Tabl e 23. MPC8275 and MPC8270 (VR and ZQ Pack ages) Pinou t List (continued)
Pin Name Ball
MPC827 5/MPC8270 MPC82 75 only
MPC8280 PowerQUI CC™ II Famil y Hardw are Sp ecif ications , Rev. 1.8
72 Freescale Semiconductor
Package Descripti on
9 Package Description
The following sections provide the package parameters and mechanical dimensions.
9.1 Package Parameters
Package par ame ters are provided in Table 24.
Core Power L3, V4, W3, AC11, AD11, AB15,
U25, T24, J24, H25, F23, B19, D17,
C17, D10, C10
Ground B18 6, A1 8 7, A2, B1, B2, A5, C5,
C18, D4, D6, G2, L4, P1, R1, R4,
AC4, AE7, AC23, Y25, N24, J23,
A23, D2 3, D20, E18, A13, A16, K10,
K11, K12 , K13, K14, K15, K16, K17,
L10, L11, L 12, L13, L14, L15, L16,
L17, M10, M11, M12, M1 3, M14,
M15, M16 , M17, N10, N11, N12,
N13, N14, N15, N16, N17, P10, P11,
P12, P13, P14, P15, P16, P17, R10,
R11,R12, R13, R14, R15, R16, R17,
T10, T11, T1 2, T13, T14, T15, T16,
T17, U10, U1 1, U12, U13, U14, U15,
U16, U17
1
Should be tied to VDDH via a 2K Ω external pull- up resistor.
2
The default configuration of t he CPM pi ns (PA[0–31], PB[4–31], PC[0–31], PD[4–31]) is input . To prevent excessive DC
current, it is recommended to either pull unused pins to GND or VDDH, or to configure them as outputs.
3
Must be pulled down or left floating.
4
If PCI is not desired, must be pulled up or left floating.
5
Sphere is not connect ed to die.
6
GNDSYN (B 18): This p in exists as a separate ground signal in M PC8 26x(A) devices; it does not exist as a s eparate ground
signal on the MPC8275/ MPC8270. New designs must connect B18 to GND and f ollow t he suggesti ons in Sect ion 4.6, “L ayout
Practices.” Old designs in which the MPC8275/ M PC8270 is used as a drop-in replacement c an leave the pin con nected to
GND with the noise filt ering capacitors.
7
XFC (A18) pi n: This pin is used in MPC826x (A) de vices; it is not used in MPC8275/MPC8270 because there is no need for
external capacitor to operate the PLL. New designs should co nnect A18 (XFC) pin to GND. Old desi gns in which the
MPC8275/ MPC8 270 is us ed as a drop-in replacement can leave the pin connected to the cu rrent capacitor.
Tabl e 23. MPC8275 and MPC8270 (VR and ZQ Pack ages) Pinou t List (continued)
Pin Name Ball
MPC827 5/MPC8270 MPC82 75 only
MPC8280 PowerQUI CC™ II Famil y Hardw are Sp ecif ications, Rev. 1.8
Freescale Semiconductor 73
Package Description
Table 24. P ackage Param e te rs
Package Devices Outline
(mm) Type Interconnects Pi tch
(mm) Nominal Unmounted
Height (mm)
ZU MPC8280
MPC8270 37.5 × 37.5 TBGA 480 1.27 1.55
VV MPC8280
MPC8270 37.5 × 37.5 TBGA 480 1.27 1.55
VR MPC8275VR
MPC8270VR 27 × 27 PBGA 516 1 2.25
ZQ MPC8275ZQ
MPC8270ZQ 27 × 27 PBGA 516 1 2 .25
MPC8280 PowerQUI CC™ II Famil y Hardw are Sp ecif ications , Rev. 1.8
74 Freescale Semiconductor
Package Descripti on
9.2 Mechanical Dimensions
Figure 17 provides the mechanic al dimensions and bottom surface nomenclature of the 480 TBGA (ZU/VV)
package. Refer to Table 2.
Figure 17. Mech anical Dimensions an d Bottom Surfac e Nomenc lature— 480 TBG A
Dim Millimeters
Min Max
A 1.45 1.65
A1 0.60 0.70
A2 0.85 0.95
A3 0.25 —
b 0.65 0.85
D 37.50 BSC
D1 35. 56 REF
e 1.27 BSC
E 37.50 BSC
E1 35.56 REF
Notes:
1. Dimensions and Tolerancing per ASME
Y14.5M-1994.
2. Dimensions in millimeters.
3. Dimension b is measured at the
maximum solder ball diameter, parallel to
pri mary data A.
4. Primary data A and the seating plane are
defined by the spherical crowns of the
solder balls.
MPC8280 PowerQUI CC™ II Famil y Hardw are Sp ecif ications, Rev. 1.8
Freescale Semiconductor 75
Package Description
Figure 18 provides the mechanic al dimensions and bottom surface nomenclature of the 516 PBGA (VR/ZQ)
packages.
Figure 18. Mechanical Dimensions and Bottom Surface Nomenclature—516 PBGA
MPC8280 PowerQUI CC™ II Famil y Hardw are Sp ecif ications , Rev. 1.8
76 Freescale Semiconductor
Orderi ng Inf ormation
10 Ordering Information
Figure 19 provides an examp le of the Fr eesc ale part numbering nomenc lature for the MPC8280. In addition to the
processor freque ncy, the part numbering scheme also c onsists of a part modifier that indicates any enhancement(s)
in the par t from the origina l producti on desi gn. Each part number als o contai ns a revision code that refer s to the die
mask revision number and is specified in the part numbering scheme for identification purposes only. For more
information, contact your local Free scale sales office.
Figure 19. Freescale Part Number Key
11 Document Revision History
Table 25. Document Revision History
Revision Date Substantive Changes
1.8 07/2007 • Updated the entire document, adding information on the VV package.
1.7 12/2006 • Section 6, “AC Electri cal Charact eri stics,” removed deratings statem ent a nd clarified AC
timing descri pti ons.
1.6 05/2006 • Table 11: Added tex t to clarify that Dat a Bus Pari ty is not suppo rted at 66 Mhz.
• Table 11: Added text to clarify that Dat a Bus ECC is supported at 66 Mhz
• Table 11: Added not e to DP pins to show it is not supported at 66 MHz
• Table 12: Added note to support 1 ns hold time
1.5 03/2006 • Added Section 6.3, “JTAG Timings ”
1.4 11/2005 • In Se cti o n 6.2 , “SIU AC Character isti c s”, modif ied the note on CLKIN Jitter and Du ty Cycle.
• Modified Figure 17 to di splay all te xt.
1.3 01/2005 • Modification for correct display of asser tion level (“overbar”) for some signals
Product Code
Devic e Number
Package
Processor Frequency
Die Revision Level
MPC 82XX C ZU XXX
(CPU/CPM/Bus)
X
Tem perature Range
Blank = 0TA to 105Tj
C = (-40)TA– 105TjZU = 480 TBG A Lead Spheres
VR = 516 PBGA Lead-Free Spheres
ZQ = 516 PBGA Lead Spheres
VV = 480 TBGA Lead-Free Spheres
MPC8280 PowerQUI CC™ II Famil y Hardw are Sp ecif ications, Rev. 1.8
Freescale Semiconductor 77
Documen t Revi sion History
1.2 12/2004 • Section 2: re mo ved voltage tr acking note
• Table 3: Not e 2 upd ated regar ding VDD/ VCCSYN rel ations hip to VDDH d uring power -on r eset
• Table 5: Note 2 updated to refl ect VIH=2.5 for TCK, TRST, PORESET; request fo r ext ernal
pull up removed.
• Table 5: Note 4 added r egarding IIC comp ati bility
• Secti on 4.2: New informati on about jumper- to-case therm al resistance
• Secti on 4.3: New information about jumper- to-board thermal resis tance
• Secti on 4.4: New inf ormation about estimati on wit h simulation
• Secti on 4.6: Updated description of layout practices
• Secti on 6: Added sentence providing derating fa ctor
• Section 6.1, “CPM AC Charact eristics”: added Note: Ris e/Fall Time on CPM In put Pins
• Table 9: updated values f or following specs: sp42, sp43, sp42a
• Table 10: updated values for f oll owing specs: s p16b, s p18b, sp20, sp22
• Section 6.2: added spread sprectrum clocking note
• Table 11: combined specs sp11 and sp11a
• Secti ons 7.2, 7.3: unit of ns added to Tval notes
• Secti on 7, “Clock Configurati on Modes” : Updated all table footnotes r eflect updated CPU Fmin
of 150 MHz commercial temp devices, 175 MHz extended temp; CPM Fmin of 120 MHz.
Table 25. Document Revision History (continued)
Revision Date Substantive Changes
MPC8280 PowerQUI CC™ II Famil y Hardw are Sp ecif ications , Rev. 1.8
78 Freescale Semiconductor
Docume nt Revision History
1.0 2/2004 • Removal of “Advance Information” and “Preliminary.” The MPC8280 is fully qualified.
• Table 1: Ne w
• Figure 1: Modi fi cation to not e 2
• Section 1.1: Core frequency range is 166–450 MHz
• Addition of ZQ (516 PBGA with Lead spheres) package references
• Table 4: VDD and VCCSYN mod if ied to 1.45–1.60 V
• Note following Table 4: Modified
• Table 5: Addit ion of note 2 regardi ng TRST and PORESET (see V IH row of Table 5)
• Table 5: Changed IOL for 60x signals to 6.0 mA
• Table 5: Moved QREQ to VOL: IOL= 3.2 mA
• Table 5: Addit ion of criti cal interrupt (CINT) to IRQ5 for V OL (IOL = 6.0mA)
• Table 6: Addition of ΨJT and note 4
• Secti ons 4.1–4.5: New
• Table 7: Modified power values (+ 150mW to each)
• Table 8: Addit ion of note 2. Changed PCI impe dance to 27 Ω.
• Table 9: Changes to sp36b, SP38a, sp38b, sp37a, sp39a, sp40 and sp41
• Table 10: Changes to sp16a, sp18a, sp20 and sp21
• Section 6.2: Addition of Note: CLKIN Jitter and Duty Cycle
• Table 11: Changes to sp13 @ 66 and 83 MHz, sp14 @ 83 MHz
• Table 12: Change to sp30 (data bus signals). Changes to sp33b. Removal of note 2.
• Table 16 thr ough Table 20: Modi ficati on of not e 1 r egardi ng CPU and CPM Fm in. Modifi catio n
to corr esponding values in tables.
• Table 21: Addition of note 1 to TRST (AH3) and PORESET (AG6 )
• Table 21: Addition of RXD3 to CPM port pin PB14. Previously omitted.
• Table 21: Addition of critical interrupt (CI NT ) to B21 and U4. Previously omitted.
• Table 21: Addition of note 5 to ‘No connect’ (AA1, AG4)
• Addit ion of “Note: Temperature Re fl ow for the VR Package" on page 59
• Table 23: Addition of note 1 to TRST (F22) and PORESET (B25)
• Table 23: Addition of previ ously omitted signals t hat ar e mu lt iplexed with CPM port pins:
PA6—FCC2_UT_RXADDR3
PA7—FCC2_UT_TXADDR3
PA8—FCC2_UT_TXADDR4
PB14—RXD3
PC19—SPICLK
PC22—FCC1_UT_TXPRTY
PC28—FCC2_UT_RXADDR4
• Table 23: Remo val o f ser ial interface 1 (SI1) signals from por t pi ns (see n ote 2 in Figure 1):
PA[6–9], PB[8–17, 20–25] , PC[6– 7, 10–13], PD[4, 10–13, 16, 23–28]
• Table 23: Addition of critical interrupt (CI NT ) to AC 1 and B14. Previously omitted.
• Table 23: Addition of note 5 to ‘No connect’ (E17, C23)
Table 25. Document Revision History (continued)
Revision Date Substantive Changes
MPC8280 PowerQUI CC™ II Famil y Hardw are Sp ecif ications, Rev. 1.8
Freescale Semiconductor 79
Documen t Revi sion History
0.3 6/2003 • Removal of notes st ating “no local b us” on VR-package devi ces. The MPC8270VR and the
MPC8275VR hav e local bus suppor t.
• References to “G2 core ” changed to “G2_LE cor e.” Re fer to the G2 Core Reference Manual
(G2CORERM/D).
• Addition of VC CSYN to “Note” below Table 4, and to note 3 of Table 5
• Figure 2: New
• Table 5: Addit ion of note 1
• Table 6: Addition of θJB and θJC. Modifi ca ti o ns to ZU pa c k ag e valu e s .
• Table 7: Addit ion of various configur ations, Modi fi cation of va lues. Addition of note 3.
• Table 9: Addition of 66 MHZ and 100 MHz values. Addition of sp42a/sp43a.
• Table 10: Addition of 66 MHZ and 100 MHz val ues
• Table 12: sp30 values. sp33 b @100 MHz va lue. Removal of previous note 2. Modification of
current note 2.
• Figure 5, Figure 6, Figure 7, and Figure 8: Add it ion of notes
• Secti on 6.2: Addition of note on PCI timi ng
• Table 16, Table 17, Table 18, Table 19, Table 20: Addition of not e 1 concerning mini m um
operating frequencies
• Addit ion of statement before clock tabl es about selection of clock c onfigurat ion and input
frequency
• Table 21 and Table 23: Additi on of no te 1 to CPM pins
0.2 11/2002 Table 23, “VR Pinout”: Additio n of C18 to the Ground (GND) pin list (page 63)
0.1 — Initi a l p u blic release
Table 25. Document Revision History (continued)
Revision Date Substantive Changes
Document Number: MPC8280EC
Rev. 1.8
8/2007
Freescale™ and the Freescale logo are trademarks of Freescale Semiconductor, Inc.
The PowerPC name is a trademark of IBM Corp. and is used under license. All other
product or service names are the property of their respective owners.
© Freescale Semiconductor, Inc., 2004, 2007.
Information in this document is provided solely to enable system and software
implementers to use Freescale Semiconductor products. There are no express or
implied copyright licenses granted hereunder to design or fabricate any integrated
circuits or integrated circuits based on the information in this document.
Freescale Semiconductor reserves the right to make changes without further notice to
any products herein. Freescale Semiconductor makes no warranty, representation or
guarantee regarding the suitability of its products for any particular purpose, nor does
Freescale Semiconductor assume any liability arising out of the application or use of
any product or circuit, and specifically disclaims any and all liability, including without
limitation consequential or incidental damages. “Typical” parameters which may be
provided in Freescale Semiconductor data sheets and/or specifications can and do
vary in different applications and actual performance may vary over time. All operating
parameters, including “Typicals” must be validated for each customer application by
customer’s technical experts. Freescale Semiconductor does not convey any license
under its patent rights nor the rights of others. Freescale Semiconductor products are
not designed, intended, or authorized for use as components in systems intended for
surgical implant into the body, or other applications intended to support or sustain life,
or for any other application in which the failure of the Freescale Semiconductor product
could create a situation where personal injury or death may occur. Should Buyer
purch ase or use Freesc ale Semico nduc tor products for any suc h unintended or
unauthorized application, Buyer shall indemnify and hold Freescale Semiconductor
and its officers, employees, subsidiaries, affiliates, and distributors harmless against all
claims, costs, damages, and expenses, and reasonable attorney fees arising out of,
directly or indirectly, any claim of personal injury or death associated with such
unintended or unauthorized use, even if such claim alleges that Freescale
Semiconductor was negligent regarding the design or manufacture of the part.
How to Reach Us:
Home Page:
www.freescale.com
email:
support@freescale.com
USA/Europe or Locations Not Listed:
Freescale Semiconductor
Technical Information Center, CH370
1300 N. Alma School Road
Chandler, Arizona 85224
1-800-521-6274
480-768-2130
support@freescale.com
Europe, Middle East, and Africa:
Freescale Halbleiter Deutschland GmbH
Technical Information Center
Schatzbogen 7
81829 Mu enc he n, G er m a ny
+44 1296 380 45 6 ( Eng lish )
+46 8 52 2000 80 (English)
+49 89 9210 3 55 9 ( G erm an )
+33 1 69 35 48 48 (French)
support@freescale.com
Japan:
Fre es c ale Sem icon du c t or Ja pan Lt d.
Headquarters
ARCO Tower 15F
1-8-1, Shimo-Meguro, Meguro-ku
Tokyo 153-0064, Japan
0120 191014
+81 3 5437 91 25
support.japan@freescale.com
Asia/Pacific:
Freescale Semiconductor Hong Kong Ltd.
Technical Information Center
2 Dai King Street
Ta i Po Indus tri al Estate,
Tai Po, N.T., Hong Kong
+800 26 66 8080
support.asia@freescale.com
For Lite rat ur e Req ues ts Only:
Freescale Semiconductor
Literature Distribution Center
P.O . Box 5405
Denver, Color ado 80 217
1-800-441-2447
303-675-2140
Fax: 303-675-2150
LDCForFreescaleSemiconductor
@hibbertgroup.com