19-0097; Rev 1; 8/93 General Description The MAX741 is a highly versatile switch-mode power- supply (SMPS) controller IC that operates from an input supply as low as 2.7V, and typically starts up from 1.8V. The MAX741 can be pin-programmed into hundreds of different SMPS configurations. The internal blocks (refer- ence, error amplifier, etc.) are interconnected via analog switches so they can be reconfigured into different architectures by applying trilevel data (V+, VREF, GND) to certain logic input pins. This pin-programming feature lends tremendous application flexibility. For example, the output stage can drive N-channel or P-channel MOSFETs (or bipolar transistors) in single-ended, complementary, or push-pull modes. The error amplifier can accom- modate positive or negative feedback voltages. The out- put voltage can be adjusted with external resistors, or it can be set at any one of six preset values by switching in the appropriate laser-trimmed resistor-divider net- work. For mainstream applications (step-up, step-down, and in- verting), basic MAX741 circuits can be designed directly into the system with little effort using the tested circuit layouts found in the Application Circuits section. At the same time, the MAX741 provides the power-supply desig- ner the right inputs and controls to implement nearly any SMPS function. Applications Battery-Operated Equipment Distributed Power Systems isolated Off-Line Supplies On-Card DC-DC Converters MA AMAL/SVI Pin-Programmed, Low-Voltage, | Current-Mode SMPS Controller Features @ Pin-Programmable Architecture @ Operates on Supply Voltages from 2.7V Starts up from 1.8V NI wal, - @ Low Supply Current 1.6mA (MAX741U) (501A in Shutdown) # Bootstrap Input for Low-Voltage Applications @ Current-Mode PWM Control __ Cycle-by-Cycle Current Limiting @ Adjustable Undervoltage Lockout and Soft-Start @ Oscillator Synchronization Input/Output @ Shutdown-Control Input @ Low-Noise, Fixed-Frequency Operation Evaluation Kits Available @ PCB Layout Information Available __. Ordering Information TEMP. RANGE Ordering information continued on last page. * Dice are tested at Ta = +25C only. * Contact factory for availability and processing to MIL-STD-883. Block Diagram Pin Configuration SS FREQ SYNC Va 10 i . Net fd SLOPE [4 20} FREQ VREE sync [2 Hig] ve CONTROL vset [3 | {1a) OUTA GND UVLO PN [4 | AAAXLAA [17] OUT EAIN QUTA Vout [5] MAX747~ fitg] ORV gute ORV- ver [a 3] s s Vout | RESISTOR DUTY uo [7] iq] cB AND MOK Fol ss [8 fg] Pou vse, LU $8 eno [9 ia] bury =| VOLTAGE- SA o ee PN | SHERI CURRENT-SENSE End {iol 11 EAN 0 AMPLIFIER DIP/SO SLOPE MA AXAAA Maxim Integrated Products 4-119 Call toll free 1 -800-998-8800 for free samples or literature. PART PIN-PACKAGE MAX741UCPP 0C to +70C 20 Plastic DIP MAX741UCAP OC to +70C 20 SSOP MAX741UC/D OC to +70C Dice* MAX741UEPP -40C to +85C 20 Plastic DIP MAX741UEAP -40C to +85C 20 SSOP z MAX741UMJP -55C to +125C 20 CERDIP** ,MAX741 Pin-Programmed, Low-Voltage, ABSOLUTE MAXIMUM RATINGS Supply Voltage V+ toGND ....... eee eee eae +17V, -0.3V Oscillator Output Voltage (SYNC) ....... -0.3V to (V+ + 0.3V) MOSFET Driver Supply Voltage (DRV- toV+) ..... +0.3V, -17V Feedback Voltage (VoUT to GND)... 00... eee +50V Auxiliary Input Voltages (SLOPE, SS, VSEL, P/Z/N, EAIN, DUTY, POL, CSA, CSB, FREQ to GND) .... 6622. eee eee -0.3V to (V+ + 0.3V) Peak Output Current (louTA or lOUTB) .. 0... eee 1.0A Reference Current (IVREF) 0.0... 0... c cece eee 2.5mA Current-Mode SMPS Controller Continuous Power Dissipation (Ta = +70C) Plastic DIP (derate 11.11mMW/C above +70C)...... 889mW SSOP (derate 8.00mW/C above +70C)........... 640mWw CERDIP (derate 11.11mW/C above +70C) ........ 8s8omw Operating Temperature Ranges: MAX741_C_o eee OC to +70C MAX741. Fo. ete -40C to +85C MAX741_MUP oo. eee ce eee ees -58C to +125C Storage Temperature Range .............. -65C to + 160C Lead Temperature (soldering, 10sec) .............. +300C Stresses beyond those listed under Absolute Maximum Ratings" may cause permanent damage to the device. These are stress ratings only, and functional operation of the device at these or any other conditions beyond those indicated in the operational sections of the specifications is not implied. Exposure to absolute maximum rating conditions for extended periods may affect device reliability. ELECTRICAL CHARACTERISTICS (V+ = 5V, Ta = TMIN fo Tmax, unless ofherwise noted.) PARAMETER CONDITIONS MIN TYP MAX UNITS Supply-Voltage Range 2.7 15.5 Vv Stari-Up Supply Voltage TA = +25C, UVLO = V+ 1.8 Vv Shutdown-Mode Supply Current | FREQ = OV, Ta = +25C 50 150 pA Reference Voltage 1.17 1.23 1.29 Vv Reference-Voltage Line * Regulation 9 V+ = 2.7V to 15.5V, TA = +25C 0.5 +4 mv/V Reguanon age Load | ILOAD = OMA to 300uA, Ta = +25C, MAX741N only 1.4 6 mv FREQ = V+, Ta = +285C 130 160 190 Oscillator Frequency kHz FREQ = VREF, Ta = +25C 150 External Clock Frequency . Synchronization Range (at SYNC) 40-200 kHz SYNC Input Capacitance 10 pF 0 level, used as clock input 0.2 SYNC Trip Threshold Vv "1" level, used as clock input V+ -0.2 High Level V+ -0.3 (PON REG DUTY) | Middle Level VREF03 v Low Level 0.3 SYNC Output Low Voltage loL = 252A, used as clock output 0.2 Vv SYNC Output High Voltage IOH = 25pA, used as clock output 48 VIH = V+, used as clock input 1.0 SYNC Input Current : - mA Vit = OV, used as clock input -1,0 4-120 MAXILANPin-Programmed, Low-Voltage, Current-Mode SMPS Controller ELECTRICAL CHARACTERISTICS (continued) (V+ = 5V, TA = TMIN to TMax, unless ofherwise noted.) 2 oes a Q = 4 noe rot = PARAMETER CONDITIONS MIN TYP MAX UNITS e Error-Amplifier Input Bias Current | P/Z/N=VREF ~~ a yo 0.005 10 pA J Error-Amplifier Open-Loop Gain | EAO = 2V to 3V oo, - ~ 2000 VN a OUTA or OUTB, Ta = +25C, lot = 50mA . 0.65 0,95 Output Voltage Low see at Vv lol = 50mA, DRV- = -10V OS 985 -9.50 _ | OUTA or OUTB, Ta = +25C, lon = -50mA ~ - 4.10 4,35 Output Voltage High Cn He Vv - IOH = -50mA, DRV- = 10V_ ; _ _ 4,50 4.70 . Output Rise or FaliTime ==_ | OUTA or OUTB, Ta = +25C, CLoan = 11 nF (Note 1) 50 100 ns UVLO Threshold Adjustable mode, measured at UVLO (Note } Yack BX 048x | oy UVLO Start-Up Threshold __ | UVLO = ov ; ; 3.0 4.0 4.4 V ELECTRICAL CHARACTERISTICS~MAX741U (Step-Up Circuit of Figure 1a, V+ = 5V, LOAD = OmA, Ta = TMIN to TMAX, uniess otherwise noted.) 4 . oo PARAMETER __ ___CONDITIONS MIN TYP MAX | UNITS Fixed modes, referred to Vout, V+ = 3.3V, VSEL = V+ _, (Note 2) , fo SUSIE | 480 5.00.20 4 Output Voltage Initial Accuracy |VSEL=VREF,TA=+25C | 11:52 12.00. 12.48 Vv VSEL = OV, TA = +25C _ _| 1440 15,00 15.60 - _______ | Adjustable mode, referred to error-amplifier input _. 1.18 1.23 1.28 _ Supply Current _- | VSEL = V+ = 3.3V (Note 3) / oo a 1.6 3.5 mA ELECTRICAL CHARACTERISTICS MAX741 N _ (Inverting Circuit of Figure 1b, V+ = 5V, 1LOAD = OmA, Ta = TMIN to TMAX, unless otherwise noted.) a cos PARAMETER _ _. ; CONDITIONS _ eee. MIN TYP MAX UNITS : Fixed modes, referred to Vout. VSEL=V+ (Note2) | 5.20 -5.00 = -4.80 . VSEL = VREF, Ta = +25" : 12.48 -12, 11.52 Output Voltage Initial Accuracy V TAs 425C SA Set 48 2.00 11.52, Vv VSEL = OV, Ta = +25C i, | 718.60 15.00 -14.40. oo Adjustable mode, R1 = 50kQ, R2 = 50kQ. . _ - -1.29 -1.23 -1.17 Supply Current | VSEL = V+ (Note 3)_ ae 2.2 4.0 mA MAAXLAA ; a . _ - 4-t2tPin-Programmed, Low-Voltage, Current-Mode SMPS Controller ELECTRICAL CHARACTERISTICS MAX741D (Step-Down Circuit of Figure 1c, V+ = 12V, ILOAD = OmA, Ta = TMIN to TMAX, unless otherwise noted.) MAX741 PARAMETER CONDITIONS MIN TYP MAX UNITS 7 Fixed modes, referred to VouT, VSEL = V+ (Note 2) 480 5.00 5.20 Output Voltage Initial Accuracy Vv Adjustable mode, referred to error-amplifier input 1.18 1,23 1.28 Supply Current VSEL = V+ (Note 3) 28 4,25 mA Note 1: Guaranteed, but not 100% tested. _ Note 2: Output Voltage Initial Accuracy tests include e the effects of the error- amplifier input offset voltage. Note 3: Total supply current under actual operating conditions, including currents drawn by components. Typical Operating Characteristics (Ta = +25C, unless otherwise noted.) MAX741U STEP-UP MAX741U STEP-UP NO-LOAD SUPPLY CURRENT vs. MAX741U STEP-UP LOAD CURRENT vs. INPUT VOLTAGE CONTINUOUS-CONDUCTION REGION SUPPLY VOLTAGE 50 = 20 25 2 A5V Vout = +5V p Vout = +5 As = CIRCIUT OF FIGURE 7 f CIRCUIT OF FIGURE 7 _ = OF FIGURE 7 15 ; 20pm pn o ; z z ao s = = 15 <|_\ S ss 2 1.9) CONTINUQUS CONDUCT! = NO LOAD DURING gS s STARTUP z 2 3g 10 oo Q 30 s & 4 a 3 os 05 08 J, OADED DURING = 3 BUIRST-MODE REGION 2" / nT 20 im a 25 80~CS a0 45 25 30 35 40 45 50 25. 480285) AOASSCBO SUPPLY VOLTAGE (V) SUPPLY VOLTAGE (V) SUPPLY VOLTAGE (V) _MAXTA1U _ MAXTAIU SWITCHING WAVEFORMS SWITCHING WAVEFORMS - CONTINUOUS-CONDUCTION BURST-MODE A B c A= MOSFET DRAIN YOLTAGE (5V/ yy B~ OUTPUT VOLTAGE R ria a 50mV/div) C = INDUCTOR CURRENT (1A/div) CIRCUIT OF FIGURE 7 B= GE RIPPLE C= INDUCTOR CURRENT CAI CIRCUIT OF FIGURE 7 As MOsteT PRAY YOLTAGE es iM visiv) imV/div 4-122 - MAXIMAPin-Programmed, Low-Voltage, Current-Mode SMPS Controller Typical Operating Characteristics (continued) = MAX741U MAX741 LOAD-TRANSIENT RESPONSE LINE TRANSIENT RESPONSE . , a mal, B B A= 1ALOAD (HIGH) /200mA LOAD (Low . A= Vive 4V (HIGH (w= 3 04 B= OUTPUT VOLTAGE (AC: 100mV/div) B= OUTPUT VOLTAGE (AC: {00mV/div) C= INDUCTOR CURRENT (1A/div) C= INDUCTOR CURRENT (1A/div) CIRCUIT OF FIGURE 7 CIRCUIT OF FIGURE 7 MAX741U STEP-UP MAX741D STEP-DOWN MAX741D STEP-DOWN EFFICIENCY vs. LOAD-TRANSIENT RESPOSNE LOAD-TRANSIENT RESPOSNE LOAD CURRENT (Vour = 3.3V) (Vour = 5V) 95 t I i ] Vour=+5V CIRCUIT OF FIGURE 7 Vout 90 Vout 20mV/div ee ae 20mWeiv z iF > PN V Vin = 7V 5 YON I~ CIRCUIT OF FIGURE 9 85 i - eee wet . s \ \ es f A Vis aby . WoaD 80 F-4VIN = 4. : 3 500mA/div Vin= 3.3] . soOmAVdiV VIN = 2.7--] Vin =5V an OA OA 5 CIRCIUT OF FIGURE 9 ; . Co - 0 02 04 06 08 10 12 14 16 = LOAD CURRENT (A) 100us/div 2001s/div MAX741D STEP-DOWN MAX741D STEP-DOWN MAX741D STEP-DOWN EFFICIENCY vs, OUTPUT CURRENT EFFICIENCY vs. OUTPUT CURRENT LINE-TRANSIENT RESPOSNE (Vour = 5V) (Vour = 3.3V} . De 100 95 . i . : Vin OV 90 ay 20 m Vin = _ 1 _ i sonviv & 60 & . = -- B59 2 Y= +7M ae Ss Vout = +5V S = a 5 0 CIRGIUT OF FIGURE 9 & 30 ash aN 20 men Vour = +3.3V OA " CIRCUIT OF FIGURE 9 av z fee i 50 . 0 02 04 06 08 1012 14 16 18 0 02 04 06 08 10 12 14 16 18 200us/div OUTPUT CURRENT (A) OUTPUT CURRENT (A) MA AXLA - pe ee kB ee : _ -4-123MAX741 4 Pin-Programmed, Low-Voltage, Current-Mode SMPS Controller Typical Operating Characteristics (continued) MAX741D STEP-DOWN MAX741N INVERTING NO-LOAD SUPPLY CURRENT vs. MAX741N INVERTING NO-LOAD SUPPLY CURRENT vs. SUPPLY VOLTAGE LOAD CURRENT vs. SUPPLY VOLTAGE SUPPLY VOLTAGE 18 40 rt ot Tf TT TT Tt =45 =-! Vout = -5V = OF CHRUIUT OF FIGURE 11 = CIRCUIT OF FIGURE 11 1.6 = 35 ff + _ i & i 2 ii) & & a] > 2 iA a > 3.0 \ E 3 By = B 2 Wa B NI 2 = ff 3S NI 12 = 25 hl 2 7 2 a sold 20 7 8 9 10 11 12 13 14 15 16 17 45 65 85 105 125 145 45 65 85 105 125 145 SUPPLY VOLTAGE (V) SUPPLY VOLTAGE (V} SUPPLY VOLTAGE (V) ene BOCTSTRAPPED MOSFET DRIVE (DRV- = Vout) NON-BOOTSTRAPPED MOSFET DRIVE (DRV- = GND) MAX741NINVERTING EFFICIENCY vs. LOAD CURRENT 90 = Vout=-5V CIRCUIT OF FIGURE 11 85 L-Vin= +10V | Cans ay A VW = 48V >: | : 7 N NA ad N 70 0 62 04 06 08 10 12 14 16 LOAD CURRENT (A) 4-124 MAXIPin-Programmed, Low-Voltage, Current-Mode SMPS Controller Pin Description NAME L PIN i ; - ____ FUNCTION _ a . _ 1 |SLOpE | Sets slope compensation for AC stability, Normally a 50kQ to 1MQ resistor connected to ground. Required for con- tinuous-conduction mode operation. _ oe a SYNC output at the oscillator frequency. Also functions as a clock input when driven externally. Capacitive loads 2 | SYNC | reduce oscillator frequency up to 25%. When_using an external clock, the clock's high time corresponds to power switch-offtime. | . ; oe ae . | Le, Voliage Select (VSEL) and P/Z/N are decoded to determine the output voltage. See Table 2 under Output Voltage 3 VSEL Selection. - oo ee o. . _ ; See VSEL (pin 3). 0 P ny + __= Positive Output (P), 4 | PIZIN | VREF = Adjustable Mode (2) GND_ = Negative Output (N) _ cee ee ee . VouT | Output Voltage connection to internal resistor dividers. Connect to output or leave open in adjustable mode. VREF | Voltage-Reference Output that can source 300uA for external loads. Bypass with 1pF minimum. . Undervoltage Lock-Out disables IC when V+ is less than the UVLO threshold. See Undervoltage Lockout section. 7 | uUvLo V+ = No Lockout - . . - 0.47V+ to 0.075V+ = adjustable threshold GND = 4V threshold ; oe oe . a oo . Soft-Start and current-limit adjust. A DC voltage applied here sets the maximum peak switch-current limit. See Soft- 8 ss Start and Current Limiting section. An RC network reduces surge currents on start-up. Connect a 150kQ resistor from VREF to SS and _0.1,1F from SS to GND for a 15ms soft-start time. Always connect a resistor (50kQ. to 1MQ) between VREFandSS. ee eo we 9 GND | Ground ; ; oo - e 10 | EAO | Error-Amplifier Output ee oe 11} EAIN | Error-Amplifier Input _ cer - Duty Cycle Adjust when DUTY = V+: push-pull mode, 50% max duty cycle - . 12 | DUTY | DUTY = VREF: Complementary, 50% max duty cycle . a DUTY = GND and FREQ = V+: complementary, 85% max duty cycle DUTY = GND and FREQ = VREF: complementary mode, 95% max duty cycle ; . _. oe Polarity. Selects current-sense amplifier output polarity and controls OUTA and OUTB polarity when in push-pull mode. ao nn - _- ae oo 13 POL V+ _= N-Channel (CS inputs sense around ave GND_ = P-Channel (CS inputs sense around V+) | eee wee * : Current-Sense Amp "B" input, connects to signal side of current-sense resistor. Signal passes through a ist-order 14 | CSB IT fitter. oo. ne _ : 15 cga_ | Current-sense amp A" input. Connect fo V+ in buck and inverting circuits, Connect to GND in step-up circuits. CSA should be bypassed with 0. 1p F located close to CSA and GND when in the buck or inverting power-supply modes. Negative Drive Bootstrap Supply Voltage Input accepts a DC bias voltage as the negative supply rail for the drivers 16 | DRV- | at OUTA and OUTB, useful when driving P-channel MOSFETs from low supply voltages. Observe Absolute Maximum Ratings carefully. _ ee . : oe 47 | OUTB | Output B MOSFET Driver drives P-Channel or PNP transistors in complementary modes. See Table 1. When V+ > 14V, use 5.69 in series between OUTB and gate of power FET. wo 18 | ouTA | Output A MOSFET Driver drives N-channel or NPN transistors in complementary modes. When V+ > 14V, use 5.6Q in series between OUTA and gate of power FET. See Table 1. , a . _ 19 V+ _| Positive Supply Voltage +2.7V to +15.5V. Bypass with at least 0.1pF close to V+ and GND pins of IC. Frequency/Shutdown Control sets oscillator frequency or forces a non-operating shutdown mode. 20 | FREQ V+ = 145kHz with 85% duty cycle . LAV = 140KHz with 95% duty cycle (see 3-level input pins section) GND = Shutdown Mode - cette MAXIMA a a - 4-125MAX741 Pin-Programmed, Low-Voltage, Detailed Description The MAX741 is a monolithic, CMOS, current-mode PWM controller that can be used in a variety of configurations with one or more external power switching transistors. The current-mode PWM control scheme provides tight output-voltage regulation, excellent load- and line-tran- sient response, and low noise. An external current-sens- ing resistor provides cycle-by-cycle current limiting, and output current limiting in applications where there is no DC path from input to output. The MAX741 is optimized for step-up (MAX741U), step-down (MAX741D), or invert- ing (MAX741N) configurations. The basic step-up, step-down, and inverting applications, presented in detail in the Application Circuits section, use the standard topologies shown in Figure 1. Table 1 describes the pin programming necessary for various modes, including Figure 1's three basic circuits. The Table 1. Output-Stage Programming _Current-Mode SMPS Controller MAX741 can also accomodate specialized applications needing complementary or push/pull power switches. Table 1 describes the pin programming used to obtain complementary and push/pull drive, and Figure 2 shows the resulting drive waveforms at OUTA and OUTB. Operating Principle The controller consists of two feedback loops: an inner (current) loop that monitors the switch current via the current-sense resistor and amplifier, and an outer (volt- age) loop that monitors the output voltage via the error amplifier (Figure 1). The inner loop performs cycle-by- cycle current limiting, truncating the on-time of the power transistor when the switch current reaches a threshold predetermined by the outer loop. For example, a sagging output voltage produces an error signal that raises the threshold, allowing the circuit to store and transfer more energy during each cycle. PROGRAM MODES PROGRAM PINS DUTY POL FREQ OUTA OUTB MODE Axi V+ V+ V+ N . N OUTA, OUTB push/pull 50% V+ V+ VREF N N OQUTA, OUTB push/pull 50% V+ GND V+ P P OUTA, OUTB push/pull 50% _ V+ GND VREF P P OUTA, OUTB push/pull 50% V+ V+ GND GND GND Shut down using N-channel push/pull V+ GND GND V+ V+ Shut down using P-channel push/pull VREF V+ V+ N OUTA, QUTB complementary 50% VREF V+ VREF OUTA, OUTB complementary 50% VREF GND V+ OUTA, OUTB complementary 50% VREF GND VREF OUTA, OUTB complementary 50% VREF X GND GND V+ Shut down (non-push/pull mode) GND : V+ V+ N OUTA, OUTB complementary 85% GND V+ VREF OUTA, OUTB complementary 95% GND | GND V+ N OUTA, OUTB complementary 85% - GND GND VREF OUTA, OUTB complementary 95% GND X GND GND V+ Shut down (non-push/pull mode) N = Drives N-Channel FETs (On = V+ P = Drives P-Channel FETs (On = GND) X = Don't Care 4-126 MAXLAAPin-Programmed, Low-Voltage, Current-Mode SMPS Controller N = RSENSE CSA Vout Ja. STEP-UP CONFIGURATION (MAX741U) V. AVREF 4 R2 -VouT Ri Rl Vour="p9 (REF) ib. INVERTING CONFIGURATION (MAX741N) = te. STEP-DOWN CONFIGURATION (MAX741D) Figure 1. Basic Configurations Continuous-/Discontinuous- Conduction Modes In continuous-conduction mode (CCM), the inductor current never decays to zero. In discontinuous-con- duction mode (DCM or burst-mode), the inductor cur- rent slope is steep enough so it decays to zero before the end of the transistor off-time. The MAX741 operates in either CCM or DCM by the selection of higher or lower MNAXLAN ON ON QUTA ouTB COMPLEMENTARY MODE (POL =V+, DUTY = GND) OUTA om | i. Figure 2. Push-Pull and Complementary Waveforms PUSH-PULL MODE (POL = V+, DUTY = V+) inductor values, respectively. CCM allows the MAX741 to deliver maximum load currents, and is normally less noisy than DCM. However, DCM does not provide a continuous feedback path through the inductor, and hence is easier to stabilize; it does not require slope compensation, and allows for a smaller output capacitor. Output-Voltage Selection The output voltage can be adjusted by an external resis- tor-divider network, or it can be set to a fixed level (+5V, +12V, +15V, -5V, -12V or -15V) by pin programming the MAX741 as shown in Table 2. When using an external resistor divider, the output voltage is determined by the ratio of the resistors in the divider and the internal +1.23V reference. See the Application Circuits section for more information on output-voltage adjustment. Table 2. Output Voltage _ EAIN VSEL PIZIN OUTPUT IMPEDANCE V+ V+ BV 16.5k V+ VREF Adj. Positive >50M HiZ V4 GND -BV 17.5k VREF V+ 12V 5,5k VREF VREF Prohibited NA VREF GND ~12 16k GND V+ 15V 5k GND VREF Adj. Negative >50M HiZ GND GND -15V 10k 4-127 LDZXVIN KNMAX741 Pin-Programmed, Low-Voltage, Current-Mode SMPS Controller 3-Level Input Pins Pins P/Z/N , FREQ, and DUTY have three levels: Low (GND to 0.3V), middle (VREF +0.3V), and high (V+ - 0.3V to V+). Obtain middle level operation by typing the appropriate 3-level input to VREF (Figure 8), except pin 20 (FREQ), which should be held at 1.4V. This 1.4V can be generated with two forward-biased diodes tied to ground and pulled up with 100kQ to V+. This resis- tance value is suitable for V+ voltages in the +5V to +15V range. For operation with V+ as low as 2.7V, use a 60kQ resistor. Slope Compensation Slope compensation is used to eliminate subharmonic ascillation in the power output stage. Compensation is controlled by resistor RSLOPE, connected from SLOPE to ground. Current-mode regulators tend to oscillate in a local loop in the output stage, because the inductor current waveform can bounce between zero and the maximum current-limit threshold. This instability is cor- rected. by a slope compensation scheme that adds a ramp signal to the current-sense amplifier output. Slope compensation js required when the switch duty cycle exceeds 50%. When this is.the case, varying degrees of slope compensation eliminate inner-loop in- stability. Excessive slope compensation makes the loop behave like a traditional voltage-mode (triangle-wave) PWM, where the AC stability can also suffer due to the extra pole in the loop response. Slope compensation is not required when operating in DCM. Inner-loop instability manifests itself as "staircasing of the inductor current, where the current waveform ramps up in steps until it hits the maximum current-limit threshold (set by the voltage at SS) and then declines. This effect is also seen in the output-voltage ripple waveform where the noise has a large subharmonic component, or at the switching nodes where the duty cycle is seen to be. successively increasing over a period of several.cycles. This instability differs distinct- ly from instability in the outer voltage regulation feed- back loop, which has a more random character and must be debugged separately. idea! slope compensation is achieved by adding to the rising inductor current-sense signal a ramp whose value is equal to the slope of the declining inductor current. The slope (m) of the declining inductor current is deter- mined frorn the output voltage and the inductance value: m= VouT/L for step-down converters and inverters; or m= (VouT- VINYL for step-up circuits. The voltage slope (SVS) at the current-sense amplifier's output is equal to SVS = (m)(RSENSE), where RSENSE is the current-sense resistor value. The slope compensation voltage (CVS) is generated by a current source (controlled by a resistor con- nected to the SLOPE pin) charging an internal 10pF capacitor, as shown in Figure 3. This compensation voltage is summed with the signal from the current- sense amplifier, and, for ideal compensation, must be equal to the declining inductor current signal (SVS) calculated above. Hence the slope compen- sation voltage is given by SVS = CVS = VREF/[(20)(10pF)(RSLOPE)]. where the factor of 20 arises from the current source gain (Figure 3). Rearranged, these equations give the formula for the slope resistor (RSLOPE) to be connected to the SLOPE pin: RSLOPE = VREF/{(20)(10pF){m)(RSENSE)]. POLARITY DEPENDS ON POL PIN CONNECTION. CSB CSA TO PWM COMPARATOR 10pF -_ VREF |= Oy (RSLOPE) = Figure 3. Current Amplifier and Slope Compensation Model MAAXLAN 4-128Pin-Programmed, Low-Voltage, Current-Mode SMPS Controller Slope Compensation Example The following slope compensation calculation is for a +5V to +15V step-up converter using a 30uH inductor and a 0.1Q sense resistor. The ideal compensation slope is equal to the declining inductor current slope, which is given by m= (VIN - VouTyL = (15V - 5VV/30uH = 0.33A/ps. The voltage slope (SVS) at the current-sense amplifiers output is equal to SVS = (m)(RSENSE) = 0.33A/us(0.12 ) = 0.033V/us. The slope resistor (RSLOPE) is thus _ RSLOPE = VREF/[(20)(10pF)(m)(RSENSE)] = 1.23V/[(20)(10pF)(0.33A/us)(0.19 )] = 186kQ . AC Compensation The stability of the outer voltage feedback loop can be evaluated using load-iransient response tests. Sig- nificant overshoot or ringing after a step from zero to full load indicates potential stability problems. The outer loop can be compensated with an RC network around the error amplifier. Typicaliy, a pole-zero cancellation scheme is used to eliminate excess phase shift due to the zero caused by the output filter capacitors equivalent series resistance (ESR). The following example shows the compensation calculations fora 1000pF, 0.05Q ESR output capacitor (CF). The calculations are the same regardless of the circuit type (step-up, step-down, or inverting). oo The zero caused by the output capacitors ESR occurs at a frequency (fz) given by : fz = 1/(2)(m)(ESR)(CF)] = 1/[(6.284)(0.050)(1000uF)] = 3.18kHz A cancellation pole is required at 3.18kHz. This compen- sation poles frequency (fp) is given by fp = 1/{(2)(n)(REAIN)(C4)] where REAIN is the impedance of the error-amplifier input pin (EAIN), and C4 is the value of the compensation capacitor in Figures 7 and 9. From Table 2, with VSEL and P/Z/N connected to V+, EAIN has a nominal im- pedance of 16.5kQ, so CC = 1/{(2)(n)(REAIN)(fp)] = 1/{(2)(3.142)(16.5kQ)(3. 18kKHz)] = 3nF Additional outer-loop compensation may be required in step-up circuits. Capacitor C5 in Figure 7 provides the extra compensation needed in this application. The actual compensation capacitor values required depends on the printed circuit layout and the capacitor type used. These values may, therefore, vary significantly from those calculated. Prototyping is essential. Current-Sense Amplifier The current-sense amplifier (Figure 4) employs a switched- capacitor design to achieve a common-mode voltage range that exceeds both supply rails by 0.3V. The current-sense amplifier has a gain of 10 with a 0.6V +200mV output offset. For clarity, Figure 4s block diagram of the soft-start and current-limit sections omits the slope compensation circuit and summing amplifier shown in Figure 3. Soft-Start (SS) and Current Limiting The switch transistor's maximum peak current limit is determined by the voltage on SS. An external RC network on SS results in a gradual increase in peak current on power-up, minimizing the possibility of overloading the source. a The SS voltage is amplified by a factor of 3.5, and this voltage clamps the maximum swing of the error amplifier (a transconductance amplifier) as it is presented to the PWM comparator. For example: with SS connected to VREF (1.23V) and Rsense = 0.1Q, the highest peak current is: , : _ 3.5 (Vs) -0.6V__ 3.5 (1.23V) - 0.6V ~ (10) (RSENSE) _ (10) (0.19) where Vs is the SS pin voltage. Under normal load, a good value for the peak voltage differential across the current-sense amplifier inputs is 200mvV or so, achieved by adjusting the sense-resistor value. Setting the SS current limit at 1.5 to 2 times that (8V to 4V at the error-amplifier output) adds margin to handle worst-case loads. IPK =3.7A, Ensure that the error amplifiers maximum swing allows enough peak current to meet the average load current. Peak transistor current in a typical switch-mode power supply is several times greater than the DC load cur- rent. The exact value depends on configuration, input/output voltage ratio, frequency, and inductor value. 4-129 MA AXLAN LPZLXVIN NMAX741 Pin-Programmed, Low-Voltage, Current-Mode SMPS Controller CSA RSENSE CSB |Pk 4 V4 CURRENT-SENSE AMPLIFIER AV = 10 POLARITY DEPENDS ON POL PIN CONNECTION. 74 UVLO Ve PWM FAO COMPARATOR o| VREF > a oH = x - T0 EAIN Ie FiF ) TAL = ERROR AMPLIFIER AV = 2000 SOFT-START 20k 2 2.58 / \ AMPLIFIER It-WWw 35.88 VOLTAGE) - 0.6V Ss Fre) RENse; Dam MAX741_ Re 0.523 GND Figure 4. Soft-Start and Current Limit Undervoltage Lockout Switching with low gate-drive to the power MOSFET results in low efficiency and can cause excessive heating of the switching transistor. Undervoltage lockout inhibits switching activity while the supply voltage is low. When lockout is triggered, the output power FETs are disabled and the SS pin is internally pulled to GND. There are three undervoltage lockout modes: disabled, fixed at +4V, and adjustable. Connect UVLO to V+ to disable the undervoltage lockout. Connect UVLO to GND to trigger lockout at 4V or less. Undervoltage is adjus- table when the voltage applied to the UVLO pin is be- tween (0.075)(V+) and (0.47)(V+). In adjustable mode, the UVLO pin lockout threshold is nominally 0.523V. Connect a resistor-divider network from V+ to UVLO to GND as shown in Figure 5. The nominal undervoltage lockout voltage is Vix (0.523) (RA + RB) Re Values for Ra and Rp can range from 10kQ to 100k, since UVLO is a high-impedance input with leakage currents under 1pA. For example, connect an 82kQ resistor from V+ to UVLO (Ra), and a 10kQ resistor from UVLO to GND (Rp) to achieve a nominal 4.81V lockout-voltage threshold. These calculations define the undervoltage-lockout threshold when V+ is rising frorn a low value. Hysteresis 4-130 Figure &, Undervoltage Lockout Comparator (Adjustable Mode) built into the MAX741 provides a UVLO threshold voltage typically 6% lower when V+ is falling from above the undervoltage-lockout threshold. SYNC Input/Output Clock The SYNC output typically drives up to five CMOS gates. Capacitive loading of this pin lowers the internal oscillator frequency. When driven by an external gate, SYNC be- comes an input. The clock source must have 1mA source and sink capability. Standard +5V CMOS logic can easily drive this pin, as long as the logic supply voltage does not exceed V+. If V+ drops below +5V, buffer the SYNC input signal with a CMOS logic gate with its supply rails connected to.GND and V+. Externally Synchronizing the Switching Frequency To synchronize the switching frequency to an external clock, apply the clock to the SYNC pin. This signals duty cycle conirols the maximum duty cycle of OUTA or OUTB (the high portion of the clock controls the minimum off- time). A 20% duty cycle clock signal applied at SYNC, for example, forces a minimum of 20% off-time for the MOSFET driven by OUTA or OUTB. Therefore, for most applications, it is appropriate to clock SYNC with a duty cycle of approximately 10% (a series of short pulses at the desired switching frequency) allowing OUTA and OUTB to achieve duty cycles of up to 90%. MA AXIAAPin-Programmed, Low-Voltage, Current-Mode SMPS Controller Application Circuits Low-Voltage Step-Up Converter Figure 7 shows a 3V to 5V step-up (or boost) converter capable of delivering 1A. Bootstrapped operation provides efficiencies between 80% and 90%, depending on the load current and the input voltage. At light loads, the MAX741U enters discontinuous-conduction burst- mode" operation, in which inductor currents may stair- case before discharging into the output capacitor. The resulting output voltage ripple may be higher than CCM noise (up to 100mvV), and subharmonics of the fundamen- tal switching frequency will be present. With heavier loads, the MAX741U enters CCM, giving lower noise performance, see Typical Operating Characteristics. This circuit's output can be turned on and off with an open-drain logic signal applied to the ON/OFF control. In the off state, the output remains connected to the input via inductor L1 and diode D1. The ON/OFF control should be taken below 0.5V to turn the circuit off, or left open to turn it on. Do not apply a voltage to the ON/OFF control that exceeds the circuit's output voltage. INPUT VIN = 2.7V TO 5V { As Ci MALIA __ MAX741U ON/OFF e q SLOPE FREQ ] SYNC Ve pt VSEL OUTA + P/Z/N ouTB >1 VouT DRV- oe te * VAEF CSA 10nF TP Hae UVLO CSB - 88 POL once L C4 } LL aon GND DUTY TL. > 600pF EAO EAIN |= | 65 7 | TT 470pF Figure 6. MAX741U EV Kit Schematic. This step-up converter supplies +5V at 1A from a +3V input. ON/OFF e~,\A# ~ INPUT No . Rg : Re VIN = 6V 70 15.5V tk 100k inst RG ig 3 2 cit 2 9 ned 100k Ve VSEL-FREO four = LC 120pr ; 4| oa osag ts - = = Ri bse tt mw SLOPE css {4 . o + . BV 34 2 OF TN NPARALLES (Qu ~ MAAXIAA ai 5V@ 1.54: CTX20-4 COILTRONICS (20H) 6 MAX741D { 819998 | , Jf te VREF OuTB | 2 OUPLT RS 10ueaE Mo wor weet oc Po 8V@15A 103A 150k Tr 1 ~ T aa0uF 330uF $8 EAIN osu ca : Lo 2 wey pUTY Vout 3 R8 i 2 16.9k UVLO. GND CDV a7 7 aT 16] 10k = D1: NSQ03A03, SCHOTTKY Figure 7, MAX741D EV Kit Schematic. +6V to +15.5V Inout Step-Down Converter Supplies +5V at 1.5A or 3A. 4-131 MAAXKLAAN LPZLXVIN| Pin-Programmed, Low-Voltage, Current-Mode SMPS Controller ___Ordering Information (continued) = N PART __TEMP.RANGE _PIN-PACKAGE MAX741DCPP___O'C io +70C 20 Plastic DIP_ * MAX741DCAP O'Ct10+70C 20 SSOP MAX741DC/IDOC to +70C ice = MAX741DEPP -40C to +85C 20 Plastic DIP MAX741DEAP 40C t0+85C 20SSOP_ ; MAX741DMJP_-55C to +125C 20 CERDIP ; MAX741NCPP OC 10+70C_~=20 Plastic DIP MAX74iNCAPO'C lo 70C == 20. SSOP MAX741NC/D OCto+70'C Dice 8 MAX741NEPP__-40C to+85C__=20 Plastic DIP_ MAX741NEAP _-40C to +85C 20 SSOP MAX74iNMJP -55C to +125C 20 CERDIP** MAX741D EVKIT-SO_ OCto+70C __Surrface-Mount _ MAX741U EVKITSO__0Cto+70C _._ Surface-Mount * Dice are tested at TA = +25C only. Contact factory for availability and processing to MIL-STD-883. Chip Topography VSEL SYNC SLOPE FREQ V+ OUTA tp | Lh | _ PRN - a r- OUTB 190" Your - 4826 mm) VREF 7] a s DRV- UVLo~ By CSA csB . 884 iH cs _# ToT T i EAO EAIN DUTY i . to 180" TRANSISTOR COUNT: 614 (3,810 mm) SUBSTRATE CONNECTED TO V+. 4-132 . MAAXiIMA