Am5380/Am53C80N* SCSI Interface Controller DISTINCTIVE CHARACTERISTICS SCSI Interface @ Asynchronous interface to 1.5 megabytes per second e@ Supports Initiator and Target roles Parity generation with optional checking @ Supports Arbitration @ Direct control of ali bus signals @ High current outputs drive SCSI Bus directly CPU Interface @ Memory or I/O mapped interface @ DMA or programmed 1/0 @ Normal or Block mode DMA Optional CPU interrupts GENERAL DESCRIPTION The Am5380/Am53C80N Smail Computer Systems tnter- face (SCSI) Interface Controller is a 40-pin NMOS/CMOS device designed to accommodate the SCSI as defined by the ANS! X3T9.2 committee. The Am5380/Am53C80N operates in both the Initiator and Target roles and can, therefore, be used in host adapter, host port and formatter designs. This device supports Arbitration, including Rese- lection. Special high-current open-collector output drivers, capable of sinking 48 mA at 0.5 V, allow for direct connection to the SCSI Bus. The Am5380/Am53C80N communicates with the system microprocessor as a peripheral device. The chip is con- trolled by reading and writing several internal registers which may be addressed as standard or memory-mapped 1/O. Minimal processor intervention is required for DMA transfers because the Am5380/Am53C80N controls the necessary handshake signals. The Am5380/Am53C80N interrupts the CPU when it detects a bus condition that requires attention. Normal and Block mode DMA is provid- ed to match many popular DMA controllers. BLOCK DIAGRAM BDO06561 Publication # Rev. Amendment 08289 8 /0 Issue Date: October 1988 Am5380/Am53C80NCONNECTION DIAGRAMS Top View DIPs PLCC Dp 41 Vw 4017} D, B87 (| 2 39 [7 Dp . Dee (8 96 F710, BREE Ss? casas Des [7] 4 37 |] Dy, De, C5 36 [71 Dg 6 5 4 3 2 1 44 43 42 41 40 Pr 35 [7] Dg B83 e 39 [1 Dg oB2C]7 34 [7] dD, DB, 38 [D7 08; (]s 33 |] Ap DB, 97 DA, DB, DBo 3 DA, bBo [4 era DBP 35 1 Vpp DBP [} 10 3117] Vpp GND a fine GND [711 30 [7] Ag GND 23 HA SEL [TJ 12 29 |] iow SEL 32 f) ow BsY (7 13 28 [] RESET BSY 31 [0 RESET ACK [T] 14 27 |) EGP ACK 90 HEP AT 15 26 |] DACK ATN "7 19 19 20 21 22 29 24 25 26 27 26 BACK AST (16 25 [_] READY eo 24 FF BRE BR 28 2262 ci [_] 18 23 [Tra a MSG [_] 19 22 [] pn cpo0ge1s REG [7] 20 21[_] ts CD009900 *NC = No Connection Note: Pin 1 is marked for orientation. LOGIC SYMBOL cr PBB LS READY dBP DRQ BACK BSY |}-__> SEL rie cs RST }~~_> ion ATN -> iow ACK }~_e > Ag-A, REG [+ On*2 MSG }e C/D > 8 70 ___{- > Po-D7 RESET Vop RQ GND L$002643 4-4 Am5380/Am53C80NORDERING INFORMATION Standard Products AMD standard products are available in several packages and operating ranges. The order number (Valid Combination) is formed by a combination of: a. Device Number b. Speed Option (if applicable) c. Package Type d. Temperature Range e. Optional Processing AMS380_ P & | OPTIONAL PROCESSING Blank = Standard processing a . TEMPERATURE RANGE Cc = Commercial (0 to + 70C) . PACKAGE TYPE P = 40-Pin Plastic DIP (PD 040) D = 40-Pin Sidebrazed Ceramic DIP (SD 040) J = 44-Pin Plastic Leaded Chip Carrier (PL 044) f b. SPEED OPTION Not Applicable a. DEVICE NUMBER/DESCRIPTION Am5380/Am53C80N SCSI Interface Controller Valid Combinations Valid Combinations list configurations planned to be Valid Combinations supported in volume for this device. Consult the local AMD AM5380 PC, DC, JC sales office to confirm availability of specific valid AM53C80N PC, JC combinations, to check on newly released combinations, and to obtain additional data on AMD's standard military grade products. Am5380/Am53C80N 4-5PIN DESCRIPTION Microprocessor Interface Signals Ag-A2 Address Lines (Input) These signals are used with CS, IOR or IOW to address all internal registers. CS _ Chip Select (Input, Active LOW) CS enables a read or write of the interna! register selected by Ag - Ao. DACK DMA Acknowledge (input, Active LOW) DACK resets DRQ and selects the data register for input or output data transfers. DRQ DMA Request (Output) DRQ indicates that the data register is ready to be read or written. DRQ occurs only if DMA mode is TRUE in the Command Register. DRQ is cleared by DACK. Do-D7 Data Lines (Input/Output; Three-State, Active HIGH) Bidirectional microprocessor data bus lines. EOP End of Process (Input, Active LOW) EOP is used to terminate a DMA transfer. If asserted during a DMA cycle, the current byte will be transferred, but no additional bytes will be requested. TOR 1/0 Read (input, Active LOW) TOR is used to read an internal register selected by CS and Ag ~ Ap. It also selects the Input Data Register when used with DACK. TOW 170 Write (input, Active LOW) 1OW is used to write an internal register selected by CS and Ag Az. It also selects the Output Data Register when used with DACK. IRQ Interrupt Request (Output) IRQ alerts a microprocessor of an error condition or an event completion. READY Ready (Output) READY can be used to control the speed of Block mode DMA transfers. This signal goes active to indicate the chip is ready to send/receive data and remains FALSE after a transfer until the last byte is sent or until the DMA MODE bit is reset. RESET Reset (Input, Active LOW) RESET clears all registers. It does not force the SCSI RST signal to the active state. Power Signais Vpp +5-Volt Power Supply GND Ground SCSI Interface Signals The foliowing signals are alt bidirectional, active-LOW, open-collector signals. With 48-mA sink capability, all pins interface directly with the SCSI Bus. ACK Acknowledge (Input/Output; Open Collector, Active LOW) Driven by an Initiator, ACK indicates an acknowledgment for a REQ/ACK data-transfer handshake. In the Target role, ACK is received as a response to the REQ signal. ATN Attention (Input/Output; Open Collector, Active LOW) Driven by an Initiator, ATN indicates an Attention condition. This signal is received in the Target role. BSY Busy (Input/Output; Open Collector, Active LOW) This signal indicates that the SCS! Bus is being used and can be driven by both the Initiator and the Target device. C/7D Controi/Data (input/Output; Open Collector, Active LOW) A signal driven by the Target, C/D indicates Control or Data information is on the Data Bus. This signal is received by the Initiator. 1/0 Input/Output (Input/Output; Open Collector, Active LOW) 170 is a signal driven by a Target which controls the direction of data movement on the SCSI Bus. TRUE indicates input to the Initiator. This signal is also used to distinguish between Selection and Reselection phases. MSG Message (Input/Output; Open Collector, Active LOW) MSG is a signal driven by the Target during the Message phase. This signal is received by the Initiator. REQ Request (Input/Output; Open Collector, Active Low) Driven by a Target, REQ indicates a request for a REQ/ACK data-transfer handshake. This signal is received by the Initiator. RST SCSI Bus RESET (Input/Output; Open Collector, Active LOW) The RST signal indicates an SCSI Bus RESET condition. DBp-DB;, DBP Data Bits, Parity Bit (Input/Output; Open Collector, Active LOW) These eight data bits (DBp - DB7), plus a parity bit (DBP) form the Data Bus. DB7 is the most significant bit (MSB) and has the highest priority during the Arbitration phase. Data parity is odd. Parity is always generated and optionally checked. Parity is not valid during Arbitration. SEL Select (Input/Output; Open Collector, Active Low) SEL is used by an Initiator to select a Target, or by a Target to reselect an Initiator. Am5380/Am53C80NFUNCTIONAL DESCRIPTION General The Am5380/Am53C80N Smaii Computer Systems Interface (SCS!) device appears as a set of eight registers to the controlling CPU. By reading and writing the appropriate registers, the CPU may initiate any SCSI Bus activity or may sample and assert any signal on the SCSI Bus. This allows the user to implement all or portions of the SCSI protocol in software. These registers are read (written) by activating CS with an address on Ag~ Ap and then issuing an IOR (IJOW) pulse. This section describes the operation of the internal registers. TABLE 1. REGISTER SUMMARY Address A2| Ay/ Ao| R/W | Register Name 0/0 {0 /R Current SCS! Data 070 1/0 |W Output Data 0 }0 |1 | R/W | initiator Command 0 }1 10 | R/W | Mode O71 11 | R/W | Target Command 1/010 ]R Current SCSI Bus Status 1/0 [Oo |W Select Enable 1/0 /1 1)R Bus and Status 4470/1 |W Start DMA Send 1 11/0 7R Input Data 1/1 [0 |W Start DMA Target Receive 1]1 /1 49R Reset Parity/Interrupts 1/1 s1 tw Start DMA initiator Receive Data Registers The data registers are used to transfer SCSI commands, data, status, and message bytes between the microprocessor Data Bus and the SCSI Bus. The Am5380/Am53C80N does not interpret any information that passes through the data regis- ters. The data registers consist of the transparent Current SCSI Data Register, the Output Data Register, and the Input Data Register. Current SCSI Data Register Address 0 (Read Only) The Current SCS{ Data Register is a read-only register which allows the microprocessor to read the active SCS! Data Bus. This is accomplished by activating CS with an address on Az - Ag of 000 and issuing an IOR pulse. If parity checking is enabled, the SCSI Bus parity is checked at the beginning of the read cycie. This register is used during a programmed I/O data read or during Arbitration to check for higher priority arbitrating devices. Parity is not guaranteed valid during Arbitration. 7 6 5 4 3 2 1 0 DBB7 DBs DBs DB, DB3 DBs 58; DBo Figure 1. Current SCSI Data Register Output Data Register Address 0 (Write Only) The Output Data Register is a write-only register that is used to send data to the SCS! Bus. This is accomplished by either using a normal CPU write, or under DMA control, by using IOW and DACK. This register is also used to assert the proper ID bits or the SCSI Bus during the Arbitration and Selection phases. 687 DB. DBs 0B, B83 DBs BB; DB Figure 2. Output Data Register Input Data Register Address 6 (Read Only) The Input Data Register is a read-only register that is used to read latched data from the SCSi Bus. Data is latched either during a DMA Target receive operation when ACK goes active or during a DMA Initiator receive when REQ goes active. The DMA MODE bit (port 2, bit 1} must be set before data can be latched in the Input Data Register. This register may be read under DMA control using IOR and DACK. Parity is optionally checked when the Input Data Register is ioaded. 7 6 5 4 3 2 1 0 DB7 OB DBs 684, DBs DBs DB; DB Figure 3. Input Data Register initiator Command Register Address 1 (Read/ Write) The Initiator Command Register is a read/write register which is used to assert certain SCSi Bus signals, to monitor those signals, and to monitor the progress of bus arbitration. Many of these bits are significant only when being used as an Initiator; however, most can be used during Target role operation. 7 6 5 4 a 2 1 0 ASSERT AIP. LA ASSERT ASSERT ASSERT ASSERT ASSERT AST ACK BSY SEL AN DATA BUS Figure 4-1, Initiator Command Register Register Read 7 6 5 4 3 2 1 0 0 ASSERT TEST DIFF ASSERT ASSERT ASSERT ASSERT ASSERT RST MODE ENBL ACK BSY SEL AIN DATA BUS Figure 4-2. Initiator Command Register Register Write The foliowing describes the operation of all bits in the Initiator Command Register. Bit 7 ASSERT RST Whenever a one is written to bit 7 of the initiator Command Register, the RST signal is asserted on the SCSI Bus. The RSF signal will remain asserted until this bit is reset or until an external RESET occurs. After this bit is set (1), IRO goes active and all internal logic and control registers are reset (except for the interrupt latch and the ASSERT RST bit). Writing a zero to bit 7 of the Initiator Command Register de- asserts the RST signal. Reading this register simply reflects the status of this bit. Bit 6 AIP (Arbitration in Progress) (Read Bit) This bit is used to determine if Arbitration is in progress. For this bit to be active, the ARBITRATE bit (port 2, bit 0) must Am5380/Am53C80N 4-7have been set previously. It indicates that a Bus-Free condi- tion has been detected and that the chip has asserted BSY and the contents of the Output Data Register (port 0) onto the SCSI Bus. AIP will remain active until the ARBITRATE bit is reset. Bit 6 TEST MODE (Write Bit) This bit may be written during a test environment to disable all output drivers, effectively removing the Am5380/Am53C80N from the circuit. Resetting this bit returns the part to normal operation. Bit 5 LA (Lost Arbitration) (Read Bit) This bit, when active, indicates that the Am5380/Am53C80N detected a Bus-Free condition, arbitrated for use of the bus by asserting BSY and its ID on the Data Bus, and lost Arbitration due to SEL being asserted by another bus device. For this bit to be active, the ARBITRATE bit (port 2, bit 0) must be active. Bit 5 DIFF ENSL (Differential Enable) (Write Bit) This bit should be written with a zero for proper operation. Bit 4 ASSERT ACK This bit is used by the bus initiator to assert ACK on the SCSI Bus. In order to assert ACK, the TARGETMODE bit (port 2, bit 6) must be FALSE. Writing a zero to this bit resets ACK on the SCSI Bus. Reading this register simply reflects the status of this bit. Bit 3 ASSERT BSY Writing a one (1) into this bit position asserts BSY onto the SCSI Bus. Conversely, a zero resets the BSY signal. Asserting BSY indicates a successful selection or reselection and resetting this bit creates a Bus-Disconnect condition. Reading this register simply reflects the status of this bit. Bit 2 ASSERT SEL Writing a one (1) into this bit position asserts SEL onto the SCSI Bus. SEL is normally asserted after Arbitration has been successfully completed. SEL may be de-asserted by resetting this bit to a zero. A read of this register simply reflects the status of this bit. Bit 1 ASSERT ATN ATN may be asserted on the SCSi Bus by setting this bit to a one (1) if the TARGETMODE bit (port 2, bit 6) is FALSE. ATN is normally asserted by the initiator to request a Message Out bus phase. Note that since ASSERT SEL and ASSERT ATN are in the same register, a select with ATN may be imple- mented with one CPU write. ATN may be de-asserted by resetting this bit to zero. A read of this register simply reflects the status of this bit. Bit 0 ASSERT DATA BUS The ASSERT DATA BUS bit, when set, allows the contents of the Output Data Register to be enabled as chip outputs on the signals DBo - DB7. Parity is also generated and asserted on BBP. When connected as an Initiator, the outputs are only enabled if the TARGETMODE bit (port 2, bit 6) is FALSE, the received signal 176 is FALSE, and the phase signals (C/D, 170, and MSG) match the contents of the ASSERT C/D, ASSERT 170, and ASSERT MSG in the Target Command Register. This bit should also be set during DMA send operations. Mode Register Address 2 (Read/Write) The Mode Register is used to control the operation of the chip. This register determines whether the Am5380/Am53C80N operates as an Initiator or a Target, whether DMA transfers are being used, whether parity is checked, and whether interrupts are generated on various external conditions. This register may be read to check the value of these internal contro! bits. Figure 5 describes the operation of these control bits. 7 6 5 4 3 2 1 0 BLOCK TAR- ENABLE ENABLE ENABLE MONI- OMA ARBI- MODE GET PARITY PARITY EOP TOR MODE TAATE DMA MODE CHECK- INTER. = INTER- BUSY ING RUPT RUPT Figure 5. Mode Register Bit 7 BLOCK MODE DMA The BLOCK MODE DMA bit controls the characteristics of the DMA DRQ-DACK handshake. When this bit is reset (0) and the DMA MODE bit is active (1), the DMA handshake uses the normal interlocked handshake, and the rising edge of DACK indicates the end of each byte being transferred. In block mode operations, BLOCK MODE DMA bit set (1) and DMA MODE bit set (1), the end of JOR or IOW signifies the end of each byte transferred and DACK is allowed to remain active throughout the DMA operation. READY can then be used to request the next transfer. Bit 6 TARGETMODE The TARGETMODE bit allows the Am5380/Am53C80N to operate as either an SCSI Bus Initiator, bit reset (0), or as an SCSI Bus Target device, bit set (1). In order for the signals ATN and ACK to be asserted on the SCSI Bus, the TARGET- MODE bit must be reset (0). In order for the signals C/D, 170, MSG, and REQ to be asserted on the SCSI Bus, the TARGETMODE bit must be set (1). Bit 5 ENABLE PARITY CHECKING The ENABLE PARITY CHECKING bit determines whether parity errors will be ignored or saved in the parity error latch. If this bit is reset (0), parity will be ignored. Conversely, if this bit is set (1), parity errors will be saved. Bit 4 ENABLE PARITY INTERRUPT The ENABLE PARITY INTERRUPT bit, when set (1), will cause an interrupt (IRQ) to occur if a parity error is detected. A parity interrupt will only be generated if the ENABLE PARITY CHECKING bit (bit 5) is also enabled (1). Bit 3 ENABLE EOP INTERRUPT The ENABLE EOP INTERRUPT, when set (1), causes an interrupt to occur when the EOP (End of Process) signal is teceived from the DMA controller logic. Bit 2 MONITOR BUSY The MONITOR BUSY bit, when TRUE (1), causes an interrupt to be generated for an unexpected loss of BSY. When the interrupt is generated due to loss of BSY, the lower six bits of the Initiator Command Register are reset (0) and all signals are removed from the SCSi Bus. Bit 1 DMA MODE The DMA MODE bit is normally used to enable a DMA transfer and must be set (1) prior to writing ports 5 through 7. Ports 5 through 7 are used to start DMA transfers. The TARGET- MODE bit (port 2, bit 6) must be consistent with writes to port 6 and 7 [i.e., set (1) for a write to port 6 and reset (0) for a write to port 7]. The control bit ASSERT DATA BUS (port 4, bit 0) must be TRUE (1) for ail DMA send operations. In the DMA mode, REQ and ACK are automatically controlled. 4-8 Am5380/Am53C80NThe DMA MODE bit is not reset upon the receipt of an EOP signal. Any DMA transfer may be stopped by writing a zero into this bit location; however, care must be taken not to cause CS and DACK to be active simultaneously. Bit 0 ARBITRATE The ARBITRATE bit is set (1) to start the Arbitration process. Prior to setting this bit, the Output Data Register should contain the proper SCSI device ID value. Only one data bit should be active for SCSI Bus Arbitration. The Am5380/ Am53C80N will wait for a Bus-Free condition before entering the Arbitration phase. The results of the Arbitration phase may be determined by reading the status bits LA and AIP (port 1, bits 5 and 6, respectively). Target Command Register Address 3 (Read/ Write) When connected as a target device, the Target Command Register allows the CPU to control the SCSI Bus Information Transfer phase and/or to assert REQ simply by writing this register. The TARGETMODE bit (port 2, bit 6) must be TRUE (1) for bus assertion to occur. The SCSI Bus phases are described in Table 2. TABLE 2. SCSI INFORMATION TRANSFER PHASES ASSERT | ASSERT | ASSERT Bus Phase 176 c/o Data Out 0 0 0 Unspecified 0 0 1 Command 0 1 0 Message Out 0 1 1 Data in 1 0 0 Unspecified 1 0 1 Status 1 1 0 Message In 1 1 1 When connected as an Initiator with DMA Mode TRUE, if the phase lines (170, C/D, and MSG) do not match the phase bits in the Target Command Register, a phase-mismatch interrupt is generated when REQ goes active. In order to send data as an Initiator, the ASSERT [70, ASSERT C7D, and ASSERT MSG bits must match the corresponding bits in the Current SCSI Bus Status Register (port 4). The ASSERT REO bit (bit 3) has no meaning when operating as an Initiator. 7 6 5 4 3 2 1 o x x x X ASSERT ASSERT ASSERT ASSERT REG MSG 7 Figure 6. Target Command Register Current SCSI Bus Status Register - Address 4 (Read Only) The Current SCSI Bus Status Register is a read-only register which is used to monitor seven SCSI Bus control signals plus the Data Bus parity bit. For example, an Initiator device can use this register to determine the current bus phase and to poll REQ for pending data transfers. This register may also be used to determine why a particular interrupt occurred. Figure 7 describes the Current SCS! Bus Status Register. 7 6 5 4 3 2 1 0 RST BSY REQ MSG T/D 1/0 SEL DBP Figure 7. Current SCSI Bus Status Register Select Enable Register Address 4 (Write Only) The Select Enable Register is a write-only register which is used as a mask to monitor a signal ID during a selection attempt. The simultaneous occurrence of the correct 1D bit, BSY FALSE, and SEL TRUE will cause an interrupt. This interrupt can be disabled by resetting all bits in this register. If the ENABLE PARITY CHECKING bit (port 2, bit 5) is active (1), parity will be checked during selection. 7 6 5 4 3 2 1 0 DB; DBg DBs DB, DBs DB2 08; Be Figure 8. Select Enable Register Bus and Status Register Address 5 (Read Only) The Bus and Status Register is a read-only register which can be used to monitor the remaining SCSI control signals not found in the Current SCS! Bus Status Register (ATN and ACR), as well as six other status bits. The following describes each bit of the Bus and Status Register individually. ? 6 5 4 3 2 1 9 END DMA PARITY INTER- PHASE 8SUSY AN ACK OF RE- ERROR RUPT MATCH ERROR DMA QUEST RE- QUEST ACTIVE Figure 9. Bus and Status Register Bit 7 END OF DMA TRANSFER The END OF DMA TRANSFER bit is set if EOP, DACK, and either TOR or IOW are simultaneously active for at least 100 ns. Since the EOP signal can occur during the last byte sent to the Output Data Register (port 0), the REQ and ACK signals should be monitored to ensure that the last byte has been transferred. This bit is reset when the DMA MODE bit is reset (0) in the Mode Register (port 2). Bit 6 DMA REQUEST The DMA REQUEST bit allows the CPU to sampie the output pin DRQ. DRQ can be cleared by asserting DACK or by resetting the DMA MODE bit (bit 1) in the Mode Register (port 2). The DRQ signal does not reset when a phase-mismatch interrupt occurs. Bit 5 PARITY ERROR This bit is set if a parity error occurs during a data receive or a device selection. The PARITY ERROR bit can only be set (1) if the ENABLE PARITY CHECK bit (port 2, bit 5) is active (1). This bit may be cleared by reading the Reset Parity/tnterrupt Register (port 7). Bit 4 INTERRUPT REQUEST ACTIVE This bit is set if an enabled interrupt condition occurs. It reflects the current state of the IRQ output and can be cleared by reading the Reset Parity/interrupt Register (port 7). Bit 3 PHASE MATCH The SCSI signals, MSG, C/D, and 1/0, represent the current Information Transfer phase. The PHASE MATCH bit indicates whether the current SCSI Bus phase matches the lower 3 bits of the Target Command Register. PHASE MATCH is continu- Am5380/Am53C80N 4-9ously updated and is only significant when operating as a Bus Initiator. A phase match is required for data transfers to occur on the SCSI Bus. Bit 2 BUSY ERROR The BUSY ERROR bit is active if an unexpected loss of the BSY signal has occurred. This latch is set whenever the MONITOR BUSY bit (port 2, bit 2) is TRUE and BSY is FALSE. An unexpected loss of BSY will disable any SCSt outputs and will reset the DMA MODE bit (port 2, bit 1). Bit 1 ATN This bit reflects the condition of the SCSi Bus control signal ATN. This signal is normally monitored by the Target device. Bit 0 ACK This bit reflects the condition of the SCSI Bus control signal ACK. This signal is normally monitored by the Target device. DMA Registers Three write-only registers are used to initiate all DMA activity. They are Start DMA Send (port 5), Start DMA Target Receive (port 6), and Start DMA Initiator Receive (port 7). Simply writing these registers starts the DMA transfers. Data present- ed to the Am5380/Am53C80N on signals Do D7 during the register write is meaningless and has no effect on the operation. Prior to writing these registers, the BLOCK MODE DMA bit (bit 7). The DMA MODE bit (bit 1) and the TARGET- MODE bit (bit 6) in the Mode Register (port 2) must be appropriately set. The individual registers are briefly described as foliows: Start DMA Send Address 5 (Write Only) This register is written to initiate a DMA send, from the DMA to the SCSI Bus, for either Initiator or Target role operations. The DMA MODE bit (port 2, bit 1) must be set prior to writing this register. Start DMA Target Receive Address 6 (Write Only) This register is written to initiate a DMA receive from the SCSI Bus to the DMA, for Target operation only. The DMA MODE bit (bit 1) and the TARGETMODE bit (bit 6) in the Mode Register (port 2) must both be set (1) prior to writing this register. Start DMA Initiator Receive Address 7 (Write Only) This register is written to initiate a DMA receive from the SCSI Bus to the DMA, for Initiator operation only. The OMA MODE bit (bit 6) must be FALSE (0) in the Mode Register (port 2) prior to writing this register. Reset Parity/Interrupt - Address 7 (Read Only) Reading this register resets the PARITY ERROR bit (bit 5), the INTERRUPT REQUEST bit (bit 4), and the BUSY ERROR bit (bit 2) in the Bus and Status Register (port 5). On-Chip SCSI Hardware Support The Am5380/Am53C80N is easy to use because of its simple architecture. The chip allows direct control and monitoring of the SCSI Bus by providing a latch for each signal. However, portions of the protocol define timings which are much too quick for traditional microprocessors to control. Therefore, hardware support has been provided for DMA transfers, bus arbitration, phase-change monitoring, bus disconnection, bus reset, parity generation, parity checking, and device selection/ reselection. Arbitration is accomplished using a Bus-Free filter to continu- ously monitor BSY. If BSY remains inactive for at least 400 ns then the SCSI Bus is considered free and Arbitration may begin. Arbitration will begin if the bus is free, SEL is inactive, and the ARBITRATION bit (port 2, bit 0) is active. Once arbitration has begun (BSY asserted), an arbitration delay of 2.2 us must elapse before the Data Bus can be examined to determine if Arbitration has been won. This delay must be implemented in the controlling software driver. The Am5380/Am53C80N is a clockwise device. Delays such as bus-free delay, bus-set delay, and bus-settle delay are implemented using gate delays. These delays may differ between devices because of inherent process variations, but are well within the proposed ANSI X3T9.2 specification. interrupts The Am5380/Am53C80N provides an interrupt output (IRQ) to indicate a task completion or an abnormal bus occurrence. The use of interrupts is optional and may be disabled by resetting the appropriate bits in the Mode Register (port 2) or the Select Enable Register (port 4). When an interrupt occurs, the Bus and Status Register and the Current SCSt Bus Status Register must be read to determine which condition created the interrupt. [RQ can be reset simply by reading the Reset Parity/Interrupt Register (port 7) or by an external chip reset (RESET active for 200 ns). Assuming the Am5380/Am53C80N has been properly initiai- ized, an interrupt will be generated if the chip is selected or reselected, if an EOP signal occurs during a DMA transfer, if an SCS! Bus reset occurs, if a parity error occurs during a data transfer, if a bus phase mismatch occurs, or if an SCS! Bus disconnection occurs. Selection/Reselection The Am5380/Am53C80N can generate a select interrupt if SET is TRUE (1), its device ID is TRUE (1), and BSY is FALSE for at least a bus-settle delay (400 ns). If 176 is active, this should be considered a reselect interrupt. The correct ID bit is determined by a match in the Select Enable Register (port 4). Only a single bit match is required to generate an interrupt. This interrupt may be disabled by writing zeros into all bits of the Select Enable Register. If parity is supported, parity should also be good during the selection phase. Therefore, if the ENABLE PARITY bit (port 2, bit 5) is active, then the PARITY ERROR bit should be checked to ensure that a proper selection has occurred. The ENABLE PARITY INTERRUPT bit need not be set for this interrupt to be generated. The proposed SCSI specification also requires that no more that two device IDs be active during the selection process. To ensure this, the Current SCS! Data Register (port 0) should be read. The proper values for the Bus and Status Register (port 5) and the Current SCSI Bus Status Register (port 4) are displayed in Figures 10 and 11, respectively. 7 6 5 4 3 2 1 0 0 0 1 x 0 x 0 END DMA PARITY INTER. PHASE BUSY ATR ACK OF RE- ERROR RUPT MATCH ERROR DMA QUEST RE- QUEST ACTIVE Figure 10. Bus and Status Register 7 6 5 4 3 2 1 0 0 0 0 xX x x 1 x AST BSY REQ MSG C/D 176 SEL DBP Figure 11. Current SCSI Bus Status Register 4-10 Am5380/Am53C80NEnd of Process (EOP) Interrupt An End of Process signal (EOP) which occurs during a DMA transfer (DMAMODE TRUE) will set the END OF DMA Status bit (port 5, bit 7) and will optionally generate an interrupt if ENABLE EOP INTERRUPT bit (port 2, bit 3) is TRUE. The EOP pulse will not be recognized (END OF DMA bit set) unless EOP, BACK, and either TOR or IOW are concurrently active for at least 100 ns. DMA transfers can still occur if EOP was not asserted at the correct time. This interrupt can be disabled by resetting the ENABLE EOP INTERRUPT bit. The proper values for the Bus and Status Register (port 5) and the Current SCSI Bus Status Register (port 4) for this interrupt are shown in Figures 12 and 13, respectively. 7 6 5 4 3 2 1 9 1 0 0 1 9 9 0 x END DMA PARITY INTER- PHASE BUSY ATN ACK OF RE- ERROR RUPT MATCH ERROR DMA QUEST RE- QUEST ACTIVE Figure 12. Bus and Status Register 0 1 xX xX x x 0 x RST BSY REQ MSG C/O 176 SEL DBP Figure 13. Current SCS! Bus Status Register The END OF DMA bit is used to determine when a block transfer is complete. Receive operations are complete when there is no data ieft in the chip and no additional handshakes occurring. The only exception to this is receiving data as an Initiator and the Target opts to send additional data for the same phase. In this case, REQ goes active and the new data is present in the Input Data Register. Since a phase-mismatch interrupt will not occur, REQ and ACK need to be sampled to determine that the Target is attempting to send more data For send operations, the END OF DMA bit is set when the DMA finishes its transfer, but the SCS! transfer may still be in progress. If connected as a Target, REQ and ACK should be sampled until both are FALSE. !f connected as an Initiator, a phase change interrupt can be used to signal the completion of the previous phase. It is possible for the Target to request additional data for the same phase. In this case, a phase change will not occur and both REQ and ACK must be sampled to determine when the last byte was transferred. SCSI Bus Reset The Am5380/Am53C80N generates an interrupt when the RST signal transitions to TRUE. The device releases all bus signals within a bus-clear delay (800 ns) of this transition. This interrupt also occurs after setting the ASSERT RST bit (port 1, bit 7). This interrupt cannot be disabled. (Note: RST is not latched in bit 7 of the Current SCSI Bus Status Register and may not be active when this port is read. For this case, the Bus Reset interrupt may be determined by default). The proper values for the Bus and Status Register (port 5) and the Current SCSI Bus Status Register (port 4) are displayed in Figures 14 and 15, respectively. 7? 6 4 3 2 1 9 0 x 0 1 x 0 x x ENO DMA PARITY iNTER- PHASE BUSY ATN ACK OF RE- ERROR RUPT MATCH ERROR DMA = QUEST RE- QUEST ACTIVE Figure 14. Bus and Status Register Xx X Xx xX x x x xX RST BSY REG MSG C/O 1/0 SEL DBP Figure 15. Current SCSI Bus Status Register Parity Error An interrupt is generated for a received parity error if the ENABLE PARITY CHECK (bit 5) and the ENABLE PARITY INTERRUPT (bit 4) bits are set (1) in the Mode Register (port 2). Parity is checked during a read of the Current SCS! Data Register (port 0) and during a DMA receive operation. A parity error can be detected without generating an interrupt by disabling the ENABLE PARITY INTERRUPT bit and checking the PARITY ERROR flag (port 5, bit 5). The proper values for the Bus and Status Register (port 5) and the Current SCSI Bus Status Register (port 4) are displayed in Figures 16 and 17, respectively. 7 6 5 4 a 2 1 0 0 x 1 1 1 0 x x END DMA PARITY INTER- PHASE BUSY ATN ACK OF RE- ERROR AUPT MATCH ERROR OMA = QUEST RE- QUEST ACTIVE Figure 16. Bus and Status Register 7 6 & 4 38 2 1 0 0 1 1 x x x 0 x RST BSY REQ MSG C/D (76 SEL DBP Figure 17. Current SCSI Bus Status Register Bus Phase Mismatch The SCSI phase lines are comprised of the signals 170, C/D, and MSG. These signals are compared with the corresponding bits in the Target Command Register: ASSERT 170 (bit 0), ASSERT C/D (bit 1), and ASSERT MSG (bit 2). The compari- son occurs continually and is reflected in the PHASE MATCH bit (bit 3) of the Bus and Status Register (port 5). If the DMA MODE bit (port 2, bit 1) is active and a phase mismatch occurs when REQ transitions from FALSE to TRUE, an interrupt (IRQ) is generated. A phase mismatch prevents the recognition of REQ and removes the chip from the bus during an Initiator send operation (DBo ~ DB7 and DBP will not be driven even though the ASSERT DATA BUS bit (port 1, bit 0) is active). This interrupt is only significant when connected as an Initiator and may be disabled by resetting the DMA MODE bit (Note: it is possible for this interrupt to occur when connected as a Target if another device is driving the phase lines to a different state). Am5380/Am53C80N 4-11The proper values for the Bus and Status Register (port 5) and the Current SCSI Bus Status Register (port 4) are displayed in Figures 18 and 19, respectively. 7 6 5 4 3 2 1 0 0 0 0 1 0 0 x 0 END DMA PARITY INTER- PHASE BUSY ATN ACK OF RE- ERROR RUPT MATCH EAROR DMA QUEST RE- QUEST ACTIVE Figure 18. Bus and Status Register 0 1 x x x x 0 x RST BSY REQ MSG C/D [70 SEL DBP Figure 19. Current SCS! Bus Status Register Loss of BSY If the MONITOR BUSY bit (bit 2) in the Mode Register (port 2) is active, an interrupt will be generated if the BSY signal goes FALSE for at least a bus-settle delay (400 ns). This interrupt may be disabled by resetting the MONITOR BUSY bit. Register values are displayed in Figures 20 and 21. 7 6 5 4 3 2 1 0 0 0 1 x 1 0 9 END DMA PARITY INTER- PHASE BUSY ATN ACK OF RE- ERROR RUPT MATCH ERROR DMA QUEST RE- QUEST ACTIVE Figure 20. Bus and Status Register 0 0 0 x Xx x 0 0 RST BSY REQ MSG C/O 170 SEL DBP Figure 21. Current SCS! Bus Status Register Reset Conditions Three possible reset situations exist with the Am5380/ Am53C80N, as follows: Hardware Chip Reset When the signal RST is active for at least 200 ns, the Am5380/Am53C80N device is re-initialized and all internal logic and contro! registers are cleared. This is a chip reset only and does not create an SCSI Bus-Reset condition. SCS! Bus Reset (RST) Received When an SCSI RST signal is received, an IRQ interrupt is generated and a chip reset is performed. All internal togic and registers are cleared, except for the IRQ interrupt latch and the ASSERT RST bit (bit 7) in the initiator Command Register (port 1). (Note: The RST signal may be sampled by reading the Current SCSI Bus Status Register (port 4); however, this signal is not latched and may not be present when this port is read.) SCSI Bus Reset (RAST) Issued If the CPU sets the ASSERT RST bit (bit 7) in the Initiator Command Register (port 1), the RST signal goes active on the SCS! Bus and an internal reset is performed. Again, all interna! logic and registers are cleared except for the IRQ interrupt latch and the ASSERT RST bit (bit 7) in the Initiator Command Register (port 1). The RST signal will continue to be active until the ASSERT RST bit is reset or until a hardware reset occurs. Data Transfers Data may be transferred between SCSI Bus devices in one of four modes: 1) Programmed 1/0, 2) Normal DMA, 3) Block Mode DMA, or 4) Pseudo DMA. The following sections describe these modes in detail (Note: for all data transfer operations DACK and CS should never be active simulta- neously). Programmed 1/O Transfers Programmed |/O is the most primitive form of data transfer. The REQ and ACK handshake signals are individually moni- tored and asserted by readinig and writing the appropriate register bits. This type of transfer is normally used when transferring small blocks of data such as command biocks or message and status bytes. An Initiator send operation would begin by setting the C/D, 176, and MSG bits in the Target Command Register to the correct state so that a phase match exists. In addition to the phase match condition, it is necessary for the ASSERT DATA BUS bit (port 1, bit 0) to be TRUE and the received 1/O signal to be FALSE for the Am5380/Am53C80N to send data. For each transfer, the data is loaded into the Output Data Register (port 0). The CPU then waits for the REQ bit (port 4, bit 5) to become active. Once REG goes active, the PHASE MATCH bit (port 5, bit 3) is checked and the ASSERT ACK bit (port 1, bit 4) is set. The REQ bit is sampled until it becomes FALSE and the CPU resets the ASSERT ACK bit to complete the transfer. Normal DMA Mode DMA transfers are normaily used for large block transfers. The SCSI chip outputs a DMA request (DRQ) whenever it is ready fog a byte transfer. External DMA logic uses this DRQ signa! to Prorate DACK and an IGOR or an IOW pulse to the Am5380/ Am53C80N. DRQ goes inactive when DACK is asserted and DACK goes inactive some time after the minimum read or write pulse width. This process is repeated for every byte. For this mode, DACK should not be allowed to cycle unless a transfer is taking place. Block Mode DMA Some popular DMA controllers such as the Am9517A provide a Block mode DMA transfer. This type of transfer allows the DMA controller to transfer blocks of data without relinquishing the use of the Data Bus to the CPU after each byte is transferred: thus, faster transfer rates are achieved by elimi- nating the repetitive access and release of the CPU Bus. lf the BLOCK MODE DMA bit (port 2, bit 7) is active, the Am5380/Am53C80N will begin the transfer by asserting DRQ. The DMA controller then asserts DACK for the remainder of the block transfer. DRQ goes inactive for the duration of the transfer. The READY output is used to control the transfer rate. Non-Biock mode DMA transfers end when DACK goes FALSE, whereas Block mode transfers end when IOR or IOW becomes inactive. Since this is the case, DMA transfers may be started sooner in a Block mode transfer. 4-12 Am5380/Am53C80NTo obtain optimum performance in Block mode operation, the DMA logic may optionally use the normal OMA mode interiock- ing handshake. READY is stilt available to throttle the DMA transfer, but DRQ is 30 to 40 ns faster than READY and may be used to start the cycle sooner. The methods described under Halting a DMA Operation apply for ail OMA operations. Pseudo DMA Mode To avoid the tedium of monitoring and asserting the request/ acknowledge handshake signals for programmed 1/O trans- fers, the system may be designed to implement a pseudo DMA mode. This mode is implemented by programming the Am5380/Am53C80N to operate in the DMA mode, but using the CPU to emulate the DMA handshake. DRQ may be detected by polling the DMA REQUEST bit (bit 6) in the Bus and Status Register (port 5), by sampling the signai through an external port or by using it to generate a CPU interrupt. Once DROQ is detected, the CPU can perform a read or write data transfer. This CPU read/write is externally decoded to gener- ate the appropriate DACK and IOR or IOW signals. Often, external decoding logic is necessary to generate the Am5380/Am53C80N CS signal. This same logic may be used to generate DACK at no extra system cost and provide an increased performance in programmed I/O transfers. Halting a DMA Operation The EOP signal is not the only way to halt a DMA transfer. A bus phase mismatch or a reset of the DMA MODE bit (port 2, bit 1) can also terminate a DMA cycle for the current bus phase. Using the EOP Signal If EOP is used, it should be asserted for at least 100 ns while DACK and JOR or IOW are simultaneously active. Note, however, that if JOR or IOW is not active an interrupt will be generated, but the DMA activity will continue. The EOP signal does not reset the DMA MODE bit. Since the EOP signal can occur during the last byte sent to the Output Data Register (port 0), the REQ and ACK signals should be monitored to ensure that the last byte has transferred. Bus Phase Mismatch Interrupt A bus phase mismatch interrupt may be used to halt the transfer if operating as an Initiator. Using this method frees the host from maintaining a data length counter and frees the DMA logic from providing the EOP signal. If performing an Initiator send operation, the Am5380/Am53C80N requires DACK to cycle before ACK goes inactive. Since phase changes cannot occur if ACK is active, either DACK must be cycled after the last byte is sent or the DMA MODE bit must be reset in order to receive the phase mismatch interrupt. Resetting the DMA MODE Bit A DMA operation may be halted at any time simply by resetting the DMA MODE bit. It is recommended that the DMA MODE bit be reset after receiving an EOP or bus phase-mismatch interrupt. The DMA MODE bit must then be set before writing any of the start DMA registers for subsequent bus phases. if resetting the DMA MODE bit is used instead of EOP for Target role operation, then care must be taken to reset this bit at the proper time. {f receiving data as a Target device, the DMA MODE bit must be reset once the fast DRQ is received and before DACK is asserted to prevent an additional REQ from occurring. Resetting this bit causes DRQ to go inactive. However, the last byte received remains in the Input Data Register and may be obtained either by performing a normal CPU read or by cycling DACK and IOR. in most cases EOP is easier to use when operating as a Target device. Flowcharts Flowcharts are provided (see Figures 22 through 25) as a guideline to facilitate your firmware development. Firmware will vary depending on the application and the level of the SCSI protocol being supported. Am5380/Am53C80N 4-13WRITE (0 BIT TO DATA OUTPUT REGISTER (PORT 0) SET TARGET MODE (PORT 2, BIT 6) SET ARBIT (PORT 2, BIT 0) WAIT 2.2 ys ARBITRATION DELAY ASAT. BSY, AND ASAT. DATA BUS {PORT 1, BITS 3, 0) t RESET ARBIT {PORT 2, BIT 0) L READ PORT 0 TO SEE IF A HIGHER PRIORITY 10 1S PRESENT CLEAR THE SELECT ENABLE REGISTER {PORT 4) ! RESET BSY (PORT 1, BIT 3) Set SEL (PORT 1, BIT 2) i WAIT 1.2 4s Min (BUS CLEAR + SETTLE) [ ** RESELECTION ONLY CLEAR SEL ANO ASAT. OATA BUS FLAGS (PORT 1, BITS 2.0) INFORMATION TRANSFER PHASES Figure 22. Arbitration and (Re) Selection PF002331 4-14 Am5380/Am53C80N! SET C75 ANO REG FLacs [REQ = 1 (PORT 3, BIT 1,3) AR = 0 ss OFF ACK FLAG (PORT 5, BIT 0) SET C/O FLAG REQ = 0 ON PORT 3, BIT 1 TCK = ) ACK = 0 READ CURRENT scsi REG = DATA REGISTER ee : (PORT 0) SET C/O FLAG REQ =1 PORT 3, BIT 1, 3) ACK = ) K SET C/D FLAG CLEAR REG FLAG (PORT 3, BIT 1, 3) REG = 0 RK = 0 READ CURRENT scsi REG <1 DATA REGISTER ACK = 1 (PORT 0) EXAMINE FUNCTION CODE SET COMMAND LENGTH POINTER SET C/O FLAG CLEAR-REQ FLAG REQ = 0 (PORT 3, BIT 1, 3) ACK =1 Greck kek =o ON IER FLAG (PORT 5, BIT 0) OFF PF002340 Figure 23. Command Transfer Phase (Target) Am5380/Am53C80N 4-15ACCEPT AND RESPOND TO MESSAGE CHECK ATN (PORT 5, BIT 1) SET BSY, AND ASAT. DATA BUS (PORT 1, BITS 3, 0) SET ASAT. 70 {PORT 3, BIT 0) WRITE DATA BYTE __ TO OUTPUT DATA REG = 0 REGISTER aK = 0 (PORT 0) BEG -1 ACK = 0 DOWNCOUNT REG =1 BYTE ACK =1 COUNTER REQ =0 AK =1 YES SEND STATUS PFO02351 Figure 24. Data Transfer to Host via Programmed I/O 4-16 Am5380/Am53C80NSET-UP OMA CHIP WITH BASE ADDRESS, WORD COUNT AND MODE OF OPERATION SET BSY, ASSERT DATA BUS (PORT 1, BITS 3, 0) SET BLK MOOE DMA, EN. EOP INT., TARGETMODE, AND DMA MOOE {PORT 2, BITS 7, 3, 1) SET ASRT. VO (PORT 3, BIT 1) SET START OMA (PORT 5) NO EOP INTERRUPT? YES CHECK ENDING STATUS (PORT 5) STATUS PHASE PF002360 Figure 25. Data Transfer via OMA 4-17 Am5380/Am53C80NREAD CURRENT SCSI DATA (00) 76543210 DB7... 5B INITIATOR COMMAND REGISTER (01) 7 6 5 43 2 1 0 MODE REGISTER (02) 7 65 43 2 t 0 7 6 5 43 2 1 06 CURRENT SCSI BUS STATUS (04) 7 6 5 43 2 1 0 BUS & STATUS REGISTER (05) 76 5 43 2 1 90 INPUT DATA REGISTER (06) 7 65 43 2 1 0 LLTT Tit) RESET PARITY/INTERRUPT (07) 765 43 21 0 DFO06090 WRITE QUTPUT DATA REGISTER (00) 7 65 43 2 1 0 (TTT TT TT) DB; ... BB INITIATOR COMMAND REGISTER Test Mode Assort AST MODE REGISTER (02) 7 6 5&5 4 3 TARGET COMMAND REGISTER (03) 7 6 5 43 2 + 0 SELECT ENABLE REGISTER (04) 7 6 5 43 2 1 0 CITLTL tt By... BB START OMA SEND (05) 7 6 5 43 2 1 0 START DMA TARGET RECEIVE (06) 7 6 5 43 2 1 0 START DMA INITIATOR RECEIVE (07) NOTE: X = DON'T CARE DFO06100 Figure 26. Register Reference Chart 4-18 Am5380/Am53C80NABSOLUTE MAXIMUM RATINGS OPERATING RANGES Storage Temperature ...............: ces -65 to + 150C Commercial (C) Devices Supply Voltage on Any Pin Ambient Temperature (Ta) ........---:02eeeeee 0 to +70C with Respect to Ground .................... -0.5 to +7.0 V Supply Voltage (Voc) .........ccceeeee +4.75 to +5.25 V Power Dissipation: Operating ranges define those limits between which the AMS380 2.0... e cece nec eee cee n nee e se eee nee ne een eee 0.8 W functionality of the device is guaranteed. AMBSCBON .......-ceeececeteeeeeeeeeareenneetsenersseeeenes 0.2 W Stresses above those listed under ABSOLUTE MAXIMUM RATINGS may cause permanent device failure. Functionality at or above these limits is not implied. Exposure to absolute maximum ratings for extended periods may affect device reliability. DC CHARACTERISTICS over operating range (Note 1) Parameter Description | Test Conditions Min. Max. | Unit INPUT SIGNAL REQUIREMENTS HIGH-Level Input (ViH) 2.0 5.25 v LOW-Level Input (Vi) -0.3 0.8 Vv HIGH-Level input Current (114): Am5380 = SCSI Bus Pins Vin = 5.25 V, AmS3C80N = SCSI Bus Pins except AST Vit = 0 50 HA All Other Pins 10 LOW-Level Input Current (liv): Am5380 = SCSI Bus Pins Vin = 5.25 V, AmS53C80N = SCSI Bus Pins except RST Vi, = 0 -50 HA All Other Pins -10 OUTPUT SIGNAL REQUIREMENTS HIGH-Level Output Voltage (Voy): Am5380 = All Pins Vop = 4.75 V, 2.4 Vv AmS3C80N = All Pins except SCSI Bus lou = -3.0 mA LOW-Level Output Voltage (VoL): . Vop = 4.75 V, SCSI Bus Pins lo. = 48.0 mA . Vop = 4.75 V, All Other Pins lo. = 7.0 mA 0.5 Vv Power Supply Current (Ipp) Voc = Max, Am5380 145 mA Am53C80N -35 Notes: 1. Information for the Am53C80N is Preliminary and Subject to Change. KEY TO SWITCHING WAVEFORMS WAVEFORM INPUTS OUTPUTS MUST BE WILL BE STEADY STEADY WILL BE CHANGING FROMH TOL MAY CHANGE FROM H TOL WILL BE CHANGING FROML TOH MAY CHANGE FROML TOH DON'T CARE, CHANGING; ANY CHANGE STATE PERMITTED UNKNOWN CENTER DOES NOT LINE IS HIGH APPLY qt SESE | OFF STATE KS000010 Am5380/Am53C80N 4-19SWITCHING CHARACTERISTICS/WAVEFORMS (Cont'd.) CPU Write Cycle Name Description Min. Max. Unit T1 Address Setup to Write Enable* 410 ns T2 Address Hold from End Write Enable* 0 ns T3 Write Enable Width* 40 ns T4 Chip Select Hold from End of OW 0 ns TS Data Setup to End of Write Enable* 20 ns T6 Data Hoid Time from End of JOW 30 ns Write Enable is the occurrence of IOW and CS Ag-Ap ZZZZZ2X XVII ome fe Tr eT] ke 72 e] cs T3 T4 | iow 5 hee TS m| Do D7 LLLTTTTITEN TTT DX KITT. WF022360 CPU Read Cycle Name Description Min. Max. Unit 1 Address Setup to Read Enabie* 10 ns T2 Address Hold from End Read Enable 0 ns 73 Chip Select Hold from End of IOR 0 ns T4 Data Access Time from Read Enable* 400 ns T5 Data Hold Time from End of IOR 0 ns *Read Enable is the occurrence of IOR and CS Ag-Ag ZZZZZ2XK MITTEE TTT pe Ti wl lea T2 ot cs _ | letaad ion Ye T4m] ee T5 ml Do-D7 WLLL TTT TTT TX KITT TTT TET TTT WF022370 Am5380/Am53C80NSWITCHING CHARACTERISTICS/WAVEFORMS (Cont'd.) DMA Write (Non-Block Mode) Target Send Cycle Name Description Min. Max. Unit T ORQ FALSE from DACK TRUE 100 ns T2 DACK FALSE to DRQ TRUE 30 ns T3 Write Enable Width* 70 ns T4 DACK Hold from End of JOW 0 ns T5 Data Setup to End of Write Enabie* 30 ns 6 Data Hold Time from End of iOW 40 ns 17 Width of EOP Pulse (Note 1) 70 ns T8 ACK TRUE to REQ FALSE 125 ns T9 REQ from End of BACK (ACK FALSE) 120 ns T10 | ACK TRUE to DRQ TRUE (Target) 110 ns v1 REG from End of ACK (DACK FALSE) 120 ns T12 Data Hold from Write Enable 0 ns 713 Data Setup to REQ TRUE (Target) 60 ns Write Enable is the occurrence of OW and DACK Notes: 1. EOP, OW, and DACK must be concurrently TRUE for at least T7 for proper recognition of the EOP puise. Dace if __ ke T3 T4 iow he T5 ee Te EOP j=a 18 | s Ts | BEN _ OS REQ fe T11 ACK a ae T10 ee fe T12->| 113 m| DBy-DB7, DEP <ZTTDK. WF022380 Am5380/Am53C80N 4-21SWITCHING CHARACTERISTICS/WAVEFORMS (Cont'd.) DMA Write (Non-Block Mode) Initiator Send Cycle Name Description Min. Max. Unit Ti DRQ FALSE from BACK TRUE 100 ns T2 BACK FALSE to DRQ TRUE 30 ns T3 Write Enable Width* 70 ns 14 DACK Hold from End of OW 0 ns TS Data Setup to End of Write Enable* 30 ns T6 Data Hold Time from End of IOW 40 ns 7 Width of EOP Pulse (Note 1) 70 ns T8 REQ TRUE to ACK TRUE 110 ns T9 REQ FALSE to DRQ TRUE 110 ns T10 BACK FALSE to ACK FALSE 130 ns TW11 IOW FALSE to Valid SCSI Data 100 ns T12 Data Hoid from Write Enable 0 ns Write Enable is the occurrence of IOW and DACK Notes: 1. EOP, IOW, and DACK must be concurrently TRUE for at least T7 for proper recognition of the EOP pulse. baT1 T2 | ha T3 mhe- 74 oe! oe TS hee TE m| LITT TELLTALE. b 17 af I hose T9 a jeg-T12-mj RTI > T10 WF022390 4-22 Am5380/Am53C80NSWITCHING CHARACTERISTICS/WAVEFORMS (Cont'd.) DMA Read (Non-Block Mode) Target Receive Cycle Name Description Min. Max. Unit Ti DRQ FALSE from DACK TRUE 100 ns T2 DACK FALSE to DRQ TRUE 30 ns 73 DAGK Hold Time from End of 1OR 0 ns T4 Data Access Time from Read Enable* 100 ns T5 Data Hold Time from End of IOR ns T6 Width of EOP Pulse (Note 1) 70 ns 17 ACK TRUE to DRQ TRUE 110 ns Ta Paceey HSE to REG TRUE (ACK 420 ns T9 ACK TRUE to REQ FALSE 125 ns T10 Aiea to REQ TRUE (DACK 120 ns TH Data Setup Time to ACK 20 ns T12 Data Hold Time from ACK 50 ns *Read Enable is the occurrence of JOR and DACK Notes: 1. EOP, IOR, and DACK must be concurrently TRUE for at least T6 for proper recognition of the EOP pulse. RQ eet et DACK | a wt T3 i Nae et 14 be TS ~2| Do-D7 TTT TLL LLL TTT TR MALLLLETTT TEL ee T7 je TS >| REQ le 79-21 ja T10 m} AR TAA tof 1712-2} 0B9-DB7. <7 77 77 TTT LETTE. DBP WF022400 Am5380/Am53C80N 4-23SWITCHING CHARACTERISTICS/WAVEFORMS (Cont'd.) DMA Read (Non-Block Mode) Initiator Receive Cycle Name Description Min. Max. Unit T1 DRQ FALSE from DACK TRUE 100 ns T2 DACK FALSE to DRQ TRUE 30 ns T3 BACK Hold Time from End of IOR ) ns T4 Data Access Time from Read Enabie* 100 ns T5 Data Hold Time from End of IOR 0 ns T6 Width of EOP Pulse (Note 1) 70 ns T7 REQ TRUE to DRQ TRUE 440 ns 18 ony TSE to ACK FALSE (REQ 100 ns T9 REQ TRUE to ACK TRUE 110 ns To REQ. EASE to ACK FALSE (DACK 400 ns TH Data Setup Time to REQ 20 ns 712 Data Hold Time from REQ 50 ns *Read Enable is the occurrence of IOR and DACK Notes: 1. EOP, IOR, and DACK must be concurrently TRUE for at least T6 for proper recognition of the EOP pulse. fae Tt mf | je we T3 fa 14 el ee TS el LTLITTIML LILA LLL LLL LAL TL IX XT TT TT T6 he k- T7 m| ACK oF T1 1 fo aoopue-T 12-204 DBp-5B7. CRATE TTT ITT TT DBP T2 T8 gabe tt f7 WF022410 4-24 Am5380/Am53C80NSWITCHING CHARACTERISTICS/WAVEFORMS (Cont'd.) DMA Write (Block Mode) Target Send Cycle Name Description Min. Max. Unit 71 DRQ FALSE from DACK TRUE _ | 100 ns T2 Write Enable Width* 70 ns 3 Write Recovery Time 120 ns T4 Data Setup to End of Write Enable* 30 ns TS Data Hold Time from End of (OW 40 ns T6 Width of EOP Pulse (Note 1) 70 ns 17 ACK TRUE to REQ FALSE 120 ns T8 REQ from End of OW (ACK FALSE) 130 ns T9 REG from End of ACK (OW FALSE) 110 ns T10 ACK TRUE to READY TRUE 140 ns Ti READY TRUE to IOW FALSE 70 ns T12 JOW FALSE to READY FALSE 120 ns 713 Data Hold from ACK TRUE 0 ns T14 Data Setup to REQ TRUE 60 ns *write Enable is the occurrence of [OW and DACK Notes: 1. EOP, OW, and DACK must be concurrently TRUE for at least T6 for proper recognition of the EOP pulse. a SE DRA pT 1] DACK Ye ba 12 keg 3 J] iow OO ja 14 hee TS ml Do-D7 CALLILLILITALITIIIG< 5 QTIALTEETITEZTTL EOB T6 NL jot 17 o} - TS _______m| REO FF REQ a 19 a j~<___ 113 je T14 ___ WF022420 Am5380/Am53C80N 4-25SWITCHING CHARACTERISTICS/WAVEFORMS (Cont'd.) DMA Read (Block Mode) Target Receive Cycle Name Description Min. Max. Unit 71 DRQ FALSE from DACK TRUE 100 ns T2 JOR Recovery Time 120 ns T3 Data Access Time from Read Enable* 100 ns T4 Data Hold Time from End of IOR 0 ns TS Width of EOP Pulse (Note 1) 70 ns T6 TOR FALSE to REQ TRUE (ACK FALSE) 130 ns 7 ACK TRUE to REQ FALSE 125 ns T8 ACK FALSE to REQ TRUE (JOR FALSE) 110 ns T9 ACK TRUE to READY TRUE 140 ns T10 READY TRUE to Valid Data 50 ns TH JOR FALSE to READY FALSE 120 ns T12 Data Setup Time to ACK 20 ns T13 Data Hold Time from ACK 50 ns *Read Enable is the occurrence of IOR and DACK Notes: 1. EOP, iOR, and DACK must be concurrently TRUE for at least T5 for proper recognition of the EOP pulse. DRQ ~~? T1 DACK = _TF"F _ >? ior Me x \ lee 73 eT ee 74 ml Do-D7_ CLL ZT TTT TTT TT TT MIIT TIL TT k T6 | 17} he 18 _ he 79 whe T10 el ee 11 el READY ___ a 112 attfeat-T 13 tm DBo-DB7, < MITLIITTT TT ITT ITITITT TTT TTT DBP 8 m oO >| qa Al WF022430 4-26 Am5380/Am53C80NSWITCHING CHARACTERISTICS/WAVEFORMS Reset Name Description Min. Max. Unit T1 Minimum Width of Reset 100 ns T1 | RESET y, [~ WF022450 Arbitration Name Description Min. Max. Unit 11 Bus Clear from SEL TRUE 600 ns T2 Arbitrate Start from BSY FALSE 1200 | 2200 ns T3 Bus Clear from BSY FALSE 4100 ns AST SEL bea 11 a ae Se BSY fee T2 ~el | OBg-DB7Z ZZ ZL TT TT WZLTTTT TZ I { we NN ARB pe- T3 my BSY (IN) 7 WF022440 Am5380/Am53C80N 4-27SWITCHING TEST CIRCUIT FROM OUTPUT UNDER TEST TCoo3860 SWITCHING TEST WAVEFORM 24 Kaen WFO009541 4-28 Am5380/Am53C80NAPPENDIX A DESIGN MODIFICATIONS IN Am53C80N Spurious RST Interrupts If Am5380 is not terminated on the SCSI Interface, the floating input of the RST signal can generate spurious interrupts. Am53C80N has 35 yA pull up on the RST signal which prevents the spurious interrupts caused by an unterminated SCSI Bus Interface. The End of DMA for Send Operations While sending the data to Am5380, if EOP is asserted on the last byte, the End of DMA Status Bit indicates that the last byte has been received from the DMA device; there is no indication that the last byte has been transferred to the SCSI Bus. The Am53C80N uses Bit 7 of the Target Command Register to indicate that the last byte has been transferred to the SCSI Bus. Faster REQ/ACK Transition Times The Am53C80N has faster REG/ACK handshake to improve overall data transfer rates. Prevents the Possibility of an Additional ACK from Occurring The Am5380, upon receipt of an EOP signal, sets the End of DMA Status Bit and prevents additional DMA requests; it does not reset the DMA Mode Bit. If receiving data as an initiator and the target continues to request data for the same bus phase after receiving an EOP pulse, the Am5380 will assert ACK without issuing DRQ. The Am53C80N prevents ACK from being asserted until the device is instructed to continue by writing the Start DMA Initiator Receive Register. Am5380/Am53C80N 4-29Am5380/Am53C80N ERRATA 1) Edge triggered RST interrupt If the SCSI Bus is not terminated, the RST interrupt is continually generated. 2) TRUE End of DMA Interrupt The Am5380/Am53C80N generates an interrupt when it receives the last byte from the DMA, not when the last byte is transferred to the SCSI Bus. 3) Return to READY after EOP Interrupt When operating in Block mode DMA, the Am5380/Am53C80N does not return the READY signal to a Ready condition. This locks up the bus and prevents the CPU from executing. 4) SCSI handshake clean up after EOP interrupt Currently the ACK remains active after the EOP Interrupt is generated and must be turned off for the Send operations. 5) SCSI handshake after EOP occurs if an EOP occurs when receiving data, a subsequent REQ will cause ACK to be asserted even though no DRQ is issued. 6) During Reselection, if the Target Command Register does not reflect the current bus phases (most likely Data Out), the Reselection interrupt may get reset. 7) A phase-mismatch interrupt is not guaranteed after a Reselection for the following reasons: -DMA MODE bit must be set in order to receive a phase-mismatch interrupt -DMA MODE bit cannot be set unless BSY is active ~BSY cannot be asserted until after the Reselection has occurred -Once BSY is asserted, the Target may assert REQ in less than 500 ns ~ The phase-mismatch interrupt is generated on the active edge of REG. If the DMA MODE bit is not set before the REG goes active, the phase-mismatch interrupt will not occur 4-30 Am5380/Am53C80N