Semiconductor Components Industries, LLC, 2001
April, 2001 – Rev. 3 1Publication Order Number:
MC10EP58/D
MC10EP58, MC100EP58
3.3V / 5VECL 2:1 Multiplexer
The MC10/100EP58 is a 2:1 multiplexer. The device is pin and
functionally equivalent to the EL58 and LVEL58 devices.
The 100 Series contains temperature compensation.
•310 ps Typical Propagation Delay
•Maximum Frequency > 3 GHz Typical
•PECL Mode Operating Range: VCC = 3.0 V to 5.5 V
with VEE = 0 V
•NECL Mode Operating Range: VCC = 0 V
with VEE = –3.0 V to –5.5 V
•Open Input Default State
•Q Output Will Default LOW with Inputs Open or at VEE
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Device Package Shipping
ORDERING INFORMATION
MC10EP58D SO–8 98 Units/Rail
MC10EP58DR2 SO–8 2500 Tape & Reel
L = Wafer Lot
Y = Year
W = Work Week
H = MC10
K = MC100
A = Assembly Location
MC100EP58D SO–8 98 Units/Rail
MC100EP58DR2 SO–8 2500 Tape & Reel
SO–8
D SUFFIX
CASE 751
MARKING DIAGRAMS*
ALYW
KEP58
ALYW
HP58
TSSOP–8
DT SUFFIX
CASE 948R
HEP58
MC10EP58DT TSSOP–8 100 Units/Rail
MC10EP58DTR2 TSSOP–8 2500 Tape & Reel
MC100EP581DT TSSOP–8 100 Units/Rail
MC100EP58DTR2 TSSOP–8 2500 Tape & Reel
ALYW
ALYW
KP58
1
8
1
8
1
8
1
8
1
8
1
8
MC10EP58, MC100EP58
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2
1
2
3
45
6
7
8
Q
VEE
VCC
Da
QDb
SEL
NC
1
0
MUX
Figure 1. 8–Lead Pinout (Top View) and Logic Diagram
PIN DESCRIPTION
PIN
Da*, Db*
ECL Select Inputs
FUNCTION
ECL Data Inputs
TRUTH TABLE
SEL
H
L
Data
a
b
SEL*
ECL Data Outputs
Negative Supply
Positive Supply
NC
VCC
VEE
No Connect
Q, Q
* Pins will default LOW when left open.
ATTRIBUTES
Characteristics Value
Internal Input Pulldown Resistor 75 k
Internal Input Pullup Resistor N/A
ESD Protection Human Body Model
Machine Model
Charged Device Model
> 4 kV
> 200 V
> 2 kV
Moisture Sensitivity, Indefinite Time Out of Drypack (Note 1.) Level 1
Flammability Rating
Oxygen Index UL–94 code V–0 A 1/8”
28 to 34
Transistor Count 41 Devices
Meets or exceeds JEDEC Spec EIA/JESD78 IC Latchup Test
1. For additional information, see Application Note AND8003/D.
MAXIMUM RATINGS (Note 2.)
Symbol Parameter Condition 1 Condition 2 Rating Units
VCC PECL Mode Power Supply VEE = 0 V 6 V
VEE NECL Mode Power Supply VCC = 0 V –6 V
VIPECL Mode Input Volta
g
e VEE = 0 V VI V
CC
6 V
VI
PECL
Mode
In ut
Voltage
NECL Mode Input Voltage
VEE
=
0
V
VCC = 0 V
VI
VCC
VI VEE
6
–6
V
V
Iout Output Current Continuous
Surge 50
100 mA
mA
IBB VBB Sink/Source ± 0.5 mA
TA Operating Temperature Range –40 to +85 °C
Tstg Storage Temperature Range –65 to +150 °C
θJA Thermal Resistance (Junction to Ambient) 0 LFPM
500 LFPM 8 SOIC
8 SOIC 190
130 °C/W
°C/W
θJC Thermal Resistance (Junction to Case) std bd 8 SOIC 41 to 44 °C/W
θJA Thermal Resistance (Junction to Ambient) 0 LFPM
500 LFPM 8 TSSOP
8 TSSOP 185
140 °C/W
°C/W
θJC Thermal Resistance (Junction to Case) std bd 8 TSSOP 41 to 44 °C/W
Tsol Wave Solder <2 to 3 sec @ 248°C 265 °C
2. Maximum Ratings are those values beyond which device damage may occur .
MC10EP58, MC100EP58
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3
10EP DC CHARACTERISTICS, PECL VCC = 3.3 V, VEE = 0 V (Note 3.)
–40°C 25°C 85°C
Symbol Characteristic Min Typ Max Min Typ Max Min Typ Max Unit
IEE Power Supply Current 20 28 37 20 30 39 22 31 40 mA
VOH Output HIGH Voltage (Note 4.) 2165 2290 2415 2230 2355 2480 2290 2415 2540 mV
VOL Output LOW Voltage (Note 4.) 1365 1490 1615 1430 1555 1680 1490 1615 1740 mV
VIH Input HIGH Voltage (Single Ended) 2090 2415 2155 2480 2215 2540 mV
VIL Input LOW Voltage (Single Ended) 1365 1690 1460 1755 1490 1815 mV
IIH Input HIGH Current 150 150 150 µA
IIL Input LOW Current 0.5 0.5 0.5 µA
NOTE: EP circuits are designed to meet the DC specifications shown in the above table after thermal equilibrium has been established. The
circuit is in a test socket or mounted on a printed circuit board and transverse airflow greater than 500 lfpm is maintained.
3. Input and output parameters vary 1:1 with VCC. VEE can vary +0.3 V to –2.2 V.
4. All loading with 50 ohms to VCC–2.0 volts.
10EP DC CHARACTERISTICS, PECL VCC = 5.0 V, VEE = 0 V (Note 5.)
–40°C 25°C 85°C
Symbol Characteristic Min Typ Max Min Typ Max Min Typ Max Unit
IEE Power Supply Current 20 28 37 20 30 39 22 31 40 mA
VOH Output HIGH Voltage (Note 6.) 3865 3990 4115 3930 4055 4180 3990 4115 4240 mV
VOL Output LOW Voltage (Note 6.) 3065 3190 3315 3130 3255 3380 3190 3315 3440 mV
VIH Input HIGH Voltage (Single Ended) 3790 4115 3855 4180 3915 4240 mV
VIL Input LOW Voltage (Single Ended) 3065 3390 3130 3455 3190 3515 mV
IIH Input HIGH Current 150 150 150 µA
IIL Input LOW Current 0.5 0.5 0.5 µA
NOTE: EP circuits are designed to meet the DC specifications shown in the above table after thermal equilibrium has been established. The
circuit is in a test socket or mounted on a printed circuit board and transverse airflow greater than 500 lfpm is maintained.
5. Input and output parameters vary 1:1 with VCC. VEE can vary +2.0 V to –0.5 V.
6. All loading with 50 ohms to VCC–2.0 volts.
10EP DC CHARACTERISTICS, NECL VCC = 0 V, VEE = –5.5 V to –3.0 V (Note 7.)
–40°C 25°C 85°C
Symbol Characteristic Min Typ Max Min Typ Max Min Typ Max Unit
IEE Power Supply Current 20 28 37 20 30 39 22 31 40 mA
VOH Output HIGH Voltage (Note 8.) –1135 –1010 –885 –1070 –945 –820 –1010 –885 –760 mV
VOL Output LOW Voltage (Note 8.) –1935 –1810 –1685 –1870 –1745 –1620 –1810 –1685 –1560 mV
VIH Input HIGH Voltage (Single Ended) –1210 –885 –1145 –820 –1085 –760 mV
VIL Input LOW Voltage (Single Ended) –1935 –1610 –1870 –1545 –1810 –1485 mV
IIH Input HIGH Current 150 150 150 µA
IIL Input LOW Current 0.5 0.5 0.5 µA
NOTE: EP circuits are designed to meet the DC specifications shown in the above table after thermal equilibrium has been established. The
circuit is in a test socket or mounted on a printed circuit board and transverse airflow greater than 500 lfpm is maintained.
7. Input and output parameters vary 1:1 with VCC.
8. All loading with 50 ohms to VCC–2.0 volts.
MC10EP58, MC100EP58
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4
100EP DC CHARACTERISTICS, PECL VCC = 3.3 V, VEE = 0 V (Note 9.)
–40°C 25°C 85°C
Symbol Characteristic Min Typ Max Min Typ Max Min Typ Max Unit
IEE Power Supply Current 20 28 37 20 31 39 25 33 42 mA
VOH Output HIGH Voltage (Note 10.) 2155 2280 2405 2155 2280 2405 2155 2280 2405 mV
VOL Output LOW Voltage (Note 10.) 1355 1480 1605 1355 1480 1605 1355 1480 1605 mV
VIH Input HIGH Voltage (Single Ended) 2075 2420 2075 2420 2075 2420 mV
VIL Input LOW Voltage (Single Ended) 1355 1675 1355 1675 1355 1675 mV
IIH Input HIGH Current 150 150 150 µA
IIL Input LOW Current 0.5 0.5 0.5 µA
NOTE: EP circuits are designed to meet the DC specifications shown in the above table after thermal equilibrium has been established. The
circuit is in a test socket or mounted on a printed circuit board and transverse airflow greater than 500 lfpm is maintained.
9. Input and output parameters vary 1:1 with VCC. VEE can vary +0.3 V to –2.2 V.
10.All loading with 50 ohms to VCC–2.0 volts.
100EP DC CHARACTERISTICS, PECL VCC = 5.0 V, VEE = 0 V (Note 11.)
–40°C 25°C 85°C
Symbol Characteristic Min Typ Max Min Typ Max Min Typ Max Unit
IEE Power Supply Current 20 28 37 20 31 39 25 33 42 mA
VOH Output HIGH Voltage (Note 12.) 3855 3980 4105 3855 3980 4105 3855 3980 4105 mV
VOL Output LOW Voltage (Note 12.) 3055 3180 3305 3055 3180 3305 3055 3180 3305 mV
VIH Input HIGH Voltage (Single Ended) 3775 4120 3775 4120 3775 4120 mV
VIL Input LOW Voltage (Single Ended) 3055 3375 3055 3375 3055 3375 mV
IIH Input HIGH Current 150 150 150 µA
IIL Input LOW Current 0.5 0.5 0.5 µA
NOTE: EP circuits are designed to meet the DC specifications shown in the above table after thermal equilibrium has been established. The
circuit is in a test socket or mounted on a printed circuit board and transverse airflow greater than 500 lfpm is maintained.
11.Input and output parameters vary 1:1 with VCC. VEE can vary +2.0 V to –0.5 V.
12.All loading with 50 ohms to VCC–2.0 volts.
100EP DC CHARACTERISTICS, NECL VCC = 0 V, VEE = –5.5 V to –3.0 V (Note 13.)
–40°C 25°C 85°C
Symbol Characteristic Min Typ Max Min Typ Max Min Typ Max Unit
IEE Power Supply Current 20 28 37 20 31 39 25 33 42 mA
VOH Output HIGH Voltage (Note 14.) –1145 –1020 –895 –1145 –1020 –895 –1145 –1020 –895 mV
VOL Output LOW Voltage (Note 14.) –1945 –1820 –1695 –1945 –1820 –1695 –1945 –1820 –1695 mV
VIH Input HIGH Voltage (Single Ended) –1225 –880 –1225 –880 –1225 –880 mV
VIL Input LOW Voltage (Single Ended) –1945 –1625 –1945 –1625 –1945 –1625 mV
IIH Input HIGH Current 150 150 150 µA
IIL Input LOW Current 0.5 0.5 0.5 µA
NOTE: EP circuits are designed to meet the DC specifications shown in the above table after thermal equilibrium has been established. The
circuit is in a test socket or mounted on a printed circuit board and transverse airflow greater than 500 lfpm is maintained.
13.Input and output parameters vary 1:1 with VCC.
14.All loading with 50 ohms to VCC–2.0 volts.
MC10EP58, MC100EP58
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5
AC CHARACTERISTICS VCC = 0 V ; VEE = –3.0 V to –5.5 V or VCC = 3.0 V to 5.5 V; VEE = 0 V (Note 15.)
–40°C 25°C 85°C
Symbol Characteristic Min Typ Max Min Typ Max Min Typ Max Unit
fmax Maximum Frequency
(See Figure 2. Fmax/JITTER) > 3 > 3 > 3 GHz
tPLH,
tPHL Propagation Delay to
Output Differential D to Q,Q
SEL to Q,Q 200 280 380 210 310 410 220 340 420 ps
tJITTER Cycle–to–Cycle Jitter
(See Figure 2. Fmax/JITTER) 0.2 < 2 0.2 < 2 0.2 < 2 ps
VPP Input Voltage Swing (Differential) 150 800 1200 150 800 1200 150 800 1200 mV
tr
tfOutput Rise/Fall Times Q, Q
(20% – 80%) 70 120 170 80 130 180 100 150 200 ps
15.Measured using a 750 mV source, 50% duty cycle clock source. All loading with 50 ohms to VCC–2.0 V.
0
100
200
300
400
500
600
700
800
900
1000
0 1000 2000 3000 4000 5000 6000
Figure 2. Fmax/Jitter
FREQUENCY (MHz)
1
2
3
4
5
6
7
8
(JITTER)
9
10
ÉÉÉÉÉÉÉÉÉÉ
ÉÉÉÉÉÉÉÉÉÉ
ÉÉÉÉÉÉÉÉÉÉ
VOUTpp (mV)
JITTEROUT ps (RMS)
ÉÉ
ÉÉ
ÉÉ
MC10EP58, MC100EP58
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6
VTT =VCC – 2.0 V
Figure 3. Typical Termination for Output Driver and Device Evaluation
(See Application Note AND8020 – Termination of ECL Logic Devices.)
Driver
Device Receiver
Device
Q
Qb
D
Db
50
50
VTT
Resource Reference of Application Notes
AN1404 –ECLinPS Circuit Performance at Non–Standard VIH Levels
AN1405 –ECL Clock Distribution Techniques
AN1406 –Designing with PECL (ECL at +5.0 V)
AN1504 –Metastability and the ECLinPS Family
AN1568 –Interfacing Between LVDS and ECL
AN1650 –Using Wire–OR Ties in ECLinPS Designs
AN1672 –The ECL Translator Guide
AND8001 –Odd Number Counters Design
AND8002 –Marking and Date Codes
AND8009 –ECLinPS Plus Spice I/O Model Kit
AND8020 –Termination of ECL Logic Devices
For an updated list of Application Notes, please see our website at http://onsemi.com.
MC10EP58, MC100EP58
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7
PACKAGE DIMENSIONS
SO–8
D SUFFIX
PLASTIC SOIC PACKAGE
CASE 751–07
ISSUE W
SEATING
PLANE
1
4
58
N
J
X 45
K
NOTES:
1. DIMENSIONING AND TOLERANCING PER ANSI
Y14.5M, 1982.
2. CONTROLLING DIMENSION: MILLIMETER.
3. DIMENSION A AND B DO NOT INCLUDE MOLD
PROTRUSION.
4. MAXIMUM MOLD PROTRUSION 0.15 (0.006) PER
SIDE.
5. DIMENSION D DOES NOT INCLUDE DAMBAR
PROTRUSION. ALLOWABLE DAMBAR
PROTRUSION SHALL BE 0.127 (0.005) TOTAL IN
EXCESS OF THE D DIMENSION AT MAXIMUM
MATERIAL CONDITION.
A
BS
D
H
C
0.10 (0.004)
DIM
A
MIN MAX MIN MAX
INCHES
4.80 5.00 0.189 0.197
MILLIMETERS
B3.80 4.00 0.150 0.157
C1.35 1.75 0.053 0.069
D0.33 0.51 0.013 0.020
G1.27 BSC 0.050 BSC
H0.10 0.25 0.004 0.010
J0.19 0.25 0.007 0.010
K0.40 1.27 0.016 0.050
M0 8 0 8
N0.25 0.50 0.010 0.020
S5.80 6.20 0.228 0.244
–X–
–Y–
G
M
Y
M
0.25 (0.010)
–Z–
Y
M
0.25 (0.010) Z SXS
M
DIM MIN MAX MIN MAX
INCHESMILLIMETERS
A2.90 3.10 0.114 0.122
B2.90 3.10 0.114 0.122
C0.80 1.10 0.031 0.043
D0.05 0.15 0.002 0.006
F0.40 0.70 0.016 0.028
G0.65 BSC 0.026 BSC
L4.90 BSC 0.193 BSC
M0 6 0 6
SEATING
PLANE
PIN 1 14
85
DETAIL E
B
C
D
A
G
DETAIL E
F
M
L
2X L/2
–U–
S
U0.15 (0.006) T
S
U0.15 (0.006) T
S
U
M
0.10 (0.004) V S
T
0.10 (0.004)
–T–
–V–
–W–
0.25 (0.010)
8x REFK
IDENT
K0.25 0.40 0.010 0.016
TSSOP–8
DT SUFFIX
PLASTIC TSSOP PACKAGE
CASE 948R–02
ISSUE A
NOTES:
1. DIMENSIONING AND TOLERANCING PER ANSI
Y14.5M, 1982.
2. CONTROLLING DIMENSION: MILLIMETER.
3. DIMENSION A DOES NOT INCLUDE MOLD FLASH.
PROTRUSIONS OR GATE BURRS. MOLD FLASH
OR GATE BURRS SHALL NOT EXCEED 0.15
(0.006) PER SIDE.
4. DIMENSION B DOES NOT INCLUDE INTERLEAD
FLASH OR PROTRUSION. INTERLEAD FLASH OR
PROTRUSION SHALL NOT EXCEED 0.25 (0.010)
PER SIDE.
5. TERMINAL NUMBERS ARE SHOWN FOR
REFERENCE ONLY.
6. DIMENSION A AND B ARE TO BE DETERMINED
AT DATUM PLANE -W-.
MC10EP58, MC100EP58
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8
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without further notice to any products herein. SCILLC makes no warranty , representation or guarantee regarding the suitability of its products for any particular
purpose, nor does SCILLC assume any liability arising out of the application or use of any product or circuit, and specifically disclaims any and all liability,
including without limitation special, consequential or incidental damages. “Typical” parameters which may be provided in SCILLC data sheets and/or
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MC10EP58/D
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