DS90LV031AQML www.ti.com SNLS204A - NOVEMBER 2011 - REVISED APRIL 2013 DS90LV031AQML 3V LVDS Quad CMOS Differential Line Driver Check for Samples: DS90LV031AQML FEATURES DESCRIPTION * * * * * * * * The DS90LV031A is a quad CMOS differential line driver designed for applications requiring ultra low power dissipation and high data rates. The device is designed to support data rates in excess of 400 Mbps (200 MHz) utilizing Low Voltage Differential Signaling (LVDS) technology. 1 23 * * * * High impedance LVDS outputs with power-off Low differential skew Low propagation delay 3.3V power supply design 350 mV differential signaling Low power dissipation Interoperable with existing 5V LVDS devices Compatible with IEEE 1596.3 SCI LVDS standard Compatible with proposed TIA/EIA-644 LVDS standard Pin compatible with DS26C31 Typical Rise/Fall times of 800pS. Typical Tri-State Enable/Disable delays of less than 5nS. The DS90LV031A accepts low voltage TTL/CMOS input levels and translates them to low voltage (350 mV) differential output signals. In addition the driver supports a TRI-STATE(R) function that may be used to disable the output stage, disabling the load current, and thus dropping the device to an ultra low idle power state of 13 mW typical. The EN and EN* inputs allow active Low or active High control of the TRI-STATE outputs. The enables are common to all four drivers. The DS90LV031A and companion line receiver (DS90LV032A) provide a new alternative to high power psuedo-ECL devices for high speed point-to-point interface applications. Connection Diagram Figure 1. Dual-In-Line See Package Number NAC0016A or NAD0016A 1 2 3 Please be aware that an important notice concerning availability, standard warranty, and use in critical applications of Texas Instruments semiconductor products and disclaimers thereto appears at the end of this data sheet. TRI-STATE is a registered trademark of Texas Instruments. All other trademarks are the property of their respective owners. PRODUCTION DATA information is current as of publication date. Products conform to specifications per the terms of the Texas Instruments standard warranty. Production processing does not necessarily include testing of all parameters. Copyright (c) 2011-2013, Texas Instruments Incorporated DS90LV031AQML SNLS204A - NOVEMBER 2011 - REVISED APRIL 2013 www.ti.com Functional Diagram Figure 2. Truth Table - Driver Enables Input Outputs En En* DI DO+ L H X Z Z L L H H H L All other combinations of ENABLE inputs DO- These devices have limited built-in ESD protection. The leads should be shorted together or the device placed in conductive foam during storage or handling to prevent electrostatic damage to the MOS gates. 2 Submit Documentation Feedback Copyright (c) 2011-2013, Texas Instruments Incorporated Product Folder Links: DS90LV031AQML DS90LV031AQML www.ti.com SNLS204A - NOVEMBER 2011 - REVISED APRIL 2013 Absolute Maximum Ratings (1) -0.3V to +4V Supply Voltage (VCC) Input Voltage (DI) -0.3V to (VCC + 0.3V) Enable Input Voltage (En, En*) -0.3V to (VCC + 0.3V) Output Voltage (DO+, DO-) -0.3V to +3.9V -65C TA +150C Storage Temperature Range Lead Temperature Range (Soldering 4 sec.) +260C Maximum Junction Temperature Maximum Power Dissipation @ +25C +150C (2) 16LD CLGA (NAC and NAD) 845mW Thermal Resistance JA 16LD CLGA (NAC and NAD) 148C/W JC 16LD CLGA (NAC and NAD) ESD Rating (1) (2) (3) 22C/W (3) 6KV Absolute Maximum Ratings indicate limits beyond which damage to the device may occur. Operating Ratings indicate conditions for which the device is functional, but do not ensure specific performance limits. For ensured specifications and test conditions, see the Electrical Characteristics. The ensured specifications apply only for the test conditions listed. Some performance characteristics may degrade when the device is not operated under the listed test conditions. Derate (NAD & NAC packages) at 6.8mW/C for temperatures above +25C. Human body model, 1.5 k in series with 100 pF Recommended Operating Conditions Min Typ Max Supply Voltage (VCC) +3.0V +3.3V +3.6V Operating Free Air Temperature (TA) -55C +25C +125C Table 1. Quality Conformance InspectionMil-Std-883, Method 5005 - Group A Subgroup Description Temp C 1 Static tests at +25 2 Static tests at +125 3 Static tests at -55 4 Dynamic tests at +25 5 Dynamic tests at +125 6 Dynamic tests at -55 7 Functional tests at +25 8A Functional tests at +125 8B Functional tests at -55 9 Switching tests at +25 10 Switching tests at +125 11 Switching tests at -55 12 Settling time at +25 13 Settling time at +125 14 Settling time at -55 Submit Documentation Feedback Copyright (c) 2011-2013, Texas Instruments Incorporated Product Folder Links: DS90LV031AQML 3 DS90LV031AQML SNLS204A - NOVEMBER 2011 - REVISED APRIL 2013 www.ti.com DS90LV031A Electrical Characteristics DC Parameters The following conditions apply, unless otherwise specified. DC: VCC = 3.0/3.6V Symbol Parameter Conditions Notes Min Max Units Subgroups 250 450 mV 1, 2, 3 50 mV 1, 2, 3 1.625 V 1, 2, 3 VOD1 Differential Ouput Voltage RL = 100 Figure 3 VOD1 in magnitude of VOD1 for complementary output States RL = 100 Figure 3 VOS Offset Voltage RL = 100 Figure 3 VOS in Magnitude of VOS for RL = 100 Complementary Output States Figure 3 50 mV 1, 2, 3 VOH Output Voltage High RL = 100 Figure 3 1.85 V 1, 2, 3 VOL Output Voltage Low RL = 100 Figure 3 V 1, 2, 3 VIH Input Voltage High (1) 2.0 VCC V 1, 2, 3 VIL Input Voltage Low (1) Gnd 0.8 V 1, 2, 3 IIH Input Current VI = VCC or 2.5V, VCC = 3.6V 10 A 1, 2, 3 IIL Input Current VI = Gnd or 0.4V, VCC = 3.6V 10 A 1, 2, 3 VCl Input Clamp Voltage ICl = -8mA, VCC = 3.0V -1.5 V 1, 2, 3 IOS Output Short Circuit Current Enabled, DI = VCC, DO+ = 0V or DI = Gnd, DO- = 0V mA 1, 2, 3 IOff Power-off Leakage VO = 0V or 3.6V VCC = 0V or VCC = Open 20 A 1, 2, 3 IOZ Output TRI-STATE Current En = 0.8V and En* = 2.0V VO = 0V or VCC, VCC = 3.6V 10 A 1, 2, 3 ICC No Load Drivers Enabled Supply Current DI = VCC or Gnd 18 mA 1, 2, 3 ICCL Loaded Drivers Enabled Supply Current RL = 100 All Channels, DI = VCC or Gnd (all inputs) 35 mA 1, 2, 3 ICCZ Loaded or No Load Drivers Disabled Supply Current DI = VCC or Gnd, En = Gnd, En* = VCC 12 mA 1, 2, 3 (1) 1.125 0.9 -9.0 Tested during VOH/VOL tests. DS90LV031A Electrical Characteristics AC Parameters The following conditions apply, unless otherwise specified. AC: VCC = 3.0/3.3/3.6V, RL = 100, CL = 20pF. Symbol Parameter Conditions Notes Min Max Units Subgroups tPHLD Differential Propagation Delay High to Low Figure 4 and Figure 5 0.3 3.5 ns 9, 10, 11 tPLHD Differential Propagation Delay Low to High Figure 4 and Figure 5 0.3 3.5 ns 9, 10, 11 tSkD Differential Skew tPHLD - tPLHD tSk1 Channel to Channel Skew (1) tSk2 Chip to Chip Skew (2) (1) (2) 4 1.5 ns 9, 10, 11 1.75 ns 9, 10, 11 3.2 ns 9, 10, 11 Channel to Channel Skew is defined as the difference between the propagation delay of one channel and that of the others on the same chip with any event on the inputs. Chip to Chip Skew is defined as the difference between the minimum and maximum specified differential propagation delays. Submit Documentation Feedback Copyright (c) 2011-2013, Texas Instruments Incorporated Product Folder Links: DS90LV031AQML DS90LV031AQML www.ti.com SNLS204A - NOVEMBER 2011 - REVISED APRIL 2013 PARAMETER MEASUREMENT INFORMATION Figure 3. Driver VOD and VOS Test Circuit Figure 4. Driver Propagation Delay and Transition Time Test Circuit Figure 5. Driver Propagation Delay and Transition Time Waveforms Submit Documentation Feedback Copyright (c) 2011-2013, Texas Instruments Incorporated Product Folder Links: DS90LV031AQML 5 DS90LV031AQML SNLS204A - NOVEMBER 2011 - REVISED APRIL 2013 www.ti.com TYPICAL APPLICATION Figure 6. Point-to-Point Application APPLICATION INFORMATION General application guidelines and hints for LVDS drivers and receivers may be found in the LVDS Owner's Manual at http://www.ti.com/ww/en/analog/interface/lvds.shtml. LVDS drivers and receivers are intended to be primarily used in an uncomplicated point-to-point configuration as is shown in Figure 6. This configuration provides a clean signaling environment for the quick edge rates of the drivers. The receiver is connected to the driver through a balanced media which may be a standard twisted pair cable, a parallel pair cable, or simply PCB traces. Typically, the characteristic differential impedance of the media is in the range of 100. A termination resistor of 100 should be selected to match the media, and is located as close to the receiver input pins as possible. The termination resistor converts the current sourced by the driver into a voltage that is detected by the receiver. Other configurations are possible such as a multi-receiver configuration, but the effects of a mid-stream connector(s), cable stub(s), and other impedance discontinuities as well as ground shifting, noise margin limits, and total termination loading must be taken into account. The DS90LV031A differential line driver is a balanced current source design. A current mode driver, generally speaking has a high output impedance and supplies a constant current for a range of loads (a voltage mode driver on the other hand supplies a constant voltage for a range of loads). Current is switched through the load in one direction to produce a logic state and in the other direction to produce the other logic state. The output current is typically 3.5 mA, a minimum of 2.5 mA, and a maximum of 4.5 mA. The current mode requires (as discussed above) that a resistive termination be employed to terminate the signal and to complete the loop as shown in Figure 6. AC or unterminated configurations are not allowed. The 3.5 mA loop current will develop a differential voltage of 350 mV across the 100 termination resistor which the receiver detects with a 250 mV minimum differential noise margin neglecting resistive line losses (driven signal minus receiver threshold (350 mV - 100 mV = 250 mV)). The signal is centered around +1.2V (Driver Offset, VOS) with respect to ground as shown in Figure 7. Note that the steady-state voltage (VSS) peak-to-peak swing is twice the differential voltage (VOD) and is typically 700 mV. The current mode driver provides substantial benefits over voltage mode drivers, such as an RS-422 driver. Its quiescent current remains relatively flat versus switching frequency. Whereas the RS-422 voltage mode driver increases exponentially in most case between 20 MHz-50 MHz. This is due to the overlap current that flows between the rails of the device when the internal gates switch. Whereas the current mode driver switches a fixed current between its output without any substantial overlap current. This is similar to some ECL and PECL devices, but without the heavy static ICC requirements of the ECL/PECL designs. LVDS requires > 80% less current than similar PECL devices. AC specifications for the driver are a tenfold improvement over other existing RS-422 drivers. The TRI-STATE function allows the driver outputs to be disabled, thus obtaining an even lower power state when the transmission of data is not required. The footprint of the DS90LV031A is the same as the industry standard 26LS31 Quad Differential (RS-422) Driver and is a step down replacement for the 5V DS90C031 Quad Driver. Power Decoupling Recommendations Bypass capacitors must be used on power pins. High frequency ceramic (surface mount is recommended) 0.1F in parallel with 0.01F, in parallel with 0.001F at the power supply pin as well as scattered capacitors over the printed circuit board. Multiple vias should be used to connect the decoupling capacitors to the power planes. A 10F (35V) or greater solid tantalum capacitor should be connected at the power entry point on the printed circuit board. 6 Submit Documentation Feedback Copyright (c) 2011-2013, Texas Instruments Incorporated Product Folder Links: DS90LV031AQML DS90LV031AQML www.ti.com SNLS204A - NOVEMBER 2011 - REVISED APRIL 2013 PC Board considerations Use at least 4 PCB layers (top to bottom); LVDS signals, ground, power, TTL signals. Isolate TTL signals from LVDS signals, otherwise the TTL may couple onto the LVDS lines. It is best to put TTL and LVDS signals on different layers which are isolated by a power/ground plane(s). Keep drivers and receivers as close to the (LVDS port side) connectors as possible. Differential Traces Use controlled impedance traces which match the differential impedance of your transmission medium (ie. cable) and termination resistor. Run the differential pair trace lines as close together as possible as soon as they leave the IC (stubs should be < 10mm long). This will help eliminate reflections and ensure noise is coupled as common-mode. Lab experiments show that differential signals which are 1mm apart radiate far less noise than traces 3mm apart since magnetic field cancellation is greater with the closer traces. Plus, noise induced on the differential lines is much more likely to appear as common-mode which is rejected by the receiver. Match electrical lengths between traces to reduce skew. Skew between the signals of a pair means a phase difference between signals which destroys the magnetic field cancellation benefits of differential signals and EMI will result. (Note the velocity of propagation, v = c/Er where c (the speed of light) = 0.2997mm/ps or 0.0118 in/ps). Do not rely solely on the auto-route function for differential traces. Carefully review dimensions to match differential impedance and provide isolation for the differential lines. Minimize the number of vias and other discontinuities on the line. Avoid 90 turns (these cause impedance discontinuities). Use arcs or 45 bevels. Within a pair of traces, the distance between the two traces should be minimized to maintain common-mode rejection of the receivers. On the printed circuit board, this distance should remain constant to avoid discontinuities in differential impedance. Minor violations at connection points are allowable. Termination Use a resistor which best matches the differential impedance of your transmission line. The resistor should be between 90 and 130. Remember that the current mode outputs need the termination resistor to generate the differential voltage. LVDS will not work without resistor termination. Typically, connect a single resistor across the pair at the receiver end. Surface mount 1% to 2% resistors are best. PCB stubs, component lead, and the distance from the termination to the receiver inputs should be minimized. The distance between the termination resistor and the receiver should be < 10mm (12mm MAX). Probing LVDS Transmission Lines Always use high impedance (> 100k), low capacitance (< 2pF) scope probes with a wide bandwidth (1GHz) scope. Improper probing will give deceiving results. Cables and Connectors, General Comments When choosing cable and connectors for LVDS it is important to remember: Use controlled impedance media. The cables and connectors you use should have a matched differential impedance of about 100. They should not introduce major impedance discontinuities. Balanced cables (e.g. twisted pair) are usually better than unbalanced cables (ribbon cable, simple coax.) for noise reduction and signal quality. Balanced cables tend to generate less EMI due to field canceling effects and also tend to pick up electromagnetic radiation a common-mode (not differential mode) noise which is rejected by the receiver. For cable distances < 0.5M, most cables can be made to work effectively. For distances 0.5M d 10M, CAT 3 (category 3) twisted pair cable works well, is readily available and relatively inexpensive. Fail-safe Feature The LVDS receiver is a high gain, high speed device that amplifies a small differential signal (20mV) to CMOS logic levels. Due to the high gain and tight threshold of the receiver, care should be taken to prevent noise from appearing as a valid signal. Submit Documentation Feedback Copyright (c) 2011-2013, Texas Instruments Incorporated Product Folder Links: DS90LV031AQML 7 DS90LV031AQML SNLS204A - NOVEMBER 2011 - REVISED APRIL 2013 www.ti.com The receiver's internal fail-safe circuitry is designed to source/sink a small amount of current, providing fail-safe protection (a stable known state of HIGH output voltage) for floating, terminated or shorted receiver inputs. 1. Open Input Pins. The DS90LV032A is a quad receiver device, and if an application requires only 1, 2 or 3 receivers, the unused channel(s) inputs should be left OPEN. Do not tie unused receiver inputs to ground or any other voltages. The input is biased by internal high value pull up and pull down resistors to set the output to a HIGH state. This internal circuitry will ensure a HIGH, stable output state for open inputs. 2. Terminated Input. If the driver is disconnected (cable unplugged), or if the driver is in a TRI-STATE or power-off condition, the receiver output will again be in a HIGH state, even with the end of cable 100 termination resistor across the input pins. The unplugged cable can become a floating antenna which can pick up noise. If the cable picks up more than 10mV of differential noise, the receiver may see the noise as a valid signal and switch. To insure that any noise is seen as common-mode and not differential, a balanced interconnect should be used. Twisted pair cable will offer better balance than flat ribbon cable. 3. Shorted Inputs. If a fault condition occurs that shorts the receiver inputs together, thus resulting in a 0V differential input voltage, the receiver output will remain in a HIGH state. Shorted input fail-safe is not supported across the common-mode range of the device (GND to 2.4V). It is only supported with inputs shorted and no external common-mode voltage applied. External lower value pull up and pull down resistors (for a stronger bias) may be used to boost fail-safe in the presence of higher noise levels. The pull up and pull down resistors should be in the 5k to 15k range to minimize loading and waveform distortion to the driver. The common-mode bias point should be set to approximately 1.2V (less than 1.75V) to be compatible with the internal circuitry. Figure 7. Driver Output Levels Pin Descriptions Pin No. 8 Name Description 1, 7, 9, 15 DI 2, 6, 10, 14 DO+ Driver input pin, TTL/CMOS compatible Non-inverting driver output pin, LVDS levels 3, 5, 11, 13 DO- Inverting driver output pin, LVDS levels 4 En Active high enable pin, OR-ed with En* 12 En* Active low enable pin, OR-ed with En 16 VCC Power supply pin, +3.3V 0.3V 8 Gnd Ground pin Submit Documentation Feedback Copyright (c) 2011-2013, Texas Instruments Incorporated Product Folder Links: DS90LV031AQML DS90LV031AQML www.ti.com SNLS204A - NOVEMBER 2011 - REVISED APRIL 2013 Typical Performance Curves Figure 8. Typical DS90LV031, TA = 25C DO (single ended) vs RL Figure 9. Typical DS90LV031, DO vs RL, VCC = 3.3V, TA = 25C Submit Documentation Feedback Copyright (c) 2011-2013, Texas Instruments Incorporated Product Folder Links: DS90LV031AQML 9 DS90LV031AQML SNLS204A - NOVEMBER 2011 - REVISED APRIL 2013 www.ti.com REVISION HISTORY Changes from Original (April 2013) to Revision A * 10 Page Changed layout of National Data Sheet to TI format ............................................................................................................ 9 Submit Documentation Feedback Copyright (c) 2011-2013, Texas Instruments Incorporated Product Folder Links: DS90LV031AQML PACKAGE OPTION ADDENDUM www.ti.com 17-Apr-2013 PACKAGING INFORMATION Orderable Device Status (1) Package Type Package Pins Package Drawing Qty Eco Plan Lead/Ball Finish (2) MSL Peak Temp Op Temp (C) (3) Top-Side Markings (4) 5962-9865101QFA ACTIVE CFP NAD 16 19 TBD Call TI Call TI -55 to 125 DS90LV031AW -QML Q 5962-98651 01QFA ACO 01QFA >T DS90LV031AW-MLS ACTIVE CFP NAD 16 19 TBD Call TI Call TI -40 to 85 DS90LV031AW-QML ACTIVE CFP NAD 16 19 TBD Call TI Call TI -55 to 125 DS90LV031AW -QML Q 5962-98651 01QFA ACO 01QFA >T DS90LV031AWGMLS ACTIVE CFP NAC 16 42 TBD Call TI Call TI -55 to 125 DS90LV031AWG MLS ACO MLS >T (1) The marketing status values are defined as follows: ACTIVE: Product device recommended for new designs. LIFEBUY: TI has announced that the device will be discontinued, and a lifetime-buy period is in effect. NRND: Not recommended for new designs. Device is in production to support existing customers, but TI does not recommend using this part in a new design. PREVIEW: Device has been announced but is not in production. Samples may or may not be available. OBSOLETE: TI has discontinued the production of the device. (2) Eco Plan - The planned eco-friendly classification: Pb-Free (RoHS), Pb-Free (RoHS Exempt), or Green (RoHS & no Sb/Br) - please check http://www.ti.com/productcontent for the latest availability information and additional product content details. TBD: The Pb-Free/Green conversion plan has not been defined. Pb-Free (RoHS): TI's terms "Lead-Free" or "Pb-Free" mean semiconductor products that are compatible with the current RoHS requirements for all 6 substances, including the requirement that lead not exceed 0.1% by weight in homogeneous materials. Where designed to be soldered at high temperatures, TI Pb-Free products are suitable for use in specified lead-free processes. Pb-Free (RoHS Exempt): This component has a RoHS exemption for either 1) lead-based flip-chip solder bumps used between the die and package, or 2) lead-based die adhesive used between the die and leadframe. The component is otherwise considered Pb-Free (RoHS compatible) as defined above. Green (RoHS & no Sb/Br): TI defines "Green" to mean Pb-Free (RoHS compatible), and free of Bromine (Br) and Antimony (Sb) based flame retardants (Br or Sb do not exceed 0.1% by weight in homogeneous material) (3) MSL, Peak Temp. -- The Moisture Sensitivity Level rating according to the JEDEC industry standard classifications, and peak solder temperature. (4) Multiple Top-Side Markings will be inside parentheses. Only one Top-Side Marking contained in parentheses and separated by a "~" will appear on a device. If a line is indented then it is a continuation of the previous line and the two combined represent the entire Top-Side Marking for that device. Addendum-Page 1 Samples PACKAGE OPTION ADDENDUM www.ti.com 17-Apr-2013 Important Information and Disclaimer:The information provided on this page represents TI's knowledge and belief as of the date that it is provided. TI bases its knowledge and belief on information provided by third parties, and makes no representation or warranty as to the accuracy of such information. Efforts are underway to better integrate information from third parties. TI has taken and continues to take reasonable steps to provide representative and accurate information but may not have conducted destructive testing or chemical analysis on incoming materials and chemicals. TI and TI suppliers consider certain information to be proprietary, and thus CAS numbers and other limited information may not be available for release. In no event shall TI's liability arising out of such information exceed the total purchase price of the TI part(s) at issue in this document sold by TI to Customer on an annual basis. OTHER QUALIFIED VERSIONS OF DS90LV031AQML, DS90LV031AQML-SP : * Military: DS90LV031AQML * Space: DS90LV031AQML-SP NOTE: Qualified Version Definitions: * Military - QML certified for Military and Defense Applications * Space - Radiation tolerant, ceramic packaging and qualified for use in Space-based application Addendum-Page 2 MECHANICAL DATA NAD0016A W16A (Rev T) www.ti.com MECHANICAL DATA NAC0016A WG16A (RevG) www.ti.com IMPORTANT NOTICE Texas Instruments Incorporated and its subsidiaries (TI) reserve the right to make corrections, enhancements, improvements and other changes to its semiconductor products and services per JESD46, latest issue, and to discontinue any product or service per JESD48, latest issue. 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