1
Document # SRAM131 REV OR
Revised March 2006
P3C1011
HIGH SPEED 128K x 16 (2 MEG)
STATIC CMOS RAM
High Speed (Equal Access and Cycle Times)
— 10/12/15/20 ns (Commercial)
— 12/15/20 ns (Industrial)
— 20/25/35 (Military)
Low Power
— 360 mW (max.)
Single 3.3V ± 0.3V Power Supply
FUNCTIONAL BLOCK DIAGRAM PIN CONFIGURATION
1519B
FEATURES
DESCRIPTION
The P3C101 1 is a 131,072 words by 16 bit s high-speed
CMOS static RAM. The CMOS memory requires no
clocks or refreshing, and has equal access and cycle
times. Inputs are fully TTL-compatible. The RAM oper-
ates from a single 3.3V ± 0.3V tolerance power
supply.
Access times as fast as 10 nanoseconds permit greatly
enhanced system operating speeds. CMOS is utilized
to reduce power consumption to a low level. The P3C101 1
is a member of a family of P ACE RAM™ product s offer-
ing fast access times.
The P3C1011 device provides asynchronous operation
with matching access and cycle times. Memory loca-
tions are specified on address pins A0 to A17. Reading is
accomplished by device selection (CE and output en-
abling (OE) while write enable (WE) remains HIGH. By
presenting the address under these conditions, the data
in the addressed memory location is presented on the
data input/output pins. The input/output pins stay in the
HIGH Z state when either CE or OE is HIGH or WE is
LOW.
For both reading and writing, the Byte Enable control lines
(BLE for I/O0-7 and BHE for I/O8-15) allow for the selection
of only 8 of the 16 I/O lines if desired. When a Byte
Enable control line is HIGH, the corresponding I/Os are
active.
Package options for the P3C101 1 include 44-pin SOJ and
TSOP packages.
2.0V Data Retention
Easy Memory Expansion Using CECE
CECE
CE and OEOE
OEOE
OE
Inputs
Fully TTL Compatible Inputs and Outputs
Advanced CMOS T echnology
Fast tOE
Automatic Power Down when deselected
Packages
—44-Pin SOJ, TSOP II
SOJ
TSOP II
P3C1011
Page 2 of 10Document # SRAM131 REV OR
MAXIMUM RATINGS(1)
Symbol Parameter Value Unit
VCC Power Supply Pin with –0.5 to +4.6 V
Respect to GND
Terminal Voltage with –0.5 to
VTERM Respect to GND VCC +0.5 V
TAOperating Temperature –55 to +125 ° C
Symbol Parameter Value Unit
TBIAS Temperature Under –55 to +125 ° C
Bias
TSTG Storage Temperature –65 to +150 ° C
IOUT DC Output Current 20 mA
RECOMMENDED OPERATING
TEMPERATURE AND SUPPLY VOLTAGE
ISB Standby Power Supply
Current (TTL Input Levels)
CE ≥ VIH
VCC= Max,
f = Max., Outputs Open
VIN ≥ VIH or VIN ≤ VIL
CE ≥ VCC - 0.2V
VCC= Max,
f = 0, Outputs Open
VIN ≥ VCC - 0.3V or
VIN ≤ 0.3V
Standby Power Supply
Current
(CMOS Input Levels)
ISB1
Industrial
Grade(2) Ambient
Temperature VSS VCC
0V
0V 3.3V ± 0.3V
3.3V ± 0.3V
Symbol
CIN
COUT
Parameter
Input Capacitance
I/O Capacitance
Conditions
VIN = 0V
VOUT = 0V
8
8
Unit
pF
pF
CAPACITANCES(4)
VCC = 3.3V, TA = 25°C, f = 1.0MHz
Symbol
DC ELECTRICAL CHARACTERISTICS
Over recommended operating temperature and supply voltage(2)
VIH
ILI
ILO
Parameter
Input High Voltage
Input Low Voltage
Input Leakage Current
Test Conditions
VCC = Max.
VIN = GND to VCC
VCC = Max.,
CE = VIH,
VOUT = GND to VCC
Typ.
Commercial –40°C to +85°C
0°C to +70°C
Unit
V
V
µA
µA
mA
mA
VOL Output Low Voltage
(TTL Load) IOL = +8 mA, VCC = Min. V
Output High Voltage
(TTL Load)
VOH IOH = –4 mA, VCC = Min. V
Output Leakage Current
P3C1011
___ 40
10
___
Min
2.0
–0.3(3)
-1
-1
Max
VCC +0.3
0.8
+1
+1
0.4
2.4
VIL
0V 3.3V ± 0.3V
Military -55°C to +125°C
P3C1011
Page 3 of 10Document # SRAM131 REV OR
*VCC = 3.6V. Tested with outputs open. f = Max. Switching inputs are 0V and 3V. CE = VIL, OE = VIH.
ICC
Symbol Parameter Temperature
Range
Dynamic Operating Current*
Commercial
Industrial N/A
–12
–10 –15 –20 Unit
mA
mA
POWER DISSIPATION CHARACTERISTICS VS. SPEED
90 85
95 80
90 75
85
AC ELECTRICAL CHARACTERISTICS—READ CYCLE
(VCC = 3.3V ± 0.3V, All Temperature Ranges)(2)
Sym.
tRC
tAA
tAC
tOH
tLZ
tHZ
tOE
tOLZ
tOHZ
tPU
tPD
Parameter
Read Cycle Time
Address Access Time
Chip Enable Access Time
Output Hold from Address Change
Chip Enable to Output in Low Z
Chip Disable to Output in High Z
Output Enable Low to Low Z
Output Enable High to High Z
Chip Enable to Power Up Time
Chip Disable to Power Down Time
Output Enable Low to Data Valid
MaxMin
Max
MinMaxMinMax
Min
-10 -12 -15 -20 Unit
10
3
3
0
0
10
10
5
5
5
10
12
3
3
0
0
12
12
6
6
6
12
15
3
3
0
0
15
15
7
7
7
15
20
3
3
0
0
20
20
8
8
8
20
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
tBE Byte Enable to Data Valid 5 6 7 8ns
tLZBE Byte Enable to Low Z 0000ns
tHZBE Byte Disable to High Z 6 6 7 8ns
MaxMin
-25
MaxMin
-35
–25 –35
25
3
3
0
0
10
10
10
25
10
0
10
35
3
3
0
0
12
12
12
35
12
0
12
25
25
35
35
Military N/A mA
N/A N/A 100
70
80
95
65
75
90
P3C1011
Page 4 of 10Document # SRAM131 REV OR
TIMING WAVEFORM OF READ CYCLE NO. 2 (OEOE
OEOE
OE CONTROLLED)(5,6)
Notes:
1. Stresses greater than those listed under MAXIMUM RATINGS may
cause permanent damage to the device. This is a stress rating only
and functional operation of the device at these or any other conditions
above those indicated in the operational sections of this specification
is not implied. Exposure to MAXIMUM rating conditions for extended
periods may affect reliability.
2. Extended temperature operation guaranteed with 400 linear feet per
minute of air flow.
3. Transient inputs with VIL not more negative than –2.0V and
VIH ≤ VCC + 0.5V, are permissible for pulse widths up to 20 ns.
4. This parameter is sampled and not 100% tested.
5. WE is HIGH for READ cycle.
6. CE is LOW and OE is LOW for READ cycle.
7. ADDRESS must be valid prior to, or coincident with CE transition LOW.
8. Transition is measured ± 200 mV from steady state voltage prior to
change, with loading as specified in Figure 1. This parameter is
sampled and not 100% tested.
9. Read Cycle Time is measured from the last valid address to the first
transitioning address.
TIMING WAVEFORM OF READ CYCLE NO. 1
P3C1011
Page 5 of 10Document # SRAM131 REV OR
-10
AC CHARACTERISTICS—WRITE CYCLE
(VCC = 3.3V ± 0.3V, All Temperature Ranges)(2)
Sym.
tWC
tCW
tAS
tWP
tAH
tDW
tDH
Parameter
Write Cycle Time
Chip Enable Time to End of
Write
Address Set-up Time to Write
Start
Write Pulse Width
Address Hold Time
Data Hold Time
Data Valid to End of Write
MaxMin
Max
MinMaxMinMaxMin -12 -15 -20 Unit
10
0
7
0
12
0
8
0
15
0
10
0
20
0
10
0
7
7
0
5
8
8
0
6
10
10
0
7
10
10
0
8
ns
ns
ns
ns
ns
ns
ns
ns
tAW Address Valid to End of Write
Write Enable to Output in High ZtWZ 5678 ns
Output Active from End of WritetOW 3333 ns
TIMING WAVEFORM OF WRITE CYCLE NO. 1 (CECE
CECE
CE CONTROLLED)
WE High to Low ZtLZWE 3333 ns
Byte Enable to End of WritetBW 7 8 10 10 ns
MaxMin
-25 MaxMin
-35
25
0
12
0
12
12
0
10
10
3
3
12
35
0
15
0
15
15
0
12
12
3
3
15
P3C1011
Page 6 of 10Document # SRAM131 REV OR
TIMING WAVEFORM OF WRITE CYCLE NO. 2 (BLEBLE
BLEBLE
BLE OR BHEBHE
BHEBHE
BHE CONTROLLED)
TIMING WAVEFORM OF WRITE CYCLE NO. 3 (WEWE
WEWE
WE CONTROLLED, OEOE
OEOE
OE LOW)
P3C1011
Page 7 of 10Document # SRAM131 REV OR
Input Pulse Levels VSS to 3.0V
Input Rise and Fall Times 3ns
Input Timing Reference Level 1.5V
Output Timing Reference Level 1.5V
Output Load See Figures 1 and 2
AC TEST CONDITIONS
Figure 1. Output Load Figure 2. Thevenin Equivalent
* including scope and test fixture.
Note:
Because of the ultra-high speed of the P3C1041, care must be taken
when testing this device; an inadequate setup can cause a normal
functioning part to be rejected as faulty. Long high-inductance leads
that cause supply bounce must be avoided by bringing the VCC and
ground planes directly up to the contactor fingers. A 0.01 µF high
frequency capacitor is also required between VCC and ground. To avoid
signal reflections, proper termination must be used; for example, a 50Ω
test environment should be terminated into a 50Ω load with 1.73V
(Thevenin Voltage) at the comparator input, and a 116Ω resistor must
be used in series with DOUT to match 166Ω (Thevenin Resistance).
Active
TRUTH TABLE
Standby
PowerI/O0 - I/O7
WEWE
WEWE
WE
OEOE
OEOE
OE
CECE
CECE
CE
DOUT
DOUT
High Z
DIN
X
H
H
H
L
X
L
L
L
X
H
L
L
L
Active
Active
Active
High Z
L
BHEBHE
BHEBHE
BHE
BLEBLE
BLEBLE
BLE
X
L
H
L
L
X
L
L
H
L
I/O8 - I/O15
DOUT
High Z
DOUT
DIN
High Z
Read Upper Bits Only
Power-down Mode
Read All Bits
Read Lower Bits Only
Write All Bits DIN
LXL ActiveHL High Z
Write Lower Bits Only High ZLXL ActiveLHD
IN
Write Upper Bits Only High ZHHL ActiveXX High Z
Selected, Outputs Disabled
P3C1011
Page 8 of 10Document # SRAM131 REV OR
ORDERING INFORMATION
P3C1011
Page 9 of 10Document # SRAM131 REV OR
SOJ SMALL OUTLINE IC PACKAGE
TSOP II THIN SMALL OUTLINE PACKAGE
Pkg #
# P ins
Symbol Min Max
A 0.128 0.148
A1 0.082 -
b 0.013 0.023
C 0.007 0.013
D 1.120 1.130
e
E 0.435 0.445
E1 0.395 0.405
E2
Q0.025-
J8
44 (400 mil )
0. 05 0 BSC
0. 37 0 BSC
Pkg #
# P i ns
Symbol Min Max
A 0.039 0.047
A20.033 0.045
b 0.012 0.016
D 0.396 0.404
E 0.721 0.729
e
HD0.462 0.470
T2
44
0. 0315 BS C
P3C1011
Page 10 of 10Document # SRAM131 REV OR
REVISIONS
DOCUMENT NUMBER: SRAM131
DOCUMENT TITLE:P3C1011 HIGH SPEED 128K x 16 (4 MEG) STATIC CMOS RAM
REV. ISSUE
DATE ORIG. OF
CHANGE DESCRIPTION OF CHANGE
OR Mar-06 JDB New Data Sheet
